mirror of
https://github.com/Bodmer/TFT_eSPI.git
synced 2025-07-31 03:07:33 +02:00
ESP32 board package compatibility update
This commit is contained in:
@ -11,7 +11,10 @@
|
||||
// Get the screen touch coordinates, returns true if screen has been touched
|
||||
// if the touch coordinates are off screen then x and y are not updated
|
||||
// The returned value can be treated as a bool type, false or 0 means touch not detected
|
||||
// In future the function may return an 8 "quality" (jitter) value.
|
||||
// In future the function may return an 8-bit "quality" (jitter) value.
|
||||
// The threshold value is optional, this must be higher than the bias level for z (pressure)
|
||||
// reported by Test_Touch_Controller when the screen is NOT touched. When touched the z value
|
||||
// must be higher than the threshold for a touch to be detected.
|
||||
uint8_t getTouch(uint16_t *x, uint16_t *y, uint16_t threshold = 600);
|
||||
|
||||
// Run screen calibration and test, report calibration values to the serial port
|
||||
|
@ -806,6 +806,10 @@ bool TFT_eSPI::initDMA(bool ctrl_cs)
|
||||
.sclk_io_num = TFT_SCLK,
|
||||
.quadwp_io_num = -1,
|
||||
.quadhd_io_num = -1,
|
||||
.data4_io_num = -1,
|
||||
.data5_io_num = -1,
|
||||
.data6_io_num = -1,
|
||||
.data7_io_num = -1,
|
||||
.max_transfer_sz = TFT_WIDTH * TFT_HEIGHT * 2 + 8, // TFT screen size
|
||||
.flags = 0,
|
||||
.intr_flags = 0
|
||||
|
@ -843,6 +843,10 @@ bool TFT_eSPI::initDMA(bool ctrl_cs)
|
||||
.sclk_io_num = TFT_SCLK,
|
||||
.quadwp_io_num = -1,
|
||||
.quadhd_io_num = -1,
|
||||
.data4_io_num = -1,
|
||||
.data5_io_num = -1,
|
||||
.data6_io_num = -1,
|
||||
.data7_io_num = -1,
|
||||
.max_transfer_sz = 65536, // ESP32 S3 max size is 64Kbytes
|
||||
.flags = 0,
|
||||
.intr_flags = 0
|
||||
|
@ -14,6 +14,15 @@
|
||||
#define TFT_NOP 0x00
|
||||
#define TFT_SWRST 0x01
|
||||
|
||||
#define TFT_SLPIN 0x10
|
||||
#define TFT_SLPOUT 0x11
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
||||
#define TFT_DISPOFF 0x28
|
||||
#define TFT_DISPON 0x29
|
||||
|
||||
#define TFT_CASET 0x2A
|
||||
#define TFT_PASET 0x2B
|
||||
#define TFT_RAMWR 0x2C
|
||||
@ -29,6 +38,3 @@
|
||||
#define TFT_MAD_BGR 0x08
|
||||
#define TFT_MAD_MH 0x04
|
||||
#define TFT_MAD_RGB 0x00
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
@ -42,6 +42,12 @@
|
||||
#define TFT_NOP 0x00
|
||||
#define TFT_SWRST 0x01
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
||||
#define TFT_DISPOFF 0x28
|
||||
#define TFT_DISPON 0x29
|
||||
|
||||
#define TFT_CASET 0x2A
|
||||
#define TFT_PASET 0x2B
|
||||
#define TFT_RAMWR 0x2C
|
||||
@ -57,6 +63,3 @@
|
||||
#define TFT_MAD_BGR 0x08
|
||||
#define TFT_MAD_MH 0x04
|
||||
#define TFT_MAD_RGB 0x00
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
@ -40,6 +40,12 @@
|
||||
#define TFT_NOP 0x00
|
||||
#define TFT_SWRST 0x01
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
||||
#define TFT_DISPOFF 0x28
|
||||
#define TFT_DISPON 0x29
|
||||
|
||||
#define TFT_CASET 0x2A
|
||||
#define TFT_PASET 0x2B
|
||||
#define TFT_RAMWR 0x2C
|
||||
@ -66,10 +72,6 @@
|
||||
#define TFT_MAD_COLOR_ORDER TFT_MAD_BGR
|
||||
#endif
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
||||
|
||||
// All ILI9341 specific commands some are used by init()
|
||||
#define ILI9341_NOP 0x00
|
||||
#define ILI9341_SWRESET 0x01
|
||||
|
@ -39,6 +39,12 @@
|
||||
#define TFT_NOP 0x00
|
||||
#define TFT_SWRST 0x01
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
||||
#define TFT_DISPOFF 0x28
|
||||
#define TFT_DISPON 0x29
|
||||
|
||||
#define TFT_CASET 0x2A
|
||||
#define TFT_PASET 0x2B
|
||||
#define TFT_RAMWR 0x2C
|
||||
@ -56,6 +62,3 @@
|
||||
#define TFT_MAD_SS 0x02
|
||||
#define TFT_MAD_GS 0x01
|
||||
#define TFT_MAD_RGB 0x00
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
@ -17,6 +17,12 @@
|
||||
#define TFT_NOP 0x0000
|
||||
#define TFT_SWRST 0x0100
|
||||
|
||||
#define TFT_INVOFF 0x2000
|
||||
#define TFT_INVON 0x2100
|
||||
|
||||
#define TFT_DISPOFF 0x2800
|
||||
#define TFT_DISPON 0x2900
|
||||
|
||||
#define TFT_CASET 0x2A00
|
||||
#define TFT_PASET 0x2B00
|
||||
#define TFT_RAMWR 0x2C00
|
||||
@ -44,6 +50,3 @@
|
||||
#else
|
||||
#define TFT_MAD_COLOR_ORDER TFT_MAD_RGB
|
||||
#endif
|
||||
|
||||
#define TFT_INVOFF 0x2000
|
||||
#define TFT_INVON 0x2100
|
||||
|
@ -35,6 +35,12 @@
|
||||
#define TFT_NOP 0x00
|
||||
#define TFT_SWRST 0x01
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
||||
#define TFT_DISPOFF 0x28
|
||||
#define TFT_DISPON 0x29
|
||||
|
||||
#define TFT_CASET 0x2A
|
||||
#define TFT_PASET 0x2B
|
||||
#define TFT_RAMWR 0x2C
|
||||
@ -50,6 +56,3 @@
|
||||
#define TFT_MAD_BGR 0x08
|
||||
#define TFT_MAD_MH 0x04
|
||||
#define TFT_MAD_RGB 0x00
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
@ -26,6 +26,12 @@
|
||||
#define TFT_NOP 0x00
|
||||
#define TFT_SWRST 0x01
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
||||
#define TFT_DISPOFF 0x28
|
||||
#define TFT_DISPON 0x29
|
||||
|
||||
#define TFT_CASET 0x2A
|
||||
#define TFT_PASET 0x2B
|
||||
#define TFT_RAMWR 0x2C
|
||||
@ -51,6 +57,3 @@
|
||||
#else
|
||||
#define TFT_MAD_COLOR_ORDER TFT_MAD_BGR
|
||||
#endif
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
@ -12,6 +12,12 @@
|
||||
#define TFT_NOP 0x00
|
||||
#define TFT_SWRST 0x01
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
||||
#define TFT_DISPOFF 0x28
|
||||
#define TFT_DISPON 0x29
|
||||
|
||||
#define TFT_CASET 0x2A
|
||||
#define TFT_PASET 0x2B
|
||||
#define TFT_RAMWR 0x2C
|
||||
@ -36,10 +42,6 @@
|
||||
#define TFT_MAD_COLOR_ORDER TFT_MAD_BGR
|
||||
#endif
|
||||
|
||||
#define TFT_INVOFF 0x20
|
||||
#define TFT_INVON 0x21
|
||||
|
||||
|
||||
// ST7796 specific commands
|
||||
#define ST7796_NOP 0x00
|
||||
#define ST7796_SWRESET 0x01
|
||||
|
@ -2097,7 +2097,7 @@ void TFT_eSPI::pushMaskedImage(int32_t x, int32_t y, int32_t w, int32_t h, uint1
|
||||
if (_vpOoB || w < 1 || h < 1) return;
|
||||
|
||||
// To simplify mask handling the window clipping is done by the pushImage function
|
||||
// Each mask image line assumed to be padded to and integer number of bytes & padding bits are 0
|
||||
// Each mask image line assumed to be padded to an integer number of bytes & padding bits are 0
|
||||
|
||||
begin_tft_write();
|
||||
inTransaction = true;
|
||||
@ -4966,7 +4966,10 @@ uint16_t TFT_eSPI::decodeUTF8(uint8_t *buf, uint16_t *index, uint16_t remaining)
|
||||
}
|
||||
|
||||
// 21-bit Unicode not supported so fall-back to extended ASCII
|
||||
// if ((c & 0xF8) == 0xF0) return c;
|
||||
// if (((c & 0xF8) == 0xF0) && (remaining > 3)) {
|
||||
// c = ((c & 0x07) << 18) | ((buf[(*index)++] & 0x03F) << 12);
|
||||
// c |= ((buf[(*index)++] & 0x3F) << 6);
|
||||
// return c | ((buf[(*index)++] & 0x3F));
|
||||
|
||||
return c; // fall-back to extended ASCII
|
||||
}
|
||||
|
@ -16,7 +16,7 @@
|
||||
#ifndef _TFT_eSPIH_
|
||||
#define _TFT_eSPIH_
|
||||
|
||||
#define TFT_ESPI_VERSION "2.5.41"
|
||||
#define TFT_ESPI_VERSION "2.5.42"
|
||||
|
||||
// Bit level feature flags
|
||||
// Bit 0 set: viewport capability
|
||||
|
@ -1,6 +1,6 @@
|
||||
{
|
||||
"name": "TFT_eSPI",
|
||||
"version": "2.5.41",
|
||||
"version": "2.5.42",
|
||||
"keywords": "Arduino, tft, display, ttgo, LilyPi, WT32-SC01, ePaper, display, Pico, RP2040 Nano Connect, RP2040, STM32, ESP8266, NodeMCU, ESP32, M5Stack, ILI9341, ST7735, ILI9163, S6D02A1, ILI9481, ILI9486, ILI9488, ST7789, ST7796, RM68140, SSD1351, SSD1963, ILI9225, HX8357D, GC9A01, R61581",
|
||||
"description": "A TFT and ePaper (SPI or parallel interface) graphics library with optimisation for Raspberry Pi Pico, RP2040, ESP8266, ESP32 and STM32 processors",
|
||||
"repository":
|
||||
|
@ -1,5 +1,5 @@
|
||||
name=TFT_eSPI
|
||||
version=2.5.41
|
||||
version=2.5.42
|
||||
author=Bodmer
|
||||
maintainer=Bodmer
|
||||
sentence=TFT graphics library for Arduino processors with performance optimisation for RP2040, STM32, ESP8266 and ESP32
|
||||
|
Reference in New Issue
Block a user