diff --git a/Processors/TFT_eSPI_STM32.c b/Processors/TFT_eSPI_STM32.c
index e9156df..0f804a7 100644
--- a/Processors/TFT_eSPI_STM32.c
+++ b/Processors/TFT_eSPI_STM32.c
@@ -128,26 +128,16 @@ void TFT_eSPI::pushPixels(const void* data_in, uint32_t len){
 ***************************************************************************************/
 void TFT_eSPI::busDir(uint32_t mask, uint8_t mode)
 {
-  // Use pinMode() for each pin at least one first to enable clocks etc
 
 #ifdef STM_PORTA_DATA_BUS
-  if (mode == OUTPUT) {
-    LL_GPIO_SetPinMode(GPIOA, 0xFF, LL_GPIO_MODE_OUTPUT);
-  }
-  else {
-    LL_GPIO_SetPinMode(GPIOA, 0xFF, LL_GPIO_MODE_INPUT);
-  }
+  if (mode == OUTPUT) GPIOA->CRL = 0x33333333;
+  else GPIOA->CRL = 0x88888888;
 
 #elif STM_PORTB_DATA_BUS
-  if (mode == OUTPUT) {
-    LL_GPIO_SetPinMode(GPIOB, 0xFF, LL_GPIO_MODE_OUTPUT);
-  }
-  else {
-    LL_GPIO_SetPinMode(GPIOB, 0xFF, LL_GPIO_MODE_INPUT);
-  }
+  if (mode == OUTPUT) GPIOB->CRL = 0x33333333;
+  else GPIOB->CRL = 0x88888888;
 
 #else
-  // Now we can use a minimal set of register changes
   if (mode == OUTPUT) {
     LL_GPIO_SetPinMode(D0_PIN_PORT, D0_PIN_MASK, LL_GPIO_MODE_OUTPUT);
     LL_GPIO_SetPinMode(D1_PIN_PORT, D1_PIN_MASK, LL_GPIO_MODE_OUTPUT);
diff --git a/Processors/TFT_eSPI_STM32.h b/Processors/TFT_eSPI_STM32.h
index ecb65a6..e77cc05 100644
--- a/Processors/TFT_eSPI_STM32.h
+++ b/Processors/TFT_eSPI_STM32.h
@@ -647,14 +647,14 @@
       #define tft_Write_32D(C)   tft_Write_16((uint16_t)(C)); tft_Write_16((uint16_t)(C))
 
       // Read a data bit
-      #define RD_TFT_D0 ((GPIOA->IDR) & 0x80) // Read pin TFT_D0
-      #define RD_TFT_D1 ((GPIOA->IDR) & 0x40) // Read pin TFT_D1
-      #define RD_TFT_D2 ((GPIOA->IDR) & 0x20) // Read pin TFT_D2
-      #define RD_TFT_D3 ((GPIOA->IDR) & 0x10) // Read pin TFT_D3
-      #define RD_TFT_D4 ((GPIOA->IDR) & 0x08) // Read pin TFT_D4
-      #define RD_TFT_D5 ((GPIOA->IDR) & 0x04) // Read pin TFT_D5
-      #define RD_TFT_D6 ((GPIOA->IDR) & 0x02) // Read pin TFT_D6
-      #define RD_TFT_D7 ((GPIOA->IDR) & 0x01) // Read pin TFT_D7
+      #define RD_TFT_D0 ((GPIOA->IDR) & 0x01) // Read pin TFT_D0
+      #define RD_TFT_D1 ((GPIOA->IDR) & 0x02) // Read pin TFT_D1
+      #define RD_TFT_D2 ((GPIOA->IDR) & 0x04) // Read pin TFT_D2
+      #define RD_TFT_D3 ((GPIOA->IDR) & 0x08) // Read pin TFT_D3
+      #define RD_TFT_D4 ((GPIOA->IDR) & 0x10) // Read pin TFT_D4
+      #define RD_TFT_D5 ((GPIOA->IDR) & 0x20) // Read pin TFT_D5
+      #define RD_TFT_D6 ((GPIOA->IDR) & 0x40) // Read pin TFT_D6
+      #define RD_TFT_D7 ((GPIOA->IDR) & 0x80) // Read pin TFT_D7
 
     #elif defined (STM_PORTB_DATA_BUS)