From 28be85212eaf01bb0920f2614bcc6b895ea9475f Mon Sep 17 00:00:00 2001 From: Mateusz Czarnecki Date: Wed, 23 Jun 2021 14:53:42 +0200 Subject: [PATCH] Added option to use SPI3 in STM32F4 --- Processors/TFT_eSPI_STM32.c | 9 ++++++++- Processors/TFT_eSPI_STM32.h | 7 +++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/Processors/TFT_eSPI_STM32.c b/Processors/TFT_eSPI_STM32.c index 1584d4b..9fcd013 100644 --- a/Processors/TFT_eSPI_STM32.c +++ b/Processors/TFT_eSPI_STM32.c @@ -551,6 +551,9 @@ void TFT_eSPI::pushImageDMA(int32_t x, int32_t y, int32_t w, int32_t h, uint16_t #elif (TFT_SPI_PORT == 2) extern "C" void DMA1_Stream4_IRQHandler(); void DMA1_Stream4_IRQHandler(void) + #elif (TFT_SPI_PORT == 3) + extern "C" void DMA1_Stream5_IRQHandler(); + void DMA1_Stream5_IRQHandler(void) #endif { // Call the default end of buffer handler @@ -572,8 +575,12 @@ bool TFT_eSPI::initDMA(bool ctrl_cs) __HAL_RCC_DMA2_CLK_ENABLE(); // Enable DMA2 clock dmaHal.Init.Channel = DMA_CHANNEL_3; // DMA channel 3 is for SPI1 TX #elif (TFT_SPI_PORT == 2) - __HAL_RCC_DMA1_CLK_ENABLE(); // Enable DMA2 clock + __HAL_RCC_DMA1_CLK_ENABLE(); // Enable DMA1 clock dmaHal.Init.Channel = DMA_CHANNEL_0; // DMA channel 0 is for SPI2 TX + #elif (TFT_SPI_PORT == 3) + __HAL_RCC_DMA1_CLK_ENABLE(); // Enable DMA1 clock + dmaHal.Init.Channel = DMA_CHANNEL_0; // DMA channel 0 is for SPI3 TX + #endif dmaHal.Init.Mode = DMA_NORMAL; //DMA_CIRCULAR; // // Normal = send buffer once diff --git a/Processors/TFT_eSPI_STM32.h b/Processors/TFT_eSPI_STM32.h index d705466..725c17d 100644 --- a/Processors/TFT_eSPI_STM32.h +++ b/Processors/TFT_eSPI_STM32.h @@ -170,6 +170,13 @@ // The DMA hard-coding for SPI2 is in TFT_eSPI_STM32.c as follows: // DMA_CHANNEL_4 // DMA1_Stream4_IRQn and DMA1_Stream4_IRQHandler() + #elif (TFT_SPI_PORT == 3) + // Initialise processor specific SPI and DMA instances - used by init() + #define INIT_TFT_DATA_BUS spiHal.Instance = SPI3; \ + dmaHal.Instance = DMA1_Stream5 + // The DMA hard-coding for SPI3 is in TFT_eSPI_STM32.c as follows: + // DMA_CHANNEL_4 + // DMA1_Stream5_IRQn and DMA1_Stream5_IRQHandler() #endif #elif defined (STM32F1xx)