From 3c6dab0a5246e7eddfcb421e970f6f0d819427fc Mon Sep 17 00:00:00 2001 From: Bodmer Date: Sat, 5 Nov 2022 18:12:28 +0000 Subject: [PATCH] Add ability to set the RP2040 parallel interface speed // For RP2040 processor and 8 or 16 bit parallel displays: // The parallel interface write cycle period is derived from a division of the CPU clock // speed so scales with the processor clock. This means that the divider ratio may need // to be increased when overclocking. I may also need to be adjusted dependant on the // display controller type (ILI94341, HX8357C etc). If RP2040_PIO_CLK_DIV is not defined // the library will set default values which may not suit your display. // The display controller data sheet will specify the minimum write cycle period. The // controllers often work reliably for shorter periods, however if the period is too short // the display may not initialise or graphics will become corrupted. // PIO write cycle frequency = (CPU clock/(4 * RP2040_PIO_CLK_DIV)) //#define RP2040_PIO_CLK_DIV 1 // 32ns write cycle at 125MHz CPU clock #define RP2040_PIO_CLK_DIV 2 // 64ns write cycle at 125MHz CPU clock //#define RP2040_PIO_CLK_DIV 3 // 96ns write cycle at 125MHz CPU clock --- Processors/TFT_eSPI_RP2040.h | 26 +++--- TFT_Drivers/ST7789_2_Rotation.h | 140 -------------------------------- TFT_Drivers/ST7789_Init.h | 2 +- User_Setup.h | 14 ++++ 4 files changed, 30 insertions(+), 152 deletions(-) diff --git a/Processors/TFT_eSPI_RP2040.h b/Processors/TFT_eSPI_RP2040.h index f4d5e92..c4a8f9f 100644 --- a/Processors/TFT_eSPI_RP2040.h +++ b/Processors/TFT_eSPI_RP2040.h @@ -82,9 +82,18 @@ // Different controllers have different minimum write cycle periods, so the PIO clock is changed accordingly // The PIO clock is a division of the CPU clock so scales when the processor is overclocked - // PIO write frequency = (CPU clock/(4 * DIV_UNITS)) - #if defined (TFT_PARALLEL_8_BIT) || defined (TFT_PARALLEL_16_BIT) || defined (RP2040_PIO_SPI) - #if defined (TFT_PARALLEL_16_BIT) + // PIO write frequency = (CPU clock/(4 * RP2040_PIO_CLK_DIV)) + // The write cycle periods below assume a 125MHz CPU clock speed + #if defined (TFT_PARALLEL_8_BIT) || defined (TFT_PARALLEL_16_BIT) + #if defined (RP2040_PIO_CLK_DIV) + #if (RP2040_PIO_CLK_DIV > 0) + #define DIV_UNITS RP2040_PIO_CLK_DIV + #define DIV_FRACT 0 + #else + #define DIV_UNITS 3 + #define DIV_FRACT 0 + #endif + #elif defined (TFT_PARALLEL_16_BIT) // Different display drivers have different minimum write cycle times #if defined (HX8357C_DRIVER) || defined (SSD1963_DRIVER) #define DIV_UNITS 1 // 32ns write cycle time SSD1963, HX8357C (maybe HX8357D?) @@ -94,14 +103,9 @@ #define DIV_UNITS 3 // 96ns write cycle time #endif #define DIV_FRACT 0 - #else // 8 bit parallel mode - #ifdef ILI9481_DRIVER - #define DIV_UNITS 1 - #define DIV_FRACT 160 // Note: Fractional values done with clock period dithering - #else - #define DIV_UNITS 1 - #define DIV_FRACT 0 - #endif + #else // 8 bit parallel mode default 64ns write cycle time + #define DIV_UNITS 2 + #define DIV_FRACT 0 // Note: Fractional values done with clock period dithering #endif #endif diff --git a/TFT_Drivers/ST7789_2_Rotation.h b/TFT_Drivers/ST7789_2_Rotation.h index 5bb8131..df5860c 100644 --- a/TFT_Drivers/ST7789_2_Rotation.h +++ b/TFT_Drivers/ST7789_2_Rotation.h @@ -138,143 +138,3 @@ _height = _init_width; break; } - // This is the command sequence that rotates the ST7789 driver coordinate frame - - writecommand(TFT_MADCTL); - rotation = m % 4; - switch (rotation) { - case 0: // Portrait -#ifdef CGRAM_OFFSET - if (_init_width == 135) - { - colstart = 52; - rowstart = 40; - } - else if(_init_height == 280) - { - colstart = 0; - rowstart = 20; - } - else if(_init_width == 172) - { - colstart = 34; - rowstart = 0; - } - else if(_init_width == 170) - { - colstart = 35; - rowstart = 0; - } - else - { - colstart = 0; - rowstart = 0; - } -#endif - writedata(TFT_MAD_COLOR_ORDER); - - _width = _init_width; - _height = _init_height; - break; - - case 1: // Landscape (Portrait + 90) -#ifdef CGRAM_OFFSET - if (_init_width == 135) - { - colstart = 40; - rowstart = 53; - } - else if(_init_height == 280) - { - colstart = 20; - rowstart = 0; - } - else if(_init_width == 172) - { - colstart = 0; - rowstart = 34; - } - else if(_init_width == 170) - { - colstart = 0; - rowstart = 35; - } - else - { - colstart = 0; - rowstart = 0; - } -#endif - writedata(TFT_MAD_MX | TFT_MAD_MV | TFT_MAD_COLOR_ORDER); - - _width = _init_height; - _height = _init_width; - break; - - case 2: // Inverter portrait -#ifdef CGRAM_OFFSET - if (_init_width == 135) - { - colstart = 53; - rowstart = 40; - } - else if(_init_height == 280) - { - colstart = 0; - rowstart = 20; - } - else if(_init_width == 172) - { - colstart = 34; - rowstart = 0; - } - else if(_init_width == 170) - { - colstart = 35; - rowstart = 0; - } - else - { - colstart = 0; - rowstart = 80; - } -#endif - writedata(TFT_MAD_MX | TFT_MAD_MY | TFT_MAD_COLOR_ORDER); - - _width = _init_width; - _height = _init_height; - break; - case 3: // Inverted landscape -#ifdef CGRAM_OFFSET - if (_init_width == 135) - { - colstart = 40; - rowstart = 52; - } - else if(_init_height == 280) - { - colstart = 20; - rowstart = 0; - } - else if(_init_width == 172) - { - colstart = 0; - rowstart = 34; - } - else if(_init_width == 170) - { - colstart = 0; - rowstart = 35; - } - else - { - colstart = 80; - rowstart = 0; - } -#endif - writedata(TFT_MAD_MV | TFT_MAD_MY | TFT_MAD_COLOR_ORDER); - - _width = _init_height; - _height = _init_width; - break; - } diff --git a/TFT_Drivers/ST7789_Init.h b/TFT_Drivers/ST7789_Init.h index 4855f08..05b9dd7 100644 --- a/TFT_Drivers/ST7789_Init.h +++ b/TFT_Drivers/ST7789_Init.h @@ -103,7 +103,7 @@ writedata(0x00); writedata(0x00); writedata(0x00); - writedata(0xE5); // 239 + writedata(0xEF); // 239 writecommand(ST7789_RASET); // Row address set writedata(0x00); diff --git a/User_Setup.h b/User_Setup.h index 5b47982..d1c85aa 100644 --- a/User_Setup.h +++ b/User_Setup.h @@ -324,6 +324,20 @@ // For RP2040 processor and SPI displays, uncomment the following line to use the PIO interface. //#define RP2040_PIO_SPI // Leave commented out to use standard RP2040 SPI port interface +// For RP2040 processor and 8 or 16 bit parallel displays: +// The parallel interface write cycle period is derived from a division of the CPU clock +// speed so scales with the processor clock. This means that the divider ratio may need +// to be increased when overclocking. I may also need to be adjusted dependant on the +// display controller type (ILI94341, HX8357C etc). If RP2040_PIO_CLK_DIV is not defined +// the library will set default values which may not suit your display. +// The display controller data sheet will specify the minimum write cycle period. The +// controllers often work reliably for shorter periods, however if the period is too short +// the display may not initialise or graphics will become corrupted. +// PIO write cycle frequency = (CPU clock/(4 * RP2040_PIO_CLK_DIV)) +//#define RP2040_PIO_CLK_DIV 1 // 32ns write cycle at 125MHz CPU clock +//#define RP2040_PIO_CLK_DIV 2 // 64ns write cycle at 125MHz CPU clock +//#define RP2040_PIO_CLK_DIV 3 // 96ns write cycle at 125MHz CPU clock + // For the RP2040 processor define the SPI port channel used (default 0 if undefined) //#define TFT_SPI_PORT 1 // Set to 0 if SPI0 pins are used, or 1 if spi1 pins used