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Update for high GPIO

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Bodmer
2023-01-13 16:20:11 +00:00
parent 1a50a23561
commit 90c3511913
1 changed files with 11 additions and 12 deletions
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23
Processors/TFT_eSPI_ESP32_S3.c
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@@ -96,21 +96,20 @@ uint8_t TFT_eSPI::readByte(void)
#if defined (TFT_PARALLEL_8_BIT) #if defined (TFT_PARALLEL_8_BIT)
RD_L; RD_L;
uint32_t reg; // Read all GPIO pins 0-31 b = gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET)); // Read three times to allow for bus access time
reg = gpio_input_get(); // Read three times to allow for bus access time b = gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET));
reg = gpio_input_get(); b = gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET)); // Data should be stable now
reg = gpio_input_get(); // Data should be stable now
RD_H; RD_H;
// Check GPIO bits used and build value // Check GPIO bits used and build value
b = (((reg>>TFT_D0)&1) << 0); b = (gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET)) << 0);
b |= (((reg>>TFT_D1)&1) << 1); b |= (gpio_get_level((gpio_num_t)(TFT_D1-MASK_OFFSET)) << 1);
b |= (((reg>>TFT_D2)&1) << 2); b |= (gpio_get_level((gpio_num_t)(TFT_D2-MASK_OFFSET)) << 2);
b |= (((reg>>TFT_D3)&1) << 3); b |= (gpio_get_level((gpio_num_t)(TFT_D3-MASK_OFFSET)) << 3);
b |= (((reg>>TFT_D4)&1) << 4); b |= (gpio_get_level((gpio_num_t)(TFT_D4-MASK_OFFSET)) << 4);
b |= (((reg>>TFT_D5)&1) << 5); b |= (gpio_get_level((gpio_num_t)(TFT_D5-MASK_OFFSET)) << 5);
b |= (((reg>>TFT_D6)&1) << 6); b |= (gpio_get_level((gpio_num_t)(TFT_D6-MASK_OFFSET)) << 6);
b |= (((reg>>TFT_D7)&1) << 7); b |= (gpio_get_level((gpio_num_t)(TFT_D7-MASK_OFFSET)) << 7);
#endif #endif
return b; return b;