Bodmer/TFT_eSPI
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Fix read for high (>31) GPIO

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Bodmer
2023-02-25 00:47:56 +00:00
parent ab55b0ed03
commit f76ed73a3f
1 changed files with 12 additions and 12 deletions
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24
Processors/TFT_eSPI_ESP32_S3.c
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@@ -93,20 +93,20 @@ uint8_t TFT_eSPI::readByte(void)
#if defined (TFT_PARALLEL_8_BIT)
RD_L;
b = gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET)); // Read three times to allow for bus access time
b = gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET));
b = gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET)); // Data should be stable now
RD_H;
b = gpio_get_level((gpio_num_t)TFT_D0); // Read three times to allow for bus access time
b = gpio_get_level((gpio_num_t)TFT_D0);
b = gpio_get_level((gpio_num_t)TFT_D0); // Data should be stable now
// Check GPIO bits used and build value
b = (gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET)) << 0);
b |= (gpio_get_level((gpio_num_t)(TFT_D1-MASK_OFFSET)) << 1);
b |= (gpio_get_level((gpio_num_t)(TFT_D2-MASK_OFFSET)) << 2);
b |= (gpio_get_level((gpio_num_t)(TFT_D3-MASK_OFFSET)) << 3);
b |= (gpio_get_level((gpio_num_t)(TFT_D4-MASK_OFFSET)) << 4);
b |= (gpio_get_level((gpio_num_t)(TFT_D5-MASK_OFFSET)) << 5);
b |= (gpio_get_level((gpio_num_t)(TFT_D6-MASK_OFFSET)) << 6);
b |= (gpio_get_level((gpio_num_t)(TFT_D7-MASK_OFFSET)) << 7);
b = (gpio_get_level((gpio_num_t)TFT_D0) << 0);
b |= (gpio_get_level((gpio_num_t)TFT_D1) << 1);
b |= (gpio_get_level((gpio_num_t)TFT_D2) << 2);
b |= (gpio_get_level((gpio_num_t)TFT_D3) << 3);
b |= (gpio_get_level((gpio_num_t)TFT_D4) << 4);
b |= (gpio_get_level((gpio_num_t)TFT_D5) << 5);
b |= (gpio_get_level((gpio_num_t)TFT_D6) << 6);
b |= (gpio_get_level((gpio_num_t)TFT_D7) << 7);
RD_H;
#endif
return b;