diff --git a/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp b/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp
index d0db731de4..310c85089f 100644
--- a/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp
+++ b/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp
@@ -126,7 +126,7 @@ void Jit64AsmRoutineManager::Generate()
 
   // Check both block.effectiveAddress and block.msrBits.
   MOV(32, R(RSCRATCH2), PPCSTATE(msr));
-  AND(32, R(RSCRATCH2), Imm32(JitBlock::JIT_CACHE_MSR_MASK));
+  AND(32, R(RSCRATCH2), Imm32(JitBaseBlockCache::JIT_CACHE_MSR_MASK));
   SHL(64, R(RSCRATCH2), Imm8(32));
   MOV(32, R(RSCRATCH_EXTRA), PPCSTATE(pc));
   OR(64, R(RSCRATCH2), R(RSCRATCH_EXTRA));
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
index 20921b2b70..7f323ebe6d 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
@@ -88,7 +88,7 @@ void JitArm64::GenerateAsm()
     FixupBranch pc_missmatch = B(CC_NEQ);
 
     LDR(INDEX_UNSIGNED, pc_and_msr2, PPC_REG, PPCSTATE_OFF(msr));
-    ANDI2R(pc_and_msr2, pc_and_msr2, JitBlock::JIT_CACHE_MSR_MASK);
+    ANDI2R(pc_and_msr2, pc_and_msr2, JitBaseBlockCache::JIT_CACHE_MSR_MASK);
     LDR(INDEX_UNSIGNED, pc_and_msr, block, offsetof(JitBlock, msrBits));
     CMP(pc_and_msr, pc_and_msr2);
     FixupBranch msr_missmatch = B(CC_NEQ);
diff --git a/Source/Core/Core/PowerPC/JitCommon/JitCache.cpp b/Source/Core/Core/PowerPC/JitCommon/JitCache.cpp
index a108a3fdb6..f8dabcef69 100644
--- a/Source/Core/Core/PowerPC/JitCommon/JitCache.cpp
+++ b/Source/Core/Core/PowerPC/JitCommon/JitCache.cpp
@@ -116,7 +116,7 @@ JitBlock* JitBaseBlockCache::AllocateBlock(u32 em_address)
   b.invalid = false;
   b.effectiveAddress = em_address;
   b.physicalAddress = PowerPC::JitCache_TranslateAddress(em_address).address;
-  b.msrBits = MSR & JitBlock::JIT_CACHE_MSR_MASK;
+  b.msrBits = MSR & JIT_CACHE_MSR_MASK;
   b.linkData.clear();
   b.in_icache = 0;
   num_blocks++;  // commit the current block
@@ -180,7 +180,7 @@ JitBlock* JitBaseBlockCache::GetBlockFromStartAddress(u32 addr, u32 msr)
 
   JitBlock* b = map_result->second;
   if (b->invalid || b->effectiveAddress != addr ||
-      b->msrBits != (msr & JitBlock::JIT_CACHE_MSR_MASK))
+      b->msrBits != (msr & JIT_CACHE_MSR_MASK))
     return nullptr;
   return b;
 }
@@ -189,10 +189,9 @@ const u8* JitBaseBlockCache::Dispatch()
 {
   JitBlock* block = iCache[FastLookupEntryForAddress(PC)];
 
-  while (!block || block->effectiveAddress != PC ||
-         block->msrBits != (MSR & JitBlock::JIT_CACHE_MSR_MASK))
+  while (!block || block->effectiveAddress != PC || block->msrBits != (MSR & JIT_CACHE_MSR_MASK))
   {
-    MoveBlockIntoFastCache(PC, MSR & JitBlock::JIT_CACHE_MSR_MASK);
+    MoveBlockIntoFastCache(PC, MSR & JIT_CACHE_MSR_MASK);
     block = iCache[FastLookupEntryForAddress(PC)];
   }
 
diff --git a/Source/Core/Core/PowerPC/JitCommon/JitCache.h b/Source/Core/Core/PowerPC/JitCommon/JitCache.h
index d0bcd07bf2..d9f3e9944d 100644
--- a/Source/Core/Core/PowerPC/JitCommon/JitCache.h
+++ b/Source/Core/Core/PowerPC/JitCommon/JitCache.h
@@ -24,13 +24,6 @@ class JitBase;
 // address.
 struct JitBlock
 {
-  enum
-  {
-    // Mask for the MSR bits which determine whether a compiled block
-    // is valid (MSR.IR and MSR.DR, the address translation bits).
-    JIT_CACHE_MSR_MASK = 0x30,
-  };
-
   // A special entry point for block linking; usually used to check the
   // downcount.
   const u8* checkedEntry;
@@ -115,6 +108,10 @@ public:
 class JitBaseBlockCache
 {
 public:
+  // Mask for the MSR bits which determine whether a compiled block
+  // is valid (MSR.IR and MSR.DR, the address translation bits).
+  static constexpr u32 JIT_CACHE_MSR_MASK = 0x30;
+
   static constexpr int MAX_NUM_BLOCKS = 65536 * 2;
   static constexpr u32 iCache_Num_Elements = 0x10000;
   static constexpr u32 iCache_Mask = iCache_Num_Elements - 1;