diff --git a/Source/Core/Core/Src/DSP/Jit/DSPJitBranch.cpp b/Source/Core/Core/Src/DSP/Jit/DSPJitBranch.cpp
index 1dbb31fe58..8ca770e35d 100644
--- a/Source/Core/Core/Src/DSP/Jit/DSPJitBranch.cpp
+++ b/Source/Core/Core/Src/DSP/Jit/DSPJitBranch.cpp
@@ -40,19 +40,17 @@ static void ReJitConditional(const UDSPInstruction opc, DSPEmitter& emitter)
 	{
 	case 0x0: // GE - Greater Equal
 	case 0x1: // L - Less
-		emitter.MOV(16, R(EDX), R(EAX));
-		emitter.SHL(16, R(EDX), Imm8(2));
+		emitter.LEA(16, EDX, MScaled(EAX, SCALE_4, 0));
 		emitter.XOR(16, R(EAX), R(EDX));
 		emitter.TEST(16, R(EAX), Imm16(8));
 		break;
 	case 0x2: // G - Greater
 	case 0x3: // LE - Less Equal
-		emitter.MOV(16, R(EDX), R(EAX));
-		emitter.SHL(16, R(EDX), Imm8(2));
+		emitter.LEA(16, EDX, MScaled(EAX, SCALE_4, 0));
 		emitter.XOR(16, R(EAX), R(EDX));
-		emitter.SHR(16, R(EDX), Imm8(1));
+		emitter.LEA(16, EAX, MScaled(EAX, SCALE_2, 0));
 		emitter.OR(16, R(EAX), R(EDX));
-		emitter.TEST(16, R(EAX), Imm16(8));
+		emitter.TEST(16, R(EAX), Imm16(0x10));
 		break;
 	case 0x4: // NZ - Not Zero
 	case 0x5: // Z - Zero 
@@ -68,14 +66,12 @@ static void ReJitConditional(const UDSPInstruction opc, DSPEmitter& emitter)
 		break;
 	case 0xa: // ?
 	case 0xb: // ?
-		emitter.MOV(16, R(EDX), R(EAX));
-		emitter.SHR(16, R(EDX), Imm8(1));
+		emitter.LEA(16, EDX, MScaled(EAX, SCALE_2, 0));
 		emitter.OR(16, R(EAX), R(EDX));
-		emitter.SHL(16, R(EDX), Imm8(3));
-		emitter.NOT(16, R(EDX));
-		emitter.AND(16, R(EAX), R(EDX)); 
+		emitter.LEA(16, EDX, MScaled(EDX, SCALE_8, 0));
 		emitter.NOT(16, R(EAX));
-		emitter.TEST(16, R(EAX), Imm16(0x10));
+		emitter.OR(16, R(EAX), R(EDX));
+		emitter.TEST(16, R(EAX), Imm16(0x20));
 		break;
 	case 0xc: // LNZ  - Logic Not Zero
 	case 0xd: // LZ - Logic Zero
diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp
index 987b1561db..6050a27777 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp
@@ -1308,15 +1308,14 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak
 			Jit->MOVZX(32, 16, EAX, M(((char *)&GQR(quantreg)) + 2));
 			Jit->MOVZX(32, 8, EDX, R(AL));
 			Jit->OR(32, R(EDX), Imm8(w << 3));
-			// FIXME: Fix ModR/M encoding to allow [EDX*4+disp32]! (MComplex can do this, no?)
 #ifdef _M_IX86
-			Jit->SHL(32, R(EDX), Imm8(2));
+			int addr_scale = SCALE_4;
 #else
-			Jit->SHL(32, R(EDX), Imm8(3));
+			int addr_scale = SCALE_8;
 #endif
 			Jit->MOV(32, R(ECX), regLocForInst(RI, getOp1(I)));
 			Jit->ABI_AlignStack(0);
-			Jit->CALLptr(MDisp(EDX, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedLoadQuantized)));
+			Jit->CALLptr(MScaled(EDX, addr_scale, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedLoadQuantized)));
 			Jit->ABI_RestoreStack(0);
 			Jit->MOVAPD(reg, R(XMM0));
 			RI.fregs[reg] = I;
@@ -1409,16 +1408,15 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak
 			u32 quantreg = *I >> 24;
 			Jit->MOVZX(32, 16, EAX, M(&PowerPC::ppcState.spr[SPR_GQR0 + quantreg]));
 			Jit->MOVZX(32, 8, EDX, R(AL));
-			// FIXME: Fix ModR/M encoding to allow [EDX*4+disp32]!
 #ifdef _M_IX86
-			Jit->SHL(32, R(EDX), Imm8(2));
+			int addr_scale = SCALE_4;
 #else
-			Jit->SHL(32, R(EDX), Imm8(3));
+			int addr_scale = SCALE_8;
 #endif
 			Jit->MOV(32, R(ECX), regLocForInst(RI, getOp2(I)));
 			Jit->MOVAPD(XMM0, fregLocForInst(RI, getOp1(I)));
 			Jit->ABI_AlignStack(0);
-			Jit->CALLptr(MDisp(EDX, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedStoreQuantized)));
+			Jit->CALLptr(MScaled(EDX, addr_scale, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedStoreQuantized)));
 			Jit->ABI_RestoreStack(0);
 			if (RI.IInfo[I - RI.FirstI] & 4)
 				fregClearInst(RI, getOp1(I));