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arduino-esp32/tools/sdk/esp32/lib/libxtensa.a

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Initial Commit
2020-05-09 19:11:30 +03:00
!<arch>
Add camera support first automated cmake build
2020-10-12 23:56:00 +03:00
/ 1602535595 0 0 0 390 `
Try with speed optimization as opposed to debug. Coremark 240 -> 430
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<02><02>t<>}<7D>}<7D>}<7D>}<7D>}<7D><00><><00><00>  YXesp_backtrace_get_next_frameesp_backtrace_printesp_backtrace_get_startxtensa_shared_stack_function_donextensa_shared_stackxtensa_shared_stack_callbackxtensa_shared_stack_envesp_execute_shared_stack_functionesp_shared_stack_invoke_functioneri_readeri_writetrax_start_tracetrax_trigger_traceend_after_delaytrax_enable// 122 `
Initial Commit
2020-05-09 19:11:30 +03:00
debug_helpers.c.obj/
debug_helpers_asm.S.obj/
expression_with_stack_xtensa.c.obj/
Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
expression_with_stack_xtensa_asm.S.obj/
Add camera support first automated cmake build
2020-10-12 23:56:00 +03:00
/0 1602535594 501 20 100644 29240 `
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
Backtrace:0x%08X:0x%08X |<-CORRUPTED |<-CONTINUES
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
<EFBFBD>
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
<00><01> /Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/soc/include/soc/Users/ficeto/.espressif/tools/xtensa-esp32-elf/esp-2020r2-8.2.0/xtensa-esp32-elf/xtensa-esp32-elf/sys-include/machine/Users/ficeto/.espressif/tools/xtensa-esp32-elf/esp-2020r2-8.2.0/xtensa-esp32-elf/lib/gcc/xtensa-esp32-elf/8.2.0/include/Users/ficeto/.espressif/tools/xtensa-esp32-elf/esp-2020r2-8.2.0/xtensa-esp32-elf/xtensa-esp32-elf/sys-include/sys/Users/ficeto/.espressif/tools/xtensa-esp32-elf/esp-2020r2-8.2.0/xtensa-esp32-elf/xtensa-esp32-elf/sys-include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_common/include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/include/xtensa/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/esp32/include/xtensa/config/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_rom/includedebug_helpers.csoc_memory_layout.hcpu.h_default_types.hstddef.h_stdint.hlock.h_types.hreent.hstdlib.hesp_err.hesp_debug_helpers.hhal.h core.h
Try with speed optimization as opposed to debug. Coremark 240 -> 430
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Initial Commit
2020-05-09 19:11:30 +03:00
ABI=0
Try with speed optimization as opposed to debug. Coremark 240 -> 430
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-10-12 23:56:00 +03:00
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2020-05-09 19:11:30 +03:00
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Add camera support first automated cmake build
2020-10-12 23:56:00 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
FreeRTOS.h queue.h semphr.h esp_expression_with_stack.h xtensa_rtos.h
xtensa_timer.h
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
setjmp.hesp_debug_helpers.h string.htask.h assert.hsetjmp.hportable.h :               ' ^ '"   Z    |  2|    -  A z A  x G   w        p   "          -         Xthal_cp_id_FPUXthal_cp_id_XCHAL_CP5_IDENTXthal_all_extra_sizesize_tXthal_itlb_arf_ways__locale_t__value__sfXthal_all_extra_alignXthal_have_booleansowner_readXthal_excm_levelGNU C99 8.2.0 -mlongcalls -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -ggdb -O2 -std=gnu99 -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fstack-protectorXthal_rev_no_asctime_buf_cvtlenXthal_have_exceptionsXthal_instrom_vaddrsoc_memory_type_desc_tXthal_cp_id_XCHAL_CP6_IDENT__func____tm_wcsrtombs_state_nbuf__tm_secXthal_have_sextBaseType_txtensa_shared_stack_l64a_bufsetjmpXthal_tram_syncucDummy7_lock_writeXthal_have_fptype_multXthal_have_clampsXthal_dataram_paddrXthal_num_ibreakXthal_cpregs_restore_fnXthal_cp_id_XCHAL_CP7_IDENTXthal_have_ccountXthal_cp_numXthal_cpregs_save_nw_fn__wchXthal_xlmi_size__uint8_t_file_on_exit_argsXthal_dtlb_way_bitsiram_addressXthal_have_loopsXthal_icache_line_lockableXthal_num_instram_mbrlen_statelong int_result_k_sizeXthal_hw_configid0Xthal_hw_configid1Xthal_cp_names_localtime_bufXthal_dataram_vaddr__tm_monXthal_dtlb_arf_waysxMPU_SETTINGS_misc_reentXthal_dcache_sizeQueueHandle_tsigned charuint8_t__sf_fake_stdinesp_shared_stack_invoke_functionaliased_iramXthal_intlevelXthal_have_highlevel_interruptsXthal_xea_versionunsigned charXthal_itlb_wayssoc_memory_regionsStaticTask_t_unspecified_locale_info_reent_global_impure_ptrXthal_hw_release_minorXthal_have_tlbswatchpoint_place_BoolXthal_cp_maxpxDummy1pxDummy6pxDummy8Xthal_release_minorcharmemset_fnsXthal_num_writebuffer_entries_closeXthal_num_dbreakXthal_cpregs_save_fnSemaphoreHandle_tlockXthal_mpu_bgmap_stdinXthal_num_dataromXthal_mmu_ringsuxDummy12startup_stackXthal_datarom_paddrXthal_dcache_setwidthXthal_datarom_sizeXthal_mmu_asid_kerneluxDummy20capsvPortSetStackWatchpointXthal_tram_enabledXT_INTEXC_HOOKXthal_release_internal_cookie__sFILE_fake_wds_sig_funcXthal_icache_linesizeXthal_have_minmax_offset_cvtbuffunction__assert_funcXthal_have_speculationXthal_datarom_vaddrXthal_hw_release_majorspinlockXthal_tram_pendingXthal_mmu_min_pte_page_sizeesp_execute_shared_stack_function_p5slong unsigned intXthal_release_majorXthal_mmu_ring_bitsXthal_icache_size__sFILE__sdidinit_flags2Xthal_instram_paddresp_set_watchpointxDummy17_LOCK_RECURSIVE_T__sf_fake_stderr_errnouxDummy5stack_sizeXthal_cpregs_size_signal_buf_Bigint_maxwdsXthal_have_cacheattr__cleanup_atexit0__intptr_tXthal_cp_mask_XCHAL_CP1_IDENTXthal_dtlb_ways__uint32_t_emergency_lock_tXthal_instram_vaddrlong long int_on_exit_args_ptr_niobs__sglueXthal_hw_release_nameshared_stack_functionpvDummy15stack_gamma_signgamXthal_have_xlt_cacheattrXthal_cp_mask_XCHAL_CP2_IDENT_freelist_iobsXthal_intlevel_andbelow_mask_glue_signesp_clear_watchpointXthal_have_nmicountXthal_cp_id_XCHAL_CP4_IDENT__sf_fake_stdoutunsigned intXthal_debug_configuredtop_of_stackxtensa_shared_stack_callbackintptr_t_xt_intexc_hooksXthal_num_ccompareXthal_have_densityulDummy18Xthal_have_interruptsXthal_cp_mask_XCHAL_CP3_IDENTXthal_dcache_wayscurrent_task_stack_wcrtomb_stateXthal_build_unique_id__tm_mday/Users/ficeto/Desktop/ESP32/ESP32S2/esp32-arduino-lib-builder/buildXthal_instrom_size_ubufXthal_num_aregspvDummyLocalStorageCallBack_stderr_wctomb_state_mbstatecurrent_rand_nextxtensa_share
Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
ABI=0
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-10-12 23:56:00 +03:00
x <00> .symtab.strtab.shstrtab.rela.literal.esp_execute_shared_stack_function.text.data.bss.rodata.esp_execute_shared_stack_function.str1.4.rela.text.esp_execute_shared_stack_function.rodata.__func__$5205.bss.current_task_stack.data.xtensa_shared_stack_spinlock.bss.xtensa_shared_stack_function_done.rela.debug_frame.rela.debug_info.debug_abbrev.rela.debug_loc.rela.debug_aranges.rela.debug_ranges.rela.debug_line.debug_str.comment.xtensa.info.rela.xt.lit.rela.xt.prop 4|@<00>Eh! K<00>Q<00>W<00>\2<00><00><00>x<<00>@<00>F<00>! <00><00>"<00><00><00><00> <00>7<00>(2@<00>IH!  I<00>D@8J<00>! U<00><00>h<00>gc@<00>^<00>! x<00> s@<00>`$! <00> !0<00>@<00>``! <00>;!<00><00>@Ta<! <00>0<00>):<00>0@&<00>4@8<00>l@<00>@<00>d ! <00>t@<00><00>@<00>d<00>! A<00>" <00>C<00>,e<00>/82 1602535594 501 20 100644 4568 `
Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
ELF^@4( a&<00><00> <0C> a ya <07><00> <0A> Xtensa_InfoUSE_ABSOLUTE_LITERALS=0
Initial Commit
2020-05-09 19:11:30 +03:00
ABI=0
Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
<00>~<01> /Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensaexpression_with_stack_xtensa_asm.S               "$h<00><01>%$/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/expression_with_stack_xtensa_asm.S/Users/ficeto/Desktop/ESP32/ESP32S2/esp32-arduino-lib-builder/buildGNU AS 2.31.1($$<00><> <00><><00><><00><>$<00><>0 <00><>:$<00><>D(<00><>O,<00><>Z0<00><>b@<00><>r<00><>z<00><><EFBFBD><00><><EFBFBD> <00><><EFBFBD><00><><EFBFBD><00><><EFBFBD><00><><EFBFBD><00><><EFBFBD> <00><><EFBFBD>$<00><><EFBFBD>(<00><><EFBFBD>,<00><><EFBFBD>0<00><><EFBFBD>4<00><><EFBFBD>8<00><>H<00><>
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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2020-10-12 23:56:00 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00

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2020-05-09 19:11:30 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
ABI=0
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Add camera support first automated cmake build
2020-10-12 23:56:00 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00

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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
ABI=0
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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