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arduino-esp32/tools/sdk/esp32s2/lib/libxtensa.a

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Initial Commit
2020-05-09 19:11:30 +03:00
!<arch>
Add camera support first automated cmake build
2020-10-12 23:56:00 +03:00
/ 1602535338 0 0 0 1014 `
Try with speed optimization as opposed to debug. Coremark 240 -> 430
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&<04><04>v<00><><00>t<00>t \ \W<><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><><01><>esp_backtrace_get_next_frameesp_backtrace_printesp_backtrace_get_startxtensa_shared_stack_function_donextensa_shared_stackxtensa_shared_stack_callbackxtensa_shared_stack_envesp_execute_shared_stack_functionesp_shared_stack_invoke_functioneri_readeri_writetrax_start_tracetrax_trigger_traceend_after_delaytrax_enable__atomic_compare_exchange_1__atomic_compare_exchange_2__atomic_compare_exchange_4__atomic_compare_exchange_8__atomic_fetch_add_1__atomic_fetch_add_2__atomic_fetch_add_4__atomic_fetch_add_8__atomic_fetch_sub_1__atomic_fetch_sub_2__atomic_fetch_sub_4__atomic_fetch_sub_8__atomic_fetch_and_1__atomic_fetch_and_2__atomic_fetch_and_4__atomic_fetch_and_8__atomic_fetch_or_1__atomic_fetch_or_2__atomic_fetch_or_4__atomic_fetch_or_8__atomic_fetch_xor_1__atomic_fetch_xor_2__atomic_fetch_xor_4__atomic_fetch_xor_8// 122 `
Initial Commit
2020-05-09 19:11:30 +03:00
debug_helpers.c.obj/
debug_helpers_asm.S.obj/
expression_with_stack_xtensa.c.obj/
Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
expression_with_stack_xtensa_asm.S.obj/
Add camera support first automated cmake build
2020-10-12 23:56:00 +03:00
/0 1602535338 501 20 100644 28904 `
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
Backtrace:0x%08X:0x%08X |<-CORRUPTED |<-CONTINUES
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
<01> /Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/soc/include/soc/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/machine/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/lib/gcc/xtensa-esp32s2-elf/8.2.0/include/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/sys/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_common/include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/include/xtensa/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/esp32s2/include/xtensa/config/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_rom/includedebug_helpers.csoc_memory_layout.hcpu.h_default_types.hstddef.h_stdint.hlock.h_types.hreent.hstdlib.hesp_err.hesp_debug_helpers.hhal.h core.h
Try with speed optimization as opposed to debug. Coremark 240 -> 430
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esp_rom_sys.h               '<03>   <03>~  <03>  m  '    L     <03>~      <03>         %|   %    <03>    S  '  ~                 \   <03>  m  '   '   L     <03>~      <03>      %   %    <03>    
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Initial Commit
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ABI=0
Try with speed optimization as opposed to debug. Coremark 240 -> 430
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Add camera support first automated cmake build
2020-10-12 23:56:00 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Add camera support first automated cmake build
2020-10-12 23:56:00 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-10-11 19:51:11 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
FreeRTOS.h queue.h semphr.h esp_expression_with_stack.h xtensa_rtos.h
xtensa_timer.h
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
setjmp.hesp_debug_helpers.h string.htask.h assert.hsetjmp.hportable.h :               ' ^ '"   Z    |  2|  |   -  A z A { G  G} z  w       p   "          -         Xthal_cp_id_XCHAL_CP5_IDENTXthal_all_extra_sizesize_tXthal_itlb_arf_ways__locale_t__value__sfXthal_all_extra_alignXthal_have_booleansowner_readXthal_excm_level_writeXthal_rev_no_asctime_buf_cvtlenXthal_have_exceptionsXthal_instrom_vaddrsoc_memory_type_desc_tXthal_cp_id_XCHAL_CP6_IDENT__func____tm_wcsrtombs_state_nbuf__tm_secXthal_have_sextBaseType_txtensa_shared_stack_l64a_bufsetjmpXthal_tram_syncucDummy7_lockXthal_have_fptype_multXthal_have_clampsXthal_dataram_paddrXthal_num_ibreakXthal_cpregs_restore_fnXthal_cp_id_XCHAL_CP7_IDENTXthal_have_ccountXthal_cp_numXthal_cpregs_save_nw_fn__wchXthal_xlmi_size__uint8_t_file_on_exit_argsXthal_dtlb_way_bitsiram_addressXthal_have_loopsXthal_icache_line_lockableXthal_num_instram_mbrlen_statelong int_result_k_sizeXthal_hw_configid0Xthal_hw_configid1Xthal_cp_names_localtime_bufXthal_dataram_vaddr__tm_monXthal_dtlb_arf_ways_misc_reentXthal_dcache_sizeQueueHandle_tsigned charuint8_t__sf_fake_stdinesp_shared_stack_invoke_functionaliased_iramXthal_intlevelXthal_have_highlevel_interruptsXthal_xea_versionunsigned charXthal_itlb_wayssoc_memory_regionsStaticTask_t_unspecified_locale_info_reent_global_impure_ptrXthal_hw_release_minorXthal_have_tlbswatchpoint_place_BoolXthal_cp_maxpxDummy1pxDummy6pxDummy8Xthal_release_minorcharmemset_fnsXthal_num_writebuffer_entries_closeXthal_num_dbreakXthal_cpregs_save_fnSemaphoreHandle_tlockXthal_mpu_bgmap_stdinXthal_num_dataromXthal_mmu_ringsuxDummy12startup_stackXthal_datarom_paddrXthal_dcache_setwidthXthal_datarom_sizeXthal_mmu_asid_kerneluxDummy20capsvPortSetStackWatchpointXthal_tram_enabledXT_INTEXC_HOOKXthal_release_internal_cookie__sFILE_fake_wds_sig_funcXthal_icache_linesizeXthal_have_minmax_offset_cvtbuffunction__assert_funcXthal_have_speculationXthal_datarom_vaddrXthal_hw_release_majorspinlockXthal_tram_pendingXthal_mmu_min_pte_page_sizeesp_execute_shared_stack_function_p5slong unsigned intXthal_release_majorXthal_mmu_ring_bitsXthal_icache_size__sFILE__sdidinit_flags2Xthal_instram_paddrXthal_cp_mask_XCHAL_CP0_IDENTesp_set_watchpointxDummy17_LOCK_RECURSIVE_T__sf_fake_stderr_errnouxDummy5stack_sizeXthal_cpregs_size_signal_buf_Bigint_maxwdsXthal_have_cacheattr__cleanup_atexit0__intptr_tXthal_cp_mask_XCHAL_CP1_IDENTXthal_dtlb_ways__uint32_t_emergency_lock_tXthal_instram_vaddrlong long int_on_exit_args_ptr_niobs__sglueXthal_hw_release_nameshared_stack_functionpvDummy15stack_gamma_signgamXthal_have_xlt_cacheattrXthal_cp_mask_XCHAL_CP2_IDENT_freelist_iobsXthal_intlevel_andbelow_mask_glue_signesp_clear_watchpointXthal_have_nmicountXthal_cp_id_XCHAL_CP4_IDENT__sf_fake_stdoutunsigned intXthal_debug_configuredtop_of_stackxtensa_shared_stack_callbackintptr_t_xt_intexc_hooksXthal_num_ccompareXthal_have_densityulDummy18Xthal_have_interruptsXthal_cp_mask_XCHAL_CP3_IDENTXthal_dcache_wayscurrent_task_stack_wcrtomb_stateXthal_build_unique_id__tm_mday/Users/ficeto/Desktop/ESP32/ESP32S2/esp32-arduino-lib-builder/buildXthal_instrom_size_ubufXthal_num_aregspvDummyLocalStorageCallBack_stderr_wctomb_state_mbstatecurrent_rand_nextxtensa_shared_stack_env_flagsXthal_num_instrom_atexitsoc_memory_region_count__countxthal_MPU_entryXthal_dcache_is_writebackXthal_cp_mask_XCHAL_CP4_IDENTxDummy1__tm_wdayXthal_dataram_size
Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
ABI=0
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-10-12 23:56:00 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
ABI=0
Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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2020-10-12 23:56:00 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00

Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-08-24 19:10:52 +03:00
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2020-10-11 19:51:11 +03:00
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2020-10-11 19:51:11 +03:00
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2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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esp_rom_sys.h      n    6     z    Xthal_hw_release_nameXthal_hw_configid0Xthal_hw_configid1Xthal_mmu_ca_bits_miscXthal_have_ccountXthal_memory_orderGNU C99 8.2.0 -mlongcalls -ggdb -O2 -std=gnu99 -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fstack-protector_lock_tXthal_cp_mask_XCHAL_CP2_IDENT_on_exit_args_writeXthal_num_xlmi_wctomb_stateXthal_instrom_sizeXthal_dtlb_ways_r48Xthal_dcache_linewidthXthal_cp_namesXthal_debug_configured_signal_bufunsigned intXthal_cp_maxXthal_num_interruptsXthal_dtlb_way_bits_lbfsize_flagsXthal_mmu_ringsXthal_release_internalXthal_cp_id_XCHAL_CP7_IDENT_errnoesp_log_timestampXthal_cpregs_sizeXthal_have_spanning_wayESP_LOG_DEBUGXthal_inttypeXthal_cpregs_save_fn__sf_fake_stdout_LOCK_RECURSIVE_TXthal_have_highlevel_interruptsXthal_num_intlevels_read_mbrlen_stateXthal_cp_id_XCHAL_CP0_IDENTXthal_have_mimic_cacheattrxthal_MPU_entry_stdoutXthal_cpregs_align_fpos_tXthal_mmu_max_pte_page_size_fnsXthal_icache_line_lockable_cookie_Bigint__tm_wdayXthal_cpregs_save_nw_fn_resultuint32_tXthal_cp_mask_XCHAL_CP4_IDENT__tm_hourXthal_intlevel_maskXthal_have_tlbsXthal_icache_linewidthXthal_hw_release_major__countXthal_num_aregs/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/trax.c__tm_min/Users/ficeto/Desktop/ESP32/ESP32S2/esp32-arduino-lib-builder/build__sftrax_trigger_traceend_after_delayXthal_instram_vaddr_rand48trax_start_trace_result_klong long unsigned int_asctime_bufXthal_num_ccompare__sFILE_wdsXthal_mmu_sr_bits__FILEXthal_instrom_vaddrXthal_cp_id_XCHAL_CP2_IDENT_offsetXthal_xlmi_sizeXthal_cp_mask_XCHAL_CP6_IDENTXthal_have_sextXthal_have_minmaxXthal_num_datarom_emergencyXthal_have_booleansXthal_dtlb_arf_waysXthal_num_instromXthal_have_mac16Xthal_tram_syncXthal_instram_paddr__tm_secXthal_dcache_sizesuboptarg__tm_yday_inc_indXthal_cp_id_XCHAL_CP5_IDENT_next_mbsrtowcs_stateXthal_itlb_way_bitsXthal_instrom_paddrXthal_icache_setwidthESP_LOG_NONEXthal_have_fpXthal_num_dataramTRAX_DOWNCOUNT_INSTRUCTIONSXthal_num_instram__valueXthal_have_windowed_p5sXthal_xea_versionXthal_have_identity_map_wcsrtombs_state_mblen_stateXthal_hw_release_minorchar__tm_mdayXthal_have_mul16_sig_func_mbrtowc_stateXthal_intlevelXthal_have_nmi_flock_tXthal_tram_pending__wch_iobsXthal_release_name_on_exit_args_ptrXthal_extra_size_close__sdidinit__sFILE_fakeXthal_cpregs_restore_fnXthal_excm_level_stdin_gamma_signgamlong long intXthal_have_cacheattrXthal_extra_align_baseXthal_build_unique_id_freelist_mult__ULongXthal_instram_size_wcrtomb_stateXthal_icache_sizeXthal_rev_no_fileexc_cause_tableXthal_dataram_vaddrXthal_cp_id_XCHAL_CP6_IDENTXthal_mmu_ring_bits__cleanup_mbstate_tXthal_have_xlt_cacheattr_mprecXthal_num_writebuffer_entriesXthal_num_ibreakXthal_cpregs_restore_nw_fn__tm_isdstesp_rom_printfESP_LOG_INFOXthal_release_majorXthal_cp_id_XCHAL_CP4_IDENTXthal_cp_mask_XCHAL_CP3_IDENTXthal_icache_waystrax_downcount_unit_tXthal_intlevel_andbelow_mask__tm_monXthal_dataram_paddr_atexit0Xthal_dcache_setwidthXthal_dcache_line_lockableXthal_mpu_bgmap_atexit_mbstateXthal_have_densityXthal_mmu_asid_bitsshort intXthal_datarom_vaddrXthal_all_extra_sizelong intXthal_have_loopsXthal_dcache_linesizeXthal_datarom_sizeTRAX_DOWNCOUNT_WORDS_signdelayXthal_cp_id_XCHAL_CP1_IDENT_data__wchb_global_impure_ptr__tm_year_misc_reentXthal_inttype_maskXthal_itlb_arf_waysESP_LOG_ERROR_localtime_buf_cvtlen_maxwds_l64a_bufXthal_have_clampsXthal_datarom_paddrunits_until_stop_blksize__tmXthal_cp_numXthal_num_aregs_log2_lockXthal_dcache_is_writebackXthal_release_minorlong unsigned intXthal_dataram_sizeESP_LOG_VERBOSE_niobswint_tXthal_icache_linesize_dso_handleXthal_timer_interruptXthal_have_nsaXthal_itlb_ways_cvtbufunsigned charESP_LOG_WARN__uint32_tXthal_cp_id_XCHAL_CP
Initial Commit
2020-05-09 19:11:30 +03:00
ABI=0
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Add camera support first automated cmake build
2020-10-12 23:56:00 +03:00
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Initial Commit
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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Initial Commit
2020-05-09 19:11:30 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Update IDF, tools and toolchains
2020-08-24 19:10:52 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
          Xthal_hw_release_nameXthal_hw_configid0Xthal_hw_configid1Xthal_mmu_ca_bits_miscXthal_have_ccount/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/esp32s2/trax_init.cGNU C99 8.2.0 -mlongcalls -ggdb -O2 -std=gnu99 -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fstack-protector_lock_tXthal_cp_mask_XCHAL_CP2_IDENT_on_exit_args_writeXthal_num_xlmi_wctomb_stateXthal_instrom_sizeXthal_dtlb_ways_r48Xthal_dcache_linewidthXthal_cp_namesXthal_debug_configured_signal_bufunsigned intXthal_cp_maxXthal_num_interruptsXthal_dtlb_way_bits_lbfsize_flagsXthal_mmu_ringsXthal_release_internalXthal_cp_id_XCHAL_CP7_IDENT_errnoesp_log_timestampXthal_cpregs_sizeTRAX_ENA_PRO_APP_SWAPXthal_have_spanning_wayESP_LOG_DEBUGXthal_inttypeXthal_cpregs_save_fn__sf_fake_stdout_LOCK_RECURSIVE_TXthal_have_highlevel_interruptsXthal_num_intlevels_read_mbrlen_stateXthal_cp_id_XCHAL_CP0_IDENTXthal_have_mimic_cacheattrxthal_MPU_entry_stdoutXthal_cpregs_align_fpos_tXthal_mmu_max_pte_page_size_fnsXthal_icache_line_lockable_cookie_Bigint__tm_wdayXthal_cpregs_save_nw_fn_resultuint32_tXthal_cp_mask_XCHAL_CP4_IDENT__tm_hourXthal_intlevel_maskXthal_have_tlbsXthal_icache_linewidthXthal_hw_release_major__countXthal_num_aregs__tm_min/Users/ficeto/Desktop/ESP32/ESP32S2/esp32-arduino-lib-builder/build__sfXthal_instram_vaddr_rand48_result_klong long unsigned int_asctime_bufXthal_num_ccompare__sFILE_wdsXthal_mmu_sr_bitsXthal_memory_order__FILEXthal_instrom_vaddrXthal_cp_id_XCHAL_CP2_IDENT_offsetXthal_xlmi_sizeXthal_cp_mask_XCHAL_CP6_IDENTXthal_have_sextXthal_have_minmaxXthal_num_datarom_emergencyXthal_have_booleansXthal_dtlb_arf_waysXthal_num_instromXthal_have_mac16Xthal_tram_syncXthal_instram_paddr__tm_secXthal_dcache_sizesuboptarg__tm_yday_inc_indXthal_cp_id_XCHAL_CP5_IDENT_next_mbsrtowcs_stateXthal_itlb_way_bitsXthal_instrom_paddrXthal_icache_setwidthESP_LOG_NONEXthal_have_fpXthal_num_dataramXthal_num_instram__valueXthal_have_windowed_p5sXthal_xea_versionXthal_have_identity_map_wcsrtombs_state_mblen_stateXthal_hw_release_minorchar__tm_mdayXthal_have_mul16_sig_func_mbrtowc_stateXthal_intlevelXthal_have_nmi_flock_tXthal_tram_pending__wch_iobsXthal_release_name_on_exit_args_ptrXthal_extra_size_close__sdidinit__sFILE_fakeXthal_cpregs_restore_fnXthal_excm_level_stdin_gamma_signgamlong long inttrax_ena_select_tXthal_have_cacheattrXthal_extra_align_baseXthal_build_unique_id_freelist_mult__ULongXthal_instram_size_wcrtomb_stateXthal_icache_sizeXthal_rev_no_fileexc_cause_tableXthal_dataram_vaddrXthal_cp_id_XCHAL_CP6_IDENTXthal_mmu_ring_bits__cleanup_mbstate_tXthal_have_xlt_cacheattr_mprecXthal_num_writebuffer_entriesXthal_num_ibreakXthal_cpregs_restore_nw_fn__tm_isdstESP_LOG_INFOesp_log_writeXthal_release_majorXthal_cp_id_XCHAL_CP4_IDENTXthal_cp_mask_XCHAL_CP3_IDENTXthal_icache_waysXthal_intlevel_andbelow_maskwhich__tm_monXthal_dataram_paddrTRAX_ENA_APP_atexit0Xthal_dcache_setwidthXthal_dcache_line_lockableXthal_mpu_bgmap_atexit_mbstateXthal_have_densityXthal_mmu_asid_bitsshort intXthal_datarom_vaddrXthal_all_extra_sizelong intXthal_have_loopsXthal_dcache_linesizeXthal_datarom_size_signTRAX_ENA_PROXthal_cp_id_XCHAL_CP1_IDENT_data__wchb_global_impure_ptr__tm_year_misc_reentXthal_inttype_maskXthal_itlb_arf_waysESP_LOG_ERROR_localtime_buf_cvtlen_maxwds_l64a_bufXthal_have_clampsXthal_datarom_paddr_blksize__tmXthal_cp_numXthal_num_aregs_log2TRAX_ENA_PRO_APP_lockXthal_dcache_is_writebackXthal_release_minorlong unsigned intXthal_dataram_sizeESP_LOG_VERBOSE_niobswint_tXthal_icache_linesize_dso_handleXthal_timer_interruptXthal_have_nsaXthal_itlb_ways_cvtbufunsigned charESP_LOG_WARN__uint32_tXthal_cp_id_XCHAL_CP3_IDENT_getdate_errXthal_dcache_waysXthal_cp_mask_XCHAL_CP7_IDENTXthal_xlmi_vaddr_addXthal_have_interrupts__sbufXthal_have_speculati
Initial Commit
2020-05-09 19:11:30 +03:00
ABI=0
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Add camera support first automated cmake build
2020-10-12 23:56:00 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
<04>F <0B>
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00

Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
<13>wjTNw<01>7
Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
<00>
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
<00>
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
<12>v<01><00>
Initial Commit
2020-05-09 19:11:30 +03:00
<00>
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
<13>vjTNv<01><00>
Initial Commit
2020-05-09 19:11:30 +03:00
<00>
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
ABI=0
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00

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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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