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arduino-esp32/tools/sdk/esp32s2/lib/libesp_gdbstub.a

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Initial Commit
2020-05-09 19:11:30 +03:00
!<arch>
Update IDF and Tools
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/ 1602592719 0 0 0 438 `
ddw<>w<>w<>w<>w<>w<>w<>w<><00><><00><><00><><00><>~<7E>~<7E>esp_gdbstub_handle_commandesp_gdbstub_panic_handleresp_gdbstub_send_startesp_gdbstub_send_charesp_gdbstub_send_stresp_gdbstub_send_hexesp_gdbstub_send_endesp_gdbstub_send_str_packetesp_gdbstub_gethexesp_gdbstub_read_commandesp_gdbstub_target_initesp_gdbstub_getcharesp_gdbstub_putcharesp_gdbstub_readmemesp_gdbstub_frame_to_regfileesp_gdbstub_get_signal// 46 `
Initial Commit
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gdbstub_esp32s2.c.obj/
gdbstub_xtensa.c.obj/
Update IDF and Tools
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gdbstub.c.obj/ 1602592718 501 20 100644 29972 `
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2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
ABI=0
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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Update IDF and Tools
2020-10-13 16:52:16 +03:00
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2020-10-11 19:51:11 +03:00
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2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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2020-10-11 19:51:11 +03:00
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2020-10-11 19:51:11 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00

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2020-10-13 16:52:16 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-13 16:52:16 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-09 19:11:30 +03:00
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2020-05-09 19:11:30 +03:00
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2020-08-24 19:10:52 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-09 19:11:30 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
ABI=0
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00

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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-10-13 16:52:16 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-05-09 19:11:30 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-10-11 19:51:11 +03:00
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2020-10-13 16:52:16 +03:00
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2020-10-11 19:51:11 +03:00
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2020-10-13 16:52:16 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-11 19:51:11 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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2020-05-30 03:58:15 +03:00
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2020-10-13 16:52:16 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-10-13 16:52:16 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-30 03:58:15 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Update IDF and Tools
2020-10-13 16:52:16 +03:00
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Pull latest IDF and enable TinyUSB
2020-05-30 03:58:15 +03:00
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Update IDF and Tools
2020-10-13 16:52:16 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF and Tools
2020-10-13 16:52:16 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF and Tools
2020-10-13 16:52:16 +03:00
r}|!<21><><00> {<7B>}|!<21><><00>X<00><00>S<><00>S<03><00>R<00><00>X<><00>s<00><00>X<><00>s$<00>J!!I<00><00><00><00><00><00><00><00><00><00><00><00><00>J<00><00><01> /Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_gdbstub/xtensa/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/hal/esp32s2/include/hal/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/soc/include/soc/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r3-8.4.0/xtensa-esp32s2-elf/lib/gcc/xtensa-esp32s2-elf/8.4.0/include/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r3-8.4.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/machine/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r3-8.4.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/sys/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/include/xtensa/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/esp32s2/include/xtensa/config/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/freertos/xtensa/include/freertos/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r3-8.4.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-includegdbstub_xtensa.ccpu_ll.hsoc_memory_layout.hstddef.h_default_types.hlock.h_types.hreent.h_stdint.hhal.hcore.hxtensa_context.h esp_gdbstub_arch.hstdlib.h
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF and Tools
2020-10-13 16:52:16 +03:00
 <03>  m  '   '   L    <03>~       !  Z      <03>               $     Xthal_hw_release_nameXthal_hw_configid0Xthal_hw_configid1Xthal_mmu_ca_bitstmp0tmp1tmp2_miscXthal_have_ccountesp_gdbstub_frame_to_regfileXthal_memory_orderaliased_iram_lock_tXthal_cp_mask_XCHAL_CP2_IDENTwindowbase_on_exit_args_writeXthal_num_xlmi_wctomb_stateXthal_instrom_sizeXthal_dtlb_ways_r48Xthal_dcache_linewidthXthal_cp_namesXthal_debug_configured_signal_bufunsigned intXthal_cp_maxXthal_num_interruptsXthal_dtlb_way_bits_lbfsize_flagsXthal_mmu_ringsXthal_release_internalXthal_cp_id_XCHAL_CP7_IDENT_errnoXthal_cpregs_sizeXthal_have_spanning_wayXthal_inttypeXthal_cpregs_save_fn__sf_fake_stdout_LOCK_RECURSIVE_Tsoc_memory_type_countXthal_have_highlevel_interruptsXthal_num_intlevels_readinit_regfile_mbrlen_stateXthal_cp_id_XCHAL_CP0_IDENTcpu_ll_pc_to_ptrsizeXthal_have_mimic_cacheattrxthal_MPU_entry_stdoutXthal_cpregs_align__intptr_t_fpos_tXthal_mmu_max_pte_page_size_fnsXthal_icache_line_lockable_cookieupdate_regfile_common_Bigint__tm_wdayXthal_cpregs_save_nw_fn_resultesp_gdbstub_gdb_regfile_tuint32_tXthal_cp_mask_XCHAL_CP4_IDENT__tm_hourXthal_intlevel_maskXthal_have_tlbsXthal_icache_linewidthXthal_hw_release_major__countXthal_num_aregs__tm_min/Users/ficeto/Desktop/ESP32/ESP32S2/esp32-arduino-lib-builder/build__sfXthal_instram_vaddresp_stack_ptr_in_dram_rand48_result_klong long unsigned int_asctime_bufXthal_num_ccompare__sFILE_wdsXthal_mmu_sr_bitsiram_address__FILEXthal_instrom_vaddrXthal_cp_id_XCHAL_CP2_IDENT_offsetXthal_xlmi_sizenameXthal_cp_mask_XCHAL_CP6_IDENTXthal_have_sextXthal_have_minmaxXthal_num_datarom_emergencyXthal_have_booleansXthal_dtlb_arf_waysesp_gdbstub_frame_tXthal_num_instromXthal_have_mac16Xthal_tram_syncsize_tXthal_instram_paddr__tm_secXthal_dcache_sizesuboptarg__tm_yday_inc_indsoc_memory_type_desc_tXthal_cp_id_XCHAL_CP5_IDENT_next_mbsrtowcs_stateXthal_itlb_way_bitsXthal_instrom_paddrXthal_icache_setwidthexccause_to_signalXthal_have_fpXthal_num_dataramesp_stack_ptr_is_saneXthal_num_instram__valueXthal_have_windowed_p5sXthal_xea_versionXthal_have_identity_map/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_gdbstub/xtensa/gdbstub_xtensa.c_wcsrtombs_state_mblen_stateXthal_hw_release_minorchar__tm_mdayXthal_have_mul16_sig_func_mbrtowc_stateexccauseXthal_intlevelXthal_have_nmiexit_flock_tXthal_tram_pending__wch_iobsXthal_release_name_on_exit_args_ptrXthal_extra_size_closesoc_memory_region_t__sdidinit__sFILE_fakeXthal_cpregs_restore_fnXtExcFrameXthal_excm_level_stdin_gamma_signgamlong long intXthal_have_cacheattrXthal_extra_align_baseXthal_build_unique_id_freelist_multframe__ULongXthal_instram_size_wcrtomb_statethreadptrXthal_icache_sizeXthal_rev_no_fileXthal_dataram_vaddrXthal_cp_id_XCHAL_CP6_IDENTesp_ptr_executableXthal_mmu_ring_bitsmemset__cleanup_mbstate_tXthal_have_xlt_cacheattr_mprecXthal_num_writebuffer_entriesXthal_num_ibreakXthal_cpregs_restore_nw_fn__tm_isdststartXthal_release_majorXthal_cp_id_XCHAL_CP4_IDENTXthal_cp_mask_XCHAL_CP3_IDENT_BoolXthal_icache_waysexcvaddrXthal_intlevel_andbelow_mask__tm_moncapsXthal_dataram_paddrintptr_t_atexit0Xthal_dcache_setwidthXthal_dcache_line_lockableXthal_mpu_bgmap_atexit_mbstateXthal_have_densityXthal_mmu_asid_bitsshort intesp_gdbstub_get_signalXthal_datarom_vaddrXthal_all_extra_sizelong intXthal_have_loopsXthal_dcache_linesizeXthal_datarom_size__stack_chk_fail_signXthal_cp_id_XCHAL_CP1_IDENT_data__wchb_global_impure_ptr__tm_year_misc_reentXthal_inttype_maskXthal_itlb_arf_ways_localtime_buf_cvtlen_maxwds_l64a_bufstartup_stackGNU C99 8.4.0 -mlongcalls -ggdb
Initial Commit
2020-05-09 19:11:30 +03:00
ABI=0
Update IDF and Tools
2020-10-13 16:52:16 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Update IDF and Tools
2020-10-13 16:52:16 +03:00
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