mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
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75 lines
4.4 KiB
C
75 lines
4.4 KiB
C
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#ifndef XTENSA_DEBUG_MODULE_H
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#define XTENSA_DEBUG_MODULE_H
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/*
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ERI registers / OCD offsets and field definitions
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*/
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#define ERI_DEBUG_OFFSET 0x100000
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#define ERI_TRAX_OFFSET (ERI_DEBUG_OFFSET+0)
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#define ERI_PERFMON_OFFSET (ERI_DEBUG_OFFSET+0x1000)
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#define ERI_OCDREG_OFFSET (ERI_DEBUG_OFFSET+0x2000)
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#define ERI_MISCDBG_OFFSET (ERI_DEBUG_OFFSET+0x3000)
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#define ERI_CORESIGHT_OFFSET (ERI_DEBUG_OFFSET+0x3F00)
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#define ERI_TRAX_TRAXID (ERI_TRAX_OFFSET+0x00)
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#define ERI_TRAX_TRAXCTRL (ERI_TRAX_OFFSET+0x04)
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#define ERI_TRAX_TRAXSTAT (ERI_TRAX_OFFSET+0x08)
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#define ERI_TRAX_TRAXDATA (ERI_TRAX_OFFSET+0x0C)
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#define ERI_TRAX_TRAXADDR (ERI_TRAX_OFFSET+0x10)
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#define ERI_TRAX_TRIGGERPC (ERI_TRAX_OFFSET+0x14)
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#define ERI_TRAX_PCMATCHCTRL (ERI_TRAX_OFFSET+0x18)
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#define ERI_TRAX_DELAYCNT (ERI_TRAX_OFFSET+0x1C)
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#define ERI_TRAX_MEMADDRSTART (ERI_TRAX_OFFSET+0x20)
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#define ERI_TRAX_MEMADDREND (ERI_TRAX_OFFSET+0x24)
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#define TRAXCTRL_TREN (1<<0) //Trace enable. Tracing starts on 0->1
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#define TRAXCTRL_TRSTP (1<<1) //Trace Stop. Make 1 to stop trace.
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#define TRAXCTRL_PCMEN (1<<2) //PC match enable
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#define TRAXCTRL_PTIEN (1<<4) //Processor-trigger enable
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#define TRAXCTRL_CTIEN (1<<5) //Cross-trigger enable
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#define TRAXCTRL_TMEN (1<<7) //Tracemem Enable. Always set.
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#define TRAXCTRL_CNTU (1<<9) //Post-stop-trigger countdown units; selects when DelayCount-- happens.
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//0 - every 32-bit word written to tracemem, 1 - every cpu instruction
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#define TRAXCTRL_TSEN (1<<11) //Undocumented/deprecated?
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#define TRAXCTRL_SMPER_SHIFT 12 //Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg
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#define TRAXCTRL_SMPER_MASK 0x7 //Synchronization message period
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#define TRAXCTRL_PTOWT (1<<16) //Processor Trigger Out (OCD halt) enabled when stop triggered
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#define TRAXCTRL_PTOWS (1<<17) //Processor Trigger Out (OCD halt) enabled when trace stop completes
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#define TRAXCTRL_CTOWT (1<<20) //Cross-trigger Out enabled when stop triggered
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#define TRAXCTRL_CTOWS (1<<21) //Cross-trigger Out enabled when trace stop completes
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#define TRAXCTRL_ITCTO (1<<22) //Integration mode: cross-trigger output
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#define TRAXCTRL_ITCTIA (1<<23) //Integration mode: cross-trigger ack
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#define TRAXCTRL_ITATV (1<<24) //replaces ATID when in integration mode: ATVALID output
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#define TRAXCTRL_ATID_MASK 0x7F //ARB source ID
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#define TRAXCTRL_ATID_SHIFT 24
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#define TRAXCTRL_ATEN (1<<31) //ATB interface enable
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#define TRAXSTAT_TRACT (1<<0) //Trace active flag.
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#define TRAXSTAT_TRIG (1<<1) //Trace stop trigger. Clears on TREN 1->0
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#define TRAXSTAT_PCMTG (1<<2) //Stop trigger caused by PC match. Clears on TREN 1->0
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#define TRAXSTAT_PJTR (1<<3) //JTAG transaction result. 1=err in preceding jtag transaction.
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#define TRAXSTAT_PTITG (1<<4) //Stop trigger caused by Processor Trigger Input. Clears on TREN 1->0
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#define TRAXSTAT_CTITG (1<<5) //Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0
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#define TRAXSTAT_MEMSZ_SHIFT 8 //Traceram size inducator. Usable trace ram is 2^MEMSZ bytes.
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#define TRAXSTAT_MEMSZ_MASK 0x1F
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#define TRAXSTAT_PTO (1<<16) //Processor Trigger Output: current value
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#define TRAXSTAT_CTO (1<<17) //Cross-Trigger Output: current value
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#define TRAXSTAT_ITCTOA (1<<22) //Cross-Trigger Out Ack: current value
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#define TRAXSTAT_ITCTI (1<<23) //Cross-Trigger Input: current value
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#define TRAXSTAT_ITATR (1<<24) //ATREADY Input: current value
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#define TRAXADDR_TADDR_SHIFT 0 //Trax memory address, in 32-bit words.
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#define TRAXADDR_TADDR_MASK 0x1FFFFF //Actually is only as big as the trace buffer size max addr.
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#define TRAXADDR_TWRAP_SHIFT 21 //Amount of times TADDR has overflown
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#define TRAXADDR_TWRAP_MASK 0x3FF
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#define TRAXADDR_TWSAT (1<<31) //1 if TWRAP has overflown, clear by disabling tren.
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#define PCMATCHCTRL_PCML_SHIFT 0 //Amount of lower bits to ignore in pc trigger register
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#define PCMATCHCTRL_PCML_MASK 0x1F
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#define PCMATCHCTRL_PCMS (1<<31) //PC Match Sense, 0 - match when procs PC is in-range, 1 - match when
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//out-of-range
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#endif
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