arduino-esp32/tools/sdk/esp32s2/lib/libperfmon.a

!<arch>
/               1590840352  0     0     0       328       `
o\o\<00><><00><><00><>xtensa_perfmon_initxtensa_perfmon_dumpxtensa_perfmon_resetxtensa_perfmon_startxtensa_perfmon_stopxtensa_perfmon_valuextensa_perfmon_overflowxtensa_perfmon_execxtensa_perfmon_view_cbxtensa_perfmon_select_mask_allxtensa_perfmon_masks_tablextensa_perfmon_select_table//                                              84        `
xtensa_perfmon_access.c.obj/
xtensa_perfmon_apis.c.obj/
xtensa_perfmon_masks.c.obj/
/0              1590840345  501   20    100644  27908     `
ELF



^
Dd4(87 @ @`   `6A00<30>@@<40><>"H<>f``t<>3<11><00>30f D@f <20>U<0C>0UPf <20><00><><EFBFBD><EFBFBD><00><><11><00><00><00><><EFBFBD><06><><11><00><02>"<22><1D>perfmon: PGM=%08x, INTPC=%08x
perfmon: pm%i=%08x, pmctrl%i=%08x, pmstat%i=%08x
6a<00><00><00><00>* <20><00><00><00>
<EFBFBD><02><00><00><02><00><00><><EFBFBD><EFBFBD><11><00>=
<EFBFBD><00><><EFBFBD><EFBFBD><11><00>M
<EFBFBD><00><><EFBFBD><EFBFBD><11><00><00>
<01><02><04><02> <20> <20><00><00>"<22>"<22><1D>6A<00>"<15><00><><0B><><11><00><02>"<22><1D>6A<1B><00><00><1D>6A<0B><00><00><1D>6A<00>"<12><00><><EFBFBD><EFBFBD><11><00>-
F<1D>6A<00>"<15><00><><EFBFBD><EFBFBD><11><00><07>
<02>
"<22>F|<7C><1D><00><><EFBFBD><EFBFBD>
|
Z w0!    & 
<01><00>
<06>
<08>,3<04>9K<07>K\McintcO{<07>
{b	F<04>$?<04>,W,0o<04>
c<04><11>z,,<0E><04>r<0E><07>e
{<05>!
	<09><05><0C>	<09><05>!

,1
{<05>	U

<0A><05>c
<0A><05><05>p
<05>1
<04><05><1B><07>
<04>	m
<0E>/<08>

?1<13>
_k2c
h
2c
<0A>2c
<0A>2c_x3<0B>
<04>

t
<00>
{<0E>
$7s
<0A>9	c
<0A>:	c
S;	c
T<	c
<0A>=	c

>	c
?	c
@	c
<0A>
A	c <11>
J<08>
<0A>K
<EFBFBD>
<0A>L	<09><00><12>N
t

<12>Q
t


<EFBFBD><00>{<0E><00>U

?V

Wc
<0A>X	
<0A>Y '<00><04>
  {&s<0E>uU
<0A>	vU
<0A>wc,	 <07><08>_p<07>U_r<07>c_w<07>c
.<07>	8

<07>	8_bf<07>-
%<07>c
<0A><07>2[<14><00>t
2fx
cL	}
<0B>l}
<14>"}
<1E>
cp<07>
	<09>	<07>
c|<07>
cb<07>
<16> _mp<07>
<12>$f
<07>

		(S	<07>
c,`
<07>
c0<15><07>
	<09>4<15>
<07>
	8Q
<07>
	<]<07>
	<09>@o<07>
&	D<15><07>

H<15><07>
<12>L<07>
K<00><07>
<0B><00>c<07>
2	<00><15>
<07>
	<09><00><04>}h<07>{_p<07>U_r<07>c_w<07>c
.<07>	8

<07>	8_bf<07>-
%<07>c
<0A><07>2
<0A><07>
<EFBFBD> 
<07><1D>$
<0A><07><1D>(
<07>
<0A>,
	<07>	0_ub<07>-4_up<07>U<_ur<07>c@
*<07>D
3<07>.G_lb<07>-H
<0A>
<07>cP
<0A><07>
<EFBFBD>T
<0A>
<07>a
X
<07>U
\
<0A><07>	cdc<00>2<18><18>c<04>
O<03>{c<00>2<18><18>c<04><03><04><17><00>2<18><18>c<04>c2<18>
,.{
,>{<07>
8<14>#
<08>?%
<11><15>&
c<15>'
<0B>K>-?
<08><15>@
<12><15>	A
<12><15>B
K<15>E
$<24>
K<00>{<14>
X
.$[
<13>
<\
c<15>]
<13>
<15>	^
.<04>

Pb
<08>4e
	<09>"f
U

g
U
Ah
U
p
i
<08>3j
c$k
U
(yl
U
0Em
U
8<15>	n
U
@o
U
H
<EFBFBD><00>{<19><04><04>		2<04><04><04>
&	c,		40<07>
"<22><1B><07>
"<22><1B><07>
"<22>


2g<0E><04>	<11>
<EFBFBD><00>	{'<03>	

<EFBFBD><1A>	<1C>	<0B><1B>
<EFBFBD><00>	{<1C><0B><0E>	#	<0B><0E>	<0B><0E>	<1C>
<0B><0E>	<1C><0B><1B><1C>	<0B><1B>
<EFBFBD>
{	
m<0B>
t<0B>
Q<0B><1B><1C><0B><1B>
<EFBFBD>^
{N
<1C>
<0B>^
@<0B><1B><1C>
<0B>3<1C>
<0B>3<0B><1C><1C><0B><1C><1C>
<0B>3<1C><0B>3<1C>
<0B>3<1C><0B>R<1C><0B>R<1C>	<0B><1C><1B>
<1C><1B>

3<1B>
[
j<0B>
<1C><0B>
<1C><1B><0B>
<1C>E<0B>
<1C>{<0B>
3<1B><0B>
3<0B>
3{<0B>
3<1B><0B>
3<1B><0B>
3B<0B>
32<0B>
3z
<0B>
3<1B><0B>
3^<0B>
3<1B><0B>
3<1B><0B>
3<1B><0B>
3m<0B>
3<1B>
<0B>
R<1B>	<0B>
<1C><0B>
<1C>)<0B>
<1C><1B><0B>
<1C>8<0B>
<1C><0B>
<1C><0B>
<1C><1B><0B>3<1B>
<0B>3;	<0B>3
<EFBFBD><00>{<03>]<0B><1B>n<0B><1B>
3<00>{<03><1B><0B><1C><1B><0B><1C>
<EFBFBD>
{
<03>*
<0B>
j0
{ 
<1B><0B>0
<1B>
<0B>j<1B><0B>ji<0B>3j<0B>3<0B>3<1B><0B>3<1B><0B>3<1B><0B>3<1B><0B>3<1B><0B>3<1B>{O{<1B>{<1B>(3<1B>)3T*3<1B>+3<1B>,3
<EFBFBD>7,<1B>07j17`
2737<1B>47<1B>	57=67<1B>
77<1B>87"
97<1B>:7v;7p<7=7<1B>>7~F3<1B>G3UI<1C>@J<1C><1B>L3<1B>M3<0B>3<1B><0B>3A<0B>3{
<0B>3p	<0B>3q<0B>3<0B>3W<0B>35<0B>3R
<0B>3<1B><0B>3<<0B>3<1B><0B><1C><1B><0B><1C>V<0B>3<1B><0B>3=
<0B>3<0B>3}
<0B>3<1B><0B>3\}zas<0B>at<0B><0B>\<0B>Qz
<EFBFBD><00><03><1B><0B><1E>%53j6<1C><1B>93<1B>:<1C><1B>=3<1B>><1C>A37B<1C>E35F<1C>#I39J<1C>6
M3N<1C><1B>Q3RR<1C><1E>
Nx	&
<01><>id
N'c 5
S<0E>c_!<00>"
Zr<><72>2$<1E>
E
<EFBFBD>
<01>%id
E#c<00><00> 5
J<0E><00><00>!<00>"
Zr<><72>2$#f
@
<01>T!"
Z"
[
0#<23>
;
<01><>!"
Z"
[
1N
2x	!
<01><>id
2$c<00><00>!"
Zr<><72>2$"
[
0#<23>
$w
<01>.$pgm
&<0E>

 <20>
'<0E>3
/
%%P<00>$i
*cU
Q
&,D$pm
+<12>v
t
 <20>
,<12><00>
<00>
 <20>
-<12><00>
<00>
':<00><00>"
Zr<><72>2$'J<00><00>"
Zr<><72>2$'Z<00><00>"
Zr<><72>2$!p"
Z "
[r"
\s"
]r"
^t"
_r'<00><00>"
Z'<00>"
Z!%"
Z"
[r<1E>

x	Z
<01><>id
#c<00>
<00>
(g
0<>(<28>

A<>,((f
KcUM(<28>
Zc<00><00>$pmc
<0E><00><00>'@<00>"
Zr<><72>2$"
[
0!P"
Zr<><72>2$"
[v)//

)s
s

)<29>
<00>
<0E>

%U
$>&I:;9I$>:;9I
:;9
	
:;9I


I
!I/
:;9


:;9I8
:;9

:;9I8I
:;9

:;9I8'
:;9

:;9I8
:;9I8
'I
I<
'
4:;9I?<4:;9I?<!.
?:;9'I
@<18>B
:;9I<17>B 4:;9I<17>B!<21><>


1"<22><>
<18>B#.
?:;9'
@<18>B
$4:;9I<17>B%


&

'<27><>


1
(:;9I<17>B).?<n:;9
R<00>
R<>
R"<00>
R<>"$
R$&<00>
R<>
Z"$
Z
R<00>
R<>
R<00>
R<>
R
R<00>
R<>
R!<00>
R<>'
R
Z$
\%,0<>,w
R<r
SLr
TZj
Zjo<00>PR
RRU<00>
R<>UX
RXZ<00>
R<>
SZ<00>
S<>!
T!Z<00>
T<>'
U'U<00>
U<>UX
UXZ<00>
U<>
VU<00>
V<>UX
VXZ<00>
V<>/U
VLZw!&Zw!&@<00>

<01>






/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/perfmon/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/machine/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/sys/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/lib/gcc/xtensa-esp32s2-elf/8.2.0/include/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_common/include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_rom/include/esp32s2/rom/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/include/xtensa/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/esp32s2/include/xtensa/config/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/includextensa_perfmon_access.c
_default_types.h_stdint.hlock.h_types.hstddef.hreent.hstdlib.hesp_err.hets_sys.hhal.hcore.h	eri.h
stdio.h

	
	

	
	
	
0
	
	
(
	
	
L	
$	
@	
	
	
:	
	
	
	

	
#	
	

	
	
	
v	

	
	


$

	
	

	
	

		
	
	

	
	
	
	
	
0	
	
	
	
8	
	
	
	
8	
	
	
		
	
	
-|	

	

	
	


2
	

	
	
	
	
	

	
	
	
}	

	
	


;

	


	
	


<03>

	


	
	


<03>
	

	
	
	
0	
	

	
	
}	

	
	


<03>
	

	
	
	
4	
	

		
	
	
	
z	
	
	

	
	

Xthal_hw_release_nameXthal_hw_configid0Xthal_hw_configid1Xthal_mmu_ca_bitsxtensa_perfmon_reset_miscXthal_have_ccountXthal_memory_order_lock_tXthal_cp_mask_XCHAL_CP2_IDENT_on_exit_args_writepmctrlXthal_num_xlmiGNU C99 8.2.0 -mlongcalls -ggdb -Og -std=gnu99 -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fstack-protectorXthal_instrom_sizeeri_writeXthal_dtlb_ways_r48Xthal_dcache_linewidthXthal_cp_namesXthal_debug_configuredprintf_signal_bufunsigned intXthal_cp_maxXthal_num_interruptsXthal_dtlb_way_bits_lbfsize_flagsXthal_mmu_ringsXthal_release_internal__int32_t_errnoXthal_cpregs_sizeXthal_have_spanning_wayXthal_inttypeXthal_cpregs_save_fn__sf_fake_stdout_LOCK_RECURSIVE_TXthal_have_highlevel_interruptsXthal_num_intlevels_read_mbrlen_stateXthal_cp_id_XCHAL_CP0_IDENTXthal_have_mimic_cacheattrxthal_MPU_entry_stdoutXthal_cpregs_aligntracelevelpmstat_fpos_tXthal_mmu_max_pte_page_size_fnsXthal_icache_line_lockable_cookiextensa_perfmon_start_Bigint__tm_wdayXthal_cpregs_save_nw_fn_resultuint32_tXthal_cp_mask_XCHAL_CP4_IDENT__tm_hourXthal_intlevel_maskXthal_have_tlbsXthal_icache_linewidthXthal_hw_release_major__countXthal_num_aregs__tm_min/Users/ficeto/Desktop/ESP32/ESP32S2/esp32-arduino-lib-builder/build__sfXthal_instram_vaddr_rand48result_result_klong long unsigned int_asctime_bufXthal_num_ccompare__sFILE_wdsXthal_mmu_sr_bits__uint16_t__FILEXthal_instrom_vaddrXthal_cp_id_XCHAL_CP2_IDENTintpc_offsetXthal_xlmi_sizextensa_perfmon_overflowXthal_cp_mask_XCHAL_CP6_IDENTXthal_have_sextXthal_have_minmaxXthal_num_dataromkernelcnt_emergencyXthal_have_booleansXthal_dtlb_arf_waysXthal_num_instromXthal_have_mac16Xthal_tram_syncXthal_instram_paddr__tm_secXthal_dcache_sizesuboptarg__tm_yday_inc_indXthal_cp_id_XCHAL_CP5_IDENT_next_mbsrtowcs_stateXthal_itlb_way_bitsXthal_instrom_paddrXthal_icache_setwidthXthal_have_fpXthal_num_dataramXthal_num_instram__valueXthal_have_windowed_p5sXthal_xea_versionXthal_have_identity_map_wcsrtombs_state_mblen_stateeri_readXthal_hw_release_minorchar__tm_mdayXthal_have_mul16_sig_func_mbrtowc_stateXthal_intlevelXthal_have_nmi_flock_tXthal_tram_pending__wch_iobsXthal_release_name_on_exit_args_ptrXthal_extra_size_close__sdidinit__sFILE_fakeXthal_cpregs_restore_fnXthal_excm_level_stdin_gamma_signgamlong long intXthal_have_cacheattrXthal_extra_align_baseXthal_build_unique_id_freelist_mult__ULongXthal_instram_size_wcrtomb_stateXthal_icache_sizeXthal_rev_no_fileexc_cause_tableXthal_dataram_vaddrXthal_cp_id_XCHAL_CP6_IDENTXthal_mmu_ring_bits__cleanup_mbstate_tXthal_have_xlt_cacheattr_mprecXthal_num_writebuffer_entriesXthal_num_ibreakXthal_cpregs_restore_nw_fn__tm_isdstmasklong unsigned intXthal_release_majorXthal_cp_id_XCHAL_CP4_IDENTXthal_cp_mask_XCHAL_CP3_IDENTXthal_icache_waysselectXthal_intlevel_andbelow_mask__tm_monXthal_dataram_paddruint16_t_atexit0Xthal_dcache_setwidthXthal_dcache_line_lockableXthal_mpu_bgmap_atexit_mbstateXthal_have_densityXthal_mmu_asid_bitsshort intXthal_datarom_vaddrXthal_all_extra_sizextensa_perfmon_stoplong intXthal_have_loopsXthal_dcache_linesizeXthal_datarom_size_signxtensa_perfmon_valueXthal_cp_id_XCHAL_CP1_IDENT_data__wchb_global_impure_ptr__tm_year_misc_reentXthal_inttype_maskXthal_itlb_arf_ways_localtime_buf_cvtlen_maxwds_l64a_bufXthal_have_clampsXthal_
ABI=0
8
8





(UUU"Z(**,K"w(
"!((("(""""&
<00><>!#%&(*,.
	
/013Z-7wKT[!p<00><00><00>&xtensa_perfmon_access.cxtensa_perfmon_initeri_writextensa_perfmon_dumperi_readprintfxtensa_perfmon_resetxtensa_perfmon_startxtensa_perfmon_stopxtensa_perfmon_valuextensa_perfmon_overflow
!
!


# 
#$
$(
#,
#0
#4
$
!
!
!
#
#/@RX	U::!JJ!'r,<Lg# #$$4(4#D,D#T0T#j4j$r,!!!#$$#"




!(
,,

0
49@
DD

H
LQX
\\

`
	d	i	p
tt

x

|
<00>
<00>
<00><00>

<00>
<00><00><00>
<00><00>

<00>
<00><00>




!
(
/
;
@
N
X
p
~
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
	



;

H

V

b

p

u

<00>

<00>

<00>

<00>

<00>

<00>

<00>



%
2
?
L
Y
f
t
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
.
;
H
\
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


(
6
D
R
n
|
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


$
9
j
w
<00>
<00>
<00>
<00>
<00>
<00>
<00>

 
:
G
T
a
n
<00>
?
L
Z
h
v
<00>
<00>
<00>
<00>
<00>
<00>
<00>


 
5
C
Q
_
m
{
<00>
<00>
<00>
<00>
<00>
<00>
<00>
9	
F	
S	
`	
m	
y	
<00>	
<00>	
<00>	
<00>	
<00>	
<00>	
<00>	
<00>	


+

7

C

d

p

|

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>





(
5
B
O
\
i
v
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>



,
9
F
S
`
m
z
<00>
<00>
<00>
<00>
<00>
<00>


6

C

P

]

j

w

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>



 
=
J
W
d
q
~
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>




'
4
A
N
[
h
u
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>



+
8
E
R
{
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>



,
9
F
S
`
m
z
<00>
<00><00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00><00>
<00>
<00>



&
-

1
<

U
\
	`	k
	<00>
<00>
<00><00>
<00>
<00>
<00>
<00>
<00><00>
<00>
<00>


	

%
#
(
,,;
?
D
O
S
X
c
g
l
<00>
<00>
<00>
<00>
<00>
<00>

"
/
:
>S
W
\
g
k
p
{

<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>








%
)
0
4
>
B
I
M
c
g
n
r
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>






 

3

7

>

B

U

Y

a

e

v

z

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>





,
0
7
;
U
Y
`
d
n
r
y
}
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>



 
$(
	,	0

4
8
<@
D






	
	 

$

(
,
0
4
<00>
<00>
<00>

	;

_
<00>
<00><00><00><00>	<00>	<00><00><00> !&$.'7,@/H/O4X@`@gEpPvP~R<00>U<00>X<00><00><00><00><00><00><00><00>%<00>%<00>%<00>',,1+<7<DAQL]LjQuZj<00>p<00>p<00>r<00>u<00><00><00><00><00><00><00><00><00>
$	-	1	H
Q
U
kt}<00><00><00><00><00><00><00><00><00><00><00><00><00><00>'-3;"?$



 
(
0



$
0
<
H
T
`
l
x
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


	

	 

	,


8


D


P

\

h

t

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

.symtab.strtab.shstrtab.rela.literal.xtensa_perfmon_init.rela.literal.xtensa_perfmon_dump.rela.literal.xtensa_perfmon_reset.rela.literal.xtensa_perfmon_start.rela.literal.xtensa_perfmon_stop.rela.literal.xtensa_perfmon_value.rela.literal.xtensa_perfmon_overflow.text.data.bss.rela.text.xtensa_perfmon_init.rodata.xtensa_perfmon_dump.str1.4.rela.text.xtensa_perfmon_dump.rela.text.xtensa_perfmon_reset.rela.text.xtensa_perfmon_start.rela.text.xtensa_perfmon_stop.rela.text.xtensa_perfmon_value.rela.text.xtensa_perfmon_overflow.rela.debug_frame.rela.debug_info.debug_abbrev.rela.debug_loc.rela.debug_aranges.rela.debug_ranges.rela.debug_line.debug_str.comment.xtensa.info.rela.xt.lit.rela.xt.prop 
4@p>5
B
H8=@<00>>l5d
<00>_@<00>>5<00>
<00><00>@?5<00>
<00><00>@?5	<00>
<00><00>@?5<00>
<00><00>@$?5


<00>


<00>

<00>
&

<00>Z!
@0?l5@

2
R
h

X
wc
@<00>?
5<00>

<00>
!<00>
@<00>@<5<00>

<00>
<00>
@<00>@$5<00>

<00>
@A$5<00>

<00>
@4A<5
4&
@pAT5)
\<00>$@<00>A<00>
5!;

6@tC|5#G
0Q
Z
<00><00>
U@<00>T5&j
gP
e@<00>X<00>5(~
<00>@
y@<00>Y<00>5*<00>
<00>D
<00>@TZ<00>5,<00>
0;&W

<00>
0<00>8&

<00><00>88
<00>
<00>88
<00>@4_T51<00>
(9<00>

<00>@<00>_<00>
53
;<00>6 	<00>=<00>
ha<00>
/29             1590840345  501   20    100644  28732     `
ELF



^
tj4(%$@<00><>0perfmonE (%d) %s: Parameter call_function must be defined.
E (%d) %s: Parameter callback must be defined.
6a82<38>Ӂ<00><00><00><0B>
<EFBFBD><00><>
<01><00>"<22>FO8BVc<12><00><00><00><0B>
<EFBFBD><00><>
<01><00>"<22>FF<00><00><00>b<EFBFBD>NF<13><03><0B><0B><00>h<><68>1Љ<11>f<EFBFBD>b<EFBFBD><03><02><1A><00><00><00>82<38>"<22><00><00><00><><00><00><00>: <20><>
<01><00><00><00>m
<EFBFBD><02><00><00>
<EFBFBD><06><00><00>
<EFBFBD><05><00>]
h!g<>
9!7<>
}D<>Q}|<7C>9!87<><06><>H!@<40><><EFBFBD><00>=
H<12><07><00><00><04><00><00>
<EFBFBD><03><00><00>:HB8<42>h1<68>vzcKwz3<7A><05><00><00>
<EFBFBD><03><06>R<EFBFBD>81391<39>I18rh176<37>F|<7C><1D>Value = %9i, select = %2i, mask = %04x.  %s.
                  %s
6AVr<00><00>(*7<>І<11><00><><EFBFBD><18><04><03><05><00><02><00>fІ<11><00><><EFBFBD>f<08><05>
7<>#<23>eZf<5A><66>a<00>fhGa<00>f<EFBFBD>&<26><00><02><00>U<><55>Z<><5A>h<11>j<>hf<06><1D><00><><EFBFBD><EFBFBD>
|
f
0<00> <00>
<01><0C>hHX<02>1<07>
1[=intI
:
s\<05>
XMI<02>O1U
<07><02>
I<11><05>
<02>,<0E><02>r<0E><06>e
1<05><03><08>	<05><0C>l<05><13>	\

1<05>	/
A<05>I<0C><05><05>o<05>
<02>	<05><1B>
<07>V

)	V
<02>
I
D/<08>
<0C>1<13>
_k2I<0C>2I/2I2I_x3<0B>
n
	b
<00>

1N$7as9	I_:	I<0C>;	I.	<	I<0C>=	I<0C>>	IL?	I<0C>@	I<0C>A	I <11>
J<08>2K
<EFBFBD>L	<09><00><12>N
b

<12>Q
b

	G
<00>
1Q
<00>U<08><0C>V<12><0C>WIX	<09><0C>	Y <00><04>	
1acuC<0C>
vC<0C>wI\<0F>	 <06><08>_p<06>C_r<06>I_w<06>I*<06>	h<06>	h_bf<06>!<06>If<06> IT<00>t
 ~x
I?
}
f<15>}
f<15>}
f<15>
I<15><06>
	P
<15>	<06>
I5<06>
I<06>
<16> _mp<06>
<12>$e<06>

<EFBFBD>(F
<06>
I,<15><06>
I0k<06>
	P
4t
<06>
<13>8<15><06>
<10><<15><06>
	P
@I	<06>
	DQ
<06>
<13>H
<06>
<12>L<15><06>
'<00><15><06>
f<00>U<06>
	<00><15>
<06>
	P
<00><04>h<06>i_p<06>C_r<06>I_w<06>I*<06>	h<06>	h_bf<06>!<06>If<06> '<06>
G
 T<06><1D>$<0C><06><1D>(<0C><06>
<0A>,<0C>	<06>	<09>0_ub<06>4_up<06>C<_ur<06>I@<0C><06><11>D<0C><06>
G_lb<06>HE<06>IPu<06>
<EFBFBD>Tu<06>;
XY
<06>/
\p<06>	IdI<00> G
P
IiI<00> G
<18>I]
<04><04><17><00> G
<18>I<04>I<00> G
<04>	\

1	\
1>
&<14>#
`<15>%
`<15>&
I<15>	'
f'<14>?
<08><15>@
<12><15>
A
<12>"B
=<15>E
$<24>	=<00>
1<14>X

<15>[
<13>
<15>\
I<15>]
<13>
<15>
^

<04>
<14>Pb
<08><15>e
	P
	f
/
<15>g
/
<15>h
/
<15>i
<08><15>j
I$hk
/
(S	l
/
0<15>m
/
8<15>
n
/
@<15>o
/
H	V
<00>
1<19><04><04><1A> <04>l<04>
	I	<04><06>
"<22><1B><06>
"<22>N<06>
"<22>s
 <1C>gP
,o<02>0{`	y	B'
T	<04>	<1A>	G
	<09><00>	
1'<04>	<0B><1A>	1#<0E>	5<1E>
<1E><1E><1E><1E><1C>
<0C>8	G



1<1C><0C><0E>	
<0C><0E>	l<0C><0E>	<1C><0C><0E>	<1C>	<0C>8x
<0C>8	8b

1R
<1C><0C>b
<1C><0C>b
<1C>
<0C>8x<0C>8	<09><00>

1<04>
<1C>
<0C><1B>
<0C>8S<0C>c<1C>
<0C>c<1C><0C>8I<0C>8`<0C>c<1C><0C>cy
<0C>c<0C>D<0C>D<1C>
<0C>8|
8{
c<1B>
[
Pf<0C>
8<1B><0C>
8<1B>	<0C>
<1C>A<0C>
<1C>m<0C>
c<1B><0C>
ci
<0C>
c<1B><0C>
c<1B>
<0C>
c@<0C>
c<1B><0C>
c<1B><0C>
c<0C>
c7<0C>
c8	<0C>
cO<0C>
cj<0C>
c<1B><0C>
c&<0C>
c<1B><0C>
D<1B>
<0C>
8<0C>
8)<0C>
8*<0C>
8	<0C>
8<0C>
<1C><1B><0C>
<1C>@<0C>c<1B>
<0C>c.
<0C>c	8<00>
1<04><1B><0C><1B><1B><0C><1B>	c(
1
n	<0C>(
<1B><0C>(
	8W
1
G
<1B><0C>W
	Py
1i
*<0C>y
<1B><0C>P_<0C>P[<0C>c<0C>c<1B><0C>c<1B><0C>c<1B><0C>c1<0C>c <0C>c}	<0C>c<1B>	1<1B>1H1%(c<1B>)c<1B>*c]+c<1B>,c	8<00>uE0<1C>1<1C>Q
2<1C><1B>3<1C>_4<1C><1B>
5<1C><1B>
6<1C>7<1C>8<1C>!9<1C><1B>:<1C><1B>;<1C><<1C><1B>=<1C>}><1C>Fc
Gc<1B>I8<1B>J8Lc&
Mc<1B><0C>c<1B><0C>c<1B><0C>cz<0C>cc
<0C>c<1B><0C>c|
<0C>c<0C>c1<0C>cQ<0C>c"<0C>c<<0C>c<1B><0C>8<1B><0C>8<1B><0C>c[<0C>c<1B><0C>c<0C>cd
<0C>c<0C>c<14>}<10>as`	at<0C>`	<06><0C><03><04>	<09><00><04>A
<0C><1E>v
5c
68J
9cn
:8Y
=c<1B>
>8<1B>
Ac<1B>
B8z
Ec<1B>
F8<1B>
Ic<1B>
J85
Mc<1B>
N8G
Qc<1B>
R8<10><0C> 	I<0C>
!<11>o"<03><04><0F>
)0<0C>*	I+	I<0C>
,<11>b-<03>0	<09>LA<1C>7&L	<h]<1C>>%h	l	<00>
1<00>y<1C>E<17>V$B 	IF!b	"G
<0C>#<0C>	<0C>$><0C>%G
<0C>&	IZ)`	O*D Y>G
`	`	`	$l	<02>+<03>J TAG
<14>!<21>

F<00>
<01>j"N
F#G
#<23>
F4`	
S#
FE`	
T"<22>
FT`	)%$<24>
HjLJ%3 &i
NIc_'2y(
Zr(
[(
\u(
]s(
^t%AC`&i
SI<00><00>'py(
Zr(
[0(
\v)<00>q	*<2A>
}	f

<01>s"b

>s<00><00>+<2B>
}	,&n
 %

-$<24>
!`	e
_
$
"`	<00>
<00>
$	

#<00>
<00>
$4
;`	<00>
<00>
,0<00>&i
%%A=.L<00>$<24>
(Ic_&p0
0`	<00><00>&p1
1`	<00><00>)R<00>/m<00><00>(
Z
0(
[
0(
\
<EFBFBD><EFBFBD>(
]s/<2F><00><00>(
Z
1(
]s)<29><00>0<>s)<29><00>/<2F><00><00>(
Z
0'<27><00>(
Z
10I
t)
<00>/ <00>?(
Z
1(
[(
\(
^)1<00>'D<00>(
Z
1(
[(
\@(
^V1<><00>	<09>2<><00>1<>
<00>
N111-1//E155\
1<EFBFBD><00>[
1XX~

%U
:;9I$>&I$>:;9I
:;9

:;9I	

I

!I/
:;9

:;9I8
I
:;9

:;9I8
:;9

:;9I8'
:;9

:;9I8
:;9I8
'I
I<
'
4:;9I?<4:;9I?<
>I:;9
(! 4:;9I!.
?:;9'
@<18>B
":;9I<17>B#:;9I$4:;9I<17>B%


&4:;9I<17>B'<27><>


1(<28><>
<18>B)<29><>

1*.
?:;9'I
@<18>B
+4:;9I,
U
-
U.

/<2F><>


1
0<><30>

<01>B1.?<n:;92.?<n:;9
R<00><00>
R<>C
UC<00><00>
U<><00>
R0<>I
VI<00>
U#
R#&<00>
R<>&G
RGL<00>
R<>L_

R_
b
<00>
R<>b
d

Rd
f
<00>
R<>L<00><00>\<5C><00>
V<>O
<00>\O
R

SV
d
<00>\L<00><00>X<EFBFBD>R
<00>Xb
d
<00>XL<00>
W<>0

Wb
d

WL<00>
U<>R

Ub
d

U
<00>
w<00>X<1C>


Z
0
w<00>X<1C>b
d
w<00>X<1C>L<00>
T<><00>
T
R^0<>^<00>
S<00><00>
S<00><00>
Z$f
<00>L]
_
d
LI
b
d
L<00><00><00>f
<00><00>	C

<01>






/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/perfmon/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/lib/gcc/xtensa-esp32s2-elf/8.2.0/include/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/machine/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/sys/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_common/include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_rom/include/esp32s2/rom/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/include/xtensa/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/esp32s2/include/xtensa/config/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/perfmon/include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/log/includextensa_perfmon_apis.c
stddef.h_default_types.hlock.h_types.hreent.hstdlib.h_stdint.hstdio.hesp_err.hets_sys.hhal.hcore.h	xtensa_perfmon_masks.h
xtensa_perfmon_apis.h
xtensa_perfmon_access.h
esp_log.h

	

	

	
	
	
	
	
	
	
	
	

	
	
	
	
	
	
	
	
	
	
	
	

	
	
	

		

	
	
	
	
~	
3	


	

	
7	

	

	

	
	

	

	

	
	


	
	


		
	
	
'	
	


	
	

	

	
	

	

	
	
7l	
	
	
~	
	
	
&
	
	
	
	
	
	
	
	
	
*	
"	
	

	

	

	
J	
	
j	

	
4`	
	
	
"
	

	
#	
	
{	
	

	
	


<03>
	

	

	
	
		
	
	
	

	
	
	
	
	
	


	
D~	
4
	

	

	
	
	
	
	
_
	
>
	


	
C~	
3
	

	

	
	

Xthal_hw_release_nameXthal_hw_configid0Xthal_hw_configid1Xthal_mmu_ca_bitsparams_miscXthal_have_ccountXthal_memory_order_lock_tXthal_cp_mask_XCHAL_CP2_IDENT_on_exit_argsvalue_writeXthal_num_xlmiGNU C99 8.2.0 -mlongcalls -ggdb -Og -std=gnu99 -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fstack-protectorXthal_instrom_sizeXthal_dtlb_ways_r48Xthal_dcache_linewidthXthal_cp_namesXthal_debug_configured_signal_bufunsigned intXthal_cp_maxxtensa_perfmon_view_cbXthal_num_interruptsXthal_dtlb_way_bitsmask_lbfsize_flagsXthal_mmu_ringsXthal_release_internal__int32_txtensa_perfmon_masks_tFILE_errnoesp_log_timestampXthal_cpregs_sizeXthal_have_spanning_wayESP_LOG_DEBUG__getreentXthal_inttypeXthal_cpregs_save_fn__sf_fake_stdout_LOCK_RECURSIVE_TXthal_have_highlevel_interruptsXthal_num_intlevels_readcounters_size_mbrlen_stateXthal_cp_id_XCHAL_CP0_IDENTXthal_have_mimic_cacheattrxthal_MPU_entry_stdoutXthal_cpregs_aligntracelevel_fpos_tXthal_mmu_max_pte_page_size_fnsXthal_icache_line_lockable_cookiextensa_perfmon_start_Bigint__tm_wdayxtensa_perfmon_configXthal_cpregs_save_nw_fn_resultxtensa_perfmon_select_tableuint32_tXthal_cp_mask_XCHAL_CP4_IDENT__tm_hourXthal_intlevel_maskXthal_have_tlbsXthal_icache_linewidthxtensa_perfmon_selectXthal_hw_release_major__countXthal_num_aregsfloat__tm_min/Users/ficeto/Desktop/ESP32/ESP32S2/esp32-arduino-lib-builder/build__sfXthal_instram_vaddr_rand48result_result_klong long unsigned int_asctime_bufXthal_num_ccompare__sFILE_wdsXthal_mmu_sr_bitscall_diff__FILEXthal_instrom_vaddrXthal_cp_id_XCHAL_CP2_IDENT_offsetXthal_xlmi_sizecall_minXthal_cp_mask_XCHAL_CP6_IDENTXthal_have_sextXthal_have_minmaxXthal_num_dataromkernelcnt_emergencyXthal_have_booleansXthal_dtlb_arf_waysXthal_num_instromXthal_have_mac16Xthal_tram_syncsize_tXthal_instram_paddr__tm_secXthal_dcache_sizesuboptarg__tm_yday_inc_indXthal_cp_id_XCHAL_CP5_IDENT_next_mbsrtowcs_statextensa_perfmon_config_tXthal_itlb_way_bitsXthal_instrom_paddrXthal_icache_setwidthESP_LOG_NONErepeat_countXthal_have_fpXthal_num_dataramxtensa_perfmon_select_tXthal_num_instram__valueXthal_have_windowed_p5sXthal_xea_versionXthal_have_identity_mapcallback_params_wcsrtombs_state_mblen_stateXthal_hw_release_minorchar__tm_mdayXthal_have_mul16_sig_func_mbrtowc_statecall_paramsXthal_intlevelXthal_have_nmi_flock_tXthal_tram_pending__wch_iobsXthal_release_name_on_exit_args_ptrXthal_extra_size_close__sdidinit__sFILE_fakeresult_valueXthal_cpregs_restore_fnXthal_excm_level_stdin_gamma_signgamlong long intXthal_have_cacheattrXthal_extra_align_basedescriptionXthal_build_unique_id_freelist_mult__ULongXthal_instram_size_wcrtomb_stateXthal_icache_sizeXthal_rev_no_fileexc_cause_tableXthal_dataram_vaddrXthal_cp_id_XCHAL_CP6_IDENTXthal_mmu_ring_bits__cleanup_mbstate_tXthal_have_xlt_cacheattr_mprecXthal_num_writebuffer_entriesXthal_num_ibreakXthal_cpregs_restore_nw_fn__tm_isdstESP_LOG_INFO/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/perfmon/xtensa_perfmon_apis.cesp_log_writeXthal_release_majorXthal_cp_id_XCHAL_CP4_IDENTXthal_cp_mask_XCHAL_CP3_IDENTXthal_icache_waysselectXthal_intlevel_andbelow_mask__tm_monXthal_dataram_paddr_atexit0Xthal_dcache_setwidthXthal_dcache_line_lockableXthal_mpu_bgmap_atexit_mbstateconfigXthal_have_densityXthal_mmu_asid_bitsshort intxtensa_perfmon_masksXthal_datarom_vaddrXthal_all_extra_sizextensa_perfmon_stoplong intXthal_have_loopsXthal_dcache_linesizeXthal_datarom_size_signxtensa_perfmon_valueXthal_cp_id_XCHAL_CP1_IDENT_data__wchb_global_impure_ptr__tm_yearfprintf_misc_reentXthal_inttype_maskXthal_itlb_arf_waysESP_LOG_ERROR_localtime_buf_cvtlen_maxwds_l64a_bufcall_maxXthal_have_clampsXthal_datarom_paddrxtensa_perfmon_init_blksize__tmXthal_cp_numXthal_num_aregs_log2_lockXthal_dcache_i
ABI=0
dd

(&&&$"JL"\\<00>"<00>
"<00>
<00>j"R
R
"b
b
f
(
"2"FI'"p"<00>
<00><>	
 %1:CLTaf
	u<00><00><00><00><00><00>

<00>5
@
xtensa_perfmon_apis.c__floatunsisf__floatsisf__divsf3__addsf3__mulsf3__gtsf2__fixunssfsixtensa_perfmon_execesp_log_timestampesp_log_writextensa_perfmon_stopxtensa_perfmon_initxtensa_perfmon_startxtensa_perfmon_valuextensa_perfmon_select_tablextensa_perfmon_masks_tablextensa_perfmon_view_cb__getreentfprintf




 
 
 $
!(
",
"0
#4
!8
$<
$@
D
H
L
P
T
X
\
`

%

&

(
)
)
#d
18Gd
Y^`<00><00><00>O
V
_
d
& (R
++> > L$L!T\g(g"<00>,<00>"<00>0<00>#<00>4<00>!<00>8<00>$<00><<00>$<00>@<00><00>D<00><00>H<00><00>L<00><00><00><00><00><00><00><00>L
P

T

X

\
$
b
8
`8
Z
<00>4'7CrT^ez(2,,)>Ip[pjj)<00>I		
	
!(	,,
	0
49




!
&
4
@
X
_
k
p
|
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


"

0

<

L

Y

c

o

|

<00>

<00>

<00>

<00>

<00>

<00>



 
-
:
G
T
b
p
}
<00>
<00>
<00>
<00>
<00>
<00>
<00>

)
6
J
{
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


$
2
@
\
j
x
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


'
X
e

<00>
<00>
<00>
<00>
<00>
<00>



(
5
B
O
\

(
6
D
R
m
{
<00>
<00>
<00>
<00>
<00>
<00>
<00>



#

/

;

G

h

t

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>






%
1
=
J
W
d
q
~
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>




'
4
A
N
[
h
u
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


.

;

]



<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>





(
5
B
O
\
i
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


"
/
<
I
V
c
p
}
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


&
3
@
M
Z
g
t
<00>
<00>
<00>
<00>
<00>
<00>




'
4
A
N
[
h
u
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
	

#
1
R
n
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


 
K
h
o
s~
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00><00>
<00>
<00>

!
%A7
;
@
S
a
q
|
<00><00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>





.
2
7
;L@
K
O
^
b
q
u
z
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
	

(
1
:
@
I
[
d
m
z
~
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>




)
-
4
8
L
P
c
g
o
s
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>





!

)

-

4

8

@

D

K

O

e

i

q

u

}

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>





$
(
A
E
L
P
c
g
o
s
<00>
<00>
<00>
<00>










 
$
0
4
8
<
H
L
P
T
R
<00>
]flu}<00><00><00><00><00><00><00> <00> <00>#<00>&<00>&<00>(+++"+,+9DCDLGRLXRaRiRqTyW<00>\<00>^<00>m<00>o<00>v<00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00>!<00>*<00>3<00>;<00>H<00>R<00>_<00>i<00>q<00>y<00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00><00>
<00>
<00>
<00>

<00>
<00>'
'
)
+
'0
32
?6
II
QO
]R
iV
qX
w]
_
<00>b
<00>d
<00>d
<00><00><00><00><00><00><00><00><00><00><00>	
		#	/	2;	4C	>I	AR	C[	Ig	Is	L|	[<00>	^<00>	p<00>	r<00>	<00><00>	<00>




$
0
<
H
T
`
l
x
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>




 

,

8

.symtab.strtab.shstrtab.rela.literal.xtensa_perfmon_exec.rela.literal.xtensa_perfmon_view_cb.text.data.bss.rodata.xtensa_perfmon_exec.str1.4.rela.text.xtensa_perfmon_exec.rodata.xtensa_perfmon_view_cb.str1.4.rela.text.xtensa_perfmon_view_cb.rela.debug_frame.rela.debug_info.debug_abbrev.rela.debug_loc.rela.debug_aranges.rela.debug_ranges.rela.debug_line.debug_str.comment.xtensa.info.rela.xt.lit.rela.xt.prop 
4d@<00>C
"
B
<00>=@<00>DT"b
<00>
h
<00>
n<00>
s
2<00>p
<00>
$
f
<00>@PE<00>"	<00>
2<00>F
<00>
<00><00><00>@,H<00>"

\@<00>@(I<00>"

<00><00>

@<00>I8" 

w<00>
3

;<00>
.
@<00>\<00>"C

<00>(
>
@<00>`<"W

 `
R
@<00>`<00>"j

o <00>	
e
@<00>a<00>"v

0!*+

<00>

0L>&

<00>
r>8
<00>

<00>>
<00>
@dg"<00>

<00>>D

<00>
@|gD
" 
@<00>#	<00>BH

<00>h<00>

/56             1590840345  501   20    100644  18688     `
ELF



^
@E4(



 @<00>
<00><00><> @<00>

 @<00>

 @<00>

 @<00>


	
			

















 


 

 @<00>
 @Amount of cyclesOverflow counterJX instructionsCALLXn instructionsreturn instructions (RET, RETW, ...)supervisor return instructions (RFDE, RFE, RFI, RFWO, RFWU)Conditional branch instructions where executiontransfers to the target (aka. taken branch), or loopgtz/loopnez instr where execution skips the loop (aka. not-taken loop)J instrCALLn instrConditional branch instr where execution falls through (aka. not-taken branch)Loop instr where execution falls into loop (aka. taken loop)Last inst of loop and execution transfers to LBEG (aka. loopback taken)Last inst of loop and execution falls  through to LEND (aka. loopback fallthrough)Non-branch instr (aka. non-CTI)Store buffer full stallStore buffer conflict stallData Cache-miss stall (unused)Data RAM/ROM/XLMI busy stallData inbound-PIF request stall (includes s32c1i)MHT lookup stallUncached load stall (included in MHT lookup stall below)Bank-conflict stallICache-miss stallInstruction RAM/ROM busy stallInstruction RAM inbound-PIF request stallTIE port stallExternal RunStall signal statusUncached fetch stallFastL32R stallIterative multiply stallIterative divide stallOther Pipeline Replay (i.e. excludes cache miss etc.)Level-1 interruptGreater-than-level-1 interruptDebug exceptionNMIWindow exceptionAllocate exceptionOther exceptionsHW-corrected memory errorProcessor domain PSO bubbleR hold caused by Data Cache miss(unused)R hold caused by Store releaseR hold caused by register dependencyR hold caused by MEMW, EXTW or EXCWR hold caused by Halt instruction (TX only)CTI bubble (e.g. branch delay slot)WAITI bubble i.e. a cycle spent in WaitI power down mode.ITLB HitReplay of instruction due to ITLB missHW-assisted TLB Refill completesITLB Miss ExceptionInstruction Cache HitInstruction Cache MissAll InstRAM or InstROM accessesBypass (i.e. uncached) fetchDTLB HitReplay of load/store due to DTLB missDTLB Miss ExceptionData Cache Hit(unused)Data Cache Miss(unused)Load from local memory i.e. DataRAM, DataROM, InstRAM, InstROMBypass (i.e. uncached) loadData Cache Hit (unused)Data Cache Miss (unused)Store to local memory i.e. DataRAM, InstRAMPIF StoreCache Miss0 stores and 0 loads0 stores and 1 loads1 stores and 0 loads1 stores and 1 loads0 stores and 2 loads2 stores and 0 loadsCastoutPrefetchData DMAInstruction DMAI prefetch-buffer-lookup hitD prefetch-buffer-lookup hitI prefetch-buffer-lookup missD prefetch-buffer-lookup missDirect fill to (L1) Data Cache (unused)active cycles16-bit24-bit32-bit40-bit48-bit56-bit64-bit72-bit80-bit88-bit96-bit104-bit112-bit120-bit128-bitCounts cyclesOverflow of counterSuccessfully Retired InstructionsData-related GlobalStall cyclesInstruction-related and Other GlobalStall cyclesExceptions and Pipeline ReplaysHold and Other Bubble cyclesInstruction TLB Accesses (per instruction retiring)Instruction Memory Accesses (per instruction retiring)Data TLB AccessesLoad Instruction (Data Memory)Store Instruction (Data Memory)Accesses to Data Memory (Load, Store, S32C1I, ...)Multiple Load/StoreOutbound PIFInbound PIFiDMALength of Instructions



(8Lt<00><00>
@
 `
@h
<00>t
<00><00>

<00>
4T|<00><00><00><00>  @



0
p



0
p
<00><00>0p
<00><00><00><00>
<00><00>
<00><00><00><00>
<00>
<00>
<00>
		4	L	d	 |	
<00>	<00>	
<00>	<00>	
<00>	<00>	
$
 D

l

|
<00>
<00>
<00>
<00>
 <00>
@<00>
<00><00>

<00>
<00>
<00>
<00>
<00>
 <00>
@<00>
<00><><EFBFBD><EFBFBD><00>
<00>

@`<00><00><00>	@
T
TTttt<00><00><00><00><00><00><00>	<00>
<00><><EFBFBD><EFBFBD><EFBFBD>
r	

<00>
'
(	$v	C7intC<05>
O[<07>[
H
0Ou<06><03>b<07><00>[	P<03><0E><06>	<03><0E><03><0E>6	<03><0E><03>b<06><03>bb<00>[<03><06>
<03><1B>e<03><1B><06>
<03>b&<03>bL
A
[1

X
F

<08>
Q
p
<03>A
<06>	<03>bQ
<03>+M<03>+p<03>b<06><03>bu<03>+<06><03>+<06><03>+<06><03>><06>
<03>><06>	<03>br
b<0B>

+^[
J<03>
b<03>
b<0B><03>
L
p<03>
L

<03>
+<03>
+<0B><03>
+q<03>
+2
<03>
+<0B><03>
+<03>
+:<03>
+^
<03>
+)<03>
+<0B><03>
+<0B><03>
+Z<03>
+<0B><03>
+g	<03>
+
	<03>
><0B>
<03>
bJ<03>
b]<03>
bI<03>
b<0B><03>
bH<03>
L
<0B><03>
L
<0B><03>+
<03>+9<03>+b<00>[<03>%<03><1B>o<03><1B>+<00>[<03>v<03><1C><0B><03><1C>b[
<03><0B>
<03>J*[~<03>*<0B><03>J<<03>JC<03>+<0B><03>+8
<03>+Q	<03>+<0B><03>+<0B>
<03>+<0B><03>+<03>+<0B>[K[`[<0B>(+<0B>
)+**+<0B>++,+b1&<0B>01<0B>1121<31<0B>
41x51<0B>61^71<0B>81<0B>91<0B>:1;1<0B><1q=1<0B>
>1<0B>
F+C
G+<0B>Ib<0B>Jb<0B>L+<0B>M+<0B><03>+<0B>	<03>+<0B><03>+<0B>
<03>+<0B><03>+<03>+<0B><03>+<0B><03>+<0B>	<03>+/<03>+<0B><03>+<0B><03>+<0B><03>b<0B><03>b<03>+<0B><03>+<0B><03>+<0B><03>+<03>+J<03>+
<0A>}tasuat<03>u<0F><03>Kt<07><00><03><0B><03><1E>5+V6b<0B>9+u
:bU=+<0B>>b<0B>	A+<0B>Bb<0B>E+
FbtI+
Jb<0B>M++NbY
Q+<0B>Rb<10><10><11> 	C<11>!F
^"s<03>3)<10><11>*	C<11>+	C<11>,F
<05>-<03><03><07><00><03>/7&<26><07>		<06>>%	<07>:	[<00>*	<06>E:			4?	<06>

%$>&I$>:;9I4:;9I?<

I
!I/	
I4:;9I?<!

:;9

:;9I8:;9I
:;9

:;9I84G:;9<00><00>

<01>






/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/machine/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/sys/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/include/xtensa/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/esp32s2/include/xtensa/config/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/perfmon/include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/perfmon_default_types.h
_stdint.hhal.hcore.hxtensa_perfmon_masks.hxtensa_perfmon_masks.cXthal_extra_sizeXthal_have_windowedXthal_intlevel_maskXthal_excm_levelXthal_dtlb_arf_waysXthal_debug_configuredXthal_num_aregs_log2Xthal_have_spanning_wayXthal_dcache_waysXthal_dataram_paddrXthal_have_mul16Xthal_num_ccompareselectXthal_tram_pendinglong long unsigned intGNU C99 8.2.0 -mlongcalls -ggdb -Og -std=gnu99 -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fstack-protectorXthal_num_instramXthal_dcache_linesizeXthal_build_unique_idXthal_icache_setwidthXthal_inttype_maskXthal_release_minorlong long intsigned charxtensa_perfmon_masksXthal_hw_release_nameXthal_datarom_paddrXthal_dcache_sizeXthal_mmu_ca_bitsXthal_instrom_paddrXthal_dtlb_way_bitsXthal_mmu_max_pte_page_sizeXthal_icache_linesizeXthal_num_intlevelsXthal_dataram_sizeXthal_cpregs_save_nw_fnxtensa_perfmon_select_tableXthal_tram_enabledxtensa_perfmon_select_tXthal_intlevelxtensa_perfmon_select_mask_allXthal_dcache_linewidthxtensa_perfmon_masks_tXthal_cp_id_XCHAL_CP4_IDENTXthal_rev_no__uint32_tXthal_itlb_way_bitsXthal_dtlb_waysXthal_num_dataromXthal_num_dbreakXthal_cp_maxXthal_have_speculationXthal_xlmi_paddrXthal_have_nsaunsigned intXthal_mmu_asid_bitsXthal_cp_id_XCHAL_CP1_IDENTXthal_num_ibreakXthal_itlb_waysXthal_num_aregs/Users/ficeto/Desktop/ESP32/ESP32S2/esp32-arduino-lib-builder/buildshort unsigned intXthal_cp_mask_XCHAL_CP0_IDENTXthal_cp_id_XCHAL_CP5_IDENTXthal_have_threadptrXthal_cp_id_XCHAL_CP6_IDENTXthal_datarom_sizeXthal_have_highlevel_interruptsXthal_cp_mask_XCHAL_CP2_IDENT/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/perfmon/xtensa_perfmon_masks.cXthal_intlevel_andbelow_maskXthal_mpu_bgmapXthal_cp_mask_XCHAL_CP7_IDENTXthal_inttypeXthal_have_fpXthal_num_dataramXthal_have_densityXthal_xlmi_vaddrXthal_num_xlmiXthal_have_tlbsXthal_cp_mask_XCHAL_CP6_IDENTXthal_hw_release_majorXthal_tram_syncXthal_release_internalXthal_icache_linewidthXthal_mmu_asid_kernelXthal_icache_line_lockableXthal_hw_release_minorxtensa_perfmon_selectXthal_dcache_line_lockableXthal_have_nmiXthal_all_extra_alignXthal_instram_vaddrXthal_cpregs_save_fnXthal_cpregs_alignXthal_instram_sizeXthal_extra_alignXthal_mmu_sr_bitsXthal_instrom_vaddrXthal_hw_release_internalXthal_icache_waysXthal_have_mimic_cacheattrXthal_num_writebuffer_entriesunsigned charXthal_cpregs_restore_nw_fnXthal_have_exceptionsXthal_have_pifshort intXthal_have_identity_mapXthal_mmu_ringsXthal_cp_id_XCHAL_CP3_IDENTXthal_cpregs_restore_fnXthal_num_coprocessorsXthal_icache_sizeXthal_num_interruptsXthal_cp_mask_XCHAL_CP4_IDENTXthal_have_priduint32_tXthal_cp_numXthal_have_clampsXthal_cp_namesXthal_memory_ordercharXthal_dcache_is_writebackXthal_xlmi_sizeXthal_have_xlt_cacheattrXthal_cpregs_sizeXthal_instram_paddrXthal_instrom_sizeXthal_cp_id_XCHAL_CP0_IDENTXthal_mmu_ring_bitsXthal_have_ccountXthal_cp_id_XCHAL_CP2_IDENTXthal_have_booleansXthal_dataram_vaddrmaskxthal_MPU_entryXthal_xea_versionXthal_itlb_arf_waysXthal_mmu_min_pte_page_sizeXthal_release_nameXthal_have_minmaxXthal_release_majorXthal_have_mac16Xthal_have_sextXthal_hw_configid0Xthal_hw_configid1Xthal_cp_maskXthal_timer_interruptXthal_data
ABI=0
(((
<00><>


<00>7<00>R<00>xtensa_perfmon_masks.cxtensa_perfmon_select_mask_allxtensa_perfmon_masks_tablextensa_perfmon_select_table

 
,
8
D
P
\
h
t
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>






(

4

@

L

X

d

p

|

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>




$
0
<
H
T
`
l
x
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


 
,
8
D
P
\
h
t
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>



(
4
@
L
X
d
p
|
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>



$
0
<
H
T
`
l
x
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>




$
,
4
<
D
L
T
\
d
l
t
|
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>









 

'

3

:

P

^

j

q

v

<00>

<00>

<00>

<00>

<00>

<00>

<00>










&


T


^


j


v


<00>


<00>


<00>


<00>


<00>


<00>


<00>


<00>


<00>


<00>


<00>






"

/

<

I

V

c

p

}

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>





&

3

@

M

Z

g

t

<00>

<00>

<00>

<00>

<00>

<00>



0

=

J

W

d

q

~

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>








7

D

Q

^

k

x

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>





!

.

;

H

U

b

o

|

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>





%

2

?

L

u

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>





&

3

@

M

Z

g

t

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

	

	

@	

U	
c	
q	

	


.symtab.strtab.shstrtab.text.data.bss.rodata.xtensa_perfmon_select_mask_all.rodata.str1.4.rela.rodata.xtensa_perfmon_masks_table.rela.rodata.xtensa_perfmon_select_table.rela.debug_info.debug_abbrev.rela.debug_aranges.debug_line.debug_str.comment.xtensa.info.rela.xt.prop
4
!
4
'4
,
4<00>S
2<00>

g
<00>b@<00>4<00><00>
<00><00><00>@<00>:8
<00>
<00>v	
<00>@<00>;<00>
<00>
&!<00>
<00>
"
<00>@<00>C
<00>
)"<00>
<00>
0<00>$<00>


<00>
0<00>2&


<00>28


3$

@<00>C$
03@
	p4n
D!