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https://github.com/0xFEEDC0DE64/arduino-esp32.git
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63 lines
2.3 KiB
C
63 lines
2.3 KiB
C
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/* Definitions for the xt_mmu TIE package */
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/*
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* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
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* These coded instructions, statements, and computer programs are the
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* copyrighted works and confidential proprietary information of Tensilica Inc.
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* They may not be modified, copied, reproduced, distributed, or disclosed to
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* third parties in any manner, medium, or form, in whole or in part, without
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* the prior written consent of Tensilica Inc.
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*/
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/* Do not modify. This is automatically generated.*/
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#ifndef _XTENSA_xt_mmu_HEADER
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#define _XTENSA_xt_mmu_HEADER
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#ifdef __XTENSA__
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#ifdef __XCC__
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#include <xtensa/tie/xt_core.h>
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/*
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* The following prototypes describe intrinsic functions
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* corresponding to TIE instructions. Some TIE instructions
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* may produce multiple results (designated as "out" operands
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* in the iclass section) or may have operands used as both
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* inputs and outputs (designated as "inout"). However, the C
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* and C++ languages do not provide syntax that can express
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* the in/out/inout constraints of TIE intrinsics.
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* Nevertheless, the compiler understands these constraints
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* and will check that the intrinsic functions are used
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* correctly. To improve the readability of these prototypes,
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* the "out" and "inout" parameters are marked accordingly
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* with comments.
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*/
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extern void _TIE_xt_mmu_IDTLB(unsigned ars);
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extern unsigned _TIE_xt_mmu_RDTLB1(unsigned ars);
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extern unsigned _TIE_xt_mmu_RDTLB0(unsigned ars);
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extern unsigned _TIE_xt_mmu_PDTLB(unsigned ars);
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extern void _TIE_xt_mmu_WDTLB(unsigned art, unsigned ars);
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extern void _TIE_xt_mmu_IITLB(unsigned ars);
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extern unsigned _TIE_xt_mmu_RITLB1(unsigned ars);
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extern unsigned _TIE_xt_mmu_RITLB0(unsigned ars);
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extern unsigned _TIE_xt_mmu_PITLB(unsigned ars);
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extern void _TIE_xt_mmu_WITLB(unsigned art, unsigned ars);
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#define XT_IDTLB _TIE_xt_mmu_IDTLB
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#define XT_RDTLB1 _TIE_xt_mmu_RDTLB1
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#define XT_RDTLB0 _TIE_xt_mmu_RDTLB0
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#define XT_PDTLB _TIE_xt_mmu_PDTLB
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#define XT_WDTLB _TIE_xt_mmu_WDTLB
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#define XT_IITLB _TIE_xt_mmu_IITLB
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#define XT_RITLB1 _TIE_xt_mmu_RITLB1
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#define XT_RITLB0 _TIE_xt_mmu_RITLB0
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#define XT_PITLB _TIE_xt_mmu_PITLB
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#define XT_WITLB _TIE_xt_mmu_WITLB
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#endif /* __XCC__ */
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#endif /* __XTENSA__ */
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#endif /* !_XTENSA_xt_mmu_HEADER */
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