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arduino-esp32/tools/sdk/esp32s2/lib/libcxx.a

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Initial Commit
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!<arch>
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<z<z<z<z__cxa_guard_acquire__cxa_guard_release__cxa_guard_abort__cxa_guard_dummy// 50 `
cxx_exception_stubs.cpp.obj/
cxx_guards.cpp.obj/
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Initial Commit
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Initial Commit
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Initial Commit
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Initial Commit
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Initial Commit
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-<1D>g->pending && "tried to release a guard which wasn't acquired"6A<00><00>fF 1 <0A>|<7C><> <0A><00>V<><05><00><00><00><><EFBFBD><EFBFBD><00><00><00><00><00><><EFBFBD><EFBFBD><00><00><00><00><00><><EFBFBD><EFBFBD><00> <08>B<01><><01>B<00><00> <0A><03> <0A> <0A><00><00><>F<EFBFBD><46><EFBFBD>VX<56><58><EFBFBD><EFBFBD> 2B<01>B2V<><56><EFBFBD><EFBFBD><EFBFBD><1D>!g->ready && "tried to abort a guard which is ready"g->pending && "tried to release a guard which is not acquired"6A<00><00>M
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<EFBFBD><00><00><00><>ҁ<00><1D>6A<1D>void __cxa_guard_abort(__cxxabiv1::__guard*)void __cxa_guard_release(__cxxabiv1::__guard*)void wait_for_guard_obj(guard_t*)int __cxa_guard_acquire(__cxxabiv1::__guard*)<00><>?<3F> <00><><EFBFBD><EFBFBD>| & h <00> <00>  | & ,h D<00> \<00> <00>&j<04><00>8std!e:AA0 <0B><03> <0B><03> @<03> V<03> s<03> <0B><03> <0B><03> <0B><03> <0B><03> <0B><03> <03> 0<03> b<03> <0B><03> <0B><03> <0B><03> <0B><03> <0B><03> <03> "<03> 8<03> ^<03><16><03><16><03>y<03><16><03><16><03><16><03><16><03>absN
Initial Commit
2020-05-09 19:11:30 +03:00
WLWabsJ f absFl<00>labs=CP<00>Pabs8<00><00><07>div<03>O<00><00><07><07><08>9 * \;-Q
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
b<07><01><00> <0C><07><1A>
Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
$l<08> /<08><17>1<13>1_k2D<17> 2 D<17>2D <17> 2D1_x3<0F>0<04>-<2D>.8<08>$7<08><17>9 Dz: D<17>; D<17>< D <17>= D`> Dw? D<17>@ D<17>A D 2RJ<08><17>K<1E><17>L!<21><00>31N
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Initial Commit
2020-05-09 19:11:30 +03:00
j <17><12>)<29> $<17><12>"<22> (<12>:<3A> ,<17><12>) 01_ub<12>> 41_up<12>f <1_ur<12>D@A<12> D<17><12>- G1_lb<12>> H<17><12>DP#
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
<EFBFBD>T<12> ^X<17><12>R\<17> <12> Dd8D<00> C jsD0<04> 8D<00> C j<07> D0<04><0F> 0<04> 8<><00> C j<07>D0<04> 8D C j0 -v- .8-v= .8)<29>I 5<> #<08> 6<>%<11> 6<> &D6`' <0B> 0J 0= 5<>?<08> 6@<19> 6FA<19> 6rB<12> 6<>E$<24>-<2D><00> .85<>X-6<>[<13>6<>\D6<>
Initial Commit
2020-05-09 19:11:30 +03:00
]<13>6H^- 0<04>5<>Pb<08>6<>e s6<>fR6<>gR 6shR6<>i<13>6<>jD$6<>kR(6lR06mR86<38>nR@6<>oRH-y<00>.89M0<04>0<04> :C 0<04>0<04> 0:%D0+003;<12>"<22> ;<3B><12>"<22> ;<3B> <12>"<22> ;<3B>
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
b s<00><07> ><3E>k<08><07><07>><3E>mD0<07> '><3E>s'PP<07> '0V&<07>V><3E> oD<00>P<07> '@<40><13><06>j''A_<13>D@4<13><06>8><13>l<00><07> <07>0s>O<13><06><07> <07>D>; <13>l"<07> <07>D>'<13>D8<07> ><3E>u'XsX'0]>DqDysVB<> <09><00>PPB<> P<00><07> B<> P<00><07> <07>DB<><14><00><07> <07>D>!<13>  <07> <07>&<04>B<>LW,<07> <07>' @3 <0C>4 <0C>?absJDZD6 D6 26 L6 f6 <0C>6 <0C>7 V8 s9 <0C>: <0C>< <0C>< <0C>< <0C>> <0C>@ <0C>C D 0E bG <0C>H <0C>J <0C>K <0C>L <0C>M N "P 8Q ^C'!J
Initial Commit
2020-05-09 19:11:30 +03:00
A
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
<17><0E>=<3D><17><0E>=c<17><0E>=^<17><0E>=,<17>?=h<17>?-?_.8O=+ <17>_=g<17>_=<17>?=<3D><17>?-<2D> <00>.8<0F>=&<17><1B>=<3D><17>?=<17>}=O<17>}=<3D><17>?=G<17>?=<3D><17>}=P<17>}=q<17>}=<3D> <17><1D>=U<17><1D>=d <17>?;<3B>?;:};<3B>[K;<3B><17>?;b<17>?;<3B><17><1C> ;{ <17><1C> ;<3B><17>};<17>};G<17>};<17>};U<17>};+<17>};<3B> <17>};<3B><17>};L<17>};<3B><17>};<3B><17>};<17>};<17>};<3B><17>};y<17>};f<17><1D>;<3B><17>?;<3B><17>?;n<17>?;<3B>
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Initial Commit
2020-05-09 19:11:30 +03:00
8;
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
8;8;<3B>(};<3B>)};"*};N+};<3B>,}-?}I;E0r;C1r;.2r;<3B>3r;<3B> 4r;<3B>5r;v
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<17>?;]<17>};<3B><17>};/<17>};4<17>};? <17>};<3B><17>}5<> }<10>7as o7at<17> o)<29> <17><03><0F>-<2D><00>I;X<17><1E>;<3B>5};<3B> 6?;k9};! :?;=};>?;XA};<3B>B?;<3B>E};TF?;<3B>I};AJ?;pM};<3B>N?;<3B>Q};7R?-<2D> <00>.8'<0F>=<3D><19><1A>*<t<17>=<11>  >+<?
Initial Commit
2020-05-09 19:11:30 +03:00
J<17>@
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
Z1<03>K<> <00>K1<L<><00><00><><EFBFBD>G?M@F _Tp8N__a<02>N__b<02>$Op<01><01>Pd<01><00><01><> Qpg<01>,<2C> Rg<01>!)%S<><01>QLJTS!U'! S<><01>DecV!x&<00>W[0W\ <09>W]0X5<00>&WZW[<08>W\W]Uj+<00> S<><01>DzxYp<00>%V<><00>&k W[sW\sW]sX<><00>&WZW[<08>W\W]Y <00>&VM<00>&<00> WZW[<08>W\W]Xd<00>&WZW[<08>W\W]80=0<04>-<2D>!.8,!P_<01><00><01><>"Zpg<01>.<2E> RRg<01>!<00><00>S<><01>Q<00><00>TS<00>"U&<00>!S<><01>D<00><00>V x&<00>!W[0W\ <09>W]0X5<00>&WZW[<08>W\W][ N"S<><01>D<00><00>VY<00>&+"WZW[<08>W\W]Yj<00>%Xx<00>&W[0W\0W]0Y <00>&XG<00>&WZW[<08>W\W]-<2D><00>".8.<0F>"\:xDh<01><>%Qpgx-<2D> !Rgz!FBS<>{QogTS<00>%Rret<01> D<00><00>UL%S<><01>D<00><00>]o&! !G<01> <20>#V,<00>&\#WZsV9<00>&o#WZ1VF<00>&<00>#WZ <0C><><EFBFBD>W[uXf<00>&WZs]%&<00> <0B><00><01>%^2&_<><00>`K&<00>$aL&'V<><00>&$W[sW\sW]sV<><00>&5$WZW[TW\W]V<>x&U$W[sW\uW]sV<><00>&<00>$WZW[[W\W]V<>x&<00>$W[sW\uW]sX<00>&WZW[aW\W]b<00><16>O,^9sq^-<00><00>Vtx& %W[0W\ <09>W]0X<><00>&WZW[<08>W\W]U"<00>%S<><01>D<00><00>V,<00>&<00>%W[0W\0W]0X@<00>&WZW[<08>W\W]Y <00>&Y<00>&-<2D><00>%.8-<0F>%c(p &<01>%&S]r
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Initial Commit
2020-05-09 19:11:30 +03:00
3
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
)h<><00>e h<><00> <20> i<><00><1C>h<> <00> xhO O ziZZ<1C>i..I% U9: ; 9: ;9 <0B>:: ;9 : ; 9 .?: ; 9 nI<I : ; 9  : ; 9 I?<l
Initial Commit
2020-05-09 19:11:30 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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l9: ; 9 9: ;9 <0B>9: ; 9  : ; 9  : ; 9 I8 .?: ; 9 n<cd.?: ; 9 n<d.?: ; 9 n2 <d.?: ; 9 nI2 <d.?: ; 9 nI2 <cd.?: ; 9 nI2 <d.?: ; 9 n<0E><< 4: ; 9 nI?<!.?: ; 9 nI<"9: ;9 # : ; 9 $ : ; 9 I?<%/I&$ > '$ > (;): ;9 I* : ; 9 n+ : ; 9 , : ; 9 I-I.!I/ / 0 I1 : ; 9 I8 2 : ; 9 3 : ; 9 I845 : ;9 6 : ;9 I8 7 : ;9 I8 8I9<:;4: ;9 I?<<&=4: ; 9 I?<>.?: ; 9 I<?.?: ; 9 I<@.?: ; 9 <A.?: ; 9 I<B.?: ;9 I<C9: ; D: ;9 E4GF:: ; 9 G IHB II!J4: ; 9 IK4nG L4nGM.G N: ; 9 IO.?: ; 9 @<18>BP.?: ; 9 @<18>BQ: ; 9 I<17>BR4: ; 9 I<17>BS4: ; 9 I<17>BT4I4U V<><56>1W<><57><18>BX<><58>1Y<><59>1Z: ; 9 I[ U\.?: ; 9 I@<18>B]1R<01>B X Y W ^1<17>B_ ` 1Ua41<17>Bb1R<01>B X Y W c.: ; 9 @<18>Bd.: ; 9 e f4: ; 9 Ig.: ; 9 h.?<n: ;9 i.?<n: ; 9 sRs<00><00>R<> sRs<00><00>R<> <00>t1.<2E>!,Z<00><00>Z <00>R z1.<2E><><00>z1.<2E> ,ZYiZ}<00>ZGPZx}ZfRfh<00>R<> fRfh<00>R<> z1.<2E>z1.<2E>LUz1.<2E>_dz1.<2E>@SZ_1<>bd1<>tZ<><00>Z<00>R<00><00>Z<><00>Z<><00>Z<><00>Z<>ZZ<02><00><00><02><00><00>,7Z
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R!r<01>!&R<&h<00><00><00><00><00><00><00>GYd}&h<00><00><00><00><01> /Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/cxx/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/include/c++/8.2.0/bits/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/include/c++/8.2.0/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/include/c++/8.2.0/debug/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/include/c++/8.2.0/xtensa-esp32s2-elf/no-rtti/bits/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/include/c++/8.2.0/ext/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/lib/gcc/xtensa-esp32s2-elf/8.2.0/include/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/machine/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/sys/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r2-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/include/xtensa/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/xtensa/esp32s2/include/xtensa/config/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_rom/include/esp32s2/rom/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/soc/include/soc/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/freertos/xtensa/include/freertos/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/freertos/include/freertoscxx_guards.cppstl_algobase.hcstdlibstd_abs.htype_traitsstl_pair.hdebug.hc++config.halgorithmfwd.hexception_ptr.hnewpredefined_ops.hnumeric_traits.hstddef.h_default_types.hlock.h _types.h reent.h stdlib.h
Initial Commit
2020-05-09 19:11:30 +03:00
stdlib.hcxxabi_tweaks.h_stdint.h hal.h core.h ets_sys.h soc_memory_layout.hspinlock.hportmacro.hqueue.hsemphr.hassert.h
task.h<built-in>cxxabi.h<03> 
Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00
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2020-05-09 19:11:30 +03:00
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2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00

Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00


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2020-10-11 19:51:11 +03:00
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2020-05-09 19:11:30 +03:00

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2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
2020-05-09 19:11:30 +03:00

Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
2020-10-11 19:51:11 +03:00
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Initial Commit
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Try with speed optimization as opposed to debug. Coremark 240 -> 430
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