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IDF master 3e370c4296

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* Fix build compilation due to changes in the HW_TIMER's structs

* Fix compilation warnings and errors with USB

* Update USBCDC.cpp

* Update CMakeLists.txt

* Update HWCDC.cpp
This commit is contained in:
Me No Dev
2021-10-01 17:52:29 +03:00
committed by GitHub
parent 381e88ec75
commit 00214d5c2a
1475 changed files with 88153 additions and 49503 deletions
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4
tools/sdk/esp32/include/soc/esp32/include/soc/dport_reg.h
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@ -1156,6 +1156,8 @@
#define DPORT_CPU_INTR_FROM_CPU_1_V 0x1
#define DPORT_CPU_INTR_FROM_CPU_1_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_2_REG DPORT_CPU_INTR_FROM_CPU_2_REG
#define SYSTEM_CPU_INTR_FROM_CPU_2 DPORT_CPU_INTR_FROM_CPU_2
#define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4)
/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
@ -1164,6 +1166,8 @@
#define DPORT_CPU_INTR_FROM_CPU_2_V 0x1
#define DPORT_CPU_INTR_FROM_CPU_2_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_3_REG DPORT_CPU_INTR_FROM_CPU_3_REG
#define SYSTEM_CPU_INTR_FROM_CPU_3 DPORT_CPU_INTR_FROM_CPU_3
#define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8)
/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */

2
tools/sdk/esp32/include/soc/esp32/include/soc/emac_dma_struct.h
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@ -20,7 +20,7 @@ extern "C"
#include <stdint.h>
typedef volatile struct {
typedef volatile struct emac_dma_dev_s {
union {
struct {
uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit.*/

2
tools/sdk/esp32/include/soc/esp32/include/soc/emac_ext_struct.h
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@ -19,7 +19,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct emac_ext_dev_s {
union {
struct {
uint32_t div_num : 4;

2
tools/sdk/esp32/include/soc/esp32/include/soc/emac_mac_struct.h
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@ -19,7 +19,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct emac_mac_dev_s {
union {
struct {
uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/

26
tools/sdk/esp32/include/soc/esp32/include/soc/gpio_sig_map.h
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@ -236,26 +236,8 @@
#define PWM1_CAP1_IN_IDX 113
#define PWM1_OUT2B_IDX 113
#define PWM1_CAP2_IN_IDX 114
#define PWM2_OUT1H_IDX 114
#define PWM2_FLTA_IDX 115
#define PWM2_OUT1L_IDX 115
#define PWM2_FLTB_IDX 116
#define PWM2_OUT2H_IDX 116
#define PWM2_CAP1_IN_IDX 117
#define PWM2_OUT2L_IDX 117
#define PWM2_CAP2_IN_IDX 118
#define PWM2_OUT3H_IDX 118
#define PWM2_CAP3_IN_IDX 119
#define PWM2_OUT3L_IDX 119
#define PWM3_FLTA_IDX 120
#define PWM2_OUT4H_IDX 120
#define PWM3_FLTB_IDX 121
#define PWM2_OUT4L_IDX 121
#define PWM3_CAP1_IN_IDX 122
#define PWM3_CAP2_IN_IDX 123
#define TWAI_TX_IDX 123
#define CAN_TX_IDX TWAI_TX_IDX
#define PWM3_CAP3_IN_IDX 124
#define TWAI_BUS_OFF_ON_IDX 124
#define CAN_BUS_OFF_ON_IDX TWAI_BUS_OFF_ON_IDX
#define TWAI_CLKOUT_IDX 125
@ -369,19 +351,11 @@
#define I2S1O_DATA_OUT22_IDX 188
#define I2S1O_DATA_OUT23_IDX 189
#define I2S0I_H_SYNC_IDX 190
#define PWM3_OUT1H_IDX 190
#define I2S0I_V_SYNC_IDX 191
#define PWM3_OUT1L_IDX 191
#define I2S0I_H_ENABLE_IDX 192
#define PWM3_OUT2H_IDX 192
#define I2S1I_H_SYNC_IDX 193
#define PWM3_OUT2L_IDX 193
#define I2S1I_V_SYNC_IDX 194
#define PWM3_OUT3H_IDX 194
#define I2S1I_H_ENABLE_IDX 195
#define PWM3_OUT3L_IDX 195
#define PWM3_OUT4H_IDX 196
#define PWM3_OUT4L_IDX 197
#define U2RXD_IN_IDX 198
#define U2TXD_OUT_IDX 198
#define U2CTS_IN_IDX 199

4
tools/sdk/esp32/include/soc/esp32/include/soc/i2c_struct.h
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@ -104,8 +104,8 @@ typedef volatile struct i2c_dev_s {
} fifo_conf;
union {
struct {
uint8_t data; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
uint8_t reserved[3];
uint32_t data: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
uint32_t reserved: 24;
};
uint32_t val;
} fifo_data;

6556
tools/sdk/esp32/include/soc/esp32/include/soc/mcpwm_reg.h
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File diff suppressed because it is too large Load Diff

1889
tools/sdk/esp32/include/soc/esp32/include/soc/mcpwm_struct.h
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File diff suppressed because it is too large Load Diff

2
tools/sdk/esp32/include/soc/esp32/include/soc/pcnt_struct.h
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@ -21,7 +21,7 @@ extern "C" {
#endif
typedef volatile struct pcnt_dev_s {
struct{
struct {
union {
struct {
uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/

6
tools/sdk/esp32/include/soc/esp32/include/soc/rmt_struct.h
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@ -24,7 +24,7 @@ typedef volatile struct rmt_dev_s {
uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.
Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue
and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/
struct{
struct {
union {
struct {
uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/
@ -250,9 +250,7 @@ typedef struct rmt_item32_s {
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct rmt_mem_s {
struct {
union {
rmt_item32_t data32[64];
};
rmt_item32_t data32[64];
} chan[8];
} rmt_mem_t;
extern rmt_mem_t RMTMEM;

37
tools/sdk/esp32/include/soc/esp32/include/soc/sdmmc_struct.h
View File

@ -23,18 +23,22 @@ extern "C" {
#endif
typedef struct sdmmc_desc_s {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
struct {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
};
struct {
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
};
void* buffer1_ptr;
union {
void* buffer2_ptr;
@ -146,8 +150,10 @@ typedef volatile struct sdmmc_dev_s {
uint32_t val;
} ctype;
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t : 16;
struct {
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t reserved: 16;
};
uint32_t bytcnt; ///< number of bytes to be transferred
@ -326,6 +332,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t ces: 1; ///< card error summary
uint32_t reserved2: 2;
uint32_t nis: 1; ///< normal interrupt summary
uint32_t ais: 1; ///< abnormal interrupt summary
uint32_t fbe_code: 3; ///< code of fatal bus error
uint32_t fsm: 4; ///< DMAC FSM state
uint32_t reserved3: 15;
@ -362,6 +369,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes
uint32_t reserved1 : 13;
uint32_t card_threshold : 12; ///< threshold value for reads/writes, in bytes
uint32_t reserved28: 4;
};
uint32_t val;
} cardthrctl;
@ -378,6 +386,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
uint32_t reserved21: 11;
};
uint32_t val;
} clock;

64
tools/sdk/esp32/include/soc/esp32/include/soc/soc.h
View File

@ -307,8 +307,8 @@
#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/
#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for IPC_ISR */
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for IPC_ISR */
#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/
@ -351,6 +351,60 @@
#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/
#define ETS_MAX_INTR_SOURCE 69/**< total number of interrupt sources*/
#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer Reserved Reserved
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level
* 25 4 extern level BT/BLE Controller BT/BLE Controller
* 26 5 extern level TG1_WDT & CACHEERR
* 27 3 extern level Reserved Reserved
* 28 4 extern edge
* 29 3 software BT/BLE hli BT/BLE hli
* 30 4 extern edge Reserved Reserved
* 31 5 extern level IPC_ISR IPC_ISR
*************************************************************************************************************
*/
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_CACHEERR_INUM 26
#define ETS_T1_WDT_INUM ETS_T1_WDT_CACHEERR_INUM
#define ETS_MEMACCESS_ERR_INUM ETS_T1_WDT_CACHEERR_INUM
/* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/
#define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM
#define ETS_IPC_ISR_INUM 31
#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
@ -382,7 +436,7 @@
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
* 28 4 extern edge IPC_ISR IPC_ISR
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level
@ -399,7 +453,9 @@
#define ETS_MEMACCESS_ERR_INUM 25
/* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/
#define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM
#define ETS_DPORT_INUM 28
#define ETS_IPC_ISR_INUM 28
#endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1

66
tools/sdk/esp32/include/soc/esp32/include/soc/soc_caps.h
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@ -68,7 +68,6 @@
#define SOC_SDIO_SLAVE_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_EMAC_SUPPORTED 1
#define SOC_RISCV_COPROC_SUPPORTED 0 //TODO: correct the caller and remove this line
#define SOC_CPU_CORES_NUM 2
#define SOC_ULP_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
@ -76,20 +75,33 @@
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1
/*-------------------------- ADC CAPS ----------------------------------------*/
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
#define SOC_ADC_MAX_BITWIDTH (12)
/**
* TO BE REMOVED in !14278
* Check if adc support digital controller (DMA) mode.
* @value
* - 1 : support;
* - 0 : not support;
*/
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 0)
#define SOC_ADC_SUPPORT_RTC_CTRL 1
/*!< SAR ADC Module*/
#define SOC_ADC_RTC_CTRL_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16) //Two pattern table, each contains 16 items. Each item takes 1 byte. But only support ADC1 using DMA mode
#define SOC_ADC_DIGI_MIN_BITWIDTH (9)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_MAX_BITWIDTH (12)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#if SOC_CAPS_ECO_VER >= 1
@ -117,8 +129,8 @@
// set pullup/down/capability via RTC register. On ESP32-S2, Digital IOs have their own registers to
// control pullup/down/capability, independent with RTC registers.
// 0~39 except from 20, 24, 28~31 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT20 | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
// 0~39 except from 24, 28~31 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
// GPIO >= 34 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))
@ -136,15 +148,23 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32 have 2 I2S
#define SOC_I2S_NUM (2)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_SUPPORTS_PDM_RX (1)
#define SOC_I2S_SUPPORTS_ADC (1) // ESP32 support ADC and DAC
#define SOC_I2S_SUPPORTS_DAC (1)
#define SOC_I2S_SUPPORTS_PDM (1) // ESP32 support PDM
#define SOC_I2S_SUPPORTS_ADC_DAC (1) // ESP32 support ADC and DAC
#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define SOC_I2S_SUPPORTS_APLL (1)// ESP32 support APLL
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define SOC_I2S_TRANS_SIZE_ALIGN_WORD (1) // I2S DMA transfer size must be aligned to word
#define SOC_I2S_LCD_I80_VARIANT (1) // I2S has a special LCD mode that can generate Intel 8080 TX timing
/*-------------------------- LCD CAPS ----------------------------------------*/
/* Notes: On esp32, LCD intel 8080 timing is generated by I2S peripheral */
#define SOC_LCD_I80_SUPPORTED (1) /*!< Intel 8080 LCD is supported */
#define SOC_LCD_I80_BUSES (1) /*!< Only I2S0 has LCD mode */
#define SOC_LCD_I80_BUS_WIDTH (24) /*!< Intel 8080 bus width */
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_HS_MODE (1)
@ -158,10 +178,11 @@
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_FAULT_DETECTORS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of GPIO fault signals that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_EXT_SYNCERS_PER_GROUP (3) ///< The number of external syncers that each group has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz
/*-------------------------- MPU CAPS ----------------------------------------*/
@ -173,10 +194,10 @@
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*-------------------------- PCNT CAPS ---------------------------------------*/
// ESP32 have 1 PCNT peripheral
#define SOC_PCNT_PORT_NUM (1)
#define SOC_PCNT_UNIT_NUM (8)
#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
#define SOC_PCNT_GROUPS (1)
#define SOC_PCNT_UNITS_PER_GROUP (8)
#define SOC_PCNT_CHANNELS_PER_UNIT (2)
#define SOC_PCNT_THRES_POINT_PER_UNIT (2)
/*-------------------------- RMT CAPS ----------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
@ -292,3 +313,6 @@
*/
#define SOC_SDMMC_USE_IOMUX 1
#define SOC_SDMMC_NUM_SLOTS 2
/*------------------------------ BLE --------------------------------------------*/
#define SOC_BLE_DONT_UPDATE_OWN_RPA (1)

2
tools/sdk/esp32/include/soc/esp32/include/soc/timer_group_struct.h
View File

@ -21,7 +21,7 @@ extern "C" {
#endif
typedef volatile struct timg_dev_s {
struct{
struct {
union {
struct {
uint32_t reserved0: 10;

87
tools/sdk/esp32/include/soc/esp32/include/soc/twai_struct.h
View File

@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
uint32_t stm: 1; /* MOD.2 Self Test Mode */
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
};
uint32_t val;
} mode_reg; /* Address 0 */
} mode_reg; /* Address 0x0000 */
union {
struct {
uint32_t tr: 1; /* CMR.0 Transmission Request */
@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; /* Address 1 */
} command_reg; /* Address 0x0004 */
union {
struct {
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
@ -60,23 +60,24 @@ typedef volatile struct twai_dev_s {
uint32_t ts: 1; /* SR.5 Transmit Status */
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 2 */
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_reg; /* Address 3 */
} interrupt_reg; /* Address 0x000C */
union {
struct {
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
@ -87,70 +88,70 @@ typedef volatile struct twai_dev_s {
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_enable_reg; /* Address 4 */
uint32_t reserved_05; /* Address 5 */
} interrupt_enable_reg; /* Address 0x0010 */
uint32_t reserved_14;
union {
struct {
uint32_t brp: 6; /* BTR0[5:0] Baud Rate Prescaler */
uint32_t sjw: 2; /* BTR0[7:6] Synchronization Jump Width*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_0_reg; /* Address 6 */
} bus_timing_0_reg; /* Address 0x0018 */
union {
struct {
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
uint32_t sam: 1; /* BTR1.7 Sampling*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 7 */
uint32_t reserved_08; /* Address 8 (Output control not supported) */
uint32_t reserved_09; /* Address 9 (Test Register not supported) */
uint32_t reserved_10; /* Address 10 */
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
uint32_t reserved_28; /* Address 0x0028 */
//Capture and Counter Registers
union {
struct {
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} arbitration_lost_captue_reg; /* Address 11 */
} arbitration_lost_captue_reg; /* Address 0x002C */
union {
struct {
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
uint32_t errc: 2; /* ECC[7:6] Error Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_code_capture_reg; /* Address 12 */
} error_code_capture_reg; /* Address 0x0030 */
union {
struct {
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
} error_warning_limit_reg; /* Address 0x0034 */
union {
struct {
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} rx_error_counter_reg; /* Address 12 */
} rx_error_counter_reg; /* Address 0x0038 */
union {
struct {
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} tx_error_counter_reg; /* Address 15 */
} tx_error_counter_reg; /* Address 0x003C */
//Shared Registers (TX Buff/RX Buff/Acc Filter)
union {
@ -158,47 +159,51 @@ typedef volatile struct twai_dev_s {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved32[5];
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
} acceptance_filter;
union {
struct {
uint32_t byte: 8;
uint32_t reserved24: 24;
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
uint32_t reserved24: 24; /* Internal Reserved */
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 0x0040 - 0x0070 */
//Misc Registers
union {
struct {
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
uint32_t reserved25: 25; /* Internal Reserved */
uint32_t reserved7: 25; /* Internal Reserved */
};
uint32_t val;
} rx_message_counter_reg; /* Address 29 */
uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
} rx_message_counter_reg; /* Address 0x0074 */
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
union {
struct {
uint32_t cd: 3; /* CDR[2:0] CLKOUT frequency selector based of fOSC */
uint32_t co: 1; /* CDR.3 CLKOUT enable/disable */
uint32_t reserved3: 3; /* Internal Reserved. RXINTEN and CBP not supported */
uint32_t reserved4: 3; /* Internal Reserved. RXINTEN and CBP not supported */
uint32_t cm: 1; /* CDR.7 Register Layout. Basic:0 Extended:1 */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved6: 24; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 31 */
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");

53
tools/sdk/esp32/include/soc/esp32/include/soc/uart_pins.h Normal file
View File

@ -0,0 +1,53 @@
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0TXD_GPIO_NUM (1)
#define U0RXD_GPIO_NUM (3)
#define U0CTS_GPIO_NUM (19)
#define U0RTS_GPIO_NUM (22)
#define U1TXD_GPIO_NUM (10)
#define U1RXD_GPIO_NUM (9)
#define U1CTS_GPIO_NUM (6)
#define U1RTS_GPIO_NUM (11)
#define U2TXD_GPIO_NUM (17)
#define U2RXD_GPIO_NUM (16)
#define U2CTS_GPIO_NUM (8)
#define U2RTS_GPIO_NUM (7)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD)
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
#define U0RTS_MUX_FUNC (FUNC_GPIO22_U0RTS)
#define U0CTS_MUX_FUNC (FUNC_GPIO19_U0CTS)
#define U1TXD_MUX_FUNC (FUNC_SD_DATA3_U1TXD)
#define U1RXD_MUX_FUNC (FUNC_SD_DATA2_U1RXD)
#define U1RTS_MUX_FUNC (FUNC_SD_CMD_U1RTS)
#define U1CTS_MUX_FUNC (FUNC_SD_CLK_U1CTS)
#define U2TXD_MUX_FUNC (FUNC_GPIO17_U2TXD)
#define U2RXD_MUX_FUNC (FUNC_GPIO16_U2RXD)
#define U2RTS_MUX_FUNC (FUNC_SD_DATA0_U2RTS)
#define U2CTS_MUX_FUNC (FUNC_SD_DATA1_U2CTS)

4
tools/sdk/esp32/include/soc/esp32/include/soc/uart_struct.h
View File

@ -23,8 +23,8 @@ extern "C" {
typedef volatile struct uart_dev_s {
union {
struct {
uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/
uint8_t reserved[3];
uint32_t rw_byte: 8; /*This register stores one byte data read by rx fifo.*/
uint32_t reserved: 24;
};
uint32_t val;
} fifo;

2
tools/sdk/esp32/include/soc/esp32/include/soc/uhci_struct.h
View File

@ -277,7 +277,7 @@ typedef volatile struct uhci_dev_s {
};
uint32_t val;
} quick_sent;
struct{
struct {
uint32_t w_data[2]; /*This register stores the content of short packet's dword*/
} q_data[7];
union {

2
tools/sdk/esp32/include/soc/include/soc/adc_periph.h
View File

@ -18,7 +18,7 @@
#include "soc/soc_caps.h"
#include "soc/syscon_struct.h"
#if SOC_ADC_SUPPORT_RTC_CTRL
#if SOC_ADC_RTC_CTRL_SUPPORTED
#include "soc/sens_reg.h"
#include "soc/sens_struct.h"
#endif

27
tools/sdk/esp32/include/soc/include/soc/i2s_periph.h
View File

@ -1,4 +1,4 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -27,16 +27,21 @@ extern "C" {
Stores a bunch of per-I2S-peripheral data.
*/
typedef struct {
const uint8_t o_bck_in_sig;
const uint8_t o_ws_in_sig;
const uint8_t o_bck_out_sig;
const uint8_t o_ws_out_sig;
const uint8_t o_data_out_sig;
const uint8_t i_bck_in_sig;
const uint8_t i_ws_in_sig;
const uint8_t i_bck_out_sig;
const uint8_t i_ws_out_sig;
const uint8_t i_data_in_sig;
const uint8_t mck_out_sig;
const uint8_t m_tx_bck_sig;
const uint8_t m_rx_bck_sig;
const uint8_t m_tx_ws_sig;
const uint8_t m_rx_ws_sig;
const uint8_t s_tx_bck_sig;
const uint8_t s_rx_bck_sig;
const uint8_t s_tx_ws_sig;
const uint8_t s_rx_ws_sig;
const uint8_t data_out_sig;
const uint8_t data_in_sig;
const uint8_t irq;
const periph_module_t module;
} i2s_signal_conn_t;

14
tools/sdk/esp32/include/soc/include/soc/lcd_periph.h
View File

@ -21,6 +21,7 @@
extern "C" {
#endif
#if SOC_LCDCAM_SUPPORTED
typedef struct {
struct {
const periph_module_t module;
@ -41,6 +42,19 @@ typedef struct {
} panels[SOC_LCD_RGB_PANELS];
} lcd_signal_conn_t;
#endif // SOC_LCDCAM_SUPPORTED
#if SOC_I2S_LCD_I80_VARIANT
typedef struct {
struct {
const periph_module_t module;
const int irq_id;
const int data_sigs[SOC_LCD_I80_BUS_WIDTH];
const int wr_sig;
} buses[SOC_LCD_I80_BUSES];
} lcd_signal_conn_t;
#endif // SOC_I2S_LCD_I80_VARIANT
extern const lcd_signal_conn_t lcd_periph_signals;
#ifdef __cplusplus

4
tools/sdk/esp32/include/soc/include/soc/mcpwm_periph.h
View File

@ -34,13 +34,13 @@ typedef struct {
} operators[SOC_MCPWM_OPERATORS_PER_GROUP];
struct {
const uint32_t fault_sig;
} detectors[SOC_MCPWM_FAULT_DETECTORS_PER_GROUP];
} gpio_faults[SOC_MCPWM_GPIO_FAULTS_PER_GROUP];
struct {
const uint32_t cap_sig;
} captures[SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER];
struct {
const uint32_t sync_sig;
} ext_syncers[SOC_MCPWM_EXT_SYNCERS_PER_GROUP];
} gpio_synchros[SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP];
} groups[SOC_MCPWM_GROUPS];
} mcpwm_signal_conn_t;

16
tools/sdk/esp32/include/soc/include/soc/pcnt_periph.h
View File

@ -1,4 +1,4 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -27,12 +27,14 @@ extern "C" {
typedef struct {
struct {
struct {
const uint32_t pulse_sig;
const uint32_t control_sig;
} channels[SOC_PCNT_UNIT_CHANNEL_NUM];
} units[SOC_PCNT_UNIT_NUM];
const uint32_t irq;
const periph_module_t module;
struct {
const uint32_t pulse_sig;
const uint32_t control_sig;
} channels[SOC_PCNT_CHANNELS_PER_UNIT];
} units[SOC_PCNT_UNITS_PER_GROUP];
const uint32_t irq;
const periph_module_t module;
} groups[SOC_PCNT_GROUPS];
} pcnt_signal_conn_t;
extern const pcnt_signal_conn_t pcnt_periph_signals;

2
tools/sdk/esp32/include/soc/include/soc/rtc_io_periph.h
View File

@ -27,7 +27,7 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_cntl_struct.h"
#if SOC_ADC_SUPPORT_RTC_CTRL
#if SOC_ADC_RTC_CTRL_SUPPORTED
#include "soc/sens_struct.h"
#endif

3
tools/sdk/esp32/include/soc/include/soc/sdio_slave_periph.h
View File

@ -15,9 +15,12 @@
#pragma once
#include <stdint.h>
//include soc related (generated) definitions
#include "soc/soc_caps.h"
#include "soc/soc_pins.h"
#ifdef SOC_SDIO_SLAVE_SUPPORTED
#include "soc/slc_reg.h"
#include "soc/slc_struct.h"
#endif
#include "soc/host_reg.h"
#include "soc/host_struct.h"
#include "soc/hinf_reg.h"

17
tools/sdk/esp32/include/soc/include/soc/spi_periph.h
View File

@ -30,8 +30,7 @@
#endif
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
#if CONFIG_IDF_TARGET_ESP32S2
@ -41,8 +40,6 @@ extern "C"
#define SPI_FWRITE_QIO 0
#endif
/*
Stores a bunch of per-spi-peripheral data.
*/
@ -53,10 +50,22 @@ typedef struct {
const uint8_t spiq_out;
const uint8_t spiwp_out;
const uint8_t spihd_out;
#if SOC_SPI_SUPPORT_OCT
const uint8_t spid4_out;
const uint8_t spid5_out;
const uint8_t spid6_out;
const uint8_t spid7_out;
#endif // SOC_SPI_SUPPORT_OCT
const uint8_t spid_in; //GPIO mux input signals
const uint8_t spiq_in;
const uint8_t spiwp_in;
const uint8_t spihd_in;
#if SOC_SPI_SUPPORT_OCT
const uint8_t spid4_in;
const uint8_t spid5_in;
const uint8_t spid6_in;
const uint8_t spid7_in;
#endif // SOC_SPI_SUPPORT_OCT
const uint8_t spics_out[3]; // /CS GPIO output mux signals
const uint8_t spics_in;
const uint8_t spidqs_out;

32
tools/sdk/esp32/include/soc/include/soc/uart_periph.h
View File

@ -18,16 +18,40 @@
#include "soc/uart_struct.h"
#include "soc/periph_defs.h"
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
#include "soc/uart_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_UART_TX_PIN_IDX (0)
#define SOC_UART_RX_PIN_IDX (1)
#define SOC_UART_RTS_PIN_IDX (2)
#define SOC_UART_CTS_PIN_IDX (3)
/**
* @brief Macro that can be used to retrieve the signal of a certain pin for a
* certain UART.
*/
#define UART_PERIPH_SIGNAL(IDX, PIN) (uart_periph_signal[(IDX)].pins[(PIN)].signal)
typedef struct {
const uint8_t tx_sig;
const uint8_t rx_sig;
const uint8_t rts_sig;
const uint8_t cts_sig;
/* Default GPIO number for this UART pin in the IOMUX.
* This value can be -1 if there is no default GPIO for a pin.
* For example, ESP32-C3 doesn't have any default GPIO for
* U0CTS and U0RTS. */
int32_t default_gpio : 15;
/* Func which should be assigned to the GPIO to be used as UART */
int32_t iomux_func : 4;
/* Marks if the current UART pin is input (or not) */
uint32_t input : 1;
/* Signal in the GPIO signal map. */
uint32_t signal : 12;
} uart_periph_sig_t;
typedef struct {
const uart_periph_sig_t pins[SOC_UART_PINS_COUNT];
const uint8_t irq;
const periph_module_t module;
} uart_signal_conn_t;

35
tools/sdk/esp32/include/soc/include/soc/usb_phy_periph.h Normal file
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@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
Stores a bunch of USB-peripheral data.
*/
typedef struct {
const uint8_t extphy_vp_in;
const uint8_t extphy_vm_in;
const uint8_t extphy_rcv_in;
const uint8_t extphy_oen_out;
const uint8_t extphy_vpo_out;
const uint8_t extphy_vmo_out;
const uint8_t extphy_suspend_in;
const uint8_t extphy_speed_in;
const periph_module_t module;
} usb_phy_signal_conn_t;
extern const usb_phy_signal_conn_t usb_phy_periph_signal;
#ifdef __cplusplus
}
#endif