IDF master 3e370c4296

* Fix build compilation due to changes in the HW_TIMER's structs

* Fix compilation warnings and errors with USB

* Update USBCDC.cpp

* Update CMakeLists.txt

* Update HWCDC.cpp
This commit is contained in:
Me No Dev
2021-10-01 17:52:29 +03:00
committed by GitHub
parent 381e88ec75
commit 00214d5c2a
1475 changed files with 88153 additions and 49503 deletions

View File

@ -87,6 +87,7 @@ typedef enum {
ESP_PARTITION_SUBTYPE_DATA_COREDUMP = 0x03, //!< COREDUMP partition
ESP_PARTITION_SUBTYPE_DATA_NVS_KEYS = 0x04, //!< Partition for NVS keys
ESP_PARTITION_SUBTYPE_DATA_EFUSE_EM = 0x05, //!< Partition for emulate eFuse bits
ESP_PARTITION_SUBTYPE_DATA_UNDEFINED = 0x06, //!< Undefined (or unspecified) data partition
ESP_PARTITION_SUBTYPE_DATA_ESPHTTPD = 0x80, //!< ESPHTTPD partition
ESP_PARTITION_SUBTYPE_DATA_FAT = 0x81, //!< FAT partition

View File

@ -68,3 +68,7 @@
#define SPI_FLASH_FASTRD_DUMMY_BITLEN 8
#define SPI_FLASH_SLOWRD_ADDR_BITLEN 24
#define SPI_FLASH_SLOWRD_DUMMY_BITLEN 0
#define SPI_FLASH_OPISTR_ADDR_BITLEN 32
#define SPI_FLASH_OPISTR_DUMMY_BITLEN 20
#define SPI_FLASH_OPIDTR_ADDR_BITLEN 32
#define SPI_FLASH_OPIDTR_DUMMY_BITLEN 40

View File

@ -206,6 +206,11 @@ struct spi_flash_chip_t {
* Get the capabilities of the flash chip. See SPI_FLASH_CHIP_CAP_* macros as reference.
*/
spi_flash_caps_t (*get_chip_caps)(esp_flash_t *chip);
/**
* Configure the host registers to use the specified read mode set in the ``chip->read_mode``.
*/
esp_err_t (*config_host_io_mode)(esp_flash_t *chip, uint32_t flags);
};
/* Pointer to an array of pointers to all known drivers for flash chips. This array is used

View File

@ -370,14 +370,15 @@ esp_err_t spi_flash_common_set_io_mode(esp_flash_t *chip, esp_flash_wrsr_func_t
* transactions. Also prepare the command to be sent in read functions.
*
* @param chip Pointer to SPI flash chip to use. If NULL, esp_flash_default_chip is substituted.
* @param addr_32bit Whether 32 bit commands will be used (Currently only W25Q256 and GD25Q256 are supported)
* @param flags Special rules to configure io mode, (i.e. Whether 32 bit commands will be used (Currently only W25Q256 and GD25Q256 are supported))
*
* @return
* - ESP_OK if success
* - ESP_ERR_FLASH_NOT_INITIALISED if chip not initialized properly
* - or other error passed from the ``configure_host_mode`` function of host driver
*/
esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip, bool addr_32bit);
esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip, uint32_t flags);
#define SPI_FLASH_CONFIG_IO_MODE_32B_ADDR BIT(0)
/**
* @brief Handle explicit yield requests
@ -396,5 +397,15 @@ esp_err_t spi_flash_chip_generic_yield(esp_flash_t* chip, uint32_t wip);
*/
esp_err_t spi_flash_chip_generic_suspend_cmd_conf(esp_flash_t *chip);
/**
*
* @brief Read the chip unique ID unsupported function.
*
* @param chip Pointer to SPI flash chip to use.
* @param flash_unique_id Pointer to store output unique id (Although this function is an unsupported function, but the parameter should be kept for the consistence of the function pointer).
* @return Always ESP_ERR_NOT_SUPPORTED.
*/
esp_err_t spi_flash_chip_generic_read_unique_id_none(esp_flash_t *chip, uint64_t* flash_unique_id);
/// Default timeout configuration used by most chips
const flash_chip_op_timeout_t spi_flash_chip_generic_timeout;
extern const flash_chip_op_timeout_t spi_flash_chip_generic_timeout;

View File

@ -25,3 +25,10 @@
* is not found.
*/
extern const spi_flash_chip_t esp_flash_chip_mxic;
/**
* MXIC OPI flash chip_drv, uses all the above functions for its operations. In
* default autodetection, this is used as a catchall if a more specific chip_drv
* is not found.
*/
extern const spi_flash_chip_t esp_flash_chip_mxic_opi;

View File

@ -26,6 +26,8 @@
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#endif
#include "esp_flash.h"
#include "hal/spi_flash_hal.h"
#ifdef __cplusplus
extern "C" {
@ -38,13 +40,15 @@ esp_err_t esp_opiflash_init(void);
/**
* @brief Make MSPI work under 20Mhz
* @param control_spi1 Select whether to control SPI1. For tuning, we need to use SPI1. After tuning (during startup stage), let the flash driver to control SPI1
*/
void spi_timing_enter_mspi_low_speed_mode(void);
void spi_timing_enter_mspi_low_speed_mode(bool control_spi1);
/**
* @brief Make MSPI work under the frequency as users set
* @param control_spi1 Select whether to control SPI1. For tuning, we need to use SPI1. After tuning (during startup stage), let the flash driver to control SPI1
*/
void spi_timing_enter_mspi_high_speed_mode(void);
void spi_timing_enter_mspi_high_speed_mode(bool control_spi1);
/**
* @brief Tune MSPI flash timing to make it work under high frequency
@ -56,12 +60,34 @@ void spi_timing_flash_tuning(void);
*/
void spi_timing_psram_tuning(void);
/**
* @brief To initislize the MSPI pins
*/
void esp_mspi_pin_init(void);
/**
* @brief Set SPI1 registers to make ROM functions work
* @note This function is used for setting SPI1 registers to the state that ROM SPI functions work
*/
void spi_flash_set_rom_required_regs(void);
/**
* @brief Initialize main flash
* @param chip Pointer to main SPI flash(SPI1 CS0) chip to use..
*/
esp_err_t esp_flash_init_main(esp_flash_t *chip);
/**
* @brief Should be only used by SPI1 Flash driver to know the necessary timing registers
* @param out_timing_config Pointer to timing_tuning parameters.
*/
void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config);
/**
* @brief Judge if the flash in tuned
*/
bool spi_timine_config_flash_is_tuned(void);
#ifdef __cplusplus
}
#endif