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IDF master 3e370c4296

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* Fix build compilation due to changes in the HW_TIMER's structs

* Fix compilation warnings and errors with USB

* Update USBCDC.cpp

* Update CMakeLists.txt

* Update HWCDC.cpp
This commit is contained in:
Me No Dev
2021-10-01 17:52:29 +03:00
committed by GitHub
parent 381e88ec75
commit 00214d5c2a
1475 changed files with 88153 additions and 49503 deletions
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2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/apb_ctrl_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_ctrl_dev_s {
union {
struct {
uint32_t pre_div: 10;

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/apb_saradc_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force: 1;

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/cache_memory.h
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@ -67,7 +67,7 @@ extern "C" {
#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1)
#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT)
#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT_CACHE)
#define PRO_CACHE_IBUS0 0
#define PRO_CACHE_IBUS0_MMU_START 0

6
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/cp_dma_struct.h
View File

@ -69,6 +69,7 @@ typedef union {
* This is the interrupt raw bit. Triggered when crc calculation is done.
*/
uint32_t dma_crc_done_int_raw: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_raw_reg_t;
@ -123,6 +124,7 @@ typedef union {
* cp_crc_done_int_ena is set to 1.
*/
uint32_t dma_crc_done_int_st: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_st_reg_t;
@ -168,6 +170,7 @@ typedef union {
* This is the interrupt enable bit for cp_crc_done_int interrupt.
*/
uint32_t dma_crc_done_int_ena: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_ena_reg_t;
@ -213,6 +216,7 @@ typedef union {
* Set this bit to clear cp_crc_done_int interrupt.
*/
uint32_t dma_crc_done_int_clr: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_clr_reg_t;
@ -491,6 +495,7 @@ typedef union {
* Copy DMA FIFO empty signal.
*/
uint32_t dma_fifo_empty: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} cp_dma_in_st_reg_t;
@ -516,6 +521,7 @@ typedef union {
* Copy DMA FIFO full signal.
*/
uint32_t dma_fifo_full: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} cp_dma_out_st_reg_t;

12
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/dedic_gpio_struct.h
View File

@ -31,6 +31,7 @@ typedef union {
* gpio.
*/
uint32_t gpio_out_drt_vlaue: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_out_drt_reg_t;
@ -49,6 +50,7 @@ typedef union {
* channel's output would be masked.
*/
uint32_t gpio_out_msk: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} dedic_gpio_out_msk_reg_t;
@ -98,6 +100,7 @@ typedef union {
* clear output value; 3: inverse output value.
*/
uint32_t gpio_out_idv_ch7: 2;
uint32_t reserved16: 16;
};
uint32_t val;
} dedic_gpio_out_idv_reg_t;
@ -147,6 +150,7 @@ typedef union {
* select CPU instructors.
*/
uint32_t gpio_out_cpu_sel7: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_out_cpu_reg_t;
@ -196,6 +200,7 @@ typedef union {
* 3: three clock delay.
*/
uint32_t gpio_in_dly_ch7: 2;
uint32_t reserved16: 16;
};
uint32_t val;
} dedic_gpio_in_dly_reg_t;
@ -285,6 +290,7 @@ typedef union {
* 6/7: falling and raising edge trigger.
*/
uint32_t gpio_intr_mode_ch7: 3;
uint32_t reserved24: 8;
};
uint32_t val;
} dedic_gpio_intr_rcgn_reg_t;
@ -301,6 +307,7 @@ typedef union {
* DEDIC_GPIO_OUT_IDV_REG.
*/
uint32_t gpio_out_status: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_out_scan_reg_t;
@ -314,6 +321,7 @@ typedef union {
* gpio in value after configured by DEDIC_GPIO_IN_DLY_REG.
*/
uint32_t gpio_in_status: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_in_scan_reg_t;
@ -365,6 +373,7 @@ typedef union {
* change configured by DEDIC_GPIO_INTR_RCGN_REG.
*/
uint32_t gpio7_int_raw: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_raw_reg_t;
@ -406,6 +415,7 @@ typedef union {
* This enable bit for reg_gpio7_int_st register.
*/
uint32_t gpio7_int_ena: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_rls_reg_t;
@ -447,6 +457,7 @@ typedef union {
* This is the status bit for reg_gpio7_int_raw when reg_gpio7_int_ena is set to 1.
*/
uint32_t gpio7_int_st: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_st_reg_t;
@ -488,6 +499,7 @@ typedef union {
* Set this bit to clear the reg_gpio7_int_raw interrupt.
*/
uint32_t gpio7_int_clr: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_clr_reg_t;

40
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_reg.h
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@ -917,18 +917,18 @@ extern "C" {
#define EFUSE_SPI_PAD_CONF_1_S 0
#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050)
/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:25] ;default: 7'h0 ; */
/*description: Stores the fist 7 bits of the zeroth part of system data.*/
#define EFUSE_SYS_DATA_PART0_0 0x0000007F
#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
#define EFUSE_SYS_DATA_PART0_0_V 0x7F
#define EFUSE_SYS_DATA_PART0_0_S 25
/* EFUSE_PKG_VERSION : RO ;bitpos:[24:21] ;default: 4'h0 ; */
/*description: Package version 0:ESP32-S2, 1:ESP32-S2FH16, 2:ESP32-S2FH32 */
#define EFUSE_PKG_VERSION 0x0000000F
#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
#define EFUSE_PKG_VERSION_V 0xF
#define EFUSE_PKG_VERSION_S 21
/* EFUSE_PSRAM_VERSION : RO ;bitpos:[31:28] ;default: 4'h0 ; */
/*description: PSRAM version */
#define EFUSE_PSRAM_VERSION 0x0000000F
#define EFUSE_PSRAM_VERSION_M ((EFUSE_PSRAM_VERSION_V)<<(EFUSE_PSRAM_VERSION_S))
#define EFUSE_PSRAM_VERSION_V 0xF
#define EFUSE_PSRAM_VERSION_S 28
/* EFUSE_FLASH_VERSION : RO ;bitpos:[24:21] ;default: 4'h0 ; */
/*description: Flash version */
#define EFUSE_FLASH_VERSION 0x0000000F
#define EFUSE_FLASH_VERSION_M ((EFUSE_FLASH_VERSION_V)<<(EFUSE_FLASH_VERSION_S))
#define EFUSE_FLASH_VERSION_V 0xF
#define EFUSE_FLASH_VERSION_S 21
/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */
/*description: WAFER version 0:A */
#define EFUSE_WAFER_VERSION 0x00000007
@ -943,12 +943,18 @@ extern "C" {
#define EFUSE_SPI_PAD_CONF_2_S 0
#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054)
/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:4] ;default: 28'h0 ; */
/*description: Stores the fist 32 bits of the zeroth part of system data.*/
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF
#define EFUSE_SYS_DATA_PART0_1 0x0FFFFFFF
#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S))
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF
#define EFUSE_SYS_DATA_PART0_1_S 0
#define EFUSE_SYS_DATA_PART0_1_V 0x0FFFFFFF
#define EFUSE_SYS_DATA_PART0_1_S 4
/* EFUSE_PKG_VERSION : RO ;bitpos:[3:0] ;default: 4'h0 ; */
/*description: Package version */
#define EFUSE_PKG_VERSION 0x0000000F
#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
#define EFUSE_PKG_VERSION_V 0xF
#define EFUSE_PKG_VERSION_S 0
#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058)
/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
@ -1902,7 +1908,7 @@ extern "C" {
#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1
#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0
#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190)
#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18C)
/* EFUSE_RPT1_RESERVED0_ERR : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT1_RESERVED0_ERR 0x000000FF

26
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct efuse_dev_s {
uint32_t pgm_data0; /**/
union {
struct {
@ -357,7 +357,6 @@ typedef volatile struct {
};
uint32_t val;
} rd_repeat_err3;
uint32_t reserved_18c;
union {
struct {
uint32_t rd_chip_version_err:24;
@ -365,6 +364,18 @@ typedef volatile struct {
};
uint32_t val;
} rd_repeat_err4;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
union {
struct {
uint32_t rd_mac_spi_8m_err_num: 3;
@ -500,17 +511,6 @@ typedef volatile struct {
};
uint32_t val;
} wr_tim_conf1;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t date; /**/
} efuse_dev_t;

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/gpio_sd_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_sd_dev_s {
union {
struct {
uint32_t duty: 8;

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/gpio_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_dev_s {
uint32_t bt_select; /**/
uint32_t out; /**/
uint32_t out_w1ts; /**/

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/i2c_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2c_dev_s {
union {
struct {
uint32_t period: 14;

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/i2s_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
union {

5
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/io_mux_reg.h
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@ -145,11 +145,6 @@
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define U1RXD_GPIO_NUM 18
#define U1TXD_GPIO_NUM 17
#define U0RXD_GPIO_NUM 44
#define U0TXD_GPIO_NUM 43
#define SPI_CS1_GPIO_NUM 26
#define SPI_HD_GPIO_NUM 27
#define SPI_WP_GPIO_NUM 28

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/ledc_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct ledc_dev_s {
struct {
struct {
union {

131
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/memprot_defs.h Normal file
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@ -0,0 +1,131 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/soc.h"
#include "soc/sensitive_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
//IRAM0 interrupt status bitmasks
#define IRAM0_INTR_ST_OP_TYPE_BIT BIT(1) //instruction: 0, data: 1
#define IRAM0_INTR_ST_OP_RW_BIT BIT(0) //read: 0, write: 1
#define CONF_REG_ADDRESS_SHIFT 2
//IRAM0 range
#define IRAM0_SRAM_BASE_ADDRESS 0x40000000
#define IRAM0_SRAM_ADDRESS_LOW 0x40020000
#define IRAM0_SRAM_ADDRESS_HIGH 0x4006FFFF
//IRAM0 unified managemnt blocks
#define IRAM0_SRAM_TOTAL_UNI_BLOCKS 4
#define IRAM0_SRAM_UNI_BLOCK_0 0
#define IRAM0_SRAM_UNI_BLOCK_1 1
#define IRAM0_SRAM_UNI_BLOCK_2 2
#define IRAM0_SRAM_UNI_BLOCK_3 3
//unified management addr range (blocks 0-3)
#define IRAM0_SRAM_UNI_BLOCK_0_LOW 0x40020000
#define IRAM0_SRAM_UNI_BLOCK_1_LOW 0x40022000
#define IRAM0_SRAM_UNI_BLOCK_2_LOW 0x40024000
#define IRAM0_SRAM_UNI_BLOCK_3_LOW 0x40026000
//split management addr range (blocks 4-21)
#define IRAM0_SRAM_SPL_BLOCK_LOW 0x40028000 //block 4 low
#define IRAM0_SRAM_SPL_BLOCK_HIGH 0x4006FFFF //block 21 high
#define IRAM0_INTR_ST_FAULTADDR_M 0x003FFFFC //bits 21:6 in the reg, as well as in real address
#define IRAM0_SRAM_INTR_ST_FAULTADDR_HI 0x40000000 //high nonsignificant bits 31:22 of the faulting address - constant
#define IRAM0_SRAM_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR) << DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_S)
//IRAM0 RTCFAST
#define IRAM0_RTCFAST_ADDRESS_LOW 0x40070000
#define IRAM0_RTCFAST_ADDRESS_HIGH 0x40071FFF
#define IRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x40070000 //RTCFAST faulting address high bits (31:22, constant)
#define IRAM0_RTCFAST_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR) << DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_S)
//DRAM0 interrupt status bitmasks
#define DRAM0_INTR_ST_FAULTADDR_M 0x03FFFFC0 //(bits 25:6 in the reg)
#define DRAM0_INTR_ST_FAULTADDR_S 0x4 //(bits 21:2 of real address)
#define DRAM0_INTR_ST_OP_RW_BIT BIT(4) //read: 0, write: 1
#define DRAM0_INTR_ST_OP_ATOMIC_BIT BIT(5) //non-atomic: 0, atomic: 1
#define DRAM0_SRAM_ADDRESS_LOW 0x3FFB0000
#define DRAM0_SRAM_ADDRESS_HIGH 0x3FFFFFFF
#define DRAM0_SRAM_TOTAL_UNI_BLOCKS 4
#define DRAM0_SRAM_UNI_BLOCK_0 0
#define DRAM0_SRAM_UNI_BLOCK_1 1
#define DRAM0_SRAM_UNI_BLOCK_2 2
#define DRAM0_SRAM_UNI_BLOCK_3 3
//unified management (SRAM blocks 0-3)
#define DRAM0_SRAM_UNI_BLOCK_0_LOW 0x3FFB0000
#define DRAM0_SRAM_UNI_BLOCK_1_LOW 0x3FFB2000
#define DRAM0_SRAM_UNI_BLOCK_2_LOW 0x3FFB4000
#define DRAM0_SRAM_UNI_BLOCK_3_LOW 0x3FFB6000
//split management (SRAM blocks 4-21)
#define DRAM0_SRAM_SPL_BLOCK_HIGH 0x3FFFFFFF //block 21 high
#define DRAM0_SRAM_INTR_ST_FAULTADDR_HI 0x3FF00000 //SRAM high bits 31:22 of the faulting address - constant
#define DRAM0_SRAM_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR) << DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S)
//DRAM0 RTCFAST
#define DRAM0_RTCFAST_ADDRESS_LOW 0x3FF9E000
#define DRAM0_RTCFAST_ADDRESS_HIGH 0x3FF9FFFF
#define DRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x3FF00000 //RTCFAST high bits 31:22 of the faulting address - constant
#define DRAM0_RTCFAST_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR) << DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_S)
//RTCSLOW
#define RTCSLOW_MEMORY_SIZE 0x00002000
//PeriBus1 interrupt status bitmasks
#define PERI1_INTR_ST_OP_TYPE_BIT BIT(4) //0: non-atomic, 1: atomic
#define PERI1_INTR_ST_OP_HIGH_BITS BIT(5) //0: high bits = unchanged, 1: high bits = 0x03F40000
#define PERI1_INTR_ST_FAULTADDR_M 0x03FFFFC0 //(bits 25:6 in the reg)
#define PERI1_INTR_ST_FAULTADDR_S 0x4 //(bits 21:2 of real address)
#define PERI1_RTCSLOW_ADDRESS_BASE 0x3F421000
#define PERI1_RTCSLOW_ADDRESS_LOW PERI1_RTCSLOW_ADDRESS_BASE
#define PERI1_RTCSLOW_ADDRESS_HIGH PERI1_RTCSLOW_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE
#define PERI1_RTCSLOW_INTR_ST_FAULTADDR_HI_0 0x3F400000
#define PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR) << DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_S)
//PeriBus2 interrupt status bitmasks
#define PERI2_INTR_ST_OP_TYPE_BIT BIT(1) //instruction: 0, data: 1
#define PERI2_INTR_ST_OP_RW_BIT BIT(0) //read: 0, write: 1
#define PERI2_INTR_ST_FAULTADDR_M 0xFFFFFFFC //(bits 31:2 in the reg)
#define PERI2_RTCSLOW_0_ADDRESS_BASE 0x50000000
#define PERI2_RTCSLOW_0_ADDRESS_LOW PERI2_RTCSLOW_0_ADDRESS_BASE
#define PERI2_RTCSLOW_0_ADDRESS_HIGH PERI2_RTCSLOW_0_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE
#define PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR) << DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_S)
#define PERI2_RTCSLOW_1_ADDRESS_BASE 0x60021000
#define PERI2_RTCSLOW_1_ADDRESS_LOW PERI2_RTCSLOW_1_ADDRESS_BASE
#define PERI2_RTCSLOW_1_ADDRESS_HIGH PERI2_RTCSLOW_1_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE
#define PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR) << DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_S)
#ifdef __cplusplus
}
#endif

1976
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/pcnt_reg.h
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571
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/pcnt_struct.h
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@ -1,177 +1,416 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_PCNT_STRUCT_H_
#define _SOC_PCNT_STRUCT_H_
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
/** Group: Configuration Register */
/** Type of un_conf0 register
* Configuration register 0 for unit n
*/
typedef union {
struct {
union {
struct {
uint32_t filter_thres: 10;
uint32_t filter_en: 1;
uint32_t thr_zero_en: 1;
uint32_t thr_h_lim_en: 1;
uint32_t thr_l_lim_en: 1;
uint32_t thr_thres0_en: 1;
uint32_t thr_thres1_en: 1;
uint32_t ch0_neg_mode: 2;
uint32_t ch0_pos_mode: 2;
uint32_t ch0_hctrl_mode: 2;
uint32_t ch0_lctrl_mode: 2;
uint32_t ch1_neg_mode: 2;
uint32_t ch1_pos_mode: 2;
uint32_t ch1_hctrl_mode: 2;
uint32_t ch1_lctrl_mode: 2;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t cnt_thres0: 16;
uint32_t cnt_thres1: 16;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t cnt_h_lim: 16;
uint32_t cnt_l_lim: 16;
};
uint32_t val;
} conf2;
/** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
* This sets the maximum threshold, in APB_CLK cycles, for the filter.
*
* Any pulses with width less than this will be ignored when the filter is enabled.
*/
uint32_t filter_thres_un: 10;
/** filter_en_un : R/W; bitpos: [10]; default: 1;
* This is the enable bit for unit n's input filter.
*/
uint32_t filter_en_un: 1;
/** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
* This is the enable bit for unit n's zero comparator.
*/
uint32_t thr_zero_en_un: 1;
/** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
* This is the enable bit for unit n's thr_h_lim comparator.
*/
uint32_t thr_h_lim_en_un: 1;
/** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
* This is the enable bit for unit n's thr_l_lim comparator.
*/
uint32_t thr_l_lim_en_un: 1;
/** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
* This is the enable bit for unit n's thres0 comparator.
*/
uint32_t thr_thres0_en_un: 1;
/** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
* This is the enable bit for unit n's thres1 comparator.
*/
uint32_t thr_thres1_en_un: 1;
/** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
* This register sets the behavior when the signal input of channel 0 detects a
* negative edge.
*
* 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
*/
uint32_t ch0_neg_mode_un: 2;
/** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
* This register sets the behavior when the signal input of channel 0 detects a
* positive edge.
*
* 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
*/
uint32_t ch0_pos_mode_un: 2;
/** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is high.
*
* 0: No modification;1: Invert behavior (increase -> decrease, decrease ->
* increase);2, 3: Inhibit counter modification
*/
uint32_t ch0_hctrl_mode_un: 2;
/** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is low.
*
* 0: No modification;1: Invert behavior (increase -> decrease, decrease ->
* increase);2, 3: Inhibit counter modification
*/
uint32_t ch0_lctrl_mode_un: 2;
/** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
* This register sets the behavior when the signal input of channel 1 detects a
* negative edge.
*
* 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
*/
uint32_t ch1_neg_mode_un: 2;
/** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
* This register sets the behavior when the signal input of channel 1 detects a
* positive edge.
*
* 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
*/
uint32_t ch1_pos_mode_un: 2;
/** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is high.
*
* 0: No modification;1: Invert behavior (increase -> decrease, decrease ->
* increase);2, 3: Inhibit counter modification
*/
uint32_t ch1_hctrl_mode_un: 2;
/** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is low.
*
* 0: No modification;1: Invert behavior (increase -> decrease, decrease ->
* increase);2, 3: Inhibit counter modification
*/
uint32_t ch1_lctrl_mode_un: 2;
};
uint32_t val;
} pcnt_un_conf0_reg_t;
/** Type of un_conf1 register
* Configuration register 1 for unit n
*/
typedef union {
struct {
/** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
* This register is used to configure the thres0 value for unit n.
*/
uint32_t cnt_thres0_un: 16;
/** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
* This register is used to configure the thres1 value for unit n.
*/
uint32_t cnt_thres1_un: 16;
};
uint32_t val;
} pcnt_un_conf1_reg_t;
/** Type of un_conf2 register
* Configuration register 2 for unit n
*/
typedef union {
struct {
/** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
* This register is used to configure the thr_h_lim value for unit n.
*/
uint32_t cnt_h_lim_un: 16;
/** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
* This register is used to configure the thr_l_lim value for unit n.
*/
uint32_t cnt_l_lim_un: 16;
};
uint32_t val;
} pcnt_un_conf2_reg_t;
/** Type of ctrl register
* Control register for all counters
*/
typedef union {
struct {
/** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
* Set this bit to clear unit 0's counter.
*/
uint32_t pulse_cnt_rst_u0: 1;
/** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
* Set this bit to freeze unit 0's counter.
*/
uint32_t cnt_pause_u0: 1;
/** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
* Set this bit to clear unit 1's counter.
*/
uint32_t pulse_cnt_rst_u1: 1;
/** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
* Set this bit to freeze unit 1's counter.
*/
uint32_t cnt_pause_u1: 1;
/** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
* Set this bit to clear unit 2's counter.
*/
uint32_t pulse_cnt_rst_u2: 1;
/** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
* Set this bit to freeze unit 2's counter.
*/
uint32_t cnt_pause_u2: 1;
/** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
* Set this bit to clear unit 3's counter.
*/
uint32_t pulse_cnt_rst_u3: 1;
/** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
* Set this bit to freeze unit 3's counter.
*/
uint32_t cnt_pause_u3: 1;
uint32_t reserved_8: 8;
/** clk_en : R/W; bitpos: [16]; default: 0;
* The registers clock gate enable signal of PCNT module. 1: the registers can be read
* and written by application. 0: the registers can not be read or written by
* application
*/
uint32_t clk_en: 1;
uint32_t reserved_17: 15;
};
uint32_t val;
} pcnt_ctrl_reg_t;
/** Group: Status Register */
/** Type of un_cnt register
* Counter value for unit n
*/
typedef union {
struct {
/** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
* This register stores the current pulse count value for unit n.
*/
uint32_t pulse_cnt_un: 16;
uint32_t reserved_16: 16;
};
uint32_t val;
} pcnt_un_cnt_reg_t;
/** Type of un_status register
* PNCT UNITn status register
*/
typedef union {
struct {
/** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
* The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases
* from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
* is negative. 3: pulse counter is positive.
*/
uint32_t cnt_thr_zero_mode_un: 2;
/** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
* The latched value of thres1 event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
* others
*/
uint32_t cnt_thr_thres1_lat_un: 1;
/** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
* The latched value of thres0 event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
* others
*/
uint32_t cnt_thr_thres0_lat_un: 1;
/** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
* The latched value of low limit event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
* valid. 0: others
*/
uint32_t cnt_thr_l_lim_lat_un: 1;
/** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
* The latched value of high limit event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
* valid. 0: others
*/
uint32_t cnt_thr_h_lim_lat_un: 1;
/** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
* The latched value of zero threshold event of PCNT_Un when threshold event interrupt
* is valid. 1: the current pulse counter equals to 0 and zero threshold event is
* valid. 0: others
*/
uint32_t cnt_thr_zero_lat_un: 1;
uint32_t reserved_7: 25;
};
uint32_t val;
} pcnt_un_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* Interrupt raw status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_raw : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_raw: 1;
/** cnt_thr_event_u1_int_raw : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_raw: 1;
/** cnt_thr_event_u2_int_raw : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_raw: 1;
/** cnt_thr_event_u3_int_raw : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_raw: 1;
uint32_t reserved_4: 28;
};
uint32_t val;
} pcnt_int_raw_reg_t;
/** Type of int_st register
* Interrupt status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_st: 1;
/** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_st: 1;
/** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_st: 1;
/** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_st: 1;
uint32_t reserved_4: 28;
};
uint32_t val;
} pcnt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_ena: 1;
/** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_ena: 1;
/** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_ena: 1;
/** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_ena: 1;
uint32_t reserved_4: 28;
};
uint32_t val;
} pcnt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_clr : WO; bitpos: [0]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_clr: 1;
/** cnt_thr_event_u1_int_clr : WO; bitpos: [1]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_clr: 1;
/** cnt_thr_event_u2_int_clr : WO; bitpos: [2]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_clr: 1;
/** cnt_thr_event_u3_int_clr : WO; bitpos: [3]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_clr: 1;
uint32_t reserved_4: 28;
};
uint32_t val;
} pcnt_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* PCNT version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 419898881;
* This is the PCNT version control register.
*/
uint32_t date: 32;
};
uint32_t val;
} pcnt_date_reg_t;
typedef struct {
volatile struct {
pcnt_un_conf0_reg_t conf0;
pcnt_un_conf1_reg_t conf1;
pcnt_un_conf2_reg_t conf2;
} conf_unit[4];
union {
struct {
uint32_t cnt_val: 16;
uint32_t reserved16: 16;
};
uint32_t val;
} cnt_unit[4];
union {
struct {
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t cnt_mode: 2;
uint32_t thres1_lat: 1;
uint32_t thres0_lat: 1;
uint32_t l_lim_lat: 1;
uint32_t h_lim_lat: 1;
uint32_t zero_lat: 1;
uint32_t reserved7: 25;
};
uint32_t val;
} status_unit[4];
union {
struct {
uint32_t cnt_rst_u0: 1;
uint32_t cnt_pause_u0: 1;
uint32_t cnt_rst_u1: 1;
uint32_t cnt_pause_u1: 1;
uint32_t cnt_rst_u2: 1;
uint32_t cnt_pause_u2: 1;
uint32_t cnt_rst_u3: 1;
uint32_t cnt_pause_u3: 1;
uint32_t reserved8: 8;
uint32_t clk_en: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} ctrl;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
volatile pcnt_un_cnt_reg_t cnt_unit[4];
volatile pcnt_int_raw_reg_t int_raw;
volatile pcnt_int_st_reg_t int_st;
volatile pcnt_int_ena_reg_t int_ena;
volatile pcnt_int_clr_reg_t int_clr;
volatile pcnt_un_status_reg_t status_unit[4];
volatile pcnt_ctrl_reg_t ctrl;
uint32_t reserved_064[38];
volatile pcnt_date_reg_t date;
} pcnt_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
#endif
extern pcnt_dev_t PCNT;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_PCNT_STRUCT_H_ */

8
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/periph_defs.h
View File

@ -27,7 +27,6 @@ typedef enum {
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_UHCI0_MODULE,
@ -86,15 +85,14 @@ typedef enum {
ETS_DEDICATED_GPIO_INTR_SOURCE, /**< interrupt of dedicated GPIO, level*/
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/
ETS_SPI1_INTR_SOURCE = 32, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/
ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART0_INTR_SOURCE = 37, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/
ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/

8
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/rmt_struct.h
View File

@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rmt_dev_s {
uint32_t data_ch[4]; /* Data FIFO, Can only be accessed by PeriBus2 */
struct {
union {
@ -300,11 +300,9 @@ typedef struct {
} rmt_item32_t;
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct {
typedef volatile struct rmt_mem_s {
struct {
union {
rmt_item32_t data32[64];
};
rmt_item32_t data32[64];
} chan[4];
} rmt_mem_t;
extern rmt_mem_t RMTMEM;

3
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/rtc.h
View File

@ -215,7 +215,8 @@ typedef enum {
typedef enum {
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL
RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL
RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator
} rtc_cal_sel_t;
/**

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/rtc_cntl_struct.h
View File

@ -19,7 +19,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct rtc_cntl_dev_s {
union {
struct {
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/rtc_i2c_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_i2c_dev_s {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/rtc_io_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_io_dev_s {
union {
struct {
uint32_t reserved0: 10;

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/sens_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct sens_dev_s {
union {
struct {
uint32_t sar1_clk_div: 8; /*clock divider*/

27
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/soc.h
View File

@ -299,23 +299,23 @@
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
* Intr num Level Type PRO CPU usage
* 0 1 extern level WMAC
* 1 1 extern level BT/BLE Host HCI DMA
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level BT/BLE Controller BT/BLE Controller
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
* 5 1 extern level BT/BLE Controller
* 6 1 timer FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 14 7 nmi Reserved
* 15 3 timer FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
@ -327,10 +327,10 @@
* 24 4 extern level TG1_WDT
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 27 3 extern level Reserved
* 28 4 extern edge Reserved
* 29 3 software Reserved
* 30 4 extern edge Reserved
* 31 5 extern level
*************************************************************************************************************
*/
@ -343,7 +343,6 @@
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_MEMACCESS_ERR_INUM 25
#define ETS_DPORT_INUM 28
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1

72
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/soc_caps.h
View File

@ -44,7 +44,7 @@
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_RISCV_COPROC_SUPPORTED 1
#define SOC_USB_SUPPORTED 1
#define SOC_USB_OTG_SUPPORTED 1
#define SOC_PCNT_SUPPORTED 1
#define SOC_ULP_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
@ -59,24 +59,32 @@
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define SOC_PSRAM_DMA_CAPABLE 1
#define SOC_XT_WDT_SUPPORTED 1
/*-------------------------- ADC CAPS ----------------------------------------*/
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
#define SOC_ADC_MAX_BITWIDTH (13)
#define SOC_ADC_HW_CALIBRATION_V1 (1) /*!< support HW offset calibration */
/*!< SAR ADC Module*/
#define SOC_ADC_RTC_CTRL_SUPPORTED 1
#define SOC_ADC_ARBITER_SUPPORTED 1
#define SOC_ADC_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (32) /*!< Two pattern table, each contains 16 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_MAX_BITWIDTH (13)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
/**
* Check if adc support digital controller (DMA) mode.
* @value
* - 1 : support;
* - 0 : not support;
*/
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
#define SOC_ADC_SUPPORT_RTC_CTRL 1
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
@ -118,6 +126,7 @@
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_GPIO_ALLOW_REG_ACCESS (1) /*!< Allow access dedicated GPIO channel by register */
#define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */
#define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE (1) /*!< Dedicated GPIO output attribution is enabled automatically */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-S2 have 2 I2C.
@ -134,16 +143,20 @@
#define SOC_I2C_SUPPORT_APB (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32-S2 have 2 I2S
#define SOC_I2S_NUM (1)
// ESP32-S2 have 1 I2S
#define SOC_I2S_NUM (1)
#define SOC_I2S_SUPPORTS_APLL (1)// ESP32-S2 support APLL
#define SOC_I2S_SUPPORTS_DMA_EQUAL (1)
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define SOC_I2S_LCD_I80_VARIANT (1)
#define SOC_I2S_SUPPORTS_DMA_EQUAL (1) // ESP32-S2 need dma equal
#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
/*-------------------------- LCD CAPS ----------------------------------------*/
/* Notes: On esp32-s2, LCD intel 8080 timing is generated by I2S peripheral */
#define SOC_LCD_I80_SUPPORTED (1) /*!< Intel 8080 LCD is supported */
#define SOC_LCD_I80_BUSES (1) /*!< Only I2S0 has LCD mode */
#define SOC_LCD_I80_BUS_WIDTH (24) /*!< Intel 8080 bus width */
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
@ -159,10 +172,10 @@
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*-------------------------- PCNT CAPS ---------------------------------------*/
// ESP32-S2 have 1 PCNT peripheral
#define SOC_PCNT_PORT_NUM (1)
#define SOC_PCNT_UNIT_NUM (4) // ESP32-S2 only have 4 unit
#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
#define SOC_PCNT_GROUPS (1)
#define SOC_PCNT_UNITS_PER_GROUP (4)
#define SOC_PCNT_CHANNELS_PER_UNIT (2)
#define SOC_PCNT_THRES_POINT_PER_UNIT (2)
/*-------------------------- RMT CAPS ----------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
@ -213,6 +226,7 @@
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_SUPPORT_OCT 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units
@ -241,7 +255,7 @@
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-S2 have 2 UART.
// ESP32-S2 has 2 UART.
#define SOC_UART_NUM (2)
#define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */

44
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/spi_pins.h
View File

@ -22,21 +22,37 @@
#define SPI_IOMUX_PIN_NUM_MISO 31
#define SPI_IOMUX_PIN_NUM_WP 28
#define SPI2_FUNC_NUM FSPI_FUNC_NUM
#define SPI2_IOMUX_PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
#define SPI2_IOMUX_PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
#define SPI2_IOMUX_PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define SPI2_IOMUX_PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
#define SPI2_IOMUX_PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
#define SPI2_IOMUX_PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
// There are 2 sets of GPIO pins which could be routed to FSPICS0, FSPICLK, FSPID, FSPIQ, FSPIHD, FSPIWP.
// However, there is only one set of GPIO pins which could be routed to FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7.
// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows.
#define SPI2_FUNC_NUM 4
#define SPI2_IOMUX_PIN_NUM_HD 9
#define SPI2_IOMUX_PIN_NUM_CS 10
#define SPI2_IOMUX_PIN_NUM_MOSI 11
#define SPI2_IOMUX_PIN_NUM_CLK 12
#define SPI2_IOMUX_PIN_NUM_MISO 13
#define SPI2_IOMUX_PIN_NUM_WP 14
// When using Octal SPI, we make use of SPI2_FUNC_NUM_OCT to route them as follows.
#define SPI2_FUNC_NUM_OCT 2
#define SPI2_IOMUX_PIN_NUM_HD_OCT 33
#define SPI2_IOMUX_PIN_NUM_CS_OCT 34
#define SPI2_IOMUX_PIN_NUM_MOSI_OCT 35
#define SPI2_IOMUX_PIN_NUM_CLK_OCT 36
#define SPI2_IOMUX_PIN_NUM_MISO_OCT 37
#define SPI2_IOMUX_PIN_NUM_WP_OCT 38
#define SPI2_IOMUX_PIN_NUM_IO4_OCT 10
#define SPI2_IOMUX_PIN_NUM_IO5_OCT 11
#define SPI2_IOMUX_PIN_NUM_IO6_OCT 12
#define SPI2_IOMUX_PIN_NUM_IO7_OCT 13
//SPI3 has no iomux pins
//Following Macros are deprecated. Please use the Macros above
#define FSPI_FUNC_NUM 4
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
#define FSPI_IOMUX_PIN_NUM_MOSI 11
#define FSPI_IOMUX_PIN_NUM_CLK 12
#define FSPI_IOMUX_PIN_NUM_MISO 13
#define FSPI_IOMUX_PIN_NUM_WP 14
#define FSPI_FUNC_NUM SPI2_FUNC_NUM
#define FSPI_IOMUX_PIN_NUM_HD SPI2_IOMUX_PIN_NUM_HD
#define FSPI_IOMUX_PIN_NUM_CS SPI2_IOMUX_PIN_NUM_CS
#define FSPI_IOMUX_PIN_NUM_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define FSPI_IOMUX_PIN_NUM_CLK SPI2_IOMUX_PIN_NUM_CLK
#define FSPI_IOMUX_PIN_NUM_MISO SPI2_IOMUX_PIN_NUM_MISO
#define FSPI_IOMUX_PIN_NUM_WP SPI2_IOMUX_PIN_NUM_WP

8
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/syscon_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct syscon_dev_s {
union {
struct {
uint32_t pre_div: 10;
@ -29,7 +29,7 @@ typedef volatile struct {
uint32_t reserved16: 16;
};
uint32_t val;
} apb_ctrl_sysclk_conf;
} sysclk_conf;
union {
struct {
uint32_t xtal_tick: 8;
@ -38,7 +38,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
} apb_ctrl_tick_conf;
} tick_conf;
union {
struct {
uint32_t clk20_oen: 1;
@ -55,7 +55,7 @@ typedef volatile struct {
uint32_t reserved11: 21;
};
uint32_t val;
} apb_ctrl_clk_out_en;
} clk_out_en;
union {
struct {
uint32_t peri_io_swap: 8;

4
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/systimer_struct.h
View File

@ -91,6 +91,7 @@ typedef union {
* system timer accumulation step when using PLL
*/
uint32_t timer_pll_step: 10;
uint32_t reserved20: 12;
};
uint32_t val;
} systimer_step_reg_t;
@ -201,6 +202,7 @@ typedef union {
* system timer target2 interrupt enable
*/
uint32_t systimer_int2_ena: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_ena_reg_t;
@ -222,6 +224,7 @@ typedef union {
* system timer target2 interrupt raw
*/
uint32_t systimer_int2_raw: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_raw_reg_t;
@ -243,6 +246,7 @@ typedef union {
* system timer target2 interrupt clear
*/
uint32_t systimer_int2_clr: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_clr_reg_t;

1535
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/timer_group_reg.h
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File diff suppressed because it is too large Load Diff

988
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/timer_group_struct.h
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File diff suppressed because it is too large Load Diff

86
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/twai_struct.h
View File

@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
uint32_t stm: 1; /* MOD.2 Self Test Mode */
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
};
uint32_t val;
} mode_reg; /* Address 0 */
} mode_reg; /* Address 0x0000 */
union {
struct {
uint32_t tr: 1; /* CMR.0 Transmission Request */
@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; /* Address 1 */
} command_reg; /* Address 0x0004 */
union {
struct {
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
@ -61,37 +61,39 @@ typedef volatile struct twai_dev_s {
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t ms: 1; /* SR.8 Miss Status */
uint32_t reserved23: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 2 */
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_reg; /* Address 3 */
} interrupt_reg; /* Address 0x000C */
union {
struct {
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_enable_reg; /* Address 4 */
uint32_t reserved_05; /* Address 5 */
} interrupt_enable_reg; /* Address 0x0010 */
uint32_t reserved_14;
union {
struct {
uint32_t brp: 14; /* BTR0[13:0] Baud Rate Prescaler */
@ -99,58 +101,58 @@ typedef volatile struct twai_dev_s {
uint32_t reserved16: 16; /* Internal Reserved */
};
uint32_t val;
} bus_timing_0_reg; /* Address 6 */
} bus_timing_0_reg; /* Address 0x0018 */
union {
struct {
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
uint32_t sam: 1; /* BTR1.7 Sampling*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 7 */
uint32_t reserved_08; /* Address 8 (Output control not supported) */
uint32_t reserved_09; /* Address 9 (Test Register not supported) */
uint32_t reserved_10; /* Address 10 */
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
uint32_t reserved_28; /* Address 0x0028 */
//Capture and Counter Registers
union {
struct {
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} arbitration_lost_captue_reg; /* Address 11 */
} arbitration_lost_captue_reg; /* Address 0x002C */
union {
struct {
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
uint32_t errc: 2; /* ECC[7:6] Error Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_code_capture_reg; /* Address 12 */
} error_code_capture_reg; /* Address 0x0030 */
union {
struct {
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
} error_warning_limit_reg; /* Address 0x0034 */
union {
struct {
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} rx_error_counter_reg; /* Address 12 */
} rx_error_counter_reg; /* Address 0x0038 */
union {
struct {
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} tx_error_counter_reg; /* Address 15 */
} tx_error_counter_reg; /* Address 0x003C */
//Shared Registers (TX Buff/RX Buff/Acc Filter)
union {
@ -158,45 +160,49 @@ typedef volatile struct twai_dev_s {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved32[5];
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
} acceptance_filter;
union {
struct {
uint32_t byte: 8;
uint32_t reserved24: 24;
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
uint32_t reserved24: 24; /* Internal Reserved */
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 0x0040 - 0x0070 */
//Misc Registers
union {
struct {
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
uint32_t reserved25: 25; /* Internal Reserved */
uint32_t reserved7: 25; /* Internal Reserved */
};
uint32_t val;
} rx_message_counter_reg; /* Address 29 */
uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
} rx_message_counter_reg; /* Address 0x0074 */
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
union {
struct {
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
uint32_t reserved24: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 31 */
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");

43
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/uart_pins.h Normal file
View File

@ -0,0 +1,43 @@
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM (44)
#define U0TXD_GPIO_NUM (43)
#define U0RTS_GPIO_NUM (15)
#define U0CTS_GPIO_NUM (16)
#define U1RXD_GPIO_NUM (18)
#define U1TXD_GPIO_NUM (17)
#define U1RTS_GPIO_NUM (19)
#define U1CTS_GPIO_NUM (20)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD)
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
#define U0RTS_MUX_FUNC (FUNC_XTAL_32K_P_U0RTS)
#define U0CTS_MUX_FUNC (FUNC_XTAL_32K_N_U0CTS)
#define U1TXD_MUX_FUNC (FUNC_DAC_1_U1TXD)
#define U1RXD_MUX_FUNC (FUNC_DAC_2_U1RXD)
#define U1RTS_MUX_FUNC (FUNC_GPIO19_U1RTS)
#define U1CTS_MUX_FUNC (FUNC_GPIO20_U1CTS)

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/uart_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte;/*note: rw_byte is a uint8_t field, however, ESP32-S2 do not support 8 bits read/write*/

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/uhci_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uhci_dev_s {
union {
struct {
uint32_t in_rst: 1;

1
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/usb_wrap_struct.h
View File

@ -153,6 +153,7 @@ typedef union {
* USB D- rx value in test.
*/
uint32_t test_rx_dm:1;
uint32_t reserved:25;
};
uint32_t val;
} usb_wrap_test_conf_reg_t;

2
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/usbh_struct.h
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@ -830,7 +830,7 @@ typedef union {
uint32_t bbleerr: 1;
uint32_t nakintrpt: 1;
uint32_t nyetintrpt: 1;
uint32_t reserved16: 16;
uint32_t reserved15: 17;
};
uint32_t val;
} usb_diepint_reg_t;

2
tools/sdk/esp32s2/include/soc/include/soc/adc_periph.h
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@ -18,7 +18,7 @@
#include "soc/soc_caps.h"
#include "soc/syscon_struct.h"
#if SOC_ADC_SUPPORT_RTC_CTRL
#if SOC_ADC_RTC_CTRL_SUPPORTED
#include "soc/sens_reg.h"
#include "soc/sens_struct.h"
#endif

27
tools/sdk/esp32s2/include/soc/include/soc/i2s_periph.h
View File

@ -1,4 +1,4 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -27,16 +27,21 @@ extern "C" {
Stores a bunch of per-I2S-peripheral data.
*/
typedef struct {
const uint8_t o_bck_in_sig;
const uint8_t o_ws_in_sig;
const uint8_t o_bck_out_sig;
const uint8_t o_ws_out_sig;
const uint8_t o_data_out_sig;
const uint8_t i_bck_in_sig;
const uint8_t i_ws_in_sig;
const uint8_t i_bck_out_sig;
const uint8_t i_ws_out_sig;
const uint8_t i_data_in_sig;
const uint8_t mck_out_sig;
const uint8_t m_tx_bck_sig;
const uint8_t m_rx_bck_sig;
const uint8_t m_tx_ws_sig;
const uint8_t m_rx_ws_sig;
const uint8_t s_tx_bck_sig;
const uint8_t s_rx_bck_sig;
const uint8_t s_tx_ws_sig;
const uint8_t s_rx_ws_sig;
const uint8_t data_out_sig;
const uint8_t data_in_sig;
const uint8_t irq;
const periph_module_t module;
} i2s_signal_conn_t;

14
tools/sdk/esp32s2/include/soc/include/soc/lcd_periph.h
View File

@ -21,6 +21,7 @@
extern "C" {
#endif
#if SOC_LCDCAM_SUPPORTED
typedef struct {
struct {
const periph_module_t module;
@ -41,6 +42,19 @@ typedef struct {
} panels[SOC_LCD_RGB_PANELS];
} lcd_signal_conn_t;
#endif // SOC_LCDCAM_SUPPORTED
#if SOC_I2S_LCD_I80_VARIANT
typedef struct {
struct {
const periph_module_t module;
const int irq_id;
const int data_sigs[SOC_LCD_I80_BUS_WIDTH];
const int wr_sig;
} buses[SOC_LCD_I80_BUSES];
} lcd_signal_conn_t;
#endif // SOC_I2S_LCD_I80_VARIANT
extern const lcd_signal_conn_t lcd_periph_signals;
#ifdef __cplusplus

4
tools/sdk/esp32s2/include/soc/include/soc/mcpwm_periph.h
View File

@ -34,13 +34,13 @@ typedef struct {
} operators[SOC_MCPWM_OPERATORS_PER_GROUP];
struct {
const uint32_t fault_sig;
} detectors[SOC_MCPWM_FAULT_DETECTORS_PER_GROUP];
} gpio_faults[SOC_MCPWM_GPIO_FAULTS_PER_GROUP];
struct {
const uint32_t cap_sig;
} captures[SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER];
struct {
const uint32_t sync_sig;
} ext_syncers[SOC_MCPWM_EXT_SYNCERS_PER_GROUP];
} gpio_synchros[SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP];
} groups[SOC_MCPWM_GROUPS];
} mcpwm_signal_conn_t;

16
tools/sdk/esp32s2/include/soc/include/soc/pcnt_periph.h
View File

@ -1,4 +1,4 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -27,12 +27,14 @@ extern "C" {
typedef struct {
struct {
struct {
const uint32_t pulse_sig;
const uint32_t control_sig;
} channels[SOC_PCNT_UNIT_CHANNEL_NUM];
} units[SOC_PCNT_UNIT_NUM];
const uint32_t irq;
const periph_module_t module;
struct {
const uint32_t pulse_sig;
const uint32_t control_sig;
} channels[SOC_PCNT_CHANNELS_PER_UNIT];
} units[SOC_PCNT_UNITS_PER_GROUP];
const uint32_t irq;
const periph_module_t module;
} groups[SOC_PCNT_GROUPS];
} pcnt_signal_conn_t;
extern const pcnt_signal_conn_t pcnt_periph_signals;

2
tools/sdk/esp32s2/include/soc/include/soc/rtc_io_periph.h
View File

@ -27,7 +27,7 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_cntl_struct.h"
#if SOC_ADC_SUPPORT_RTC_CTRL
#if SOC_ADC_RTC_CTRL_SUPPORTED
#include "soc/sens_struct.h"
#endif

3
tools/sdk/esp32s2/include/soc/include/soc/sdio_slave_periph.h
View File

@ -15,9 +15,12 @@
#pragma once
#include <stdint.h>
//include soc related (generated) definitions
#include "soc/soc_caps.h"
#include "soc/soc_pins.h"
#ifdef SOC_SDIO_SLAVE_SUPPORTED
#include "soc/slc_reg.h"
#include "soc/slc_struct.h"
#endif
#include "soc/host_reg.h"
#include "soc/host_struct.h"
#include "soc/hinf_reg.h"

17
tools/sdk/esp32s2/include/soc/include/soc/spi_periph.h
View File

@ -30,8 +30,7 @@
#endif
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
#if CONFIG_IDF_TARGET_ESP32S2
@ -41,8 +40,6 @@ extern "C"
#define SPI_FWRITE_QIO 0
#endif
/*
Stores a bunch of per-spi-peripheral data.
*/
@ -53,10 +50,22 @@ typedef struct {
const uint8_t spiq_out;
const uint8_t spiwp_out;
const uint8_t spihd_out;
#if SOC_SPI_SUPPORT_OCT
const uint8_t spid4_out;
const uint8_t spid5_out;
const uint8_t spid6_out;
const uint8_t spid7_out;
#endif // SOC_SPI_SUPPORT_OCT
const uint8_t spid_in; //GPIO mux input signals
const uint8_t spiq_in;
const uint8_t spiwp_in;
const uint8_t spihd_in;
#if SOC_SPI_SUPPORT_OCT
const uint8_t spid4_in;
const uint8_t spid5_in;
const uint8_t spid6_in;
const uint8_t spid7_in;
#endif // SOC_SPI_SUPPORT_OCT
const uint8_t spics_out[3]; // /CS GPIO output mux signals
const uint8_t spics_in;
const uint8_t spidqs_out;

32
tools/sdk/esp32s2/include/soc/include/soc/uart_periph.h
View File

@ -18,16 +18,40 @@
#include "soc/uart_struct.h"
#include "soc/periph_defs.h"
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
#include "soc/uart_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_UART_TX_PIN_IDX (0)
#define SOC_UART_RX_PIN_IDX (1)
#define SOC_UART_RTS_PIN_IDX (2)
#define SOC_UART_CTS_PIN_IDX (3)
/**
* @brief Macro that can be used to retrieve the signal of a certain pin for a
* certain UART.
*/
#define UART_PERIPH_SIGNAL(IDX, PIN) (uart_periph_signal[(IDX)].pins[(PIN)].signal)
typedef struct {
const uint8_t tx_sig;
const uint8_t rx_sig;
const uint8_t rts_sig;
const uint8_t cts_sig;
/* Default GPIO number for this UART pin in the IOMUX.
* This value can be -1 if there is no default GPIO for a pin.
* For example, ESP32-C3 doesn't have any default GPIO for
* U0CTS and U0RTS. */
int32_t default_gpio : 15;
/* Func which should be assigned to the GPIO to be used as UART */
int32_t iomux_func : 4;
/* Marks if the current UART pin is input (or not) */
uint32_t input : 1;
/* Signal in the GPIO signal map. */
uint32_t signal : 12;
} uart_periph_sig_t;
typedef struct {
const uart_periph_sig_t pins[SOC_UART_PINS_COUNT];
const uint8_t irq;
const periph_module_t module;
} uart_signal_conn_t;

35
tools/sdk/esp32s2/include/soc/include/soc/usb_phy_periph.h Normal file
View File

@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
Stores a bunch of USB-peripheral data.
*/
typedef struct {
const uint8_t extphy_vp_in;
const uint8_t extphy_vm_in;
const uint8_t extphy_rcv_in;
const uint8_t extphy_oen_out;
const uint8_t extphy_vpo_out;
const uint8_t extphy_vmo_out;
const uint8_t extphy_suspend_in;
const uint8_t extphy_speed_in;
const periph_module_t module;
} usb_phy_signal_conn_t;
extern const usb_phy_signal_conn_t usb_phy_periph_signal;
#ifdef __cplusplus
}
#endif