mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
synced 2025-07-01 04:50:58 +02:00
Update IDF to abea9e4c0 (#2458)
* Update IDF to abea9e4c0 * Update esptool * Enable PSRAM for PICO D4 * Enable APP_ROLLBACK_ENABLE
This commit is contained in:
Me No Dev
GitHub
@ -15,68 +15,88 @@
|
||||
#ifndef __ESP_ETH_H__
|
||||
#define __ESP_ETH_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "esp_err.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "esp_types.h"
|
||||
#include "esp_err.h"
|
||||
|
||||
/**
|
||||
* @brief Ethernet interface mode
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
ETH_MODE_RMII = 0,
|
||||
ETH_MODE_MII,
|
||||
ETH_MODE_RMII = 0, /*!< RMII mode */
|
||||
ETH_MODE_MII, /*!< MII mode */
|
||||
} eth_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Ethernet clock mode
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
ETH_CLOCK_GPIO0_IN = 0,
|
||||
ETH_CLOCK_GPIO16_OUT = 2,
|
||||
ETH_CLOCK_GPIO17_OUT = 3
|
||||
ETH_CLOCK_GPIO0_IN = 0, /*!< RMII clock input to GPIO0 */
|
||||
ETH_CLOCK_GPIO0_OUT = 1, /*!< RMII clock output from GPIO0 */
|
||||
ETH_CLOCK_GPIO16_OUT = 2, /*!< RMII clock output from GPIO16 */
|
||||
ETH_CLOCK_GPIO17_OUT = 3 /*!< RMII clock output from GPIO17 */
|
||||
} eth_clock_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Ethernet Speed
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
ETH_SPEED_MODE_10M = 0,
|
||||
ETH_SPEED_MODE_100M,
|
||||
ETH_SPEED_MODE_10M = 0, /*!< Ethernet speed: 10Mbps */
|
||||
ETH_SPEED_MODE_100M, /*!< Ethernet speed: 100Mbps */
|
||||
} eth_speed_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Ethernet Duplex
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
ETH_MODE_HALFDUPLEX = 0,
|
||||
ETH_MODE_FULLDUPLEX,
|
||||
ETH_MODE_HALFDUPLEX = 0, /*!< Ethernet half duplex */
|
||||
ETH_MODE_FULLDUPLEX, /*!< Ethernet full duplex */
|
||||
} eth_duplex_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Ethernet PHY address
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
PHY0 = 0,
|
||||
PHY1,
|
||||
PHY2,
|
||||
PHY3,
|
||||
PHY4,
|
||||
PHY5,
|
||||
PHY6,
|
||||
PHY7,
|
||||
PHY8,
|
||||
PHY9,
|
||||
PHY10,
|
||||
PHY11,
|
||||
PHY12,
|
||||
PHY13,
|
||||
PHY14,
|
||||
PHY15,
|
||||
PHY16,
|
||||
PHY17,
|
||||
PHY18,
|
||||
PHY19,
|
||||
PHY20,
|
||||
PHY21,
|
||||
PHY22,
|
||||
PHY23,
|
||||
PHY24,
|
||||
PHY25,
|
||||
PHY26,
|
||||
PHY27,
|
||||
PHY28,
|
||||
PHY29,
|
||||
PHY30,
|
||||
PHY31,
|
||||
PHY0 = 0, /*!< PHY address 0 */
|
||||
PHY1, /*!< PHY address 1 */
|
||||
PHY2, /*!< PHY address 2 */
|
||||
PHY3, /*!< PHY address 3 */
|
||||
PHY4, /*!< PHY address 4 */
|
||||
PHY5, /*!< PHY address 5 */
|
||||
PHY6, /*!< PHY address 6 */
|
||||
PHY7, /*!< PHY address 7 */
|
||||
PHY8, /*!< PHY address 8 */
|
||||
PHY9, /*!< PHY address 9 */
|
||||
PHY10, /*!< PHY address 10 */
|
||||
PHY11, /*!< PHY address 11 */
|
||||
PHY12, /*!< PHY address 12 */
|
||||
PHY13, /*!< PHY address 13 */
|
||||
PHY14, /*!< PHY address 14 */
|
||||
PHY15, /*!< PHY address 15 */
|
||||
PHY16, /*!< PHY address 16 */
|
||||
PHY17, /*!< PHY address 17 */
|
||||
PHY18, /*!< PHY address 18 */
|
||||
PHY19, /*!< PHY address 19 */
|
||||
PHY20, /*!< PHY address 20 */
|
||||
PHY21, /*!< PHY address 21 */
|
||||
PHY22, /*!< PHY address 22 */
|
||||
PHY23, /*!< PHY address 23 */
|
||||
PHY24, /*!< PHY address 24 */
|
||||
PHY25, /*!< PHY address 25 */
|
||||
PHY26, /*!< PHY address 26 */
|
||||
PHY27, /*!< PHY address 27 */
|
||||
PHY28, /*!< PHY address 28 */
|
||||
PHY29, /*!< PHY address 29 */
|
||||
PHY30, /*!< PHY address 30 */
|
||||
PHY31 /*!< PHY address 31 */
|
||||
} eth_phy_base_t;
|
||||
|
||||
typedef bool (*eth_phy_check_link_func)(void);
|
||||
@ -94,15 +114,15 @@ typedef void (*eth_phy_power_enable_func)(bool enable);
|
||||
*
|
||||
*/
|
||||
typedef struct {
|
||||
eth_phy_base_t phy_addr; /*!< phy base addr (0~31) */
|
||||
eth_mode_t mac_mode; /*!< mac mode only support RMII now */
|
||||
eth_clock_mode_t clock_mode; /*!< external/internal clock mode selecton */
|
||||
eth_tcpip_input_func tcpip_input; /*!< tcpip input func */
|
||||
eth_phy_func phy_init; /*!< phy init func */
|
||||
eth_phy_check_link_func phy_check_link; /*!< phy check link func */
|
||||
eth_phy_check_init_func phy_check_init; /*!< phy check init func */
|
||||
eth_phy_get_speed_mode_func phy_get_speed_mode; /*!< phy check init func */
|
||||
eth_phy_get_duplex_mode_func phy_get_duplex_mode; /*!< phy check init func */
|
||||
eth_phy_base_t phy_addr; /*!< PHY address (0~31) */
|
||||
eth_mode_t mac_mode; /*!< MAC mode: only support RMII now */
|
||||
eth_clock_mode_t clock_mode; /*!< external/internal clock mode selection */
|
||||
eth_tcpip_input_func tcpip_input; /*!< tcpip input func */
|
||||
eth_phy_func phy_init; /*!< phy init func */
|
||||
eth_phy_check_link_func phy_check_link; /*!< phy check link func */
|
||||
eth_phy_check_init_func phy_check_init; /*!< phy check init func */
|
||||
eth_phy_get_speed_mode_func phy_get_speed_mode; /*!< phy check init func */
|
||||
eth_phy_get_duplex_mode_func phy_get_duplex_mode; /*!< phy check init func */
|
||||
eth_gpio_config_func gpio_config; /*!< gpio config func */
|
||||
bool flow_ctrl_enable; /*!< flag of flow ctrl enable */
|
||||
eth_phy_get_partner_pause_enable_func phy_get_partner_pause_enable; /*!< get partner pause enable */
|
||||
|
||||
@ -20,38 +20,55 @@ extern "C" {
|
||||
|
||||
#include "esp_eth.h"
|
||||
|
||||
/** Common PHY-management functions.
|
||||
/**
|
||||
* @brief Common PHY-management functions.
|
||||
*
|
||||
* @note These are not enough to drive any particular Ethernet PHY.
|
||||
* They provide a common configuration structure and management functions.
|
||||
*
|
||||
*/
|
||||
|
||||
These are not enough to drive any particular Ethernet PHY, but they provide a common configuration structure and
|
||||
management functions.
|
||||
*/
|
||||
|
||||
/** Configure fixed pins for RMII data interface.
|
||||
|
||||
This configures GPIOs 0, 19, 22, 25, 26, 27 for use with RMII
|
||||
data interface. These pins cannot be changed, and must be wired to
|
||||
ethernet functions.
|
||||
|
||||
This is not sufficient to fully configure the Ethernet PHY,
|
||||
MDIO configuration interface pins (such as SMI MDC, MDO, MDI)
|
||||
must also be configured correctly in the GPIO matrix.
|
||||
*/
|
||||
/**
|
||||
* @brief Configure fixed pins for RMII data interface.
|
||||
*
|
||||
* @note This configures GPIOs 0, 19, 22, 25, 26, 27 for use with RMII data interface.
|
||||
* These pins cannot be changed, and must be wired to ethernet functions.
|
||||
* This is not sufficient to fully configure the Ethernet PHY.
|
||||
* MDIO configuration interface pins (such as SMI MDC, MDO, MDI) must also be configured correctly in the GPIO matrix.
|
||||
*
|
||||
*/
|
||||
void phy_rmii_configure_data_interface_pins(void);
|
||||
|
||||
/** Configure variable pins for SMI (MDIO) ethernet functions.
|
||||
|
||||
Calling this function along with mii_configure_default_pins() will
|
||||
fully configure the GPIOs for the ethernet PHY.
|
||||
/**
|
||||
* @brief Configure variable pins for SMI ethernet functions.
|
||||
*
|
||||
* @param mdc_gpio MDC GPIO Pin number
|
||||
* @param mdio_gpio MDIO GPIO Pin number
|
||||
*
|
||||
* @note Calling this function along with mii_configure_default_pins() will fully configure the GPIOs for the ethernet PHY.
|
||||
*/
|
||||
void phy_rmii_smi_configure_pins(uint8_t mdc_gpio, uint8_t mdio_gpio);
|
||||
|
||||
|
||||
/** Enable flow control in standard PHY MII register.
|
||||
/**
|
||||
* @brief Enable flow control in standard PHY MII register.
|
||||
*
|
||||
*/
|
||||
void phy_mii_enable_flow_ctrl(void);
|
||||
|
||||
/**
|
||||
* @brief Check Ethernet link status via MII interface
|
||||
*
|
||||
* @return true Link is on
|
||||
* @return false Link is off
|
||||
*/
|
||||
bool phy_mii_check_link_status(void);
|
||||
|
||||
/**
|
||||
* @brief Check pause frame ability of partner via MII interface
|
||||
*
|
||||
* @return true Partner is able to process pause frame
|
||||
* @return false Partner can not process pause frame
|
||||
*/
|
||||
bool phy_mii_get_partner_pause_enable(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
75
tools/sdk/include/ethernet/eth_phy/phy_ip101.h
Normal file
75
tools/sdk/include/ethernet/eth_phy/phy_ip101.h
Normal file
@ -0,0 +1,75 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "phy.h"
|
||||
|
||||
/**
|
||||
* @brief Dump IP101 PHY SMI configuration registers
|
||||
*
|
||||
*/
|
||||
void phy_ip101_dump_registers();
|
||||
|
||||
/**
|
||||
* @brief Default IP101 phy_check_init function
|
||||
*
|
||||
*/
|
||||
void phy_ip101_check_phy_init(void);
|
||||
|
||||
/**
|
||||
* @brief Default IP101 phy_get_speed_mode function
|
||||
*
|
||||
* @return eth_speed_mode_t Ethernet speed mode
|
||||
*/
|
||||
eth_speed_mode_t phy_ip101_get_speed_mode(void);
|
||||
|
||||
/**
|
||||
* @brief Default IP101 phy_get_duplex_mode function
|
||||
*
|
||||
* @return eth_duplex_mode_t Ethernet duplex mode
|
||||
*/
|
||||
eth_duplex_mode_t phy_ip101_get_duplex_mode(void);
|
||||
|
||||
/**
|
||||
* @brief Default IP101 phy_power_enable function
|
||||
*
|
||||
*/
|
||||
void phy_ip101_power_enable(bool);
|
||||
|
||||
/**
|
||||
* @brief Default IP101 phy_init function
|
||||
*
|
||||
* @return esp_err_t
|
||||
* - ESP_OK on success
|
||||
* - ESP_FAIL on error
|
||||
*/
|
||||
esp_err_t phy_ip101_init(void);
|
||||
|
||||
/**
|
||||
* @brief Default IP101 PHY configuration
|
||||
*
|
||||
* @note This configuration is not suitable for use as-is,
|
||||
* it will need to be modified for your particular PHY hardware setup.
|
||||
*
|
||||
*/
|
||||
extern const eth_config_t phy_ip101_default_ethernet_config;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -20,45 +20,53 @@ extern "C" {
|
||||
|
||||
#include "phy.h"
|
||||
|
||||
|
||||
/** @brief Dump all LAN8720 PHY SMI configuration registers
|
||||
/**
|
||||
* @brief Dump LAN8720 PHY SMI configuration registers
|
||||
*
|
||||
* @note These registers are dumped at 'debug' level, so output
|
||||
* may not be visible depending on default log levels.
|
||||
*/
|
||||
void phy_lan8720_dump_registers();
|
||||
|
||||
/** @brief Default LAN8720 phy_check_init function.
|
||||
/**
|
||||
* @brief Default LAN8720 phy_check_init function
|
||||
*
|
||||
*/
|
||||
void phy_lan8720_check_phy_init(void);
|
||||
|
||||
/** @brief Default LAN8720 phy_get_speed_mode function.
|
||||
/**
|
||||
* @brief Default LAN8720 phy_get_speed_mode function
|
||||
*
|
||||
* @return eth_speed_mode_t Ethernet speed mode
|
||||
*/
|
||||
eth_speed_mode_t phy_lan8720_get_speed_mode(void);
|
||||
|
||||
/** @brief Default LAN8720 phy_get_duplex_mode function.
|
||||
/**
|
||||
* @brief Default LAN8720 phy_get_duplex_mode function
|
||||
*
|
||||
* @return eth_duplex_mode_t Ethernet duplex mode
|
||||
*/
|
||||
eth_duplex_mode_t phy_lan8720_get_duplex_mode(void);
|
||||
|
||||
/** @brief Default LAN8720 phy_power_enable function.
|
||||
/**
|
||||
* @brief Default LAN8720 phy_power_enable function
|
||||
*
|
||||
* @note This function may need to be replaced with a custom function
|
||||
* if the PHY has a GPIO to enable power or start a clock.
|
||||
*
|
||||
* Consult the ethernet example to see how this is done.
|
||||
*/
|
||||
void phy_lan8720_power_enable(bool);
|
||||
|
||||
/** @brief Default LAN8720 phy_init function.
|
||||
/**
|
||||
* @brief Default LAN8720 phy_init function
|
||||
*
|
||||
* @return esp_err_t
|
||||
* - ESP_OK on success
|
||||
* - ESP_FAIL on error
|
||||
*/
|
||||
esp_err_t phy_lan8720_init(void);
|
||||
|
||||
/** @brief Default LAN8720 PHY configuration
|
||||
/**
|
||||
* @brief Default LAN8720 PHY configuration
|
||||
*
|
||||
* This configuration is not suitable for use as-is, it will need
|
||||
* to be modified for your particular PHY hardware setup.
|
||||
* @note This configuration is not suitable for use as-is,
|
||||
* it will need to be modified for your particular PHY hardware setup.
|
||||
*
|
||||
* Consult the Ethernet example to see how this is done.
|
||||
*/
|
||||
extern const eth_config_t phy_lan8720_default_ethernet_config;
|
||||
|
||||
|
||||
@ -18,9 +18,10 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* This header contains register/bit masks for the standard
|
||||
PHY MII registers that should be supported by all PHY models.
|
||||
*/
|
||||
/**
|
||||
* @brief This header contains register/bit masks for the standard PHY MII registers that should be supported by all PHY models.
|
||||
*
|
||||
*/
|
||||
|
||||
#define MII_BASIC_MODE_CONTROL_REG (0x0)
|
||||
#define MII_SOFTWARE_RESET BIT(15)
|
||||
|
||||
@ -20,44 +20,53 @@ extern "C" {
|
||||
|
||||
#include "phy.h"
|
||||
|
||||
/** @brief Dump all TLK110 PHY SMI configuration registers
|
||||
/**
|
||||
* @brief Dump TLK110 PHY SMI configuration registers
|
||||
*
|
||||
* @note These registers are dumped at 'debug' level, so output
|
||||
* may not be visible depending on default log levels.
|
||||
*/
|
||||
void phy_tlk110_dump_registers();
|
||||
|
||||
/** @brief Default TLK110 phy_check_init function.
|
||||
/**
|
||||
* @brief Default TLK110 phy_check_init function
|
||||
*
|
||||
*/
|
||||
void phy_tlk110_check_phy_init(void);
|
||||
|
||||
/** @brief Default TLK110 phy_get_speed_mode function.
|
||||
/**
|
||||
* @brief Default TLK110 phy_get_speed_mode function
|
||||
*
|
||||
* @return eth_speed_mode_t Ethernet speed mode
|
||||
*/
|
||||
eth_speed_mode_t phy_tlk110_get_speed_mode(void);
|
||||
|
||||
/** @brief Default TLK110 phy_get_duplex_mode function.
|
||||
/**
|
||||
* @brief Default TLK110 phy_get_duplex_mode function
|
||||
*
|
||||
* @return eth_duplex_mode_t Ethernet duplex mode
|
||||
*/
|
||||
eth_duplex_mode_t phy_tlk110_get_duplex_mode(void);
|
||||
|
||||
/** @brief Default TLK110 phy_power_enable function.
|
||||
/**
|
||||
* @brief Default TLK110 phy_power_enable function
|
||||
*
|
||||
* @note This function may need to be replaced with a custom function
|
||||
* if the PHY has a GPIO to enable power or start a clock.
|
||||
*
|
||||
* Consult the ethernet example to see how this is done.
|
||||
*/
|
||||
void phy_tlk110_power_enable(bool);
|
||||
|
||||
/** @brief Default TLK110 phy_init function.
|
||||
/**
|
||||
* @brief Default TLK110 phy_init function
|
||||
*
|
||||
* @return esp_err_t
|
||||
* - ESP_OK on success
|
||||
* - ESP_FAIL on error
|
||||
*/
|
||||
esp_err_t phy_tlk110_init(void);
|
||||
|
||||
/** @brief Default TLK110 PHY configuration
|
||||
/**
|
||||
* @brief Default TLK110 PHY configuration
|
||||
*
|
||||
* This configuration is not suitable for use as-is, it will need
|
||||
* to be modified for your particular PHY hardware setup.
|
||||
* @note This configuration is not suitable for use as-is,
|
||||
* it will need to be modified for your particular PHY hardware setup.
|
||||
*
|
||||
* Consult the Ethernet example to see how this is done.
|
||||
*/
|
||||
extern const eth_config_t phy_tlk110_default_ethernet_config;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user