mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
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Update IDF to a0468b2 (#2108)
* Update IDF to a0468b2 * add missing ld file * Fix PIO builds and change coex policy
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@ -19,6 +19,7 @@
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#include <stdbool.h>
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#include <stddef.h>
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#include "xtensa/corebits.h"
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#include "xtensa/config/core.h"
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/* C macros for xtensa special register read/write/exchange */
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@ -51,6 +52,14 @@ static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
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asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
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}
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static inline void cpu_init_memctl()
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{
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#if XCHAL_ERRATUM_572
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uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
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WSR(MEMCTL, memctl);
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#endif // XCHAL_ERRATUM_572
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}
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/**
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* @brief Configure memory region protection
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*
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@ -298,6 +298,9 @@
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#define EFUSE_RD_CODING_SCHEME_V 0x3
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#define EFUSE_RD_CODING_SCHEME_S 0
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#define EFUSE_CODING_SCHEME_VAL_NONE 0x0
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#define EFUSE_CODING_SCHEME_VAL_34 0x1
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#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c)
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/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[27:20] ;default: 8'b0 ; */
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/*description: program for flash_crypt_cnt*/
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@ -52,6 +52,9 @@ typedef enum {
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PERIPH_WIFI_BT_COMMON_MODULE,
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PERIPH_BT_BASEBAND_MODULE,
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PERIPH_BT_LC_MODULE,
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PERIPH_AES_MODULE,
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PERIPH_SHA_MODULE,
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PERIPH_RSA_MODULE,
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} periph_module_t;
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#ifdef __cplusplus
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@ -59,16 +59,18 @@
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#define APP_CPU_NUM (1)
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/* Overall memory map */
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_DROM_LOW 0x3F400000
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#define SOC_DROM_HIGH 0x3F800000
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#define SOC_RTC_IRAM_LOW 0x400C0000
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#define SOC_RTC_IRAM_HIGH 0x400C2000
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#define SOC_RTC_DATA_LOW 0x50000000
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#define SOC_RTC_DATA_HIGH 0x50002000
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#define SOC_EXTRAM_DATA_LOW 0x3F800000
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#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_DROM_LOW 0x3F400000
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#define SOC_DROM_HIGH 0x3F800000
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#define SOC_DRAM_LOW 0x3FAE0000
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#define SOC_DRAM_HIGH 0x40000000
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#define SOC_RTC_IRAM_LOW 0x400C0000
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#define SOC_RTC_IRAM_HIGH 0x400C2000
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#define SOC_RTC_DATA_LOW 0x50000000
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#define SOC_RTC_DATA_HIGH 0x50002000
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#define SOC_EXTRAM_DATA_LOW 0x3F800000
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#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
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#define DR_REG_DPORT_BASE 0x3ff00000
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@ -130,7 +132,7 @@
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#ifndef __ASSEMBLER__
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#define BIT(nr) (1UL << (nr))
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@ -284,10 +286,16 @@
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#define SOC_DROM_HIGH 0x3F800000
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_CACHE_PRO_LOW 0x40070000
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#define SOC_CACHE_PRO_HIGH 0x40078000
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#define SOC_CACHE_APP_LOW 0x40078000
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#define SOC_CACHE_APP_HIGH 0x40080000
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#define SOC_IRAM_LOW 0x40080000
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#define SOC_IRAM_HIGH 0x400A0000
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#define SOC_RTC_IRAM_LOW 0x400C0000
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#define SOC_RTC_IRAM_HIGH 0x400C2000
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#define SOC_RTC_DRAM_LOW 0x3FF80000
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#define SOC_RTC_DRAM_HIGH 0x3FF82000
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#define SOC_RTC_DATA_LOW 0x50000000
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#define SOC_RTC_DATA_HIGH 0x50002000
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@ -173,3 +173,19 @@ inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
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inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) {
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return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
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}
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inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) {
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#ifndef CONFIG_FREERTOS_UNICORE
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return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
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#else
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return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
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#endif
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}
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inline static bool IRAM_ATTR esp_ptr_in_drom(const void *p) {
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return ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < SOC_DROM_HIGH);
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}
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inline static bool IRAM_ATTR esp_ptr_in_dram(const void *p) {
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return ((intptr_t)p >= SOC_DRAM_LOW && (intptr_t)p < SOC_DRAM_HIGH);
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}
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