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me-no-dev
2020-05-09 19:11:30 +03:00
parent ebe0d9a6cb
commit 0a262244e6
4324 changed files with 645232 additions and 253864 deletions
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tools/sdk/esp32s2/include/soc/include/hal/adc_hal.h
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#pragma once
#include "hal/adc_types.h"
#include "hal/adc_ll.h"
/*---------------------------------------------------------------
Common setting
---------------------------------------------------------------*/
/**
* ADC module initialization.
*/
void adc_hal_init(void);
/**
* ADC module deinitialization.
*/
void adc_hal_deinit(void);
/**
* Set adc sample cycle for digital controller.
*
* @note Normally, please use default value.
* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
* Range: 2 ~ 0xFF.
*/
#define adc_hal_digi_set_sample_cycle(sample_cycle) adc_ll_digi_set_sample_cycle(sample_cycle)
/**
* Set ADC module power management.
*
* @prarm manage Set ADC power status.
*/
#define adc_hal_set_power_manage(manage) adc_ll_set_power_manage(manage)
/**
* Get ADC module power management.
*
* @return
* - ADC power status.
*/
#define adc_hal_get_power_manage() adc_ll_get_power_manage()
/**
* ADC module clock division factor setting. ADC clock devided from APB clock.
*
* @prarm div Division factor.
*/
#define adc_hal_digi_set_clk_div(div) adc_ll_digi_set_clk_div(div)
/**
* ADC SAR clock division factor setting. ADC SAR clock devided from `RTC_FAST_CLK`.
*
* @prarm div Division factor.
*/
#define adc_hal_set_sar_clk_div(adc_n, div) adc_ll_set_sar_clk_div(adc_n, div)
/**
* Set ADC module controller.
* There are five SAR ADC controllers:
* Two digital controller: Continuous conversion mode (DMA). High performance with multiple channel scan modes;
* Two RTC controller: Single conversion modes (Polling). For low power purpose working during deep sleep;
* the other is dedicated for Power detect (PWDET / PKDET), Only support ADC2.
*
* @prarm adc_n ADC unit.
* @prarm ctrl ADC controller.
*/
#define adc_hal_set_controller(adc_n, ctrl) adc_ll_set_controller(adc_n, ctrl)
/**
* Set the attenuation of a particular channel on ADCn.
*
* @note For any given channel, this function must be called before the first time conversion.
*
* The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage,
* usually 3.3V) requires setting >0dB signal attenuation for that ADC channel.
*
* When VDD_A is 3.3V:
*
* - 0dB attenuaton (ADC_ATTEN_DB_0) gives full-scale voltage 1.1V
* - 2.5dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5V
* - 6dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2V
* - 11dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9V (see note below)
*
* @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured
* bit width, this value is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.)
*
* @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage.
*
* Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges:
*
* - 0dB attenuaton (ADC_ATTEN_DB_0) between 100 and 950mV
* - 2.5dB attenuation (ADC_ATTEN_DB_2_5) between 100 and 1250mV
* - 6dB attenuation (ADC_ATTEN_DB_6) between 150 to 1750mV
* - 11dB attenuation (ADC_ATTEN_DB_11) between 150 to 2450mV
*
* For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges.
*
* @prarm adc_n ADC unit.
* @prarm channel ADCn channel number.
* @prarm atten The attenuation option.
*/
#define adc_hal_set_atten(adc_n, channel, atten) adc_ll_set_atten(adc_n, channel, atten)
/**
* Get the attenuation of a particular channel on ADCn.
*
* @param adc_n ADC unit.
* @param channel ADCn channel number.
* @return atten The attenuation option.
*/
#define adc_hal_get_atten(adc_n, channel) adc_ll_get_atten(adc_n, channel)
/**
* Close ADC AMP module if don't use it for power save.
*/
#define adc_hal_amp_disable() adc_ll_amp_disable()
/*---------------------------------------------------------------
PWDET(Power detect) controller setting
---------------------------------------------------------------*/
/**
* Set adc cct for PWDET controller.
*
* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
* @prarm cct Range: 0 ~ 7.
*/
#define adc_hal_pwdet_set_cct(cct) adc_ll_pwdet_set_cct(cct)
/**
* Get adc cct for PWDET controller.
*
* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
* @return cct Range: 0 ~ 7.
*/
#define adc_hal_pwdet_get_cct() adc_ll_pwdet_get_cct()
/*---------------------------------------------------------------
RTC controller setting
---------------------------------------------------------------*/
/**
* Get the converted value for each ADCn for RTC controller.
*
* @note It may be block to wait conversion finish.
*
* @prarm adc_n ADC unit.
* @param channel adc channel number.
* @param value Pointer for touch value.
*
* @return
* - 0: The value is valid.
* - ~0: The value is invalid.
*/
int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value);
/**
* Set adc output data format for RTC controller.
*
* @prarm adc_n ADC unit.
* @prarm bits Output data bits width option.
*/
#define adc_hal_rtc_set_output_format(adc_n, bits) adc_ll_rtc_set_output_format(adc_n, bits)
/**
* ADC module output data invert or not.
*
* @prarm adc_n ADC unit.
*/
#define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en)
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
*
* @param adc_n ADC unit.
*/
#define adc_hal_digi_clear_pattern_table(adc_n) adc_ll_digi_clear_pattern_table(adc_n)
tools/sdk/esp32s2/include/soc/include/hal/adc_types.h
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#pragma once
#include "soc/adc_caps.h"
#include "sdkconfig.h"
#include <stdbool.h>
/**
* @brief ADC units selected handle.
*
* @note For ADC digital controller(DMA mode), ESP32 don't support `ADC_UNIT_2`, `ADC_UNIT_BOTH`, `ADC_UNIT_ALTER`.
*/
typedef enum {
ADC_UNIT_1 = 1, /*!< SAR ADC 1. */
ADC_UNIT_2 = 2, /*!< SAR ADC 2. */
ADC_UNIT_BOTH = 3, /*!< SAR ADC 1 and 2. */
ADC_UNIT_ALTER = 7, /*!< SAR ADC 1 and 2 alternative mode, not supported yet */
ADC_UNIT_MAX,
} adc_unit_t;
/**
* @brief ADC channels handle. See ``adc1_channel_t``, ``adc2_channel_t``.
*
* @note For ESP32 ADC1, don't support `ADC_CHANNEL_8`, `ADC_CHANNEL_9`. See ``adc1_channel_t``.
*/
typedef enum {
ADC_CHANNEL_0 = 0, /*!< ADC channel */
ADC_CHANNEL_1, /*!< ADC channel */
ADC_CHANNEL_2, /*!< ADC channel */
ADC_CHANNEL_3, /*!< ADC channel */
ADC_CHANNEL_4, /*!< ADC channel */
ADC_CHANNEL_5, /*!< ADC channel */
ADC_CHANNEL_6, /*!< ADC channel */
ADC_CHANNEL_7, /*!< ADC channel */
ADC_CHANNEL_8, /*!< ADC channel */
ADC_CHANNEL_9, /*!< ADC channel */
ADC_CHANNEL_MAX,
} adc_channel_t;
/**
* @brief ADC attenuation parameter. Different parameters determine the range of the ADC. See ``adc1_config_channel_atten``.
*/
typedef enum {
ADC_ATTEN_DB_0 = 0, /*!<The input voltage of ADC will be reduced to about 1/1 */
ADC_ATTEN_DB_2_5 = 1, /*!<The input voltage of ADC will be reduced to about 1/1.34 */
ADC_ATTEN_DB_6 = 2, /*!<The input voltage of ADC will be reduced to about 1/2 */
ADC_ATTEN_DB_11 = 3, /*!<The input voltage of ADC will be reduced to about 1/3.6*/
ADC_ATTEN_MAX,
} adc_atten_t;
/**
* @brief ESP32 ADC DMA source selection.
*
* @note It's be deprecated in ESP32S2. Beacause ESP32S2 don't use I2S DMA.
*/
typedef enum {
ADC_I2S_DATA_SRC_IO_SIG = 0, /*!< I2S data from GPIO matrix signal */
ADC_I2S_DATA_SRC_ADC = 1, /*!< I2S data from ADC */
ADC_I2S_DATA_SRC_MAX,
} adc_i2s_source_t;
/**
* @brief ADC resolution setting option.
*
* @note For ESP32S2. Only support 13 bit resolution.
* For ESP32. Don't support 13 bit resolution.
*/
typedef enum {
ADC_WIDTH_BIT_9 = 0, /*!< ADC capture width is 9Bit. Only ESP32 is supported. */
ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit. Only ESP32 is supported. */
ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit. Only ESP32 is supported. */
ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. Only ESP32 is supported. */
#ifdef CONFIG_IDF_TARGET_ESP32S2
ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. Only ESP32S2 is supported. */
#endif
ADC_WIDTH_MAX,
} adc_bits_width_t;
#ifdef CONFIG_IDF_TARGET_ESP32S2
/**
* @brief ADC digital controller (DMA mode) clock system setting.
* Expression: controller_clk = (`APLL` or `APB`) * (div_num + div_b / div_a).
*/
typedef struct {
bool use_apll; /*!<true: use APLL clock; false: use APB clock. */
uint32_t div_num; /*!<Division factor. Range: 1 ~ 255. */
uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */
uint32_t div_a; /*!<Division factor. Range: 1 ~ 63. */
} adc_digi_clk_t;
/**
* @brief ADC digital controller (DMA mode) clock system default setting.
*/
#define ADC_DIGITAL_CLK_DEFAULT() { \
.use_apll = 0, \
.div_num = 40, \
.div_b = 1, \
.div_a = 1, \
}
/**
* @brief ADC arbiter work mode option.
*
* @note ESP32S2: Only ADC2 support arbiter.
*/
typedef enum {
ADC_ARB_MODE_SHIELD,/*!<Force shield arbiter, Select the highest priority controller to work. */
ADC_ARB_MODE_FIX, /*!<Fixed priority switch controller mode. */
ADC_ARB_MODE_LOOP, /*!<Loop priority switch controller mode. Each controller has the same priority,
and the arbiter will switch to the next controller after the measurement is completed. */
} adc_arbiter_mode_t;
/**
* @brief ADC arbiter work mode and priority setting.
*
* @note ESP32S2: Only ADC2 support arbiter.
*/
typedef struct {
adc_arbiter_mode_t mode; /*!<Refer to `adc_arbiter_mode_t`. Note: only support ADC2. */
uint8_t rtc_pri; /*!<RTC controller priority. Range: 0 ~ 2. */
uint8_t dig_pri; /*!<Digital controller priority. Range: 0 ~ 2. */
uint8_t pwdet_pri; /*!<Wi-Fi controller priority. Range: 0 ~ 2. */
} adc_arbiter_t;
/**
* @brief ADC arbiter default configuration.
*
* @note ESP32S2: Only ADC2 support arbiter.
*/
#define ADC_ARBITER_CONFIG_DEFAULT() { \
.mode = ADC_ARB_MODE_FIX, \
.rtc_pri = 1, \
.dig_pri = 0, \
.pwdet_pri = 2, \
}
/**
* @brief ADC digital controller (DMA mode) work mode.
*
* @note Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
*/
typedef enum {
ADC_CONV_SINGLE_UNIT_1 = 1, /*!< SAR ADC 1. */
ADC_CONV_SINGLE_UNIT_2 = 2, /*!< SAR ADC 2. */
ADC_CONV_BOTH_UNIT = 3, /*!< SAR ADC 1 and 2. */
ADC_CONV_ALTER_UNIT = 7, /*!< SAR ADC 1 and 2 alternative mode. */
ADC_CONV_UNIT_MAX,
} adc_digi_convert_mode_t;
/**
* @brief ADC digital controller (DMA mode) output data format option.
*/
typedef enum {
ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
Note: In single convert mode. */
ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
Note: In multi or alter convert mode. */
ADC_DIGI_FORMAT_MAX,
} adc_digi_output_format_t;
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
*
* @note Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
*/
typedef struct {
union {
struct {
uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint16_t channel: 4; /*!<ADC channel index info.
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
struct {
uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
uint16_t channel: 4; /*!<ADC channel index info.
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
} type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */
uint16_t val;
};
} adc_digi_output_data_t;
/**
* @brief ADC digital controller (DMA mode) conversion rules setting.
*/
typedef struct {
union {
struct {
uint8_t atten: 2; /*!< ADC sampling voltage attenuation configuration.
0: input voltage * 1;
1: input voltage * 1/1.34;
2: input voltage * 1/2;
3: input voltage * 1/3.6. */
uint8_t reserved: 2; /*!< reserved0 */
uint8_t channel: 4; /*!< ADC channel index. */
};
uint8_t val;
};
} adc_digi_pattern_table_t;
/**
* @brief ADC digital controller (DMA mode) interrupt type options.
*/
typedef enum {
ADC_DIGI_INTR_MASK_MONITOR = 0x1,
ADC_DIGI_INTR_MASK_MEAS_DONE = 0x2,
ADC_DIGI_INTR_MASK_ALL = 0x3,
} adc_digi_intr_t;
/**
* @brief ADC digital controller (DMA mode) configuration parameters.
*/
typedef struct {
bool conv_limit_en; /*!<Enable max conversion number detection for digital controller.
If the number of ADC conversion is equal to the `limit_num`, the conversion is stopped. */
uint32_t conv_limit_num; /*!<ADC max conversion number for digital controller. */
uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16.
The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */
uint32_t adc2_pattern_len; /*!<Refer to `adc1_pattern_len` */
adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */
adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. */
adc_digi_output_format_t format; /*!<ADC output data format for digital controller. */
uint32_t interval; /*!<The number of interval clock cycles for the digital controller to trigger the measurement.
The unit is the divided clock. Range: 40 ~ 4095. */
adc_digi_clk_t dig_clk; /*!<Refer to `adc_digi_clk_t` */
uint32_t dma_eof_num; /*!<DMA eof num of adc digital controller.
If the number of measurements reaches `dma_eof_num`,
then `dma_in_suc_eof` signal is generated. */
} adc_digi_config_t;
/**
* @brief ADC digital controller (DMA mode) filter index options.
*
* @note For ESP32S2, The filter object of the ADC is fixed.
*/
typedef enum {
ADC_DIGI_FILTER_IDX0 = 0, /*!<The filter index 0.
For ESP32S2, It can only be used to filter all enabled channels of ADC1 unit at the same time. */
ADC_DIGI_FILTER_IDX1, /*!<The filter index 1.
For ESP32S2, It can only be used to filter all enabled channels of ADC2 unit at the same time. */
ADC_DIGI_FILTER_IDX_MAX
} adc_digi_filter_idx_t;
/**
* @brief ADC digital controller (DMA mode) filter type options.
* Expression: filter_data = (k-1)/k * last_data + new_data / k.
*/
typedef enum {
ADC_DIGI_FILTER_IIR_2 = 0, /*!<The filter mode is first-order IIR filter. The coefficient is 2. */
ADC_DIGI_FILTER_IIR_4, /*!<The filter mode is first-order IIR filter. The coefficient is 4. */
ADC_DIGI_FILTER_IIR_8, /*!<The filter mode is first-order IIR filter. The coefficient is 8. */
ADC_DIGI_FILTER_IIR_16, /*!<The filter mode is first-order IIR filter. The coefficient is 16. */
ADC_DIGI_FILTER_IIR_64, /*!<The filter mode is first-order IIR filter. The coefficient is 64. */
ADC_DIGI_FILTER_IIR_MAX
} adc_digi_filter_mode_t;
/**
* @brief ADC digital controller (DMA mode) filter configuration.
*
* @note For ESP32S2, The filter object of the ADC is fixed.
* @note For ESP32S2, The filter object is always all enabled channels.
*/
typedef struct {
adc_unit_t adc_unit; /*!<Set adc unit number for filter.
For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time. */
adc_channel_t channel; /*!<Set adc channel number for filter.
For ESP32S2, it's always `ADC_CHANNEL_MAX` */
adc_digi_filter_mode_t mode;/*!<Set adc filter mode for filter. See ``adc_digi_filter_mode_t``. */
} adc_digi_filter_t;
/**
* @brief ADC digital controller (DMA mode) monitor index options.
*
* @note For ESP32S2, The monitor object of the ADC is fixed.
*/
typedef enum {
ADC_DIGI_MONITOR_IDX0 = 0, /*!<The monitor index 0.
For ESP32S2, It can only be used to monitor all enabled channels of ADC1 unit at the same time. */
ADC_DIGI_MONITOR_IDX1, /*!<The monitor index 1.
For ESP32S2, It can only be used to monitor all enabled channels of ADC2 unit at the same time. */
ADC_DIGI_MONITOR_IDX_MAX
} adc_digi_monitor_idx_t;
/**
* @brief Set monitor mode of adc digital controller.
* MONITOR_HIGH:If ADC_OUT > threshold, Generates monitor interrupt.
* MONITOR_LOW: If ADC_OUT < threshold, Generates monitor interrupt.
*/
typedef enum {
ADC_DIGI_MONITOR_HIGH = 0, /*!<If ADC_OUT > threshold, Generates monitor interrupt. */
ADC_DIGI_MONITOR_LOW, /*!<If ADC_OUT < threshold, Generates monitor interrupt. */
ADC_DIGI_MONITOR_MAX
} adc_digi_monitor_mode_t;
/**
* @brief ADC digital controller (DMA mode) monitor configuration.
*
* @note For ESP32S2, The monitor object of the ADC is fixed.
* @note For ESP32S2, The monitor object is always all enabled channels.
*/
typedef struct {
adc_unit_t adc_unit; /*!<Set adc unit number for monitor.
For ESP32S2, monitor IDX0/IDX1 can only be used to monitor all enabled channels of ADC1/ADC2 unit at the same time. */
adc_channel_t channel; /*!<Set adc channel number for monitor.
For ESP32S2, it's always `ADC_CHANNEL_MAX` */
adc_digi_monitor_mode_t mode; /*!<Set adc monitor mode. See ``adc_digi_monitor_mode_t``. */
uint32_t threshold; /*!<Set monitor threshold of adc digital controller. */
} adc_digi_monitor_t;
#endif // CONFIG_IDF_TARGET_ESP32S2
tools/sdk/esp32s2/include/soc/include/hal/brownout_hal.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "soc/brownout_caps.h"
typedef struct {
uint8_t threshold;
bool enabled;
bool reset_enabled;
bool flash_power_down;
bool rf_power_down;
} brownout_hal_config_t;
void brownout_hal_config(const brownout_hal_config_t *cfg);
void brownout_hal_intr_enable(bool enable);
void brownout_hal_intr_clear(void);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/can_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stddef.h>
#include <stdbool.h>
#include "hal/can_types.h"
#include "hal/can_ll.h"
/* ------------------------- Defines and Typedefs --------------------------- */
//Error active interrupt related
#define CAN_HAL_EVENT_BUS_OFF (1 << 0)
#define CAN_HAL_EVENT_BUS_RECOV_CPLT (1 << 1)
#define CAN_HAL_EVENT_BUS_RECOV_PROGRESS (1 << 2)
#define CAN_HAL_EVENT_ABOVE_EWL (1 << 3)
#define CAN_HAL_EVENT_BELOW_EWL (1 << 4)
#define CAN_HAL_EVENT_ERROR_PASSIVE (1 << 5)
#define CAN_HAL_EVENT_ERROR_ACTIVE (1 << 6)
#define CAN_HAL_EVENT_BUS_ERR (1 << 7)
#define CAN_HAL_EVENT_ARB_LOST (1 << 8)
#define CAN_HAL_EVENT_RX_BUFF_FRAME (1 << 9)
#define CAN_HAL_EVENT_TX_BUFF_FREE (1 << 10)
typedef struct {
can_dev_t *dev;
} can_hal_context_t;
typedef can_ll_frame_buffer_t can_hal_frame_t;
/* ---------------------------- Init and Config ----------------------------- */
/**
* @brief Initialize CAN peripheral and HAL context
*
* Sets HAL context, puts CAN peripheral into reset mode, then sets some
* registers with default values.
*
* @param hal_ctx Context of the HAL layer
* @return True if successfully initialized, false otherwise.
*/
bool can_hal_init(can_hal_context_t *hal_ctx);
/**
* @brief Deinitialize the CAN peripheral and HAL context
*
* Clears any unhandled interrupts and unsets HAL context
*
* @param hal_ctx Context of the HAL layer
*/
void can_hal_deinit(can_hal_context_t *hal_ctx);
/**
* @brief Configure the CAN peripheral
*
* @param hal_ctx Context of the HAL layer
* @param t_config Pointer to timing configuration structure
* @param f_config Pointer to filter configuration structure
* @param intr_mask Mask of interrupts to enable
* @param clkout_divider Clock divider value for CLKOUT. Set to -1 to disable CLKOUT
*/
void can_hal_configure(can_hal_context_t *hal_ctx, const can_timing_config_t *t_config, const can_filter_config_t *f_config, uint32_t intr_mask, uint32_t clkout_divider);
/* -------------------------------- Actions --------------------------------- */
/**
* @brief Start the CAN peripheral
*
* Start the CAN peripheral by configuring its operating mode, then exiting
* reset mode so that the CAN peripheral can participate in bus activities.
*
* @param hal_ctx Context of the HAL layer
* @param mode Operating mode
* @return True if successfully started, false otherwise.
*/
bool can_hal_start(can_hal_context_t *hal_ctx, can_mode_t mode);
/**
* @brief Stop the CAN peripheral
*
* Stop the CAN peripheral by entering reset mode to stop any bus activity, then
* setting the operating mode to Listen Only so that REC is frozen.
*
* @param hal_ctx Context of the HAL layer
* @return True if successfully stopped, false otherwise.
*/
bool can_hal_stop(can_hal_context_t *hal_ctx);
/**
* @brief Start bus recovery
*
* @param hal_ctx Context of the HAL layer
* @return True if successfully started bus recovery, false otherwise.
*/
static inline bool can_hal_start_bus_recovery(can_hal_context_t *hal_ctx)
{
return can_ll_exit_reset_mode(hal_ctx->dev);
}
/**
* @brief Get the value of the TX Error Counter
*
* @param hal_ctx Context of the HAL layer
* @return TX Error Counter Value
*/
static inline uint32_t can_hal_get_tec(can_hal_context_t *hal_ctx)
{
return can_ll_get_tec((hal_ctx)->dev);
}
/**
* @brief Get the value of the RX Error Counter
*
* @param hal_ctx Context of the HAL layer
* @return RX Error Counter Value
*/
static inline uint32_t can_hal_get_rec(can_hal_context_t *hal_ctx)
{
return can_ll_get_rec((hal_ctx)->dev);
}
/**
* @brief Get the RX message count register
*
* @param hal_ctx Context of the HAL layer
* @return RX message count
*/
static inline uint32_t can_hal_get_rx_msg_count(can_hal_context_t *hal_ctx)
{
return can_ll_get_rx_msg_count((hal_ctx)->dev);
}
/**
* @brief Check if the last transmitted frame was successful
*
* @param hal_ctx Context of the HAL layer
* @return True if successful
*/
static inline bool can_hal_check_last_tx_successful(can_hal_context_t *hal_ctx)
{
return can_ll_is_last_tx_successful((hal_ctx)->dev);
}
/* ----------------------------- Event Handling ----------------------------- */
/**
* @brief Decode current events that triggered an interrupt
*
* This function should be called on every CAN interrupt. It will read (and
* thereby clear) the interrupt register, then determine what events have
* occurred to trigger the interrupt.
*
* @param hal_ctx Context of the HAL layer
* @param bus_recovering Whether the CAN peripheral was previous undergoing bus recovery
* @return Bit mask of events that have occurred
*/
uint32_t can_hal_decode_interrupt_events(can_hal_context_t *hal_ctx, bool bus_recovering);
/**
* @brief Handle bus recovery complete
*
* This function should be called on an bus recovery complete event. It simply
* enters reset mode to stop bus activity.
*
* @param hal_ctx Context of the HAL layer
* @return True if successfully handled bus recovery completion, false otherwise.
*/
static inline bool can_hal_handle_bus_recov_cplt(can_hal_context_t *hal_ctx)
{
return can_ll_enter_reset_mode((hal_ctx)->dev);
}
/**
* @brief Handle arbitration lost
*
* This function should be called on an arbitration lost event. It simply clears
* the clears the ALC register.
*
* @param hal_ctx Context of the HAL layer
*/
static inline void can_hal_handle_arb_lost(can_hal_context_t *hal_ctx)
{
can_ll_clear_arb_lost_cap((hal_ctx)->dev);
}
/**
* @brief Handle bus error
*
* This function should be called on an bus error event. It simply clears
* the clears the ECC register.
*
* @param hal_ctx Context of the HAL layer
*/
static inline void can_hal_handle_bus_error(can_hal_context_t *hal_ctx)
{
can_ll_clear_err_code_cap((hal_ctx)->dev);
}
/**
* @brief Handle BUS OFF
*
* This function should be called on a BUS OFF event. It simply changes the
* mode to LOM to freeze REC
*
* @param hal_ctx Context of the HAL layer
*/
static inline void can_hal_handle_bus_off(can_hal_context_t *hal_ctx)
{
can_ll_set_mode((hal_ctx)->dev, CAN_MODE_LISTEN_ONLY);
}
/* ------------------------------- TX and RX -------------------------------- */
/**
* @brief Format a CAN Frame
*
* This function takes a CAN message structure (containing ID, DLC, data, and
* flags) and formats it to match the layout of the TX frame buffer.
*
* @param message Pointer to CAN message
* @param frame Pointer to empty frame structure
*/
static inline void can_hal_format_frame(const can_message_t *message, can_hal_frame_t *frame)
{
//Direct call to ll function
can_ll_format_frame_buffer(message->identifier, message->data_length_code, message->data,
message->flags, frame);
}
/**
* @brief Parse a CAN Frame
*
* This function takes a CAN frame (in the format of the RX frame buffer) and
* parses it to a CAN message (containing ID, DLC, data and flags).
*
* @param frame Pointer to frame structure
* @param message Pointer to empty message structure
*/
static inline void can_hal_parse_frame(can_hal_frame_t *frame, can_message_t *message)
{
//Direct call to ll function
can_ll_prase_frame_buffer(frame, &message->identifier, &message->data_length_code,
message->data, &message->flags);
}
/**
* @brief Copy a frame into the TX buffer and transmit
*
* This function copies a formatted TX frame into the TX buffer, and the
* transmit by setting the correct transmit command (e.g. normal, single shot,
* self RX) in the command register.
*
* @param hal_ctx Context of the HAL layer
* @param tx_frame Pointer to structure containing formatted TX frame
*/
void can_hal_set_tx_buffer_and_transmit(can_hal_context_t *hal_ctx, can_hal_frame_t *tx_frame);
/**
* @brief Copy a frame from the RX buffer and release
*
* This function copies a frame from the RX buffer, then release the buffer (so
* that it loads the next frame in the RX FIFO).
*
* @param hal_ctx Context of the HAL layer
* @param rx_frame Pointer to structure to store RX frame
*/
static inline void can_hal_read_rx_buffer_and_clear(can_hal_context_t *hal_ctx, can_hal_frame_t *rx_frame)
{
can_ll_get_rx_buffer(hal_ctx->dev, rx_frame);
can_ll_set_cmd_release_rx_buffer(hal_ctx->dev);
/*
* Todo: Support overrun handling by:
* - Check overrun status bit. Return false if overrun
*/
}
//Todo: Decode ALC register
//Todo: Decode error code capture
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/can_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
/**
* @brief CAN2.0B Constants
*/
#define CAN_EXTD_ID_MASK 0x1FFFFFFF /**< Bit mask for 29 bit Extended Frame Format ID */
#define CAN_STD_ID_MASK 0x7FF /**< Bit mask for 11 bit Standard Frame Format ID */
#define CAN_FRAME_MAX_DLC 8 /**< Max data bytes allowed in CAN2.0 */
#define CAN_FRAME_EXTD_ID_LEN_BYTES 4 /**< EFF ID requires 4 bytes (29bit) */
#define CAN_FRAME_STD_ID_LEN_BYTES 2 /**< SFF ID requires 2 bytes (11bit) */
#define CAN_ERR_PASS_THRESH 128 /**< Error counter threshold for error passive */
/** @cond */ //Doxy command to hide preprocessor definitions from docs
/**
* @brief CAN Message flags
*
* The message flags are used to indicate the type of message transmitted/received.
* Some flags also specify the type of transmission.
*/
#define CAN_MSG_FLAG_NONE 0x00 /**< No message flags (Standard Frame Format) */
#define CAN_MSG_FLAG_EXTD 0x01 /**< Extended Frame Format (29bit ID) */
#define CAN_MSG_FLAG_RTR 0x02 /**< Message is a Remote Transmit Request */
#define CAN_MSG_FLAG_SS 0x04 /**< Transmit as a Single Shot Transmission. Unused for received. */
#define CAN_MSG_FLAG_SELF 0x08 /**< Transmit as a Self Reception Request. Unused for received. */
#define CAN_MSG_FLAG_DLC_NON_COMP 0x10 /**< Message's Data length code is larger than 8. This will break compliance with CAN2.0B */
/**
* @brief Initializer macros for timing configuration structure
*
* The following initializer macros offer commonly found bit rates.
*
* @note These timing values are based on the assumption APB clock is at 80MHz
* @note The 20K, 16K and 12.5K bit rates are only available from ESP32 Revision 2 onwards
*/
#ifdef CAN_BRP_DIV_SUPPORTED
#define CAN_TIMING_CONFIG_12_5KBITS() {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define CAN_TIMING_CONFIG_16KBITS() {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define CAN_TIMING_CONFIG_20KBITS() {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#endif
#define CAN_TIMING_CONFIG_25KBITS() {.brp = 128, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define CAN_TIMING_CONFIG_50KBITS() {.brp = 80, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#define CAN_TIMING_CONFIG_100KBITS() {.brp = 40, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#define CAN_TIMING_CONFIG_125KBITS() {.brp = 32, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#define CAN_TIMING_CONFIG_250KBITS() {.brp = 16, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#define CAN_TIMING_CONFIG_500KBITS() {.brp = 8, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#define CAN_TIMING_CONFIG_800KBITS() {.brp = 4, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define CAN_TIMING_CONFIG_1MBITS() {.brp = 4, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
/**
* @brief Initializer macro for filter configuration to accept all IDs
*/
#define CAN_FILTER_CONFIG_ACCEPT_ALL() {.acceptance_code = 0, .acceptance_mask = 0xFFFFFFFF, .single_filter = true}
/** @endcond */
/**
* @brief CAN Controller operating modes
*/
typedef enum {
CAN_MODE_NORMAL, /**< Normal operating mode where CAN controller can send/receive/acknowledge messages */
CAN_MODE_NO_ACK, /**< Transmission does not require acknowledgment. Use this mode for self testing */
CAN_MODE_LISTEN_ONLY, /**< The CAN controller will not influence the bus (No transmissions or acknowledgments) but can receive messages */
} can_mode_t;
/**
* @brief Structure to store a CAN message
*
* @note
* @note The flags member is deprecated
*/
typedef struct {
union {
struct {
//The order of these bits must match deprecated message flags for compatibility reasons
uint32_t extd: 1; /**< Extended Frame Format (29bit ID) */
uint32_t rtr: 1; /**< Message is a Remote Transmit Request */
uint32_t ss: 1; /**< Transmit as a Single Shot Transmission. Unused for received. */
uint32_t self: 1; /**< Transmit as a Self Reception Request. Unused for received. */
uint32_t dlc_non_comp: 1; /**< Message's Data length code is larger than 8. This will break compliance with CAN2.0B. */
uint32_t reserved: 27; /**< Reserved bits */
};
//Todo: Deprecate flags
uint32_t flags; /**< Alternate way to set message flags using message flag macros (see documentation) */
};
uint32_t identifier; /**< 11 or 29 bit identifier */
uint8_t data_length_code; /**< Data length code */
uint8_t data[CAN_FRAME_MAX_DLC]; /**< Data bytes (not relevant in RTR frame) */
} can_message_t;
/**
* @brief Structure for bit timing configuration of the CAN driver
*
* @note Macro initializers are available for this structure
*/
typedef struct {
uint32_t brp; /**< Baudrate prescaler (i.e., APB clock divider) can be any even number from 2 to 128.
For ESP32 Rev 2 or later, multiples of 4 from 132 to 256 are also supported */
uint8_t tseg_1; /**< Timing segment 1 (Number of time quanta, between 1 to 16) */
uint8_t tseg_2; /**< Timing segment 2 (Number of time quanta, 1 to 8) */
uint8_t sjw; /**< Synchronization Jump Width (Max time quanta jump for synchronize from 1 to 4) */
bool triple_sampling; /**< Enables triple sampling when the CAN controller samples a bit */
} can_timing_config_t;
/**
* @brief Structure for acceptance filter configuration of the CAN driver (see documentation)
*
* @note Macro initializers are available for this structure
*/
typedef struct {
uint32_t acceptance_code; /**< 32-bit acceptance code */
uint32_t acceptance_mask; /**< 32-bit acceptance mask */
bool single_filter; /**< Use Single Filter Mode (see documentation) */
} can_filter_config_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/cpu_hal.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "hal/cpu_types.h"
#include "hal/cpu_ll.h"
#include "soc/cpu_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Return the ID of the core currently executing this code.
*
* @return core id [0..SOC_CPU_CORES_NUM - 1]
*/
#define cpu_hal_get_core_id() cpu_ll_get_core_id()
/**
* Get the current value of the stack pointer.
*
* @return the current stack pointer
*/
#define cpu_hal_get_sp() cpu_ll_get_sp()
/**
* Get the current value of the internal counter that increments
* every processor-clock cycle.
*
* @return cycle count; returns 0 if not supported
*/
#define cpu_hal_get_cycle_count() cpu_ll_get_cycle_count()
/**
* Check if some form of debugger is attached to CPU.
*
* @return true debugger is attached
* @return false no debugger is attached/ no support for debuggers
*/
#define cpu_hal_is_debugger_attached() cpu_ll_is_debugger_attached()
/**
* Init HW loop status.
*/
#define cpu_hal_init_hwloop() cpu_ll_init_hwloop()
/**
* Trigger a call to debugger.
*/
#define cpu_hal_break() cpu_ll_break()
#if SOC_CPU_BREAKPOINTS_NUM > 0
/**
* Set and enable breakpoint at an instruction address.
*
* @note Overwrites previously set breakpoint with same breakpoint ID.
*
* @param id breakpoint to set [0..SOC_CPU_BREAKPOINTS_NUM - 1]
* @param addr address to set a breakpoint on
*/
void cpu_hal_set_breakpoint(int id, const void* addr);
/**
* Clear and disable breakpoint.
*
* @param id breakpoint to clear [0..SOC_CPU_BREAKPOINTS_NUM - 1]
*/
void cpu_hal_clear_breakpoint(int id);
#endif // SOC_CPU_BREAKPOINTS_NUM > 0
#if SOC_CPU_WATCHPOINTS_NUM > 0
/**
* Set and enable a watchpoint, specifying the memory range and trigger operation.
*
* @param id watchpoint to set [0..SOC_CPU_WATCHPOINTS_NUM - 1]
* @param addr starting address
* @param size number of bytes from starting address to watch
* @param trigger operation on specified memory range that triggers the watchpoint (read, write, read/write)
*/
void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger);
/**
* Clear and disable watchpoint.
*
* @param id watchpoint to clear [0..SOC_CPU_WATCHPOINTS_NUM - 1]
*/
void cpu_hal_clear_watchpoint(int id);
#endif // SOC_CPU_WATCHPOINTS_NUM > 0
/**
* Set exception vector table base address.
*
* @param base address to move the exception vector table to
*/
void cpu_hal_set_vecbase(const void* base);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/cpu_types.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
typedef enum {
WATCHPOINT_TRIGGER_ON_RO, // on read
WATCHPOINT_TRIGGER_ON_WO, // on write
WATCHPOINT_TRIGGER_ON_RW // on either read or write
} watchpoint_trigger_t;
tools/sdk/esp32s2/include/soc/include/hal/dac_hal.h
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
#pragma once
#include "hal/dac_ll.h"
#include "hal/hal_defs.h"
#include <esp_err.h>
/**
* Power on dac module and start output voltage.
*
* @note Before powering up, make sure the DAC PAD is set to RTC PAD and floating status.
* @param channel DAC channel num.
*/
#define dac_hal_power_on(channel) dac_ll_power_on(channel)
/**
* Power done dac module and stop output voltage.
*
* @param channel DAC channel num.
*/
#define dac_hal_power_down(channel) dac_ll_power_down(channel)
/**
* Output voltage with value (8 bit).
*
* @param channel DAC channel num.
* @param value Output value. Value range: 0 ~ 255.
* The corresponding range of voltage is 0v ~ VDD3P3_RTC.
*/
#define dac_hal_update_output_value(channel, value) dac_ll_update_output_value(channel, value)
/**
* Enable cosine wave generator output.
*/
#define dac_hal_cw_generator_enable() dac_ll_cw_generator_enable()
/**
* Disable cosine wave generator output.
*/
#define dac_hal_cw_generator_disable() dac_ll_cw_generator_disable()
/**
* Config the cosine wave generator function in DAC module.
*
* @param cw Configuration.
*/
void dac_hal_cw_generator_config(dac_cw_config_t *cw);
/**
* Enable DAC output data from DMA.
*/
#define dac_hal_dma_enable() dac_ll_dma_enable()
/**
* Disable DAC output data from DMA.
*/
#define dac_hal_dma_disable() dac_ll_dma_disable()
tools/sdk/esp32s2/include/soc/include/hal/dac_types.h
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#pragma once
#include "soc/dac_caps.h"
#include "sdkconfig.h"
typedef enum {
DAC_CHANNEL_1 = 0, /*!< DAC channel 1 is GPIO25(ESP32) / GPIO17(ESP32S2) */
DAC_CHANNEL_2 = 1, /*!< DAC channel 2 is GPIO26(ESP32) / GPIO18(ESP32S2) */
DAC_CHANNEL_MAX,
} dac_channel_t;
/**
* @brief The multiple of the amplitude of the cosine wave generator. The max amplitude is VDD3P3_RTC.
*/
typedef enum {
DAC_CW_SCALE_1 = 0x0, /*!< 1/1. Default. */
DAC_CW_SCALE_2 = 0x1, /*!< 1/2. */
DAC_CW_SCALE_4 = 0x2, /*!< 1/4. */
DAC_CW_SCALE_8 = 0x3, /*!< 1/8. */
} dac_cw_scale_t;
/**
* @brief Set the phase of the cosine wave generator output.
*/
typedef enum {
DAC_CW_PHASE_0 = 0x2, /*!< Phase shift +0° */
DAC_CW_PHASE_180 = 0x3, /*!< Phase shift +180° */
} dac_cw_phase_t;
/**
* @brief Config the cosine wave generator function in DAC module.
*/
typedef struct {
dac_channel_t en_ch; /*!< Enable the cosine wave generator of DAC channel. */
dac_cw_scale_t scale; /*!< Set the amplitude of the cosine wave generator output. */
dac_cw_phase_t phase; /*!< Set the phase of the cosine wave generator output. */
uint32_t freq; /*!< Set frequency of cosine wave generator output. Range: 130(130Hz) ~ 55000(100KHz). */
int8_t offset; /*!< Set the voltage value of the DC component of the cosine wave generator output.
Note: Unreasonable settings can cause waveform to be oversaturated. Range: -128 ~ 127. */
} dac_cw_config_t;
tools/sdk/esp32s2/include/soc/include/hal/esp_flash_err.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Possible errors returned from esp flash internal functions, these error codes
* should be consistent with esp_err_t codes. But in order to make the source
* files less dependent to esp_err_t, they use the error codes defined in this
* replacable header. This header should ensure the consistency to esp_err_t.
*/
enum {
/* These codes should be consistent with esp_err_t errors. However, error codes with the same values are not
* allowed in ESP-IDF. This is a workaround in order to not introduce a dependency between the "soc" and
* "esp_common" components. The disadvantage is that the output of esp_err_to_name(ESP_ERR_FLASH_SIZE_NOT_MATCH)
* will be ESP_ERR_INVALID_SIZE. */
ESP_ERR_FLASH_SIZE_NOT_MATCH = ESP_ERR_INVALID_SIZE, ///< The chip doesn't have enough space for the current partition table
ESP_ERR_FLASH_NO_RESPONSE = ESP_ERR_INVALID_RESPONSE, ///< Chip did not respond to the command, or timed out.
};
//The ROM code has already taken 1 and 2, to avoid possible conflicts, start from 3.
#define ESP_ERR_FLASH_NOT_INITIALISED (ESP_ERR_FLASH_BASE+3) ///< esp_flash_chip_t structure not correctly initialised by esp_flash_init().
#define ESP_ERR_FLASH_UNSUPPORTED_HOST (ESP_ERR_FLASH_BASE+4) ///< Requested operation isn't supported via this host SPI bus (chip->spi field).
#define ESP_ERR_FLASH_UNSUPPORTED_CHIP (ESP_ERR_FLASH_BASE+5) ///< Requested operation isn't supported by this model of SPI flash chip.
#define ESP_ERR_FLASH_PROTECTED (ESP_ERR_FLASH_BASE+6) ///< Write operation failed due to chip's write protection being enabled.
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/gpio_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for GPIO
#pragma once
#include "soc/gpio_periph.h"
#include "hal/gpio_ll.h"
#include "hal/gpio_types.h"
#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS
#include "soc/rtc_io_reg.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
// Get GPIO hardware instance with giving gpio num
#define GPIO_HAL_GET_HW(num) GPIO_LL_GET_HW(num)
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
gpio_dev_t *dev;
uint32_t version;
} gpio_hal_context_t;
/**
* @brief Enable pull-up on GPIO.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_pullup_en(hal, gpio_num) gpio_ll_pullup_en((hal)->dev, gpio_num)
/**
* @brief Disable pull-up on GPIO.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_pullup_dis(hal, gpio_num) gpio_ll_pullup_dis((hal)->dev, gpio_num)
/**
* @brief Enable pull-down on GPIO.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_pulldown_en(hal, gpio_num) gpio_ll_pulldown_en((hal)->dev, gpio_num)
/**
* @brief Disable pull-down on GPIO.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_pulldown_dis(hal, gpio_num) gpio_ll_pulldown_dis((hal)->dev, gpio_num)
/**
* @brief GPIO set interrupt trigger type
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16);
* @param intr_type Interrupt type, select from gpio_int_type_t
*/
#define gpio_hal_set_intr_type(hal, gpio_num, intr_type) gpio_ll_set_intr_type((hal)->dev, gpio_num, intr_type)
/**
* @brief Get GPIO interrupt status
*
* @param hal Context of the HAL layer
* @param core_id interrupt core id
* @param status interrupt status
*/
#define gpio_hal_get_intr_status(hal, core_id, status) gpio_ll_get_intr_status((hal)->dev, core_id, status)
/**
* @brief Get GPIO interrupt status high
*
* @param hal Context of the HAL layer
* @param core_id interrupt core id
* @param status interrupt status high
*/
#define gpio_hal_get_intr_status_high(hal, core_id, status) gpio_ll_get_intr_status_high((hal)->dev, core_id, status)
/**
* @brief Clear GPIO interrupt status
*
* @param hal Context of the HAL layer
* @param mask interrupt status clear mask
*/
#define gpio_hal_clear_intr_status(hal, mask) gpio_ll_clear_intr_status((hal)->dev, mask)
/**
* @brief Clear GPIO interrupt status high
*
* @param hal Context of the HAL layer
* @param mask interrupt status high clear mask
*/
#define gpio_hal_clear_intr_status_high(hal, mask) gpio_ll_clear_intr_status_high((hal)->dev, mask)
/**
* @brief Enable GPIO module interrupt signal
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
* @param core_id Interrupt enabled CPU to corresponding ID
*/
void gpio_hal_intr_enable_on_core(gpio_hal_context_t *hal, gpio_num_t gpio_num, uint32_t core_id);
/**
* @brief Disable GPIO module interrupt signal
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
*/
void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num);
/**
* @brief Disable input mode on GPIO.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_input_disable(hal, gpio_num) gpio_ll_input_disable((hal)->dev, gpio_num)
/**
* @brief Enable input mode on GPIO.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_input_enable(hal, gpio_num) gpio_ll_input_enable((hal)->dev, gpio_num)
/**
* @brief Disable output mode on GPIO.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_output_disable(hal, gpio_num) gpio_ll_output_disable((hal)->dev, gpio_num)
/**
* @brief Enable output mode on GPIO.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_output_enable(hal, gpio_num) gpio_ll_output_enable((hal)->dev, gpio_num)
/**
* @brief Disable open-drain mode on GPIO.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_od_disable(hal, gpio_num) gpio_ll_od_disable((hal)->dev, gpio_num)
/**
* @brief Enable open-drain mode on GPIO.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_od_enable(hal, gpio_num) gpio_ll_od_enable((hal)->dev, gpio_num)
/**
* @brief GPIO set output level
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
* @param level Output level. 0: low ; 1: high
*/
#define gpio_hal_set_level(hal, gpio_num, level) gpio_ll_set_level((hal)->dev, gpio_num, level)
/**
* @brief GPIO get input level
*
* @warning If the pad is not configured for input (or input and output) the returned value is always 0.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
*
* @return
* - 0 the GPIO input level is 0
* - 1 the GPIO input level is 1
*/
#define gpio_hal_get_level(hal, gpio_num) gpio_ll_get_level((hal)->dev, gpio_num)
/**
* @brief Enable GPIO wake-up function.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number.
* @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
*/
#define gpio_hal_wakeup_enable(hal, gpio_num, intr_type) gpio_ll_wakeup_enable((hal)->dev, gpio_num, intr_type)
/**
* @brief Disable GPIO wake-up function.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*/
#define gpio_hal_wakeup_disable(hal, gpio_num) gpio_ll_wakeup_disable((hal)->dev, gpio_num)
/**
* @brief Set GPIO pad drive capability
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number, only support output GPIOs
* @param strength Drive capability of the pad
*/
#define gpio_hal_set_drive_capability(hal, gpio_num, strength) gpio_ll_set_drive_capability((hal)->dev, gpio_num, strength)
/**
* @brief Get GPIO pad drive capability
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number, only support output GPIOs
* @param strength Pointer to accept drive capability of the pad
*/
#define gpio_hal_get_drive_capability(hal, gpio_num, strength) gpio_ll_get_drive_capability((hal)->dev, gpio_num, strength)
/**
* @brief Enable gpio pad hold function.
*
* The gpio pad hold function works in both input and output modes, but must be output-capable gpios.
* If pad hold enabled:
* in output mode: the output level of the pad will be force locked and can not be changed.
* in input mode: the input value read will not change, regardless the changes of input signal.
*
* The state of digital gpio cannot be held during Deep-sleep, and it will resume the hold function
* when the chip wakes up from Deep-sleep. If the digital gpio also needs to be held during Deep-sleep,
* `gpio_deep_sleep_hold_en` should also be called.
*
* Power down or call gpio_hold_dis will disable this function.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number, only support output GPIOs
*/
#define gpio_hal_hold_en(hal, gpio_num) gpio_ll_hold_en((hal)->dev, gpio_num)
/**
* @brief Disable gpio pad hold function.
*
* When the chip is woken up from Deep-sleep, the gpio will be set to the default mode, so, the gpio will output
* the default level if this function is called. If you don't want the level changes, the gpio should be configured to
* a known state before this function is called.
* e.g.
* If you hold gpio18 high during Deep-sleep, after the chip is woken up and `gpio_hold_dis` is called,
* gpio18 will output low level(because gpio18 is input mode by default). If you don't want this behavior,
* you should configure gpio18 as output mode and set it to hight level before calling `gpio_hold_dis`.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number, only support output GPIOs
*/
#define gpio_hal_hold_dis(hal, gpio_num) gpio_ll_hold_dis((hal)->dev, gpio_num)
/**
* @brief Enable all digital gpio pad hold function during Deep-sleep.
*
* When the chip is in Deep-sleep mode, all digital gpio will hold the state before sleep, and when the chip is woken up,
* the status of digital gpio will not be held. Note that the pad hold feature only works when the chip is in Deep-sleep mode,
* when not in sleep mode, the digital gpio state can be changed even you have called this function.
*
* Power down or call gpio_hold_dis will disable this function, otherwise, the digital gpio hold feature works as long as the chip enter Deep-sleep.
*
* @param hal Context of the HAL layer
*/
#define gpio_hal_deep_sleep_hold_en(hal) gpio_ll_deep_sleep_hold_en((hal)->dev)
/**
* @brief Disable all digital gpio pad hold function during Deep-sleep.
*
* @param hal Context of the HAL layer
*/
#define gpio_hal_deep_sleep_hold_dis(hal) gpio_ll_deep_sleep_hold_dis((hal)->dev)
/**
* @brief Set pad input to a peripheral signal through the IOMUX.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number of the pad.
* @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``.
*/
#define gpio_hal_iomux_in(hal, gpio_num, signal_idx) gpio_ll_iomux_in((hal)->dev, gpio_num, signal_idx)
/**
* @brief Set peripheral output to an GPIO pad through the IOMUX.
*
* @param hal Context of the HAL layer
* @param gpio_num gpio_num GPIO number of the pad.
* @param func The function number of the peripheral pin to output pin.
* One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``.
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
#define gpio_hal_iomux_out(hal, gpio_num, func, oen_inv) gpio_ll_iomux_out((hal)->dev, gpio_num, func, oen_inv)
#if GPIO_SUPPORTS_FORCE_HOLD
/**
* @brief Force hold digital and rtc gpio pad.
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
*
* @param hal Context of the HAL layer
* */
#define gpio_hal_force_hold_all(hal) gpio_ll_force_hold_all((hal)->dev)
/**
* @brief Force unhold digital and rtc gpio pad.
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
*
* @param hal Context of the HAL layer
* */
#define gpio_hal_force_unhold_all(hal) gpio_ll_force_unhold_all((hal)->dev)
#endif
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/gpio_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/gpio_periph.h"
#include "soc/gpio_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
GPIO_PORT_0 = 0,
GPIO_PORT_MAX,
} gpio_port_t;
#define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */
#define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */
#define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected */
#define GPIO_SEL_3 (BIT(3)) /*!< Pin 3 selected */
#define GPIO_SEL_4 (BIT(4)) /*!< Pin 4 selected */
#define GPIO_SEL_5 (BIT(5)) /*!< Pin 5 selected */
#define GPIO_SEL_6 (BIT(6)) /*!< Pin 6 selected */
#define GPIO_SEL_7 (BIT(7)) /*!< Pin 7 selected */
#define GPIO_SEL_8 (BIT(8)) /*!< Pin 8 selected */
#define GPIO_SEL_9 (BIT(9)) /*!< Pin 9 selected */
#define GPIO_SEL_10 (BIT(10)) /*!< Pin 10 selected */
#define GPIO_SEL_11 (BIT(11)) /*!< Pin 11 selected */
#define GPIO_SEL_12 (BIT(12)) /*!< Pin 12 selected */
#define GPIO_SEL_13 (BIT(13)) /*!< Pin 13 selected */
#define GPIO_SEL_14 (BIT(14)) /*!< Pin 14 selected */
#define GPIO_SEL_15 (BIT(15)) /*!< Pin 15 selected */
#define GPIO_SEL_16 (BIT(16)) /*!< Pin 16 selected */
#define GPIO_SEL_17 (BIT(17)) /*!< Pin 17 selected */
#define GPIO_SEL_18 (BIT(18)) /*!< Pin 18 selected */
#define GPIO_SEL_19 (BIT(19)) /*!< Pin 19 selected */
#define GPIO_SEL_20 (BIT(20)) /*!< Pin 20 selected */
#define GPIO_SEL_21 (BIT(21)) /*!< Pin 21 selected */
#if CONFIG_IDF_TARGET_ESP32
#define GPIO_SEL_22 (BIT(22)) /*!< Pin 22 selected */
#define GPIO_SEL_23 (BIT(23)) /*!< Pin 23 selected */
#define GPIO_SEL_25 (BIT(25)) /*!< Pin 25 selected */
#endif
#define GPIO_SEL_26 (BIT(26)) /*!< Pin 26 selected */
#define GPIO_SEL_27 (BIT(27)) /*!< Pin 27 selected */
#define GPIO_SEL_28 (BIT(28)) /*!< Pin 28 selected */
#define GPIO_SEL_29 (BIT(29)) /*!< Pin 29 selected */
#define GPIO_SEL_30 (BIT(30)) /*!< Pin 30 selected */
#define GPIO_SEL_31 (BIT(31)) /*!< Pin 31 selected */
#define GPIO_SEL_32 ((uint64_t)(((uint64_t)1)<<32)) /*!< Pin 32 selected */
#define GPIO_SEL_33 ((uint64_t)(((uint64_t)1)<<33)) /*!< Pin 33 selected */
#define GPIO_SEL_34 ((uint64_t)(((uint64_t)1)<<34)) /*!< Pin 34 selected */
#define GPIO_SEL_35 ((uint64_t)(((uint64_t)1)<<35)) /*!< Pin 35 selected */
#define GPIO_SEL_36 ((uint64_t)(((uint64_t)1)<<36)) /*!< Pin 36 selected */
#define GPIO_SEL_37 ((uint64_t)(((uint64_t)1)<<37)) /*!< Pin 37 selected */
#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /*!< Pin 38 selected */
#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /*!< Pin 39 selected */
#if GPIO_PIN_COUNT > 40
#define GPIO_SEL_40 ((uint64_t)(((uint64_t)1)<<40)) /*!< Pin 40 selected */
#define GPIO_SEL_41 ((uint64_t)(((uint64_t)1)<<41)) /*!< Pin 41 selected */
#define GPIO_SEL_42 ((uint64_t)(((uint64_t)1)<<42)) /*!< Pin 42 selected */
#define GPIO_SEL_43 ((uint64_t)(((uint64_t)1)<<43)) /*!< Pin 43 selected */
#define GPIO_SEL_44 ((uint64_t)(((uint64_t)1)<<44)) /*!< Pin 44 selected */
#define GPIO_SEL_45 ((uint64_t)(((uint64_t)1)<<45)) /*!< Pin 45 selected */
#define GPIO_SEL_46 ((uint64_t)(((uint64_t)1)<<46)) /*!< Pin 46 selected */
#endif
#define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG
#define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG
#define GPIO_PIN_REG_2 IO_MUX_GPIO2_REG
#define GPIO_PIN_REG_3 IO_MUX_GPIO3_REG
#define GPIO_PIN_REG_4 IO_MUX_GPIO4_REG
#define GPIO_PIN_REG_5 IO_MUX_GPIO5_REG
#define GPIO_PIN_REG_6 IO_MUX_GPIO6_REG
#define GPIO_PIN_REG_7 IO_MUX_GPIO7_REG
#define GPIO_PIN_REG_8 IO_MUX_GPIO8_REG
#define GPIO_PIN_REG_9 IO_MUX_GPIO9_REG
#define GPIO_PIN_REG_10 IO_MUX_GPIO10_REG
#define GPIO_PIN_REG_11 IO_MUX_GPIO11_REG
#define GPIO_PIN_REG_12 IO_MUX_GPIO12_REG
#define GPIO_PIN_REG_13 IO_MUX_GPIO13_REG
#define GPIO_PIN_REG_14 IO_MUX_GPIO14_REG
#define GPIO_PIN_REG_15 IO_MUX_GPIO15_REG
#define GPIO_PIN_REG_16 IO_MUX_GPIO16_REG
#define GPIO_PIN_REG_17 IO_MUX_GPIO17_REG
#define GPIO_PIN_REG_18 IO_MUX_GPIO18_REG
#define GPIO_PIN_REG_19 IO_MUX_GPIO19_REG
#define GPIO_PIN_REG_20 IO_MUX_GPIO20_REG
#define GPIO_PIN_REG_21 IO_MUX_GPIO21_REG
#define GPIO_PIN_REG_22 IO_MUX_GPIO22_REG
#define GPIO_PIN_REG_23 IO_MUX_GPIO23_REG
#define GPIO_PIN_REG_24 IO_MUX_GPIO24_REG
#define GPIO_PIN_REG_25 IO_MUX_GPIO25_REG
#define GPIO_PIN_REG_26 IO_MUX_GPIO26_REG
#define GPIO_PIN_REG_27 IO_MUX_GPIO27_REG
#if CONFIG_IDF_TARGET_ESP32S2
#define GPIO_PIN_REG_28 IO_MUX_GPIO28_REG
#define GPIO_PIN_REG_29 IO_MUX_GPIO29_REG
#define GPIO_PIN_REG_30 IO_MUX_GPIO30_REG
#define GPIO_PIN_REG_31 IO_MUX_GPIO31_REG
#endif
#define GPIO_PIN_REG_32 IO_MUX_GPIO32_REG
#define GPIO_PIN_REG_33 IO_MUX_GPIO33_REG
#define GPIO_PIN_REG_34 IO_MUX_GPIO34_REG
#define GPIO_PIN_REG_35 IO_MUX_GPIO35_REG
#define GPIO_PIN_REG_36 IO_MUX_GPIO36_REG
#define GPIO_PIN_REG_37 IO_MUX_GPIO37_REG
#define GPIO_PIN_REG_38 IO_MUX_GPIO38_REG
#define GPIO_PIN_REG_39 IO_MUX_GPIO39_REG
#if GPIO_PIN_COUNT > 40
#define GPIO_PIN_REG_40 IO_MUX_GPIO40_REG
#define GPIO_PIN_REG_41 IO_MUX_GPIO41_REG
#define GPIO_PIN_REG_42 IO_MUX_GPIO42_REG
#define GPIO_PIN_REG_43 IO_MUX_GPIO43_REG
#define GPIO_PIN_REG_44 IO_MUX_GPIO44_REG
#define GPIO_PIN_REG_45 IO_MUX_GPIO45_REG
#define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG
#endif
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */
GPIO_NUM_3 = 3, /*!< GPIO3, input and output */
GPIO_NUM_4 = 4, /*!< GPIO4, input and output */
GPIO_NUM_5 = 5, /*!< GPIO5, input and output */
GPIO_NUM_6 = 6, /*!< GPIO6, input and output */
GPIO_NUM_7 = 7, /*!< GPIO7, input and output */
GPIO_NUM_8 = 8, /*!< GPIO8, input and output */
GPIO_NUM_9 = 9, /*!< GPIO9, input and output */
GPIO_NUM_10 = 10, /*!< GPIO10, input and output */
GPIO_NUM_11 = 11, /*!< GPIO11, input and output */
GPIO_NUM_12 = 12, /*!< GPIO12, input and output */
GPIO_NUM_13 = 13, /*!< GPIO13, input and output */
GPIO_NUM_14 = 14, /*!< GPIO14, input and output */
GPIO_NUM_15 = 15, /*!< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
#if CONFIG_IDF_TARGET_ESP32
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
#endif
/* Note: The missing IO is because it is used inside the chip. */
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
GPIO_NUM_27 = 27, /*!< GPIO27, input and output */
GPIO_NUM_28 = 28, /*!< GPIO28, input and output */
GPIO_NUM_29 = 29, /*!< GPIO29, input and output */
GPIO_NUM_30 = 30, /*!< GPIO30, input and output */
GPIO_NUM_31 = 31, /*!< GPIO31, input and output */
GPIO_NUM_32 = 32, /*!< GPIO32, input and output */
GPIO_NUM_33 = 33, /*!< GPIO33, input and output */
GPIO_NUM_34 = 34, /*!< GPIO34, input mode only(ESP32) / input and output(ESP32-S2) */
GPIO_NUM_35 = 35, /*!< GPIO35, input mode only(ESP32) / input and output(ESP32-S2) */
GPIO_NUM_36 = 36, /*!< GPIO36, input mode only(ESP32) / input and output(ESP32-S2) */
GPIO_NUM_37 = 37, /*!< GPIO37, input mode only(ESP32) / input and output(ESP32-S2) */
GPIO_NUM_38 = 38, /*!< GPIO38, input mode only(ESP32) / input and output(ESP32-S2) */
GPIO_NUM_39 = 39, /*!< GPIO39, input mode only(ESP32) / input and output(ESP32-S2) */
#if GPIO_PIN_COUNT > 40
GPIO_NUM_40 = 40, /*!< GPIO40, input and output */
GPIO_NUM_41 = 41, /*!< GPIO41, input and output */
GPIO_NUM_42 = 42, /*!< GPIO42, input and output */
GPIO_NUM_43 = 43, /*!< GPIO43, input and output */
GPIO_NUM_44 = 44, /*!< GPIO44, input and output */
GPIO_NUM_45 = 45, /*!< GPIO45, input and output */
GPIO_NUM_46 = 46, /*!< GPIO46, input mode only */
#endif
GPIO_NUM_MAX,
/** @endcond */
} gpio_num_t;
typedef enum {
GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */
GPIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */
GPIO_INTR_NEGEDGE = 2, /*!< GPIO interrupt type : falling edge */
GPIO_INTR_ANYEDGE = 3, /*!< GPIO interrupt type : both rising and falling edge */
GPIO_INTR_LOW_LEVEL = 4, /*!< GPIO interrupt type : input low level trigger */
GPIO_INTR_HIGH_LEVEL = 5, /*!< GPIO interrupt type : input high level trigger */
GPIO_INTR_MAX,
} gpio_int_type_t;
typedef enum {
GPIO_MODE_DISABLE = GPIO_MODE_DEF_DISABLE, /*!< GPIO mode : disable input and output */
GPIO_MODE_INPUT = GPIO_MODE_DEF_INPUT, /*!< GPIO mode : input only */
GPIO_MODE_OUTPUT = GPIO_MODE_DEF_OUTPUT, /*!< GPIO mode : output only mode */
GPIO_MODE_OUTPUT_OD = ((GPIO_MODE_DEF_OUTPUT) | (GPIO_MODE_DEF_OD)), /*!< GPIO mode : output only with open-drain mode */
GPIO_MODE_INPUT_OUTPUT_OD = ((GPIO_MODE_DEF_INPUT) | (GPIO_MODE_DEF_OUTPUT) | (GPIO_MODE_DEF_OD)), /*!< GPIO mode : output and input with open-drain mode*/
GPIO_MODE_INPUT_OUTPUT = ((GPIO_MODE_DEF_INPUT) | (GPIO_MODE_DEF_OUTPUT)), /*!< GPIO mode : output and input mode */
} gpio_mode_t;
typedef enum {
GPIO_PULLUP_DISABLE = 0x0, /*!< Disable GPIO pull-up resistor */
GPIO_PULLUP_ENABLE = 0x1, /*!< Enable GPIO pull-up resistor */
} gpio_pullup_t;
typedef enum {
GPIO_PULLDOWN_DISABLE = 0x0, /*!< Disable GPIO pull-down resistor */
GPIO_PULLDOWN_ENABLE = 0x1, /*!< Enable GPIO pull-down resistor */
} gpio_pulldown_t;
/**
* @brief Configuration parameters of GPIO pad for gpio_config function
*/
typedef struct {
uint64_t pin_bit_mask; /*!< GPIO pin: set with bit mask, each bit maps to a GPIO */
gpio_mode_t mode; /*!< GPIO mode: set input/output mode */
gpio_pullup_t pull_up_en; /*!< GPIO pull-up */
gpio_pulldown_t pull_down_en; /*!< GPIO pull-down */
gpio_int_type_t intr_type; /*!< GPIO interrupt type */
} gpio_config_t;
typedef enum {
GPIO_PULLUP_ONLY, /*!< Pad pull up */
GPIO_PULLDOWN_ONLY, /*!< Pad pull down */
GPIO_PULLUP_PULLDOWN, /*!< Pad pull up + pull down*/
GPIO_FLOATING, /*!< Pad floating */
} gpio_pull_mode_t;
typedef enum {
GPIO_DRIVE_CAP_0 = 0, /*!< Pad drive capability: weak */
GPIO_DRIVE_CAP_1 = 1, /*!< Pad drive capability: stronger */
GPIO_DRIVE_CAP_2 = 2, /*!< Pad drive capability: medium */
GPIO_DRIVE_CAP_DEFAULT = 2, /*!< Pad drive capability: medium */
GPIO_DRIVE_CAP_3 = 3, /*!< Pad drive capability: strongest */
GPIO_DRIVE_CAP_MAX,
} gpio_drive_cap_t;
typedef void (*gpio_isr_t)(void *);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/hal_defs.h
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// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "esp_log.h"
// platform related stuff
#define HAL_SWAP32(word) __builtin_bswap32(word)
#define HAL_SWAP64(word) __builtin_bswap64(word)
#define HAL_LOGE(...) ESP_LOGE(__VA_ARGS__)
#define HAL_LOGW(...) ESP_LOGW(__VA_ARGS__)
#define HAL_LOGI(...) ESP_LOGI(__VA_ARGS__)
#define HAL_LOGD(...) ESP_LOGD(__VA_ARGS__)
#define HAL_LOGV(...) ESP_LOGV(__VA_ARGS__)
#define STATIC_HAL_REG_CHECK(TAG, ENUM, VAL) _Static_assert((ENUM) == (VAL), #TAG" "#ENUM" definition no longer matches register value")
tools/sdk/esp32s2/include/soc/include/hal/i2c_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for I2C
#pragma once
#include "hal/i2c_ll.h"
#include "hal/i2c_types.h"
/**
* @brief I2C hal Context definition
*/
typedef struct {
i2c_dev_t *dev;
uint32_t version;
} i2c_hal_context_t;
/**
* @brief Write the I2C rxfifo with the given length
*
* @param hal Context of the HAL layer
* @param wr_data Pointer to data buffer
* @param wr_size Amount of data needs write
*
* @return None
*/
#define i2c_hal_write_txfifo(hal,wr_data,wr_size) i2c_ll_write_txfifo((hal)->dev,wr_data,wr_size)
/**
* @brief Read the I2C rxfifo with the given length
*
* @param hal Context of the HAL layer
* @param buf Pointer to data buffer
* @param rd_size Amount of data needs read
*
* @return None
*/
#define i2c_hal_read_rxfifo(hal,buf,rd_size) i2c_ll_read_rxfifo((hal)->dev,buf,rd_size)
/**
* @brief Write I2C cmd register
*
* @param hal Context of the HAL layer
* @param cmd I2C hardware command
* @param cmd_idx The index of the command register, should be less than 16
*
* @return None
*/
#define i2c_hal_write_cmd_reg(hal,cmd, cmd_idx) i2c_ll_write_cmd_reg((hal)->dev,cmd,cmd_idx)
/**
* @brief Configure the I2C to triger a trasaction
*
* @param hal Context of the HAL layer
*
* @return None
*/
#define i2c_hal_trans_start(hal) i2c_ll_trans_start((hal)->dev)
/**
* @brief Enable I2C master RX interrupt
*
* @param hal Context of the HAL layer
*
* @return None
*/
#define i2c_hal_enable_master_rx_it(hal) i2c_ll_master_enable_rx_it((hal)->dev)
/**
* @brief Enable I2C master TX interrupt
*
* @param hal Context of the HAL layer
*
* @return None
*/
#define i2c_hal_enable_master_tx_it(hal) i2c_ll_master_enable_tx_it((hal)->dev)
/**
* @brief Clear I2C slave TX interrupt
*
* @param hal Context of the HAL layer
*
* @return None
*/
#define i2c_hal_slave_clr_tx_it(hal) i2c_ll_slave_clr_tx_it((hal)->dev)
/**
* @brief Clear I2C slave RX interrupt
*
* @param hal Context of the HAL layer
*
* @return None
*/
#define i2c_hal_slave_clr_rx_it(hal) i2c_ll_slave_clr_rx_it((hal)->dev)
/**
* @brief Init the I2C master.
*
* @param hal Context of the HAL layer
* @param i2c_num I2C port number
*
* @return None
*/
void i2c_hal_master_init(i2c_hal_context_t *hal, i2c_port_t i2c_num);
/**
* @brief Init the I2C slave.
*
* @param hal Context of the HAL layer
* @param i2c_num I2C port number
*
* @return None
*/
void i2c_hal_slave_init(i2c_hal_context_t *hal, i2c_port_t i2c_num);
/**
* @brief Reset the I2C hw txfifo
*
* @param hal Context of the HAL layer
*
* @return None
*/
void i2c_hal_txfifo_rst(i2c_hal_context_t *hal);
/**
* @brief Reset the I2C hw rxfifo
*
* @param hal Context of the HAL layer
*
* @return None
*/
void i2c_hal_rxfifo_rst(i2c_hal_context_t *hal);
/**
* @brief Configure the I2C data MSB bit shifted first or LSB bit shifted first.
*
* @param hal Context of the HAL layer
* @param tx_mode Data format of TX
* @param rx_mode Data format of RX
*
* @return None
*/
void i2c_hal_set_data_mode(i2c_hal_context_t *hal, i2c_trans_mode_t tx_mode, i2c_trans_mode_t rx_mode);
/**
* @brief Configure the I2C hardware filter function.
*
* @param hal Context of the HAL layer
* @param filter_num If the glitch period on the line is less than this value(in APB cycle), it will be filtered out
* If `filter_num == 0`, the filter will be disabled
*
* @return None
*/
void i2c_hal_set_filter(i2c_hal_context_t *hal, uint8_t filter_num);
/**
* @brief Get the I2C hardware filter configuration
*
* @param hal Context of the HAL layer
* @param filter_num Pointer to accept the hardware filter configuration
*
* @return None
*/
void i2c_hal_get_filter(i2c_hal_context_t *hal, uint8_t *filter_num);
/**
* @brief Configure the I2C SCL timing
*
* @param hal Context of the HAL layer
* @param hight_period SCL high period
* @param low_period SCL low period
*
* @return None
*/
void i2c_hal_set_scl_timing(i2c_hal_context_t *hal, int hight_period, int low_period);
/**
* @brief Configure the I2C master SCL frequency
*
* @param hal Context of the HAL layer
* @param src_clk The I2C Source clock frequency
* @param scl_freq The SCL frequency to be set
*
* @return None
*/
void i2c_hal_set_scl_freq(i2c_hal_context_t *hal, uint32_t src_clk, uint32_t scl_freq);
/**
* @brief Clear the I2C interrupt status with the given mask
*
* @param hal Context of the HAL layer
* @param mask The interrupt bitmap needs to be clearned
*
* @return None
*/
void i2c_hal_clr_intsts_mask(i2c_hal_context_t *hal, uint32_t mask);
/**
* @brief Enable the I2C interrupt with the given mask
*
* @param hal Context of the HAL layer
* @param mask The interrupt bitmap needs to be enabled
*
* @return None
*/
void i2c_hal_enable_intr_mask(i2c_hal_context_t *hal, uint32_t mask);
/**
* @brief Disable the I2C interrupt with the given mask
*
* @param hal Context of the HAL layer
* @param mask The interrupt bitmap needs to be disabled
*
* @return None
*/
void i2c_hal_disable_intr_mask(i2c_hal_context_t *hal, uint32_t mask);
/**
* @brief Configure the I2C memory access mode, FIFO mode or none FIFO mode
*
* @param hal Context of the HAL layer
* @param fifo_mode_en Set true to enable FIFO access mode, else set it false
*
* @return None
*/
void i2c_hal_set_fifo_mode(i2c_hal_context_t *hal, bool fifo_mode_en);
/**
* @brief Configure the I2C timeout value
*
* @param hal Context of the HAL layer
* @param tout_val the timeout value to be set
*
* @return None
*/
void i2c_hal_set_tout(i2c_hal_context_t *hal, int tout_val);
/**
* @brief Get the I2C time out configuration
*
* @param tout_val Pointer to accept the timeout configuration
*
* @return None
*/
void i2c_hal_get_tout(i2c_hal_context_t *hal, int *tout_val);
/**
* @brief Configure the I2C slave address
*
* @param hal Context of the HAL layer
* @param slave_addr Slave address
* @param addr_10bit_en Set true to enable 10-bit slave address mode, Set false to enable 7-bit address mode
*
* @return None
*/
void i2c_hal_set_slave_addr(i2c_hal_context_t *hal, uint16_t slave_addr, bool addr_10bit_en);
/**
* @brief Configure the I2C stop timing
*
* @param hal Context of the HAL layer
* @param stop_setup The stop condition setup period (in APB cycle)
* @param stop_hold The stop condition hold period (in APB cycle)
*
* @return None
*/
void i2c_hal_set_stop_timing(i2c_hal_context_t *hal, int stop_setup, int stop_hold);
/**
* @brief Configure the I2C start timing
*
* @param hal Context of the HAL layer
* @param start_setup The start condition setup period (in APB cycle)
* @param start_hold The start condition hold period (in APB cycle)
*
* @return None
*/
void i2c_hal_set_start_timing(i2c_hal_context_t *hal, int start_setup, int start_hold);
/**
* @brief Configure the I2C sda sample timing
*
* @param hal Context of the HAL layer
* @param sda_sample The SDA sample time (in APB cycle)
* @param sda_hold The SDA hold time (in APB cycle)
*
* @return None
*/
void i2c_hal_set_sda_timing(i2c_hal_context_t *hal, int sda_sample, int sda_hold);
/**
* @brief Configure the I2C txfifo empty threshold value
*
* @param hal Context of the HAL layer.
* @param empty_thr TxFIFO empty threshold value
*
* @return None
*/
void i2c_hal_set_txfifo_empty_thr(i2c_hal_context_t *hal, uint8_t empty_thr);
/**
* @brief Configure the I2C rxfifo full threshold value
*
* @param hal Context of the HAL layer
* @param full_thr RxFIFO full threshold value
*
* @return None
*/
void i2c_hal_set_rxfifo_full_thr(i2c_hal_context_t *hal, uint8_t full_thr);
/**
* @brief Get the I2C interrupt status
*
* @param hal Context of the HAL layer
* @param mask Pointer to accept the interrupt status
*
* @return None
*/
void i2c_hal_get_intsts_mask(i2c_hal_context_t *hal, uint32_t *mask);
/**
* @brief Check if the I2C bus is busy
*
* @param hal Context of the HAL layer
*
* @return True if the bus is busy, otherwise, fale will be returned
*/
bool i2c_hal_is_bus_busy(i2c_hal_context_t *hal);
/**
* @brief Get the I2C sda sample timing configuration
*
* @param hal Context of the HAL layer
* @param sample_time Pointer to accept the SDA sample time
* @param hold_time Pointer to accept the SDA hold time
*
* @return None
*/
void i2c_hal_get_sda_timing(i2c_hal_context_t *hal, int *sample_time, int *hold_time);
/**
* @brief Get the I2C stop timing configuration
*
* @param hal Context of the HAL layer
* @param setup_time Pointer to accept the stop condition setup period
* @param hold_time Pointer to accept the stop condition hold period
*
* @return None
*/
void i2c_hal_get_stop_timing(i2c_hal_context_t *hal, int *setup_time, int *hold_time);
/**
* @brief Get the I2C scl timing configuration
*
* @param hal Context of the HAL layer
* @param high_period Pointer to accept the scl high period
* @param low_period Pointer to accept the scl low period
*
* @return None
*/
void i2c_hal_get_scl_timing(i2c_hal_context_t *hal, int *high_period, int *low_period);
/**
* @brief Get the I2C start timing configuration
*
* @param hal Context of the HAL layer
* @param setup_time Pointer to accept the start condition setup period
* @param hold_time Pointer to accept the start condition hold period
*
* @return None
*/
void i2c_hal_get_start_timing(i2c_hal_context_t *hal, int *setup_time, int *hold_time);
/**
* @brief Check if the I2C is master mode
*
* @param hal Context of the HAL layer
*
* @return True if in master mode, otherwise, false will be returned
*/
bool i2c_hal_is_master_mode(i2c_hal_context_t *hal);
/**
* @brief Get the rxFIFO readable length
*
* @param hal Context of the HAL layer
* @param len Pointer to accept the rxFIFO readable length
*
* @return None
*/
void i2c_hal_get_rxfifo_cnt(i2c_hal_context_t *hal, uint32_t *len);
/**
* @brief Set I2C bus timing with the given frequency
*
* @param hal Context of the HAL layer
* @param scl_freq The scl frequency to be set
* @param src_clk Source clock of I2C
*
* @return None
*/
void i2c_hal_set_bus_timing(i2c_hal_context_t *hal, uint32_t scl_freq, i2c_sclk_t src_clk);
/**
* @brief Get I2C txFIFO writeable length
*
* @param hal Context of the HAL layer
* @param len Pointer to accept the txFIFO writeable length
*
* @return None
*/
void i2c_hal_get_txfifo_cnt(i2c_hal_context_t *hal, uint32_t *len);
/**
* @brief Check if the I2C is master mode
*
* @param hal Context of the HAL layer
* @param tx_mode Pointer to accept the TX data mode
* @param rx_mode Pointer to accept the RX data mode
*
* @return None
*/
void i2c_hal_get_data_mode(i2c_hal_context_t *hal, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode);
/**
* @brief I2C hardware FSM reset
*
* @param hal Context of the HAL layer
*
* @return None
*/
void i2c_hal_master_fsm_rst(i2c_hal_context_t *hal);
/**
* @brief @brief Clear I2C bus
*
* @param hal Context of the HAL layer
*
* @return None
*/
void i2c_hal_master_clr_bus(i2c_hal_context_t *hal);
/**
* @brief Enable I2C slave TX interrupt
*
* @param hal Context of the HAL layer
*
* @return None
*/
void i2c_hal_enable_slave_tx_it(i2c_hal_context_t *hal);
/**
* @brief Disable I2C slave TX interrupt
*
* @param hal Context of the HAL layer
*
* @return None
*/
void i2c_hal_disable_slave_tx_it(i2c_hal_context_t *hal);
/**
* @brief Enable I2C slave RX interrupt
*
* @param hal Context of the HAL layer
*
* @return None
*/
void i2c_hal_enable_slave_rx_it(i2c_hal_context_t *hal);
/**
* @brief Disable I2C slave RX interrupt
*
* @param hal Context of the HAL layer
*
* @return None
*/
void i2c_hal_disable_slave_rx_it(i2c_hal_context_t *hal);
/**
* @brief I2C master handle tx interrupt event
*
* @param hal Context of the HAL layer
* @param event Pointer to accept the interrupt event
*
* @return None
*/
void i2c_hal_master_handle_tx_event(i2c_hal_context_t *hal, i2c_intr_event_t *event);
/**
* @brief I2C master handle rx interrupt event
*
* @param hal Context of the HAL layer
* @param event Pointer to accept the interrupt event
*
* @return None
*/
void i2c_hal_master_handle_rx_event(i2c_hal_context_t *hal, i2c_intr_event_t *event);
/**
* @brief I2C slave handle interrupt event
*
* @param hal Context of the HAL layer
* @param event Pointer to accept the interrupt event
*
* @return None
*/
void i2c_hal_slave_handle_event(i2c_hal_context_t *hal, i2c_intr_event_t *event);
tools/sdk/esp32s2/include/soc/include/hal/i2c_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include "soc/i2c_caps.h"
/**
* @brief I2C port number, can be I2C_NUM_0 ~ (I2C_NUM_MAX-1).
*/
typedef int i2c_port_t;
typedef enum{
I2C_MODE_SLAVE = 0, /*!< I2C slave mode */
I2C_MODE_MASTER, /*!< I2C master mode */
I2C_MODE_MAX,
} i2c_mode_t;
typedef enum {
I2C_MASTER_WRITE = 0, /*!< I2C write data */
I2C_MASTER_READ, /*!< I2C read data */
} i2c_rw_t;
typedef enum{
I2C_CMD_RESTART = 0, /*!<I2C restart command */
I2C_CMD_WRITE, /*!<I2C write command */
I2C_CMD_READ, /*!<I2C read command */
I2C_CMD_STOP, /*!<I2C stop command */
I2C_CMD_END /*!<I2C end command */
} i2c_opmode_t;
typedef enum {
I2C_DATA_MODE_MSB_FIRST = 0, /*!< I2C data msb first */
I2C_DATA_MODE_LSB_FIRST = 1, /*!< I2C data lsb first */
I2C_DATA_MODE_MAX
} i2c_trans_mode_t;
typedef enum {
I2C_ADDR_BIT_7 = 0, /*!< I2C 7bit address for slave mode */
I2C_ADDR_BIT_10, /*!< I2C 10bit address for slave mode */
I2C_ADDR_BIT_MAX,
} i2c_addr_mode_t;
typedef enum {
I2C_MASTER_ACK = 0x0, /*!< I2C ack for each byte read */
I2C_MASTER_NACK = 0x1, /*!< I2C nack for each byte read */
I2C_MASTER_LAST_NACK = 0x2, /*!< I2C nack for the last byte*/
I2C_MASTER_ACK_MAX,
} i2c_ack_type_t;
typedef enum {
I2C_SCLK_REF_TICK, /*!< I2C source clock from REF_TICK */
I2C_SCLK_APB, /*!< I2C source clock from APB */
} i2c_sclk_t;
/**
* @brief I2C initialization parameters
*/
typedef struct{
i2c_mode_t mode; /*!< I2C mode */
int sda_io_num; /*!< GPIO number for I2C sda signal */
int scl_io_num; /*!< GPIO number for I2C scl signal */
bool sda_pullup_en; /*!< Internal GPIO pull mode for I2C sda signal*/
bool scl_pullup_en; /*!< Internal GPIO pull mode for I2C scl signal*/
union {
struct {
uint32_t clk_speed; /*!< I2C clock frequency for master mode, (no higher than 1MHz for now) */
} master; /*!< I2C master config */
struct {
uint8_t addr_10bit_en; /*!< I2C 10bit address mode enable for slave mode */
uint16_t slave_addr; /*!< I2C address for slave mode */
} slave; /*!< I2C slave config */
};
} i2c_config_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/i2s_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for I2S.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#include "soc/i2s_periph.h"
#include "soc/i2s_caps.h"
#include "hal/i2s_ll.h"
#include "hal/i2s_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
i2s_dev_t *dev;
uint32_t version;
} i2s_hal_context_t;
/**
* @brief Reset I2S fifo
*
* @param hal Context of the HAL layer
*/
void i2s_hal_reset_fifo(i2s_hal_context_t *hal);
/**
* @brief Get I2S interrupt status
*
* @param hal Context of the HAL layer
* @param status interrupt status
*/
#define i2s_hal_get_intr_status(hal, status) i2s_ll_get_intr_status((hal)->dev, status)
/**
* @brief Clear I2S interrupt status
*
* @param hal Context of the HAL layer
* @param mask interrupt status mask
*/
#define i2s_hal_clear_intr_status(hal, mask) i2s_ll_clear_intr_status((hal)->dev, mask)
/**
* @brief Get I2S out eof des address
*
* @param hal Context of the HAL layer
* @param addr out eof des address
*/
#define i2s_hal_get_out_eof_des_addr(hal, addr) i2s_ll_get_out_eof_des_addr((hal)->dev, addr)
/**
* @brief Get I2S in eof des address
*
* @param hal Context of the HAL layer
* @param addr in eof des address
*/
#define i2s_hal_get_in_eof_des_addr(hal, addr) i2s_ll_get_in_eof_des_addr((hal)->dev, addr)
/**
* @brief Enable I2S rx interrupt
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_enable_rx_intr(hal) i2s_ll_enable_rx_intr((hal)->dev)
/**
* @brief Disable I2S rx interrupt
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_disable_rx_intr(hal) i2s_ll_disable_rx_intr((hal)->dev)
/**
* @brief Disable I2S tx interrupt
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_disable_tx_intr(hal) i2s_ll_disable_tx_intr((hal)->dev)
/**
* @brief Enable I2S tx interrupt
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_enable_tx_intr(hal) i2s_ll_enable_tx_intr((hal)->dev)
/**
* @brief Set I2S tx mode
*
* @param hal Context of the HAL layer
* @param ch i2s channel
* @param bits bits per sample
*/
void i2s_hal_set_tx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_sample_t bits);
/**
* @brief Set I2S rx mode
*
* @param hal Context of the HAL layer
* @param ch i2s channel
* @param bits bits per sample
*/
void i2s_hal_set_rx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_sample_t bits);
/**
* @brief Set I2S out link address
*
* @param hal Context of the HAL layer
* @param addr out link address
*/
#define i2s_hal_set_out_link_addr(hal, addr) i2s_ll_set_out_link_addr((hal)->dev, addr)
/**
* @brief Set I2S out link address
*
* @param hal Context of the HAL layer
* @param addr out link address
*/
#define i2s_hal_set_out_link_addr(hal, addr) i2s_ll_set_out_link_addr((hal)->dev, addr)
/**
* @brief Set I2S out link address
*
* @param hal Context of the HAL layer
* @param addr out link address
*/
#define i2s_hal_set_out_link_addr(hal, addr) i2s_ll_set_out_link_addr((hal)->dev, addr)
/**
* @brief Set I2S in link
*
* @param hal Context of the HAL layer
* @param rx_eof_num in link eof num
* @param addr in link address
*/
void i2s_hal_set_in_link(i2s_hal_context_t *hal, uint32_t rx_eof_num, uint32_t addr);
#if SOC_I2S_SUPPORTS_PDM
/**
* @brief Get I2S tx pdm
*
* @param hal Context of the HAL layer
* @param fp tx pdm fp
* @param fs tx pdm fs
*/
void i2s_hal_get_tx_pdm(i2s_hal_context_t *hal, int *fp, int *fs);
#endif
/**
* @brief Get I2S rx sinc dsr 16 en
*
* @param hal Context of the HAL layer
* @param en 0: disable, 1: enable
*/
#define i2s_hal_get_rx_sinc_dsr_16_en(hal, en) i2s_ll_get_rx_sinc_dsr_16_en((hal)->dev, en)
/**
* @brief Set I2S clk div
*
* @param hal Context of the HAL layer
* @param div_num i2s clkm div num
* @param div_a i2s clkm div a
* @param div_b i2s clkm div b
* @param tx_bck_div tx bck div num
* @param rx_bck_div rx bck div num
*/
void i2s_hal_set_clk_div(i2s_hal_context_t *hal, int div_num, int div_a, int div_b, int tx_bck_div, int rx_bck_div);
/**
* @brief Set I2S clock sel
*
* @param hal Context of the HAL layer
* @param sel clock sel
*/
#define i2s_hal_set_clock_sel(hal, sel) i2s_ll_set_clk_sel((hal)->dev, sel)
/**
* @brief Set I2S tx bits mod
*
* @param hal Context of the HAL layer
* @param bits bit width per sample.
*/
void i2s_hal_set_tx_bits_mod(i2s_hal_context_t *hal, i2s_bits_per_sample_t bits);
/**
* @brief Set I2S rx bits mod
*
* @param hal Context of the HAL layer
* @param bits bit width per sample.
*/
void i2s_hal_set_rx_bits_mod(i2s_hal_context_t *hal, i2s_bits_per_sample_t bits);
/**
* @brief Reset I2S tx
*
* @param hal Context of the HAL layer
*/
void i2s_hal_reset(i2s_hal_context_t *hal);
/**
* @brief Start I2S tx
*
* @param hal Context of the HAL layer
*/
void i2s_hal_start_tx(i2s_hal_context_t *hal);
/**
* @brief Start I2S rx
*
* @param hal Context of the HAL layer
*/
void i2s_hal_start_rx(i2s_hal_context_t *hal);
/**
* @brief Stop I2S tx
*
* @param hal Context of the HAL layer
*/
void i2s_hal_stop_tx(i2s_hal_context_t *hal);
/**
* @brief Stop I2S rx
*
* @param hal Context of the HAL layer
*/
void i2s_hal_stop_rx(i2s_hal_context_t *hal);
#if SOC_I2S_SUPPORTS_PDM
/**
* @brief Set I2S pdm rx down sample
*
* @param hal Context of the HAL layer
* @param dsr 0:disable, 1: enable
*/
#define i2s_hal_set_pdm_rx_down_sample(hal, dsr) i2s_ll_set_rx_sinc_dsr_16_en((hal)->dev, dsr)
#endif
/**
* @brief Config I2S param
*
* @param hal Context of the HAL layer
* @param i2s_config I2S configurations - see i2s_config_t struct
*/
void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_config_t *i2s_config);
/**
* @brief Enable I2S sig loopback
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_enable_sig_loopback(hal) i2s_ll_set_sig_loopback((hal)->dev, 1)
/**
* @brief Enable I2S master mode
*
* @param hal Context of the HAL layer
*/
void i2s_hal_enable_master_mode(i2s_hal_context_t *hal);
/**
* @brief Enable I2S slave mode
*
* @param hal Context of the HAL layer
*/
void i2s_hal_enable_slave_mode(i2s_hal_context_t *hal);
/**
* @brief Init the I2S hal and set the I2S to the default configuration. This function should be called first before other hal layer function is called
*
* @param hal Context of the HAL layer
* @param i2s_num The uart port number, the max port number is (I2S_NUM_MAX -1)
*/
void i2s_hal_init(i2s_hal_context_t *hal, int i2s_num);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/i2s_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include <stdlib.h>
#include <stddef.h>
#include "soc/i2s_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief I2S port number, the max port number is (I2S_NUM_MAX -1).
*/
typedef enum {
I2S_NUM_0 = 0, /*!< I2S port 0 */
#if SOC_I2S_NUM > 1
I2S_NUM_1 = 1, /*!< I2S port 1 */
#endif
I2S_NUM_MAX, /*!< I2S port max */
} i2s_port_t;
#define I2S_PIN_NO_CHANGE (-1) /*!< Use in i2s_pin_config_t for pins which should not be changed */
/**
* @brief I2S bit width per sample.
*
*/
typedef enum {
I2S_BITS_PER_SAMPLE_8BIT = 8, /*!< I2S bits per sample: 8-bits*/
I2S_BITS_PER_SAMPLE_16BIT = 16, /*!< I2S bits per sample: 16-bits*/
I2S_BITS_PER_SAMPLE_24BIT = 24, /*!< I2S bits per sample: 24-bits*/
I2S_BITS_PER_SAMPLE_32BIT = 32, /*!< I2S bits per sample: 32-bits*/
} i2s_bits_per_sample_t;
/**
* @brief I2S channel.
*
*/
typedef enum {
I2S_CHANNEL_MONO = 1, /*!< I2S 1 channel (mono)*/
I2S_CHANNEL_STEREO = 2 /*!< I2S 2 channel (stereo)*/
} i2s_channel_t;
/**
* @brief I2S communication standard format
*
*/
typedef enum {
I2S_COMM_FORMAT_I2S = 0x01, /*!< I2S communication format I2S*/
I2S_COMM_FORMAT_I2S_MSB = 0x02, /*!< I2S format MSB*/
I2S_COMM_FORMAT_I2S_LSB = 0x04, /*!< I2S format LSB*/
I2S_COMM_FORMAT_PCM = 0x08, /*!< I2S communication format PCM*/
I2S_COMM_FORMAT_PCM_SHORT = 0x10, /*!< PCM Short*/
I2S_COMM_FORMAT_PCM_LONG = 0x20, /*!< PCM Long*/
} i2s_comm_format_t;
/**
* @brief I2S channel format type
*/
typedef enum {
I2S_CHANNEL_FMT_RIGHT_LEFT = 0x00,
I2S_CHANNEL_FMT_ALL_RIGHT,
I2S_CHANNEL_FMT_ALL_LEFT,
I2S_CHANNEL_FMT_ONLY_RIGHT,
I2S_CHANNEL_FMT_ONLY_LEFT,
} i2s_channel_fmt_t;
#if SOC_I2S_SUPPORTS_PDM
/**
* @brief PDM sample rate ratio, measured in Hz.
*
*/
typedef enum {
PDM_SAMPLE_RATE_RATIO_64,
PDM_SAMPLE_RATE_RATIO_128,
} pdm_sample_rate_ratio_t;
/**
* @brief PDM PCM convter enable/disable.
*
*/
typedef enum {
PDM_PCM_CONV_ENABLE,
PDM_PCM_CONV_DISABLE,
} pdm_pcm_conv_t;
#endif
/**
* @brief I2S Mode, defaut is I2S_MODE_MASTER | I2S_MODE_TX
*
* @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip.
*
*/
typedef enum {
I2S_MODE_MASTER = 1,
I2S_MODE_SLAVE = 2,
I2S_MODE_TX = 4,
I2S_MODE_RX = 8,
#if SOC_I2S_SUPPORTS_ADC_DAC
I2S_MODE_DAC_BUILT_IN = 16, /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/
I2S_MODE_ADC_BUILT_IN = 32, /*!< Input I2S data from built-in ADC, each data can be 12-bit width at most*/
#endif
#if SOC_I2S_SUPPORTS_PDM
I2S_MODE_PDM = 64,
#endif
} i2s_mode_t;
/**
* @brief I2S configuration parameters for i2s_param_config function
*
*/
typedef struct {
i2s_mode_t mode; /*!< I2S work mode*/
int sample_rate; /*!< I2S sample rate*/
i2s_bits_per_sample_t bits_per_sample; /*!< I2S bits per sample*/
i2s_channel_fmt_t channel_format; /*!< I2S channel format */
i2s_comm_format_t communication_format; /*!< I2S communication format */
int intr_alloc_flags; /*!< Flags used to allocate the interrupt. One or multiple (ORred) ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info */
int dma_buf_count; /*!< I2S DMA Buffer Count */
int dma_buf_len; /*!< I2S DMA Buffer Length */
bool use_apll; /*!< I2S using APLL as main I2S clock, enable it to get accurate clock */
bool tx_desc_auto_clear; /*!< I2S auto clear tx descriptor if there is underflow condition (helps in avoiding noise in case of data unavailability) */
int fixed_mclk; /*!< I2S using fixed MCLK output. If use_apll = true and fixed_mclk > 0, then the clock output for i2s is fixed and equal to the fixed_mclk value.*/
} i2s_config_t;
/**
* @brief I2S event types
*
*/
typedef enum {
I2S_EVENT_DMA_ERROR,
I2S_EVENT_TX_DONE, /*!< I2S DMA finish sent 1 buffer*/
I2S_EVENT_RX_DONE, /*!< I2S DMA finish received 1 buffer*/
I2S_EVENT_MAX, /*!< I2S event max index*/
} i2s_event_type_t;
/**
* @brief I2S DAC mode for i2s_set_dac_mode.
*
* @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip.
*/
typedef enum {
I2S_DAC_CHANNEL_DISABLE = 0, /*!< Disable I2S built-in DAC signals*/
I2S_DAC_CHANNEL_RIGHT_EN = 1, /*!< Enable I2S built-in DAC right channel, maps to DAC channel 1 on GPIO25*/
I2S_DAC_CHANNEL_LEFT_EN = 2, /*!< Enable I2S built-in DAC left channel, maps to DAC channel 2 on GPIO26*/
I2S_DAC_CHANNEL_BOTH_EN = 0x3, /*!< Enable both of the I2S built-in DAC channels.*/
I2S_DAC_CHANNEL_MAX = 0x4, /*!< I2S built-in DAC mode max index*/
} i2s_dac_mode_t;
/**
* @brief Event structure used in I2S event queue
*
*/
typedef struct {
i2s_event_type_t type; /*!< I2S event type */
size_t size; /*!< I2S data size for I2S_DATA event*/
} i2s_event_t;
/**
* @brief I2S pin number for i2s_set_pin
*
*/
typedef struct {
int bck_io_num; /*!< BCK in out pin*/
int ws_io_num; /*!< WS in out pin*/
int data_out_num; /*!< DATA out pin*/
int data_in_num; /*!< DATA in pin*/
} i2s_pin_config_t;
#if SOC_I2S_SUPPORTS_PDM
/**
* @brief I2S PDM RX downsample mode
*/
typedef enum {
I2S_PDM_DSR_8S = 0, /*!< downsampling number is 8 for PDM RX mode*/
I2S_PDM_DSR_16S, /*!< downsampling number is 16 for PDM RX mode*/
I2S_PDM_DSR_MAX,
} i2s_pdm_dsr_t;
#endif
typedef enum {
I2S_CLK_D2CLK = 0,
I2S_CLK_APLL,
} i2s_clock_src_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/ledc_hal.h
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for LEDC.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#include "hal/ledc_ll.h"
#include "hal/ledc_types.h"
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
ledc_dev_t *dev;
ledc_mode_t speed_mode;
} ledc_hal_context_t;
/**
* @brief Set LEDC low speed timer clock
*
* @param hal Context of the HAL layer
* @param slow_clk_sel LEDC low speed timer clock source
*
* @return None
*/
#define ledc_hal_set_slow_clk_sel(hal, slow_clk_sel) ledc_ll_set_slow_clk_sel((hal)->dev, slow_clk_sel)
/**
* @brief Get LEDC low speed timer clock
*
* @param hal Context of the HAL layer
* @param slow_clk_sel LEDC low speed timer clock source
*
* @return None
*/
#define ledc_hal_get_slow_clk_sel(hal, slow_clk_sel) ledc_ll_get_slow_clk_sel((hal)->dev, slow_clk_sel)
/**
* @brief Update LEDC low speed timer
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
*
* @return None
*/
#define ledc_hal_ls_timer_update(hal, timer_sel) ledc_ll_ls_timer_update((hal)->dev, (hal)->speed_mode, timer_sel)
/**
* @brief Reset LEDC timer
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
*
* @return None
*/
#define ledc_hal_timer_rst(hal, timer_sel) ledc_ll_timer_rst((hal)->dev, (hal)->speed_mode, timer_sel)
/**
* @brief Pause LEDC timer
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
*
* @return None
*/
#define ledc_hal_timer_pause(hal, timer_sel) ledc_ll_timer_pause((hal)->dev, (hal)->speed_mode, timer_sel)
/**
* @brief Resume LEDC timer
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
*
* @return None
*/
#define ledc_hal_timer_resume(hal, timer_sel) ledc_ll_timer_resume((hal)->dev, (hal)->speed_mode, timer_sel)
/**
* @brief Set LEDC timer clock divider
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
* @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source
*
* @return None
*/
#define ledc_hal_set_clock_divider(hal, timer_sel, clock_divider) ledc_ll_set_clock_divider((hal)->dev, (hal)->speed_mode, timer_sel, clock_divider)
/**
* @brief Get LEDC timer clock divider
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
* @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source
*
* @return None
*/
#define ledc_hal_get_clock_divider(hal, timer_sel, clock_divider) ledc_ll_get_clock_divider((hal)->dev, (hal)->speed_mode, timer_sel, clock_divider)
/**
* @brief Set LEDC timer clock source
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
* @param clk_src Timer clock source
*
* @return None
*/
#define ledc_hal_set_clock_source(hal, timer_sel, clk_src) ledc_ll_set_clock_source((hal)->dev, (hal)->speed_mode, timer_sel, clk_src)
/**
* @brief Get LEDC timer clock source
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
* @param clk_src Pointer to accept the timer clock source
*
* @return None
*/
#define ledc_hal_get_clock_source(hal, timer_sel, clk_src) ledc_ll_get_clock_source((hal)->dev, (hal)->speed_mode, timer_sel, clk_src)
/**
* @brief Set LEDC duty resolution
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
* @param duty_resolution Resolution of duty setting in number of bits. The range of duty values is [0, (2**duty_resolution)]
*
* @return None
*/
#define ledc_hal_set_duty_resolution(hal, timer_sel, duty_resolution) ledc_ll_set_duty_resolution((hal)->dev, (hal)->speed_mode, timer_sel, duty_resolution)
/**
* @brief Get LEDC duty resolution
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
* @param duty_resolution Pointer to accept the resolution of duty setting in number of bits.
*
* @return None
*/
#define ledc_hal_get_duty_resolution(hal, timer_sel, duty_resolution) ledc_ll_get_duty_resolution((hal)->dev, (hal)->speed_mode, timer_sel, duty_resolution)
/**
* @brief Get LEDC max duty
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param max_duty Pointer to accept the max duty
*
* @return None
*/
#define ledc_hal_get_max_duty(hal, channel_num, max_duty) ledc_ll_get_max_duty((hal)->dev, (hal)->speed_mode, channel_num, max_duty)
/**
* @brief Get LEDC hpoint value
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param hpoint_val Pointer to accept the LEDC hpoint value(max: 0xfffff)
*
* @return None
*/
#define ledc_hal_get_hpoint(hal, channel_num, hpoint_val) ledc_ll_get_hpoint((hal)->dev, (hal)->speed_mode, channel_num, hpoint_val)
/**
* @brief Set LEDC the integer part of duty value
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param duty_val LEDC duty value, the range of duty setting is [0, (2**duty_resolution)]
*
* @return None
*/
#define ledc_hal_set_duty_int_part(hal, channel_num, duty_val) ledc_ll_set_duty_int_part((hal)->dev, (hal)->speed_mode, channel_num, duty_val)
/**
* @brief Set the output enable
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param sig_out_en The output enable status
*
* @return None
*/
#define ledc_hal_set_sig_out_en(hal, channel_num, sig_out_en) ledc_ll_set_sig_out_en((hal)->dev, (hal)->speed_mode, channel_num, sig_out_en)
/**
* @brief Set the duty start
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param duty_start The duty start
*
* @return None
*/
#define ledc_hal_set_duty_start(hal, channel_num, duty_start) ledc_ll_set_duty_start((hal)->dev, (hal)->speed_mode, channel_num, duty_start)
/**
* @brief Set output idle level
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param idle_level The output idle level
*
* @return None
*/
#define ledc_hal_set_idle_level(hal, channel_num, idle_level) ledc_ll_set_idle_level((hal)->dev, (hal)->speed_mode, channel_num, idle_level)
/**
* @brief Set fade end interrupt enable
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param fade_end_intr_en The fade end interrupt enable status
*
* @return None
*/
#define ledc_hal_set_fade_end_intr(hal, channel_num, fade_end_intr_en) ledc_ll_set_fade_end_intr((hal)->dev, (hal)->speed_mode, channel_num, fade_end_intr_en)
/**
* @brief Set timer index of the specified channel
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
*
* @return None
*/
#define ledc_hal_bind_channel_timer(hal, channel_num, timer_sel) ledc_ll_bind_channel_timer((hal)->dev, (hal)->speed_mode, channel_num, timer_sel)
/**
* @brief Get timer index of the specified channel
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param timer_sel Pointer to accept the LEDC timer index
*
* @return None
*/
#define ledc_hal_get_channel_timer(hal, channel_num, timer_sel) ledc_ll_get_channel_timer((hal)->dev, (hal)->speed_mode, channel_num, timer_sel)
/**
* @brief Init the LEDC hal. This function should be called first before other hal layer function is called
*
* @param hal Context of the HAL layer
* @param speed_mode speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mod
*
* @return None
*/
void ledc_hal_init(ledc_hal_context_t *hal, ledc_mode_t speed_mode);
/**
* @brief Update channel configure when select low speed mode
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
*
* @return None
*/
void ledc_hal_ls_channel_update(ledc_hal_context_t *hal, ledc_channel_t channel_num);
/**
* @brief Set LEDC hpoint value
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param hpoint_val LEDC hpoint value(max: 0xfffff)
*
* @return None
*/
void ledc_hal_set_hpoint(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t hpoint_val);
/**
* @brief Get LEDC duty value
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param duty_val Pointer to accept the LEDC duty value
*
* @return None
*/
void ledc_hal_get_duty(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t *duty_val);
/**
* @brief Set LEDC duty change direction
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param duty_direction LEDC duty change direction, increase or decrease
*
* @return None
*/
void ledc_hal_set_duty_direction(ledc_hal_context_t *hal, ledc_channel_t channel_num, ledc_duty_direction_t duty_direction);
/**
* @brief Set the number of increased or decreased times
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param duty_num The number of increased or decreased times
*
* @return None
*/
void ledc_hal_set_duty_num(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t duty_num);
/**
* @brief Set the duty cycles of increase or decrease
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param duty_cycle The duty cycles
*
* @return None
*/
void ledc_hal_set_duty_cycle(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t duty_cycle);
/**
* @brief Set the step scale of increase or decrease
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param duty_scale The step scale
*
* @return None
*/
void ledc_hal_set_duty_scale(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t duty_scale);
/**
* @brief Get interrupt status of the specified channel
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param intr_status Pointer to accept the interrupt status
*
* @return None
*/
void ledc_hal_get_fade_end_intr_status(ledc_hal_context_t *hal, uint32_t *intr_status);
/**
* @brief Clear interrupt status of the specified channel
*
* @param hal Context of the HAL layer
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
*
* @return None
*/
void ledc_hal_clear_fade_end_intr_status(ledc_hal_context_t *hal, ledc_channel_t channel_num);
/**
* @brief Get clock config of LEDC timer
*
* @param hal Context of the HAL layer
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
* @param clk_cfg Pointer to accept clock config
*
* @return None
*/
void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_clk_cfg_t *clk_cfg);
/**
* @brief Config low speed timer clock source with clock config
*s
* @param hal Context of the HAL layer
* @param clk_cfg clock config
*
* @return None
*/
void ledc_hal_set_slow_clk(ledc_hal_context_t *hal, ledc_clk_cfg_t clk_cfg);
tools/sdk/esp32s2/include/soc/include/hal/ledc_types.h
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include "soc/ledc_caps.h"
typedef enum {
#ifdef SOC_LEDC_SUPPORT_HS_MODE
LEDC_HIGH_SPEED_MODE = 0, /*!< LEDC high speed speed_mode */
#endif
LEDC_LOW_SPEED_MODE, /*!< LEDC low speed speed_mode */
LEDC_SPEED_MODE_MAX, /*!< LEDC speed limit */
} ledc_mode_t;
typedef enum {
LEDC_INTR_DISABLE = 0, /*!< Disable LEDC interrupt */
LEDC_INTR_FADE_END, /*!< Enable LEDC interrupt */
LEDC_INTR_MAX,
} ledc_intr_type_t;
typedef enum {
LEDC_DUTY_DIR_DECREASE = 0, /*!< LEDC duty decrease direction */
LEDC_DUTY_DIR_INCREASE = 1, /*!< LEDC duty increase direction */
LEDC_DUTY_DIR_MAX,
} ledc_duty_direction_t;
typedef enum {
LEDC_SLOW_CLK_RTC8M = 0, /*!< LEDC low speed timer clock source is 8MHz RTC clock*/
LEDC_SLOW_CLK_APB, /*!< LEDC low speed timer clock source is 80MHz APB clock*/
#ifdef SOC_LEDC_SUPPORT_XTAL_CLOCK
LEDC_SLOW_CLK_XTAL, /*!< LEDC low speed timer clock source XTAL clock*/
#endif
} ledc_slow_clk_sel_t;
typedef enum {
LEDC_AUTO_CLK = 0, /*!< The driver will automatically select the source clock(REF_TICK or APB) based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_REF_TICK, /*!< LEDC timer select REF_TICK clock as source clock*/
LEDC_USE_APB_CLK, /*!< LEDC timer select APB clock as source clock*/
LEDC_USE_RTC8M_CLK, /*!< LEDC timer select RTC8M_CLK as source clock. Only for low speed channels and this parameter must be the same for all low speed channels*/
#ifdef SOC_LEDC_SUPPORT_XTAL_CLOCK
LEDC_USE_XTAL_CLK, /*!< LEDC timer select XTAL clock as source clock*/
#endif
} ledc_clk_cfg_t;
/* Note: Setting numeric values to match ledc_clk_cfg_t values are a hack to avoid collision with
LEDC_AUTO_CLK in the driver, as these enums have very similar names and user may pass
one of these by mistake. */
typedef enum {
LEDC_REF_TICK = LEDC_USE_REF_TICK, /*!< LEDC timer clock divided from reference tick (1Mhz) */
LEDC_APB_CLK = LEDC_USE_APB_CLK, /*!< LEDC timer clock divided from APB clock (80Mhz) */
} ledc_clk_src_t;
typedef enum {
LEDC_TIMER_0 = 0, /*!< LEDC timer 0 */
LEDC_TIMER_1, /*!< LEDC timer 1 */
LEDC_TIMER_2, /*!< LEDC timer 2 */
LEDC_TIMER_3, /*!< LEDC timer 3 */
LEDC_TIMER_MAX,
} ledc_timer_t;
typedef enum {
LEDC_CHANNEL_0 = 0, /*!< LEDC channel 0 */
LEDC_CHANNEL_1, /*!< LEDC channel 1 */
LEDC_CHANNEL_2, /*!< LEDC channel 2 */
LEDC_CHANNEL_3, /*!< LEDC channel 3 */
LEDC_CHANNEL_4, /*!< LEDC channel 4 */
LEDC_CHANNEL_5, /*!< LEDC channel 5 */
LEDC_CHANNEL_6, /*!< LEDC channel 6 */
LEDC_CHANNEL_7, /*!< LEDC channel 7 */
LEDC_CHANNEL_MAX,
} ledc_channel_t;
typedef enum {
LEDC_TIMER_1_BIT = 1, /*!< LEDC PWM duty resolution of 1 bits */
LEDC_TIMER_2_BIT, /*!< LEDC PWM duty resolution of 2 bits */
LEDC_TIMER_3_BIT, /*!< LEDC PWM duty resolution of 3 bits */
LEDC_TIMER_4_BIT, /*!< LEDC PWM duty resolution of 4 bits */
LEDC_TIMER_5_BIT, /*!< LEDC PWM duty resolution of 5 bits */
LEDC_TIMER_6_BIT, /*!< LEDC PWM duty resolution of 6 bits */
LEDC_TIMER_7_BIT, /*!< LEDC PWM duty resolution of 7 bits */
LEDC_TIMER_8_BIT, /*!< LEDC PWM duty resolution of 8 bits */
LEDC_TIMER_9_BIT, /*!< LEDC PWM duty resolution of 9 bits */
LEDC_TIMER_10_BIT, /*!< LEDC PWM duty resolution of 10 bits */
LEDC_TIMER_11_BIT, /*!< LEDC PWM duty resolution of 11 bits */
LEDC_TIMER_12_BIT, /*!< LEDC PWM duty resolution of 12 bits */
LEDC_TIMER_13_BIT, /*!< LEDC PWM duty resolution of 13 bits */
LEDC_TIMER_14_BIT, /*!< LEDC PWM duty resolution of 14 bits */
LEDC_TIMER_15_BIT, /*!< LEDC PWM duty resolution of 15 bits */
LEDC_TIMER_16_BIT, /*!< LEDC PWM duty resolution of 16 bits */
LEDC_TIMER_17_BIT, /*!< LEDC PWM duty resolution of 17 bits */
LEDC_TIMER_18_BIT, /*!< LEDC PWM duty resolution of 18 bits */
LEDC_TIMER_19_BIT, /*!< LEDC PWM duty resolution of 19 bits */
LEDC_TIMER_20_BIT, /*!< LEDC PWM duty resolution of 20 bits */
LEDC_TIMER_BIT_MAX,
} ledc_timer_bit_t;
typedef enum {
LEDC_FADE_NO_WAIT = 0, /*!< LEDC fade function will return immediately */
LEDC_FADE_WAIT_DONE, /*!< LEDC fade function will block until fading to the target duty */
LEDC_FADE_MAX,
} ledc_fade_mode_t;
/**
* @brief Configuration parameters of LEDC channel for ledc_channel_config function
*/
typedef struct {
int gpio_num; /*!< the LEDC output gpio_num, if you want to use gpio16, gpio_num = 16 */
ledc_mode_t speed_mode; /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
ledc_channel_t channel; /*!< LEDC channel (0 - 7) */
ledc_intr_type_t intr_type; /*!< configure interrupt, Fade interrupt enable or Fade interrupt disable */
ledc_timer_t timer_sel; /*!< Select the timer source of channel (0 - 3) */
uint32_t duty; /*!< LEDC channel duty, the range of duty setting is [0, (2**duty_resolution)] */
int hpoint; /*!< LEDC channel hpoint value, the max value is 0xfffff */
} ledc_channel_config_t;
/**
* @brief Configuration parameters of LEDC Timer timer for ledc_timer_config function
*/
typedef struct {
ledc_mode_t speed_mode; /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
union {
ledc_timer_bit_t duty_resolution; /*!< LEDC channel duty resolution */
ledc_timer_bit_t bit_num __attribute__((deprecated)); /*!< Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1 */
};
ledc_timer_t timer_num; /*!< The timer source of channel (0 - 3) */
uint32_t freq_hz; /*!< LEDC timer frequency (Hz) */
ledc_clk_cfg_t clk_cfg; /*!< Configure LEDC source clock.
For low speed channels and high speed channels, you can specify the source clock using LEDC_USE_REF_TICK, LEDC_USE_APB_CLK or LEDC_AUTO_CLK.
For low speed channels, you can also specify the source clock using LEDC_USE_RTC8M_CLK, in this case, all low speed channel's source clock must be RTC8M_CLK*/
} ledc_timer_config_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/mcpwm_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for MCPWM (common part)
/*
* MCPWM HAL usages:
*
* Initialization:
* 1. Fill the parameters in `mcpwm_hal_context_t`.
* 2. Call `mcpwm_hal_init` to initialize the context.
* 3. Call `mcpwm_hal_hw_init` to initialize the hardware.
*
* Basic PWM:
* 1. Update parameters for the timers, comparators and generators.
* 2. Call `mcpwm_hal_timer_update_basic` to update the timer used.
* 3. Call `mcpwm_hal_operator_update_basic` to update all the parameters of a operator.
*
* Alternatively, if only the comparator is updated (duty rate), call
* `mcpwm_hal_operator_update_comparator` to update the comparator parameters; if only the
* generator is updated (output style), call `mcpwm_hal_operator_update_generator` to update the
* generator parameters.
*
* 4. At any time, call `mcpwm_hal_timer_start` to start the timer (so that PWM output will toggle
* according to settings), or call `mcpwm_hal_timer_stop` to stop the timer (so that the PWM output
* will be kept as called).
*
* Timer settings:
* - Sync: Call `mcpwm_hal_timer_enable_sync` to enable the sync for the timer, and call
* `mcpwm_hal_timer_disable_sync` to disable it.
*
* Operator settings:
* - Carrier: Call `mcpwm_hal_operator_enable_carrier` to enable carrier for an operator, and call
* `mcpwm_hal_operator_disable_carrier` to disable it.
*
* - Deadzone: Call `mcpwm_hal_operator_update_deadzone` to update settings of deadzone for an operator.
*
* Fault handling settings:
* 1. Call `mcpwm_hal_fault_init` to initialize an fault signal to be detected.
* 2. Call `mcpwm_hal_operator_update_fault` to update the behavior of an operator when fault is
* detected.
* 3. If the operator selects oneshot mode to handle the fault event, call
* `mcpwm_hal_fault_oneshot_clear` to clear that fault event after the fault is handled properly.
* 4. Call `mcpwm_hal_fault_disable` to deinitialize the fault signal when it's no longer used.
*
* Capture:
* 1. Call `mcpwm_hal_capture_enable` to enable the capture for one capture signal.
* 2. Call `mcpwm_hal_capture_get_result` to get the last captured result.
* 3. Call `mcpwm_hal_capture_disable` to disable the capture for a signal.
*/
#pragma once
#include <esp_err.h>
#include "hal/mcpwm_ll.h"
#define MCPWM_BASE_CLK (2 * APB_CLK_FREQ) //2*APB_CLK_FREQ 160Mhz
/// Configuration of HAL that used only once.
typedef struct {
int host_id; ///< Which MCPWM peripheral to use, 0-1.
} mcpwm_hal_init_config_t;
/// Configuration of each generator (output of operator)
typedef struct {
mcpwm_duty_type_t duty_type; ///< How the generator output
int comparator; ///< for mode `MCPWM_DUTY_MODE_*`, which comparator it refers to.
} mcpwm_hal_generator_config_t;
/// Configuration of each operator
typedef struct {
mcpwm_hal_generator_config_t gen[SOC_MCPWM_GENERATOR_NUM]; ///< Configuration of the generators
float duty[SOC_MCPWM_COMPARATOR_NUM]; ///< Duty rate for each comparator, 10 means 10%.
int timer; ///< The timer this operator is using
} mcpwm_hal_operator_config_t;
/// Configuration of each timer
typedef struct {
uint32_t timer_prescale; ///< The prescale from the MCPWM main clock to the timer clock, TIMER_FREQ=(MCPWM_FREQ/(timer_prescale+1))
uint32_t freq; ///< Frequency desired, will be updated to actual value after the `mcpwm_hal_timer_update_freq` is called.
mcpwm_counter_type_t count_mode; ///< Counting mode
} mcpwm_hal_timer_config_t;
typedef struct {
mcpwm_dev_t *dev; ///< Beginning address of the MCPWM peripheral registers. Call `mcpwm_hal_init` to initialize it.
uint32_t prescale; ///< Prescale from the 160M clock to MCPWM main clock.
mcpwm_hal_timer_config_t timer[SOC_MCPWM_TIMER_NUM]; ///< Configuration of the timers
mcpwm_hal_operator_config_t op[SOC_MCPWM_OP_NUM]; ///< Configuration of the operators
} mcpwm_hal_context_t;
/// Configuration of the carrier
typedef struct {
bool inverted; ///< Whether to invert the output
uint8_t duty; ///< Duty of the carrier, 0-7. Duty rate = duty/8.
uint8_t oneshot_pulse_width; ///< oneshot pulse width, in carrier periods. 0 to disable. 0-15.
uint32_t period; ///< Prescale from the MCPWM main clock to the carrier clock. CARRIER_FREQ=(MCPWM_FREQ/(period+1)/8.)
} mcpwm_hal_carrier_conf_t;
/// Configuration of the deadzone
typedef struct {
mcpwm_deadtime_type_t mode; ///< Deadzone mode, `MCPWM_DEADTIME_BYPASS` to disable.
uint32_t fed; ///< Delay on falling edge. By MCPWM main clock.
uint32_t red; ///< Delay on rising edge. By MCPWM main clock.
} mcpwm_hal_deadzone_conf_t;
/// Configuration of the fault handling for each operator
typedef struct {
uint32_t cbc_enabled_mask; ///< Whether the cycle-by-cycle fault handling is enabled on each fault signal. BIT(n) stands for signal n.
uint32_t ost_enabled_mask; ///< Whether the oneshot fault handling is enabled on each on each fault signal. BIT(n) stands for signal n.
mcpwm_output_action_t action_on_fault[SOC_MCPWM_GENERATOR_NUM]; ///< Action to perform on each generator when any one of the fault signal triggers.
} mcpwm_hal_fault_conf_t;
/// Configuration of the synchronization of each clock
typedef struct {
mcpwm_sync_signal_t sync_sig; ///< Sync signal to use
uint32_t reload_permillage; ///< Reload permillage when the sync is triggered. 100 means the timer will be reload to (period * 100)/1000=10% period value.
} mcpwm_hal_sync_config_t;
/// Configuration of the capture feature on each capture signal
typedef struct {
mcpwm_capture_on_edge_t cap_edge; ///< Whether the edges is captured, bitwise.
uint32_t prescale; ///< Prescale of the input signal.
} mcpwm_hal_capture_config_t;
/**
* @brief Initialize the internal state of the HAL. Call after settings are set and before other functions are called.
*
* @note Since There are several individual parts (timers + operators, captures), this funciton is
* allowed to called several times.
*
* @param hal Context of the HAL layer.
* @param init_config Configuration for the HAL to be used only once.
*/
void mcpwm_hal_init(mcpwm_hal_context_t *hal, const mcpwm_hal_init_config_t *init_config);
/**
* @brief Initialize the hardware, call after `mcpwm_hal_init` and before other functions.
*
* @param hal Context of the HAL layer.
*/
void mcpwm_hal_hw_init(mcpwm_hal_context_t *hal);
/**
* @brief Start a timer
*
* @param hal Context of the HAL layer.
* @param timer Timer to start, 0-2.
*/
void mcpwm_hal_timer_start(mcpwm_hal_context_t *hal, int timer);
/**
* @brief Stop a timer.
*
* @param hal Context of the HAL layer.
* @param timer Timer to stop, 0-2.
*/
void mcpwm_hal_timer_stop(mcpwm_hal_context_t *hal, int timer);
/**
* @brief Update the basic parameters of a timer.
*
* @note This will influence the duty rate and count mode of each operator relies on this timer.
* Call `mcpwm_hal_operator_update_basic` for each of the operator that relies on this timer after
* to update the duty rate and generator output.
*
* @param hal Context of the HAL layer.
* @param timer Timer to update, 0-2.
*/
void mcpwm_hal_timer_update_basic(mcpwm_hal_context_t *hal, int timer);
/**
* @brief Start the synchronization for a timer.
*
* @param hal Context of the HAL layer.
* @param timer Timer to enable, 0-2.
* @param sync_conf Configuration of the sync operation.
*/
void mcpwm_hal_timer_enable_sync(mcpwm_hal_context_t *hal, int timer, const mcpwm_hal_sync_config_t *sync_conf);
/**
* @brief Stop the synchronization for a timer.
*
* @param hal Context of the HAL layer.
* @param timer Timer to disable sync, 0-2.
*/
void mcpwm_hal_timer_disable_sync(mcpwm_hal_context_t *hal, int timer);
/**
* @brief Update the basic settings (duty, output mode) for an operator.
*
* Will call `mcpwm_hal_operator_update_comparator` and `mcpwm_hal_operator_update_generator`
* recursively to update each of their duty and output mode.
*
* @param hal Context of the HAL layer.
* @param op Operator to update, 0-2.
*/
void mcpwm_hal_operator_update_basic(mcpwm_hal_context_t *hal, int op);
/**
* @brief Update a comparator (duty) for an operator.
*
* @param hal Context of the HAL layer.
* @param op Operator to update, 0-2.
* @param cmp Comparator to update, 0-1.
*/
void mcpwm_hal_operator_update_comparator(mcpwm_hal_context_t *hal, int op, int cmp);
/**
* @brief Update a generator (output mode) for an operator.
*
* @param hal Context of the HAL layer.
* @param op Operator to update, 0-2.
* @param cmp Comparator to update, 0-1.
*/
void mcpwm_hal_operator_update_generator(mcpwm_hal_context_t *hal, int op, int gen_num);
/**
* @brief Enable the carrier for an operator.
*
* @param hal Context of the HAL layer.
* @param op Operator to enable carrier, 0-2.
* @param carrier_conf Configuration of the carrier.
*/
void mcpwm_hal_operator_enable_carrier(mcpwm_hal_context_t *hal, int op, const mcpwm_hal_carrier_conf_t *carrier_conf);
/**
* @brief Disable the carrier for an operator.
*
* @param hal Context of the HAL layer.
* @param op Operator to disable carrier, 0-2.
*/
void mcpwm_hal_operator_disable_carrier(mcpwm_hal_context_t *hal, int op);
/**
* @brief Update the deadzone for an operator.
*
* @param hal Context of the HAL layer.
* @param op Operator to update the deadzone, 0-2.
* @param deadzone Configuration of the deadzone. Set member `mode` to `MCPWM_DEADTIME_BYPASS` will bypass the deadzone.
*/
void mcpwm_hal_operator_update_deadzone(mcpwm_hal_context_t *hal, int op, const mcpwm_hal_deadzone_conf_t *deadzone);
/**
* @brief Enable one of the fault signal.
*
* @param hal Context of the HAL layer.
* @param fault_sig The signal to enable, 0-2.
* @param level The active level for the fault signal, true for high and false for low.
*/
void mcpwm_hal_fault_init(mcpwm_hal_context_t *hal, int fault_sig, bool level);
/**
* @brief Configure how the operator behave to the fault signals.
*
* Call after the fault signal is enabled by `mcpwm_hal_fault_init`.
*
* @param hal Context of the HAL layer.
* @param op Operator to configure, 0-2.
* @param fault_conf Configuration of the behavior of the operator when fault. Clear member `cbc_enabled_mask` and `ost_enabled_mask` will disable the fault detection of this operator.
*/
void mcpwm_hal_operator_update_fault(mcpwm_hal_context_t *hal, int op, const mcpwm_hal_fault_conf_t *fault_conf);
/**
* @brief Clear the oneshot fault status for an operator.
*
* @param hal Context of the HAL layer.
* @param op The operator to clear oneshot fault status, 0-2.
*/
void mcpwm_hal_fault_oneshot_clear(mcpwm_hal_context_t *hal, int op);
/**
* @brief Disable one of the fault signal.
*
* @param hal Context of the HAL layer.
* @param fault_sig The fault signal to disable, 0-2.
*/
void mcpwm_hal_fault_disable(mcpwm_hal_context_t *hal, int fault_sig);
/**
* @brief Enable one of the capture signal.
*
* @param hal Context of the HAL layer.
* @param cap_sig Capture signal to enable, 0-2.
* @param conf Configuration on how to capture the signal.
*/
void mcpwm_hal_capture_enable(mcpwm_hal_context_t *hal, int cap_sig, const mcpwm_hal_capture_config_t *conf);
/**
* @brief Get the capture result.
*
* @note The output value will always be updated with the register value, no matter event triggered or not.
*
* @param hal Context of the HAL layer.
* @param cap_sig Signal to get capture result, 0-2.
* @param out_count Output of the captured counter.
* @param out_edge Output of the captured edge.
* @return
* - ESP_OK: if a signal is captured
* - ESP_ERR_NOT_FOUND: if no capture event happened.
*/
esp_err_t mcpwm_hal_capture_get_result(mcpwm_hal_context_t *hal, int cap_sig, uint32_t *out_count,
mcpwm_capture_on_edge_t *out_edge);
/**
* @brief Disable one of the capture signal.
*
* @param hal Context of the HAL layer.
* @param cap_sig The signal to capture, 0-2.
*/
void mcpwm_hal_capture_disable(mcpwm_hal_context_t *hal, int cap_sig);
tools/sdk/esp32s2/include/soc/include/hal/mcpwm_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/// Interrupts for MCPWM
typedef enum {
MCPWM_LL_INTR_CAP0 = BIT(27), ///< Capture 0 happened
MCPWM_LL_INTR_CAP1 = BIT(28), ///< Capture 1 happened
MCPWM_LL_INTR_CAP2 = BIT(29), ///< Capture 2 happened
} mcpwm_intr_t;
/**
* @brief Select type of MCPWM counter
*/
typedef enum {
MCPWM_UP_COUNTER = 1, /*!<For asymmetric MCPWM*/
MCPWM_DOWN_COUNTER, /*!<For asymmetric MCPWM*/
MCPWM_UP_DOWN_COUNTER, /*!<For symmetric MCPWM, frequency is half of MCPWM frequency set*/
MCPWM_COUNTER_MAX, /*!<Maximum counter mode*/
} mcpwm_counter_type_t;
/**
* @brief Select type of MCPWM duty cycle mode
*/
typedef enum {
MCPWM_DUTY_MODE_0 = 0, /*!<Active high duty, i.e. duty cycle proportional to high time for asymmetric MCPWM*/
MCPWM_DUTY_MODE_1, /*!<Active low duty, i.e. duty cycle proportional to low time for asymmetric MCPWM, out of phase(inverted) MCPWM*/
MCPWM_HAL_GENERATOR_MODE_FORCE_LOW,
MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH,
MCPWM_DUTY_MODE_MAX, /*!<Num of duty cycle modes*/
} mcpwm_duty_type_t;
/**
* @brief MCPWM select action to be taken on the output when event happens
*/
typedef enum {
MCPWM_ACTION_NO_CHANGE = 0, /*!<No change in the output*/
MCPWM_ACTION_FORCE_LOW, /*!<Make output low*/
MCPWM_ACTION_FORCE_HIGH, /*!<Make output high*/
MCPWM_ACTION_TOGGLE, /*!<Make output toggle*/
} mcpwm_output_action_t;
/**
* @brief MCPWM deadtime types, used to generate deadtime, RED refers to rising edge delay and FED refers to falling edge delay
*/
typedef enum {
MCPWM_DEADTIME_BYPASS = 0, /*!<Bypass the deadtime*/
MCPWM_BYPASS_RED, /*!<MCPWMXA = no change, MCPWMXB = falling edge delay*/
MCPWM_BYPASS_FED, /*!<MCPWMXA = rising edge delay, MCPWMXB = no change*/
MCPWM_ACTIVE_HIGH_MODE, /*!<MCPWMXA = rising edge delay, MCPWMXB = falling edge delay*/
MCPWM_ACTIVE_LOW_MODE, /*!<MCPWMXA = compliment of rising edge delay, MCPWMXB = compliment of falling edge delay*/
MCPWM_ACTIVE_HIGH_COMPLIMENT_MODE, /*!<MCPWMXA = rising edge delay, MCPWMXB = compliment of falling edge delay*/
MCPWM_ACTIVE_LOW_COMPLIMENT_MODE, /*!<MCPWMXA = compliment of rising edge delay, MCPWMXB = falling edge delay*/
MCPWM_ACTIVE_RED_FED_FROM_PWMXA, /*!<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXA*/
MCPWM_ACTIVE_RED_FED_FROM_PWMXB, /*!<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXB*/
MCPWM_DEADTIME_TYPE_MAX,
} mcpwm_deadtime_type_t;
/**
* @brief MCPWM select sync signal input
*/
typedef enum {
MCPWM_SELECT_SYNC0 = 4, /*!<Select SYNC0 as input*/
MCPWM_SELECT_SYNC1, /*!<Select SYNC1 as input*/
MCPWM_SELECT_SYNC2, /*!<Select SYNC2 as input*/
} mcpwm_sync_signal_t;
/**
* @brief MCPWM select capture starts from which edge
*/
typedef enum {
MCPWM_NEG_EDGE = BIT(0), /*!<Capture the negative edge*/
MCPWM_POS_EDGE = BIT(1), /*!<Capture the positive edge*/
} mcpwm_capture_on_edge_t;
tools/sdk/esp32s2/include/soc/include/hal/mpu_hal.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include "esp_err.h"
#include "hal/mpu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Specify the type of access allowed on a memory region.
*
* @param id index to the region table; on targets not SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED,
* the region divisions is predefined in hardware which is likely reflected in LL implementation.
* @param access type of access allowed
*/
void mpu_hal_set_region_access(int id, mpu_access_t access);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/mpu_types.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#if SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
typedef void** mpu_region_table_t;
#endif
typedef enum {
MPU_REGION_ILLEGAL,
#if SOC_MPU_REGION_RO_SUPPORTED
MPU_REGION_RO, // read-only
#endif
#if SOC_MPU_REGION_WO_SUPPORTED
MPU_REGION_WO, // write-only
#endif
MPU_REGION_RW, // read-write
MPU_REGION_X, // executable
MPU_REGION_RWX // read-write-executable
} mpu_access_t;
tools/sdk/esp32s2/include/soc/include/hal/pcnt_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for PCNT.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#include <stdio.h>
#include "soc/pcnt_periph.h"
#include "hal/pcnt_types.h"
#include "hal/pcnt_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
pcnt_dev_t *dev;
} pcnt_hal_context_t;
/**
* @brief Set PCNT counter mode
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
* @param channel PCNT channel number
* @param pos_mode Counter mode when detecting positive edge
* @param neg_mode Counter mode when detecting negative edge
* @param hctrl_mode Counter mode when control signal is high level
* @param lctrl_mode Counter mode when control signal is low level
*/
#define pcnt_hal_set_mode(hal, unit, channel, pos_mode, neg_mode, hctrl_mode, lctrl_mode) pcnt_ll_set_mode((hal)->dev, unit, channel, pos_mode, neg_mode, hctrl_mode, lctrl_mode)
/**
* @brief Get pulse counter value
*
* @param hal Context of the HAL layer
* @param unit Pulse Counter unit number
* @param count Pointer to accept counter value
*/
#define pcnt_hal_get_counter_value(hal, unit, count) pcnt_ll_get_counter_value((hal)->dev, unit, count)
/**
* @brief Pause PCNT counter of PCNT unit
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
*/
#define pcnt_hal_counter_pause(hal, unit) pcnt_ll_counter_pause((hal)->dev, unit)
/**
* @brief Resume counting for PCNT counter
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number, select from unit_t
*/
#define pcnt_hal_counter_resume(hal, unit) pcnt_ll_counter_resume((hal)->dev, unit)
/**
* @brief Clear and reset PCNT counter value to zero
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number, select from unit_t
*/
#define pcnt_hal_counter_clear(hal, unit) pcnt_ll_counter_clear((hal)->dev, unit)
/**
* @brief Enable PCNT interrupt for PCNT unit
* @note
* Each Pulse counter unit has five watch point events that share the same interrupt.
* Configure events with pcnt_event_enable() and pcnt_event_disable()
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
*/
#define pcnt_hal_intr_enable(hal, unit) pcnt_ll_intr_enable((hal)->dev, unit)
/**
* @brief Disable PCNT interrupt for PCNT unit
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
*/
#define pcnt_hal_intr_disable(hal, unit) pcnt_ll_intr_disable((hal)->dev, unit)
/**
* @brief Get PCNT interrupt status
*
* @param hal Context of the HAL layer
* @param mask The interrupt status mask to be cleared. Pointer to accept value interrupt status mask.
*/
#define pcnt_hal_get_intr_status(hal, mask) pcnt_ll_get_intr_status((hal)->dev, mask)
/**
* @brief Clear PCNT interrupt status
*
* @param hal Context of the HAL layer
* @param mask The interrupt status mask to be cleared.
*/
#define pcnt_hal_clear_intr_status(hal, mask) pcnt_ll_clear_intr_status((hal)->dev, mask)
/**
* @brief Enable PCNT event of PCNT unit
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
* @param evt_type Watch point event type.
* All enabled events share the same interrupt (one interrupt per pulse counter unit).
*/
#define pcnt_hal_event_enable(hal, unit, evt_type) pcnt_ll_event_enable((hal)->dev, unit, evt_type)
/**
* @brief Disable PCNT event of PCNT unit
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
* @param evt_type Watch point event type.
* All enabled events share the same interrupt (one interrupt per pulse counter unit).
*/
#define pcnt_hal_event_disable(hal, unit, evt_type) pcnt_ll_event_disable((hal)->dev, unit, evt_type)
/**
* @brief Set PCNT event value of PCNT unit
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
* @param evt_type Watch point event type.
* All enabled events share the same interrupt (one interrupt per pulse counter unit).
*
* @param value Counter value for PCNT event
*/
#define pcnt_hal_set_event_value(hal, unit, evt_type, value) pcnt_ll_set_event_value((hal)->dev, unit, evt_type, value)
/**
* @brief Get PCNT event value of PCNT unit
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
* @param evt_type Watch point event type.
* All enabled events share the same interrupt (one interrupt per pulse counter unit).
* @param value Pointer to accept counter value for PCNT event
*/
#define pcnt_hal_get_event_value(hal, unit, evt_type, value) pcnt_ll_get_event_value((hal)->dev, unit, evt_type, value)
/**
* @brief Set PCNT filter value
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
* @param filter_val PCNT signal filter value, counter in APB_CLK cycles.
* Any pulses lasting shorter than this will be ignored when the filter is enabled.
* @note
* filter_val is a 10-bit value, so the maximum filter_val should be limited to 1023.
*/
#define pcnt_hal_set_filter_value(hal, unit, filter_val) pcnt_ll_set_filter_value((hal)->dev, unit, filter_val)
/**
* @brief Get PCNT filter value
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
* @param filter_val Pointer to accept PCNT filter value.
*/
#define pcnt_hal_get_filter_value(hal, unit, filter_val) pcnt_ll_get_filter_value((hal)->dev, unit, filter_val)
/**
* @brief Enable PCNT input filter
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
*/
#define pcnt_hal_filter_enable(hal, unit) pcnt_ll_filter_enable((hal)->dev, unit)
/**
* @brief Disable PCNT input filter
*
* @param hal Context of the HAL layer
* @param unit PCNT unit number
*/
#define pcnt_hal_filter_disable(hal, unit) pcnt_ll_filter_disable((hal)->dev, unit)
/**
* @brief Init the PCNT hal and set the PCNT to the default configuration. This function should be called first before other hal layer function is called
*
* @param hal Context of the HAL layer
* @param pcnt_num The uart port number, the max port number is (PCNT_NUM_MAX -1)
*/
void pcnt_hal_init(pcnt_hal_context_t *hal, int pcnt_num);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/pcnt_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define PCNT_PIN_NOT_USED (-1) /*!< When selected for a pin, this pin will not be used */
/**
* @brief PCNT port number, the max port number is (PCNT_PORT_MAX - 1).
*/
typedef enum {
PCNT_PORT_0 = 0, /*!< PCNT port 0 */
PCNT_PORT_MAX, /*!< PCNT port max */
} pcnt_port_t;
/**
* @brief Selection of all available PCNT units
*/
typedef enum {
PCNT_UNIT_0 = 0, /*!< PCNT unit 0 */
PCNT_UNIT_1 = 1, /*!< PCNT unit 1 */
PCNT_UNIT_2 = 2, /*!< PCNT unit 2 */
PCNT_UNIT_3 = 3, /*!< PCNT unit 3 */
#if SOC_PCNT_UNIT_NUM > 4
PCNT_UNIT_4 = 4, /*!< PCNT unit 4 */
PCNT_UNIT_5 = 5, /*!< PCNT unit 5 */
PCNT_UNIT_6 = 6, /*!< PCNT unit 6 */
PCNT_UNIT_7 = 7, /*!< PCNT unit 7 */
#endif
PCNT_UNIT_MAX,
} pcnt_unit_t;
/**
* @brief Selection of available modes that determine the counter's action depending on the state of the control signal's input GPIO
* @note Configuration covers two actions, one for high, and one for low level on the control input
*/
typedef enum {
PCNT_MODE_KEEP = 0, /*!< Control mode: won't change counter mode*/
PCNT_MODE_REVERSE = 1, /*!< Control mode: invert counter mode(increase -> decrease, decrease -> increase) */
PCNT_MODE_DISABLE = 2, /*!< Control mode: Inhibit counter(counter value will not change in this condition) */
PCNT_MODE_MAX
} pcnt_ctrl_mode_t;
/**
* @brief Selection of available modes that determine the counter's action on the edge of the pulse signal's input GPIO
* @note Configuration covers two actions, one for positive, and one for negative edge on the pulse input
*/
typedef enum {
PCNT_COUNT_DIS = 0, /*!< Counter mode: Inhibit counter(counter value will not change in this condition) */
PCNT_COUNT_INC = 1, /*!< Counter mode: Increase counter value */
PCNT_COUNT_DEC = 2, /*!< Counter mode: Decrease counter value */
PCNT_COUNT_MAX
} pcnt_count_mode_t;
/**
* @brief Selection of channels available for a single PCNT unit
*/
typedef enum {
PCNT_CHANNEL_0 = 0x00, /*!< PCNT channel 0 */
PCNT_CHANNEL_1 = 0x01, /*!< PCNT channel 1 */
PCNT_CHANNEL_MAX,
} pcnt_channel_t;
/**
* @brief Selection of counter's events the may trigger an interrupt
*/
typedef enum {
PCNT_EVT_THRES_1 = BIT(2), /*!< PCNT watch point event: threshold1 value event */
PCNT_EVT_THRES_0 = BIT(3), /*!< PCNT watch point event: threshold0 value event */
PCNT_EVT_L_LIM = BIT(4), /*!< PCNT watch point event: Minimum counter value */
PCNT_EVT_H_LIM = BIT(5), /*!< PCNT watch point event: Maximum counter value */
PCNT_EVT_ZERO = BIT(6), /*!< PCNT watch point event: counter value zero event */
PCNT_EVT_MAX
} pcnt_evt_type_t;
/**
* @brief Pulse Counter configuration for a single channel
*/
typedef struct {
int pulse_gpio_num; /*!< Pulse input GPIO number, if you want to use GPIO16, enter pulse_gpio_num = 16, a negative value will be ignored */
int ctrl_gpio_num; /*!< Control signal input GPIO number, a negative value will be ignored */
pcnt_ctrl_mode_t lctrl_mode; /*!< PCNT low control mode */
pcnt_ctrl_mode_t hctrl_mode; /*!< PCNT high control mode */
pcnt_count_mode_t pos_mode; /*!< PCNT positive edge count mode */
pcnt_count_mode_t neg_mode; /*!< PCNT negative edge count mode */
int16_t counter_h_lim; /*!< Maximum counter value */
int16_t counter_l_lim; /*!< Minimum counter value */
pcnt_unit_t unit; /*!< PCNT unit number */
pcnt_channel_t channel; /*!< the PCNT channel */
} pcnt_config_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/rmt_hal.h
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/rmt_struct.h"
#include "soc/rmt_caps.h"
/**
* @brief HAL context type of RMT driver
*
*/
typedef struct {
rmt_dev_t *regs; /*!< RMT Register base address */
rmt_mem_t *mem; /*!< RMT Memory base address */
} rmt_hal_context_t;
#define RMT_MEM_OWNER_SW (0) /*!< RMT Memory ownership belongs to software side */
#define RMT_MEM_OWNER_HW (1) /*!< RMT Memory ownership belongs to hardware side */
/**
* @brief Initialize the RMT HAL driver
*
* @param hal: RMT HAL context
*/
void rmt_hal_init(rmt_hal_context_t *hal);
/**
* @brief Reset RMT HAL driver
*
* @param hal: RMT HAL context
*/
void rmt_hal_reset(rmt_hal_context_t *hal);
/**
* @brief Reset RMT Channel specific HAL driver
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
*/
void rmt_hal_channel_reset(rmt_hal_context_t *hal, uint32_t channel);
/**
* @brief Set counter clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT internal channel (counter clock will divide from it)
* @param counter_clk_hz: target counter clock
*/
void rmt_hal_set_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz);
/**
* @brief Get counter clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT internal channel (counter clock will divide from it)
* @return counter clock in Hz
*/
uint32_t rmt_hal_get_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz);
/**
* @brief Set carrier clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT carrier generation (carrier clock will divide from it)
* @param carrier_clk_hz: target carrier clock
* @param carrier_clk_duty: duty ratio of carrier clock
*/
void rmt_hal_set_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t carrier_clk_hz, float carrier_clk_duty);
/**
* @brief Get carrier clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT carrier generation
* @param carrier_clk_hz: target carrier clock
* @param carrier_clk_duty: duty ratio of carrier clock
*/
void rmt_hal_get_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t *carrier_clk_hz, float *carrier_clk_duty);
/**
* @brief Set filter threshold for RMT Receive channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT receive filter
* @param thres_us: threshold of RMT receive filter, in us
*/
void rmt_hal_set_rx_filter_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us);
/**
* @brief Set idle threshold for RMT Receive channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT receive channel
* @param thres_us: IDLE threshold for RMT receive channel
*/
void rmt_hal_set_rx_idle_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us);
/**
* @brief Receive a frame from RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param buf: buffer to store received RMT frame
* @return number of items that get received
*/
uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t *buf);
/**
* @brief Transmit a from by RMT
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param src: RMT items to transmit
* @param length: length of RMT items to transmit
* @param offset: offset of RMT internal memory to store the items
*/
void rmt_hal_transmit(rmt_hal_context_t *hal, uint32_t channel, const rmt_item32_t *src, uint32_t length, uint32_t offset);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/rmt_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/rmt_caps.h"
/**
* @brief RMT channel ID
*
*/
typedef enum {
RMT_CHANNEL_0, /*!< RMT channel number 0 */
RMT_CHANNEL_1, /*!< RMT channel number 1 */
RMT_CHANNEL_2, /*!< RMT channel number 2 */
RMT_CHANNEL_3, /*!< RMT channel number 3 */
#if SOC_RMT_CHANNELS_NUM > 4
RMT_CHANNEL_4, /*!< RMT channel number 4 */
RMT_CHANNEL_5, /*!< RMT channel number 5 */
RMT_CHANNEL_6, /*!< RMT channel number 6 */
RMT_CHANNEL_7, /*!< RMT channel number 7 */
#endif
RMT_CHANNEL_MAX /*!< Number of RMT channels */
} rmt_channel_t;
/**
* @brief RMT Internal Memory Owner
*
*/
typedef enum {
RMT_MEM_OWNER_TX, /*!< RMT RX mode, RMT transmitter owns the memory block*/
RMT_MEM_OWNER_RX, /*!< RMT RX mode, RMT receiver owns the memory block*/
RMT_MEM_OWNER_MAX,
} rmt_mem_owner_t;
/**
* @brief Clock Source of RMT Channel
*
*/
typedef enum {
RMT_BASECLK_REF, /*!< RMT source clock is REF_TICK, 1MHz by default */
RMT_BASECLK_APB, /*!< RMT source clock is APB CLK, 80Mhz by default */
RMT_BASECLK_MAX,
} rmt_source_clk_t;
/**
* @brief RMT Data Mode
*
* @note We highly recommended to use MEM mode not FIFO mode since there will be some gotcha in FIFO mode.
*
*/
typedef enum {
RMT_DATA_MODE_FIFO, /*<! RMT memory access in FIFO mode */
RMT_DATA_MODE_MEM, /*<! RMT memory access in memory mode */
RMT_DATA_MODE_MAX,
} rmt_data_mode_t;
/**
* @brief RMT Channel Working Mode (TX or RX)
*
*/
typedef enum {
RMT_MODE_TX, /*!< RMT TX mode */
RMT_MODE_RX, /*!< RMT RX mode */
RMT_MODE_MAX
} rmt_mode_t;
/**
* @brief RMT Idle Level
*
*/
typedef enum {
RMT_IDLE_LEVEL_LOW, /*!< RMT TX idle level: low Level */
RMT_IDLE_LEVEL_HIGH, /*!< RMT TX idle level: high Level */
RMT_IDLE_LEVEL_MAX,
} rmt_idle_level_t;
/**
* @brief RMT Carrier Level
*
*/
typedef enum {
RMT_CARRIER_LEVEL_LOW, /*!< RMT carrier wave is modulated for low Level output */
RMT_CARRIER_LEVEL_HIGH, /*!< RMT carrier wave is modulated for high Level output */
RMT_CARRIER_LEVEL_MAX
} rmt_carrier_level_t;
/**
* @brief RMT Channel Status
*
*/
typedef enum {
RMT_CHANNEL_UNINIT, /*!< RMT channel uninitialized */
RMT_CHANNEL_IDLE, /*!< RMT channel status idle */
RMT_CHANNEL_BUSY, /*!< RMT channel status busy */
} rmt_channel_status_t;
/**
* @brief Data struct of RMT channel status
*/
typedef struct {
rmt_channel_status_t status[RMT_CHANNEL_MAX]; /*!< Store the current status of each channel */
} rmt_channel_status_result_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/rtc_io_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for RTC IO master (common part)
#pragma once
#include "hal/rtc_io_ll.h"
#include <esp_err.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* Select the rtcio function.
*
* @note The RTC function must be selected before the pad analog function is enabled.
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
* @param func Select pin function.
*/
#define rtcio_hal_function_select(rtcio_num, func) rtcio_ll_function_select(rtcio_num, func)
/**
* Enable rtcio output.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_output_enable(rtcio_num) rtcio_ll_output_enable(rtcio_num)
/**
* Disable rtcio output.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_output_disable(rtcio_num) rtcio_ll_output_disable(rtcio_num)
/**
* Set RTCIO output level.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
* @param level 0: output low; ~0: output high.
*/
#define rtcio_hal_set_level(rtcio_num, level) rtcio_ll_set_level(rtcio_num, level)
/**
* Enable rtcio input.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_input_enable(rtcio_num) rtcio_ll_input_enable(rtcio_num)
/**
* Disable rtcio input.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_input_disable(rtcio_num) rtcio_ll_input_disable(rtcio_num)
/**
* Get RTCIO input level.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
* @return 0: input low; ~0: input high.
*/
#define rtcio_hal_get_level(rtcio_num) rtcio_ll_get_level(rtcio_num)
/**
* @brief Set RTC GPIO pad drive capability.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
* @param strength Drive capability of the pad. Range: 0 ~ 3.
*/
#define rtcio_hal_set_drive_capability(rtcio_num, strength) rtcio_ll_set_drive_capability(rtcio_num, strength)
/**
* @brief Get RTC GPIO pad drive capability.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
* @return Drive capability of the pad. Range: 0 ~ 3.
*/
#define rtcio_hal_get_drive_capability(rtcio_num) rtcio_ll_get_drive_capability(rtcio_num)
/**
* Set RTCIO output level.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
* @param level 0: output low; ~0: output high.
*/
#define rtcio_hal_set_level(rtcio_num, level) rtcio_ll_set_level(rtcio_num, level)
/**
* Get RTCIO input level.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
* @return 0: input low; ~0: input high.
*/
#define rtcio_hal_get_level(rtcio_num) rtcio_ll_get_level(rtcio_num)
/**
* Set RTC IO direction.
*
* Configure RTC IO direction, such as output only, input only,
* output and input.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
* @param mode IO direction.
*/
void rtcio_hal_set_direction(int rtcio_num, rtc_gpio_mode_t mode);
/**
* Set RTC IO direction in deep sleep or disable sleep status.
*
* NOTE: ESP32 support INPUT_ONLY mode.
* ESP32S2 support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
* @param mode IO direction.
*/
void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
/**
* RTC GPIO pullup enable.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_pullup_enable(rtcio_num) rtcio_ll_pullup_enable(rtcio_num)
/**
* RTC GPIO pullup disable.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_pullup_disable(rtcio_num) rtcio_ll_pullup_disable(rtcio_num)
/**
* RTC GPIO pulldown enable.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_pulldown_enable(rtcio_num) rtcio_ll_pulldown_enable(rtcio_num)
/**
* RTC GPIO pulldown disable.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_pulldown_disable(rtcio_num) rtcio_ll_pulldown_disable(rtcio_num)
/**
* Enable force hold function for RTC IO pad.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
* This function is useful when going into light or deep sleep mode to prevent
* the pin configuration from changing.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_hold_enable(rtcio_num) rtcio_ll_force_hold_enable(rtcio_num)
/**
* Disable hold function on an RTC IO pad
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_hold_disable(rtcio_num) rtcio_ll_force_hold_disable(rtcio_num)
/**
* Enable force hold function for RTC IO pads.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
* This function is useful when going into light or deep sleep mode to prevent
* the pin configuration from changing.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_hold_all() rtcio_ll_force_hold_all()
/**
* Disable hold function on an RTC IO pads.
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_unhold_all() rtcio_ll_force_unhold_all()
/**
* Enable wakeup function and set wakeup type from light sleep status for rtcio.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
* @param type Wakeup on high level or low level.
*/
#define rtcio_hal_wakeup_enable(rtcio_num, type) rtcio_ll_wakeup_enable(rtcio_num, type)
/**
* Disable wakeup function from light sleep status for rtcio.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
#define rtcio_hal_wakeup_disable(rtcio_num) rtcio_ll_wakeup_disable(rtcio_num)
/**
* Helper function to disconnect internal circuits from an RTC IO
* This function disables input, output, pullup, pulldown, and enables
* hold feature for an RTC IO.
* Use this function if an RTC IO needs to be disconnected from internal
* circuits in deep sleep, to minimize leakage current.
*
* In particular, for ESP32-WROVER module, call
* rtc_gpio_isolate(GPIO_NUM_12) before entering deep sleep, to reduce
* deep sleep current.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
*/
void rtcio_hal_isolate(int rtc_num);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/rtc_io_types.h
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/** RTCIO output/input mode type. */
typedef enum {
RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad input */
RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad output */
RTC_GPIO_MODE_INPUT_OUTPUT, /*!< Pad input + output */
RTC_GPIO_MODE_DISABLED, /*!< Pad (output + input) disable */
RTC_GPIO_MODE_OUTPUT_OD, /*!< Pad open-drain output */
RTC_GPIO_MODE_INPUT_OUTPUT_OD, /*!< Pad input + open-drain output */
} rtc_gpio_mode_t;
tools/sdk/esp32s2/include/soc/include/hal/sdio_slave_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for SDIO slave (common part)
// SDIO slave HAL usages:
/*
Architecture:
The whole SDIO slave peripheral consists of three parts: the registers (including the interrupt
control and shared registers), a send FIFO, and a receive FIFO. The document
``esp_slave_protocol.rst`` describes the functionality of the peripheral in detail. An SDIO host
will only ever access one of the three parts at any one time, thus the hardware functionality of
the SDIO slave peripheral are completely independent. Likewise, this HAL is organized in such a
fashion as to correspond to the three independent parts.
The shared registers are quite simple: the slave can directly access them from the internal data
bus, while the host can access them by CMD52/53 with the correct address. As for the interrupts:
when an SDIO host interrupts the SDIO slave peripheral (by writing a command), the corresponding
bit in the interrupt register will be set; when the SDIO slave peripheral needs to interrupt the
host, it write some register to cause the host interrupt bit being set, and the slave hardware
will output the interrupt signal on the DAT1 line.
For the FIFOs, the peripheral provides counters as registers so that the host can always know whether the slave
is ready to send/receive data. The HAL resets the counters during initialization, and the host should somehow
inform the slave to reset the counters again if it should reboot (or lose the counter value for some reasons).
Then the host can read/write the FIFOs by CMD53 commands according to the counters.
In order to avoid copying data to/from the FIFOs or memory buffers each time, the HAL layer
contains a descriptor queue (implemented as linked-list) that allows descriptors of memory
buffers to be queued for transmission/reception. Once a buffer is queued, the HAL takes ownership
of the buffer until some "finish" functions successfully return, indicating the
transmission/reception of that buffer is complete. The ISR is invoked multiple times to iterate
through the queued descriptors, and also to signal to the upper layer if a buffer has been
freed.
The HAL is used as below:
- Receiving part:
1. Call `sdio_slave_hal_recv_start` to start the receiving DMA.
If there are already buffers loaded, the receiving will start from those buffers first.
2. Call `sdio_slave_hal_recv_init_desc` with a `sdio_slave_hal_recv_desc_t` and the buffer address to
associate the descriptor with the buffer.
The HAL initialize this descriptors with the determined length and maybe some extra data.
3. Call `sdio_slave_hal_load_buf` with the initialized descriptor of the buffer to load a
receiving buffer to the HAL.
When the DMA is started, the descriptors is loaded onto the DMA linked-list, and the
counter of receiving buffers is increased so that the host will know this by the
receiving interrupt. The hardware will automatically go through the linked list and write
data into the buffers loaded on the list.
4. (Optional, mandatory only when interrupt enabled) Call `sdio_slave_hal_recv_done` to check
and clear the receiving interrupt bits.
5. Call `sdio_slave_hal_recv_has_next_item` to check whether there are finished buffers.
6. Call `sdio_slave_hal_recv_unload_desc` for the same times as
`sdio_slave_hal_recv_has_next_item` successfully returns.
7. (Optional) Call `sdio_slave_hal_recv_reset_counter` to reset the counter to current loaded
but not used buffers if you want to reset the counter only. This is available only when
the DMA is stopped.
8. (Optional) Call `sdio_slave_hal_recv_flush_one_buffer` (recursively) if you want to
discard data of one (or more) buffers and load them again. This is available only when
the DMA is stopped.
9. (Optional when deinitialization) Call `sdio_slave_hal_recv_unload_desc` recursively to get
all the buffers loaded to the HAL, no matter they are used or not. Don't do this when the
DMA is not stopped.
- Sending part:
The sending driver is slightly different, since we are not using the re-start feature.
(TODO: re-write this part if the stitch mode is released)
1. Call `sdio_slave_hal_send_start` to start the sending DMA.
If there is already any data queued, it will ne ready to be sent to host now.
2. Call `sdio_slave_hal_send_queue` to queue the data to send.
If the interrupt is enabled, the ISR will be invoked.
3. (Required if interrupt enabled) Call `` to clear the interrupt bits used by the SW
invoking logic.
4. Call `sdio_slave_hal_send_new_packet_if_exist` to check and send new packet (if there is
data queued).
5. Call `sdio_slave_hal_send_eof_happened` to check whether the previous packet is done.
It will also clear the interrupt status bit for this event.
6. Call `sdio_slave_hal_send_get_next_finished_arg` recursively to get the arguments for the
finished buffers.
7. (Optional when deinitialization) Call `sdio_slave_hal_send_flush_next_buffer` recursively
to get all buffers queued, regardless sent or not. Don't do this when the DMA is not stopped.
8. (Optional) Call `sdio_slave_hal_send_reset_counter` to reset the counter to current loaded
but not sent buffers if you want to reset the counter only. Don't do this when the DMA is not
stopped.
Note a counter should be used when performing step 2 and 6, to make sure that the queue size
is enough.
- Host part:
1. Call `sdio_slave_hal_hostint_set_ena` and `sdio_slave_hal_hostint_get_ena` to
enable/disable the interrupt sent to master. Note that the host can also modify the same
registers at the same time. Try to avoid using them outside the initialization process.
2. Call `sdio_slave_hal_hostint_send` and `sdio_slave_hal_hostint_clear` to trigger general
purpose interrupts or cancel all kinds of interrupts send to the host. These interrupts are
set/cleared in a concurrent-safe way, so the slave can call these functions safely.
3. Call `sdio_slave_hal_slvint_fetch_clear` to fetch the general purpose interrupts sent by
the host to the slave. These interrupts will also be cleared after the calls.
4. Call `sdio_slave_hal_host_get_reg` and `sdio_slave_hal_host_set_reg` to read/write the
general purpose shared between the host and slave. Note that these registers are also not
concurrent-safe. Try not to write to the same register from two directions at the same time.
*/
#pragma once
#include <esp_err.h>
#include "soc/lldesc.h"
#include "hal/sdio_slave_types.h"
#include "hal/sdio_slave_ll.h"
/// Space used for each sending descriptor. Should initialize the sendbuf accoring to this size.
#define SDIO_SLAVE_SEND_DESC_SIZE sizeof(sdio_slave_hal_send_desc_t)
/// Status of the sending part
typedef enum {
STATE_IDLE = 1,
STATE_WAIT_FOR_START = 2,
STATE_SENDING = 3,
STATE_GETTING_RESULT = 4,
STATE_GETTING_UNSENT_DESC = 5,
} send_state_t;
typedef struct {
uint8_t* data; ///< Address of the buffer
size_t size; ///< Size of the buffer, but can only queue (size/SDIO_SLAVE_SEND_DESC_SIZE)-1 descriptors
uint8_t* write_ptr;
uint8_t* read_ptr;
uint8_t* free_ptr;
} sdio_ringbuf_t;
// Append two extra words to be used by the HAL.
// Should Initialize the member `data` of `send_desc_queue` of the HAL context
// with size of this desc * N.
/// DMA descriptor with extra fields
typedef struct sdio_slave_hal_send_desc_s {
lldesc_t dma_desc; ///< Used by Hardware, has pointer linking to next desc
uint32_t pkt_len; ///< Accumulated length till this descriptor
void* arg; ///< Holding arguments indicating this buffer */
} sdio_slave_hal_send_desc_t;
/// Descriptor used by the receiving part, call `sdio_slave_hal_recv_init_desc`
/// to initialize it before use.
typedef lldesc_t sdio_slave_hal_recv_desc_t;
#define sdio_slave_hal_recv_desc_s lldesc_s
typedef STAILQ_HEAD(recv_stailq_head_s, sdio_slave_hal_recv_desc_s) sdio_slave_hal_recv_stailq_t;
/** HAL context structure. Call `sdio_slave_hal_init` to initialize it and
* configure required members before actually use the HAL.
*/
typedef struct {
/// Hardware registers for this SDIO slave peripheral, configured by
/// `sdio_slave_hal_init`
struct {
slc_dev_t* slc;
host_dev_t* host;
hinf_dev_t* hinf;
};
sdio_slave_sending_mode_t sending_mode; /**< Sending mode, should be manually configured before using the HAL.
* see `sdio_slave_sending_mode_t`.
*/
sdio_slave_timing_t timing; /**< Timing mode (launch edge and latch edge settings). Should be manually
* configured before using the HAL. `SDIO_SLAVE_TIMING_PSEND_PSAMPLE` is
* recommended by default.
*/
int send_queue_size; /**< Max buffers that can be queued before sending. Should be manually
* configured before using the HAL.
*/
size_t recv_buffer_size; /**< The size of each buffer. The host and slave should share a
* pre-negotiated value. Should be manually configured before using
* the HAL.
*/
sdio_ringbuf_t send_desc_queue; /**< The ring buffer used to hold queued descriptors. Should be manually
* initialized before using the HAL.
*/
//Internal status, no need to touch.
send_state_t send_state; // Current state of sending part.
uint32_t tail_pkt_len; // The accumulated send length of the tail packet.
sdio_slave_hal_send_desc_t* in_flight_head; // The head of linked list in-flight.
sdio_slave_hal_send_desc_t* in_flight_end; // The end of linked list in-flight.
sdio_slave_hal_send_desc_t* in_flight_next; // The header of linked list to be sent next time.
sdio_slave_hal_send_desc_t* returned_desc; // The last returned descriptor
sdio_slave_hal_recv_stailq_t recv_link_list; // Linked list of buffers ready to hold data and the buffers already hold data.
volatile sdio_slave_hal_recv_desc_t* recv_cur_ret; // Next desc to return, NULL if all loaded descriptors are returned.
} sdio_slave_context_t ;
/**
* Initialize the HAL, should provide buffers to the context and configure the
* members before this funciton is called.
*
* @param hal Context of the HAL layer.
*/
void sdio_slave_hal_init(sdio_slave_context_t *hal);
/**
* Initialize the SDIO slave peripheral hardware.
*
* @param hal Context of the HAL layer.
*/
void sdio_slave_hal_hw_init(sdio_slave_context_t *hal);
/**
* Set the IO ready for host to read.
*
* @param hal Context of the HAL layer.
* @param ready true to tell the host the slave is ready, otherwise false.
*/
void sdio_slave_hal_set_ioready(sdio_slave_context_t *hal, bool ready);
/*---------------------------------------------------------------------------
* Send
*--------------------------------------------------------------------------*/
/**
* The hardware sending DMA starts. If there is existing data, send them.
*
* @param hal Context of the HAL layer.
*/
esp_err_t sdio_slave_hal_send_start(sdio_slave_context_t *hal);
/**
* Stops hardware sending DMA.
*
* @note The data in the queue, as well as the counter are not touched.
* @param hal Context of the HAL layer.
*/
void sdio_slave_hal_send_stop(sdio_slave_context_t *hal);
/**
* Put some data into the sending queue.
*
* @note The caller should keeps the buffer, until the `arg` is returned by
* `sdio_slave_hal_send_get_next_finished_arg`.
* @note The caller should count to ensure there is enough space in the queue.
* The initial queue size is sizeof(sendbuf.data)/sizeof(sdio_slave_hal_send_desc_t)-1,
* Will decrease by one when this function successfully returns.
* Released only by `sdio_slave_hal_send_get_next_finished_arg` or
* `sdio_slave_hal_send_flush_next_buffer`.
*
* @note The HAL is not thread-safe. The caller should use a spinlock to ensure
* the `sdio_slave_hal_send_queue` and ... are not called at the same time.
*
* @param hal Context of the HAL layer.
* @param addr Address of data in the memory to send.
* @param len Length of data to send.
* @param arg Argument indicating this sending.
* @return Always ESP_OK.
*/
esp_err_t sdio_slave_hal_send_queue(sdio_slave_context_t *hal, uint8_t *addr, size_t len, void *arg);
/**
* The ISR should call this, to handle the SW invoking event.
* @param hal Context of the HAL layer.
*/
void sdio_slave_hal_send_handle_isr_invoke(sdio_slave_context_t *hal);
/**
* Check whether there is no in-flight transactions, and send new packet if there
* is new packets queued.
*
* @param hal Context of the HAL layer.
* @return
* - ESP_OK: The DMA starts to send a new packet.
* - ESP_ERR_NOT_FOUND: No packet waiting to be sent.
* - ESP_ERR_INVALID_STATE: There is packet in-flight.
*/
esp_err_t sdio_slave_hal_send_new_packet_if_exist(sdio_slave_context_t *hal);
/**
* Check whether the sending EOF has happened and clear the interrupt.
*
* Call `sdio_slave_hal_send_get_next_finished_arg` recursively to retrieve arguments of finished
* buffers.
*
* @param hal Context of the HAL layer.
* @return true if happened, otherwise false.
*/
bool sdio_slave_hal_send_eof_happened(sdio_slave_context_t *hal);
/**
* Get the arguments of finished packets. Call recursively until all finished
* arguments are all retrieved.
*
* @param hal Context of the HAL layer.
* @param out_arg Output argument of the finished buffer.
* @param out_returned_cnt Released queue size to be queued again.
* @return
* - ESP_OK: if one argument retrieved.
* - ESP_ERR_NOT_FOUND: All the arguments of the finished buffers are retrieved.
*/
esp_err_t sdio_slave_hal_send_get_next_finished_arg(sdio_slave_context_t *hal, void **out_arg, uint32_t* out_returned_cnt);
/**
* Flush one buffer in the queue, no matter sent, canceled or not sent yet.
*
* Call recursively to clear the whole queue before deinitialization.
*
* @note Only call when the DMA is stopped!
* @param hal Context of the HAL layer.
* @param out_arg Argument indiciating the buffer to send
* @param out_return_cnt Space in the queue released after this descriptor is flushed.
* @return
* - ESP_ERR_INVALID_STATE: This function call be called only when the DMA is stopped.
* - ESP_ERR_NOT_FOUND: if no buffer in the queue
* - ESP_OK: if a buffer is successfully flushed and returned.
*/
esp_err_t sdio_slave_hal_send_flush_next_buffer(sdio_slave_context_t *hal, void **out_arg, uint32_t *out_return_cnt);
/**
* Walk through all the unsent buffers and reset the counter to the accumulated length of them. The data will be kept.
*
* @note Only call when the DMA is stopped!
* @param hal Context of the HAL layer.
* @return
* - ESP_ERR_INVALID_STATE: this function call be called only when the DMA is stopped
* - ESP_OK: if success
*/
esp_err_t sdio_slave_hal_send_reset_counter(sdio_slave_context_t *hal);
/*---------------------------------------------------------------------------
* Receive
*--------------------------------------------------------------------------*/
/**
* Start the receiving DMA.
*
* @note If there are already some buffers loaded, will receive from them first.
* @param hal Context of the HAL layer.
*/
void sdio_slave_hal_recv_start(sdio_slave_context_t *hal);
/**
* Stop the receiving DMA.
*
* @note Data and the counter will not be touched. You can still call
* `sdio_slave_hal_recv_has_next_item` to get the received buffer.
* And unused buffers loaded to the HAL will still be in the `loaded`
* state in the HAL, until returned by `sdio_slave_hal_recv_unload_desc`.
* @param hal Context of the HAL layer.
*/
void sdio_slave_hal_recv_stop(sdio_slave_context_t* hal);
/**
* Associate the buffer to the descriptor given. The descriptor may also be initialized with some
* other data.
*
* @param hal Context of the HAL layer.
* @param desc Descriptor to associate with the buffer
* @param start Start address of the buffer
*/
void sdio_slave_hal_recv_init_desc(sdio_slave_context_t *hal, sdio_slave_hal_recv_desc_t *desc, uint8_t *start);
/**
* Load the buffer to the HAL to be used to receive data.
*
* @note Loaded buffers will be returned to the upper layer only when:
* 1. Returned by `sdio_slave_hal_recv_has_next_item` when receiving to that buffer successfully
* done.
* 2. Returned by `sdio_slave_hal_recv_unload_desc` unconditionally.
* @param hal Context of the HAL layer.
* @param desc Descriptor to load to the HAL to receive.
*/
void sdio_slave_hal_load_buf(sdio_slave_context_t *hal, sdio_slave_hal_recv_desc_t *desc);
/**
* Check and clear the interrupt indicating a buffer has finished receiving.
*
* @param hal Context of the HAL layer.
* @return true if interrupt triggered, otherwise false.
*/
bool sdio_slave_hal_recv_done(sdio_slave_context_t* hal);
/**
* Call this function recursively to check whether there is any buffer that has
* finished receiving.
*
* Will walk through the linked list to find a newer finished buffer. For each successful return,
* it means there is one finished buffer. You can one by `sdio_slave_hal_recv_unload_desc`. You can
* also call `sdio_slave_hal_recv_has_next_item` several times continuously before you call the
* `sdio_slave_hal_recv_unload_desc` for the same times.
*
* @param hal Context of the HAL layer.
* @return true if there is
*/
bool sdio_slave_hal_recv_has_next_item(sdio_slave_context_t* hal);
/**
* Unconditionally remove and return the first descriptor loaded to the HAL.
*
* Unless during de-initialization, `sdio_slave_hal_recv_has_next_item` should have succeed for the
* same times as this function is called, to ensure the returned descriptor has finished its
* receiving job.
*
* @param hal Context of the HAL layer.
* @return The removed descriptor, NULL means the linked-list is empty.
*/
sdio_slave_hal_recv_desc_t *sdio_slave_hal_recv_unload_desc(sdio_slave_context_t *hal);
/**
* Walk through all the unused buffers and reset the counter to the number of
* them.
*
* @note Only call when the DMA is stopped!
* @param hal Context of the HAL layer.
*/
void sdio_slave_hal_recv_reset_counter(sdio_slave_context_t *hal);
/**
* Walk through all the used buffers, clear the finished flag and appended them
* back to the end of the unused list, waiting to receive then.
*
* @note You will lose all the received data in the buffer.
* @note Only call when the DMA is stopped!
* @param hal Context of the HAL layer.
*/
void sdio_slave_hal_recv_flush_one_buffer(sdio_slave_context_t *hal);
/*---------------------------------------------------------------------------
* Host
*--------------------------------------------------------------------------*/
/**
* Enable some of the interrupts for the host.
*
* @note May have concurrency issue wit the host or other tasks, suggest only use it during
* initialization.
* @param hal Context of the HAL layer.
* @param mask Bitwise mask for the interrupts to enable.
*/
void sdio_slave_hal_hostint_set_ena(sdio_slave_context_t *hal, const sdio_slave_hostint_t *mask);
/**
* Get the enabled interrupts.
*
* @param hal Context of the HAL layer.
* @param out_int_mask Output of the enabled interrupts
*/
void sdio_slave_hal_hostint_get_ena(sdio_slave_context_t *hal, sdio_slave_hostint_t *out_int_mask);
/**
* Send general purpose interrupt (slave send to host).
* @param hal Context of the HAL layer.
* @param mask Interrupts to send, only `SDIO_SLAVE_HOSTINT_BIT*` are allowed.
*/
void sdio_slave_hal_hostint_send(sdio_slave_context_t *hal, const sdio_slave_hostint_t *mask);
/**
* Cleared the specified interrupts for the host.
*
* @param hal Context of the HAL layer.
* @param mask Interrupts to clear.
*/
void sdio_slave_hal_hostint_clear(sdio_slave_context_t *hal, const sdio_slave_hostint_t *mask);
/**
* Fetch the interrupt (host send to slave) status bits and clear all of them.
* @param hal Context of the HAL layer.
* @param out_int_mask Output interrupt status
*/
void sdio_slave_hal_slvint_fetch_clear(sdio_slave_context_t *hal, sdio_slave_ll_slvint_t *out_int_mask);
/**
* Get the value of a shared general purpose register.
*
* @param hal Context of the HAL layer.
* @param pos Position of the register, 4 bytes share a word. 0-63 except 24-27.
* @return The register value.
*/
uint8_t sdio_slave_hal_host_get_reg(sdio_slave_context_t *hal, int pos);
/**
* Set the value of shared general purpose register.
*
* @param hal Context of the HAL layer.
* @param pos Position of the register, 4 bytes share a word. 0-63 except 24-27.
* @param reg Value to set.
*/
void sdio_slave_hal_host_set_reg(sdio_slave_context_t *hal, int pos, uint8_t reg);
tools/sdk/esp32s2/include/soc/include/hal/sdio_slave_ll.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32 SDIO slave register operations
// It's strange but `tx_*` regs for host->slave transfers while `rx_*` regs for slave->host transfers
// To reduce ambiguity, we call (host->slave, tx) transfers receiving and (slave->host, rx) transfers receiving
#pragma once
#include "hal/sdio_slave_hal.h"
#include "soc/slc_struct.h"
#include "soc/slc_reg.h"
#include "soc/host_struct.h"
#include "soc/host_reg.h"
#include "soc/hinf_struct.h"
#include "soc/lldesc.h"
/// Get address of the only SLC registers for ESP32
#define sdio_slave_ll_get_slc(ID) (&SLC)
/// Get address of the only HOST registers for ESP32
#define sdio_slave_ll_get_host(ID) (&HOST)
/// Get address of the only HINF registers for ESP32
#define sdio_slave_ll_get_hinf(ID) (&HINF)
/// Mask of general purpose interrupts sending from the host.
typedef enum {
SDIO_SLAVE_LL_SLVINT_0 = BIT(0), ///< General purpose interrupt bit 0.
SDIO_SLAVE_LL_SLVINT_1 = BIT(1),
SDIO_SLAVE_LL_SLVINT_2 = BIT(2),
SDIO_SLAVE_LL_SLVINT_3 = BIT(3),
SDIO_SLAVE_LL_SLVINT_4 = BIT(4),
SDIO_SLAVE_LL_SLVINT_5 = BIT(5),
SDIO_SLAVE_LL_SLVINT_6 = BIT(6),
SDIO_SLAVE_LL_SLVINT_7 = BIT(7),
} sdio_slave_ll_slvint_t;
/**
* Initialize the hardware.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_init(slc_dev_t *slc)
{
slc->slc0_int_ena.val = 0;
slc->conf0.slc0_rx_auto_wrback = 1;
slc->conf0.slc0_token_auto_clr = 0;
slc->conf0.slc0_rx_loop_test = 0;
slc->conf0.slc0_tx_loop_test = 0;
slc->conf1.slc0_rx_stitch_en = 0;
slc->conf1.slc0_tx_stitch_en = 0;
slc->conf1.slc0_len_auto_clr = 0;
slc->rx_dscr_conf.slc0_token_no_replace = 1;
}
/**
* Set the timing for the communication
*
* @param host Address of the host registers
* @param timing Timing configuration to set
*/
static inline void sdio_slave_ll_set_timing(host_dev_t *host, sdio_slave_timing_t timing)
{
switch(timing) {
case SDIO_SLAVE_TIMING_PSEND_PSAMPLE:
host->conf.frc_sdio20 = 0x1f;
host->conf.frc_sdio11 = 0;
host->conf.frc_pos_samp = 0x1f;
host->conf.frc_neg_samp = 0;
break;
case SDIO_SLAVE_TIMING_PSEND_NSAMPLE:
host->conf.frc_sdio20 = 0x1f;
host->conf.frc_sdio11 = 0;
host->conf.frc_pos_samp = 0;
host->conf.frc_neg_samp = 0x1f;
break;
case SDIO_SLAVE_TIMING_NSEND_PSAMPLE:
host->conf.frc_sdio20 = 0;
host->conf.frc_sdio11 = 0x1f;
host->conf.frc_pos_samp = 0x1f;
host->conf.frc_neg_samp = 0;
break;
case SDIO_SLAVE_TIMING_NSEND_NSAMPLE:
host->conf.frc_sdio20 = 0;
host->conf.frc_sdio11 = 0x1f;
host->conf.frc_pos_samp = 0;
host->conf.frc_neg_samp = 0x1f;
break;
}
}
/**
* Set the HS supported bit to be read by the host.
*
* @param hinf Address of the hinf registers
* @param hs true if supported, otherwise false.
*/
static inline void sdio_slave_ll_enable_hs(hinf_dev_t *hinf, bool hs)
{
if (hs) {
hinf->cfg_data1.sdio_ver = 0x232;
hinf->cfg_data1.highspeed_enable = 1;
}
}
/**
* Set the IO Ready bit to be read by the host.
*
* @param hinf Address of the hinf registers
* @param ready true if ready, otherwise false.
*/
static inline void sdio_slave_ll_set_ioready(hinf_dev_t *hinf, bool ready)
{
hinf->cfg_data1.sdio_ioready1 = (ready ? 1 : 0); //set IO ready to 1 to stop host from using
}
/*---------------------------------------------------------------------------
* Send
*--------------------------------------------------------------------------*/
/**
* Reset the sending DMA.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_send_reset(slc_dev_t *slc)
{
//reset to flush previous packets
slc->conf0.slc0_rx_rst = 1;
slc->conf0.slc0_rx_rst = 0;
}
/**
* Start the sending DMA with the given descriptor.
*
* @param slc Address of the SLC registers
* @param desc Descriptor to send
*/
static inline void sdio_slave_ll_send_start(slc_dev_t *slc, const lldesc_t *desc)
{
slc->slc0_rx_link.addr = (uint32_t)desc;
slc->slc0_rx_link.start = 1;
}
/**
* Write the PKT_LEN register to be written by the host to a certain value.
*
* @param slc Address of the SLC registers
* @param len Length to write
*/
static inline void sdio_slave_ll_send_write_len(slc_dev_t *slc, uint32_t len)
{
slc->slc0_len_conf.val = FIELD_TO_VALUE2(SLC_SLC0_LEN_WDATA, len) | FIELD_TO_VALUE2(SLC_SLC0_LEN_WR, 1);
}
/**
* Read the value of PKT_LEN register. The register may keep the same until read
* by the host.
*
* @param host Address of the host registers
* @return The value of PKT_LEN register.
*/
static inline uint32_t sdio_slave_ll_send_read_len(host_dev_t *host)
{
return host->pkt_len.reg_slc0_len;
}
/**
* Enable the rx_done interrupt. (sending)
*
* @param slc Address of the SLC registers
* @param ena true if enable, otherwise false.
*/
static inline void sdio_slave_ll_send_part_done_intr_ena(slc_dev_t *slc, bool ena)
{
slc->slc0_int_ena.rx_done = (ena ? 1 : 0);
}
/**
* Clear the rx_done interrupt. (sending)
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_send_part_done_clear(slc_dev_t *slc)
{
slc->slc0_int_clr.rx_done = 1;
}
/**
* Check whether the hardware is ready for the SW to use rx_done to invoke
* the ISR.
*
* @param slc Address of the SLC registers
* @return true if ready, otherwise false.
*/
static inline bool sdio_slave_ll_send_invoker_ready(slc_dev_t *slc)
{
return slc->slc0_int_raw.rx_done;
}
/**
* Stop the sending DMA.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_send_stop(slc_dev_t *slc)
{
slc->slc0_rx_link.stop = 1;
}
/**
* Enable the sending interrupt (rx_eof).
*
* @param slc Address of the SLC registers
* @param ena true to enable, false to disable
*/
static inline void sdio_slave_ll_send_intr_ena(slc_dev_t *slc, bool ena)
{
slc->slc0_int_ena.rx_eof = (ena? 1: 0);
}
/**
* Clear the sending interrupt (rx_eof).
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_send_intr_clr(slc_dev_t *slc)
{
slc->slc0_int_clr.rx_eof = 1;
}
/**
* Check whether the sending is done.
*
* @param slc Address of the SLC registers
* @return true if done, otherwise false
*/
static inline bool sdio_slave_ll_send_done(slc_dev_t *slc)
{
return slc->slc0_int_st.rx_eof != 0;
}
/**
* Clear the host interrupt indicating the slave having packet to be read.
*
* @param host Address of the host registers
*/
static inline void sdio_slave_ll_send_hostint_clr(host_dev_t *host)
{
host->slc0_int_clr.rx_new_packet = 1;
}
/*---------------------------------------------------------------------------
* Receive
*--------------------------------------------------------------------------*/
/**
* Enable the receiving interrupt.
*
* @param slc Address of the SLC registers
* @param ena
*/
static inline void sdio_slave_ll_recv_intr_ena(slc_dev_t *slc, bool ena)
{
slc->slc0_int_ena.tx_done = (ena ? 1 : 0);
}
/**
* Start receiving DMA with the given descriptor.
*
* @param slc Address of the SLC registers
* @param desc Descriptor of the receiving buffer.
*/
static inline void sdio_slave_ll_recv_start(slc_dev_t *slc, lldesc_t *desc)
{
slc->slc0_tx_link.addr = (uint32_t)desc;
slc->slc0_tx_link.start = 1;
}
/**
* Increase the receiving buffer counter by 1.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_size_inc(slc_dev_t *slc)
{
// fields wdata and inc_more should be written by the same instruction.
slc->slc0_token1.val = FIELD_TO_VALUE2(SLC_SLC0_TOKEN1_WDATA, 1) | FIELD_TO_VALUE2(SLC_SLC0_TOKEN1_INC_MORE, 1);
}
/**
* Reset the receiving buffer.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_size_reset(slc_dev_t *slc)
{
slc->slc0_token1.val = FIELD_TO_VALUE2(SLC_SLC0_TOKEN1_WDATA, 0) | FIELD_TO_VALUE2(SLC_SLC0_TOKEN1_WR, 1);
}
/**
* Check whether there is a receiving finished event.
*
* @param slc Address of the SLC registers
* @return
*/
static inline bool sdio_slave_ll_recv_done(slc_dev_t *slc)
{
return slc->slc0_int_raw.tx_done != 0;
}
/**
* Clear the receiving finished interrupt.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_done_clear(slc_dev_t *slc)
{
slc->slc0_int_clr.tx_done = 1;
}
/**
* Restart the DMA. Call after you modified the next pointer of the tail descriptor to the appended
* descriptor.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_restart(slc_dev_t *slc)
{
slc->slc0_tx_link.restart = 1;
}
/**
* Reset the receiving DMA.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_reset(slc_dev_t *slc)
{
slc->conf0.slc0_tx_rst = 1;
slc->conf0.slc0_tx_rst = 0;
}
/**
* Stop the receiving DMA.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_stop(slc_dev_t *slc)
{
slc->slc0_tx_link.stop = 1;
}
/*---------------------------------------------------------------------------
* Host
*--------------------------------------------------------------------------*/
/**
* Get the address of the shared general purpose register. Internal.
*
* @param host Address of the host registers
* @param pos Position of the register, 0-63 except 24-27.
* @return address of the register.
*/
static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t* host, int pos)
{
return (intptr_t )&(host->conf_w0) + pos + (pos>23?4:0) + (pos>31?12:0);
}
/**
* Get the value of the shared general purpose register.
*
* @param host Address of the host registers
* @param pos Position of the register, 0-63, except 24-27.
* @return value of the register.
*/
static inline uint8_t sdio_slave_ll_host_get_reg(host_dev_t *host, int pos)
{
return *(uint8_t*)sdio_slave_ll_host_get_w_reg(host, pos);
}
/**
* Set the value of the shared general purpose register.
*
* @param host Address of the host registers
* @param pos Position of the register, 0-63, except 24-27.
* @param reg Value to set.
*/
static inline void sdio_slave_ll_host_set_reg(host_dev_t* host, int pos, uint8_t reg)
{
uint32_t* addr = (uint32_t*)(sdio_slave_ll_host_get_w_reg(host, pos) & (~3));
uint32_t shift = (pos % 4) * 8;
*addr &= ~(0xff << shift);
*addr |= ((uint32_t)reg << shift);
}
/**
* Get the interrupt enable bits for the host.
*
* @param host Address of the host registers
* @return Enabled interrupts
*/
static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t* host)
{
return host->slc0_func1_int_ena.val;
}
/**
* Set the interrupt enable bits for the host.
*
* @param host Address of the host registers
* @param mask Mask of interrupts to enable
*/
static inline void sdio_slave_ll_host_set_intena(host_dev_t *host, const sdio_slave_hostint_t *mask)
{
host->slc0_func1_int_ena.val = (*mask);
}
/**
* Clear the interrupt bits for the host.
* @param host Address of the host registers
* @param mask Mask of interrupts to clear.
*/
static inline void sdio_slave_ll_host_intr_clear(host_dev_t* host, const sdio_slave_hostint_t *mask)
{
host->slc0_int_clr.val = (*mask);
}
/**
* Send general purpose interrupts to the host.
* @param slc Address of the SLC registers
* @param mask Mask of interrupts to seend to host
*/
static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_hostint_t *mask)
{
//use registers in SLC to trigger, rather than write HOST registers directly
//other interrupts than tohost interrupts are not supported yet
slc->intvec_tohost.slc0_intvec = (*mask);
}
/**
* Enable some of the slave interrups (send from host)
*
* @param slc Address of the SLC registers
* @param mask Mask of interrupts to enable, all those set to 0 will be disabled.
*/
static inline void sdio_slave_ll_slvint_set_ena(slc_dev_t *slc, const sdio_slave_ll_slvint_t *mask)
{
//other interrupts are not enabled
slc->slc0_int_ena.val = (slc->slc0_int_ena.val & (~0xff)) | ((*mask) & 0xff);
}
/**
* Fetch the slave interrupts (send from host) and clear them.
*
* @param slc Address of the SLC registers
* @param out_slv_int Output of the slave interrupts fetched and cleared.
*/
static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_ll_slvint_t *out_slv_int)
{
sdio_slave_ll_slvint_t slv_int = slc->slc0_int_st.val & 0xff;
*out_slv_int = slv_int;
slc->slc0_int_clr.val = slv_int;
}
tools/sdk/esp32s2/include/soc/include/hal/sdio_slave_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/soc.h"
/// Mask of interrupts sending to the host.
typedef enum {
SDIO_SLAVE_HOSTINT_BIT0 = BIT(0), ///< General purpose interrupt bit 0.
SDIO_SLAVE_HOSTINT_BIT1 = BIT(1),
SDIO_SLAVE_HOSTINT_BIT2 = BIT(2),
SDIO_SLAVE_HOSTINT_BIT3 = BIT(3),
SDIO_SLAVE_HOSTINT_BIT4 = BIT(4),
SDIO_SLAVE_HOSTINT_BIT5 = BIT(5),
SDIO_SLAVE_HOSTINT_BIT6 = BIT(6),
SDIO_SLAVE_HOSTINT_BIT7 = BIT(7),
SDIO_SLAVE_HOSTINT_SEND_NEW_PACKET = BIT(23), ///< New packet available
} sdio_slave_hostint_t;
/// Timing of SDIO slave
typedef enum {
SDIO_SLAVE_TIMING_PSEND_PSAMPLE = 0,/**< Send at posedge, and sample at posedge. Default value for HS mode.
* Normally there's no problem using this to work in DS mode.
*/
SDIO_SLAVE_TIMING_NSEND_PSAMPLE ,///< Send at negedge, and sample at posedge. Default value for DS mode and below.
SDIO_SLAVE_TIMING_PSEND_NSAMPLE, ///< Send at posedge, and sample at negedge
SDIO_SLAVE_TIMING_NSEND_NSAMPLE, ///< Send at negedge, and sample at negedge
} sdio_slave_timing_t;
/// Configuration of SDIO slave mode
typedef enum {
SDIO_SLAVE_SEND_STREAM = 0, ///< Stream mode, all packets to send will be combined as one if possible
SDIO_SLAVE_SEND_PACKET = 1, ///< Packet mode, one packets will be sent one after another (only increase packet_len if last packet sent).
} sdio_slave_sending_mode_t;
tools/sdk/esp32s2/include/soc/include/hal/sigmadelta_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for SIGMADELTA.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#include "soc/sigmadelta_periph.h"
#include "hal/sigmadelta_types.h"
#include "hal/sigmadelta_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
gpio_sd_dev_t *dev;
} sigmadelta_hal_context_t;
/**
* @brief Set Sigma-delta channel duty.
*
* @param hal Context of the HAL layer
* @param channel Sigma-delta channel number
* @param duty Sigma-delta duty of one channel, the value ranges from -128 to 127, recommended range is -90 ~ 90.
* The waveform is more like a random one in this range.
*/
#define sigmadelta_hal_set_duty(hal, channel, duty) sigmadelta_ll_set_duty((hal)->dev, channel, duty)
/**
* @brief Set Sigma-delta channel's clock pre-scale value.
*
* @param hal Context of the HAL layer
* @param channel Sigma-delta channel number
* @param prescale The divider of source clock, ranges from 0 to 255
*/
#define sigmadelta_hal_set_prescale(hal, channel, prescale) sigmadelta_ll_set_prescale((hal)->dev, channel, prescale)
/**
* @brief Init the SIGMADELTA hal and set the SIGMADELTA to the default configuration. This function should be called first before other hal layer function is called
*
* @param hal Context of the HAL layer
* @param sigmadelta_num The uart port number, the max port number is (SIGMADELTA_NUM_MAX -1)
*/
void sigmadelta_hal_init(sigmadelta_hal_context_t *hal, int sigmadelta_num);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/sigmadelta_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/sigmadelta_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief SIGMADELTA port number, the max port number is (SIGMADELTA_NUM_MAX -1).
*/
typedef int sigmadelta_port_t;
/**
* @brief Sigma-delta channel list
*/
typedef int sigmadelta_channel_t;
/**
* @brief Sigma-delta configure struct
*/
typedef struct {
sigmadelta_channel_t channel; /*!< Sigma-delta channel number */
int8_t sigmadelta_duty; /*!< Sigma-delta duty, duty ranges from -128 to 127. */
uint8_t sigmadelta_prescale; /*!< Sigma-delta prescale, prescale ranges from 0 to 255. */
uint8_t sigmadelta_gpio; /*!< Sigma-delta output io number, refer to gpio.h for more details. */
} sigmadelta_config_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/soc_hal.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc_caps.h"
#include "hal/cpu_hal.h"
#include "hal/soc_ll.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_CPU_CORES_NUM > 1
// Utility functions for multicore targets
#define __SOC_HAL_PERFORM_ON_OTHER_CORES(action) { \
for (int i = 0, cur = cpu_hal_get_core_id(); i < SOC_CPU_CORES_NUM; i++) { \
if (i != cur) { \
action(i); \
} \
} \
}
#define SOC_HAL_STALL_OTHER_CORES() __SOC_HAL_PERFORM_ON_OTHER_CORES(soc_hal_stall_core);
#define SOC_HAL_UNSTALL_OTHER_CORES() __SOC_HAL_PERFORM_ON_OTHER_CORES(soc_hal_unstall_core);
#define SOC_HAL_RESET_OTHER_CORES() __SOC_HAL_PERFORM_ON_OTHER_CORES(soc_hal_reset_core);
/**
* Stall the specified CPU core.
*
* @note Has no effect if the core is already stalled - does not return an
* ESP_ERR_INVALID_STATE.
*
* @param core core to stall [0..SOC_CPU_CORES_NUM - 1]
*/
void soc_hal_stall_core(int core);
/**
* Unstall the specified CPU core.
*
* @note Has no effect if the core is already unstalled - does not return an
* ESP_ERR_INVALID_STATE.
*
* @param core core to unstall [0..SOC_CPU_CORES_NUM - 1]
*/
void soc_hal_unstall_core(int core);
#endif // SOC_CPU_CORES_NUM > 1
/**
* Reset the specified core.
*
* @param core core to reset [0..SOC_CPU_CORES_NUM - 1]
*/
#define soc_hal_reset_core(core) soc_ll_reset_core((core))
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/spi_flash_hal.h
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// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The HAL is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for SPI Flash (common part)
#pragma once
#include "hal/spi_flash_ll.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include "soc/soc_memory_layout.h"
/* Hardware host-specific constants */
#define SPI_FLASH_HAL_MAX_WRITE_BYTES 64
#define SPI_FLASH_HAL_MAX_READ_BYTES 64
/**
* Generic driver context structure for all chips using the SPI peripheral.
* Include this into the HEAD of the driver data for other driver
* implementations that also use the SPI peripheral.
*/
typedef struct {
spi_dev_t *spi; ///< Pointer to SPI peripheral registers (SP1, SPI2 or SPI3). Set before initialisation.
int cs_num; ///< Which cs pin is used, 0-2.
int extra_dummy;
spi_flash_ll_clock_reg_t clock_conf;
} spi_flash_memspi_data_t;
/// Configuration structure for the SPI driver.
typedef struct {
spi_host_device_t host_id; ///< SPI peripheral ID.
int cs_num; ///< Which cs pin is used, 0-2.
bool iomux; ///< Whether the IOMUX is used, used for timing compensation.
int input_delay_ns; ///< Input delay on the MISO pin after the launch clock， used for timing compensation.
esp_flash_speed_t speed;///< SPI flash clock speed to work at.
} spi_flash_memspi_config_t;
/**
* Configure SPI flash hal settings.
*
* @param data Buffer to hold configured data, the buffer should be in DRAM to be available when cache disabled
* @param cfg Configurations to set
*
* @return
* - ESP_OK: success
* - ESP_ERR_INVALID_ARG: the data buffer is not in the DRAM.
*/
esp_err_t spi_flash_hal_init(spi_flash_memspi_data_t *data_out, const spi_flash_memspi_config_t *cfg);
/**
* Configure the device-related register before transactions.
*
* @param driver The driver context.
*
* @return always return ESP_OK.
*/
esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver);
/**
* Send an user-defined spi transaction to the device.
*
* @note This is usually used when the memspi interface doesn't support some
* particular commands. Since this function supports timing compensation, it is
* also used to receive some data when the frequency is high.
*
* @param driver The driver context.
* @param trans The transaction to send, also holds the received data.
*
* @return always return ESP_OK.
*/
esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *driver, spi_flash_trans_t *trans);
/**
* Erase whole flash chip by using the erase chip (C7h) command.
*
* @param driver The driver context.
*/
void spi_flash_hal_erase_chip(spi_flash_host_driver_t *driver);
/**
* Erase a specific sector by its start address through the sector erase (20h)
* command.
*
* @param driver The driver context.
* @param start_address Start address of the sector to erase.
*/
void spi_flash_hal_erase_sector(spi_flash_host_driver_t *driver, uint32_t start_address);
/**
* Erase a specific 64KB block by its start address through the 64KB block
* erase (D8h) command.
*
* @param driver The driver context.
* @param start_address Start address of the block to erase.
*/
void spi_flash_hal_erase_block(spi_flash_host_driver_t *driver, uint32_t start_address);
/**
* Program a page of the flash using the page program (02h) command.
*
* @param driver The driver context.
* @param address Address of the page to program
* @param buffer Data to program
* @param length Size of the buffer in bytes, no larger than ``SPI_FLASH_HAL_MAX_WRITE_BYTES`` (64) bytes.
*/
void spi_flash_hal_program_page(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length);
/**
* Read from the flash. Call ``spi_flash_hal_configure_host_read_mode`` to
* configure the read command before calling this function.
*
* @param driver The driver context.
* @param buffer Buffer to store the read data
* @param address Address to read
* @param length Length to read, no larger than ``SPI_FLASH_HAL_MAX_READ_BYTES`` (64) bytes.
*
* @return always return ESP_OK.
*/
esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len);
/**
* @brief Send the write enable (06h) or write disable (04h) command to the flash chip.
*
* @param driver The driver context.
* @param wp true to enable the write protection, otherwise false.
*
* @return always return ESP_OK.
*/
esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *chip_drv, bool wp);
/**
* Check whether the SPI host is idle and can perform other operations.
*
* @param driver The driver context.
*
* @return ture if idle, otherwise false.
*/
bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver);
/**
* @brief Configure the SPI host hardware registers for the specified io mode.
*
* Note that calling this configures SPI host registers, so if running any
* other commands as part of set_io_mode() then these must be run before
* calling this function.
*
* The command value, address length and dummy cycles are configured according
* to the format of read commands:
*
* - command: 8 bits, value set.
* - address: 24 bits
* - dummy: cycles to compensate the input delay
* - out & in data: 0 bits.
*
* The following commands still need to:
*
* - Read data: set address value and data (length and contents), no need
* to touch command and dummy phases.
* - Common read: set command value, address value (or length to 0 if not used)
* - Common write: set command value, address value (or length to 0 if not
* used), disable dummy phase, and set output data.
*
* @param driver The driver context
* @param io_mode The HW read mode to use
* @param addr_bitlen Length of the address phase, in bits
* @param dummy_cyclelen_base Base cycles of the dummy phase, some extra dummy cycles may be appended to compensate the timing.
* @param command Actual reading command to send to flash chip on the bus.
*
* @return always return ESP_OK.
*/
esp_err_t spi_flash_hal_configure_host_io_mode(spi_flash_host_driver_t *driver, uint32_t command, uint32_t addr_bitlen,
int dummy_cyclelen_base, esp_flash_io_mode_t io_mode);
/**
* Poll until the last operation is done.
*
* @param driver The driver context.
*/
void spi_flash_hal_poll_cmd_done(spi_flash_host_driver_t *driver);
/**
* Check whether the given buffer can be used as the write buffer directly. If 'chip' is connected to the main SPI bus, we can only write directly from
* regions that are accessible ith cache disabled. *
*
* @param driver The driver context
* @param p The buffer holding data to send.
*
* @return True if the buffer can be used to send data, otherwise false.
*/
bool spi_flash_hal_supports_direct_write(spi_flash_host_driver_t *driver, const void *p);
/**
* Check whether the given buffer can be used as the read buffer directly. If 'chip' is connected to the main SPI bus, we can only read directly from
* regions that are accessible ith cache disabled. *
*
* @param driver The driver context
* @param p The buffer to hold the received data.
*
* @return True if the buffer can be used to receive data, otherwise false.
*/
bool spi_flash_hal_supports_direct_read(spi_flash_host_driver_t *driver, const void *p);
tools/sdk/esp32s2/include/soc/include/hal/spi_flash_types.h
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// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <esp_types.h>
#include "esp_flash_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/** Definition of a common transaction. Also holds the return value. */
typedef struct {
uint8_t command; ///< Command to send, always 8bits
uint8_t mosi_len; ///< Output data length, in bytes
uint8_t miso_len; ///< Input data length, in bytes
uint8_t address_bitlen; ///< Length of address in bits, set to 0 if command does not need an address
uint32_t address; ///< Address to perform operation on
const uint8_t *mosi_data; ///< Output data to salve
uint8_t *miso_data; ///< [out] Input data from slave, little endian
} spi_flash_trans_t;
/**
* @brief SPI flash clock speed values, always refer to them by the enum rather
* than the actual value (more speed may be appended into the list).
*
* A strategy to select the maximum allowed speed is to enumerate from the
* ``ESP_FLSH_SPEED_MAX-1`` or highest frequency supported by your flash, and
* decrease the speed until the probing success.
*/
typedef enum {
ESP_FLASH_5MHZ = 0, ///< The flash runs under 5MHz
ESP_FLASH_10MHZ, ///< The flash runs under 10MHz
ESP_FLASH_20MHZ, ///< The flash runs under 20MHz
ESP_FLASH_26MHZ, ///< The flash runs under 26MHz
ESP_FLASH_40MHZ, ///< The flash runs under 40MHz
ESP_FLASH_80MHZ, ///< The flash runs under 80MHz
ESP_FLASH_SPEED_MAX, ///< The maximum frequency supported by the host is ``ESP_FLASH_SPEED_MAX-1``.
} esp_flash_speed_t;
///Lowest speed supported by the driver, currently 5 MHz
#define ESP_FLASH_SPEED_MIN ESP_FLASH_5MHZ
/** @brief Mode used for reading from SPI flash */
typedef enum {
SPI_FLASH_SLOWRD = 0, ///< Data read using single I/O, some limits on speed
SPI_FLASH_FASTRD, ///< Data read using single I/O, no limit on speed
SPI_FLASH_DOUT, ///< Data read using dual I/O
SPI_FLASH_DIO, ///< Both address & data transferred using dual I/O
SPI_FLASH_QOUT, ///< Data read using quad I/O
SPI_FLASH_QIO, ///< Both address & data transferred using quad I/O
SPI_FLASH_READ_MODE_MAX, ///< The fastest io mode supported by the host is ``ESP_FLASH_READ_MODE_MAX-1``.
} esp_flash_io_mode_t;
///Slowest io mode supported by ESP32, currently SlowRd
#define SPI_FLASH_READ_MODE_MIN SPI_FLASH_SLOWRD
struct spi_flash_host_driver_t;
typedef struct spi_flash_host_driver_t spi_flash_host_driver_t;
/** Host driver configuration and context structure. */
struct spi_flash_host_driver_t {
/**
* Configuration and static data used by the specific host driver. The type
* is determined by the host driver.
*/
void *driver_data;
/**
* Configure the device-related register before transactions. This saves
* some time to re-configure those registers when we send continuously
*/
esp_err_t (*dev_config)(spi_flash_host_driver_t *driver);
/**
* Send an user-defined spi transaction to the device.
*/
esp_err_t (*common_command)(spi_flash_host_driver_t *driver, spi_flash_trans_t *t);
/**
* Read flash ID.
*/
esp_err_t (*read_id)(spi_flash_host_driver_t *driver, uint32_t *id);
/**
* Erase whole flash chip.
*/
void (*erase_chip)(spi_flash_host_driver_t *driver);
/**
* Erase a specific sector by its start address.
*/
void (*erase_sector)(spi_flash_host_driver_t *driver, uint32_t start_address);
/**
* Erase a specific block by its start address.
*/
void (*erase_block)(spi_flash_host_driver_t *driver, uint32_t start_address);
/**
* Read the status of the flash chip.
*/
esp_err_t (*read_status)(spi_flash_host_driver_t *driver, uint8_t *out_sr);
/**
* Disable write protection.
*/
esp_err_t (*set_write_protect)(spi_flash_host_driver_t *driver, bool wp);
/**
* Program a page of the flash. Check ``max_write_bytes`` for the maximum allowed writing length.
*/
void (*program_page)(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length);
/** Check whether need to allocate new buffer to write */
bool (*supports_direct_write)(spi_flash_host_driver_t *driver, const void *p);
/** Check whether need to allocate new buffer to read */
bool (*supports_direct_read)(spi_flash_host_driver_t *driver, const void *p);
/** maximum length of program_page */
int max_write_bytes;
/**
* Read data from the flash. Check ``max_read_bytes`` for the maximum allowed reading length.
*/
esp_err_t (*read)(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len);
/** maximum length of read */
int max_read_bytes;
/**
* Check whether the host is idle to perform new operations.
*/
bool (*host_idle)(spi_flash_host_driver_t *driver);
/**
* Configure the host to work at different read mode. Responsible to compensate the timing and set IO mode.
*/
esp_err_t (*configure_host_io_mode)(spi_flash_host_driver_t *driver, uint32_t command,
uint32_t addr_bitlen, int dummy_bitlen_base,
esp_flash_io_mode_t io_mode);
/**
* Internal use, poll the HW until the last operation is done.
*/
void (*poll_cmd_done)(spi_flash_host_driver_t *driver);
/**
* For some host (SPI1), they are shared with a cache. When the data is
* modified, the cache needs to be flushed. Left NULL if not supported.
*/
esp_err_t (*flush_cache)(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size);
};
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/spi_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for SPI master (common part)
// SPI HAL usages:
// 1. initialize the bus
// 2. initialize the DMA descriptors if DMA used
// 3. setup the clock speed (since this takes long time)
// 4. call setup_device to update parameters for the specific device
// 5. call setup_trans to update parameters for the specific transaction
// 6. prepare data to send, and prepare the receiving buffer
// 7. trigger user defined SPI transaction to start
// 8. wait until the user transaction is done
// 9. fetch the received data
// Parameter to be updated only during ``setup_device`` will be highlighted in the
// field comments.
#pragma once
#include "hal/spi_ll.h"
#include <esp_err.h>
#include "soc/lldesc.h"
/**
* Timing configuration structure that should be calculated by
* ``spi_hal_setup_clock`` at initialization and hold. Filled into the
* ``timing_conf`` member of the context of HAL before setup a device.
*/
typedef struct {
spi_ll_clock_val_t clock_reg; ///< Register value used by the LL layer
int timing_dummy; ///< Extra dummy needed to compensate the timing
int timing_miso_delay; ///< Extra miso delay clocks to compensate the timing
} spi_hal_timing_conf_t;
/**
* Context that should be maintained by both the driver and the HAL.
*/
typedef struct {
/* configured by driver at initialization, don't touch */
spi_dev_t *hw; ///< Beginning address of the peripheral registers.
/* should be configured by driver at initialization */
lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA.
* The amount should be larger than dmadesc_n. The driver should ensure that
* the data to be sent is shorter than the descriptors can hold.
*/
lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA.
* The amount should be larger than dmadesc_n. The driver should ensure that
* the data to be sent is shorter than the descriptors can hold.
*/
int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use.
/*
* Device specific, all these parameters will be updated to the peripheral
* only when ``spi_hal_setup_device``. They may not get updated when
* ``spi_hal_setup_trans``.
*/
int mode; ///< SPI mode, device specific
int cs_setup; ///< Setup time of CS active edge before the first SPI clock, device specific
int cs_hold; ///< Hold time of CS inactive edge after the last SPI clock, device specific
int cs_pin_id; ///< CS pin to use, 0-2, otherwise all the CS pins are not used. Device specific
spi_hal_timing_conf_t *timing_conf; /**< Pointer to an structure holding
* the pre-calculated timing configuration for the device at initialization,
* device specific
*/
struct {
uint32_t sio : 1; ///< Whether to use SIO mode, device specific
uint32_t half_duplex : 1; ///< Whether half duplex mode is used, device specific
uint32_t tx_lsbfirst : 1; ///< Whether LSB is sent first for TX data, device specific
uint32_t rx_lsbfirst : 1; ///< Whether LSB is received first for RX data, device specific
uint32_t dma_enabled : 1; ///< Whether the DMA is enabled, do not update after initialization
uint32_t no_compensate : 1; ///< No need to add dummy to compensate the timing, device specific
#ifdef SOC_SPI_SUPPORT_AS_CS
uint32_t as_cs : 1; ///< Whether to toggle the CS while the clock toggles, device specific
#endif
uint32_t positive_cs : 1; ///< Whether the postive CS feature is abled, device specific
};//boolean configurations
/*
* Transaction specific (data), all these parameters will be updated to the
* peripheral every transaction.
*/
uint16_t cmd; ///< Command value to be sent
int cmd_bits; ///< Length (in bits) of the command phase
int addr_bits; ///< Length (in bits) of the address phase
int dummy_bits; ///< Base length (in bits) of the dummy phase. Note when the compensation is enabled, some extra dummy bits may be appended.
int tx_bitlen; ///< TX length, in bits
int rx_bitlen; ///< RX length, in bits
uint64_t addr; ///< Address value to be sent
uint8_t *send_buffer; ///< Data to be sent
uint8_t *rcv_buffer; ///< Buffer to hold the receive data.
spi_ll_io_mode_t io_mode; ///< IO mode of the master
} spi_hal_context_t;
/**
* Init the peripheral and the context.
*
* @param hal Context of the HAL layer.
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
*/
void spi_hal_init(spi_hal_context_t *hal, int host_id);
/**
* Deinit the peripheral (and the context if needed).
*
* @param hal Context of the HAL layer.
*/
void spi_hal_deinit(spi_hal_context_t *hal);
/**
* Setup device-related configurations according to the settings in the context.
*
* @param hal Context of the HAL layer.
*/
void spi_hal_setup_device(const spi_hal_context_t *hal);
/**
* Setup transaction related configurations according to the settings in the context.
*
* @param hal Context of the HAL layer.
*/
void spi_hal_setup_trans(const spi_hal_context_t *hal);
/**
* Prepare the data for the current transaction.
*
* @param hal Context of the HAL layer.
*/
void spi_hal_prepare_data(const spi_hal_context_t *hal);
/**
* Trigger start a user-defined transaction.
*
* @param hal Context of the HAL layer.
*/
void spi_hal_user_start(const spi_hal_context_t *hal);
/**
* Check whether the transaction is done (trans_done is set).
*
* @param hal Context of the HAL layer.
*/
bool spi_hal_usr_is_done(const spi_hal_context_t *hal);
/**
* Post transaction operations, mainly fetch data from the buffer.
*
* @param hal Context of the HAL layer.
*/
void spi_hal_fetch_result(const spi_hal_context_t *hal);
/*----------------------------------------------------------
* Utils
* ---------------------------------------------------------*/
/**
* Get the configuration of clock and timing. The configuration will be used when ``spi_hal_setup_device``.
*
* It is highly suggested to do this at initialization, since it takes long time.
*
* @param hal Context of the HAL layer.
* @param speed_hz Desired frequency.
* @param duty_cycle Desired duty cycle of SPI clock
* @param use_gpio true if the GPIO matrix is used, otherwise false
* @param input_delay_ns Maximum delay between SPI launch clock and the data to
* be valid. This is used to compensate/calculate the maximum frequency
* allowed. Left 0 if not known.
* @param out_freq Output of the actual frequency, left NULL if not required.
* @param timing_conf Output of the timing configuration.
*
* @return ESP_OK if desired is available, otherwise fail.
*/
esp_err_t spi_hal_get_clock_conf(const spi_hal_context_t *hal, int speed_hz, int duty_cycle, bool use_gpio, int input_delay_ns, int *out_freq, spi_hal_timing_conf_t *timing_conf);
/**
* Get the frequency actual used.
*
* @param hal Context of the HAL layer.
* @param fapb APB clock frequency.
* @param hz Desired frequencyc.
* @param duty_cycle Desired duty cycle.
*/
int spi_hal_master_cal_clock(int fapb, int hz, int duty_cycle);
/**
* Get the timing configuration for given parameters.
*
* @param eff_clk Actual SPI clock frequency
* @param gpio_is_used true if the GPIO matrix is used, otherwise false.
* @param input_delay_ns Maximum delay between SPI launch clock and the data to
* be valid. This is used to compensate/calculate the maximum frequency
* allowed. Left 0 if not known.
* @param dummy_n Dummy cycles required to correctly read the data.
* @param miso_delay_n suggested delay on the MISO line, in APB clocks.
*/
void spi_hal_cal_timing(int eff_clk, bool gpio_is_used, int input_delay_ns, int *dummy_n, int *miso_delay_n);
/**
* Get the maximum frequency allowed to read if no compensation is used.
*
* @param gpio_is_used true if the GPIO matrix is used, otherwise false.
* @param input_delay_ns Maximum delay between SPI launch clock and the data to
* be valid. This is used to compensate/calculate the maximum frequency
* allowed. Left 0 if not known.
*/
int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns);
tools/sdk/esp32s2/include/soc/include/hal/spi_slave_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for SPI slave (common part)
// SPI slave HAL usages:
// 1. initialize the bus
// 2. initialize the DMA descriptors if DMA used
// 3. call setup_device to update parameters for the device
// 4. prepare data to send, and prepare the receiving buffer
// 5. trigger user defined SPI transaction to start
// 6. wait until the user transaction is done
// 7. store the received data and get the length
// 8. check and reset the DMA (if needed) before the next transaction
#pragma once
#include "soc/lldesc.h"
#include "soc/spi_struct.h"
#include <esp_types.h>
#include "soc/spi_caps.h"
/**
* Context that should be maintained by both the driver and the HAL.
*/
typedef struct {
/* configured by driver at initialization, don't touch */
spi_dev_t *hw; ///< Beginning address of the peripheral registers.
/* should be configured by driver at initialization */
lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the TX DMA.
* The amount should be larger than dmadesc_n. The driver should ensure that
* the data to be sent is shorter than the descriptors can hold.
*/
lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the RX DMA.
* The amount should be larger than dmadesc_n. The driver should ensure that
* the data to be sent is shorter than the descriptors can hold.
*/
int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use.
/*
* configurations to be filled after ``spi_slave_hal_init``. Updated to
* peripheral registers when ``spi_slave_hal_setup_device`` is called.
*/
struct {
uint32_t rx_lsbfirst : 1;
uint32_t tx_lsbfirst : 1;
uint32_t use_dma : 1;
};
int mode;
/*
* Transaction specific (data), all these parameters will be updated to the
* peripheral every transaction.
*/
uint32_t bitlen; ///< Expected maximum length of the transaction, in bits.
const void *tx_buffer; ///< Data to be sent
void *rx_buffer; ///< Buffer to hold the received data.
/* Other transaction result after one transaction */
uint32_t rcv_bitlen; ///< Length of the last transaction, in bits.
} spi_slave_hal_context_t;
/**
* Init the peripheral and the context.
*
* @param hal Context of the HAL layer.
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
*/
void spi_slave_hal_init(spi_slave_hal_context_t *hal, int host_id);
/**
* Deinit the peripheral (and the context if needed).
*
* @param hal Context of the HAL layer.
*/
void spi_slave_hal_deinit(spi_slave_hal_context_t *hal);
/**
* Setup device-related configurations according to the settings in the context.
*
* @param hal Context of the HAL layer.
*/
void spi_slave_hal_setup_device(const spi_slave_hal_context_t *hal);
/**
* Prepare the data for the current transaction.
*
* @param hal Context of the HAL layer.
*/
void spi_slave_hal_prepare_data(const spi_slave_hal_context_t *hal);
/**
* Trigger start a user-defined transaction.
*
* @param hal Context of the HAL layer.
*/
void spi_slave_hal_user_start(const spi_slave_hal_context_t *hal);
/**
* Check whether the transaction is done (trans_done is set).
*
* @param hal Context of the HAL layer.
*/
bool spi_slave_hal_usr_is_done(spi_slave_hal_context_t* hal);
/**
* Post transaction operations, fetch data from the buffer and recored the length.
*
* @param hal Context of the HAL layer.
*/
void spi_slave_hal_store_result(spi_slave_hal_context_t *hal);
/**
* Get the length of last transaction, in bits. Should be called after ``spi_slave_hal_store_result``.
*
* Note that if last transaction is longer than configured before, the return
* value will be truncated to the configured length.
*
* @param hal Context of the HAL layer.
*
* @return Length of the last transaction, in bits.
*/
uint32_t spi_slave_hal_get_rcv_bitlen(spi_slave_hal_context_t *hal);
/**
* Check whether we need to reset the DMA according to the status of last transactions.
*
* In ESP32, sometimes we may need to reset the DMA for the slave before the
* next transaction. Call this to check it.
*
* @param hal Context of the HAL layer.
*
* @return true if reset is needed, else false.
*/
bool spi_slave_hal_dma_need_reset(const spi_slave_hal_context_t *hal);
tools/sdk/esp32s2/include/soc/include/hal/spi_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/spi_caps.h"
#include "sdkconfig.h"
/**
* @brief Enum with the three SPI peripherals that are software-accessible in it
*/
typedef enum {
// SPI_HOST (SPI1_HOST) is not supported by the SPI Master and SPI Slave driver on ESP32-S2
SPI1_HOST=0, ///< SPI1
SPI2_HOST=1, ///< SPI2
SPI3_HOST=2, ///< SPI3
} spi_host_device_t;
//alias for different chips
#ifdef CONFIG_IDF_TARGET_ESP32
#define SPI_HOST SPI1_HOST
#define HSPI_HOST SPI2_HOST
#define VSPI_HOST SPI3_HOST
#elif CONFIG_IDF_TARGET_ESP32S2
// SPI_HOST (SPI1_HOST) is not supported by the SPI Master and SPI Slave driver on ESP32-S2
#define SPI_HOST SPI1_HOST
#define FSPI_HOST SPI2_HOST
#define HSPI_HOST SPI3_HOST
#endif
tools/sdk/esp32s2/include/soc/include/hal/systimer_hal.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "hal/systimer_types.h"
/**
* @brief enable systimer counter
*/
void systimer_hal_enable_counter(systimer_counter_id_t counter_id);
/**
* @brief get current counter value
*/
uint64_t systimer_hal_get_counter_value(systimer_counter_id_t counter_id);
/**
* @brief get current time (in microseconds)
*/
uint64_t systimer_hal_get_time(systimer_counter_id_t counter_id);
/**
* @brief set alarm time
*/
void systimer_hal_set_alarm_value(systimer_alarm_id_t alarm_id, uint64_t timestamp);
/**
* @brief get alarm time
*/
uint64_t systimer_hal_get_alarm_value(systimer_alarm_id_t alarm_id);
/**
* @brief enable alarm interrupt
*/
void systimer_hal_enable_alarm_int(systimer_alarm_id_t alarm_id);
/**
* @brief select alarm mode
*/
void systimer_hal_select_alarm_mode(systimer_alarm_id_t alarm_id, systimer_alarm_mode_t mode);
/**
* @brief update systimer step when apb clock gets changed
*/
void systimer_hal_on_apb_freq_update(uint32_t apb_ticks_per_us);
/**
* @brief move systimer counter value forward or backward
*/
void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_t time_us);
/**
* @brief initialize systimer in HAL layer
*/
void systimer_hal_init(void);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/systimer_types.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc/systimer_caps.h"
/*
* @brief The structure of the counter value in systimer
*
*/
typedef struct {
union {
struct {
uint64_t lo : SOC_SYSTIMER_BIT_WIDTH_LO; /*!< Low part of counter value */
uint64_t hi : SOC_SYSTIMER_BIT_WIDTH_HI; /*!< High part of counter value */
};
uint64_t val; /*!< counter value */
};
} systimer_counter_value_t;
/** @cond */
_Static_assert(sizeof(systimer_counter_value_t) == 8, "systimer_counter_value_t should occupy 8 bytes in memory");
/** @endcond */
/**
* @brief systimer counter ID
*
*/
typedef enum {
SYSTIMER_COUNTER_0, /*!< systimer counter 0 */
#if SOC_SYSTIMER_COUNTER_NUM > 1
SYSTIEMR_COUNTER_1, /*!< systimer counter 1 */
#endif
} systimer_counter_id_t;
/**
* @brief systimer alarm ID
*
*/
typedef enum {
SYSTIMER_ALARM_0, /*!< systimer alarm 0 */
SYSTIMER_ALARM_1, /*!< systimer alarm 1 */
SYSTIMER_ALARM_2, /*!< systimer alarm 2 */
} systimer_alarm_id_t;
/**
* @brief systimer alarm mode
*
*/
typedef enum {
SYSTIMER_ALARM_MODE_ONESHOT, /*!< systimer alarm oneshot mode */
SYSTIMER_ALARM_MODE_PERIOD, /*!< systimer alarm period mode */
} systimer_alarm_mode_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/timer_hal.h
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for Timer Group.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "hal/timer_ll.h"
#include "hal/timer_types.h"
#include "soc/timer_group_caps.h"
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
timg_dev_t *dev;
timer_idx_t idx;
} timer_hal_context_t;
/**
* @brief Init the timer hal. This function should be called first before other hal layer function is called
*
* @param hal Context of the HAL layer
* @param group_num The timer group number
* @param timer_num The timer number
*
* @return None
*/
void timer_hal_init(timer_hal_context_t *hal, timer_group_t group_num, timer_idx_t timer_num);
/**
* @brief Get interrupt status register address and corresponding control bits mask
*
* @param hal Context of the HAL layer
* @param status_reg[out] interrupt status register address
* @param mask_bit[out] control bits mask
*/
void timer_hal_get_status_reg_mask_bit(timer_hal_context_t *hal, uint32_t *status_reg, uint32_t *mask_bit);
/**
* @brief Set timer clock prescale value
*
* @param hal Context of the HAL layer
* @param divider Prescale value
*
* @return None
*/
#define timer_hal_set_divider(hal, divider) timer_ll_set_divider((hal)->dev, (hal)->idx, divider)
/**
* @brief Get timer clock prescale value
*
* @param hal Context of the HAL layer
* @param divider Pointer to accept the prescale value
*
* @return None
*/
#define timer_hal_get_divider(hal, divider) timer_ll_get_divider((hal)->dev, (hal)->idx, divider)
/**
* @brief Load counter value into time-base counter
*
* @param hal Context of the HAL layer
* @param load_val Counter value
*
* @return None
*/
#define timer_hal_set_counter_value(hal, load_val) timer_ll_set_counter_value((hal)->dev, (hal)->idx, load_val)
/**
* @brief Get counter value from time-base counter
*
* @param hal Context of the HAL layer
* @param timer_val Pointer to accept the counter value
*
* @return None
*/
#define timer_hal_get_counter_value(hal, timer_val) timer_ll_get_counter_value((hal)->dev, (hal)->idx, timer_val)
/**
* @brief Set counter mode, include increment mode and decrement mode.
*
* @param hal Context of the HAL layer
* @param increase_en True to increment mode, fasle to decrement mode
*
* @return None
*/
#define timer_hal_set_counter_increase(hal, increase_en) timer_ll_set_counter_increase((hal)->dev, (hal)->idx, increase_en)
/**
* @brief Get counter mode, include increment mode and decrement mode.
*
* @param hal Context of the HAL layer
* @param counter_dir Pointer to accept the counter mode
*
* @return
* - true Increment mode
* - false Decrement mode
*/
#define timer_hal_get_counter_increase(hal) timer_ll_get_counter_increase((hal)->dev, (hal)->idx)
/**
* @brief Set counter status, enable or disable counter.
*
* @param hal Context of the HAL layer
* @param counter_en True to enable counter, false to disable counter
*
* @return None
*/
#define timer_hal_set_counter_enable(hal, counter_en) timer_ll_set_counter_enable((hal)->dev, (hal)->idx, counter_en)
/**
* @brief Get counter status.
*
* @param hal Context of the HAL layer
*
* @return
* - true Enable counter
* - false Disable conuter
*/
#define timer_hal_get_counter_enable(hal) timer_ll_get_counter_enable((hal)->dev, (hal)->idx)
/**
* @brief Set auto reload mode.
*
* @param hal Context of the HAL layer
* @param auto_reload_en True to enable auto reload mode, flase to disable auto reload mode
*
* @return None
*/
#define timer_hal_set_auto_reload(hal, auto_reload_en) timer_ll_set_auto_reload((hal)->dev, (hal)->idx, auto_reload_en)
/**
* @brief Get auto reload mode.
*
* @param hal Context of the HAL layer
*
* @return
* - true Enable auto reload mode
* - false Disable auto reload mode
*/
#define timer_hal_get_auto_reload(hal) timer_ll_get_auto_reload((hal)->dev, (hal)->idx)
/**
* @brief Set the counter value to trigger the alarm.
*
* @param hal Context of the HAL layer
* @param alarm_value Counter value to trigger the alarm
*
* @return None
*/
#define timer_hal_set_alarm_value(hal, alarm_value) timer_ll_set_alarm_value((hal)->dev, (hal)->idx, alarm_value)
/**
* @brief Get the counter value to trigger the alarm.
*
* @param hal Context of the HAL layer
* @param alarm_value Pointer to accept the counter value to trigger the alarm
*
* @return None
*/
#define timer_hal_get_alarm_value(hal, alarm_value) timer_ll_get_alarm_value((hal)->dev, (hal)->idx, alarm_value)
/**
* @brief Set the alarm status, enable or disable the alarm.
*
* @param hal Context of the HAL layer
* @param alarm_en True to enable alarm, false to disable alarm
*
* @return None
*/
#define timer_hal_set_alarm_enable(hal, alarm_en) timer_ll_set_alarm_enable((hal)->dev, (hal)->idx, alarm_en)
/**
* @brief Get the alarm status.
*
* @param hal Context of the HAL layer
*
* @return
* - true Enable alarm
* - false Disable alarm
*/
#define timer_hal_get_alarm_enable(hal) timer_ll_get_alarm_enable((hal)->dev, (hal)->idx)
/**
* @brief Set the level interrupt status, enable or disable the level interrupt.
*
* @param hal Context of the HAL layer
* @param level_int_en True to enable level interrupt, false to disable level interrupt
*
* @return None
*/
#define timer_hal_set_level_int_enable(hal, level_int_en) timer_ll_set_level_int_enable((hal)->dev, (hal)->idx, level_int_en)
/**
* @brief Get the level interrupt status.
*
* @param hal Context of the HAL layer
*
* @return
* - true Enable level interrupt
* - false Disable level interrupt
*/
#define timer_hal_get_level_int_enable(hal) timer_ll_get_level_int_enable((hal)->dev, (hal)->idx)
/**
* @brief Set the edge interrupt status, enable or disable the edge interrupt.
*
* @param hal Context of the HAL layer
* @param edge_int_en True to enable edge interrupt, false to disable edge interrupt
*
* @return None
*/
#define timer_hal_set_edge_int_enable(hal, edge_int_en) timer_ll_set_edge_int_enable((hal)->dev, (hal)->idx, edge_int_en)
/**
* @brief Get the edge interrupt status.
*
* @param hal Context of the HAL layer
*
* @return
* - true Enable edge interrupt
* - false Disable edge interrupt
*/
#define timer_hal_get_edge_int_enable(hal) timer_ll_get_edge_int_enable((hal)->dev, (hal)->idx)
/**
* @brief Enable timer interrupt.
*
* @param hal Context of the HAL layer
*
* @return None
*/
#define timer_hal_intr_enable(hal) timer_ll_intr_enable((hal)->dev, (hal)->idx)
/**
* @brief Disable timer interrupt.
*
* @param hal Context of the HAL layer
*
* @return None
*/
#define timer_hal_intr_disable(hal) timer_ll_intr_disable((hal)->dev, (hal)->idx)
/**
* @brief Clear interrupt status.
*
* @param hal Context of the HAL layer
*
* @return None
*/
#define timer_hal_clear_intr_status(hal) timer_ll_clear_intr_status((hal)->dev, (hal)->idx)
/**
* @brief Get interrupt status.
*
* @param hal Context of the HAL layer
* @param intr_status Interrupt status
*
* @return None
*/
#define timer_hal_get_intr_status(hal, intr_status) timer_ll_get_intr_status((hal)->dev, intr_status)
/**
* @brief Get interrupt raw status.
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
* @param intr_raw_status Interrupt raw status
*
* @return None
*/
#define timer_hal_get_intr_raw_status(group_num, intr_raw_status) timer_ll_get_intr_raw_status(group_num, intr_raw_status)
/**
* @brief Get interrupt status register address.
*
* @param hal Context of the HAL layer
*
* @return Interrupt status register address
*/
#define timer_hal_get_intr_status_reg(hal) timer_ll_get_intr_status_reg((hal)->dev)
#ifdef SOC_TIMER_GROUP_SUPPORT_XTAL
/**
* @brief Set clock source.
*
* @param hal Context of the HAL layer
* @param use_xtal_en True to use XTAL clock, flase to use APB clock
*
* @return None
*/
#define timer_hal_set_use_xtal(hal, use_xtal_en) timer_ll_set_use_xtal((hal)->dev, (hal)->idx, use_xtal_en)
/**
* @brief Get clock source.
*
* @param hal Context of the HAL layer
*
* @return
* - true Use XTAL clock
* - false Use APB clock
*/
#define timer_hal_get_use_xtal(hal) timer_ll_get_use_xtal((hal)->dev, (hal)->idx)
#endif
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/timer_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include <esp_bit_defs.h>
#include "soc/timer_group_caps.h"
#include "esp_attr.h"
/**
* @brief Selects a Timer-Group out of 2 available groups
*/
typedef enum {
TIMER_GROUP_0 = 0, /*!<Hw timer group 0*/
TIMER_GROUP_1 = 1, /*!<Hw timer group 1*/
TIMER_GROUP_MAX,
} timer_group_t;
/**
* @brief Select a hardware timer from timer groups
*/
typedef enum {
TIMER_0 = 0, /*!<Select timer0 of GROUPx*/
TIMER_1 = 1, /*!<Select timer1 of GROUPx*/
TIMER_MAX,
} timer_idx_t;
/**
* @brief Decides the direction of counter
*/
typedef enum {
TIMER_COUNT_DOWN = 0, /*!< Descending Count from cnt.high|cnt.low*/
TIMER_COUNT_UP = 1, /*!< Ascending Count from Zero*/
TIMER_COUNT_MAX
} timer_count_dir_t;
/**
* @brief Decides whether timer is on or paused
*/
typedef enum {
TIMER_PAUSE = 0, /*!<Pause timer counter*/
TIMER_START = 1, /*!<Start timer counter*/
} timer_start_t;
/**
* @brief Interrupt types of the timer.
*/
//this is compatible with the value of esp32.
typedef enum {
TIMER_INTR_T0 = BIT(0), /*!< interrupt of timer 0 */
TIMER_INTR_T1 = BIT(1), /*!< interrupt of timer 1 */
TIMER_INTR_WDT = BIT(2), /*!< interrupt of watchdog */
TIMER_INTR_NONE = 0
} timer_intr_t;
FLAG_ATTR(timer_intr_t)
/**
* @brief Decides whether to enable alarm mode
*/
typedef enum {
TIMER_ALARM_DIS = 0, /*!< Disable timer alarm*/
TIMER_ALARM_EN = 1, /*!< Enable timer alarm*/
TIMER_ALARM_MAX
} timer_alarm_t;
/**
* @brief Select interrupt type if running in alarm mode.
*/
typedef enum {
TIMER_INTR_LEVEL = 0, /*!< Interrupt mode: level mode*/
//TIMER_INTR_EDGE = 1, /*!< Interrupt mode: edge mode, Not supported Now*/
TIMER_INTR_MAX
} timer_intr_mode_t;
/**
* @brief Select if Alarm needs to be loaded by software or automatically reload by hardware.
*/
typedef enum {
TIMER_AUTORELOAD_DIS = 0, /*!< Disable auto-reload: hardware will not load counter value after an alarm event*/
TIMER_AUTORELOAD_EN = 1, /*!< Enable auto-reload: hardware will load counter value after an alarm event*/
TIMER_AUTORELOAD_MAX,
} timer_autoreload_t;
#ifdef SOC_TIMER_GROUP_SUPPORT_XTAL
/**
* @brief Select timer source clock.
*/
typedef enum {
TIMER_SRC_CLK_APB = 0, /*!< Select APB as the source clock*/
TIMER_SRC_CLK_XTAL = 1, /*!< Select XTAL as the source clock*/
} timer_src_clk_t;
#endif
/**
* @brief Data structure with timer's configuration settings
*/
typedef struct {
timer_alarm_t alarm_en; /*!< Timer alarm enable */
timer_start_t counter_en; /*!< Counter enable */
timer_intr_mode_t intr_type; /*!< Interrupt mode */
timer_count_dir_t counter_dir; /*!< Counter direction */
timer_autoreload_t auto_reload; /*!< Timer auto-reload */
uint32_t divider; /*!< Counter clock divider. The divider's range is from from 2 to 65536. */
#ifdef SOC_TIMER_GROUP_SUPPORT_XTAL
timer_src_clk_t clk_src; /*!< Use XTAL as source clock. */
#endif
} timer_config_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/touch_sensor_hal.h
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for touch sensor (common part)
#pragma once
#include "hal/touch_sensor_ll.h"
#include "hal/touch_sensor_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
touch_high_volt_t refh;
touch_low_volt_t refl;
touch_volt_atten_t atten;
} touch_hal_volt_t;
typedef struct {
touch_cnt_slope_t slope; /*!<Set touch sensor charge/discharge speed(currents) for each pad.*/
touch_tie_opt_t tie_opt; /*!<Set initial voltage state of touch channel for each measurement.*/
} touch_hal_meas_mode_t;
/**
* Set touch sensor sleep time (interval of measurement).
*
* @param sleep_time The touch sensor will sleep after each measurement.
* sleep_cycle decide the interval between each measurement.
* t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency).
* The approximate frequency value of RTC_SLOW_CLK can be obtained using `rtc_clk_slow_freq_get_hz` function.
*/
#define touch_hal_set_sleep_time(sleep_time) touch_ll_set_sleep_time(sleep_time)
/**
* Get touch sensor sleep time.
*
* @param sleep_time Pointer to accept sleep cycle count.
*/
#define touch_hal_get_sleep_time(sleep_time) touch_ll_get_sleep_time(sleep_time)
/**
* Set touch sensor high / low voltage threshold of chanrge.
* The touch sensor measures the channel capacitance value by charging and discharging the channel.
* So charge threshold should be less than the supply voltage.
* The actual charge threshold is high voltage threshold minus attenuation value.
*
* @param refh The high voltage threshold of chanrge.
*/
void touch_hal_set_voltage(const touch_hal_volt_t *volt);
/**
* Get touch sensor high / low voltage threshold of chanrge.
* The touch sensor measures the channel capacitance value by charging and discharging the channel.
* So charge threshold should be less than the supply voltage.
* The actual charge threshold is high voltage threshold minus attenuation value.
*
* @param refh The voltage threshold of chanrge / discharge.
*/
void touch_hal_get_voltage(touch_hal_volt_t *volt);
/**
* Set touch sensor charge/discharge speed(currents) and initial voltage state for each pad measurement.
*
* @param touch_num Touch pad index.
* @param meas Touch pad measurement config.
*/
void touch_hal_set_meas_mode(touch_pad_t touch_num, const touch_hal_meas_mode_t *meas);
/**
* Get touch sensor charge/discharge speed(currents) and initial voltage state for each pad measurement.
*
* @param touch_num Touch pad index.
* @param meas Touch pad measurement config.
*/
void touch_hal_get_meas_mode(touch_pad_t touch_num, touch_hal_meas_mode_t *meas);
/**
* Set touch sensor FSM mode.
* The measurement action can be triggered by the hardware timer, as well as by the software instruction.
*
* @param mode FSM mode.
*/
#define touch_hal_set_fsm_mode(mode) touch_ll_set_fsm_mode(mode)
/**
* Get touch sensor FSM mode.
* The measurement action can be triggered by the hardware timer, as well as by the software instruction.
*
* @param mode FSM mode.
*/
#define touch_hal_get_fsm_mode(mode) touch_ll_get_fsm_mode(mode)
/**
* Start touch sensor FSM timer.
* The measurement action can be triggered by the hardware timer, as well as by the software instruction.
*/
#define touch_hal_start_fsm() touch_ll_start_fsm()
/**
* Stop touch sensor FSM timer.
* The measurement action can be triggered by the hardware timer, as well as by the software instruction.
*/
#define touch_hal_stop_fsm() touch_ll_stop_fsm()
/**
* Trigger a touch sensor measurement, only support in SW mode of FSM.
*/
#define touch_hal_start_sw_meas() touch_ll_start_sw_meas()
/**
* Set touch sensor interrupt threshold.
*
* @note Refer to `touch_pad_set_trigger_mode` to see how to set trigger mode.
* @param touch_num touch pad index.
* @param threshold threshold of touchpad count.
*/
#define touch_hal_set_threshold(touch_num, threshold) touch_ll_set_threshold(touch_num, threshold)
/**
* Get touch sensor interrupt threshold.
*
* @param touch_num touch pad index.
* @param threshold pointer to accept threshold.
*/
#define touch_hal_get_threshold(touch_num, threshold) touch_ll_get_threshold(touch_num, threshold)
/**
* Enable touch sensor channel. Register touch channel into touch sensor measurement group.
* The working mode of the touch sensor is simultaneous measurement.
* This function will set the measure bits according to the given bitmask.
*
* @note If set this mask, the FSM timer should be stop firsty.
* @note The touch sensor that in scan map, should be deinit GPIO function firstly.
* @param enable_mask bitmask of touch sensor scan group.
* e.g. TOUCH_PAD_NUM1 -> BIT(1)
* @return
* - ESP_OK on success
*/
#define touch_hal_set_channel_mask(enable_mask) touch_ll_set_channel_mask(enable_mask)
/**
* Get touch sensor channel mask.
*
* @param enable_mask bitmask of touch sensor scan group.
* e.g. TOUCH_PAD_NUM1 -> BIT(1)
*/
#define touch_hal_get_channel_mask(enable_mask) touch_ll_get_channel_mask(enable_mask)
/**
* Disable touch sensor channel by bitmask.
*
* @param enable_mask bitmask of touch sensor scan group.
* e.g. TOUCH_PAD_NUM1 -> BIT(1)
*/
#define touch_hal_clear_channel_mask(disable_mask) touch_ll_clear_channel_mask(disable_mask)
/**
* Get the touch sensor status, usually used in ISR to decide which pads are 'touched'.
*
* @param status_mask The touch sensor status. e.g. Touch1 trigger status is `status_mask & (BIT1)`.
*/
#define touch_hal_read_trigger_status_mask(status_mask) touch_ll_read_trigger_status_mask(status_mask)
/**
* Clear all touch sensor status.
*/
#define touch_hal_clear_trigger_status_mask() touch_ll_clear_trigger_status_mask()
/**
* Get touch sensor raw data (touch sensor counter value) from register. No block.
*
* @param touch_num touch pad index.
* @return touch_value pointer to accept touch sensor value.
*/
#define touch_hal_read_raw_data(touch_num) touch_ll_read_raw_data(touch_num)
/**
* Get touch sensor measure status. No block.
*
* @return
* - If touch sensors measure done.
*/
#define touch_hal_meas_is_done() touch_ll_meas_is_done()
/**
* Initialize touch module.
*
* @note If default parameter don't match the usage scenario, it can be changed after this function.
*/
void touch_hal_init(void);
/**
* Un-install touch pad driver.
*
* @note After this function is called, other touch functions are prohibited from being called.
*/
void touch_hal_deinit(void);
/**
* Configure touch sensor for each channel.
*/
void touch_hal_config(touch_pad_t touch_num);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/touch_sensor_types.h
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/touch_sensor_caps.h"
#include "sdkconfig.h"
#include "esp_attr.h"
/** Touch pad channel */
typedef enum {
TOUCH_PAD_NUM0 = 0, /*!< Touch pad channel 0 is GPIO4(ESP32) */
TOUCH_PAD_NUM1, /*!< Touch pad channel 1 is GPIO0(ESP32) / GPIO1(ESP32-S2) */
TOUCH_PAD_NUM2, /*!< Touch pad channel 2 is GPIO2(ESP32) / GPIO2(ESP32-S2) */
TOUCH_PAD_NUM3, /*!< Touch pad channel 3 is GPIO15(ESP32) / GPIO3(ESP32-S2) */
TOUCH_PAD_NUM4, /*!< Touch pad channel 4 is GPIO13(ESP32) / GPIO4(ESP32-S2) */
TOUCH_PAD_NUM5, /*!< Touch pad channel 5 is GPIO12(ESP32) / GPIO5(ESP32-S2) */
TOUCH_PAD_NUM6, /*!< Touch pad channel 6 is GPIO14(ESP32) / GPIO6(ESP32-S2) */
TOUCH_PAD_NUM7, /*!< Touch pad channel 7 is GPIO27(ESP32) / GPIO7(ESP32-S2) */
TOUCH_PAD_NUM8, /*!< Touch pad channel 8 is GPIO33(ESP32) / GPIO8(ESP32-S2) */
TOUCH_PAD_NUM9, /*!< Touch pad channel 9 is GPIO32(ESP32) / GPIO9(ESP32-S2) */
#if SOC_TOUCH_SENSOR_NUM > 10
TOUCH_PAD_NUM10, /*!< Touch channel 10 is GPIO10(ESP32-S2) */
TOUCH_PAD_NUM11, /*!< Touch channel 11 is GPIO11(ESP32-S2) */
TOUCH_PAD_NUM12, /*!< Touch channel 12 is GPIO12(ESP32-S2) */
TOUCH_PAD_NUM13, /*!< Touch channel 13 is GPIO13(ESP32-S2) */
TOUCH_PAD_NUM14, /*!< Touch channel 14 is GPIO14(ESP32-S2) */
#endif
TOUCH_PAD_MAX,
} touch_pad_t;
/** Touch sensor high reference voltage */
typedef enum {
TOUCH_HVOLT_KEEP = -1, /*!<Touch sensor high reference voltage, no change */
TOUCH_HVOLT_2V4 = 0, /*!<Touch sensor high reference voltage, 2.4V */
TOUCH_HVOLT_2V5, /*!<Touch sensor high reference voltage, 2.5V */
TOUCH_HVOLT_2V6, /*!<Touch sensor high reference voltage, 2.6V */
TOUCH_HVOLT_2V7, /*!<Touch sensor high reference voltage, 2.7V */
TOUCH_HVOLT_MAX,
} touch_high_volt_t;
/** Touch sensor low reference voltage */
typedef enum {
TOUCH_LVOLT_KEEP = -1, /*!<Touch sensor low reference voltage, no change */
TOUCH_LVOLT_0V5 = 0, /*!<Touch sensor low reference voltage, 0.5V */
TOUCH_LVOLT_0V6, /*!<Touch sensor low reference voltage, 0.6V */
TOUCH_LVOLT_0V7, /*!<Touch sensor low reference voltage, 0.7V */
TOUCH_LVOLT_0V8, /*!<Touch sensor low reference voltage, 0.8V */
TOUCH_LVOLT_MAX,
} touch_low_volt_t;
/** Touch sensor high reference voltage attenuation */
typedef enum {
TOUCH_HVOLT_ATTEN_KEEP = -1, /*!<Touch sensor high reference voltage attenuation, no change */
TOUCH_HVOLT_ATTEN_1V5 = 0, /*!<Touch sensor high reference voltage attenuation, 1.5V attenuation */
TOUCH_HVOLT_ATTEN_1V, /*!<Touch sensor high reference voltage attenuation, 1.0V attenuation */
TOUCH_HVOLT_ATTEN_0V5, /*!<Touch sensor high reference voltage attenuation, 0.5V attenuation */
TOUCH_HVOLT_ATTEN_0V, /*!<Touch sensor high reference voltage attenuation, 0V attenuation */
TOUCH_HVOLT_ATTEN_MAX,
} touch_volt_atten_t;
/** Touch sensor charge/discharge speed */
typedef enum {
TOUCH_PAD_SLOPE_0 = 0, /*!<Touch sensor charge / discharge speed, always zero */
TOUCH_PAD_SLOPE_1 = 1, /*!<Touch sensor charge / discharge speed, slowest */
TOUCH_PAD_SLOPE_2 = 2, /*!<Touch sensor charge / discharge speed */
TOUCH_PAD_SLOPE_3 = 3, /*!<Touch sensor charge / discharge speed */
TOUCH_PAD_SLOPE_4 = 4, /*!<Touch sensor charge / discharge speed */
TOUCH_PAD_SLOPE_5 = 5, /*!<Touch sensor charge / discharge speed */
TOUCH_PAD_SLOPE_6 = 6, /*!<Touch sensor charge / discharge speed */
TOUCH_PAD_SLOPE_7 = 7, /*!<Touch sensor charge / discharge speed, fast */
TOUCH_PAD_SLOPE_MAX,
} touch_cnt_slope_t;
/** Touch sensor initial charge level */
typedef enum {
TOUCH_PAD_TIE_OPT_LOW = 0, /*!<Initial level of charging voltage, low level */
TOUCH_PAD_TIE_OPT_HIGH = 1, /*!<Initial level of charging voltage, high level */
TOUCH_PAD_TIE_OPT_MAX,
} touch_tie_opt_t;
/** Touch sensor FSM mode */
typedef enum {
TOUCH_FSM_MODE_TIMER = 0, /*!<To start touch FSM by timer */
TOUCH_FSM_MODE_SW, /*!<To start touch FSM by software trigger */
TOUCH_FSM_MODE_MAX,
} touch_fsm_mode_t;
/**** ESP32 Only *****/
typedef enum {
TOUCH_TRIGGER_BELOW = 0, /*!<Touch interrupt will happen if counter value is less than threshold.*/
TOUCH_TRIGGER_ABOVE = 1, /*!<Touch interrupt will happen if counter value is larger than threshold.*/
TOUCH_TRIGGER_MAX,
} touch_trigger_mode_t;
typedef enum {
TOUCH_TRIGGER_SOURCE_BOTH = 0, /*!< wakeup interrupt is generated if both SET1 and SET2 are "touched"*/
TOUCH_TRIGGER_SOURCE_SET1 = 1, /*!< wakeup interrupt is generated if SET1 is "touched"*/
TOUCH_TRIGGER_SOURCE_MAX,
} touch_trigger_src_t;
/********************************/
#define TOUCH_PAD_SLOPE_DEFAULT (TOUCH_PAD_SLOPE_7)
#define TOUCH_PAD_TIE_OPT_DEFAULT (TOUCH_PAD_TIE_OPT_LOW)
#define TOUCH_PAD_BIT_MASK_MAX (SOC_TOUCH_SENSOR_BIT_MASK_MAX)
#define TOUCH_PAD_HIGH_VOLTAGE_THRESHOLD (TOUCH_HVOLT_2V7)
#define TOUCH_PAD_LOW_VOLTAGE_THRESHOLD (TOUCH_LVOLT_0V5)
#define TOUCH_PAD_ATTEN_VOLTAGE_THRESHOLD (TOUCH_HVOLT_ATTEN_0V5)
#define TOUCH_PAD_IDLE_CH_CONNECT_DEFAULT (TOUCH_PAD_CONN_GND)
#define TOUCH_PAD_THRESHOLD_MAX (SOC_TOUCH_PAD_THRESHOLD_MAX) /*!<If set touch threshold max value, The touch sensor can't be in touched status */
#ifdef CONFIG_IDF_TARGET_ESP32
#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT (0x1000) /*!<The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options), max value is 0xffff */
#define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (0x7fff) /*!<The timer frequency is 8Mhz, the max value is 0x7fff */
#define TOUCH_FSM_MODE_DEFAULT (TOUCH_FSM_MODE_SW) /*!<The touch FSM my be started by the software or timer */
#define TOUCH_TRIGGER_MODE_DEFAULT (TOUCH_TRIGGER_BELOW) /*!<Interrupts can be triggered if sensor value gets below or above threshold */
#define TOUCH_TRIGGER_SOURCE_DEFAULT (TOUCH_TRIGGER_SOURCE_SET1) /*!<The wakeup trigger source can be SET1 or both SET1 and SET2 */
#elif CONFIG_IDF_TARGET_ESP32S2
/**
* Excessive total time will slow down the touch response.
* Too small measurement time will not be sampled enough, resulting in inaccurate measurements.
*
* @note The greater the duty cycle of the measurement time, the more system power is consumed.
*/
#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT (0xf) /*!<The number of sleep cycle in each measure process of touch channels.
The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options).
Range: 0 ~ 0xffff */
#define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (500) /*!<The times of charge and discharge in each measure process of touch channels.
The timer frequency is 8Mhz.
Recommended typical value: Modify this value to make the measurement time around 1ms.
Range: 0 ~ 0xffff */
#endif // CONFIG_IDF_TARGET_ESP32
#ifdef CONFIG_IDF_TARGET_ESP32S2
typedef enum {
TOUCH_PAD_INTR_MASK_DONE = BIT(0), /*!<Measurement done for one of the enabled channels. */
TOUCH_PAD_INTR_MASK_ACTIVE = BIT(1), /*!<Active for one of the enabled channels. */
TOUCH_PAD_INTR_MASK_INACTIVE = BIT(2), /*!<Inactive for one of the enabled channels. */
TOUCH_PAD_INTR_MASK_SCAN_DONE = BIT(3), /*!<Measurement done for all the enabled channels. */
TOUCH_PAD_INTR_MASK_TIMEOUT = BIT(4), /*!<Timeout for one of the enabled channels. */
TOUCH_PAD_INTR_MASK_MAX
#define TOUCH_PAD_INTR_MASK_ALL (TOUCH_PAD_INTR_MASK_TIMEOUT \
| TOUCH_PAD_INTR_MASK_SCAN_DONE \
| TOUCH_PAD_INTR_MASK_INACTIVE \
| TOUCH_PAD_INTR_MASK_ACTIVE \
| TOUCH_PAD_INTR_MASK_DONE) /*!<All touch interrupt type enable. */
} touch_pad_intr_mask_t;
FLAG_ATTR(touch_pad_intr_mask_t)
typedef enum {
TOUCH_PAD_DENOISE_BIT12 = 0, /*!<Denoise range is 12bit */
TOUCH_PAD_DENOISE_BIT10 = 1, /*!<Denoise range is 10bit */
TOUCH_PAD_DENOISE_BIT8 = 2, /*!<Denoise range is 8bit */
TOUCH_PAD_DENOISE_BIT4 = 3, /*!<Denoise range is 4bit */
TOUCH_PAD_DENOISE_MAX
} touch_pad_denoise_grade_t;
typedef enum {
TOUCH_PAD_DENOISE_CAP_L0 = 0, /*!<Denoise channel internal reference capacitance is 5pf */
TOUCH_PAD_DENOISE_CAP_L1 = 1, /*!<Denoise channel internal reference capacitance is 6.4pf */
TOUCH_PAD_DENOISE_CAP_L2 = 2, /*!<Denoise channel internal reference capacitance is 7.8pf */
TOUCH_PAD_DENOISE_CAP_L3 = 3, /*!<Denoise channel internal reference capacitance is 9.2pf */
TOUCH_PAD_DENOISE_CAP_L4 = 4, /*!<Denoise channel internal reference capacitance is 10.6pf */
TOUCH_PAD_DENOISE_CAP_L5 = 5, /*!<Denoise channel internal reference capacitance is 12.0pf */
TOUCH_PAD_DENOISE_CAP_L6 = 6, /*!<Denoise channel internal reference capacitance is 13.4pf */
TOUCH_PAD_DENOISE_CAP_L7 = 7, /*!<Denoise channel internal reference capacitance is 14.8pf */
TOUCH_PAD_DENOISE_CAP_MAX = 8
} touch_pad_denoise_cap_t;
/** Touch sensor denoise configuration */
typedef struct touch_pad_denoise {
touch_pad_denoise_grade_t grade; /*!<Select denoise range of denoise channel.
Determined by measuring the noise amplitude of the denoise channel. */
touch_pad_denoise_cap_t cap_level; /*!<Select internal reference capacitance of denoise channel.
Ensure that the denoise readings are closest to the readings of the channel being measured.
Use `touch_pad_denoise_read_data` to get the reading of denoise channel.
The equivalent capacitance of the shielded channel can be calculated
from the reading of denoise channel. */
} touch_pad_denoise_t;
typedef enum {
TOUCH_PAD_SHIELD_DRV_L0 = 0,/*!<The max equivalent capacitance in shield channel is 40pf */
TOUCH_PAD_SHIELD_DRV_L1, /*!<The max equivalent capacitance in shield channel is 80pf */
TOUCH_PAD_SHIELD_DRV_L2, /*!<The max equivalent capacitance in shield channel is 120pf */
TOUCH_PAD_SHIELD_DRV_L3, /*!<The max equivalent capacitance in shield channel is 160pf */
TOUCH_PAD_SHIELD_DRV_L4, /*!<The max equivalent capacitance in shield channel is 200pf */
TOUCH_PAD_SHIELD_DRV_L5, /*!<The max equivalent capacitance in shield channel is 240pf */
TOUCH_PAD_SHIELD_DRV_L6, /*!<The max equivalent capacitance in shield channel is 280pf */
TOUCH_PAD_SHIELD_DRV_L7, /*!<The max equivalent capacitance in shield channel is 320pf */
TOUCH_PAD_SHIELD_DRV_MAX
} touch_pad_shield_driver_t;
/** Touch sensor waterproof configuration */
typedef struct touch_pad_waterproof {
touch_pad_t guard_ring_pad; /*!<Waterproof. Select touch channel use for guard pad */
touch_pad_shield_driver_t shield_driver;/*!<Waterproof. Select max equivalent capacitance for shield pad
Config the Touch14 to the touch sensor and compare the measured
reading to the Touch0 reading to estimate the equivalent capacitance.*/
} touch_pad_waterproof_t;
/** Touch sensor proximity detection configuration */
#define TOUCH_PROXIMITY_MEAS_NUM_MAX (0xFF)
/** Touch channel idle state configuration */
typedef enum {
TOUCH_PAD_CONN_HIGHZ = 0, /*!<Idle status of touch channel is high resistance state */
TOUCH_PAD_CONN_GND = 1, /*!<Idle status of touch channel is ground connection */
TOUCH_PAD_CONN_MAX
} touch_pad_conn_type_t;
/**
* @brief Touch channel IIR filter coefficient configuration.
* @note On ESP32S2. There is an error in the IIR calculation. The magnitude of the error is twice the filter coefficient.
* So please select a smaller filter coefficient on the basis of meeting the filtering requirements.
* Recommended filter coefficient selection `IIR_16`.
*/
typedef enum {
TOUCH_PAD_FILTER_IIR_4 = 0, /*!<The filter mode is first-order IIR filter. The coefficient is 4. */
TOUCH_PAD_FILTER_IIR_8, /*!<The filter mode is first-order IIR filter. The coefficient is 8. */
TOUCH_PAD_FILTER_IIR_16, /*!<The filter mode is first-order IIR filter. The coefficient is 16 (Typical value). */
TOUCH_PAD_FILTER_IIR_32, /*!<The filter mode is first-order IIR filter. The coefficient is 32. */
TOUCH_PAD_FILTER_IIR_64, /*!<The filter mode is first-order IIR filter. The coefficient is 64. */
TOUCH_PAD_FILTER_IIR_128, /*!<The filter mode is first-order IIR filter. The coefficient is 128. */
TOUCH_PAD_FILTER_IIR_256, /*!<The filter mode is first-order IIR filter. The coefficient is 256. */
TOUCH_PAD_FILTER_JITTER, /*!<The filter mode is jitter filter */
TOUCH_PAD_FILTER_MAX
} touch_filter_mode_t;
/**
* @brief Level of filter applied on the original data against large noise interference.
* @note On ESP32S2. There is an error in the IIR calculation. The magnitude of the error is twice the filter coefficient.
* So please select a smaller filter coefficient on the basis of meeting the filtering requirements.
* Recommended filter coefficient selection `IIR_2`.
*/
typedef enum {
TOUCH_PAD_SMOOTH_OFF = 0, /*!<No filtering of raw data. */
TOUCH_PAD_SMOOTH_IIR_2 = 1, /*!<Filter the raw data. The coefficient is 2 (Typical value). */
TOUCH_PAD_SMOOTH_IIR_4 = 2, /*!<Filter the raw data. The coefficient is 4. */
TOUCH_PAD_SMOOTH_IIR_8 = 3, /*!<Filter the raw data. The coefficient is 8. */
TOUCH_PAD_SMOOTH_MAX,
} touch_smooth_mode_t;
/** Touch sensor filter configuration */
typedef struct touch_filter_config {
touch_filter_mode_t mode; /*!<Set filter mode. The input to the filter is raw data and the output is the baseline value.
Larger filter coefficients increase the stability of the baseline. */
uint32_t debounce_cnt; /*!<Set debounce count, such as `n`. If the measured values continue to exceed
the threshold for `n+1` times, the touch sensor state changes.
Range: 0 ~ 7 */
uint32_t hysteresis_thr; /*!<Hysteresis threshold coefficient. hysteresis = hysteresis coefficient * touch threshold.
If (raw data - baseline) > (touch threshold + hysteresis), the touch channel be touched.
If (raw data - baseline) < (touch threshold - hysteresis), the touch channel be released.
Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 2/32; 3: OFF */
uint32_t noise_thr; /*!<Noise threshold coefficient. noise = noise coefficient * touch threshold.
If (raw data - baseline) > (noise), the baseline stop updating.
If (raw data - baseline) < (noise), the baseline start updating.
Range: 0 ~ 3. The coefficient is 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; */
uint32_t noise_neg_thr; /*!<Negative noise threshold coefficient. negative noise = noise coefficient * touch threshold.
If (baseline - raw data) > (negative noise), the baseline restart reset process(refer to `baseline_reset`).
If (baseline - raw data) < (negative noise), the baseline stop reset process(refer to `baseline_reset`).
Range: 0 ~ 3. The coefficient is 0: 4/8; 1: 3/8; 2: 2/8; 3: 1/8; */
uint32_t neg_noise_limit; /*!<Set the cumulative number of baseline reset processes. such as `n`. If the measured values continue to exceed
the negative noise threshold for `n+1` times, the baseline reset to raw data.
Range: 0 ~ 15 */
uint32_t jitter_step; /*!<Set jitter filter step size. Range: 0 ~ 15 */
touch_smooth_mode_t smh_lvl;/*!<Level of filter applied on the original data against large noise interference. */
#define TOUCH_DEBOUNCE_CNT_MAX (7)
#define TOUCH_HYSTERESIS_THR_MAX (3)
#define TOUCH_NOISE_THR_MAX (3)
#define TOUCH_NOISE_NEG_THR_MAX (3)
#define TOUCH_NEG_NOISE_CNT_LIMIT (15)
#define TOUCH_JITTER_STEP_MAX (15)
} touch_filter_config_t;
/** Touch sensor channel sleep configuration */
typedef struct {
touch_pad_t touch_num; /*!<Set touch channel number for sleep pad.
Only one touch sensor channel is supported in deep sleep mode.
If clear the sleep channel, point this pad to `TOUCH_PAD_NUM0` */
bool en_proximity; /*!<enable proximity function for sleep pad */
} touch_pad_sleep_channel_t;
#endif // CONFIG_IDF_TARGET_ESP32S2
tools/sdk/esp32s2/include/soc/include/hal/uart_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The HAL layer for UART.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "hal/uart_ll.h"
#include "hal/uart_types.h"
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
uart_dev_t *dev;
} uart_hal_context_t;
/**
* @brief Clear the UART interrupt status
*
* @param hal Context of the HAL layer
* @param mask The interrupt status mask to be cleared. Using the ORred mask of `UART_INTR_RXFIFO_FULL ... UART_INTR_CMD_CHAR_DET`
*
* @return None
*/
#define uart_hal_clr_intsts_mask(hal, mask) uart_ll_clr_intsts_mask((hal)->dev, mask)
/**
* @brief Disable the UART interrupt
*
* @param hal Context of the HAL layer
* @param mask The interrupt mask to be disabled. Using the ORred mask of `UART_INTR_RXFIFO_FULL ... UART_INTR_CMD_CHAR_DET`
*
* @return None
*/
#define uart_hal_disable_intr_mask(hal, mask) uart_ll_disable_intr_mask((hal)->dev, mask)
/**
* @brief Enable the UART interrupt
*
* @param hal Context of the HAL layer
* @param mask The UART interrupt mask to be enabled. Using the ORred mask of `UART_INTR_RXFIFO_FULL ... UART_INTR_CMD_CHAR_DET`
*
* @return None
*/
#define uart_hal_ena_intr_mask(hal, mask) uart_ll_ena_intr_mask((hal)->dev, mask)
/**
* @brief Get the UART interrupt status
*
* @param hal Context of the HAL layer
*
* @return UART interrupt status
*/
#define uart_hal_get_intsts_mask(hal) uart_ll_get_intsts_mask((hal)->dev)
/**
* @brief Get status of enabled interrupt
*
* @param hal Context of the HAL layer
*
* @return UART Interrupt enabled value
*/
#define uart_hal_get_intr_ena_status(hal) uart_ll_get_intr_ena_status((hal)->dev)
/**
* @brief Get the UART pattern char configuration
*
* @param hal Context of the HAL layer
* @param cmd_char Pointer to accept UART AT cmd char
* @param char_num Pointer to accept the `UART_CHAR_NUM` configuration
*
* @return None
*/
#define uart_hal_get_at_cmd_char(hal, cmd_char, char_num) uart_ll_get_at_cmd_char((hal)->dev, cmd_char, char_num)
/**
* @brief Set the UART rst signal active level
*
* @param hal Context of the HAL layer
* @param active_level The rts active level. The active level is low if set to 0. The active level is high if set to 1
*
* @return None
*/
#define uart_hal_set_rts(hal, active_level) uart_ll_set_rts_active_level((hal)->dev, active_level)
/**
* @brief Get the txfifo writeable length(in byte)
*
* @param hal Context of the HAL layer
*
* @return UART txfifo writeable length
*/
#define uart_hal_get_txfifo_len(hal) uart_ll_get_txfifo_len((hal)->dev)
/**
* @brief Check if the UART sending state machine is in the IDLE state.
*
* @param hal Context of the HAL layer
*
* @return True if the state machine is in the IDLE state, otherwise false will be returned.
*/
#define uart_hal_is_tx_idle(hal) uart_ll_is_tx_idle((hal)->dev)
/**
* @brief Read data from the UART rxfifo
*
* @param[in] hal Context of the HAL layer
* @param[in] buf Pointer to the buffer used to store the read data. The buffer size should be large than 128 byte
* @param[inout] inout_rd_len As input, the size of output buffer to read (set to 0 to read all available data).
* As output, returns the actual size written into the output buffer.
*
* @return None
*/
void uart_hal_read_rxfifo(uart_hal_context_t *hal, uint8_t *buf, int *inout_rd_len);
/**
* @brief Write data into the UART txfifo
*
* @param hal Context of the HAL layer
* @param buf Pointer of the data buffer need to be written to txfifo
* @param data_size The data size(in byte) need to be written
* @param write_size The size has been written
*
* @return None
*/
void uart_hal_write_txfifo(uart_hal_context_t *hal, const uint8_t *buf, uint32_t data_size, uint32_t *write_size);
/**
* @brief Reset the UART txfifo
*
* @param hal Context of the HAL layer
*
* @return None
*/
void uart_hal_txfifo_rst(uart_hal_context_t *hal);
/**
* @brief Reset the UART rxfifo
*
* @param hal Context of the HAL layer
*
* @return None
*/
void uart_hal_rxfifo_rst(uart_hal_context_t *hal);
/**
* @brief Init the UART hal and set the UART to the default configuration.
*
* @param hal Context of the HAL layer
* @param uart_num The uart port number, the max port number is (UART_NUM_MAX -1)
*
* @return None
*/
void uart_hal_init(uart_hal_context_t *hal, uart_port_t uart_num);
/**
* @brief Configure the UART baud-rate and select the source clock
*
* @param hal Context of the HAL layer
* @param source_clk The UART source clock. Support `UART_SCLK_REF_TICK` and `UART_SCLK_APB`
* @param baud_rate The baud-rate to be set
*
* @return None
*/
void uart_hal_set_baudrate(uart_hal_context_t *hal, uart_sclk_t source_clk, uint32_t baud_rate);
/**
* @brief Configure the UART stop bit
*
* @param hal Context of the HAL layer
* @param stop_bit The stop bit to be set
*
* @return None
*/
void uart_hal_set_stop_bits(uart_hal_context_t *hal, uart_stop_bits_t stop_bit);
/**
* @brief Configure the UART data bit
*
* @param hal Context of the HAL layer
* @param data_bit The data bit to be set
*
* @return None
*/
void uart_hal_set_data_bit_num(uart_hal_context_t *hal, uart_word_length_t data_bit);
/**
* @brief Configure the UART parity mode
*
* @param hal Context of the HAL layer
* @param parity_mode The UART parity mode to be set
*
* @return None
*/
void uart_hal_set_parity(uart_hal_context_t *hal, uart_parity_t parity_mode);
/**
* @brief Configure the UART hardware flow control
*
* @param hal Context of the HAL layer
* @param flow_ctrl The flow control mode to be set
* @param rx_thresh The rts flow control signal will be active if the data length in rxfifo is large than this value
*
* @return None
*/
void uart_hal_set_hw_flow_ctrl(uart_hal_context_t *hal, uart_hw_flowcontrol_t flow_ctrl, uint8_t rx_thresh);
/**
* @brief Configure the UART AT cmd char detect function. When the receiver receives a continuous AT cmd char, it will produce a interrupt
*
* @param hal Context of the HAL layer
* @param at_cmd The AT cmd char detect configuration
*
* @return None.
*/
void uart_hal_set_at_cmd_char(uart_hal_context_t *hal, uart_at_cmd_t *at_cmd);
/**
* @brief Set the timeout value of the UART receiver
*
* @param hal Context of the HAL layer
* @param tout The timeout value for receiver to receive a data
*
* @return None
*/
void uart_hal_set_rx_timeout(uart_hal_context_t *hal, const uint8_t tout);
/**
* @brief Set the UART dtr signal active level
*
* @param hal Context of the HAL layer
* @param active_level The dtr active level. The active level is low if set to 0. The active level is high if set to 1
*
* @return None
*/
void uart_hal_set_dtr(uart_hal_context_t *hal, int active_level);
/**
* @brief Set the UART software flow control
*
* @param hal Context of the HAL layer
* @param flow_ctrl The software flow control configuration
* @param sw_flow_ctrl_en Set true to enable the software flow control, otherwise set it false
*
* @return None
*/
void uart_hal_set_sw_flow_ctrl(uart_hal_context_t *hal, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en);
/**
* @brief Set the UART tx idle number
*
* @param hal Context of the HAL layer
* @param idle_num The cycle number betwin the two transmission
*
* @return None
*/
void uart_hal_set_tx_idle_num(uart_hal_context_t *hal, uint16_t idle_num);
/**
* @brief Set the UART rxfifo full threshold
*
* @param hal Context of the HAL layer
* @param full_thrhd The rxfifo full threshold. If the `UART_RXFIFO_FULL` interrupt is enabled and
* the data length in rxfifo is more than this value, it will generate `UART_RXFIFO_FULL` interrupt
*
* @return None
*/
void uart_hal_set_rxfifo_full_thr(uart_hal_context_t *hal, uint32_t full_thrhd);
/**
* @brief Set the UART txfifo empty threshold
*
* @param hal Context of the HAL layer
* @param empty_thrhd The txfifo empty threshold to be set. If the `UART_TXFIFO_EMPTY` interrupt is enabled and
* the data length in txfifo is less than this value, it will generate `UART_TXFIFO_EMPTY` interrupt
*
* @return None
*/
void uart_hal_set_txfifo_empty_thr(uart_hal_context_t *hal, uint32_t empty_thrhd);
/**
* @brief Configure the UART to send a number of break(NULL) chars
*
* @param hal Context of the HAL layer
* @param break_num The number of the break char need to be send
*
* @return None
*/
void uart_hal_tx_break(uart_hal_context_t *hal, uint32_t break_num);
/**
* @brief Configure the UART wake up function.
* Note that RXD cannot be input through GPIO Matrix but only through IO_MUX when use this function
*
* @param hal Context of the HAL layer
* @param wakeup_thrd The wake up threshold to be set. The system will be woken up from light-sleep when the input RXD edge changes more times than `wakeup_thrd+2`
*
* @return None
*/
void uart_hal_set_wakeup_thrd(uart_hal_context_t *hal, uint32_t wakeup_thrd);
/**
* @brief Configure the UART mode
*
* @param hal Context of the HAL layer
* @param mode The UART mode to be set
*
* @return None
*/
void uart_hal_set_mode(uart_hal_context_t *hal, uart_mode_t mode);
/**
* @brief Configure the UART hardware to inverse the signals
*
* @param hal Context of the HAL layer
* @param inv_mask The sigal mask needs to be inversed. Use the ORred mask of type `uart_signal_inv_t`
*
* @return None
*/
void uart_hal_inverse_signal(uart_hal_context_t *hal, uint32_t inv_mask);
/**
* @brief Get the UART wakeup threshold configuration
*
* @param hal Context of the HAL layer
* @param wakeup_thrd Pointer to accept the value of UART wakeup threshold configuration
*
* @return None
*/
void uart_hal_get_wakeup_thrd(uart_hal_context_t *hal, uint32_t *wakeup_thrd);
/**
* @brief Get the UART data bit configuration
*
* @param hal Context of the HAL layer
* @param data_bit Pointer to accept the value of UART data bit configuration
*
* @return None
*/
void uart_hal_get_data_bit_num(uart_hal_context_t *hal, uart_word_length_t *data_bit);
/**
* @brief Get the UART stop bit configuration
*
* @param hal Context of the HAL layer
* @param stop_bit Pointer to accept the value of UART stop bit configuration
*
* @return None
*/
void uart_hal_get_stop_bits(uart_hal_context_t *hal, uart_stop_bits_t *stop_bit);
/**
* @brief Get the UART parity mode configuration
*
* @param hal Context of the HAL layer
* @param parity_mode Pointer to accept the UART parity mode configuration
*
* @return None
*/
void uart_hal_get_parity(uart_hal_context_t *hal, uart_parity_t *parity_mode);
/**
* @brief Get the UART baud-rate configuration
*
* @param hal Context of the HAL layer
* @param baud_rate Pointer to accept the current baud-rate
*
* @return None
*/
void uart_hal_get_baudrate(uart_hal_context_t *hal, uint32_t *baud_rate);
/**
* @brief Get the hw flow control configuration
*
* @param hal Context of the HAL layer
* @param flow_ctrl Pointer to accept the UART flow control configuration
*
* @return None
*/
void uart_hal_get_hw_flow_ctrl(uart_hal_context_t *hal, uart_hw_flowcontrol_t *flow_ctrl);
/**
* @brief Check if the UART rts flow control is enabled
*
* @param hal Context of the HAL layer
*
* @return True if rts flow control is enabled, otherwise false will be returned
*/
bool uart_hal_is_hw_rts_en(uart_hal_context_t *hal);
/**
* @brief Get the UART source clock configuration
*
* @param hal Context of the HAL layer
* @param sclk The poiter to accept the UART source clock configuration
*
* @return None
*/
void uart_hal_get_sclk(uart_hal_context_t *hal, uart_sclk_t *sclk);
/**
* @brief Configure TX signal loop back to RX module, just for the testing purposes
*
* @param hal Context of the HAL layer
* @param loop_back_en Set ture to enable the loop back function, else set it false.
*
* @return None
*/
void uart_hal_set_loop_back(uart_hal_context_t *hal, bool loop_back_en);
/**
* @brief Calculate uart symbol bit length, as defined in configuration.
*
* @param hw Beginning address of the peripheral registers.
*
* @return number of bits per UART symbol.
*/
uint8_t uart_hal_get_symb_len(uart_hal_context_t *hal);
/**
* @brief Get UART maximum timeout threshold.
*
* @param hw Beginning address of the peripheral registers.
*
* @return maximum timeout threshold value for target.
*/
uint16_t uart_hal_get_max_rx_timeout_thrd(uart_hal_context_t *hal);
/**
* @brief Get the timeout threshold value set for receiver.
*
* @param hw Beginning address of the peripheral registers.
*
* @return tout_thr The timeout value. If timeout is disabled then returns 0.
*/
#define uart_hal_get_rx_tout_thr(hal) uart_ll_get_rx_tout_thr((hal)->dev)
/**
* @brief Get the length of readable data in UART rxfifo.
*
* @param hw Beginning address of the peripheral registers.
*
* @return The readable data length in rxfifo.
*/
#define uart_hal_get_rxfifo_len(hal) uart_ll_get_rxfifo_len((hal)->dev)
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/uart_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include "soc/uart_caps.h"
/**
* @brief UART port number, can be UART_NUM_0 ~ (UART_NUM_MAX -1).
*/
typedef int uart_port_t;
/**
* @brief UART mode selection
*/
typedef enum {
UART_MODE_UART = 0x00, /*!< mode: regular UART mode*/
UART_MODE_RS485_HALF_DUPLEX = 0x01, /*!< mode: half duplex RS485 UART mode control by RTS pin */
UART_MODE_IRDA = 0x02, /*!< mode: IRDA UART mode*/
UART_MODE_RS485_COLLISION_DETECT = 0x03, /*!< mode: RS485 collision detection UART mode (used for test purposes)*/
UART_MODE_RS485_APP_CTRL = 0x04, /*!< mode: application control RS485 UART mode (used for test purposes)*/
} uart_mode_t;
/**
* @brief UART word length constants
*/
typedef enum {
UART_DATA_5_BITS = 0x0, /*!< word length: 5bits*/
UART_DATA_6_BITS = 0x1, /*!< word length: 6bits*/
UART_DATA_7_BITS = 0x2, /*!< word length: 7bits*/
UART_DATA_8_BITS = 0x3, /*!< word length: 8bits*/
UART_DATA_BITS_MAX = 0x4,
} uart_word_length_t;
/**
* @brief UART stop bits number
*/
typedef enum {
UART_STOP_BITS_1 = 0x1, /*!< stop bit: 1bit*/
UART_STOP_BITS_1_5 = 0x2, /*!< stop bit: 1.5bits*/
UART_STOP_BITS_2 = 0x3, /*!< stop bit: 2bits*/
UART_STOP_BITS_MAX = 0x4,
} uart_stop_bits_t;
/**
* @brief UART parity constants
*/
typedef enum {
UART_PARITY_DISABLE = 0x0, /*!< Disable UART parity*/
UART_PARITY_EVEN = 0x2, /*!< Enable UART even parity*/
UART_PARITY_ODD = 0x3 /*!< Enable UART odd parity*/
} uart_parity_t;
/**
* @brief UART hardware flow control modes
*/
typedef enum {
UART_HW_FLOWCTRL_DISABLE = 0x0, /*!< disable hardware flow control*/
UART_HW_FLOWCTRL_RTS = 0x1, /*!< enable RX hardware flow control (rts)*/
UART_HW_FLOWCTRL_CTS = 0x2, /*!< enable TX hardware flow control (cts)*/
UART_HW_FLOWCTRL_CTS_RTS = 0x3, /*!< enable hardware flow control*/
UART_HW_FLOWCTRL_MAX = 0x4,
} uart_hw_flowcontrol_t;
/**
* @brief UART signal bit map
*/
typedef enum {
UART_SIGNAL_INV_DISABLE = 0, /*!< Disable UART signal inverse*/
UART_SIGNAL_IRDA_TX_INV = (0x1 << 0), /*!< inverse the UART irda_tx signal*/
UART_SIGNAL_IRDA_RX_INV = (0x1 << 1), /*!< inverse the UART irda_rx signal*/
UART_SIGNAL_RXD_INV = (0x1 << 2), /*!< inverse the UART rxd signal*/
UART_SIGNAL_CTS_INV = (0x1 << 3), /*!< inverse the UART cts signal*/
UART_SIGNAL_DSR_INV = (0x1 << 4), /*!< inverse the UART dsr signal*/
UART_SIGNAL_TXD_INV = (0x1 << 5), /*!< inverse the UART txd signal*/
UART_SIGNAL_RTS_INV = (0x1 << 6), /*!< inverse the UART rts signal*/
UART_SIGNAL_DTR_INV = (0x1 << 7), /*!< inverse the UART dtr signal*/
} uart_signal_inv_t;
/**
* @brief UART source clock
*/
typedef enum {
UART_SCLK_APB = 0x0, /*!< UART source clock from APB*/
UART_SCLK_REF_TICK = 0x01, /*!< UART source clock from REF_TICK*/
} uart_sclk_t;
/**
* @brief UART AT cmd char configuration parameters
* Note that this function may different on different chip. Please refer to the TRM at confirguration.
*/
typedef struct {
uint8_t cmd_char; /*!< UART AT cmd char*/
uint8_t char_num; /*!< AT cmd char repeat number*/
uint32_t gap_tout; /*!< gap time(in baud-rate) between AT cmd char*/
uint32_t pre_idle; /*!< the idle time(in baud-rate) between the non AT char and first AT char*/
uint32_t post_idle; /*!< the idle time(in baud-rate) between the last AT char and the none AT char*/
} uart_at_cmd_t;
/**
* @brief UART software flow control configuration parameters
*/
typedef struct {
uint8_t xon_char; /*!< Xon flow control char*/
uint8_t xoff_char; /*!< Xoff flow control char*/
uint8_t xon_thrd; /*!< If the software flow control is enabled and the data amount in rxfifo is less than xon_thrd, an xon_char will be sent*/
uint8_t xoff_thrd; /*!< If the software flow control is enabled and the data amount in rxfifo is more than xoff_thrd, an xoff_char will be sent*/
} uart_sw_flowctrl_t;
/**
* @brief UART configuration parameters for uart_param_config function
*/
typedef struct {
int baud_rate; /*!< UART baud rate*/
uart_word_length_t data_bits; /*!< UART byte size*/
uart_parity_t parity; /*!< UART parity mode*/
uart_stop_bits_t stop_bits; /*!< UART stop bits*/
uart_hw_flowcontrol_t flow_ctrl; /*!< UART HW flow control mode (cts/rts)*/
uint8_t rx_flow_ctrl_thresh; /*!< UART HW RTS threshold*/
union {
uart_sclk_t source_clk; /*!< UART source clock selection */
bool use_ref_tick __attribute__((deprecated)); /*!< Deprecated method to select ref tick clock source, set source_clk field instead */
};
} uart_config_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/usb_hal.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
bool use_external_phy;
} usb_hal_context_t;
void usb_hal_init(usb_hal_context_t *usb);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/wdt_hal.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include "soc/timer_group_caps.h"
#include "hal/wdt_types.h"
#include "hal/mwdt_ll.h"
#include "hal/rwdt_ll.h"
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
wdt_inst_t inst; /**< Which WDT instance this HAL context is using (i.e. MWDT0, MWDT1, RWDT)*/
union {
timg_dev_t *mwdt_dev; /**< Starting address of the MWDT */
rtc_cntl_dev_t *rwdt_dev; /**< Starting address of the RWDT*/
};
} wdt_hal_context_t;
/* ---------------------------- Init and Config ----------------------------- */
/**
* @brief Initialize one of the WDTs associated HAL context
*
* This function initializes one of the WDTs (MWDT0, MWDT1, or RWDT) hardware by
* doing the following:
* - Disables the WDT and all of its stages
* - Sets some registers with default values
* - Sets the WDTs source clock prescaler (not applicable to RWDT)
* - Optionally enables the level interrupt
*
* The HAL context is initialized by storing the type (i.e. MWDT or RWDT) of
* this WDT instance, and a pointer to the associated registers.
*
* @param hal Context of HAL layer
* @param wdt_inst Which WDT instance to initialize (MWDT0, MWDT1, or RWDT)
* @param prescaler MWDT source clock prescaler. Unused for RWDT
* @param enable_intr True to enable level interrupt. False to disable
*
* @note Although the WDTs on the ESP32 have an edge interrupt, this HAL does
* not utilize it and will always disables it.
* @note RWDT does not have a prescaler. Its tick rate is equal to the
* frequency of its source clock (RTC slow clock).
*/
void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescaler, bool enable_intr);
/**
* @brief Deinitialize a WDT and its HAL context
*
* This function deinitializes a WDT by feeding then disabling it. The WDT's
* interrupt is also cleared and disabled. The HAL context is cleared.
*
* @param hal Context of HAL layer
*/
void wdt_hal_deinit(wdt_hal_context_t *hal);
/**
* @brief Configure a particular stage of a WDT
*
* @param hal Context of HAL layer
* @param stage Stage to configure (0 to 3)
* @param timeout Number of WDT ticks for the stage to time out
* @param behavior What action to take when the stage times out. Note that only
* the RWDT supports the RTC reset action.
*
* @note This function can only be called when the WDT is unlocked. Call
* wdt_hal_write_protect_disable() first.
*/
void wdt_hal_config_stage(wdt_hal_context_t *hal, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior);
/* -------------------------------- Runtime --------------------------------- */
/**
* @brief Disable write protection of the WDT registers
*
* @param hal Context of HAL layer
*/
void wdt_hal_write_protect_disable(wdt_hal_context_t *hal);
/**
* @brief Enable write protection of the WDT registers
*
* @param hal Context of HAL layer
*/
void wdt_hal_write_protect_enable(wdt_hal_context_t *hal);
/**
* @brief Enable the WDT
*
* The WDT will start counting when enabled. This function also feeds the WDT
* before enabling it.
*
* @param hal Context of HAL layer
*
* @note This function can only be called when the WDT is unlocked. Call
* wdt_hal_write_protect_disable() first.
*/
void wdt_hal_enable(wdt_hal_context_t *hal);
/**
* @brief Disable the WDT
*
* @param hal Context of HAL layer
*
* @note This function can only be called when the WDT is unlocked. Call
* wdt_hal_write_protect_disable() first.
*/
void wdt_hal_disable(wdt_hal_context_t *hal);
/**
* @brief Handle WDT interrupt
*
* Clears the interrupt status bit and feeds the WDT
*
* @param hal Context of HAL layer
*
* @note This function can only be called when the WDT is unlocked. Call
* wdt_hal_write_protect_disable() first.
*/
void wdt_hal_handle_intr(wdt_hal_context_t *hal);
/**
* @brief Feed the WDT
*
* Feeding the WDT will reset the internal count and current stage.
*
* @param hal Context of HAL layer
*
* @note This function can only be called when the WDT is unlocked. Call
* wdt_hal_write_protect_disable() first.
*/
void wdt_hal_feed(wdt_hal_context_t *hal);
/**
* @brief Enable/Disable the WDT flash boot mode
*
* @param hal Context of HAL layer
* @param enable True to enable flash boot mode, false to disable.
*
* @note Flash boot mode can trigger a time out even if the WDT is disabled.
* @note This function can only be called when the WDT is unlocked. Call
* wdt_hal_write_protect_disable() first.
*/
void wdt_hal_set_flashboot_en(wdt_hal_context_t *hal, bool enable);
/**
* @brief Check if the WDT is enabled
*
* @param hal Context of HAL layer
* @return True if enabled, false otherwise
*/
bool wdt_hal_is_enabled(wdt_hal_context_t *hal);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/hal/wdt_types.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WDT_RWDT = 0, /*!< RTC Watchdog Timer (RWDT) */
WDT_MWDT0, /*!< Main System Watchdog Timer (MWDT) of Timer Group 0 */
WDT_MWDT1, /*!< Main System Watchdog Timer (MWDT) of Timer Group 1 */
} wdt_inst_t;
/**
* @brief Stages of a Watchdog Timer. A WDT has 4 stages.
*/
typedef enum {
WDT_STAGE0 = 0, /*!< Stage 0 */
WDT_STAGE1 = 1, /*!< Stage 1 */
WDT_STAGE2 = 2, /*!< Stage 2 */
WDT_STAGE3 = 3 /*!< Stage 3 */
} wdt_stage_t;
/**
* @brief Behavior of the WDT stage if it times out
*
* @note These enum values should be compatible with the corresponding register
* field values.
*/
typedef enum {
WDT_STAGE_ACTION_OFF = 0, /*!< Disabled. This stage will have no effects on the system. */
WDT_STAGE_ACTION_INT = 1, /*!< Trigger an interrupt when the stage expires. */
WDT_STAGE_ACTION_RESET_CPU = 2, /*!< Reset a CPU core when the stage expires. */
WDT_STAGE_ACTION_RESET_SYSTEM = 3, /*!< Reset the main system when the stage expires. This includes the CPU and all peripherals. The RTC is an exception and will not be reset. */
WDT_STAGE_ACTION_RESET_RTC = 4, /*!< Reset the main system and the RTC when the stage expires. ONLY AVAILABLE FOR RWDT */
} wdt_stage_action_t;
/**
* @brief Length of CPU or System Reset signals
*
* @note These enum values should be compatible with the corresponding register
* field values.
*/
typedef enum {
WDT_RESET_SIG_LENGTH_100ns = 0, /*!< 100 ns */
WDT_RESET_SIG_LENGTH_200ns = 1, /*!< 200 ns */
WDT_RESET_SIG_LENGTH_300ns = 2, /*!< 300 ns */
WDT_RESET_SIG_LENGTH_400ns = 3, /*!< 400 ns */
WDT_RESET_SIG_LENGTH_500ns = 4, /*!< 500 ns */
WDT_RESET_SIG_LENGTH_800ns = 5, /*!< 800 ns */
WDT_RESET_SIG_LENGTH_1_6us = 6, /*!< 1.6 us */
WDT_RESET_SIG_LENGTH_3_2us = 7 /*!< 3.2 us */
} wdt_reset_sig_length_t;
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/soc/compare_set.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __COMPARE_SET_H
#define __COMPARE_SET_H
#include <stdint.h>
#include <stdbool.h>
#include "soc/cpu.h"
#include "soc/soc_memory_layout.h"
#include "xtensa/xtruntime.h"
static inline void __attribute__((always_inline)) compare_and_set_native(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
{
#if (XCHAL_HAVE_S32C1I > 0)
__asm__ __volatile__ (
"WSR %2,SCOMPARE1 \n"
"S32C1I %0, %1, 0 \n"
:"=r"(*set)
:"r"(addr), "r"(compare), "0"(*set)
);
#else
// No S32C1I, so do this by disabling and re-enabling interrupts (slower)
uint32_t intlevel, old_value;
__asm__ __volatile__ ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) "\n"
: "=r"(intlevel));
old_value = *addr;
if (old_value == compare) {
*addr = *set;
}
__asm__ __volatile__ ("memw \n"
"wsr %0, ps\n"
:: "r"(intlevel));
*set = old_value;
#endif
}
void compare_and_set_extram(volatile uint32_t *addr, uint32_t compare, uint32_t *set);
#endif
tools/sdk/esp32s2/include/soc/include/soc/cpu.h
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_CPU_H
#define _SOC_CPU_H
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "xtensa/corebits.h"
#include "xtensa/config/core.h"
#include "xtensa/config/specreg.h"
#include "xt_instr_macros.h"
#include "hal/cpu_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @brief Read current stack pointer address
*
*/
static inline void *get_sp(void)
{
return cpu_hal_get_sp();
}
/**
* @brief Stall CPU using RTC controller
* @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
*/
void esp_cpu_stall(int cpu_id);
/**
* @brief Un-stall CPU using RTC controller
* @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
*/
void esp_cpu_unstall(int cpu_id);
/**
* @brief Reset CPU using RTC controller
* @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
*/
void esp_cpu_reset(int cpu_id);
/**
* @brief Returns true if a JTAG debugger is attached to CPU
* OCD (on chip debug) port.
*
* @note If "Make exception and panic handlers JTAG/OCD aware"
* is disabled, this function always returns false.
*/
bool esp_cpu_in_ocd_debug_mode(void);
/**
* @brief Convert the PC register value to its true address
*
* The address of the current instruction is not stored as an exact uint32_t
* representation in PC register. This function will convert the value stored in
* the PC register to a uint32_t address.
*
* @param pc_raw The PC as stored in register format.
*
* @return Address in uint32_t format
*/
static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc)
{
if (pc & 0x80000000) {
//Top two bits of a0 (return address) specify window increment. Overwrite to map to address space.
pc = (pc & 0x3fffffff) | 0x40000000;
}
//Minus 3 to get PC of previous instruction (i.e. instruction executed before return address)
return pc - 3;
}
typedef uint32_t esp_cpu_ccount_t;
static inline esp_cpu_ccount_t esp_cpu_get_ccount(void)
{
uint32_t result;
RSR(CCOUNT, result);
return result;
}
#ifdef __cplusplus
}
#endif
#endif
tools/sdk/esp32s2/include/soc/include/soc/lldesc.h
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// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdbool.h>
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/lldesc.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/lldesc.h"
#endif
//the size field has 12 bits, but 0 not for 4096.
//to avoid possible problem when the size is not word-aligned, we only use 4096-4 per desc.
/** Maximum size of data in the buffer that a DMA descriptor can hold. */
#define LLDESC_MAX_NUM_PER_DESC (4096-4)
/**
* Generate a linked list pointing to a (huge) buffer in an descriptor array.
*
* The caller should ensure there is enough size to hold the array, by calling
* ``lldesc_get_required_num``.
*
* @param out_desc_array Output of a descriptor array, the head should be fed to the DMA.
* @param buffer Buffer for the descriptors to point to.
* @param size Size (or length for TX) of the buffer
* @param isrx The RX DMA may require the buffer to be word-aligned, set to true for a RX link, otherwise false.
*/
void lldesc_setup_link(lldesc_t *out_desc_array, const void *buffer, int size, bool isrx);
/**
* Get the number of descriptors required for a given buffer size.
*
* @param data_size Size to check descriptor num.
*
* @return Numbers required.
*/
static inline int lldesc_get_required_num(int data_size)
{
return (data_size + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC;
}
tools/sdk/esp32s2/include/soc/include/soc/rtc_wdt.h
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// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/* Recommendation of using API RTC_WDT.
1) Setting and enabling rtc_wdt:
@code
rtc_wdt_protect_off();
rtc_wdt_disable();
rtc_wdt_set_length_of_reset_signal(RTC_WDT_SYS_RESET_SIG, RTC_WDT_LENGTH_3_2us);
rtc_wdt_set_stage(RTC_WDT_STAGE0, RTC_WDT_STAGE_ACTION_RESET_SYSTEM); //RTC_WDT_STAGE_ACTION_RESET_SYSTEM or RTC_WDT_STAGE_ACTION_RESET_RTC
rtc_wdt_set_time(RTC_WDT_STAGE0, 7000); // timeout rtd_wdt 7000ms.
rtc_wdt_enable();
rtc_wdt_protect_on();
@endcode
* If you use this option RTC_WDT_STAGE_ACTION_RESET_SYSTEM then after reset you can see these messages.
They can help to understand where the CPUs were when the WDT was triggered.
W (30) boot: PRO CPU has been reset by WDT.
W (30) boot: WDT reset info: PRO CPU PC=0x400xxxxx
... function where it happened
W (31) boot: WDT reset info: APP CPU PC=0x400xxxxx
... function where it happened
* If you use this option RTC_WDT_STAGE_ACTION_RESET_RTC then you will see message (rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT))
without description where were CPUs when it happened.
2) Reset counter of rtc_wdt:
@code
rtc_wdt_feed();
@endcode
3) Disable rtc_wdt:
@code
rtc_wdt_disable();
@endcode
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/rtc_periph.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C"
{
#endif
/// List of stage of rtc watchdog. WDT has 4 stage.
typedef enum {
RTC_WDT_STAGE0 = 0, /*!< Stage 0 */
RTC_WDT_STAGE1 = 1, /*!< Stage 1 */
RTC_WDT_STAGE2 = 2, /*!< Stage 2 */
RTC_WDT_STAGE3 = 3 /*!< Stage 3 */
} rtc_wdt_stage_t;
/// List of action. When the time of stage expires this action will be triggered.
typedef enum {
RTC_WDT_STAGE_ACTION_OFF = RTC_WDT_STG_SEL_OFF, /*!< Disabled. This stage will have no effects on the system. */
RTC_WDT_STAGE_ACTION_INTERRUPT = RTC_WDT_STG_SEL_INT, /*!< Trigger an interrupt. When the stage expires an interrupt is triggered. */
RTC_WDT_STAGE_ACTION_RESET_CPU = RTC_WDT_STG_SEL_RESET_CPU, /*!< Reset a CPU core. */
RTC_WDT_STAGE_ACTION_RESET_SYSTEM = RTC_WDT_STG_SEL_RESET_SYSTEM, /*!< Reset the main system includes the CPU and all peripherals. The RTC is an exception to this, and it will not be reset. */
RTC_WDT_STAGE_ACTION_RESET_RTC = RTC_WDT_STG_SEL_RESET_RTC /*!< Reset the main system and the RTC. */
} rtc_wdt_stage_action_t;
/// Type of reset signal
typedef enum {
RTC_WDT_SYS_RESET_SIG = 0, /*!< System reset signal length selection */
RTC_WDT_CPU_RESET_SIG = 1 /*!< CPU reset signal length selection */
} rtc_wdt_reset_sig_t;
/// Length of reset signal
typedef enum {
RTC_WDT_LENGTH_100ns = 0, /*!< 100 ns */
RTC_WDT_LENGTH_200ns = 1, /*!< 200 ns */
RTC_WDT_LENGTH_300ns = 2, /*!< 300 ns */
RTC_WDT_LENGTH_400ns = 3, /*!< 400 ns */
RTC_WDT_LENGTH_500ns = 4, /*!< 500 ns */
RTC_WDT_LENGTH_800ns = 5, /*!< 800 ns */
RTC_WDT_LENGTH_1_6us = 6, /*!< 1.6 us */
RTC_WDT_LENGTH_3_2us = 7 /*!< 3.2 us */
} rtc_wdt_length_sig_t;
/**
* @brief Get status of protect of rtc_wdt.
*
* @return
* - True if the protect of RTC_WDT is set
*/
bool rtc_wdt_get_protect_status(void);
/**
* @brief Set protect of rtc_wdt.
*/
void rtc_wdt_protect_on(void);
/**
* @brief Reset protect of rtc_wdt.
*/
void rtc_wdt_protect_off(void);
/**
* @brief Enable rtc_wdt.
*/
void rtc_wdt_enable(void);
/**
* @brief Enable the flash boot protection procedure for WDT.
*
* Do not recommend to use it in the app.
* This function was added to be compatibility with the old bootloaders.
* This mode is disabled in bootloader or using rtc_wdt_disable() function.
*/
void rtc_wdt_flashboot_mode_enable(void);
/**
* @brief Disable rtc_wdt.
*/
void rtc_wdt_disable(void);
/**
* @brief Reset counter rtc_wdt.
*
* It returns to stage 0 and its expiry counter restarts from 0.
*/
void rtc_wdt_feed(void);
/**
* @brief Set time for required stage.
*
* @param[in] stage Stage of rtc_wdt.
* @param[in] timeout_ms Timeout for this stage.
*
* @return
* - ESP_OK In case of success
* - ESP_ERR_INVALID_ARG If stage has invalid value
*/
esp_err_t rtc_wdt_set_time(rtc_wdt_stage_t stage, unsigned int timeout_ms);
/**
* @brief Get the timeout set for the required stage.
*
* @param[in] stage Stage of rtc_wdt.
* @param[out] timeout_ms Timeout set for this stage. (not elapsed time).
*
* @return
* - ESP_OK In case of success
* - ESP_ERR_INVALID_ARG If stage has invalid value
*/
esp_err_t rtc_wdt_get_timeout(rtc_wdt_stage_t stage, unsigned int* timeout_ms);
/**
* @brief Set an action for required stage.
*
* @param[in] stage Stage of rtc_wdt.
* @param[in] stage_sel Action for this stage. When the time of stage expires this action will be triggered.
*
* @return
* - ESP_OK In case of success
* - ESP_ERR_INVALID_ARG If stage or stage_sel have invalid value
*/
esp_err_t rtc_wdt_set_stage(rtc_wdt_stage_t stage, rtc_wdt_stage_action_t stage_sel);
/**
* @brief Set a length of reset signal.
*
* @param[in] reset_src Type of reset signal.
* @param[in] reset_signal_length A length of reset signal.
*
* @return
* - ESP_OK In case of success
* - ESP_ERR_INVALID_ARG If reset_src or reset_signal_length have invalid value
*/
esp_err_t rtc_wdt_set_length_of_reset_signal(rtc_wdt_reset_sig_t reset_src, rtc_wdt_length_sig_t reset_signal_length);
/**
* @brief Return true if rtc_wdt is enabled.
*
* @return
* - True rtc_wdt is enabled
*/
bool rtc_wdt_is_on(void);
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/include/soc/soc_memory_layout.h
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "sdkconfig.h"
#include "esp_attr.h"
#ifdef CONFIG_BT_ENABLED
#define SOC_MEM_BT_DATA_START 0x3ffae6e0
#define SOC_MEM_BT_DATA_END 0x3ffaff10
#define SOC_MEM_BT_EM_START 0x3ffb0000
#define SOC_MEM_BT_EM_END 0x3ffb7cd8
#define SOC_MEM_BT_EM_BTDM0_START 0x3ffb0000
#define SOC_MEM_BT_EM_BTDM0_END 0x3ffb09a8
#define SOC_MEM_BT_EM_BLE_START 0x3ffb09a8
#define SOC_MEM_BT_EM_BLE_END 0x3ffb1ddc
#define SOC_MEM_BT_EM_BTDM1_START 0x3ffb1ddc
#define SOC_MEM_BT_EM_BTDM1_END 0x3ffb2730
#define SOC_MEM_BT_EM_BREDR_START 0x3ffb2730
#define SOC_MEM_BT_EM_BREDR_NO_SYNC_END 0x3ffb6388 //Not calculate with synchronize connection support
#define SOC_MEM_BT_EM_BREDR_END 0x3ffb7cd8 //Calculate with synchronize connection support
#define SOC_MEM_BT_EM_SYNC0_START 0x3ffb6388
#define SOC_MEM_BT_EM_SYNC0_END 0x3ffb6bf8
#define SOC_MEM_BT_EM_SYNC1_START 0x3ffb6bf8
#define SOC_MEM_BT_EM_SYNC1_END 0x3ffb7468
#define SOC_MEM_BT_EM_SYNC2_START 0x3ffb7468
#define SOC_MEM_BT_EM_SYNC2_END 0x3ffb7cd8
#define SOC_MEM_BT_BSS_START 0x3ffb8000
#define SOC_MEM_BT_BSS_END 0x3ffb9a20
#define SOC_MEM_BT_MISC_START 0x3ffbdb28
#define SOC_MEM_BT_MISC_END 0x3ffbdb5c
#define SOC_MEM_BT_EM_PER_SYNC_SIZE 0x870
#define SOC_MEM_BT_EM_BREDR_REAL_END (SOC_MEM_BT_EM_BREDR_NO_SYNC_END + CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF * SOC_MEM_BT_EM_PER_SYNC_SIZE)
#endif //CONFIG_BT_ENABLED
#define SOC_MEMORY_TYPE_NO_PRIOS 3
/* Type descriptor holds a description for a particular type of memory on a particular SoC.
*/
typedef struct {
const char *name; ///< Name of this memory type
uint32_t caps[SOC_MEMORY_TYPE_NO_PRIOS]; ///< Capabilities for this memory type (as a prioritised set)
bool aliased_iram; ///< If true, this is data memory that is is also mapped in IRAM
bool startup_stack; ///< If true, memory of this type is used for ROM stack during startup
} soc_memory_type_desc_t;
/* Constant table of tag descriptors for all this SoC's tags */
extern const soc_memory_type_desc_t soc_memory_types[];
extern const size_t soc_memory_type_count;
/* Region descriptor holds a description for a particular region of memory on a particular SoC.
*/
typedef struct
{
intptr_t start; ///< Start address of the region
size_t size; ///< Size of the region in bytes
size_t type; ///< Type of the region (index into soc_memory_types array)
intptr_t iram_address; ///< If non-zero, is equivalent address in IRAM
} soc_memory_region_t;
extern const soc_memory_region_t soc_memory_regions[];
extern const size_t soc_memory_region_count;
/* Region descriptor holds a description for a particular region of
memory reserved on this SoC for a particular use (ie not available
for stack/heap usage.) */
typedef struct
{
intptr_t start;
intptr_t end;
} soc_reserved_region_t;
/* Use this macro to reserved a fixed region of RAM (hardcoded addresses)
* for a particular purpose.
*
* Usually used to mark out memory addresses needed for hardware or ROM code
* purposes.
*
* Don't call this macro from user code which can use normal C static allocation
* instead.
*
* @param START Start address to be reserved.
* @param END One after the address of the last byte to be reserved. (ie length of
* the reserved region is (END - START) in bytes.
* @param NAME Name for the reserved region. Must be a valid variable name,
* unique to this source file.
*/
#define SOC_RESERVE_MEMORY_REGION(START, END, NAME) \
__attribute__((section(".reserved_memory_address"))) __attribute__((used)) \
static soc_reserved_region_t reserved_region_##NAME = { START, END };
/* Return available memory regions for this SoC. Each available memory
* region is a contiguous piece of memory which is not being used by
* static data, used by ROM code, or reserved by a component using
* the SOC_RESERVE_MEMORY_REGION() macro.
*
* This result is soc_memory_regions[] minus all regions reserved
* via the SOC_RESERVE_MEMORY_REGION() macro (which may also split
* some regions up.)
*
* At startup, all available memory returned by this function is
* registered as heap space.
*
* @note OS-level startup function only, not recommended to call from
* app code.
*
* @param regions Pointer to an array for reading available regions into.
* Size of the array should be at least the result of
* soc_get_available_memory_region_max_count(). Entries in the array
* will be ordered by memory address.
*
* @return Number of entries copied to 'regions'. Will be no greater than
* the result of soc_get_available_memory_region_max_count().
*/
size_t soc_get_available_memory_regions(soc_memory_region_t *regions);
/* Return the maximum number of available memory regions which could be
* returned by soc_get_available_memory_regions(). Used to size the
* array passed to that function.
*/
size_t soc_get_available_memory_region_max_count(void);
inline static bool IRAM_ATTR esp_ptr_dma_capable(const void *p)
{
return (intptr_t)p >= SOC_DMA_LOW && (intptr_t)p < SOC_DMA_HIGH;
}
inline static bool IRAM_ATTR esp_ptr_dma_ext_capable(const void *p)
{
#if CONFIG_IDF_TARGET_ESP32S2
return (intptr_t)p >= SOC_DMA_EXT_LOW && (intptr_t)p < SOC_DMA_EXT_HIGH;
#else
return false;
#endif
}
inline static bool IRAM_ATTR esp_ptr_word_aligned(const void *p)
{
return ((intptr_t)p) % 4 == 0;
}
inline static bool IRAM_ATTR esp_ptr_executable(const void *p)
{
intptr_t ip = (intptr_t) p;
return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH)
|| (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH)
|| (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH)
#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_FREERTOS_UNICORE)
|| (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
#endif
|| (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
{
intptr_t ip = (intptr_t) p;
bool r;
r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH);
#if CONFIG_SPIRAM
#if CONFIG_SPIRAM_SIZE != -1 // Fixed size, can be more accurate
r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE));
#else
r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_HIGH));
#endif
#endif
return r;
}
inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
bool r;
r = ((intptr_t)p >= SOC_MEM_INTERNAL_LOW && (intptr_t)p < SOC_MEM_INTERNAL_HIGH);
r |= ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
return r;
}
inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) {
return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) {
#if !CONFIG_FREERTOS_UNICORE || CONFIG_IDF_TARGET_ESP32S2
return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
#else
return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
#endif
}
inline static bool IRAM_ATTR esp_ptr_in_drom(const void *p) {
return ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < SOC_DROM_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_in_dram(const void *p) {
return ((intptr_t)p >= SOC_DRAM_LOW && (intptr_t)p < SOC_DRAM_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_in_diram_dram(const void *p) {
return ((intptr_t)p >= SOC_DIRAM_DRAM_LOW && (intptr_t)p < SOC_DIRAM_DRAM_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) {
return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_in_rtc_iram_fast(const void *p) {
return ((intptr_t)p >= SOC_RTC_IRAM_LOW && (intptr_t)p < SOC_RTC_IRAM_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_in_rtc_dram_fast(const void *p) {
return ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH);
}
inline static bool IRAM_ATTR esp_ptr_in_rtc_slow(const void *p) {
return ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
}
/* Convert a D/IRAM DRAM pointer to equivalent word address in IRAM
- Address must be word aligned
- Address must pass esp_ptr_in_diram_dram() test, or result will be invalid pointer
*/
inline static void * IRAM_ATTR esp_ptr_diram_dram_to_iram(const void *p) {
#if SOC_DIRAM_INVERTED
return (void *) ( SOC_DIRAM_IRAM_LOW + (SOC_DIRAM_DRAM_HIGH - (intptr_t)p) - 4);
#else
return (void *) ( SOC_DIRAM_IRAM_LOW + ((intptr_t)p - SOC_DIRAM_DRAM_LOW) );
#endif
}
/* Convert a D/IRAM IRAM pointer to equivalent word address in DRAM
- Address must be word aligned
- Address must pass esp_ptr_in_diram_iram() test, or result will be invalid pointer
*/
inline static void * IRAM_ATTR esp_ptr_diram_iram_to_dram(const void *p) {
#if SOC_DIRAM_INVERTED
return (void *) ( SOC_DIRAM_DRAM_LOW + (SOC_DIRAM_IRAM_HIGH - (intptr_t)p) - 4);
#else
return (void *) ( SOC_DIRAM_DRAM_LOW + ((intptr_t)p - SOC_DIRAM_IRAM_LOW) );
#endif
}
inline static bool IRAM_ATTR esp_stack_ptr_in_dram(uint32_t sp)
{
//Check if stack ptr is in between SOC_DRAM_LOW and SOC_DRAM_HIGH, and 16 byte aligned.
return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0));
}
#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
inline static bool IRAM_ATTR esp_stack_ptr_in_extram(uint32_t sp)
{
//Check if stack ptr is in between SOC_EXTRAM_DATA_LOW and SOC_EXTRAM_DATA_HIGH, and 16 byte aligned.
return !(sp < SOC_EXTRAM_DATA_LOW + 0x10 || sp > SOC_EXTRAM_DATA_HIGH - 0x10 || ((sp & 0xF) != 0));
}
#endif
inline static bool IRAM_ATTR esp_stack_ptr_is_sane(uint32_t sp)
{
#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
return (esp_stack_ptr_in_dram(sp) || esp_stack_ptr_in_extram(sp));
#else
return esp_stack_ptr_in_dram(sp);
#endif
}
tools/sdk/esp32s2/include/soc/include/soc/spinlock.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __SOC_SPINLOCK_H
#define __SOC_SPINLOCK_H
#include <stdint.h>
#include <stdbool.h>
#include "soc/cpu.h"
#include "soc/soc_memory_layout.h"
#include "soc/compare_set.h"
#include "xtensa/xtruntime.h"
#ifdef CONFIG_SPIRAM_WORKAROUND_NEED_VOLATILE_SPINLOCK
#define NEED_VOLATILE_MUX volatile
#else
#define NEED_VOLATILE_MUX
#endif
#define SPINLOCK_FREE 0xB33FFFFF
#define SPINLOCK_WAIT_FOREVER (-1)
#define SPINLOCK_NO_WAIT 0
#define SPINLOCK_INITIALIZER {.owner = SPINLOCK_FREE,.count = 0}
#define CORE_ID_REGVAL_XOR_SWAP (0xCDCD ^ 0xABAB)
typedef struct {
NEED_VOLATILE_MUX uint32_t owner;
NEED_VOLATILE_MUX uint32_t count;
}spinlock_t;
/**
* @brief Initialize a lock to its default state - unlocked
* @param lock - spinlock object to initialize
*/
static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t *lock)
{
assert(lock);
#if !CONFIG_FREERTOS_UNICORE
lock->owner = SPINLOCK_FREE;
lock->count = 0;
#endif
}
/**
* @brief Top level spinlock acquire function, spins until get the lock
* @param lock - target spinlock object
* @param timeout - cycles to wait, passing SPINLOCK_WAIT_FOREVER blocs indefinitely
*/
static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *lock, int32_t timeout)
{
#if !CONFIG_FREERTOS_UNICORE
uint32_t result;
uint32_t irq_status;
uint32_t ccount_start;
uint32_t core_id, other_core_id;
assert(lock);
irq_status = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL);
if(timeout != SPINLOCK_WAIT_FOREVER){
RSR(CCOUNT, ccount_start);
}
/*spin until we own a core */
RSR(PRID, core_id);
/* Note: coreID is the full 32 bit core ID (CORE_ID_REGVAL_PRO/CORE_ID_REGVAL_APP) */
other_core_id = CORE_ID_REGVAL_XOR_SWAP ^ core_id;
do {
/* lock->owner should be one of SPINLOCK_FREE, CORE_ID_REGVAL_PRO,
* CORE_ID_REGVAL_APP:
* - If SPINLOCK_FREE, we want to atomically set to 'core_id'.
* - If "our" core_id, we can drop through immediately.
* - If "other_core_id", we spin here.
*/
result = core_id;
#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
if (esp_ptr_external_ram(lock)) {
compare_and_set_extram(&lock->owner, SPINLOCK_FREE, &result);
} else {
#endif
compare_and_set_native(&lock->owner, SPINLOCK_FREE, &result);
#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
}
#endif
if(result != other_core_id) {
break;
}
if (timeout != SPINLOCK_WAIT_FOREVER) {
uint32_t ccount_now;
RSR(CCOUNT, ccount_now);
if (ccount_now - ccount_start > (unsigned)timeout) {
XTOS_RESTORE_INTLEVEL(irq_status);
return false;
}
}
}while(1);
/* any other value implies memory corruption or uninitialized mux */
assert(result == core_id || result == SPINLOCK_FREE);
assert((result == SPINLOCK_FREE) == (lock->count == 0)); /* we're first to lock iff count is zero */
assert(lock->count < 0xFF); /* Bad count value implies memory corruption */
lock->count++;
XTOS_RESTORE_INTLEVEL(irq_status);
return true;
#else
return true;
#endif
}
/**
* @brief Top level spinlock unlock function, unlocks a previously locked spinlock
* @param lock - target, locked before, spinlock object
*/
static inline void __attribute__((always_inline)) spinlock_release(spinlock_t *lock)
{
#if !CONFIG_FREERTOS_UNICORE
uint32_t irq_status;
uint32_t core_id;
assert(lock);
irq_status = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL);
RSR(PRID, core_id);
assert(core_id == lock->owner); // This is a mutex we didn't lock, or it's corrupt
lock->count--;
if(!lock->count) {
lock->owner = SPINLOCK_FREE;
} else {
assert(lock->count < 0x100); // Indicates memory corruption
}
XTOS_RESTORE_INTLEVEL(irq_status);
#endif
}
#endif
tools/sdk/esp32s2/include/soc/include/soc_log.h
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// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file soc_log.h
* @brief SOC library logging functions
*
* To make SOC library compatible with environments which don't use ESP-IDF,
* this header file provides wrappers for logging functions.
*/
#ifdef ESP_PLATFORM
#include "esp_log.h"
#define SOC_LOGE(tag, fmt, ...) ESP_EARLY_LOGE(tag, fmt, ##__VA_ARGS__)
#define SOC_LOGW(tag, fmt, ...) ESP_EARLY_LOGW(tag, fmt, ##__VA_ARGS__)
#define SOC_LOGI(tag, fmt, ...) ESP_EARLY_LOGI(tag, fmt, ##__VA_ARGS__)
#define SOC_LOGD(tag, fmt, ...) ESP_EARLY_LOGD(tag, fmt, ##__VA_ARGS__)
#define SOC_LOGV(tag, fmt, ...) ESP_EARLY_LOGV(tag, fmt, ##__VA_ARGS__)
#else
#include "sdkconfig.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
#define SOC_LOGE(tag, fmt, ...) ets_printf("%s(err): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGW(tag, fmt, ...) ets_printf("%s(warn): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGI(tag, fmt, ...) ets_printf("%s(info): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGD(tag, fmt, ...) ets_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGV(tag, fmt, ...) ets_printf("%s: " fmt, tag, ##__VA_ARGS__)
#endif //ESP_PLATFORM
tools/sdk/esp32s2/include/soc/soc/esp32s2/i2c_apll.h
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file i2c_apll.h
* @brief Register definitions for audio PLL (APLL)
*
* This file lists register fields of APLL, located on an internal configuration
* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
* rtc_clk_apll_enable function in rtc_clk.c.
*/
#define I2C_APLL 0X6D
#define I2C_APLL_HOSTID 1
#define I2C_APLL_IR_CAL_DELAY 0
#define I2C_APLL_IR_CAL_DELAY_MSB 3
#define I2C_APLL_IR_CAL_DELAY_LSB 0
#define I2C_APLL_IR_CAL_RSTB 0
#define I2C_APLL_IR_CAL_RSTB_MSB 4
#define I2C_APLL_IR_CAL_RSTB_LSB 4
#define I2C_APLL_IR_CAL_START 0
#define I2C_APLL_IR_CAL_START_MSB 5
#define I2C_APLL_IR_CAL_START_LSB 5
#define I2C_APLL_IR_CAL_UNSTOP 0
#define I2C_APLL_IR_CAL_UNSTOP_MSB 6
#define I2C_APLL_IR_CAL_UNSTOP_LSB 6
#define I2C_APLL_OC_ENB_FCAL 0
#define I2C_APLL_OC_ENB_FCAL_MSB 7
#define I2C_APLL_OC_ENB_FCAL_LSB 7
#define I2C_APLL_IR_CAL_EXT_CAP 1
#define I2C_APLL_IR_CAL_EXT_CAP_MSB 4
#define I2C_APLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_APLL_IR_CAL_ENX_CAP 1
#define I2C_APLL_IR_CAL_ENX_CAP_MSB 5
#define I2C_APLL_IR_CAL_ENX_CAP_LSB 5
#define I2C_APLL_OC_LBW 1
#define I2C_APLL_OC_LBW_MSB 6
#define I2C_APLL_OC_LBW_LSB 6
#define I2C_APLL_IR_CAL_CK_DIV 2
#define I2C_APLL_IR_CAL_CK_DIV_MSB 3
#define I2C_APLL_IR_CAL_CK_DIV_LSB 0
#define I2C_APLL_OC_DCHGP 2
#define I2C_APLL_OC_DCHGP_MSB 6
#define I2C_APLL_OC_DCHGP_LSB 4
#define I2C_APLL_OC_ENB_VCON 2
#define I2C_APLL_OC_ENB_VCON_MSB 7
#define I2C_APLL_OC_ENB_VCON_LSB 7
#define I2C_APLL_OR_CAL_CAP 3
#define I2C_APLL_OR_CAL_CAP_MSB 4
#define I2C_APLL_OR_CAL_CAP_LSB 0
#define I2C_APLL_OR_CAL_UDF 3
#define I2C_APLL_OR_CAL_UDF_MSB 5
#define I2C_APLL_OR_CAL_UDF_LSB 5
#define I2C_APLL_OR_CAL_OVF 3
#define I2C_APLL_OR_CAL_OVF_MSB 6
#define I2C_APLL_OR_CAL_OVF_LSB 6
#define I2C_APLL_OR_CAL_END 3
#define I2C_APLL_OR_CAL_END_MSB 7
#define I2C_APLL_OR_CAL_END_LSB 7
#define I2C_APLL_OR_OUTPUT_DIV 4
#define I2C_APLL_OR_OUTPUT_DIV_MSB 4
#define I2C_APLL_OR_OUTPUT_DIV_LSB 0
#define I2C_APLL_OC_TSCHGP 4
#define I2C_APLL_OC_TSCHGP_MSB 6
#define I2C_APLL_OC_TSCHGP_LSB 6
#define I2C_APLL_EN_FAST_CAL 4
#define I2C_APLL_EN_FAST_CAL_MSB 7
#define I2C_APLL_EN_FAST_CAL_LSB 7
#define I2C_APLL_OC_DHREF_SEL 5
#define I2C_APLL_OC_DHREF_SEL_MSB 1
#define I2C_APLL_OC_DHREF_SEL_LSB 0
#define I2C_APLL_OC_DLREF_SEL 5
#define I2C_APLL_OC_DLREF_SEL_MSB 3
#define I2C_APLL_OC_DLREF_SEL_LSB 2
#define I2C_APLL_SDM_DITHER 5
#define I2C_APLL_SDM_DITHER_MSB 4
#define I2C_APLL_SDM_DITHER_LSB 4
#define I2C_APLL_SDM_STOP 5
#define I2C_APLL_SDM_STOP_MSB 5
#define I2C_APLL_SDM_STOP_LSB 5
#define I2C_APLL_SDM_RSTB 5
#define I2C_APLL_SDM_RSTB_MSB 6
#define I2C_APLL_SDM_RSTB_LSB 6
#define I2C_APLL_OC_DVDD 6
#define I2C_APLL_OC_DVDD_MSB 4
#define I2C_APLL_OC_DVDD_LSB 0
#define I2C_APLL_DSDM2 7
#define I2C_APLL_DSDM2_MSB 5
#define I2C_APLL_DSDM2_LSB 0
#define I2C_APLL_DSDM1 8
#define I2C_APLL_DSDM1_MSB 7
#define I2C_APLL_DSDM1_LSB 0
#define I2C_APLL_DSDM0 9
#define I2C_APLL_DSDM0_MSB 7
#define I2C_APLL_DSDM0_LSB 0
tools/sdk/esp32s2/include/soc/soc/esp32s2/i2c_bbpll.h
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file i2c_apll.h
* @brief Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal configuration
* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
* rtc_clk_cpu_freq_set function in rtc_clk.c.
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 1
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
#define I2C_BBPLL_IR_CAL_RSTB 1
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
#define I2C_BBPLL_IR_CAL_START 1
#define I2C_BBPLL_IR_CAL_START_MSB 6
#define I2C_BBPLL_IR_CAL_START_LSB 6
#define I2C_BBPLL_IR_CAL_UNSTOP 1
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
#define I2C_BBPLL_OC_REF_DIV 2
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_ENB_FCAL 2
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_RSTB_DIV_ADC 4
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_DIV_ADC 4
#define I2C_BBPLL_DIV_ADC_MSB 3
#define I2C_BBPLL_DIV_ADC_LSB 2
#define I2C_BBPLL_DIV_DAC 4
#define I2C_BBPLL_DIV_DAC_MSB 4
#define I2C_BBPLL_DIV_DAC_LSB 4
#define I2C_BBPLL_DIV_CPU 4
#define I2C_BBPLL_DIV_CPU_MSB 5
#define I2C_BBPLL_DIV_CPU_LSB 5
#define I2C_BBPLL_OC_ENB_VCON 4
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 7
#define I2C_BBPLL_OC_TSCHGP_LSB 7
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_EN_USB 5
#define I2C_BBPLL_EN_USB_MSB 7
#define I2C_BBPLL_EN_USB_LSB 7
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_INC_CUR 6
#define I2C_BBPLL_INC_CUR_MSB 3
#define I2C_BBPLL_INC_CUR_LSB 3
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
#define I2C_BBPLL_OR_CAL_CAP 8
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
#define I2C_BBPLL_OR_CAL_UDF 8
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
#define I2C_BBPLL_OR_CAL_OVF 8
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
#define I2C_BBPLL_OR_CAL_END 8
#define I2C_BBPLL_OR_CAL_END_MSB 6
#define I2C_BBPLL_OR_CAL_END_LSB 6
#define I2C_BBPLL_OR_LOCK 8
#define I2C_BBPLL_OR_LOCK_MSB 7
#define I2C_BBPLL_OR_LOCK_LSB 7
#define I2C_BBPLL_BBADC_DELAY1 9
#define I2C_BBPLL_BBADC_DELAY1_MSB 1
#define I2C_BBPLL_BBADC_DELAY1_LSB 0
#define I2C_BBPLL_BBADC_DELAY2 9
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
#define I2C_BBPLL_BBADC_DVDD 9
#define I2C_BBPLL_BBADC_DVDD_MSB 5
#define I2C_BBPLL_BBADC_DVDD_LSB 4
#define I2C_BBPLL_BBADC_DREF 9
#define I2C_BBPLL_BBADC_DREF_MSB 7
#define I2C_BBPLL_BBADC_DREF_LSB 6
#define I2C_BBPLL_BBADC_DCUR 10
#define I2C_BBPLL_BBADC_DCUR_MSB 1
#define I2C_BBPLL_BBADC_DCUR_LSB 0
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 5
#define I2C_BBPLL_DTEST_LSB 4
#define I2C_BBPLL_ENT_ADC 10
#define I2C_BBPLL_ENT_ADC_MSB 7
#define I2C_BBPLL_ENT_ADC_LSB 6
tools/sdk/esp32s2/include/soc/soc/esp32s2/i2c_ulp.h
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file i2c_ulp.h
* @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
*
* This file lists register fields of ULP, located on an internal configuration
* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
* rtc_init function in rtc_init.c.
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 1
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_O_DONE_FLAG 3
#define I2C_ULP_O_DONE_FLAG_MSB 0
#define I2C_ULP_O_DONE_FLAG_LSB 0
#define I2C_ULP_BG_O_DONE_FLAG 3
#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/adc_caps.h
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#pragma once
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
#define SOC_ADC1_DATA_INVERT_DEFAULT (0)
#define SOC_ADC2_DATA_INVERT_DEFAULT (0)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2)
/**
* Check if adc support digital controller (DMA) mode.
* @value
* - 1 : support;
* - 0 : not support;
*/
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1)
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/adc_channel.h
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_ADC_CHANNEL_H
#define _SOC_ADC_CHANNEL_H
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0
#define ADC1_CHANNEL_0_GPIO_NUM 1
#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_1
#define ADC1_CHANNEL_1_GPIO_NUM 2
#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_2
#define ADC1_CHANNEL_2_GPIO_NUM 3
#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_3
#define ADC1_CHANNEL_3_GPIO_NUM 4
#define ADC1_GPIO5_CHANNEL ADC1_CHANNEL_4
#define ADC1_CHANNEL_4_GPIO_NUM 5
#define ADC1_GPIO6_CHANNEL ADC1_CHANNEL_5
#define ADC1_CHANNEL_5_GPIO_NUM 6
#define ADC1_GPIO7_CHANNEL ADC1_CHANNEL_6
#define ADC1_CHANNEL_6_GPIO_NUM 7
#define ADC1_GPIO8_CHANNEL ADC1_CHANNEL_7
#define ADC1_CHANNEL_7_GPIO_NUM 8
#define ADC1_GPIO9_CHANNEL ADC1_CHANNEL_8
#define ADC1_CHANNEL_8_GPIO_NUM 9
#define ADC1_GPIO10_CHANNEL ADC1_CHANNEL_9
#define ADC1_CHANNEL_9_GPIO_NUM 10
#define ADC2_GPIO11_CHANNEL ADC2_CHANNEL_0
#define ADC2_CHANNEL_0_GPIO_NUM 11
#define ADC2_GPIO12_CHANNEL ADC2_CHANNEL_1
#define ADC2_CHANNEL_1_GPIO_NUM 12
#define ADC2_GPIO13_CHANNEL ADC2_CHANNEL_2
#define ADC2_CHANNEL_2_GPIO_NUM 13
#define ADC2_GPIO14_CHANNEL ADC2_CHANNEL_3
#define ADC2_CHANNEL_3_GPIO_NUM 14
#define ADC2_GPIO15_CHANNEL ADC2_CHANNEL_4
#define ADC2_CHANNEL_4_GPIO_NUM 15
#define ADC2_GPIO16_CHANNEL ADC2_CHANNEL_5
#define ADC2_CHANNEL_5_GPIO_NUM 16
#define ADC2_GPIO17_CHANNEL ADC2_CHANNEL_6
#define ADC2_CHANNEL_6_GPIO_NUM 17
#define ADC2_GPIO18_CHANNEL ADC2_CHANNEL_7
#define ADC2_CHANNEL_7_GPIO_NUM 18
#define ADC2_GPIO19_CHANNEL ADC2_CHANNEL_8
#define ADC2_CHANNEL_8_GPIO_NUM 19
#define ADC2_GPIO20_CHANNEL ADC2_CHANNEL_9
#define ADC2_CHANNEL_9_GPIO_NUM 20
#endif
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/apb_ctrl_reg.h
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_APB_CTRL_REG_H_
#define _SOC_APB_CTRL_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000)
/* APB_CTRL_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
/*description: */
#define APB_CTRL_SOC_CLK_SEL 0x00000003
#define APB_CTRL_SOC_CLK_SEL_M ((APB_CTRL_SOC_CLK_SEL_V)<<(APB_CTRL_SOC_CLK_SEL_S))
#define APB_CTRL_SOC_CLK_SEL_V 0x3
#define APB_CTRL_SOC_CLK_SEL_S 14
#define APB_CTRL_SOC_CLK_SEL_XTL 0
#define APB_CTRL_SOC_CLK_SEL_PLL 1
#define APB_CTRL_SOC_CLK_SEL_8M 2
#define APB_CTRL_SOC_CLK_SEL_APLL 3
/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_RST_TICK_CNT (BIT(12))
#define APB_CTRL_RST_TICK_CNT_M (BIT(12))
#define APB_CTRL_RST_TICK_CNT_V 0x1
#define APB_CTRL_RST_TICK_CNT_S 12
/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_CLK_EN (BIT(11))
#define APB_CTRL_CLK_EN_M (BIT(11))
#define APB_CTRL_CLK_EN_V 0x1
#define APB_CTRL_CLK_EN_S 11
/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_CLK_320M_EN (BIT(10))
#define APB_CTRL_CLK_320M_EN_M (BIT(10))
#define APB_CTRL_CLK_320M_EN_V 0x1
#define APB_CTRL_CLK_320M_EN_S 10
/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
/*description: */
#define APB_CTRL_PRE_DIV_CNT 0x000003FF
#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
#define APB_CTRL_PRE_DIV_CNT_S 0
#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x004)
/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
/*description: */
#define APB_CTRL_TICK_ENABLE (BIT(16))
#define APB_CTRL_TICK_ENABLE_M (BIT(16))
#define APB_CTRL_TICK_ENABLE_V 0x1
#define APB_CTRL_TICK_ENABLE_S 16
/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: */
#define APB_CTRL_CK8M_TICK_NUM 0x000000FF
#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
#define APB_CTRL_CK8M_TICK_NUM_V 0xFF
#define APB_CTRL_CK8M_TICK_NUM_S 8
/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
/*description: */
#define APB_CTRL_XTAL_TICK_NUM 0x000000FF
#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
#define APB_CTRL_XTAL_TICK_NUM_V 0xFF
#define APB_CTRL_XTAL_TICK_NUM_S 0
#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008)
/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_V 0x1
#define APB_CTRL_CLK_XTAL_OEN_S 10
/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK40X_BB_OEN (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_V 0x1
#define APB_CTRL_CLK40X_BB_OEN_S 9
/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8))
#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8))
#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1
#define APB_CTRL_CLK_DAC_CPU_OEN_S 8
/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7))
#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7))
#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1
#define APB_CTRL_CLK_ADC_INF_OEN_S 7
/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_320M_OEN (BIT(6))
#define APB_CTRL_CLK_320M_OEN_M (BIT(6))
#define APB_CTRL_CLK_320M_OEN_V 0x1
#define APB_CTRL_CLK_320M_OEN_S 6
/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK160_OEN (BIT(5))
#define APB_CTRL_CLK160_OEN_M (BIT(5))
#define APB_CTRL_CLK160_OEN_V 0x1
#define APB_CTRL_CLK160_OEN_S 5
/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK80_OEN (BIT(4))
#define APB_CTRL_CLK80_OEN_M (BIT(4))
#define APB_CTRL_CLK80_OEN_V 0x1
#define APB_CTRL_CLK80_OEN_S 4
/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_BB_OEN (BIT(3))
#define APB_CTRL_CLK_BB_OEN_M (BIT(3))
#define APB_CTRL_CLK_BB_OEN_V 0x1
#define APB_CTRL_CLK_BB_OEN_S 3
/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK44_OEN (BIT(2))
#define APB_CTRL_CLK44_OEN_M (BIT(2))
#define APB_CTRL_CLK44_OEN_V 0x1
#define APB_CTRL_CLK44_OEN_S 2
/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK22_OEN (BIT(1))
#define APB_CTRL_CLK22_OEN_M (BIT(1))
#define APB_CTRL_CLK22_OEN_V 0x1
#define APB_CTRL_CLK22_OEN_S 1
/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK20_OEN (BIT(0))
#define APB_CTRL_CLK20_OEN_M (BIT(0))
#define APB_CTRL_CLK20_OEN_V 0x1
#define APB_CTRL_CLK20_OEN_S 0
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x00C)
/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define APB_CTRL_PERI_IO_SWAP 0x000000FF
#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
#define APB_CTRL_PERI_IO_SWAP_V 0xFF
#define APB_CTRL_PERI_IO_SWAP_S 0
#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x010)
/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x014)
/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_ATTR 0x00000007
#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
#define APB_CTRL_FLASH_ACE0_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE0_ATTR_S 0
#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x018)
/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_ATTR 0x00000007
#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
#define APB_CTRL_FLASH_ACE1_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE1_ATTR_S 0
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x01C)
/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_ATTR 0x00000007
#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
#define APB_CTRL_FLASH_ACE2_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE2_ATTR_S 0
#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x020)
/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_ATTR 0x00000007
#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
#define APB_CTRL_FLASH_ACE3_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE3_ATTR_S 0
#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x024)
/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x028)
/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x02C)
/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x030)
/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x034)
/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
#define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE0_SIZE_S 0
#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x038)
/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
#define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE1_SIZE_S 0
#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x03C)
/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
#define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE2_SIZE_S 0
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x040)
/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
#define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE3_SIZE_S 0
#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x044)
/* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE0_ATTR 0x00000007
#define APB_CTRL_SRAM_ACE0_ATTR_M ((APB_CTRL_SRAM_ACE0_ATTR_V)<<(APB_CTRL_SRAM_ACE0_ATTR_S))
#define APB_CTRL_SRAM_ACE0_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE0_ATTR_S 0
#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x048)
/* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE1_ATTR 0x00000007
#define APB_CTRL_SRAM_ACE1_ATTR_M ((APB_CTRL_SRAM_ACE1_ATTR_V)<<(APB_CTRL_SRAM_ACE1_ATTR_S))
#define APB_CTRL_SRAM_ACE1_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE1_ATTR_S 0
#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x04C)
/* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE2_ATTR 0x00000007
#define APB_CTRL_SRAM_ACE2_ATTR_M ((APB_CTRL_SRAM_ACE2_ATTR_V)<<(APB_CTRL_SRAM_ACE2_ATTR_S))
#define APB_CTRL_SRAM_ACE2_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE2_ATTR_S 0
#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x050)
/* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE3_ATTR 0x00000007
#define APB_CTRL_SRAM_ACE3_ATTR_M ((APB_CTRL_SRAM_ACE3_ATTR_V)<<(APB_CTRL_SRAM_ACE3_ATTR_S))
#define APB_CTRL_SRAM_ACE3_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE3_ATTR_S 0
#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x054)
/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE0_ADDR_S_M ((APB_CTRL_SRAM_ACE0_ADDR_S_V)<<(APB_CTRL_SRAM_ACE0_ADDR_S_S))
#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x058)
/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE1_ADDR_S_M ((APB_CTRL_SRAM_ACE1_ADDR_S_V)<<(APB_CTRL_SRAM_ACE1_ADDR_S_S))
#define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE1_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x05C)
/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE2_ADDR_S_M ((APB_CTRL_SRAM_ACE2_ADDR_S_V)<<(APB_CTRL_SRAM_ACE2_ADDR_S_S))
#define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE2_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x060)
/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE3_ADDR_S_M ((APB_CTRL_SRAM_ACE3_ADDR_S_V)<<(APB_CTRL_SRAM_ACE3_ADDR_S_S))
#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x064)
/* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE0_SIZE_M ((APB_CTRL_SRAM_ACE0_SIZE_V)<<(APB_CTRL_SRAM_ACE0_SIZE_S))
#define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE0_SIZE_S 0
#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x068)
/* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE1_SIZE_M ((APB_CTRL_SRAM_ACE1_SIZE_V)<<(APB_CTRL_SRAM_ACE1_SIZE_S))
#define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE1_SIZE_S 0
#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x06C)
/* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE2_SIZE_M ((APB_CTRL_SRAM_ACE2_SIZE_V)<<(APB_CTRL_SRAM_ACE2_SIZE_S))
#define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE2_SIZE_S 0
#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x070)
/* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE3_SIZE_M ((APB_CTRL_SRAM_ACE3_SIZE_V)<<(APB_CTRL_SRAM_ACE3_SIZE_S))
#define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE3_SIZE_S 0
#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x074)
/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F
#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F
#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2
/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0))
#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_INT_S 0
#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x078)
/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x07C)
/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x080)
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_REDCY_ANDOR (BIT(31))
#define APB_CTRL_REDCY_ANDOR_M (BIT(31))
#define APB_CTRL_REDCY_ANDOR_V 0x1
#define APB_CTRL_REDCY_ANDOR_S 31
/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_S 0
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x084)
/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_REDCY_NANDOR (BIT(31))
#define APB_CTRL_REDCY_NANDOR_M (BIT(31))
#define APB_CTRL_REDCY_NANDOR_V 0x1
#define APB_CTRL_REDCY_NANDOR_S 31
/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_S 0
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x088)
/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_S 0
#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x08C)
/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_S 0
#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x090)
/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_S 0
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x094)
/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_RST 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_S 0
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x098)
/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5))
#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PD_S 5
/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3))
#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3
/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1))
#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1))
#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PD_S 1
/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC)
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h1906210 ; */
/*description: */
#define APB_CTRL_DATE 0xFFFFFFFF
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
#define APB_CTRL_DATE_V 0xFFFFFFFF
#define APB_CTRL_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_CTRL_REG_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/apb_ctrl_struct.h
+463
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@@ -0,0 +1,463 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_APB_CTRL_STRUCT_H_
#define _SOC_APB_CTRL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t pre_div: 10;
uint32_t clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t rst_tick: 1;
uint32_t reserved13: 1;
uint32_t soc_clk_sel: 2;
uint32_t reserved16: 16;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t xtal_tick: 8;
uint32_t ck8m_tick: 8;
uint32_t tick_enable: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} tick_conf;
union {
struct {
uint32_t clk20_oen: 1;
uint32_t clk22_oen: 1;
uint32_t clk44_oen: 1;
uint32_t clk_bb_oen: 1;
uint32_t clk80_oen: 1;
uint32_t clk160_oen: 1;
uint32_t clk_320m_oen: 1;
uint32_t clk_adc_inf_oen: 1;
uint32_t clk_dac_cpu_oen: 1;
uint32_t clk40x_bb_oen: 1;
uint32_t clk_xtal_oen: 1;
uint32_t reserved11: 21;
};
uint32_t val;
} clk_out_en;
union {
struct {
uint32_t peri_io_swap: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} host_inf_sel;
union {
struct {
uint32_t ext_mem_pms_lock: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} ext_mem_pms_lock;
union {
struct {
uint32_t flash_ace0_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} flash_ace0_attr;
union {
struct {
uint32_t flash_ace1_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} flash_ace1_attr;
union {
struct {
uint32_t flash_ace2_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} flash_ace2_attr;
union {
struct {
uint32_t flash_ace3_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} flash_ace3_attr;
uint32_t flash_ace0_addr; /**/
uint32_t flash_ace1_addr; /**/
uint32_t flash_ace2_addr; /**/
uint32_t flash_ace3_addr; /**/
union {
struct {
uint32_t flash_ace0_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace0_size;
union {
struct {
uint32_t flash_ace1_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace1_size;
union {
struct {
uint32_t flash_ace2_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace2_size;
union {
struct {
uint32_t flash_ace3_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace3_size;
union {
struct {
uint32_t sram_ace0_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} sram_ace0_attr;
union {
struct {
uint32_t sram_ace1_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} sram_ace1_attr;
union {
struct {
uint32_t sram_ace2_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} sram_ace2_attr;
union {
struct {
uint32_t sram_ace3_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} sram_ace3_attr;
uint32_t sram_ace0_addr; /**/
uint32_t sram_ace1_addr; /**/
uint32_t sram_ace2_addr; /**/
uint32_t sram_ace3_addr; /**/
union {
struct {
uint32_t sram_ace0_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace0_size;
union {
struct {
uint32_t sram_ace1_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace1_size;
union {
struct {
uint32_t sram_ace2_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace2_size;
union {
struct {
uint32_t sram_ace3_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace3_size;
union {
struct {
uint32_t spi_mem_reject_int: 1;
uint32_t spi_mem_reject_clr: 1;
uint32_t spi_mem_reject_cde: 5;
uint32_t reserved7: 25;
};
uint32_t val;
} spi_mem_pms_ctrl;
uint32_t spi_mem_reject_addr; /**/
union {
struct {
uint32_t sdio_win_access_en: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} sdio_ctrl;
union {
struct {
uint32_t redcy_sig0: 31;
uint32_t redcy_andor: 1;
};
uint32_t val;
} redcy_sig0;
union {
struct {
uint32_t redcy_sig1: 31;
uint32_t redcy_nandor: 1;
};
uint32_t val;
} redcy_sig1;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t wifi_clk_en; /**/
uint32_t wifi_rst_en; /**/
union {
struct {
uint32_t agc_mem_force_pu: 1;
uint32_t agc_mem_force_pd: 1;
uint32_t pbus_mem_force_pu: 1;
uint32_t pbus_mem_force_pd: 1;
uint32_t dc_mem_force_pu: 1;
uint32_t dc_mem_force_pd: 1;
uint32_t reserved6: 26;
};
uint32_t val;
} front_end_mem_pd;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t date; /**/
} apb_ctrl_dev_t;
extern apb_ctrl_dev_t APB_CTRL;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_APB_CTRL_STRUCT_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/apb_saradc_reg.h
+618
View File
@@ -0,0 +1,618 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_APB_SARADC_REG_H_
#define _SOC_APB_SARADC_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000)
/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
/*description: wait arbit signal stable after sar_done*/
#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003
#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3
#define APB_SARADC_WAIT_ARB_CYCLE_S 30
/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: force option to xpd sar blocks*/
#define APB_SARADC_XPD_SAR_FORCE 0x00000003
#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
#define APB_SARADC_XPD_SAR_FORCE_V 0x3
#define APB_SARADC_XPD_SAR_FORCE_S 27
/* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data
is from GPIO matrix*/
#define APB_SARADC_DATA_TO_I2S (BIT(26))
#define APB_SARADC_DATA_TO_I2S_M (BIT(26))
#define APB_SARADC_DATA_TO_I2S_V 0x1
#define APB_SARADC_DATA_TO_I2S_S 26
/* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
in this case the resolution should not be larger than 11 bits.*/
#define APB_SARADC_DATA_SAR_SEL (BIT(25))
#define APB_SARADC_DATA_SAR_SEL_M (BIT(25))
#define APB_SARADC_DATA_SAR_SEL_V 0x1
#define APB_SARADC_DATA_SAR_SEL_S 25
/* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
#define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
#define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
#define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1
#define APB_SARADC_SAR2_PATT_P_CLEAR_S 24
/* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
#define APB_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
#define APB_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
#define APB_SARADC_SAR1_PATT_P_CLEAR_V 0x1
#define APB_SARADC_SAR1_PATT_P_CLEAR_S 23
/* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define APB_SARADC_SAR2_PATT_LEN 0x0000000F
#define APB_SARADC_SAR2_PATT_LEN_M ((APB_SARADC_SAR2_PATT_LEN_V)<<(APB_SARADC_SAR2_PATT_LEN_S))
#define APB_SARADC_SAR2_PATT_LEN_V 0xF
#define APB_SARADC_SAR2_PATT_LEN_S 19
/* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define APB_SARADC_SAR1_PATT_LEN 0x0000000F
#define APB_SARADC_SAR1_PATT_LEN_M ((APB_SARADC_SAR1_PATT_LEN_V)<<(APB_SARADC_SAR1_PATT_LEN_S))
#define APB_SARADC_SAR1_PATT_LEN_V 0xF
#define APB_SARADC_SAR1_PATT_LEN_S 15
/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
/*description: SAR clock divider*/
#define APB_SARADC_SAR_CLK_DIV 0x000000FF
#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
#define APB_SARADC_SAR_CLK_DIV_V 0xFF
#define APB_SARADC_SAR_CLK_DIV_S 7
/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define APB_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_SARADC_SAR_CLK_GATED_M (BIT(6))
#define APB_SARADC_SAR_CLK_GATED_V 0x1
#define APB_SARADC_SAR_CLK_GATED_S 6
/* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/
#define APB_SARADC_SAR_SEL (BIT(5))
#define APB_SARADC_SAR_SEL_M (BIT(5))
#define APB_SARADC_SAR_SEL_V 0x1
#define APB_SARADC_SAR_SEL_S 5
/* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
/*description: 0: single mode 1: double mode 2: alternate mode*/
#define APB_SARADC_WORK_MODE 0x00000003
#define APB_SARADC_WORK_MODE_M ((APB_SARADC_WORK_MODE_V)<<(APB_SARADC_WORK_MODE_S))
#define APB_SARADC_WORK_MODE_V 0x3
#define APB_SARADC_WORK_MODE_S 3
/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_SARADC_START (BIT(1))
#define APB_SARADC_START_M (BIT(1))
#define APB_SARADC_START_V 0x1
#define APB_SARADC_START_S 1
/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_START_FORCE_M (BIT(0))
#define APB_SARADC_START_FORCE_V 0x1
#define APB_SARADC_START_FORCE_S 0
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004)
/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: to enable saradc timer trigger*/
#define APB_SARADC_TIMER_EN (BIT(24))
#define APB_SARADC_TIMER_EN_M (BIT(24))
#define APB_SARADC_TIMER_EN_V 0x1
#define APB_SARADC_TIMER_EN_S 24
/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
/*description: to set saradc timer target*/
#define APB_SARADC_TIMER_TARGET 0x00000FFF
#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
#define APB_SARADC_TIMER_TARGET_V 0xFFF
#define APB_SARADC_TIMER_TARGET_S 12
/* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
/*description: 1: select saradc timer 0: i2s_ws trigger*/
#define APB_SARADC_TIMER_SEL (BIT(11))
#define APB_SARADC_TIMER_SEL_M (BIT(11))
#define APB_SARADC_TIMER_SEL_V 0x1
#define APB_SARADC_TIMER_SEL_S 11
/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
#define APB_SARADC_SAR2_INV (BIT(10))
#define APB_SARADC_SAR2_INV_M (BIT(10))
#define APB_SARADC_SAR2_INV_V 0x1
#define APB_SARADC_SAR2_INV_S 10
/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
#define APB_SARADC_SAR1_INV (BIT(9))
#define APB_SARADC_SAR1_INV_M (BIT(9))
#define APB_SARADC_SAR1_INV_V 0x1
#define APB_SARADC_SAR1_INV_S 9
/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
/*description: max conversion number*/
#define APB_SARADC_MAX_MEAS_NUM 0x000000FF
#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
#define APB_SARADC_MAX_MEAS_NUM_V 0xFF
#define APB_SARADC_MAX_MEAS_NUM_S 1
/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1
#define APB_SARADC_MEAS_NUM_LIMIT_S 0
#define APB_SARADC_FSM_REG (DR_REG_APB_SARADC_BASE + 0x008)
/* APB_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
/*description: sample cycles*/
#define APB_SARADC_SAMPLE_CYCLE 0x000000FF
#define APB_SARADC_SAMPLE_CYCLE_M ((APB_SARADC_SAMPLE_CYCLE_V)<<(APB_SARADC_SAMPLE_CYCLE_S))
#define APB_SARADC_SAMPLE_CYCLE_V 0xFF
#define APB_SARADC_SAMPLE_CYCLE_S 24
/* APB_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */
/*description: sample number*/
#define APB_SARADC_SAMPLE_NUM 0x000000FF
#define APB_SARADC_SAMPLE_NUM_M ((APB_SARADC_SAMPLE_NUM_V)<<(APB_SARADC_SAMPLE_NUM_S))
#define APB_SARADC_SAMPLE_NUM_V 0xFF
#define APB_SARADC_SAMPLE_NUM_S 16
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C)
/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
/*description: */
#define APB_SARADC_STANDBY_WAIT 0x000000FF
#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
#define APB_SARADC_STANDBY_WAIT_V 0xFF
#define APB_SARADC_STANDBY_WAIT_S 16
/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
/*description: */
#define APB_SARADC_RSTB_WAIT 0x000000FF
#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
#define APB_SARADC_RSTB_WAIT_V 0xFF
#define APB_SARADC_RSTB_WAIT_S 8
/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
/*description: */
#define APB_SARADC_XPD_WAIT 0x000000FF
#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
#define APB_SARADC_XPD_WAIT_V 0xFF
#define APB_SARADC_XPD_WAIT_S 0
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010)
/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR1_STATUS_S 0
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014)
/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_S 0
#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018)
/* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
#define APB_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB1_M ((APB_SARADC_SAR1_PATT_TAB1_V)<<(APB_SARADC_SAR1_PATT_TAB1_S))
#define APB_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB1_S 0
#define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C)
/* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
#define APB_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB2_M ((APB_SARADC_SAR1_PATT_TAB2_V)<<(APB_SARADC_SAR1_PATT_TAB2_S))
#define APB_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB2_S 0
#define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x020)
/* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
#define APB_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V)<<(APB_SARADC_SAR1_PATT_TAB3_S))
#define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB3_S 0
#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x024)
/* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
#define APB_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB4_M ((APB_SARADC_SAR1_PATT_TAB4_V)<<(APB_SARADC_SAR1_PATT_TAB4_S))
#define APB_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB4_S 0
#define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x028)
/* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
#define APB_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB1_M ((APB_SARADC_SAR2_PATT_TAB1_V)<<(APB_SARADC_SAR2_PATT_TAB1_S))
#define APB_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB1_S 0
#define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x02C)
/* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
#define APB_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V)<<(APB_SARADC_SAR2_PATT_TAB2_S))
#define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB2_S 0
#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x030)
/* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
#define APB_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB3_M ((APB_SARADC_SAR2_PATT_TAB3_V)<<(APB_SARADC_SAR2_PATT_TAB3_S))
#define APB_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB3_S 0
#define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x034)
/* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
#define APB_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB4_M ((APB_SARADC_SAR2_PATT_TAB4_V)<<(APB_SARADC_SAR2_PATT_TAB4_S))
#define APB_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB4_S 0
#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038)
/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: adc2 arbiter uses fixed priority*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
/*description: Set adc2 arbiter wifi priority*/
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
/*description: Set adc2 arbiter rtc priority*/
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
/*description: Set adc2 arbiterapb priority*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: adc2 arbiter force grant*/
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable wifi controller*/
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable rtc controller*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enableapb controller*/
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
#define APB_SARADC_FILTER_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x03C)
/* APB_SARADC_ADC1_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: enable apb_adc1_filter*/
#define APB_SARADC_ADC1_FILTER_EN (BIT(31))
#define APB_SARADC_ADC1_FILTER_EN_M (BIT(31))
#define APB_SARADC_ADC1_FILTER_EN_V 0x1
#define APB_SARADC_ADC1_FILTER_EN_S 31
/* APB_SARADC_ADC2_FILTER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: enable apb_adc2_filter*/
#define APB_SARADC_ADC2_FILTER_EN (BIT(30))
#define APB_SARADC_ADC2_FILTER_EN_M (BIT(30))
#define APB_SARADC_ADC2_FILTER_EN_V 0x1
#define APB_SARADC_ADC2_FILTER_EN_S 30
/* APB_SARADC_ADC1_FILTER_FACTOR : R/W ;bitpos:[29:23] ;default: 7'd64 ; */
/*description: apb_adc1_filter_factor*/
#define APB_SARADC_ADC1_FILTER_FACTOR 0x0000007F
#define APB_SARADC_ADC1_FILTER_FACTOR_M ((APB_SARADC_ADC1_FILTER_FACTOR_V)<<(APB_SARADC_ADC1_FILTER_FACTOR_S))
#define APB_SARADC_ADC1_FILTER_FACTOR_V 0x7F
#define APB_SARADC_ADC1_FILTER_FACTOR_S 23
/* APB_SARADC_ADC2_FILTER_FACTOR : R/W ;bitpos:[22:16] ;default: 7'd64 ; */
/*description: apb_adc2_filter_factor*/
#define APB_SARADC_ADC2_FILTER_FACTOR 0x0000007F
#define APB_SARADC_ADC2_FILTER_FACTOR_M ((APB_SARADC_ADC2_FILTER_FACTOR_V)<<(APB_SARADC_ADC2_FILTER_FACTOR_S))
#define APB_SARADC_ADC2_FILTER_FACTOR_V 0x7F
#define APB_SARADC_ADC2_FILTER_FACTOR_S 16
/* APB_SARADC_ADC1_FILTER_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: reset_adc1_filter*/
#define APB_SARADC_ADC1_FILTER_RESET (BIT(1))
#define APB_SARADC_ADC1_FILTER_RESET_M (BIT(1))
#define APB_SARADC_ADC1_FILTER_RESET_V 0x1
#define APB_SARADC_ADC1_FILTER_RESET_S 1
/* APB_SARADC_ADC2_FILTER_RESET : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: reset_adc2_filter*/
#define APB_SARADC_ADC2_FILTER_RESET (BIT(0))
#define APB_SARADC_ADC2_FILTER_RESET_M (BIT(0))
#define APB_SARADC_ADC2_FILTER_RESET_V 0x1
#define APB_SARADC_ADC2_FILTER_RESET_S 0
#define APB_SARADC_FILTER_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x040)
/* APB_SARADC_ADC1_FILTER_DATA : RO ;bitpos:[31:16] ;default: 16'd0 ; */
/*description: */
#define APB_SARADC_ADC1_FILTER_DATA 0x0000FFFF
#define APB_SARADC_ADC1_FILTER_DATA_M ((APB_SARADC_ADC1_FILTER_DATA_V)<<(APB_SARADC_ADC1_FILTER_DATA_S))
#define APB_SARADC_ADC1_FILTER_DATA_V 0xFFFF
#define APB_SARADC_ADC1_FILTER_DATA_S 16
/* APB_SARADC_ADC2_FILTER_DATA : RO ;bitpos:[15:0] ;default: 16'd0 ; */
/*description: */
#define APB_SARADC_ADC2_FILTER_DATA 0x0000FFFF
#define APB_SARADC_ADC2_FILTER_DATA_M ((APB_SARADC_ADC2_FILTER_DATA_V)<<(APB_SARADC_ADC2_FILTER_DATA_S))
#define APB_SARADC_ADC2_FILTER_DATA_V 0xFFFF
#define APB_SARADC_ADC2_FILTER_DATA_S 0
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x044)
/* APB_SARADC_ADC1_THRES_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_EN (BIT(31))
#define APB_SARADC_ADC1_THRES_EN_M (BIT(31))
#define APB_SARADC_ADC1_THRES_EN_V 0x1
#define APB_SARADC_ADC1_THRES_EN_S 31
/* APB_SARADC_ADC2_THRES_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_EN (BIT(30))
#define APB_SARADC_ADC2_THRES_EN_M (BIT(30))
#define APB_SARADC_ADC2_THRES_EN_V 0x1
#define APB_SARADC_ADC2_THRES_EN_S 30
/* APB_SARADC_ADC1_THRES : R/W ;bitpos:[29:17] ;default: 13'd0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES 0x00001FFF
#define APB_SARADC_ADC1_THRES_M ((APB_SARADC_ADC1_THRES_V)<<(APB_SARADC_ADC1_THRES_S))
#define APB_SARADC_ADC1_THRES_V 0x1FFF
#define APB_SARADC_ADC1_THRES_S 17
/* APB_SARADC_ADC2_THRES : R/W ;bitpos:[16:4] ;default: 13'd0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES 0x00001FFF
#define APB_SARADC_ADC2_THRES_M ((APB_SARADC_ADC2_THRES_V)<<(APB_SARADC_ADC2_THRES_S))
#define APB_SARADC_ADC2_THRES_V 0x1FFF
#define APB_SARADC_ADC2_THRES_S 4
/* APB_SARADC_ADC1_THRES_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_MODE (BIT(3))
#define APB_SARADC_ADC1_THRES_MODE_M (BIT(3))
#define APB_SARADC_ADC1_THRES_MODE_V 0x1
#define APB_SARADC_ADC1_THRES_MODE_S 3
/* APB_SARADC_ADC2_THRES_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_MODE (BIT(2))
#define APB_SARADC_ADC2_THRES_MODE_M (BIT(2))
#define APB_SARADC_ADC2_THRES_MODE_V 0x1
#define APB_SARADC_ADC2_THRES_MODE_S 2
/* APB_SARADC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_CLK_EN (BIT(0))
#define APB_SARADC_CLK_EN_M (BIT(0))
#define APB_SARADC_CLK_EN_V 0x1
#define APB_SARADC_CLK_EN_S 0
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x048)
/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC1_DONE_INT_ENA_S 31
/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ENA_S 30
/* APB_SARADC_ADC1_THRES_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_INT_ENA (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_ENA_M (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_ENA_V 0x1
#define APB_SARADC_ADC1_THRES_INT_ENA_S 29
/* APB_SARADC_ADC2_THRES_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_INT_ENA (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_ENA_M (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_ENA_V 0x1
#define APB_SARADC_ADC2_THRES_INT_ENA_S 28
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x04C)
/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1
#define APB_SARADC_ADC1_DONE_INT_RAW_S 31
/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1
#define APB_SARADC_ADC2_DONE_INT_RAW_S 30
/* APB_SARADC_ADC1_THRES_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_INT_RAW (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_RAW_M (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_RAW_V 0x1
#define APB_SARADC_ADC1_THRES_INT_RAW_S 29
/* APB_SARADC_ADC2_THRES_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_INT_RAW (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_RAW_M (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_RAW_V 0x1
#define APB_SARADC_ADC2_THRES_INT_RAW_S 28
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x050)
/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC1_DONE_INT_ST_S 31
/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ST_S 30
/* APB_SARADC_ADC1_THRES_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_INT_ST (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_ST_M (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_ST_V 0x1
#define APB_SARADC_ADC1_THRES_INT_ST_S 29
/* APB_SARADC_ADC2_THRES_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_INT_ST (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_ST_M (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_ST_V 0x1
#define APB_SARADC_ADC2_THRES_INT_ST_S 28
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x054)
/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1
#define APB_SARADC_ADC1_DONE_INT_CLR_S 31
/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1
#define APB_SARADC_ADC2_DONE_INT_CLR_S 30
/* APB_SARADC_ADC1_THRES_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_INT_CLR (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_CLR_M (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_CLR_V 0x1
#define APB_SARADC_ADC1_THRES_INT_CLR_S 29
/* APB_SARADC_ADC2_THRES_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_INT_CLR (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_CLR_M (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_CLR_V 0x1
#define APB_SARADC_ADC2_THRES_INT_CLR_S 28
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x058)
/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*description: enable apb_adc use spi_dma*/
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_V 0x1
#define APB_SARADC_APB_ADC_TRANS_S 31
/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: reset_apb_adc_state*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF
#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x05c)
/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
/*description: Set this bit to enable clk_apll*/
#define APB_SARADC_CLK_SEL 0x00000003
#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
#define APB_SARADC_CLK_SEL_V 0x3
#define APB_SARADC_CLK_SEL_S 21
/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
/*description: Fractional clock divider denominator value*/
#define APB_SARADC_CLKM_DIV_A 0x0000003F
#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
#define APB_SARADC_CLKM_DIV_A_V 0x3F
#define APB_SARADC_CLKM_DIV_A_S 14
/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
/*description: Fractional clock divider numerator value*/
#define APB_SARADC_CLKM_DIV_B 0x0000003F
#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
#define APB_SARADC_CLKM_DIV_B_V 0x3F
#define APB_SARADC_CLKM_DIV_B_S 8
/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
/*description: Integral I2S clock divider value*/
#define APB_SARADC_CLKM_DIV_NUM 0x000000FF
#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
#define APB_SARADC_CLKM_DIV_NUM_V 0xFF
#define APB_SARADC_CLKM_DIV_NUM_S 0
#define APB_SARADC_APB_DAC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x060)
/* APB_SARADC_APB_DAC_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_APB_DAC_RST (BIT(16))
#define APB_SARADC_APB_DAC_RST_M (BIT(16))
#define APB_SARADC_APB_DAC_RST_V 0x1
#define APB_SARADC_APB_DAC_RST_S 16
/* APB_SARADC_DAC_RESET_FIFO : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_DAC_RESET_FIFO (BIT(15))
#define APB_SARADC_DAC_RESET_FIFO_M (BIT(15))
#define APB_SARADC_DAC_RESET_FIFO_V 0x1
#define APB_SARADC_DAC_RESET_FIFO_S 15
/* APB_SARADC_APB_DAC_TRANS : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: enable dma_dac*/
#define APB_SARADC_APB_DAC_TRANS (BIT(14))
#define APB_SARADC_APB_DAC_TRANS_M (BIT(14))
#define APB_SARADC_APB_DAC_TRANS_V 0x1
#define APB_SARADC_APB_DAC_TRANS_S 14
/* APB_SARADC_APB_DAC_ALTER_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: enable dac alter mode*/
#define APB_SARADC_APB_DAC_ALTER_MODE (BIT(13))
#define APB_SARADC_APB_DAC_ALTER_MODE_M (BIT(13))
#define APB_SARADC_APB_DAC_ALTER_MODE_V 0x1
#define APB_SARADC_APB_DAC_ALTER_MODE_S 13
/* APB_SARADC_DAC_TIMER_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: enable read dac data*/
#define APB_SARADC_DAC_TIMER_EN (BIT(12))
#define APB_SARADC_DAC_TIMER_EN_M (BIT(12))
#define APB_SARADC_DAC_TIMER_EN_V 0x1
#define APB_SARADC_DAC_TIMER_EN_S 12
/* APB_SARADC_DAC_TIMER_TARGET : R/W ;bitpos:[11:0] ;default: 12'd100 ; */
/*description: dac_timer target*/
#define APB_SARADC_DAC_TIMER_TARGET 0x00000FFF
#define APB_SARADC_DAC_TIMER_TARGET_M ((APB_SARADC_DAC_TIMER_TARGET_V)<<(APB_SARADC_DAC_TIMER_TARGET_S))
#define APB_SARADC_DAC_TIMER_TARGET_V 0xFFF
#define APB_SARADC_DAC_TIMER_TARGET_S 0
#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC)
/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h01907162 ; */
/*description: */
#define APB_SARADC_APB_CTRL_DATE 0xFFFFFFFF
#define APB_SARADC_APB_CTRL_DATE_M ((APB_SARADC_APB_CTRL_DATE_V)<<(APB_SARADC_APB_CTRL_DATE_S))
#define APB_SARADC_APB_CTRL_DATE_V 0xFFFFFFFF
#define APB_SARADC_APB_CTRL_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_SARADC_REG_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/apb_saradc_struct.h
+432
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@@ -0,0 +1,432 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_APB_SARADC_STRUCT_H_
#define _SOC_APB_SARADC_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t start_force: 1;
uint32_t start: 1;
uint32_t reserved2: 1;
uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
uint32_t sar_clk_gated: 1;
uint32_t sar_clk_div: 8; /*SAR clock divider*/
uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/
uint32_t reserved29: 1;
uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t meas_num_limit: 1;
uint32_t max_meas_num: 8; /*max conversion number*/
uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/
uint32_t timer_target: 12; /*to set saradc timer target*/
uint32_t timer_en: 1; /*to enable saradc timer trigger*/
uint32_t reserved25: 7;
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t reserved0: 16;
uint32_t sample_num: 8; /*sample number*/
uint32_t sample_cycle: 8; /*sample cycles*/
};
uint32_t val;
} fsm;
union {
struct {
uint32_t xpd_wait: 8;
uint32_t rstb_wait: 8;
uint32_t standby_wait: 8;
uint32_t reserved24: 8;
};
uint32_t val;
} fsm_wait;
uint32_t sar1_status; /**/
uint32_t sar2_status; /**/
uint32_t sar1_patt_tab[4]; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
uint32_t sar2_patt_tab[4];
union {
struct {
uint32_t reserved0: 2;
uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/
uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/
uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/
uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/
uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/
uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/
uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/
uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/
uint32_t reserved13: 19;
};
uint32_t val;
} apb_adc_arb_ctrl;
union {
struct {
uint32_t adc2_filter_reset: 1; /*reset_adc2_filter*/
uint32_t adc1_filter_reset: 1; /*reset_adc1_filter*/
uint32_t reserved2: 14;
uint32_t adc2_filter_factor: 7; /*apb_adc2_filter_factor*/
uint32_t adc1_filter_factor: 7; /*apb_adc1_filter_factor*/
uint32_t adc2_filter_en: 1; /*enable apb_adc2_filter*/
uint32_t adc1_filter_en: 1; /*enable apb_adc1_filter*/
};
uint32_t val;
} filter_ctrl;
union {
struct {
uint32_t adc2_filter_data:16;
uint32_t adc1_filter_data:16;
};
uint32_t val;
} filter_status;
union {
struct {
uint32_t clk_en: 1;
uint32_t reserved1: 1;
uint32_t adc2_thres_mode: 1;
uint32_t adc1_thres_mode: 1;
uint32_t adc2_thres: 13;
uint32_t adc1_thres: 13;
uint32_t adc2_thres_en: 1;
uint32_t adc1_thres_en: 1;
};
uint32_t val;
} thres_ctrl;
union {
struct {
uint32_t reserved0: 28;
uint32_t adc2_thres: 1;
uint32_t adc1_thres: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t reserved0: 28;
uint32_t adc2_thres: 1;
uint32_t adc1_thres: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t reserved0: 28;
uint32_t adc2_thres: 1;
uint32_t adc1_thres: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t reserved0: 28;
uint32_t adc2_thres: 1;
uint32_t adc1_thres: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
uint32_t reserved16: 14;
uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/
uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
uint32_t reserved20: 1;
uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
uint32_t reserved23: 9;
};
uint32_t val;
} apb_adc_clkm_conf;
union {
struct {
uint32_t dac_timer_target: 12; /*dac_timer target*/
uint32_t dac_timer_en: 1; /*enable read dac data*/
uint32_t apb_dac_alter_mode: 1; /*enable dac alter mode*/
uint32_t apb_dac_trans: 1; /*enable dma_dac*/
uint32_t dac_reset_fifo: 1;
uint32_t apb_dac_rst: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} apb_dac_ctrl;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t apb_ctrl_date; /**/
} apb_saradc_dev_t;
extern apb_saradc_dev_t APB_SARADC;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_APB_SARADC_STRUCT_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/assist_debug_reg.h
+138
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@@ -0,0 +1,138 @@
#define ASSIST_DEBUG_BASE DR_REG_ASSIST_DEBUG_BASE
#define ASSIST_DEBUG_INTERRUPT_ENA ((ASSIST_DEBUG_BASE) +0x00)
#define ASSIST_DEBUG_INTERRUPT_RAW ((ASSIST_DEBUG_BASE) +0x04)
#define ASSIST_DEBUG_INTERRUPT_RLS ((ASSIST_DEBUG_BASE) +0x08)
#define ASSIST_DEBUG_INTERRUPT_CLR ((ASSIST_DEBUG_BASE) +0x0C)
#define ASSIST_DEBUG_SP_SPILL_MAX BIT(19)
#define ASSIST_DEBUG_SP_SPILL_MIN BIT(18)
#define ASSIST_DEBUG_AREA_2_1_AHB_WR BIT(17)
#define ASSIST_DEBUG_AREA_2_1_AHB_RD BIT(16)
#define ASSIST_DEBUG_AREA_2_0_AHB_WR BIT(15)
#define ASSIST_DEBUG_AREA_2_0_AHB_RD BIT(14)
#define ASSIST_DEBUG_AREA_1_1_DROM0_RD BIT(13)
#define ASSIST_DEBUG_AREA_1_0_DROM0_RD BIT(12)
#define ASSIST_DEBUG_AREA_0_1_DPORT0_WR BIT(11)
#define ASSIST_DEBUG_AREA_0_1_DPORT0_RD BIT(10)
#define ASSIST_DEBUG_AREA_0_1_DRAM1_WR BIT(9)
#define ASSIST_DEBUG_AREA_0_1_DRAM1_RD BIT(8)
#define ASSIST_DEBUG_AREA_0_1_DRAM0_WR BIT(7)
#define ASSIST_DEBUG_AREA_0_1_DRAM0_RD BIT(6)
#define ASSIST_DEBUG_AREA_0_0_DPORT0_WR BIT(5)
#define ASSIST_DEBUG_AREA_0_0_DPORT0_RD BIT(4)
#define ASSIST_DEBUG_AREA_0_0_DRAM1_WR BIT(3)
#define ASSIST_DEBUG_AREA_0_0_DRAM1_RD BIT(2)
#define ASSIST_DEBUG_AREA_0_0_DRAM0_WR BIT(1)
#define ASSIST_DEBUG_AREA_0_0_DRAM0_RD BIT(0)
#define ASSIST_DEBUG_AREA_0_0_MIN ((ASSIST_DEBUG_BASE) +0x10)
#define ASSIST_DEBUG_AREA_0_0_MAX ((ASSIST_DEBUG_BASE) +0x14)
#define ASSIST_DEBUG_AREA_0_1_MIN ((ASSIST_DEBUG_BASE) +0x18)
#define ASSIST_DEBUG_AREA_0_1_MAX ((ASSIST_DEBUG_BASE) +0x1C)
#define ASSIST_DEBUG_AREA_1_0_MIN ((ASSIST_DEBUG_BASE) +0x20)
#define ASSIST_DEBUG_AREA_1_0_MAX ((ASSIST_DEBUG_BASE) +0x24)
#define ASSIST_DEBUG_AREA_1_1_MIN ((ASSIST_DEBUG_BASE) +0x28)
#define ASSIST_DEBUG_AREA_1_1_MAX ((ASSIST_DEBUG_BASE) +0x2C)
#define ASSIST_DEBUG_AREA_2_0_MIN ((ASSIST_DEBUG_BASE) +0x30)
#define ASSIST_DEBUG_AREA_2_0_MAX ((ASSIST_DEBUG_BASE) +0x34)
#define ASSIST_DEBUG_AREA_2_1_MIN ((ASSIST_DEBUG_BASE) +0x38)
#define ASSIST_DEBUG_AREA_2_1_MAX ((ASSIST_DEBUG_BASE) +0x3C)
#define ASSIST_DEBUG_AREA_PC ((ASSIST_DEBUG_BASE) +0x40)
#define ASSIST_DEBUG_AREA_SP ((ASSIST_DEBUG_BASE) +0x44)
#define ASSIST_DEBUG_PRO_SP_UNSTABLE ((ASSIST_DEBUG_BASE) +0x48)
#define ASSIST_DEBUG_PRO_SP_MIN ((ASSIST_DEBUG_BASE) +0x4C)
#define ASSIST_DEBUG_PRO_SP_MAX ((ASSIST_DEBUG_BASE) +0x50)
#define ASSIST_DEBUG_PRO_SP_PC ((ASSIST_DEBUG_BASE) +0x54)
#define ASSIST_DEBUG_PRO_PDEBUGENABLE ((ASSIST_DEBUG_BASE) +0x58)
#define ASSIST_DEBUG_PRO_RCD_RECORDING ((ASSIST_DEBUG_BASE) +0x5C)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGINST ((ASSIST_DEBUG_BASE) +0x60)
/* register layout:
* SIZE [7..0] : Instructions normally complete in the W stage. The size of the instruction in the W is given
* by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing
* instruction. This is also known as a bubble cycle. Also see DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG.
* ISRC [14..12] : Instruction source.
** LOOP [23..20] : Loopback status.
** CINTLEVEL [27..24]: CINTLEVEL.
*/
#define DPORT_RECORD_PDEBUGINST_SZ_M ((DPORT_RECORD_PDEBUGINST_SZ_V)<<(DPORT_RECORD_PDEBUGINST_SZ_S))
#define DPORT_RECORD_PDEBUGINST_SZ_V 0xFF
#define DPORT_RECORD_PDEBUGINST_SZ_S 0
#define DPORT_RECORD_PDEBUGINST_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V)
#define DPORT_RECORD_PDEBUGINST_ISRC_M ((DPORT_RECORD_PDEBUGINST_ISRC_V)<<(DPORT_RECORD_PDEBUGINST_ISRC_S))
#define DPORT_RECORD_PDEBUGINST_ISRC_V 0x07
#define DPORT_RECORD_PDEBUGINST_ISRC_S 12
#define DPORT_RECORD_PDEBUGINST_ISRC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_ISRC_S) & DPORT_RECORD_PDEBUGINST_ISRC_V)
// #define DPORT_RECORD_PDEBUGINST_LOOP_M ((DPORT_RECORD_PDEBUGINST_LOOP_V)<<(DPORT_RECORD_PDEBUGINST_LOOP_S))
// #define DPORT_RECORD_PDEBUGINST_LOOP_V 0x0F
// #define DPORT_RECORD_PDEBUGINST_LOOP_S 20
// #define DPORT_RECORD_PDEBUGINST_LOOP(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_LOOP_S) & DPORT_RECORD_PDEBUGINST_LOOP_V)
#define DPORT_RECORD_PDEBUGINST_LOOP_REP (BIT(20)) /* loopback will occur */
#define DPORT_RECORD_PDEBUGINST_LOOP (BIT(21)) /* last inst of loop */
#define DPORT_RECORD_PDEBUGINST_CINTL_M ((DPORT_RECORD_PDEBUGINST_CINTL_V)<<(DPORT_RECORD_PDEBUGINST_CINTL_S))
#define DPORT_RECORD_PDEBUGINST_CINTL_V 0x0F
#define DPORT_RECORD_PDEBUGINST_CINTL_S 24
#define DPORT_RECORD_PDEBUGINST_CINTL(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS ((ASSIST_DEBUG_BASE) +0x64)
/* register layout:
* BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
* INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
*/
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V 0x3F
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S 0
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S) & DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO 0x00 /* Power shut off */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP 0x02 /* Register dependency or resource conflict. See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL 0x04 /* Control transfer bubble */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM 0x08 /* I-cache miss (incl uncached miss) */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM 0x0C /* D-cache miss (excl uncached miss) */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0 0x10 /* Exception or interrupt (W stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info.
The virtual address of the instruction that was killed appears on DPORT_PRO_CPU_RECORD_PDEBUGPC_REG[31:0] */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1 0x11 /* Exception or interrupt (W+1 stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL 0x14 /* Instruction replay (other). DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG has the PC of the replaying instruction. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB 0x18 /* HW ITLB refill. The refill address and data are available on
DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM 0x1A /* ITLB miss */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB 0x1C /* HW DTLB refill. The refill address and data are available on
DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM 0x1E /* DTLB miss */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL 0x20 /* Stall . The cause of the global stall is further classified in the DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC 0x24 /* HW-corrected memory error */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI 0x28 /* WAITI mode */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER 0x3C /* all other bubbles */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_M ((DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)<<(DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S))
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V 0x3F
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S 0
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S) & DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX 0x00 /* JX */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX 0x04 /* CALLX */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET 0x08 /* All call returns */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET 0x0C /* All exception returns */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B 0x10 /* Branch taken or loop not taken */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J 0x14 /* J */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL 0x18 /* CALL */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN 0x1C /* Branch not taken */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP 0x20 /* Loop instruction (taken) */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I 0x24 /* S32C1I. The address and load data (before the conditional store) are available on the LS signals*/
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB 0x28 /* WSR/XSR to LBEGIN */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID 0x2C /* WSR to MMID */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR 0x30 /* RSR or WSR (except MMID and LBEGIN) or XSR (except LBEGIN) */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER 0x34 /* RER or WER */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF 0x3C /* Default */
#define ASSIST_DEBUG_PRO_RCD_PDEBUGDATA ((ASSIST_DEBUG_BASE) +0x68)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGPC ((ASSIST_DEBUG_BASE) +0x6C)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT ((ASSIST_DEBUG_BASE) +0x70)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR ((ASSIST_DEBUG_BASE) +0x74)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA ((ASSIST_DEBUG_BASE) +0x78)
#define ASSIST_DEBUG_PRO_RCD_SP ((ASSIST_DEBUG_BASE) +0x7C)
#define ASSIST_DEBUG_CLOCK_GATE ((ASSIST_DEBUG_BASE) +0x80)
#define ASSIST_DEBUG_REG_DATE ((ASSIST_DEBUG_BASE) +0xFFC)
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/bb_reg.h
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_BB_REG_H_
#define _SOC_BB_REG_H_
/* Some of the baseband control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
#define BB_FFT_FORCE_PU (BIT(3))
#define BB_FFT_FORCE_PU_M (BIT(3))
#define BB_FFT_FORCE_PU_V 1
#define BB_FFT_FORCE_PU_S 3
#define BB_FFT_FORCE_PD (BIT(2))
#define BB_FFT_FORCE_PD_M (BIT(2))
#define BB_FFT_FORCE_PD_V 1
#define BB_FFT_FORCE_PD_S 2
#define BB_DC_EST_FORCE_PU (BIT(1))
#define BB_DC_EST_FORCE_PU_M (BIT(1))
#define BB_DC_EST_FORCE_PU_V 1
#define BB_DC_EST_FORCE_PU_S 1
#define BB_DC_EST_FORCE_PD (BIT(0))
#define BB_DC_EST_FORCE_PD_M (BIT(0))
#define BB_DC_EST_FORCE_PD_V 1
#define BB_DC_EST_FORCE_PD_S 0
#endif /* _SOC_BB_REG_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/boot_mode.h
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_BOOT_MODE_H_
#define _SOC_BOOT_MODE_H_
#include "soc.h"
/*SPI Boot*/
#define IS_1XXX(v) (((v)&0x08)==0x08)
/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
#define IS_00XX(v) (((v)&0x0c)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
#define IS_0000(v) (((v)&0x0f)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
#define IS_0001(v) (((v)&0x0f)==0x01)
/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
#define IS_0010(v) (((v)&0x0f)==0x02)
/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
#define IS_0011(v) (((v)&0x0f)==0x03)
/*legacy SPI Boot*/
#define IS_0100(v) (((v)&0x0f)==0x04)
/*ATE/ANALOG Mode*/
#define IS_0101(v) (((v)&0x0f)==0x05)
/*SPI(or SDIO_V1) download Mode*/
#define IS_0110(v) (((v)&0x0f)==0x06)
/*Diagnostic Mode+UART0 download Mode*/
#define IS_0111(v) (((v)&0x0f)==0x07)
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG))
/*do not include download mode*/
#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET())
/*all spi boot including spi/legacy*/
#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
/*all faster spi boot including spi*/
#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
#if SUPPORT_SDIO_DOWNLOAD
/*all sdio V2 of failing edge input, failing edge output*/
#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET())
/*all sdio V2 of failing edge input, raising edge output*/
#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, raising edge output*/
#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET())
/*all sdio V1 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET())
/*do not include joint download mode*/
#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET())
#else
/*do not include joint download mode*/
#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET())
#endif
/*joint download boot*/
#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET())
/*ATE mode*/
#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET())
/*used by ETS_IS_SDIO_UART_BOOT*/
#define SEL_NO_BOOT 0
#define SEL_SDIO_BOOT BIT0
#define SEL_UART_BOOT BIT1
#define SEL_SPI_SLAVE_BOOT BIT2
#endif /* _SOC_BOOT_MODE_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/brownout_caps.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_BROWNOUT_RESET_SUPPORTED 1
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cache_memory.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#ifdef __cplusplus
extern "C" {
#endif
/*IRAM0 is connected with Cache IBUS0*/
#define IRAM0_ADDRESS_LOW 0x40000000
#define IRAM0_ADDRESS_HIGH 0x40400000
#define IRAM0_CACHE_ADDRESS_LOW 0x40080000
#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
/*IRAM1 is connected with Cache IBUS1*/
#define IRAM1_ADDRESS_LOW 0x40400000
#define IRAM1_ADDRESS_HIGH 0x40800000
/*DROM0 is connected with Cache IBUS2*/
#define DROM0_ADDRESS_LOW 0x3f000000
#define DROM0_ADDRESS_HIGH 0x3f400000
/*DRAM0 is connected with Cache DBUS0*/
#define DRAM0_ADDRESS_LOW 0x3fc00000
#define DRAM0_ADDRESS_HIGH 0x40000000
#define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000
#define DRAM0_CACHE_ADDRESS_HIGH 0x3ff80000
/*DRAM1 is connected with Cache DBUS1*/
#define DRAM1_ADDRESS_LOW 0x3f800000
#define DRAM1_ADDRESS_HIGH 0x3fc00000
/*DPORT is connected with Cache DBUS2*/
#define DPORT_ADDRESS_LOW 0x3f400000
#define DPORT_ADDRESS_HIGH 0x3f800000
#define DPORT_CACHE_ADDRESS_LOW 0x3f500000
#define DPORT_CACHE_ADDRESS_HIGH 0x3f800000
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr)
#define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr)
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
#define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr)
#define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr)
#define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr)
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1)
#define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0)
#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1)
#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT)
#define PRO_CACHE_IBUS0 0
#define PRO_CACHE_IBUS0_MMU_START 0
#define PRO_CACHE_IBUS0_MMU_END 0x100
#define PRO_CACHE_IBUS1 1
#define PRO_CACHE_IBUS1_MMU_START 0x100
#define PRO_CACHE_IBUS1_MMU_END 0x200
#define PRO_CACHE_IBUS2 2
#define PRO_CACHE_IBUS2_MMU_START 0x200
#define PRO_CACHE_IBUS2_MMU_END 0x300
#define PRO_CACHE_DBUS0 3
#define PRO_CACHE_DBUS0_MMU_START 0x300
#define PRO_CACHE_DBUS0_MMU_END 0x400
#define PRO_CACHE_DBUS1 4
#define PRO_CACHE_DBUS1_MMU_START 0x400
#define PRO_CACHE_DBUS1_MMU_END 0x500
#define PRO_CACHE_DBUS2 5
#define PRO_CACHE_DBUS2_MMU_START 0x500
#define PRO_CACHE_DBUS2_MMU_END 0x600
// #define MMU_SIZE 0x600
#define ICACHE_MMU_SIZE 0x300
#define DCACHE_MMU_SIZE 0x300
#define MMU_BUS_START(i) ((i) * 0x100)
#define MMU_BUS_SIZE 0x100
#define MMU_INVALID BIT(14)
#define MMU_ACCESS_FLASH BIT(15)
#define MMU_ACCESS_SPIRAM BIT(16)
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
#define MMU_TABLE_INVALID_VAL 0x4000
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK 0x3fff
#define MMU_PAGE_SIZE 0x10000
#define BUS_ADDR_SIZE 0x400000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
#define BUS_NUM_MASK 0x3
#define CACHE_MEMORY_BANK_SIZE 8192
#define CACHE_MEMORY_BANK_NUM 4
#define CACHE_MEMORY_BANK_NUM_MASK 0x3
#define CACHE_MEMORY_LAYOUT_SHIFT 4
#define CACHE_MEMORY_LAYOUT_SHIFT0 0
#define CACHE_MEMORY_LAYOUT_SHIFT1 4
#define CACHE_MEMORY_LAYOUT_SHIFT2 8
#define CACHE_MEMORY_LAYOUT_SHIFT3 12
#define CACHE_MEMORY_LAYOUT_MASK 0xf
#define CACHE_MEMORY_BANK0_ADDR 0x3FFB0000
#define CACHE_MEMORY_BANK1_ADDR 0x3FFB2000
#define CACHE_MEMORY_BANK2_ADDR 0x3FFB4000
#define CACHE_MEMORY_BANK3_ADDR 0x3FFB6000
#ifdef __cplusplus
}
#endif
#endif /*_CACHE_MEMORY_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/clkout_channel.h
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_CLKOUT_CHANNEL_H
#define _SOC_CLKOUT_CHANNEL_H
//CLKOUT channels
#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1
#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20
#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2
#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19
#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3
#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18
#endif
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cpu.h
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_CPU_H
#define _SOC_CPU_H
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "xtensa/corebits.h"
#ifdef __cplusplus
extern "C" {
#endif
/* C macros for xtensa special register read/write/exchange */
#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval));
#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval));
#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval));
/** @brief Read current stack pointer address
*
*/
static inline void *get_sp(void)
{
void *sp;
asm volatile ("mov %0, sp;" : "=r" (sp));
return sp;
}
/* Functions to set page attributes for Region Protection option in the CPU.
* See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
*/
static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
{
asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
}
static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
{
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
}
/**
* @brief Configure memory region protection
*
* Make page 0 access raise an exception.
* Also protect some other unused pages so we can catch weirdness.
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*/
static inline void cpu_configure_region_protection(void)
{
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
cpu_write_dtlb(pages_to_protect[i], 0xf);
cpu_write_itlb(pages_to_protect[i], 0xf);
}
cpu_write_dtlb(0x20000000, 0);
cpu_write_itlb(0x20000000, 0);
}
/**
* @brief Stall CPU using RTC controller
* @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
*/
void esp_cpu_stall(int cpu_id);
/**
* @brief Un-stall CPU using RTC controller
* @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
*/
void esp_cpu_unstall(int cpu_id);
/**
* @brief Reset CPU using RTC controller
* @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
*/
void esp_cpu_reset(int cpu_id);
/**
* @brief Returns true if a JTAG debugger is attached to CPU
* OCD (on chip debug) port.
*
* @note If "Make exception and panic handlers JTAG/OCD aware"
* is disabled, this function always returns false.
*/
bool esp_cpu_in_ocd_debug_mode(void);
/**
* @brief Convert the PC register value to its true address
*
* The address of the current instruction is not stored as an exact uint32_t
* representation in PC register. This function will convert the value stored in
* the PC register to a uint32_t address.
*
* @param pc_raw The PC as stored in register format.
*
* @return Address in uint32_t format
*/
static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc)
{
if (pc & 0x80000000) {
//Top two bits of a0 (return address) specify window increment. Overwrite to map to address space.
pc = (pc & 0x3fffffff) | 0x40000000;
}
//Minus 3 to get PC of previous instruction (i.e. instruction executed before return address)
return pc - 3;
}
typedef uint32_t esp_cpu_ccount_t;
static inline esp_cpu_ccount_t esp_cpu_get_ccount(void)
{
uint32_t result;
RSR(CCOUNT, result);
return result;
}
#ifdef __cplusplus
}
#endif
#endif
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cpu_caps.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/crypto_dma_reg.h
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_CRYPTO_DMA_REG_H_
#define _SOC_CRYPTO_DMA_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
/* CRYPTO_DMA_CONF0 : RO ;bitpos:[31:14] ;default: 18'h0 ; */
/* CONF0_REG_GEN_CLK_EN : RW ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_GEN_CLK_EN (BIT(13))
#define CONF0_REG_GEN_CLK_EN_M (BIT(13))
#define CONF0_REG_GEN_CLK_EN_V 0x1
#define CONF0_REG_GEN_CLK_EN_S 13
/* CONF0_REG_MEM_TRANS_EN: RW ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_MEM_TRANS_EN (BIT(12))
#define CONF0_REG_MEM_TRANS_EN_M (BIT(12))
#define CONF0_REG_MEM_TRANS_EN_V 0x1
#define CONF0_REG_MEM_TRANS_EN_S 12
/* CONF0_REG_OUT_DATA_BURST_EN: RW ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_DATA_BURST_EN (BIT(11))
#define CONF0_REG_OUT_DATA_BURST_EN_M (BIT(11))
#define CONF0_REG_OUT_DATA_BURST_EN_V 0x1
#define CONF0_REG_OUT_DATA_BURST_EN_S 11
/* CONF0_REG_INDSCR_BURST_EN: RW ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_INDSCR_BURST_EN (BIT(10))
#define CONF0_REG_INDSCR_BURST_EN_M (BIT(10))
#define CONF0_REG_INDSCR_BURST_EN_V 0x1
#define CONF0_REG_INDSCR_BURST_EN_S 10
/* CONF0_REG_OUTDSCR_BURST_EN: RW ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUTDSCR_BURST_EN (BIT(9))
#define CONF0_REG_OUTDSCR_BURST_EN_M (BIT(9))
#define CONF0_REG_OUTDSCR_BURST_EN_V 0x1
#define CONF0_REG_OUTDSCR_BURST_EN_S 9
/* CONF0_REG_OUT_EOF_MODE: RW ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_EOF_MODE (BIT(8))
#define CONF0_REG_OUT_EOF_MODE_M (BIT(8))
#define CONF0_REG_OUT_EOF_MODE_V 0x1
#define CONF0_REG_OUT_EOF_MODE_S 8
/* CONF0_REG_OUT_NO_RESTART_CLR: RW ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_NO_RESTART_CLR (BIT(7))
#define CONF0_REG_OUT_NO_RESTART_CLR_M (BIT(7))
#define CONF0_REG_OUT_NO_RESTART_CLR_V 0x1
#define CONF0_REG_OUT_NO_RESTART_CLR_S 7
/* CONF0_REG_OUT_AUTO_WRBACK: RW ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_AUTO_WRBACK (BIT(6))
#define CONF0_REG_OUT_AUTO_WRBACK_M (BIT(6))
#define CONF0_REG_OUT_AUTO_WRBACK_V 0x1
#define CONF0_REG_OUT_AUTO_WRBACK_S 6
/* CONF0_REG_OUT_LOOP_TEST: RW ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_LOOP_TEST (BIT(5))
#define CONF0_REG_OUT_LOOP_TEST_M (BIT(5))
#define CONF0_REG_OUT_LOOP_TEST_V 0x1
#define CONF0_REG_OUT_LOOP_TEST_S 5
/* CONF0_REG_IN_LOOP_TEST: RW ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_IN_LOOP_TEST (BIT(4))
#define CONF0_REG_IN_LOOP_TEST_M (BIT(4))
#define CONF0_REG_IN_LOOP_TEST_V 0x1
#define CONF0_REG_IN_LOOP_TEST_S 4
/* CONF0_REG_AHBM_RST: RW ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_AHBM_RST (BIT(3))
#define CONF0_REG_AHBM_RST_M (BIT(3))
#define CONF0_REG_AHBM_RST_V 0x1
#define CONF0_REG_AHBM_RST_S 3
/* CONF0_REG_AHBM_FIFO_RST: RW ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_AHBM_FIFO_RST (BIT(2))
#define CONF0_REG_AHBM_FIFO_RST_M (BIT(2))
#define CONF0_REG_AHBM_FIFO_RST_V 0x1
#define CONF0_REG_AHBM_FIFO_RST_S 2
/* CONF0_REG_OUT_RST: RW ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_RST (BIT(1))
#define CONF0_REG_OUT_RST_M (BIT(1))
#define CONF0_REG_OUT_RST_V 0x1
#define CONF0_REG_OUT_RST_S 1
/* CONF0_REG_IN_RST: RW ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_IN_RST (BIT(0))
#define CONF0_REG_IN_RST_M (BIT(0))
#define CONF0_REG_IN_RST_V 0x1
#define CONF0_REG_IN_RST_S 0
/* CRYPTO_DMA_INT_RAW : RO ;bitpos:[31:10] ;default: 22'h0 ; */
/* INT_RAW_OUT_TOTAL_EOF : RW ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define INT_RAW_OUT_TOTAL_EOF ( BIT(8))
#define INT_RAW_OUT_TOTAL_EOF_M (BIT(8))
#define INT_RAW_OUT_TOTAL_EOF_V 0x1
#define INT_RAW_OUT_TOTAL_EOF_S 8
/* INT_RAW_IN_SUC_EOF : RW ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define INT_RAW_IN_SUC_EOF ( BIT(1))
#define INT_RAW_IN_SUC_EOF_M (BIT(1))
#define INT_RAW_IN_SUC_EOF_V 0x1
#define INT_RAW_IN_SUC_EOF_S 1
/* CRYPTO_DMA_OUT_LINK : RO ;bitpos:[31] ;default: 1'h0 ; */
/* OUT_LINK_REG_OUTLINK_RESTART : RW ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define OUT_LINK_REG_OUTLINK_RESTART ( BIT(30))
#define OUT_LINK_REG_OUTLINK_RESTART_M (BIT(30))
#define OUT_LINK_REG_OUTLINK_RESTART_V 0x1
#define OUT_LINK_REG_OUTLINK_RESTART_S 30
/* OUT_LINK_REG_OUTLINK_START : RW ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define OUT_LINK_REG_OUTLINK_START ( BIT(29))
#define OUT_LINK_REG_OUTLINK_START_M (BIT(29))
#define OUT_LINK_REG_OUTLINK_START_V 0x1
#define OUT_LINK_REG_OUTLINK_START_S 29
/* OUT_LINK_REG_OUTLINK_STOP : RW ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define OUT_LINK_REG_OUTLINK_STOP ( BIT(28))
#define OUT_LINK_REG_OUTLINK_STOP_M (BIT(28))
#define OUT_LINK_REG_OUTLINK_STOP_V 0x1
#define OUT_LINK_REG_OUTLINK_STOP_S 28
/* OUT_LINK_REG_OUTLINK_ADDR : RW ;bitpos:[19:0] ;default: 20'h0 ; */
/*description: */
#define OUT_LINK_REG_OUTLINK_ADDR 0x000FFFFF
#define OUT_LINK_REG_OUTLINK_ADDR_M (OUT_LINK_REG_OUTLINK_ADDR_V<<OUT_LINK_REG_OUTLINK_ADDR_S)
#define OUT_LINK_REG_OUTLINK_ADDR_V 0xFFFFF
#define OUT_LINK_REG_OUTLINK_ADDR_S 0
/* CRYPTO_DMA_IN_LINK : RO ;bitpos:[31] ;default: 1'h0 ; */
/* IN_LINK_REG_INLINK_RESTART : RW ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define IN_LINK_REG_INLINK_RESTART ( BIT(30))
#define IN_LINK_REG_INLINK_RESTART_M (BIT(30))
#define IN_LINK_REG_INLINK_RESTART_V 0x1
#define IN_LINK_REG_INLINK_RESTART_S 30
/* IN_LINK_REG_INLINK_START : RW ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define IN_LINK_REG_INLINK_START ( BIT(29))
#define IN_LINK_REG_INLINK_START_M (BIT(29))
#define IN_LINK_REG_INLINK_START_V 0x1
#define IN_LINK_REG_INLINK_START_S 29
/* IN_LINK_REG_INLINK_STOP : RW ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define IN_LINK_REG_INLINK_STOP ( BIT(28))
#define IN_LINK_REG_INLINK_STOP_M (BIT(28))
#define IN_LINK_REG_INLINK_STOP_V 0x1
#define IN_LINK_REG_INLINK_STOP_S 28
/* IN_LINK_REG_INLINK_ADDR : RW ;bitpos:[19:0] ;default: 20'h0 ; */
/*description: */
#define IN_LINK_REG_INLINK_ADDR 0x000FFFFF
#define IN_LINK_REG_INLINK_ADDR_M (IN_LINK_REG_INLINK_ADDR_V<<IN_LINK_REG_INLINK_ADDR_S)
#define IN_LINK_REG_INLINK_ADDR_V 0xFFFFF
#define IN_LINK_REG_INLINK_ADDR_S 0
/* CRYPTO_DMA_AES_SHA_SELECT : RO ;bitpos:[31:1] ;default: 31'b0 ; */
/* AES_SHA_SELECT : RW ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define AES_SHA_SELECT ( BIT(0))
#define AES_SHA_SELECT_M (BIT(0))
#define AES_SHA_SELECT_V 0x1
#define AES_SHA_SELECT_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_CRYPTO_DMA_REG_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/dac_caps.h
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RTC_DAC_CAPS_H_
#define _SOC_RTC_DAC_CAPS_H_
#define SOC_DAC_PERIPH_NUM 2
#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
#endif
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/dac_channel.h
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_DAC_CHANNEL_H
#define _SOC_DAC_CHANNEL_H
#define DAC_GPIO17_CHANNEL DAC_CHANNEL_1
#define DAC_CHANNEL_1_GPIO_NUM 17
#define DAC_GPIO18_CHANNEL DAC_CHANNEL_2
#define DAC_CHANNEL_2_GPIO_NUM 18
#endif
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/dport_access.h
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// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DPORT_ACCESS_H_
#define _DPORT_ACCESS_H_
#include <stdint.h>
#include "esp_attr.h"
#include "esp32s2/dport_access.h"
#include "soc.h"
#include "uart_reg.h"
#include "xtensa/xtruntime.h"
#ifdef __cplusplus
extern "C" {
#endif
// ESP32C is single core and does not have DPORT bug, so these macros are all same as the non-DPORT versions
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
// Write value to DPORT register (does not require protecting)
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
//get bit or get bits from register
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
//set bit or set bits to register
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
//clear bit or clear bits of register
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
//set bits of register controlled by mask
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
//get field from register, uses field _S & _V to determine mask
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
//set field to register, used when _f is not left shifted by _f##_S
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
//get field value from a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
//write value to register
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
//clear bits of register controlled by mask
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
//set bits of register controlled by mask
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
//get bits of register controlled by mask
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
//get bits of register controlled by highest bit and lowest bit
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
//set bits of register controlled by mask and shift
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
//get field of register
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
//}}
#ifdef __cplusplus
}
#endif
#endif /* _DPORT_ACCESS_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/dport_reg.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_DPORT_REG_H_
#define _SOC_DPORT_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "interrupt_reg.h"
#include "system_reg.h"
#include "sensitive_reg.h"
#include "soc.h"
#define DPORT_DATE_REG SYSTEM_DATE_REG
#ifndef __ASSEMBLER__
#include "dport_access.h"
#endif
#ifdef __cplusplus
}
#endif
#endif /*_SOC_DPORT_REG_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/efuse_reg.h
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tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/efuse_struct.h
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_EFUSE_STRUCT_H_
#define _SOC_EFUSE_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
uint32_t pgm_data0; /**/
union {
struct {
uint32_t rd_dis: 7;
uint32_t dis_rtc_ram_boot: 1;
uint32_t dis_icache: 1;
uint32_t dis_dcache: 1;
uint32_t dis_download_icache: 1;
uint32_t dis_download_dcache: 1;
uint32_t dis_force_download: 1;
uint32_t dis_usb: 1;
uint32_t dis_can: 1;
uint32_t dis_sdio_access: 1;
uint32_t dis_efuse_ate_wr: 1;
uint32_t soft_dis_jtag: 1;
uint32_t hard_dis_jtag: 1;
uint32_t dis_download_manual_encrypt: 1;
uint32_t usb_drefh: 2;
uint32_t usb_drefl: 2;
uint32_t usb_exchg_pins: 1;
uint32_t ext_phy_enable: 1;
uint32_t usb_force_b: 1;
uint32_t usb_dres: 2;
uint32_t sdio_modecurlim: 1;
uint32_t sdio_drefh: 2;
};
uint32_t val;
} pgm_data1;
union {
struct {
uint32_t sdio_drefm: 2;
uint32_t sdio_drefl: 2;
uint32_t sdio_xpd: 1;
uint32_t sdio_tieh: 1;
uint32_t sdio_force: 1;
uint32_t sdio_en_init: 1;
uint32_t sdio_encurlim: 1;
uint32_t sdio_dcurlim: 3;
uint32_t sdio_init: 2;
uint32_t sdio_dcap: 2;
uint32_t wdt_delay_sel: 2;
uint32_t spi_boot_crypt_cnt: 3;
uint32_t secure_boot_key_revoke0: 1;
uint32_t secure_boot_key_revoke1: 1;
uint32_t secure_boot_key_revoke2: 1;
uint32_t key_purpose_0: 4;
uint32_t key_purpose_1: 4;
};
uint32_t val;
} pgm_data2;
union {
struct {
uint32_t key_purpose_2: 4;
uint32_t key_purpose_3: 4;
uint32_t key_purpose_4: 4;
uint32_t key_purpose_5: 4;
uint32_t key_purpose_6: 4;
uint32_t secure_boot_en: 1;
uint32_t secure_boot_aggressive_revoke: 1;
uint32_t xtal_freq: 6;
uint32_t flash_tpuw: 4;
};
uint32_t val;
} pgm_data3;
union {
struct {
uint32_t dis_download_mode: 1;
uint32_t dis_legacy_spi_boot: 1;
uint32_t uart_print_channel: 1;
uint32_t dis_tiny_basic: 1;
uint32_t dis_usb_download_mode: 1;
uint32_t enable_security_download: 1;
uint32_t uart_print_control: 2;
uint32_t reserve: 24;
};
uint32_t val;
} pgm_data4;
union {
struct {
uint32_t chip_version:24;
uint32_t rs_data_23: 8;
};
uint32_t val;
} pgm_data5;
uint32_t pgm_data6; /**/
uint32_t pgm_data7; /**/
uint32_t pgm_check_value0; /**/
uint32_t pgm_check_value1; /**/
uint32_t pgm_check_value2; /**/
uint32_t rd_wr_dis; /**/
union {
struct {
uint32_t rd_dis: 7;
uint32_t dis_rtc_ram_boot: 1;
uint32_t dis_icache: 1;
uint32_t dis_dcache: 1;
uint32_t dis_download_icache: 1;
uint32_t dis_download_dcache: 1;
uint32_t dis_force_download: 1;
uint32_t dis_usb: 1;
uint32_t dis_can: 1;
uint32_t dis_sdio_access: 1;
uint32_t dis_ate_wr: 1;
uint32_t soft_dis_jtag: 1;
uint32_t hard_dis_jtag: 1;
uint32_t dis_download_manual_encrypt: 1;
uint32_t usb_drefh: 2;
uint32_t usb_drefl: 2;
uint32_t usb_exchg_pins: 1;
uint32_t ext_phy_enable: 1;
uint32_t usb_force_b: 1;
uint32_t usb_dres: 2;
uint32_t sdio_modecurlim: 1;
uint32_t sdio_drefh: 2;
};
uint32_t val;
} rd_repeat_data0;
union {
struct {
uint32_t sdio_drefm: 2;
uint32_t sdio_drefl: 2;
uint32_t sdio_xpd: 1;
uint32_t sdio_tieh: 1;
uint32_t sdio_force: 1;
uint32_t sdio_en_init: 1;
uint32_t sdio_encurlim: 1;
uint32_t sdio_dcurlim: 3;
uint32_t sdio_init: 2;
uint32_t eufse_sdio_dcap: 2;
uint32_t wdt_delay_sel: 2;
uint32_t spi_boot_crypt_cnt: 3;
uint32_t secure_boot_key_revoke0: 1;
uint32_t secure_boot_key_revoke1: 1;
uint32_t secure_boot_key_revoke2: 1;
uint32_t key_purpose_0: 4;
uint32_t key_purpose_1: 4;
};
uint32_t val;
} rd_repeat_data1;
union {
struct {
uint32_t key_purpose_2: 4;
uint32_t key_purpose_3: 4;
uint32_t key_purpose_4: 4;
uint32_t key_purpose_5: 4;
uint32_t key_purpose_6: 4;
uint32_t secure_boot_en: 1;
uint32_t secure_boot_aggressive_revoke: 1;
uint32_t xtal_freq: 6;
uint32_t flash_tpuw: 4;
};
uint32_t val;
} rd_repeat_data2;
union {
struct {
uint32_t dis_download_mode: 1;
uint32_t dis_legacy_spi_boot: 1;
uint32_t uart_print_channel: 1;
uint32_t dis_tiny_basic: 1;
uint32_t dis_usb_download_mode: 1;
uint32_t enable_security_download: 1;
uint32_t uart_print_control: 2;
uint32_t reserve: 24;
};
uint32_t val;
} rd_repeat_data3;
union {
struct {
uint32_t chip_version:24;
uint32_t reserved24: 8;
};
uint32_t val;
} rd_repeat_data4;
uint32_t rd_mac_spi_8m_0; /**/
union {
struct {
uint32_t mac_1: 16;
uint32_t spi_pad_conf_0:16;
};
uint32_t val;
} rd_mac_spi_8m_1;
union {
struct {
uint32_t spi_pad_conf_1:20;
uint32_t clk8m_freq: 12;
};
uint32_t val;
} rd_mac_spi_8m_2;
uint32_t rd_mac_spi_8m_3; /**/
uint32_t rd_mac_spi_8m_4; /**/
uint32_t rd_mac_spi_8m_5; /**/
uint32_t rd_sys_data0; /**/
uint32_t rd_sys_data1; /**/
uint32_t rd_sys_data2; /**/
uint32_t rd_sys_data3; /**/
uint32_t rd_sys_data4; /**/
uint32_t rd_sys_data5; /**/
uint32_t rd_sys_data6; /**/
uint32_t rd_sys_data7; /**/
uint32_t rd_usr_data0; /**/
uint32_t rd_usr_data1; /**/
uint32_t rd_usr_data2; /**/
uint32_t rd_usr_data3; /**/
uint32_t rd_usr_data4; /**/
uint32_t rd_usr_data5; /**/
uint32_t rd_usr_data6; /**/
uint32_t rd_usr_data7; /**/
uint32_t rd_key0_data0; /**/
uint32_t rd_key0_data1; /**/
uint32_t rd_key0_data2; /**/
uint32_t rd_key0_data3; /**/
uint32_t rd_key0_data4; /**/
uint32_t rd_key0_data5; /**/
uint32_t rd_key0_data6; /**/
uint32_t rd_key0_data7; /**/
uint32_t rd_key1_data0; /**/
uint32_t rd_key1_data1; /**/
uint32_t rd_key1_data2; /**/
uint32_t rd_key1_data3; /**/
uint32_t rd_key1_data4; /**/
uint32_t rd_key1_data5; /**/
uint32_t rd_key1_data6; /**/
uint32_t rd_key1_data7; /**/
uint32_t rd_key2_data0; /**/
uint32_t rd_key2_data1; /**/
uint32_t rd_key2_data2; /**/
uint32_t rd_key2_data3; /**/
uint32_t rd_key2_data4; /**/
uint32_t rd_key2_data5; /**/
uint32_t rd_key2_data6; /**/
uint32_t rd_key2_data7; /**/
uint32_t rd_key3_data0; /**/
uint32_t rd_key3_data1; /**/
uint32_t rd_key3_data2; /**/
uint32_t rd_key3_data3; /**/
uint32_t rd_key3_data4; /**/
uint32_t rd_key3_data5; /**/
uint32_t rd_key3_data6; /**/
uint32_t rd_key3_data7; /**/
uint32_t rd_key4_data0; /**/
uint32_t rd_key4_data1; /**/
uint32_t rd_key4_data2; /**/
uint32_t rd_key4_data3; /**/
uint32_t rd_key4_data4; /**/
uint32_t rd_key4_data5; /**/
uint32_t rd_key4_data6; /**/
uint32_t rd_key4_data7; /**/
uint32_t rd_key5_data0; /**/
uint32_t rd_key5_data1; /**/
uint32_t rd_key5_data2; /**/
uint32_t rd_key5_data3; /**/
uint32_t rd_key5_data4; /**/
uint32_t rd_key5_data5; /**/
uint32_t rd_key5_data6; /**/
uint32_t rd_key5_data7; /**/
uint32_t rd_key6_data0; /**/
uint32_t rd_key6_data1; /**/
uint32_t rd_key6_data2; /**/
uint32_t rd_key6_data3; /**/
uint32_t rd_key6_data4; /**/
uint32_t rd_key6_data5; /**/
uint32_t rd_key6_data6; /**/
uint32_t rd_key6_data7; /**/
union {
struct {
uint32_t rd_rd_dis_err: 7;
uint32_t rd_dis_rtc_ram_boot_err: 1;
uint32_t rd_dis_icache_err: 1;
uint32_t rd_dis_dcache_err: 1;
uint32_t rd_dis_download_icache_err: 1;
uint32_t rd_dis_download_dcache_err: 1;
uint32_t rd_dis_force_download: 1;
uint32_t rd_dis_usb_err: 1;
uint32_t rd_dis_can_err: 1;
uint32_t rd_dis_sdio_access_err: 1;
uint32_t rd_dis_efuse_ate_wr_err: 1;
uint32_t rd_soft_dis_jtag_err: 1;
uint32_t rd_hard_dis_jtag_err: 1;
uint32_t rd_dis_download_manual_encrypt_err: 1;
uint32_t rd_usb_drefh_err: 2;
uint32_t rd_usb_drefl_err: 2;
uint32_t rd_usb_exchg_pins_err: 1;
uint32_t rd_ext_phy_enable: 1;
uint32_t rd_usb_force: 1;
uint32_t rd_usb_dres_err: 2;
uint32_t rd_sdio_modecurlim_err: 1;
uint32_t rd_sdio_drefh_err: 2;
};
uint32_t val;
} rd_repeat_err0;
union {
struct {
uint32_t rd_sdio_drefm_err: 2;
uint32_t rd_sdio_drefl_err: 2;
uint32_t rd_sdio_xpd_err: 1;
uint32_t rd_sdio_tieh_err: 1;
uint32_t rd_sdio_force_err: 1;
uint32_t rd_sdio_en_init_err: 1;
uint32_t rd_sdio_encurlim_err: 1;
uint32_t rd_sdio_dcurlim_err: 3;
uint32_t rd_sdio_init_err: 2;
uint32_t rd_sdio_dcap_err: 2;
uint32_t rd_wdt_delay_sel_err: 2;
uint32_t rd_spi_boot_crypt_cnt_err: 3;
uint32_t rd_secure_boot_key_revoke0_err: 1;
uint32_t rd_secure_boot_key_revoke1_err: 1;
uint32_t rd_secure_boot_key_revoke2_err: 1;
uint32_t rd_key_purpose_0_err: 4;
uint32_t rd_key_purpose_1_err: 4;
};
uint32_t val;
} rd_repeat_err1;
union {
struct {
uint32_t rd_key_purpose_2_err: 4;
uint32_t rd_key_purpose_3_err: 4;
uint32_t rd_key_purpose_4_err: 4;
uint32_t rd_key_purpose_5_err: 4;
uint32_t rd_key_purpose_6_err: 4;
uint32_t rd_secure_boot_en_err: 1;
uint32_t rd_secure_boot_aggressive_revoke_err: 1;
uint32_t rd_xtal_freq_err: 6;
uint32_t rd_flash_tpuw_err: 4;
};
uint32_t val;
} rd_repeat_err2;
union {
struct {
uint32_t rd_dis_download_mode_err: 1;
uint32_t rd_dis_legacy_spi_boot_err: 1;
uint32_t rd_uart_print_channel: 1;
uint32_t rd_dis_tiny_basic: 1;
uint32_t rd_dis_usb_download_mode: 1;
uint32_t rd_enable_security_download: 1;
uint32_t rd_uart_print_control: 2;
uint32_t rd_reserve_err: 24;
};
uint32_t val;
} rd_repeat_err3;
uint32_t reserved_18c;
union {
struct {
uint32_t rd_chip_version_err:24;
uint32_t reserved24: 8;
};
uint32_t val;
} rd_repeat_err4;
union {
struct {
uint32_t rd_mac_spi_8m_err_num: 3;
uint32_t rd_mac_spi_8m_fail: 1;
uint32_t rd_sys_err_num: 3;
uint32_t rd_sys_err_fail: 1;
uint32_t rd_usr_data_err_num: 3;
uint32_t rd_usr_data_fail: 1;
uint32_t rd_key0_err_num: 3;
uint32_t rd_key0_fail: 1;
uint32_t rd_key1_err_num: 3;
uint32_t rd_key1_fail: 1;
uint32_t rd_key2_err_num: 3;
uint32_t rd_key2_fail: 1;
uint32_t rd_key3_err_num: 3;
uint32_t rd_key3_fail: 1;
uint32_t rd_key4_err_num: 3;
uint32_t rd_key4_fail: 1;
};
uint32_t val;
} rd_rs_err0;
union {
struct {
uint32_t rd_key5_err_num: 3;
uint32_t rd_key5_fail: 1;
uint32_t rd_key6_err_num: 3;
uint32_t rd_key6_fail: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} rd_rs_err1;
union {
struct {
uint32_t mem_pd: 1;
uint32_t reserved1: 15;
uint32_t clk_en: 1;
uint32_t reserved17:15;
};
uint32_t val;
} clk;
union {
struct {
uint32_t op_code: 16;
uint32_t reserved16:16;
};
uint32_t val;
} conf;
union {
struct {
uint32_t state: 3;
uint32_t otp_load_sw: 1;
uint32_t otp_vddq_c_sync2: 1;
uint32_t otp_strobe_sw: 1;
uint32_t otp_csb_sw: 1;
uint32_t otp_pgenb_sw: 1;
uint32_t otp_vddq_is_sw: 1;
uint32_t repeat_err_cnt: 8;
uint32_t reserved17: 15;
};
uint32_t val;
} status;
union {
struct {
uint32_t read_cmd: 1;
uint32_t pgm_cmd: 1;
uint32_t blk_num: 4;
uint32_t reserved6: 26;
};
uint32_t val;
} cmd;
union {
struct {
uint32_t read_done: 1;
uint32_t pgm_done: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t read_done: 1;
uint32_t pgm_done: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t read_done: 1;
uint32_t pgm_done: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t read_done: 1;
uint32_t pgm_done: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t dac_clk_div: 8;
uint32_t dac_clk_pad_sel: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} dac_conf;
union {
struct {
uint32_t thr_a: 8;
uint32_t trd: 8;
uint32_t tsur_a: 8;
uint32_t read_init_num: 8;
};
uint32_t val;
} rd_tim_conf;
union {
struct {
uint32_t thp_a: 8;
uint32_t tpgm_inactive: 8;
uint32_t tpgm: 16;
};
uint32_t val;
} wr_tim_conf0;
union {
struct {
uint32_t tsup_a: 8;
uint32_t pwr_on_num:16;
uint32_t reserved24: 8;
};
uint32_t val;
} wr_tim_conf1;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t date; /**/
} efuse_dev_t;
extern efuse_dev_t EFUSE;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_EFUSE_STRUCT_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/extmem_reg.h
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tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/fe_reg.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/soc.h"
/* Some of the RF frontend control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
#define FE_IQ_EST_FORCE_PU (BIT(5))
#define FE_IQ_EST_FORCE_PU_M (BIT(5))
#define FE_IQ_EST_FORCE_PU_V 1
#define FE_IQ_EST_FORCE_PU_S 5
#define FE_IQ_EST_FORCE_PD (BIT(4))
#define FE_IQ_EST_FORCE_PD_M (BIT(4))
#define FE_IQ_EST_FORCE_PD_V 1
#define FE_IQ_EST_FORCE_PD_S 4
#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
#define FE2_TX_INF_FORCE_PU (BIT(10))
#define FE2_TX_INF_FORCE_PU_M (BIT(10))
#define FE2_TX_INF_FORCE_PU_V 1
#define FE2_TX_INF_FORCE_PU_S 10
#define FE2_TX_INF_FORCE_PD (BIT(9))
#define FE2_TX_INF_FORCE_PD_M (BIT(9))
#define FE2_TX_INF_FORCE_PD_V 1
#define FE2_TX_INF_FORCE_PD_S 9
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/frc_timer_reg.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_FRC_TIMER_REG_H_
#define _SOC_FRC_TIMER_REG_H_
#include "soc.h"
/**
* These are the register definitions for "legacy" timers
*/
#define REG_FRC_TIMER_BASE(i) (DR_REG_FRC_TIMER_BASE + i*0x20)
#define FRC_TIMER_LOAD_REG(i) (REG_FRC_TIMER_BASE(i) + 0x0) // timer load value (23 bit for i==0, 32 bit for i==1)
#define FRC_TIMER_LOAD_VALUE(i) ((i == 0)?0x007FFFFF:0xffffffff)
#define FRC_TIMER_LOAD_VALUE_S 0
#define FRC_TIMER_COUNT_REG(i) (REG_FRC_TIMER_BASE(i) + 0x4) // timer count value (23 bit for i==0, 32 bit for i==1)
#define FRC_TIMER_COUNT ((i == 0)?0x007FFFFF:0xffffffff)
#define FRC_TIMER_COUNT_S 0
#define FRC_TIMER_CTRL_REG(i) (REG_FRC_TIMER_BASE(i) + 0x8)
#define FRC_TIMER_INT_STATUS (BIT(8)) // interrupt status (RO)
#define FRC_TIMER_ENABLE (BIT(7)) // enable timer
#define FRC_TIMER_AUTOLOAD (BIT(6)) // enable autoload
#define FRC_TIMER_PRESCALER 0x00000007
#define FRC_TIMER_PRESCALER_S 1
#define FRC_TIMER_PRESCALER_1 (0 << FRC_TIMER_PRESCALER_S)
#define FRC_TIMER_PRESCALER_16 (2 << FRC_TIMER_PRESCALER_S)
#define FRC_TIMER_PRESCALER_256 (4 << FRC_TIMER_PRESCALER_S)
#define FRC_TIMER_LEVEL_INT (BIT(0)) // 1: level, 0: edge
#define FRC_TIMER_INT_REG(i) (REG_FRC_TIMER_BASE(i) + 0xC)
#define FRC_TIMER_INT_CLR (BIT(0)) // clear interrupt
#define FRC_TIMER_ALARM_REG(i) (REG_FRC_TIMER_BASE(i) + 0x10) // timer alarm value; register only present for i == 1
#define FRC_TIMER_ALARM 0xFFFFFFFF
#define FRC_TIMER_ALARM_S 0
#endif //_SOC_FRC_TIMER_REG_H_
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_caps.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-S2 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define GPIO_PIN_COUNT (48)
// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-S2
#define GPIO_SUPPORTS_FORCE_HOLD (1)
#define GPIO_PRO_CPU_INTR_ENA (BIT(0))
#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(1))
#define GPIO_MODE_DEF_DISABLE (0)
#define GPIO_MODE_DEF_INPUT (BIT0)
#define GPIO_MODE_DEF_OUTPUT (BIT1)
#define GPIO_MODE_DEF_OD (BIT2)
#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */
#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_46))) /*!< Check whether it contains input io */
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_reg.h
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tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_sd_reg.h
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_SD_REG_H_
#define _SOC_GPIO_SD_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
#define GPIO_SD0_PRESCALE_V 0xFF
#define GPIO_SD0_PRESCALE_S 8
/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD0_IN 0x000000FF
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
#define GPIO_SD0_IN_V 0xFF
#define GPIO_SD0_IN_S 0
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004)
/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD1_PRESCALE 0x000000FF
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
#define GPIO_SD1_PRESCALE_V 0xFF
#define GPIO_SD1_PRESCALE_S 8
/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD1_IN 0x000000FF
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
#define GPIO_SD1_IN_V 0xFF
#define GPIO_SD1_IN_S 0
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008)
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD2_PRESCALE 0x000000FF
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
#define GPIO_SD2_PRESCALE_V 0xFF
#define GPIO_SD2_PRESCALE_S 8
/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD2_IN 0x000000FF
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
#define GPIO_SD2_IN_V 0xFF
#define GPIO_SD2_IN_S 0
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c)
/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD3_PRESCALE 0x000000FF
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
#define GPIO_SD3_PRESCALE_V 0xFF
#define GPIO_SD3_PRESCALE_S 8
/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD3_IN 0x000000FF
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
#define GPIO_SD3_IN_V 0xFF
#define GPIO_SD3_IN_S 0
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010)
/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD4_PRESCALE 0x000000FF
#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
#define GPIO_SD4_PRESCALE_V 0xFF
#define GPIO_SD4_PRESCALE_S 8
/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD4_IN 0x000000FF
#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
#define GPIO_SD4_IN_V 0xFF
#define GPIO_SD4_IN_S 0
#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014)
/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD5_PRESCALE 0x000000FF
#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
#define GPIO_SD5_PRESCALE_V 0xFF
#define GPIO_SD5_PRESCALE_S 8
/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD5_IN 0x000000FF
#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
#define GPIO_SD5_IN_V 0xFF
#define GPIO_SD5_IN_S 0
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018)
/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD6_PRESCALE 0x000000FF
#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
#define GPIO_SD6_PRESCALE_V 0xFF
#define GPIO_SD6_PRESCALE_S 8
/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD6_IN 0x000000FF
#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
#define GPIO_SD6_IN_V 0xFF
#define GPIO_SD6_IN_S 0
#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c)
/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD7_PRESCALE 0x000000FF
#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
#define GPIO_SD7_PRESCALE_V 0xFF
#define GPIO_SD7_PRESCALE_S 8
/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD7_IN 0x000000FF
#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
#define GPIO_SD7_IN_V 0xFF
#define GPIO_SD7_IN_S 0
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020)
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define GPIO_SD_CLK_EN (BIT(31))
#define GPIO_SD_CLK_EN_M (BIT(31))
#define GPIO_SD_CLK_EN_V 0x1
#define GPIO_SD_CLK_EN_S 31
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024)
/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define GPIO_SPI_SWAP (BIT(31))
#define GPIO_SPI_SWAP_M (BIT(31))
#define GPIO_SPI_SWAP_V 0x1
#define GPIO_SPI_SWAP_S 31
/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
/*description: */
#define GPIO_FUNCTION_CLK_EN (BIT(30))
#define GPIO_FUNCTION_CLK_EN_M (BIT(30))
#define GPIO_FUNCTION_CLK_EN_V 0x1
#define GPIO_FUNCTION_CLK_EN_S 30
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028)
/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */
/*description: */
#define GPIO_SD_DATE 0x0FFFFFFF
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
#define GPIO_SD_DATE_V 0xFFFFFFF
#define GPIO_SD_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_GPIO_SD_REG_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_sd_struct.h
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_SD_STRUCT_H_
#define _SOC_GPIO_SD_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t duty: 8;
uint32_t prescale: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} channel[8];
union {
struct {
uint32_t reserved0: 31;
uint32_t clk_en: 1;
};
uint32_t val;
} cg;
union {
struct {
uint32_t reserved0: 30;
uint32_t function_clk_en: 1;
uint32_t spi_swap: 1;
};
uint32_t val;
} misc;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} version;
} gpio_sd_dev_t;
extern gpio_sd_dev_t SIGMADELTA;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_GPIO_SD_STRUCT_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_sig_map.h
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_
#define SPICLK_OUT_IDX SPICLK_OUT_MUX_IDX
#define CLK_I2S_IDX CLK_I2S_MUX_IDX
#define FSPICLK_OUT_IDX FSPICLK_OUT_MUX_IDX
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
#define SPID_IN_IDX 1
#define SPID_OUT_IDX 1
#define SPIHD_IN_IDX 2
#define SPIHD_OUT_IDX 2
#define SPIWP_IN_IDX 3
#define SPIWP_OUT_IDX 3
#define SPICLK_OUT_MUX_IDX 4
#define SPICS0_OUT_IDX 5
#define SPICS1_OUT_IDX 6
#define SPID4_IN_IDX 7
#define SPID4_OUT_IDX 7
#define SPID5_IN_IDX 8
#define SPID5_OUT_IDX 8
#define SPID6_IN_IDX 9
#define SPID6_OUT_IDX 9
#define SPID7_IN_IDX 10
#define SPID7_OUT_IDX 10
#define SPIDQS_IN_IDX 11
#define SPIDQS_OUT_IDX 11
#define U0RXD_IN_IDX 14
#define U0TXD_OUT_IDX 14
#define U0CTS_IN_IDX 15
#define U0RTS_OUT_IDX 15
#define U0DSR_IN_IDX 16
#define U0DTR_OUT_IDX 16
#define U1RXD_IN_IDX 17
#define U1TXD_OUT_IDX 17
#define U1CTS_IN_IDX 18
#define U1RTS_OUT_IDX 18
#define U1DSR_IN_IDX 21
#define U1DTR_OUT_IDX 21
#define I2S0O_BCK_IN_IDX 23
#define I2S0O_BCK_OUT_IDX 23
#define I2S0O_WS_IN_IDX 25
#define I2S0O_WS_OUT_IDX 25
#define I2S0I_BCK_IN_IDX 27
#define I2S0I_BCK_OUT_IDX 27
#define I2S0I_WS_IN_IDX 28
#define I2S0I_WS_OUT_IDX 28
#define I2CEXT0_SCL_IN_IDX 29
#define I2CEXT0_SCL_OUT_IDX 29
#define I2CEXT0_SDA_IN_IDX 30
#define I2CEXT0_SDA_OUT_IDX 30
#define SDIO_TOHOST_INT_OUT_IDX 31
#define GPIO_BT_ACTIVE_IDX 37
#define GPIO_BT_PRIORITY_IDX 38
#define PCNT_SIG_CH0_IN0_IDX 39
#define GPIO_WLAN_PRIO_IDX 39
#define PCNT_SIG_CH1_IN0_IDX 40
#define GPIO_WLAN_ACTIVE_IDX 40
#define PCNT_CTRL_CH0_IN0_IDX 41
#define BB_DIAG0_IDX 41
#define PCNT_CTRL_CH1_IN0_IDX 42
#define BB_DIAG1_IDX 42
#define PCNT_SIG_CH0_IN1_IDX 43
#define BB_DIAG2_IDX 43
#define PCNT_SIG_CH1_IN1_IDX 44
#define BB_DIAG3_IDX 44
#define PCNT_CTRL_CH0_IN1_IDX 45
#define BB_DIAG4_IDX 45
#define PCNT_CTRL_CH1_IN1_IDX 46
#define BB_DIAG5_IDX 46
#define PCNT_SIG_CH0_IN2_IDX 47
#define BB_DIAG6_IDX 47
#define PCNT_SIG_CH1_IN2_IDX 48
#define BB_DIAG7_IDX 48
#define PCNT_CTRL_CH0_IN2_IDX 49
#define BB_DIAG8_IDX 49
#define PCNT_CTRL_CH1_IN2_IDX 50
#define BB_DIAG9_IDX 50
#define PCNT_SIG_CH0_IN3_IDX 51
#define BB_DIAG10_IDX 51
#define PCNT_SIG_CH1_IN3_IDX 52
#define BB_DIAG11_IDX 52
#define PCNT_CTRL_CH0_IN3_IDX 53
#define BB_DIAG12_IDX 53
#define PCNT_CTRL_CH1_IN3_IDX 54
#define BB_DIAG13_IDX 54
#define BB_DIAG14_IDX 55
#define BB_DIAG15_IDX 56
#define BB_DIAG16_IDX 57
#define BB_DIAG17_IDX 58
#define BB_DIAG18_IDX 59
#define BB_DIAG19_IDX 60
#define USB_EXTPHY_VP_IDX 61
#define USB_EXTPHY_OEN_IDX 61
#define USB_EXTPHY_VM_IDX 62
#define USB_EXTPHY_SPEED_IDX 62
#define USB_EXTPHY_RCV_IDX 63
#define USB_EXTPHY_VPO_IDX 63
#define USB_OTG_IDDIG_IN_IDX 64
#define USB_EXTPHY_VMO_IDX 64
#define USB_OTG_AVALID_IN_IDX 65
#define USB_EXTPHY_SUSPND_IDX 65
#define USB_SRP_BVALID_IN_IDX 66
#define USB_OTG_IDPULLUP_IDX 66
#define USB_OTG_VBUSVALID_IN_IDX 67
#define USB_OTG_DPPULLDOWN_IDX 67
#define USB_SRP_SESSEND_IN_IDX 68
#define USB_OTG_DMPULLDOWN_IDX 68
#define USB_OTG_DRVVBUS_IDX 69
#define USB_SRP_CHRGVBUS_IDX 70
#define USB_SRP_DISCHRGVBUS_IDX 71
#define SPI3_CLK_IN_IDX 72
#define SPI3_CLK_OUT_MUX_IDX 72
#define SPI3_Q_IN_IDX 73
#define SPI3_Q_OUT_IDX 73
#define SPI3_D_IN_IDX 74
#define SPI3_D_OUT_IDX 74
#define SPI3_HD_IN_IDX 75
#define SPI3_HD_OUT_IDX 75
#define SPI3_CS0_IN_IDX 76
#define SPI3_CS0_OUT_IDX 76
#define SPI3_CS1_OUT_IDX 77
#define SPI3_CS2_OUT_IDX 78
#define LEDC_LS_SIG_OUT0_IDX 79
#define LEDC_LS_SIG_OUT1_IDX 80
#define LEDC_LS_SIG_OUT2_IDX 81
#define LEDC_LS_SIG_OUT3_IDX 82
#define RMT_SIG_IN0_IDX 83
#define LEDC_LS_SIG_OUT4_IDX 83
#define RMT_SIG_IN1_IDX 84
#define LEDC_LS_SIG_OUT5_IDX 84
#define RMT_SIG_IN2_IDX 85
#define LEDC_LS_SIG_OUT6_IDX 85
#define RMT_SIG_IN3_IDX 86
#define LEDC_LS_SIG_OUT7_IDX 86
#define RMT_SIG_OUT0_IDX 87
#define RMT_SIG_OUT1_IDX 88
#define RMT_SIG_OUT2_IDX 89
#define RMT_SIG_OUT3_IDX 90
#define EXT_ADC_START_IDX 93
#define I2CEXT1_SCL_IN_IDX 95
#define I2CEXT1_SCL_OUT_IDX 95
#define I2CEXT1_SDA_IN_IDX 96
#define I2CEXT1_SDA_OUT_IDX 96
#define GPIO_SD0_OUT_IDX 100
#define GPIO_SD1_OUT_IDX 101
#define GPIO_SD2_OUT_IDX 102
#define GPIO_SD3_OUT_IDX 103
#define GPIO_SD4_OUT_IDX 104
#define GPIO_SD5_OUT_IDX 105
#define GPIO_SD6_OUT_IDX 106
#define GPIO_SD7_OUT_IDX 107
#define FSPICLK_IN_IDX 108
#define FSPICLK_OUT_MUX_IDX 108
#define FSPIQ_IN_IDX 109
#define FSPIQ_OUT_IDX 109
#define FSPID_IN_IDX 110
#define FSPID_OUT_IDX 110
#define FSPIHD_IN_IDX 111
#define FSPIHD_OUT_IDX 111
#define FSPIWP_IN_IDX 112
#define FSPIWP_OUT_IDX 112
#define FSPIIO4_IN_IDX 113
#define FSPIIO4_OUT_IDX 113
#define FSPIIO5_IN_IDX 114
#define FSPIIO5_OUT_IDX 114
#define FSPIIO6_IN_IDX 115
#define FSPIIO6_OUT_IDX 115
#define FSPIIO7_IN_IDX 116
#define FSPIIO7_OUT_IDX 116
#define FSPICS0_IN_IDX 117
#define FSPICS0_OUT_IDX 117
#define FSPICS1_OUT_IDX 118
#define FSPICS2_OUT_IDX 119
#define FSPICS3_OUT_IDX 120
#define FSPICS4_OUT_IDX 121
#define FSPICS5_OUT_IDX 122
#define CAN_RX_IDX 123
#define CAN_TX_IDX 123
#define CAN_BUS_OFF_ON_IDX 124
#define CAN_CLKOUT_IDX 125
#define SUBSPICLK_OUT_MUX_IDX 126
#define SUBSPIQ_IN_IDX 127
#define SUBSPIQ_OUT_IDX 127
#define SUBSPID_IN_IDX 128
#define SUBSPID_OUT_IDX 128
#define SUBSPIHD_IN_IDX 129
#define SUBSPIHD_OUT_IDX 129
#define SUBSPIWP_IN_IDX 130
#define SUBSPIWP_OUT_IDX 130
#define SUBSPICS0_OUT_IDX 131
#define SUBSPICS1_OUT_IDX 132
#define FSPIDQS_OUT_IDX 133
#define FSPI_HSYNC_OUT_IDX 134
#define FSPI_VSYNC_OUT_IDX 135
#define FSPI_DE_OUT_IDX 136
#define FSPICD_OUT_IDX 137
#define SPI3_CD_OUT_IDX 139
#define SPI3_DQS_OUT_IDX 140
#define I2S0I_DATA_IN0_IDX 143
#define I2S0O_DATA_OUT0_IDX 143
#define I2S0I_DATA_IN1_IDX 144
#define I2S0O_DATA_OUT1_IDX 144
#define I2S0I_DATA_IN2_IDX 145
#define I2S0O_DATA_OUT2_IDX 145
#define I2S0I_DATA_IN3_IDX 146
#define I2S0O_DATA_OUT3_IDX 146
#define I2S0I_DATA_IN4_IDX 147
#define I2S0O_DATA_OUT4_IDX 147
#define I2S0I_DATA_IN5_IDX 148
#define I2S0O_DATA_OUT5_IDX 148
#define I2S0I_DATA_IN6_IDX 149
#define I2S0O_DATA_OUT6_IDX 149
#define I2S0I_DATA_IN7_IDX 150
#define I2S0O_DATA_OUT7_IDX 150
#define I2S0I_DATA_IN8_IDX 151
#define I2S0O_DATA_OUT8_IDX 151
#define I2S0I_DATA_IN9_IDX 152
#define I2S0O_DATA_OUT9_IDX 152
#define I2S0I_DATA_IN10_IDX 153
#define I2S0O_DATA_OUT10_IDX 153
#define I2S0I_DATA_IN11_IDX 154
#define I2S0O_DATA_OUT11_IDX 154
#define I2S0I_DATA_IN12_IDX 155
#define I2S0O_DATA_OUT12_IDX 155
#define I2S0I_DATA_IN13_IDX 156
#define I2S0O_DATA_OUT13_IDX 156
#define I2S0I_DATA_IN14_IDX 157
#define I2S0O_DATA_OUT14_IDX 157
#define I2S0I_DATA_IN15_IDX 158
#define I2S0O_DATA_OUT15_IDX 158
#define I2S0O_DATA_OUT16_IDX 159
#define I2S0O_DATA_OUT17_IDX 160
#define I2S0O_DATA_OUT18_IDX 161
#define I2S0O_DATA_OUT19_IDX 162
#define I2S0O_DATA_OUT20_IDX 163
#define I2S0O_DATA_OUT21_IDX 164
#define I2S0O_DATA_OUT22_IDX 165
#define I2S0O_DATA_OUT23_IDX 166
#define SUBSPID4_IN_IDX 167
#define SUBSPID4_OUT_IDX 167
#define SUBSPID5_IN_IDX 168
#define SUBSPID5_OUT_IDX 168
#define SUBSPID6_IN_IDX 169
#define SUBSPID6_OUT_IDX 169
#define SUBSPID7_IN_IDX 170
#define SUBSPID7_OUT_IDX 170
#define SUBSPIDQS_IN_IDX 171
#define SUBSPIDQS_OUT_IDX 171
#define I2S0I_H_SYNC_IDX 193
#define I2S0I_V_SYNC_IDX 194
#define I2S0I_H_ENABLE_IDX 195
#define PCMFSYNC_IN_IDX 203
#define BT_AUDIO0_IRQ_IDX 203
#define PCMCLK_IN_IDX 204
#define BT_AUDIO1_IRQ_IDX 204
#define PCMDIN_IDX 205
#define BT_AUDIO2_IRQ_IDX 205
#define RW_WAKEUP_REQ_IDX 206
#define BLE_AUDIO0_IRQ_IDX 206
#define BLE_AUDIO1_IRQ_IDX 207
#define BLE_AUDIO2_IRQ_IDX 208
#define PCMFSYNC_OUT_IDX 209
#define PCMCLK_OUT_IDX 210
#define PCMDOUT_IDX 211
#define BLE_AUDIO_SYNC0_P_IDX 212
#define BLE_AUDIO_SYNC1_P_IDX 213
#define BLE_AUDIO_SYNC2_P_IDX 214
#define ANT_SEL0_IDX 215
#define ANT_SEL1_IDX 216
#define ANT_SEL2_IDX 217
#define ANT_SEL3_IDX 218
#define ANT_SEL4_IDX 219
#define ANT_SEL5_IDX 220
#define ANT_SEL6_IDX 221
#define ANT_SEL7_IDX 222
#define SIG_IN_FUNC_223_IDX 223
#define SIG_IN_FUNC223_IDX 223
#define SIG_IN_FUNC_224_IDX 224
#define SIG_IN_FUNC224_IDX 224
#define SIG_IN_FUNC_225_IDX 225
#define SIG_IN_FUNC225_IDX 225
#define SIG_IN_FUNC_226_IDX 226
#define SIG_IN_FUNC226_IDX 226
#define SIG_IN_FUNC_227_IDX 227
#define SIG_IN_FUNC227_IDX 227
#define PRO_ALONEGPIO_IN0_IDX 235
#define PRO_ALONEGPIO_OUT0_IDX 235
#define PRO_ALONEGPIO_IN1_IDX 236
#define PRO_ALONEGPIO_OUT1_IDX 236
#define PRO_ALONEGPIO_IN2_IDX 237
#define PRO_ALONEGPIO_OUT2_IDX 237
#define PRO_ALONEGPIO_IN3_IDX 238
#define PRO_ALONEGPIO_OUT3_IDX 238
#define PRO_ALONEGPIO_IN4_IDX 239
#define PRO_ALONEGPIO_OUT4_IDX 239
#define PRO_ALONEGPIO_IN5_IDX 240
#define PRO_ALONEGPIO_OUT5_IDX 240
#define PRO_ALONEGPIO_IN6_IDX 241
#define PRO_ALONEGPIO_OUT6_IDX 241
#define PRO_ALONEGPIO_IN7_IDX 242
#define PRO_ALONEGPIO_OUT7_IDX 242
#define CLK_I2S_MUX_IDX 251
#define SIG_GPIO_OUT_IDX 256
#define GPIO_MAP_DATE_IDX 0x1904100
#endif /* _SOC_GPIO_SIG_MAP_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_struct.h
+252
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_STRUCT_H_
#define _SOC_GPIO_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
uint32_t bt_select; /**/
uint32_t out; /**/
uint32_t out_w1ts; /**/
uint32_t out_w1tc; /**/
union {
struct {
uint32_t data: 22;
uint32_t reserved22:10;
};
uint32_t val;
} out1;
union {
struct {
uint32_t data: 22;
uint32_t reserved22:10;
};
uint32_t val;
} out1_w1ts;
union {
struct {
uint32_t data: 22;
uint32_t reserved22:10;
};
uint32_t val;
} out1_w1tc;
union {
struct {
uint32_t sel: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} sdio_select;
uint32_t enable; /**/
uint32_t enable_w1ts; /**/
uint32_t enable_w1tc; /**/
union {
struct {
uint32_t data: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} enable1;
union {
struct {
uint32_t data: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} enable1_w1ts;
union {
struct {
uint32_t data: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} enable1_w1tc;
union {
struct {
uint32_t strapping: 16;
uint32_t reserved16:16;
};
uint32_t val;
} strap;
uint32_t in; /**/
union {
struct {
uint32_t data: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} in1;
uint32_t status; /**/
uint32_t status_w1ts; /**/
uint32_t status_w1tc; /**/
union {
struct {
uint32_t intr_st: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} status1;
union {
struct {
uint32_t intr_st: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} status1_w1ts;
union {
struct {
uint32_t intr_st: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} status1_w1tc;
uint32_t pcpu_int; /**/
uint32_t pcpu_nmi_int; /**/
uint32_t cpusdio_int; /**/
union {
struct {
uint32_t intr: 22;
uint32_t reserved22:10;
};
uint32_t val;
} pcpu_int1;
union {
struct {
uint32_t intr: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} pcpu_nmi_int1;
union {
struct {
uint32_t intr: 22;
uint32_t reserved22:10;
};
uint32_t val;
} cpusdio_int1;
union {
struct {
uint32_t sync2_bypass: 2;
uint32_t pad_driver: 1;
uint32_t sync1_bypass: 2;
uint32_t reserved5: 2;
uint32_t int_type: 3;
uint32_t wakeup_enable: 1;
uint32_t config: 2;
uint32_t int_ena: 5;
uint32_t reserved18: 14;
};
uint32_t val;
} pin[54];
uint32_t status_next; /**/
union {
struct {
uint32_t intr_st_next: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} status_next1;
union {
struct {
uint32_t func_sel: 6;
uint32_t sig_in_inv: 1;
uint32_t sig_in_sel: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} func_in_sel_cfg[256];
union {
struct {
uint32_t func_sel: 9;
uint32_t inv_sel: 1;
uint32_t oen_sel: 1;
uint32_t oen_inv_sel: 1;
uint32_t reserved12: 20;
};
uint32_t val;
} func_out_sel_cfg[54];
union {
struct {
uint32_t clk_en: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} clock_gate;
uint32_t reserved_630;
uint32_t reserved_634;
uint32_t reserved_638;
uint32_t reserved_63c;
uint32_t reserved_640;
uint32_t reserved_644;
uint32_t reserved_648;
uint32_t reserved_64c;
uint32_t reserved_650;
uint32_t reserved_654;
uint32_t reserved_658;
uint32_t reserved_65c;
uint32_t reserved_660;
uint32_t reserved_664;
uint32_t reserved_668;
uint32_t reserved_66c;
uint32_t reserved_670;
uint32_t reserved_674;
uint32_t reserved_678;
uint32_t reserved_67c;
uint32_t reserved_680;
uint32_t reserved_684;
uint32_t reserved_688;
uint32_t reserved_68c;
uint32_t reserved_690;
uint32_t reserved_694;
uint32_t reserved_698;
uint32_t reserved_69c;
uint32_t reserved_6a0;
uint32_t reserved_6a4;
uint32_t reserved_6a8;
uint32_t reserved_6ac;
uint32_t reserved_6b0;
uint32_t reserved_6b4;
uint32_t reserved_6b8;
uint32_t reserved_6bc;
uint32_t reserved_6c0;
uint32_t reserved_6c4;
uint32_t reserved_6c8;
uint32_t reserved_6cc;
uint32_t reserved_6d0;
uint32_t reserved_6d4;
uint32_t reserved_6d8;
uint32_t reserved_6dc;
uint32_t reserved_6e0;
uint32_t reserved_6e4;
uint32_t reserved_6e8;
uint32_t reserved_6ec;
uint32_t reserved_6f0;
uint32_t reserved_6f4;
uint32_t reserved_6f8;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} date;
} gpio_dev_t;
extern gpio_dev_t GPIO;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_GPIO_STRUCT_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/hinf_reg.h
+248
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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_HINF_REG_H_
#define _SOC_HINF_REG_H_
#include "soc.h"
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
/*description: */
#define HINF_DEVICE_ID_FN1 0x0000FFFF
#define HINF_DEVICE_ID_FN1_M ((HINF_DEVICE_ID_FN1_V)<<(HINF_DEVICE_ID_FN1_S))
#define HINF_DEVICE_ID_FN1_V 0xFFFF
#define HINF_DEVICE_ID_FN1_S 16
/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
/*description: */
#define HINF_USER_ID_FN1 0x0000FFFF
#define HINF_USER_ID_FN1_M ((HINF_USER_ID_FN1_V)<<(HINF_USER_ID_FN1_S))
#define HINF_USER_ID_FN1_V 0xFFFF
#define HINF_USER_ID_FN1_S 0
#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */
/*description: */
#define HINF_SDIO20_CONF1 0x00000007
#define HINF_SDIO20_CONF1_M ((HINF_SDIO20_CONF1_V)<<(HINF_SDIO20_CONF1_S))
#define HINF_SDIO20_CONF1_V 0x7
#define HINF_SDIO20_CONF1_S 29
/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define HINF_FUNC2_EPS (BIT(28))
#define HINF_FUNC2_EPS_M (BIT(28))
#define HINF_FUNC2_EPS_V 0x1
#define HINF_FUNC2_EPS_S 28
/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */
/*description: */
#define HINF_SDIO_VER 0x00000FFF
#define HINF_SDIO_VER_M ((HINF_SDIO_VER_V)<<(HINF_SDIO_VER_S))
#define HINF_SDIO_VER_V 0xFFF
#define HINF_SDIO_VER_S 16
/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */
/*description: */
#define HINF_SDIO20_CONF0 0x0000000F
#define HINF_SDIO20_CONF0_M ((HINF_SDIO20_CONF0_V)<<(HINF_SDIO20_CONF0_S))
#define HINF_SDIO20_CONF0_V 0xF
#define HINF_SDIO20_CONF0_S 12
/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define HINF_IOENABLE1 (BIT(11))
#define HINF_IOENABLE1_M (BIT(11))
#define HINF_IOENABLE1_V 0x1
#define HINF_IOENABLE1_S 11
/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define HINF_EMP (BIT(10))
#define HINF_EMP_M (BIT(10))
#define HINF_EMP_V 0x1
#define HINF_EMP_S 10
/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define HINF_FUNC1_EPS (BIT(9))
#define HINF_FUNC1_EPS_M (BIT(9))
#define HINF_FUNC1_EPS_V 0x1
#define HINF_FUNC1_EPS_S 9
/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define HINF_CD_DISABLE (BIT(8))
#define HINF_CD_DISABLE_M (BIT(8))
#define HINF_CD_DISABLE_V 0x1
#define HINF_CD_DISABLE_S 8
/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define HINF_IOENABLE2 (BIT(7))
#define HINF_IOENABLE2_M (BIT(7))
#define HINF_IOENABLE2_V 0x1
#define HINF_IOENABLE2_S 7
/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define HINF_SDIO_INT_MASK (BIT(6))
#define HINF_SDIO_INT_MASK_M (BIT(6))
#define HINF_SDIO_INT_MASK_V 0x1
#define HINF_SDIO_INT_MASK_S 6
/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define HINF_SDIO_IOREADY2 (BIT(5))
#define HINF_SDIO_IOREADY2_M (BIT(5))
#define HINF_SDIO_IOREADY2_V 0x1
#define HINF_SDIO_IOREADY2_S 5
/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define HINF_SDIO_CD_ENABLE (BIT(4))
#define HINF_SDIO_CD_ENABLE_M (BIT(4))
#define HINF_SDIO_CD_ENABLE_V 0x1
#define HINF_SDIO_CD_ENABLE_S 4
/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define HINF_HIGHSPEED_MODE (BIT(3))
#define HINF_HIGHSPEED_MODE_M (BIT(3))
#define HINF_HIGHSPEED_MODE_V 0x1
#define HINF_HIGHSPEED_MODE_S 3
/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define HINF_HIGHSPEED_ENABLE (BIT(2))
#define HINF_HIGHSPEED_ENABLE_M (BIT(2))
#define HINF_HIGHSPEED_ENABLE_V 0x1
#define HINF_HIGHSPEED_ENABLE_S 2
/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define HINF_SDIO_IOREADY1 (BIT(1))
#define HINF_SDIO_IOREADY1_M (BIT(1))
#define HINF_SDIO_IOREADY1_V 0x1
#define HINF_SDIO_IOREADY1_S 1
/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define HINF_SDIO_ENABLE (BIT(0))
#define HINF_SDIO_ENABLE_M (BIT(0))
#define HINF_SDIO_ENABLE_V 0x1
#define HINF_SDIO_ENABLE_S 0
#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C)
/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */
/*description: */
#define HINF_SDIO_IOREADY0 (BIT(17))
#define HINF_SDIO_IOREADY0_M (BIT(17))
#define HINF_SDIO_IOREADY0_V 0x1
#define HINF_SDIO_IOREADY0_S 17
/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define HINF_SDIO_RST (BIT(16))
#define HINF_SDIO_RST_M (BIT(16))
#define HINF_SDIO_RST_V 0x1
#define HINF_SDIO_RST_S 16
/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
/*description: */
#define HINF_CHIP_STATE 0x000000FF
#define HINF_CHIP_STATE_M ((HINF_CHIP_STATE_V)<<(HINF_CHIP_STATE_S))
#define HINF_CHIP_STATE_V 0xFF
#define HINF_CHIP_STATE_S 8
/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: */
#define HINF_PIN_STATE 0x000000FF
#define HINF_PIN_STATE_M ((HINF_PIN_STATE_V)<<(HINF_PIN_STATE_S))
#define HINF_PIN_STATE_V 0xFF
#define HINF_PIN_STATE_S 0
#define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20)
/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W0 0xFFFFFFFF
#define HINF_CIS_CONF_W0_M ((HINF_CIS_CONF_W0_V)<<(HINF_CIS_CONF_W0_S))
#define HINF_CIS_CONF_W0_V 0xFFFFFFFF
#define HINF_CIS_CONF_W0_S 0
#define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24)
/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W1 0xFFFFFFFF
#define HINF_CIS_CONF_W1_M ((HINF_CIS_CONF_W1_V)<<(HINF_CIS_CONF_W1_S))
#define HINF_CIS_CONF_W1_V 0xFFFFFFFF
#define HINF_CIS_CONF_W1_S 0
#define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28)
/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W2 0xFFFFFFFF
#define HINF_CIS_CONF_W2_M ((HINF_CIS_CONF_W2_V)<<(HINF_CIS_CONF_W2_S))
#define HINF_CIS_CONF_W2_V 0xFFFFFFFF
#define HINF_CIS_CONF_W2_S 0
#define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C)
/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W3 0xFFFFFFFF
#define HINF_CIS_CONF_W3_M ((HINF_CIS_CONF_W3_V)<<(HINF_CIS_CONF_W3_S))
#define HINF_CIS_CONF_W3_V 0xFFFFFFFF
#define HINF_CIS_CONF_W3_S 0
#define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30)
/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W4 0xFFFFFFFF
#define HINF_CIS_CONF_W4_M ((HINF_CIS_CONF_W4_V)<<(HINF_CIS_CONF_W4_S))
#define HINF_CIS_CONF_W4_V 0xFFFFFFFF
#define HINF_CIS_CONF_W4_S 0
#define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34)
/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W5 0xFFFFFFFF
#define HINF_CIS_CONF_W5_M ((HINF_CIS_CONF_W5_V)<<(HINF_CIS_CONF_W5_S))
#define HINF_CIS_CONF_W5_V 0xFFFFFFFF
#define HINF_CIS_CONF_W5_S 0
#define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38)
/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W6 0xFFFFFFFF
#define HINF_CIS_CONF_W6_M ((HINF_CIS_CONF_W6_V)<<(HINF_CIS_CONF_W6_S))
#define HINF_CIS_CONF_W6_V 0xFFFFFFFF
#define HINF_CIS_CONF_W6_S 0
#define HINF_CIS_CONF7_REG (DR_REG_HINF_BASE + 0x3C)
/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W7 0xFFFFFFFF
#define HINF_CIS_CONF_W7_M ((HINF_CIS_CONF_W7_V)<<(HINF_CIS_CONF_W7_S))
#define HINF_CIS_CONF_W7_V 0xFFFFFFFF
#define HINF_CIS_CONF_W7_S 0
#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */
/*description: */
#define HINF_DEVICE_ID_FN2 0x0000FFFF
#define HINF_DEVICE_ID_FN2_M ((HINF_DEVICE_ID_FN2_V)<<(HINF_DEVICE_ID_FN2_S))
#define HINF_DEVICE_ID_FN2_V 0xFFFF
#define HINF_DEVICE_ID_FN2_S 16
/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
/*description: */
#define HINF_USER_ID_FN2 0x0000FFFF
#define HINF_USER_ID_FN2_M ((HINF_USER_ID_FN2_V)<<(HINF_USER_ID_FN2_S))
#define HINF_USER_ID_FN2_V 0xFFFF
#define HINF_USER_ID_FN2_S 0
#define HINF_DATE_REG (DR_REG_HINF_BASE + 0xFC)
/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */
/*description: */
#define HINF_SDIO_DATE 0xFFFFFFFF
#define HINF_SDIO_DATE_M ((HINF_SDIO_DATE_V)<<(HINF_SDIO_DATE_S))
#define HINF_SDIO_DATE_V 0xFFFFFFFF
#define HINF_SDIO_DATE_S 0
#endif /*_SOC_HINF_REG_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/hinf_struct.h
+134
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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_HINF_STRUCT_H_
#define _SOC_HINF_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t user_id_fn1: 16;
uint32_t device_id_fn1:16;
};
uint32_t val;
} cfg_data0;
union {
struct {
uint32_t sdio_enable: 1;
uint32_t sdio_ioready1: 1;
uint32_t highspeed_enable: 1;
uint32_t highspeed_mode: 1;
uint32_t sdio_cd_enable: 1;
uint32_t sdio_ioready2: 1;
uint32_t sdio_int_mask: 1;
uint32_t ioenable2: 1;
uint32_t cd_disable: 1;
uint32_t func1_eps: 1;
uint32_t emp: 1;
uint32_t ioenable1: 1;
uint32_t sdio20_conf0: 4;
uint32_t sdio_ver: 12;
uint32_t func2_eps: 1;
uint32_t sdio20_conf1: 3;
};
uint32_t val;
} cfg_data1;
uint32_t reserved_8;
uint32_t reserved_c;
uint32_t reserved_10;
uint32_t reserved_14;
uint32_t reserved_18;
union {
struct {
uint32_t pin_state: 8;
uint32_t chip_state: 8;
uint32_t sdio_rst: 1;
uint32_t sdio_ioready0: 1;
uint32_t reserved18: 14;
};
uint32_t val;
} cfg_data7;
uint32_t cis_conf0; /**/
uint32_t cis_conf1; /**/
uint32_t cis_conf2; /**/
uint32_t cis_conf3; /**/
uint32_t cis_conf4; /**/
uint32_t cis_conf5; /**/
uint32_t cis_conf6; /**/
uint32_t cis_conf7; /**/
union {
struct {
uint32_t user_id_fn2: 16;
uint32_t device_id_fn2:16;
};
uint32_t val;
} cfg_data16;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
} hinf_dev_t;
extern hinf_dev_t HINF;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_HINF_STRUCT_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/host_reg.h
+1806
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tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/host_struct.h
+602
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_HOST_STRUCT_H_
#define _SOC_HOST_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
uint32_t reserved_c;
uint32_t reserved_10;
uint32_t reserved_14;
uint32_t reserved_18;
uint32_t reserved_1c;
union {
struct {
uint32_t func1_mdstat: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} func2_2;
uint32_t reserved_24;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t gpio_status0; /**/
union {
struct {
uint32_t sdio_int1: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} gpio_status1;
uint32_t gpio_in0; /**/
union {
struct {
uint32_t sdio_in1: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} gpio_in1;
union {
struct {
uint32_t token0: 12;
uint32_t rx_pf_valid: 1;
uint32_t reserved13: 3;
uint32_t reg_token1: 12;
uint32_t rx_pf_eof: 4;
};
uint32_t val;
} slc0_token_rdata;
uint32_t slc0_pf; /**/
uint32_t reserved_4c;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_int_raw;
uint32_t reserved_54;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_int_st;
uint32_t reserved_5c;
union {
struct {
uint32_t reg_slc0_len: 20;
uint32_t reg_slc0_len_check:12;
};
uint32_t val;
} pkt_len;
union {
struct {
uint32_t state0: 8;
uint32_t state1: 8;
uint32_t state2: 8;
uint32_t state3: 8;
};
uint32_t val;
} state_w0;
union {
struct {
uint32_t state4: 8;
uint32_t state5: 8;
uint32_t state6: 8;
uint32_t state7: 8;
};
uint32_t val;
} state_w1;
union {
struct {
uint32_t conf0: 8;
uint32_t conf1: 8;
uint32_t conf2: 8;
uint32_t conf3: 8;
};
uint32_t val;
} conf_w0;
union {
struct {
uint32_t conf4: 8;
uint32_t conf5: 8;
uint32_t conf6: 8;
uint32_t conf7: 8;
};
uint32_t val;
} conf_w1;
union {
struct {
uint32_t conf8: 8;
uint32_t conf9: 8;
uint32_t conf10: 8;
uint32_t conf11: 8;
};
uint32_t val;
} conf_w2;
union {
struct {
uint32_t conf12: 8;
uint32_t conf13: 8;
uint32_t conf14: 8;
uint32_t conf15: 8;
};
uint32_t val;
} conf_w3;
union {
struct {
uint32_t conf16: 8; /*SLC timeout value*/
uint32_t conf17: 8; /*SLC timeout enable*/
uint32_t conf18: 8;
uint32_t conf19: 8; /*Interrupt to target CPU*/
};
uint32_t val;
} conf_w4;
union {
struct {
uint32_t conf20: 8;
uint32_t conf21: 8;
uint32_t conf22: 8;
uint32_t conf23: 8;
};
uint32_t val;
} conf_w5;
union {
struct {
uint32_t win_cmd: 16;
uint32_t reserved16: 16;
};
uint32_t val;
} win_cmd;
union {
struct {
uint32_t conf24: 8;
uint32_t conf25: 8;
uint32_t conf26: 8;
uint32_t conf27: 8;
};
uint32_t val;
} conf_w6;
union {
struct {
uint32_t conf28: 8;
uint32_t conf29: 8;
uint32_t conf30: 8;
uint32_t conf31: 8;
};
uint32_t val;
} conf_w7;
union {
struct {
uint32_t reg_slc0_len0: 20;
uint32_t reg_slc0_len0_check:12;
};
uint32_t val;
} pkt_len0;
union {
struct {
uint32_t reg_slc0_len1: 20;
uint32_t reg_slc0_len1_check:12;
};
uint32_t val;
} pkt_len1;
union {
struct {
uint32_t reg_slc0_len2: 20;
uint32_t reg_slc0_len2_check:12;
};
uint32_t val;
} pkt_len2;
union {
struct {
uint32_t conf32: 8;
uint32_t conf33: 8;
uint32_t conf34: 8;
uint32_t conf35: 8;
};
uint32_t val;
} conf_w8;
union {
struct {
uint32_t conf36: 8;
uint32_t conf37: 8;
uint32_t conf38: 8;
uint32_t conf39: 8;
};
uint32_t val;
} conf_w9;
union {
struct {
uint32_t conf40: 8;
uint32_t conf41: 8;
uint32_t conf42: 8;
uint32_t conf43: 8;
};
uint32_t val;
} conf_w10;
union {
struct {
uint32_t conf44: 8;
uint32_t conf45: 8;
uint32_t conf46: 8;
uint32_t conf47: 8;
};
uint32_t val;
} conf_w11;
union {
struct {
uint32_t conf48: 8;
uint32_t conf49: 8;
uint32_t conf50: 8;
uint32_t conf51: 8;
};
uint32_t val;
} conf_w12;
union {
struct {
uint32_t conf52: 8;
uint32_t conf53: 8;
uint32_t conf54: 8;
uint32_t conf55: 8;
};
uint32_t val;
} conf_w13;
union {
struct {
uint32_t conf56: 8;
uint32_t conf57: 8;
uint32_t conf58: 8;
uint32_t conf59: 8;
};
uint32_t val;
} conf_w14;
union {
struct {
uint32_t conf60: 8;
uint32_t conf61: 8;
uint32_t conf62: 8;
uint32_t conf63: 8;
};
uint32_t val;
} conf_w15;
uint32_t check_sum0; /**/
uint32_t check_sum1; /**/
uint32_t reserved_c4;
union {
struct {
uint32_t token0_wd: 12;
uint32_t reserved12: 4;
uint32_t token1_wd: 12;
uint32_t reserved28: 4;
};
uint32_t val;
} slc0_token_wdata;
uint32_t reserved_cc;
union {
struct {
uint32_t slc0_token0_dec: 1;
uint32_t slc0_token1_dec: 1;
uint32_t slc0_token0_wr: 1;
uint32_t slc0_token1_wr: 1;
uint32_t reserved4: 4;
uint32_t slc0_len_wr: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} token_con;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_int_clr;
uint32_t reserved_d8;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_func1_int_ena;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_int_ena;
uint32_t reserved_f0;
union {
struct {
uint32_t infor: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} slc0_rx_infor;
uint32_t reserved_f8;
uint32_t slc0_len_wd; /**/
uint32_t apbwin_wdata; /**/
union {
struct {
uint32_t addr: 28;
uint32_t wr: 1;
uint32_t start: 1;
uint32_t bus: 1;
uint32_t reserved31: 1;
};
uint32_t val;
} apbwin_conf;
uint32_t apbwin_rdata; /**/
union {
struct {
uint32_t bit7_clraddr: 9;
uint32_t bit6_clraddr: 9;
uint32_t reserved18: 14;
};
uint32_t val;
} slc0_rdclr;
uint32_t reserved_110;
union {
struct {
uint32_t tohost_bit01: 1;
uint32_t tohost_bit11: 1;
uint32_t tohost_bit21: 1;
uint32_t tohost_bit31: 1;
uint32_t tohost_bit41: 1;
uint32_t tohost_bit51: 1;
uint32_t tohost_bit61: 1;
uint32_t tohost_bit71: 1;
uint32_t token0_1to01: 1;
uint32_t token1_1to01: 1;
uint32_t token0_0to11: 1;
uint32_t token1_0to11: 1;
uint32_t rx_sof1: 1;
uint32_t rx_eof1: 1;
uint32_t rx_start1: 1;
uint32_t tx_start1: 1;
uint32_t rx_udf1: 1;
uint32_t tx_ovf1: 1;
uint32_t rx_pf_valid1: 1;
uint32_t ext_bit01: 1;
uint32_t ext_bit11: 1;
uint32_t ext_bit21: 1;
uint32_t ext_bit31: 1;
uint32_t rx_new_packet1: 1;
uint32_t rd_retry1: 1;
uint32_t gpio_sdio1: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_int_ena1;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t date; /**/
uint32_t id; /**/
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
union {
struct {
uint32_t frc_sdio11: 5;
uint32_t frc_sdio20: 5;
uint32_t frc_neg_samp: 5;
uint32_t frc_pos_samp: 5;
uint32_t frc_quick_in: 5;
uint32_t sdio20_int_delay: 1;
uint32_t sdio_pad_pullup: 1;
uint32_t hspeed_con_en: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} conf;
union {
struct {
uint32_t sdio20_mode: 5;
uint32_t sdio_neg_samp: 5;
uint32_t sdio_quick_in: 5;
uint32_t reserved15: 17;
};
uint32_t val;
} inf_st;
} host_dev_t;
extern host_dev_t HOST;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_HOST_STRUCT_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/hwcrypto_reg.h
+223
View File
@@ -0,0 +1,223 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __HWCRYPTO_REG_H__
#define __HWCRYPTO_REG_H__
#include "soc.h"
/* registers for RSA acceleration via Multiple Precision Integer ops */
#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000)
/* RB & Z use the same memory block, depending on phase of operation */
#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400)
#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600)
/* Configuration registers */
#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800)
#define RSA_LENGTH_REG (DR_REG_RSA_BASE + 0x804)
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
#define RSA_SEARCH_OPEN_REG (DR_REG_RSA_BASE + 0x824)
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
/* Initialization registers */
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
/* Calculation start registers */
#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c)
#define RSA_MOD_MULT_START_REG (DR_REG_RSA_BASE + 0x810)
#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814)
/* Interrupt registers */
#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818)
#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C)
#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C)
#define SHA_MODE_SHA1 0
#define SHA_MODE_SHA224 1
#define SHA_MODE_SHA256 2
#define SHA_MODE_SHA384 3
#define SHA_MODE_SHA512 4
#define SHA_MODE_SHA512_224 5
#define SHA_MODE_SHA512_256 6
#define SHA_MODE_SHA512_T 7
/* SHA acceleration registers */
#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
#define SHA_T_STRING_REG ((DR_REG_SHA_BASE) + 0x04)
#define SHA_T_LENGTH_REG ((DR_REG_SHA_BASE) + 0x08)
#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C)
#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10)
#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14)
#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18)
#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C)
#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20)
#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24)
#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28)
#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40)
#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80)
/* AES acceleration registers */
#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
#define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
#define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
#define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC)
#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0)
#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4)
#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8)
#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00)
#define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20)
#define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30)
#define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50)
#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60)
#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70)
#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80)
#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC)
#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0)
#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4)
#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8)
/* AES_STATE_REG values */
#define AES_STATE_IDLE 0
#define AES_STATE_BUSY 1
#define AES_STATE_DONE 2
/* Crypto DMA */
#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00)
#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04)
#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08)
#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C)
#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10)
#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14)
#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18)
#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C)
#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20)
#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24)
#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28)
#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C)
#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30)
#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34)
#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38)
#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C)
#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40)
#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44)
#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48)
#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C)
#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50)
#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54)
#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58)
#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C)
#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60)
#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64)
#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC)
/* HMAC Module */
#define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40)
#define HMAC_SET_PARA_PURPOSE_REG ((DR_REG_HMAC_BASE) + 0x44)
#define HMAC_SET_PARA_KEY_REG ((DR_REG_HMAC_BASE) + 0x48)
#define HMAC_SET_PARA_FINISH_REG ((DR_REG_HMAC_BASE) + 0x4c)
#define HMAC_SET_MESSAGE_ONE_REG ((DR_REG_HMAC_BASE) + 0x50)
#define HMAC_SET_MESSAGE_ING_REG ((DR_REG_HMAC_BASE) + 0x54)
#define HMAC_SET_MESSAGE_END_REG ((DR_REG_HMAC_BASE) + 0x58)
#define HMAC_SET_RESULT_FINISH_REG ((DR_REG_HMAC_BASE) + 0x5c)
#define HMAC_SET_INVALIDATE_JTAG_REG ((DR_REG_HMAC_BASE) + 0x60)
#define HMAC_SET_INVALIDATE_DS_REG ((DR_REG_HMAC_BASE) + 0x64)
#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68)
#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c)
#define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80)
#define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0)
#define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0)
#define HMAC_ONE_BLOCK_REG ((DR_REG_HMAC_BASE) + 0xF4)
/* AES-XTS registers */
#define AES_XTS_PLAIN_BASE ((DR_REG_AES_BASE) + 0x100)
#define AES_XTS_SIZE_REG ((DR_REG_AES_BASE) + 0x140)
#define AES_XTS_DESTINATION_REG ((DR_REG_AES_BASE) + 0x144)
#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_BASE) + 0x148)
#define AES_XTS_TRIGGER_REG ((DR_REG_AES_BASE) + 0x14C)
#define AES_XTS_RELEASE_REG ((DR_REG_AES_BASE) + 0x150)
#define AES_XTS_DESTROY_REG ((DR_REG_AES_BASE) + 0x154)
#define AES_XTS_STATE_REG ((DR_REG_AES_BASE) + 0x158)
/* Digital Signature registers*/
#define DS_C_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
#define DS_IV_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 )
#define DS_X_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 )
#define DS_Z_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 )
#define DS_SET_START_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00)
#define DS_SET_ME_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04)
#define DS_SET_FINISH_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08)
#define DS_QUERY_BUSY_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C)
#define DS_QUERY_KEY_WRONG_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10)
#define DS_QUERY_CHECK_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14)
#define DS_QUERY_CHECK_INVALID_DIGEST (1<<0)
#define DS_QUERY_CHECK_INVALID_PADDING (1<<1)
#define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20)
/* Crypto DMA */
#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00)
#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04)
#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08)
#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C)
#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10)
#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14)
#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18)
#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C)
#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20)
#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24)
#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28)
#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C)
#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30)
#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34)
#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38)
#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C)
#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40)
#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44)
#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48)
#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C)
#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50)
#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54)
#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58)
#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C)
#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60)
#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64)
#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC)
#endif
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/i2c_caps.h
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// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-S2 have 2 I2C.
#define SOC_I2C_NUM (2)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define I2C_INTR_MASK (0x1ffff) /*!< I2C all interrupt bitmap */
//ESP32-S2 support hardware FSM reset
#define I2C_SUPPORT_HW_FSM_RST (1)
//ESP32-S2 support hardware clear bus
#define I2C_SUPPORT_HW_CLR_BUS (1)
#ifdef __cplusplus
}
#endif
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/i2c_reg.h
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tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/i2c_struct.h
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_I2C_STRUCT_H_
#define _SOC_I2C_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t period: 14;
uint32_t reserved14: 18;
};
uint32_t val;
} scl_low_period;
union {
struct {
uint32_t sda_force_out: 1;
uint32_t scl_force_out: 1;
uint32_t sample_scl_level: 1;
uint32_t rx_full_ack_level: 1;
uint32_t ms_mode: 1;
uint32_t trans_start: 1;
uint32_t tx_lsb_first: 1;
uint32_t rx_lsb_first: 1;
uint32_t clk_en: 1;
uint32_t arbitration_en: 1;
uint32_t fsm_rst: 1;
uint32_t ref_always_on: 1;
uint32_t reserved12: 20;
};
uint32_t val;
} ctr;
union {
struct {
uint32_t resp_rec: 1;
uint32_t slave_rw: 1;
uint32_t time_out: 1;
uint32_t arb_lost: 1;
uint32_t bus_busy: 1;
uint32_t slave_addressed: 1;
uint32_t byte_trans: 1;
uint32_t reserved7: 1;
uint32_t rx_fifo_cnt: 6;
uint32_t stretch_cause: 2;
uint32_t reserved16: 2;
uint32_t tx_fifo_cnt: 6;
uint32_t scl_main_state_last: 3;
uint32_t reserved27: 1;
uint32_t scl_state_last: 3;
uint32_t reserved31: 1;
};
uint32_t val;
} status_reg;
union {
struct {
uint32_t tout: 24;
uint32_t time_out_en: 1;
uint32_t reserved25: 7;
};
uint32_t val;
} timeout;
union {
struct {
uint32_t addr: 15;
uint32_t reserved15: 16;
uint32_t en_10bit: 1;
};
uint32_t val;
} slave_addr;
union {
struct {
uint32_t rx_fifo_start_addr: 5;
uint32_t rx_fifo_end_addr: 5;
uint32_t tx_fifo_start_addr: 5;
uint32_t tx_fifo_end_addr: 5;
uint32_t rx_update: 1;
uint32_t tx_update: 1;
uint32_t slave_rw_point: 8;
uint32_t reserved30: 2;
};
uint32_t val;
} fifo_st;
union {
struct {
uint32_t rx_fifo_wm_thrhd: 5;
uint32_t tx_fifo_wm_thrhd: 5;
uint32_t nonfifo_en: 1;
uint32_t fifo_addr_cfg_en: 1;
uint32_t rx_fifo_rst: 1;
uint32_t tx_fifo_rst: 1;
uint32_t nonfifo_rx_thres: 6;
uint32_t nonfifo_tx_thres: 6;
uint32_t fifo_prt_en: 1;
uint32_t reserved27: 5;
};
uint32_t val;
} fifo_conf;
union {
struct {
uint32_t data;
};
uint32_t val;
} fifo_data;
union {
struct {
uint32_t rx_fifo_wm: 1;
uint32_t tx_fifo_wm: 1;
uint32_t rx_fifo_ovf: 1;
uint32_t end_detect: 1;
uint32_t byte_trans_done: 1;
uint32_t arbitration_lost: 1;
uint32_t mst_tx_fifo_udf: 1;
uint32_t trans_complete: 1;
uint32_t time_out: 1;
uint32_t trans_start: 1;
uint32_t nack: 1;
uint32_t tx_fifo_ovf: 1;
uint32_t rx_fifo_udf: 1;
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t slave_stretch: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_fifo_wm: 1;
uint32_t tx_fifo_wm: 1;
uint32_t rx_fifo_ovf: 1;
uint32_t end_detect: 1;
uint32_t byte_trans_done: 1;
uint32_t arbitration_lost: 1;
uint32_t mst_tx_fifo_udf: 1;
uint32_t trans_complete: 1;
uint32_t time_out: 1;
uint32_t trans_start: 1;
uint32_t nack: 1;
uint32_t tx_fifo_ovf: 1;
uint32_t rx_fifo_udf: 1;
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t slave_stretch: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t rx_fifo_wm: 1;
uint32_t tx_fifo_wm: 1;
uint32_t rx_fifo_ovf: 1;
uint32_t end_detect: 1;
uint32_t byte_trans_done: 1;
uint32_t arbitration_lost: 1;
uint32_t mst_tx_fifo_udf: 1;
uint32_t trans_complete: 1;
uint32_t time_out: 1;
uint32_t trans_start: 1;
uint32_t nack: 1;
uint32_t tx_fifo_ovf: 1;
uint32_t rx_fifo_udf: 1;
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t slave_stretch: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rx_fifo_wm: 1;
uint32_t tx_fifo_wm: 1;
uint32_t rx_fifo_ovf: 1;
uint32_t end_detect: 1;
uint32_t byte_trans_done: 1;
uint32_t arbitration_lost: 1;
uint32_t mst_tx_fifo_udf: 1;
uint32_t trans_complete: 1;
uint32_t time_out: 1;
uint32_t trans_start: 1;
uint32_t nack: 1;
uint32_t tx_fifo_ovf: 1;
uint32_t rx_fifo_udf: 1;
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t slave_stretch: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_status;
union {
struct {
uint32_t time: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} sda_hold;
union {
struct {
uint32_t time: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} sda_sample;
union {
struct {
uint32_t period: 14;
uint32_t scl_wait_high_period:14;
uint32_t reserved28: 4;
};
uint32_t val;
} scl_high_period;
uint32_t reserved_3c;
union {
struct {
uint32_t time: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} scl_start_hold;
union {
struct {
uint32_t time: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} scl_rstart_setup;
union {
struct {
uint32_t time: 14;
uint32_t reserved14: 18;
};
uint32_t val;
} scl_stop_hold;
union {
struct {
uint32_t time: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} scl_stop_setup;
union {
struct {
uint32_t thres: 4;
uint32_t en: 1;
uint32_t reserved5: 27;
};
uint32_t val;
} scl_filter_cfg;
union {
struct {
uint32_t thres: 4;
uint32_t en: 1;
uint32_t reserved5: 27;
};
uint32_t val;
} sda_filter_cfg;
union {
struct {
uint32_t byte_num: 8;
uint32_t ack_en: 1;
uint32_t ack_exp: 1;
uint32_t ack_val: 1;
uint32_t op_code: 3;
uint32_t reserved14: 17;
uint32_t done: 1;
};
uint32_t val;
} command[16];
union {
struct {
uint32_t scl_st_to: 24;
uint32_t reserved24: 8;
};
uint32_t val;
} scl_st_time_out;
union {
struct {
uint32_t scl_main_st_to:24;
uint32_t reserved24: 8;
};
uint32_t val;
} scl_main_st_time_out;
union {
struct {
uint32_t scl_rst_slv_en: 1;
uint32_t scl_rst_slv_num: 5;
uint32_t scl_pd_en: 1;
uint32_t sda_pd_en: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} scl_sp_conf;
union {
struct {
uint32_t stretch_protect_num: 10;
uint32_t slave_scl_stretch_en: 1;
uint32_t slave_scl_stretch_clr: 1;
uint32_t reserved12: 20;
};
uint32_t val;
} scl_stretch_conf;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t date; /**/
uint32_t reserved_fc;
uint32_t txfifo_start_addr; /**/
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t fifo_start_addr; /**/
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_I2C_STRUCT_H_ */
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/i2s_caps.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define APLL_MIN_FREQ (250000000)
#define APLL_MAX_FREQ (500000000)
#define APLL_I2S_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define I2S_AD_BCK_FACTOR (2)
#define I2S_PDM_BCK_FACTOR (64)
#define I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define I2S_BASE_CLK (2*APB_CLK_FREQ)
// ESP32-S2 have 2 I2S
#define SOC_I2S_NUM (1)
#define SOC_I2S_SUPPORTS_PDM (0) // ESP32-S2 don't support PDM
#define SOC_I2S_SUPPORTS_DMA_EQUAL (1) // ESP32-S2 need dma equal
#define SOC_I2S_SUPPORTS_ADC_DAC (0) // ESP32-S2 don't support ADC and DAC

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