Update IDF to 65acd99 (#358)

* Update IDF to 65acd99

* Update platformio and arduino build paths and libs

* Update esptool binaries

tools/sdk/include/ethernet/esp_eth.h

@@ -15,6 +15,7 @@
 #ifndef __ESP_ETH_H__
 #define __ESP_ETH_H__
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "esp_err.h"
 
@@ -24,7 +25,7 @@ extern "C" {
 
 typedef enum {
     ETH_MODE_RMII = 0,
-    ETH_MDOE_MII,
+    ETH_MODE_MII,
 } eth_mode_t;
 
 typedef enum {
@@ -34,7 +35,7 @@ typedef enum {
 
 typedef enum {
     ETH_MODE_HALFDUPLEX = 0,
-    ETH_MDOE_FULLDUPLEX,
+    ETH_MODE_FULLDUPLEX,
 } eth_duplex_mode_t;
 
 typedef enum {
@@ -99,9 +100,10 @@ typedef struct {
     bool flow_ctrl_enable;                      /*!< flag of flow ctrl enable */
     eth_phy_get_partner_pause_enable_func  phy_get_partner_pause_enable; /*!< get partner pause enable */
     eth_phy_power_enable_func  phy_power_enable;  /*!< enable or disable phy power */
-    
+
 } eth_config_t;
 
+
 /**
  * @brief  Init ethernet mac
  *
@@ -173,7 +175,7 @@ void esp_eth_get_mac(uint8_t mac[6]);
 void esp_eth_smi_write(uint32_t reg_num, uint16_t value);
 
 /**
- * @brief  Write phy reg with smi interface.
+ * @brief  Read phy reg with smi interface.
  *
  * @note  phy base addr must be right.
  *
@@ -183,6 +185,35 @@ void esp_eth_smi_write(uint32_t reg_num, uint16_t value);
  */
 uint16_t esp_eth_smi_read(uint32_t reg_num);
 
+/**
+ * @brief Continuously read a PHY register over SMI interface, wait until the register has the desired value.
+ *
+ * @note PHY base address must be right.
+ *
+ * @param reg_num: PHY register number
+ * @param value: Value to wait for (masked with value_mask)
+ * @param value_mask: Mask of bits to match in the register.
+ * @param timeout_ms: Timeout to wait for this value (milliseconds). 0 means never timeout.
+ *
+ * @return ESP_OK if desired value matches, ESP_ERR_TIMEOUT if timed out.
+ */
+esp_err_t esp_eth_smi_wait_value(uint32_t reg_num, uint16_t value, uint16_t value_mask, int timeout_ms);
+
+/**
+ * @brief Continuously read a PHY register over SMI interface, wait until the register has all bits in a mask set.
+ *
+ * @note PHY base address must be right.
+ *
+ * @param reg_num: PHY register number
+ * @param value_mask: Value mask to wait for (all bits in this mask must be set)
+ * @param timeout_ms: Timeout to wait for this value (milliseconds). 0 means never timeout.
+ *
+ * @return ESP_OK if desired value matches, ESP_ERR_TIMEOUT if timed out.
+ */
+static inline esp_err_t esp_eth_smi_wait_set(uint32_t reg_num, uint16_t value_mask, int timeout_ms) {
+    return esp_eth_smi_wait_value(reg_num, value_mask, value_mask, timeout_ms);
+}
+
 /**
  * @brief  Free emac rx buf.
  *

tools/sdk/include/ethernet/eth_phy/phy.h

@@ -0,0 +1,59 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "esp_eth.h"
+
+/* Common PHY-management functions.
+
+   These are not enough to drive any particular Ethernet PHY, but they provide a common configuration structure and
+   management functions.
+*/
+
+/* Configure fixed pins for RMII data interface.
+
+   This configures GPIOs 0, 19, 22, 25, 26, 27 for use with RMII
+   data interface. These pins cannot be changed, and must be wired to
+   ethernet functions.
+
+   This is not sufficient to fully configure the Ethernet PHY,
+   MDIO configuration interface pins (such as SMI MDC, MDO, MDI)
+   must also be configured correctly in the GPIO matrix.
+*/
+void phy_rmii_configure_data_interface_pins(void);
+
+/* Configure variable pins for SMI (MDIO) ethernet functions.
+
+   Calling this function along with mii_configure_default_pins() will
+   fully configure the GPIOs for the ethernet PHY.
+ */
+void phy_rmii_smi_configure_pins(uint8_t mdc_gpio, uint8_t mdio_gpio);
+
+
+/* Enable flow control in standard PHY MII register.
+ */
+void phy_mii_enable_flow_ctrl(void);
+
+bool phy_mii_check_link_status(void);
+
+bool phy_mii_get_partner_pause_enable(void);
+
+#ifdef __cplusplus
+}
+#endif

tools/sdk/include/ethernet/eth_phy/phy_lan8720.h

@@ -0,0 +1,67 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "phy.h"
+
+
+/* @brief Dump all LAN8720 PHY SMI configuration registers
+ *
+ * @note These registers are dumped at 'debug' level, so output
+ * may not be visible depending on default log levels.
+ */
+void phy_lan8720_dump_registers();
+
+/* @brief Default LAN8720 phy_check_init function.
+ */
+void phy_lan8720_check_phy_init(void);
+
+/* @brief Default LAN8720 phy_get_speed_mode function.
+ */
+eth_speed_mode_t phy_lan8720_get_speed_mode(void);
+
+/* @brief Default LAN8720 phy_get_duplex_mode function.
+ */
+eth_duplex_mode_t phy_lan8720_get_duplex_mode(void);
+
+/* @brief Default LAN8720 phy_power_enable function.
+ *
+ * @note This function may need to be replaced with a custom function
+ * if the PHY has a GPIO to enable power or start a clock.
+ *
+ * Consult the ethernet example to see how this is done.
+ */
+void phy_lan8720_power_enable(bool);
+
+/* @brief Default LAN8720 phy_init function.
+ */
+void phy_lan8720_init(void);
+
+/* @brief Default LAN8720 PHY configuration
+ *
+ * This configuration is not suitable for use as-is, it will need
+ * to be modified for your particular PHY hardware setup.
+ *
+ * Consult the Ethernet example to see how this is done.
+ */
+extern const eth_config_t phy_lan8720_default_ethernet_config;
+
+#ifdef __cplusplus
+}
+#endif

tools/sdk/include/ethernet/eth_phy/phy_reg.h

@@ -0,0 +1,37 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/* This header contains register/bit masks for the standard
+   PHY MII registers that should be supported by all PHY models.
+*/
+
+#define MII_BASIC_MODE_CONTROL_REG          (0x0)
+#define MII_SOFTWARE_RESET                     BIT(15)
+
+#define MII_BASIC_MODE_STATUS_REG           (0x1)
+#define MII_AUTO_NEGOTIATION_COMPLETE          BIT(5)
+#define MII_LINK_STATUS                        BIT(2)
+
+#define MII_PHY_IDENTIFIER_1_REG              (0x2)
+#define MII_PHY_IDENTIFIER_2_REG              (0x3)
+
+#define MII_AUTO_NEG_ADVERTISEMENT_REG      (0x4)
+#define MII_ASM_DIR                            BIT(11)
+#define MII_PAUSE                              BIT(10)
+
+#define MII_PHY_LINK_PARTNER_ABILITY_REG    (0x5)
+#define MII_PARTNER_ASM_DIR                    BIT(11)
+#define MII_PARTNER_PAUSE                      BIT(10)

tools/sdk/include/ethernet/eth_phy/phy_tlk110.h

@@ -0,0 +1,66 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "phy.h"
+
+/* @brief Dump all TLK110 PHY SMI configuration registers
+ *
+ * @note These registers are dumped at 'debug' level, so output
+ * may not be visible depending on default log levels.
+ */
+void phy_tlk110_dump_registers();
+
+/* @brief Default TLK110 phy_check_init function.
+ */
+void phy_tlk110_check_phy_init(void);
+
+/* @brief Default TLK110 phy_get_speed_mode function.
+ */
+eth_speed_mode_t phy_tlk110_get_speed_mode(void);
+
+/* @brief Default TLK110 phy_get_duplex_mode function.
+ */
+eth_duplex_mode_t phy_tlk110_get_duplex_mode(void);
+
+/* @brief Default TLK110 phy_power_enable function.
+ *
+ * @note This function may need to be replaced with a custom function
+ * if the PHY has a GPIO to enable power or start a clock.
+ *
+ * Consult the ethernet example to see how this is done.
+ */
+void phy_tlk110_power_enable(bool);
+
+/* @brief Default TLK110 phy_init function.
+ */
+void phy_tlk110_init(void);
+
+/* @brief Default TLK110 PHY configuration
+ *
+ * This configuration is not suitable for use as-is, it will need
+ * to be modified for your particular PHY hardware setup.
+ *
+ * Consult the Ethernet example to see how this is done.
+ */
+extern const eth_config_t phy_tlk110_default_ethernet_config;
+
+#ifdef __cplusplus
+}
+#endif