mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
synced 2025-07-01 04:50:58 +02:00
Update IDF to 65acd99 (#358)
* Update IDF to 65acd99 * Update platformio and arduino build paths and libs * Update esptool binaries
This commit is contained in:
Me No Dev
GitHub
@ -21,12 +21,20 @@
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#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
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#define BB_FFT_FORCE_PU (BIT(3))
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#define BB_FFT_FORCE_PU_M (BIT(3))
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#define BB_FFT_FORCE_PU_V 1
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#define BB_FFT_FORCE_PU_S 3
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#define BB_FFT_FORCE_PD (BIT(2))
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#define BB_FFT_FORCE_PD_M (BIT(2))
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#define BB_FFT_FORCE_PD_V 1
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#define BB_FFT_FORCE_PD_S 2
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#define BB_DC_EST_FORCE_PU (BIT(1))
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#define BB_DC_EST_FORCE_PU_M (BIT(1))
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#define BB_DC_EST_FORCE_PU_V 1
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#define BB_DC_EST_FORCE_PU_S 1
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#define BB_DC_EST_FORCE_PD (BIT(0))
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#define BB_DC_EST_FORCE_PD_M (BIT(0))
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#define BB_DC_EST_FORCE_PD_V 1
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#define BB_DC_EST_FORCE_PD_S 0
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@ -73,15 +73,6 @@ static inline void cpu_configure_region_protection()
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cpu_write_itlb(0x20000000, 0);
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}
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/**
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* @brief Set CPU frequency to the value defined in menuconfig
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*
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* Called from cpu_start.c, not intended to be called from other places.
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* This is a temporary function which will be replaced once dynamic
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* CPU frequency changing is implemented.
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*/
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void esp_set_cpu_freq(void);
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/**
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* @brief Stall CPU using RTC controller
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* @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
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@ -2851,6 +2851,40 @@
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_M ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S))
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_V 0x3F
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9
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/* This is the contents of DPORT_PRO_CPU_DISABLED_CACHE_IA field expanded */
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/* The following bits will be set upon invalid access for different memory
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* regions: */
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/* Port of the APP CPU cache when cache is used in high/low or odd/even mode */
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE BIT(9)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9
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/* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 BIT(10)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_M BIT(10)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_V 1
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_S 10
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/* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0 BIT(11)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_M BIT(11)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_V 1
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_S 11
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/* IRAM1: 0x4040_0000 ~ 0x407F_FFFF(RO) */
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1 BIT(12)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_M BIT(12)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_V 1
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_S 12
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/* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0 BIT(13)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_M BIT(13)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_V 1
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_S 13
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/* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 BIT(14)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_M BIT(14)
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_V 1
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#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_S 14
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/* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */
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/*description: */
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#define DPORT_PRO_MMU_RDATA 0x000001FF
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@ -2985,6 +3019,40 @@
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_M ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S))
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_V 0x3F
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9
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/* This is the contents of DPORT_APP_CPU_DISABLED_CACHE_IA field expanded */
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/* The following bits will be set upon invalid access for different memory
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* regions: */
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/* Port of the PRO CPU cache when cache is used in high/low or odd/even mode */
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE BIT(9)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9
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/* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 BIT(10)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_M BIT(10)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_V 1
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_S 10
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/* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0 BIT(11)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_M BIT(11)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_V 1
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_S 11
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/* IRAM1: 0x4040_0000 ~ 0x407F_FFFF(RO) */
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1 BIT(12)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_M BIT(12)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_V 1
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_S 12
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/* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0 BIT(13)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_M BIT(13)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_V 1
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_S 13
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/* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0 BIT(14)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_M BIT(14)
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_V 1
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#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_S 14
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/* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */
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/*description: */
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#define DPORT_APP_MMU_RDATA 0x000001FF
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@ -3083,6 +3151,32 @@
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#define DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S))
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#define DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF
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#define DPORT_RECORD_PRO_PDEBUGINST_S 0
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/* register layout:
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* SIZE [7..0] : Instructions normally complete in the W stage. The size of the instruction in the W is given
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* by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing
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* instruction. This is also known as a bubble cycle. Also see DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG.
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* ISRC [14..12] : Instruction source.
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** LOOP [23..20] : Loopback status.
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** CINTLEVEL [27..24]: CINTLEVEL.
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*/
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#define DPORT_RECORD_PDEBUGINST_SZ_M ((DPORT_RECORD_PDEBUGINST_SZ_V)<<(DPORT_RECORD_PDEBUGINST_SZ_S))
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#define DPORT_RECORD_PDEBUGINST_SZ_V 0xFF
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#define DPORT_RECORD_PDEBUGINST_SZ_S 0
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#define DPORT_RECORD_PDEBUGINST_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V)
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#define DPORT_RECORD_PDEBUGINST_ISRC_M ((DPORT_RECORD_PDEBUGINST_ISRC_V)<<(DPORT_RECORD_PDEBUGINST_ISRC_S))
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#define DPORT_RECORD_PDEBUGINST_ISRC_V 0x07
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#define DPORT_RECORD_PDEBUGINST_ISRC_S 12
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#define DPORT_RECORD_PDEBUGINST_ISRC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_ISRC_S) & DPORT_RECORD_PDEBUGINST_ISRC_V)
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// #define DPORT_RECORD_PDEBUGINST_LOOP_M ((DPORT_RECORD_PDEBUGINST_LOOP_V)<<(DPORT_RECORD_PDEBUGINST_LOOP_S))
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// #define DPORT_RECORD_PDEBUGINST_LOOP_V 0x0F
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// #define DPORT_RECORD_PDEBUGINST_LOOP_S 20
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// #define DPORT_RECORD_PDEBUGINST_LOOP(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_LOOP_S) & DPORT_RECORD_PDEBUGINST_LOOP_V)
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#define DPORT_RECORD_PDEBUGINST_LOOP_REP (BIT(20)) /* loopback will occur */
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#define DPORT_RECORD_PDEBUGINST_LOOP (BIT(21)) /* last inst of loop */
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#define DPORT_RECORD_PDEBUGINST_CINTL_M ((DPORT_RECORD_PDEBUGINST_CINTL_V)<<(DPORT_RECORD_PDEBUGINST_CINTL_S))
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#define DPORT_RECORD_PDEBUGINST_CINTL_V 0x0F
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#define DPORT_RECORD_PDEBUGINST_CINTL_S 24
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#define DPORT_RECORD_PDEBUGINST_CINTL(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V)
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#define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450)
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/* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
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@ -3091,6 +3185,52 @@
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#define DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S))
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#define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF
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#define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0
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/* register layout:
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* BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
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* INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
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*/
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V 0x3F
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S 0
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S) & DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO 0x00 /* Power shut off */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP 0x02 /* Register dependency or resource conflict. See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL 0x04 /* Control transfer bubble */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM 0x08 /* I-cache miss (incl uncached miss) */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM 0x0C /* D-cache miss (excl uncached miss) */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0 0x10 /* Exception or interrupt (W stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info.
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The virtual address of the instruction that was killed appears on DPORT_PRO_CPU_RECORD_PDEBUGPC_REG[31:0] */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1 0x11 /* Exception or interrupt (W+1 stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL 0x14 /* Instruction replay (other). DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG has the PC of the replaying instruction. */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB 0x18 /* HW ITLB refill. The refill address and data are available on
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DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM 0x1A /* ITLB miss */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB 0x1C /* HW DTLB refill. The refill address and data are available on
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DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM 0x1E /* DTLB miss */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL 0x20 /* Stall . The cause of the global stall is further classified in the DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG. */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC 0x24 /* HW-corrected memory error */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI 0x28 /* WAITI mode */
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#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER 0x3C /* all other bubbles */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_M ((DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)<<(DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S))
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V 0x3F
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S 0
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S) & DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX 0x00 /* JX */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX 0x04 /* CALLX */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET 0x08 /* All call returns */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET 0x0C /* All exception returns */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B 0x10 /* Branch taken or loop not taken */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J 0x14 /* J */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL 0x18 /* CALL */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN 0x1C /* Branch not taken */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP 0x20 /* Loop instruction (taken) */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I 0x24 /* S32C1I. The address and load data (before the conditional store) are available on the LS signals*/
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB 0x28 /* WSR/XSR to LBEGIN */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID 0x2C /* WSR to MMID */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR 0x30 /* RSR or WSR (except MMID and LBEGIN) or XSR (except LBEGIN) */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER 0x34 /* RER or WER */
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#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF 0x3C /* Default */
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#define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454)
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/* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
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@ -3099,6 +3239,115 @@
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#define DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S))
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#define DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF
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#define DPORT_RECORD_PRO_PDEBUGDATA_S 0
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/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP:
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*
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* HALT [17]: HALT instruction (TX only)
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* MEMW [16]: MEMW, EXTW or EXCW instruction dependency
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* REG [12]: register dependencies or resource (e.g.TIE ports) conflicts
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* STR [11]: store release (instruction) dependency
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* LSU [8] : various LSU dependencies (MHT access, prefetch, cache access insts, s32c1i, etc)
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* OTHER[0] : all other hold dependencies resulting from data or resource dependencies
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*/
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#define DPORT_RECORD_PDEBUGDATA_DEP_HALT (BIT(17))
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#define DPORT_RECORD_PDEBUGDATA_DEP_MEMW (BIT(16))
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#define DPORT_RECORD_PDEBUGDATA_DEP_REG (BIT(12))
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#define DPORT_RECORD_PDEBUGDATA_DEP_STR (BIT(11))
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#define DPORT_RECORD_PDEBUGDATA_DEP_LSU (BIT(8))
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#define DPORT_RECORD_PDEBUGDATA_DEP_OTHER (BIT(0))
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/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXCn:
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*
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* EXCCAUSE[21..16]: Processor exception cause
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* EXCVEC [4..0] : Encoded Exception Vector
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*/
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#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_M ((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S))
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#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V 0x3F
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#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S 16
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#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_M ((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S))
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_V 0x1F
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_S 0
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_NONE 0x00 /* no vector */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_RST 0x01 /* Reset */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBG 0x02 /* Debug (repl corresp level “n”) */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_NMI 0x03 /* NMI (repl corresp level “n”) */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_USR 0x04 /* User */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_KRNL 0x05 /* Kernel */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBL 0x06 /* Double */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_EMEM 0x07 /* Memory Error */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF4 0x0A /* Window Overflow 4 */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF4 0x0B /* Window Underflow 4 */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF8 0x0C /* Window Overflow 8 */
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#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF8 0x0D /* Window Underflow 8 */
|
||||
#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF12 0x0E /* Window Overflow 12 */
|
||||
#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF12 0x0F /* Window Underflow 12 */
|
||||
#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT2 0x10 /* Int Level 2 (n/a if debug/NMI) */
|
||||
#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT3 0x11 /* Int Level 3 (n/a if debug/NMI) */
|
||||
#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT4 0x12 /* Int Level 4 (n/a if debug/NMI) */
|
||||
#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT5 0x13 /* Int Level 5 (n/a if debug/NMI) */
|
||||
#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT6 0x14 /* Int Level 6 (n/a if debug/NMI) */
|
||||
/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL:
|
||||
*
|
||||
* ITERDIV[19] : Iterative divide stall.
|
||||
* ITERMUL[18] : Iterative multiply stall.
|
||||
* BANKCONFL[16]: Bank-conflict stall.
|
||||
* BPLOAD[15] : Bypass load stall.
|
||||
* LSPROC[14] : Load/store miss-processing stall.
|
||||
* L32R[13] : FastL32R stall.
|
||||
* BPIFETCH[12] : Bypass I fetch stall.
|
||||
* RUNSTALL[10] : RunStall.
|
||||
* TIE[9] : TIE port stall.
|
||||
* IPIF[8] : Instruction RAM inbound-PIF stall.
|
||||
* IRAMBUSY[7] : Instruction RAM/ROM busy stall.
|
||||
* ICM[6] : I-cache-miss stall.
|
||||
* LSU[4] : The LSU will stall the pipeline under various local memory access conflict situations.
|
||||
* DCM[3] : D-cache-miss stall.
|
||||
* BUFFCONFL[2] : Store buffer conflict stall.
|
||||
* BUFF[1] : Store buffer full stall.
|
||||
*/
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_ITERDIV (BIT(19))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_ITERMUL (BIT(18))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_BANKCONFL (BIT(16))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_BPLOAD (BIT(15))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_LSPROC (BIT(14))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_L32R (BIT(13))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_BPIFETCH (BIT(12))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_RUN (BIT(10))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_TIE (BIT(9))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_IPIF (BIT(8))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_IRAMBUSY (BIT(7))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_ICM (BIT(6))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_LSU (BIT(4))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_DCM (BIT(3))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_BUFFCONFL (BIT(2))
|
||||
#define DPORT_RECORD_PDEBUGDATA_STALL_BUFF (BIT(1))
|
||||
/* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR:
|
||||
*
|
||||
* XSR[10] : XSR Instruction
|
||||
* WSR[9] : WSR Instruction
|
||||
* RSR[8] : RSR Instruction
|
||||
* SR[7..0] : Special Register Number
|
||||
*/
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_XSR (BIT(10))
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WSR (BIT(9))
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RSR (BIT(8))
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_M ((DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S))
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V 0xFF
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S 0
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)
|
||||
/* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER:
|
||||
*
|
||||
* ER[13..2]: ER Address
|
||||
* WER[1] : WER Instruction
|
||||
* RER[0] : RER Instruction
|
||||
*/
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_M ((DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S))
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V 0xFFF
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S 2
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WER (BIT(1))
|
||||
#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RER (BIT(0))
|
||||
|
||||
|
||||
#define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458)
|
||||
/* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
@ -3115,6 +3364,68 @@
|
||||
#define DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S))
|
||||
#define DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF
|
||||
#define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0
|
||||
/* register layout:
|
||||
* TYPE [3..0] : Type of instruction in LS.
|
||||
* SZ [7..4] : Operand size.
|
||||
* DTLBM [8] : Data TLB miss.
|
||||
* DCM [9] : D-cache miss.
|
||||
* DCH [10] : D-cache hit.
|
||||
* UC [12] : Uncached.
|
||||
* WB [13] : Writeback.
|
||||
* COH [16] : Coherency.
|
||||
* STCOH [18..17]: Coherent state.
|
||||
* TGT [23..20] : Local target.
|
||||
*/
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_M ((DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TYPE_S))
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_V 0x0F
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S 0
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TYPE_S) & DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_NONE 0x00 /* neither */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_ITLBR 0x01 /* hw itlb refill */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_DTLBR 0x02 /* hw dtlb refill */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_LD 0x05 /* load */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_STR 0x06 /* store */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_L32R 0x08 /* l32r */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S32CLI1 0x0A /* s32ci1 */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_CTI 0x0C /* cache test inst */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWXSR 0x0E /* rsr/wsr/xsr */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWER 0x0F /* rer/wer */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_SZ_M ((DPORT_RECORD_PDEBUGLS0STAT_SZ_V)<<(DPORT_RECORD_PDEBUGLS0STAT_SZ_S))
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_SZ_V 0x0F
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_SZ_S 4
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_SZ_S) & DPORT_RECORD_PDEBUGLS0STAT_SZ_V)
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_SZB(_r_) ((8<<DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_))/8) // in bytes
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_DTLBM (BIT(8))
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_DCM (BIT(9))
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_DCH (BIT(10))
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_UC (BIT(12))
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_WB (BIT(13))
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_COH (BIT(16))
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_M ((DPORT_RECORD_PDEBUGLS0STAT_STCOH_V)<<(DPORT_RECORD_PDEBUGLS0STAT_STCOH_S))
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_V 0x03
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_S 17
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_STCOH(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_STCOH_S) & DPORT_RECORD_PDEBUGLS0STAT_STCOH_V)
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_NONE 0x0 /* neither shared nor exclusive nor modified */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_SHARED 0x1 /* shared */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_EXCL 0x2 /* exclusive */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_MOD 0x3 /* modified */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_M ((DPORT_RECORD_PDEBUGLS0STAT_TGT_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TGT_S))
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_V 0x0F
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_S 20
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TGT_S) & DPORT_RECORD_PDEBUGLS0STAT_TGT_V)
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_EXT 0x0 /* not to local memory */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM0 0x2 /* 001x: InstRAM (0/1) */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM1 0x3 /* 001x: InstRAM (0/1) */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM0 0x4 /* 010x: InstROM (0/1) */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM1 0x5 /* 010x: InstROM (0/1) */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM0 0x0A /* 101x: DataRAM (0/1) */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM1 0x0B /* 101x: DataRAM (0/1) */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM0 0xE /* 111x: DataROM (0/1) */
|
||||
#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM1 0xF /* 111x: DataROM (0/1) */
|
||||
// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM(_t_) (((_t_)&0xE)=0x2) /* 001x: InstRAM (0/1) */
|
||||
// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM(_t_) (((_t_)&0xE)=0x4) /* 010x: InstROM (0/1) */
|
||||
// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM(_t_) (((_t_)&0xE)=0x2) /* 101x: DataRAM (0/1) */
|
||||
// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM(_t_) (((_t_)&0xE)=0x2) /* 111x: DataROM (0/1) */
|
||||
|
||||
#define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460)
|
||||
/* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
@ -3788,11 +4099,84 @@
|
||||
|
||||
#define DPORT_CACHE_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x5A0)
|
||||
/* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
|
||||
/*description: */
|
||||
/*description: Interrupt enable bits for various invalid cache access reasons*/
|
||||
#define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF
|
||||
#define DPORT_CACHE_IA_INT_EN_M ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S))
|
||||
#define DPORT_CACHE_IA_INT_EN_V 0xFFFFFFF
|
||||
#define DPORT_CACHE_IA_INT_EN_S 0
|
||||
/* Contents of DPORT_CACHE_IA_INT_EN field: */
|
||||
/* DPORT_CACHE_IA_INT_PRO_OPPOSITE : R/W ;bitpos:[19] ;default: 1'b0 ; */
|
||||
/*description: PRO CPU invalid access to APP CPU cache when cache disabled */
|
||||
#define DPORT_CACHE_IA_INT_PRO_OPPOSITE BIT(19)
|
||||
#define DPORT_CACHE_IA_INT_PRO_OPPOSITE_M BIT(19)
|
||||
#define DPORT_CACHE_IA_INT_PRO_OPPOSITE_V (1)
|
||||
#define DPORT_CACHE_IA_INT_PRO_OPPOSITE_S (19)
|
||||
/* DPORT_CACHE_IA_INT_PRO_DRAM1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
|
||||
/*description: PRO CPU invalid access to DRAM1 when cache is disabled */
|
||||
#define DPORT_CACHE_IA_INT_PRO_DRAM1 BIT(18)
|
||||
#define DPORT_CACHE_IA_INT_PRO_DRAM1_M BIT(18)
|
||||
#define DPORT_CACHE_IA_INT_PRO_DRAM1_V (1)
|
||||
#define DPORT_CACHE_IA_INT_PRO_DRAM1_S (18)
|
||||
/* DPORT_CACHE_IA_INT_PRO_IROM0 : R/W ;bitpos:[17] ;default: 1'b0 ; */
|
||||
/*description: PRO CPU invalid access to IROM0 when cache is disabled */
|
||||
#define DPORT_CACHE_IA_INT_PRO_IROM0 BIT(17)
|
||||
#define DPORT_CACHE_IA_INT_PRO_IROM0_M BIT(17)
|
||||
#define DPORT_CACHE_IA_INT_PRO_IROM0_V (1)
|
||||
#define DPORT_CACHE_IA_INT_PRO_IROM0_S (17)
|
||||
/* DPORT_CACHE_IA_INT_PRO_IRAM1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
||||
/*description: PRO CPU invalid access to IRAM1 when cache is disabled */
|
||||
#define DPORT_CACHE_IA_INT_PRO_IRAM1 BIT(16)
|
||||
#define DPORT_CACHE_IA_INT_PRO_IRAM1_M BIT(16)
|
||||
#define DPORT_CACHE_IA_INT_PRO_IRAM1_V (1)
|
||||
#define DPORT_CACHE_IA_INT_PRO_IRAM1_S (16)
|
||||
/* DPORT_CACHE_IA_INT_PRO_IRAM0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: PRO CPU invalid access to IRAM0 when cache is disabled */
|
||||
#define DPORT_CACHE_IA_INT_PRO_IRAM0 BIT(15)
|
||||
#define DPORT_CACHE_IA_INT_PRO_IRAM0_M BIT(15)
|
||||
#define DPORT_CACHE_IA_INT_PRO_IRAM0_V (1)
|
||||
#define DPORT_CACHE_IA_INT_PRO_IRAM0_S (15)
|
||||
/* DPORT_CACHE_IA_INT_PRO_DROM0 : R/W ;bitpos:[14] ;default: 1'b0 ; */
|
||||
/*description: PRO CPU invalid access to DROM0 when cache is disabled */
|
||||
#define DPORT_CACHE_IA_INT_PRO_DROM0 BIT(14)
|
||||
#define DPORT_CACHE_IA_INT_PRO_DROM0_M BIT(14)
|
||||
#define DPORT_CACHE_IA_INT_PRO_DROM0_V (1)
|
||||
#define DPORT_CACHE_IA_INT_PRO_DROM0_S (14)
|
||||
/* DPORT_CACHE_IA_INT_APP_OPPOSITE : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: APP CPU invalid access to APP CPU cache when cache disabled */
|
||||
#define DPORT_CACHE_IA_INT_APP_OPPOSITE BIT(5)
|
||||
#define DPORT_CACHE_IA_INT_APP_OPPOSITE_M BIT(5)
|
||||
#define DPORT_CACHE_IA_INT_APP_OPPOSITE_V (1)
|
||||
#define DPORT_CACHE_IA_INT_APP_OPPOSITE_S (5)
|
||||
/* DPORT_CACHE_IA_INT_APP_DRAM1 : R/W ;bitpos:43] ;default: 1'b0 ; */
|
||||
/*description: APP CPU invalid access to DRAM1 when cache is disabled */
|
||||
#define DPORT_CACHE_IA_INT_APP_DRAM1 BIT(4)
|
||||
#define DPORT_CACHE_IA_INT_APP_DRAM1_M BIT(4)
|
||||
#define DPORT_CACHE_IA_INT_APP_DRAM1_V (1)
|
||||
#define DPORT_CACHE_IA_INT_APP_DRAM1_S (4)
|
||||
/* DPORT_CACHE_IA_INT_APP_IROM0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: APP CPU invalid access to IROM0 when cache is disabled */
|
||||
#define DPORT_CACHE_IA_INT_APP_IROM0 BIT(3)
|
||||
#define DPORT_CACHE_IA_INT_APP_IROM0_M BIT(3)
|
||||
#define DPORT_CACHE_IA_INT_APP_IROM0_V (1)
|
||||
#define DPORT_CACHE_IA_INT_APP_IROM0_S (3)
|
||||
/* DPORT_CACHE_IA_INT_APP_IRAM1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: APP CPU invalid access to IRAM1 when cache is disabled */
|
||||
#define DPORT_CACHE_IA_INT_APP_IRAM1 BIT(2)
|
||||
#define DPORT_CACHE_IA_INT_APP_IRAM1_M BIT(2)
|
||||
#define DPORT_CACHE_IA_INT_APP_IRAM1_V (1)
|
||||
#define DPORT_CACHE_IA_INT_APP_IRAM1_S (2)
|
||||
/* DPORT_CACHE_IA_INT_APP_IRAM0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: APP CPU invalid access to IRAM0 when cache is disabled */
|
||||
#define DPORT_CACHE_IA_INT_APP_IRAM0 BIT(1)
|
||||
#define DPORT_CACHE_IA_INT_APP_IRAM0_M BIT(1)
|
||||
#define DPORT_CACHE_IA_INT_APP_IRAM0_V (1)
|
||||
#define DPORT_CACHE_IA_INT_APP_IRAM0_S (1)
|
||||
/* DPORT_CACHE_IA_INT_APP_DROM0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: APP CPU invalid access to DROM0 when cache is disabled */
|
||||
#define DPORT_CACHE_IA_INT_APP_DROM0 BIT(0)
|
||||
#define DPORT_CACHE_IA_INT_APP_DROM0_M BIT(0)
|
||||
#define DPORT_CACHE_IA_INT_APP_DROM0_V (1)
|
||||
#define DPORT_CACHE_IA_INT_APP_DROM0_S (0)
|
||||
|
||||
#define DPORT_SECURE_BOOT_CTRL_REG (DR_REG_DPORT_BASE + 0x5A4)
|
||||
/* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
|
||||
@ -23,75 +23,135 @@ extern "C" {
|
||||
|
||||
#define EMAC_EX_CLKOUT_CONF_REG (REG_EMAC_EX_BASE + 0x0000)
|
||||
#define EMAC_EX_CLK_OUT_DLY_NUM 0x00000003
|
||||
#define EMAC_EX_CLK_OUT_DLY_NUM_M (EMAC_EX_CLK_OUT_DLY_NUM_V << EMAC_EX_CLK_OUT_DLY_NUM_S)
|
||||
#define EMAC_EX_CLK_OUT_DLY_NUM_V 0x00000003
|
||||
#define EMAC_EX_CLK_OUT_DLY_NUM_S 8
|
||||
#define EMAC_EX_CLK_OUT_H_DIV_NUM 0x0000000F
|
||||
#define EMAC_EX_CLK_OUT_H_DIV_NUM_M (EMAC_EX_CLK_OUT_H_DIV_NUM_V << EMAC_EX_CLK_OUT_H_DIV_NUM_S)
|
||||
#define EMAC_EX_CLK_OUT_H_DIV_NUM_V 0x0000000F
|
||||
#define EMAC_EX_CLK_OUT_H_DIV_NUM_S 4
|
||||
#define EMAC_EX_CLK_OUT_DIV_NUM 0x0000000F
|
||||
#define EMAC_EX_CLK_OUT_DIV_NUM_M (EMAC_EX_CLK_OUT_DIV_NUM_V << EMAC_EX_CLK_OUT_DIV_NUM_S)
|
||||
#define EMAC_EX_CLK_OUT_DIV_NUM_V 0x0000000F
|
||||
#define EMAC_EX_CLK_OUT_DIV_NUM_S 0
|
||||
|
||||
#define EMAC_EX_OSCCLK_CONF_REG (REG_EMAC_EX_BASE + 0x0004)
|
||||
#define EMAC_EX_OSC_CLK_SEL (BIT(24))
|
||||
#define EMAC_EX_OSC_CLK_SEL_M (BIT(24))
|
||||
#define EMAC_EX_OSC_CLK_SEL_V 1
|
||||
#define EMAC_EX_OSC_CLK_SEL_S 24
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_100M 0x0000003F
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_100M_M (EMAC_EX_OSC_H_DIV_NUM_100M_V << EMAC_EX_OSC_H_DIV_NUM_100M_S)
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_100M_V 0x0000003F
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_100M_S 18
|
||||
#define EMAC_EX_OSC_DIV_NUM_100M 0x0000003F
|
||||
#define EMAC_EX_OSC_DIV_NUM_100M_M (EMAC_EX_OSC_DIV_NUM_100M_V << EMAC_EX_OSC_DIV_NUM_100M_S)
|
||||
#define EMAC_EX_OSC_DIV_NUM_100M_V 0x0000003F
|
||||
#define EMAC_EX_OSC_DIV_NUM_100M_S 12
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_10M 0x0000003F
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_10M_M (EMAC_EX_OSC_H_DIV_NUM_10M_V << EMAC_EX_OSC_H_DIV_NUM_10M_S)
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_10M_V 0x0000003F
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_10M_S 6
|
||||
#define EMAC_EX_OSC_DIV_NUM_10M 0x0000003F
|
||||
#define EMAC_EX_OSC_DIV_NUM_10M_M (EMAC_EX_OSC_DIV_NUM_10M_V << EMAC_EX_OSC_DIV_NUM_10M_S)
|
||||
#define EMAC_EX_OSC_DIV_NUM_10M_V 0x0000003F
|
||||
#define EMAC_EX_OSC_DIV_NUM_10M_S 0
|
||||
|
||||
#define EMAC_EX_CLK_CTRL_REG (REG_EMAC_EX_BASE + 0x0008)
|
||||
#define EMAC_EX_CLK_EN (BIT(5))
|
||||
#define EMAC_EX_CLK_EN_M (BIT(5))
|
||||
#define EMAC_EX_CLK_EN_V 1
|
||||
#define EMAC_EX_CLK_EN_S 5
|
||||
#define EMAC_EX_MII_CLK_RX_EN (BIT(4))
|
||||
#define EMAC_EX_MII_CLK_RX_EN_M (BIT(4))
|
||||
#define EMAC_EX_MII_CLK_RX_EN_V 1
|
||||
#define EMAC_EX_MII_CLK_RX_EN_S 4
|
||||
#define EMAC_EX_MII_CLK_TX_EN (BIT(3))
|
||||
#define EMAC_EX_MII_CLK_TX_EN_M (BIT(3))
|
||||
#define EMAC_EX_MII_CLK_TX_EN_V 1
|
||||
#define EMAC_EX_MII_CLK_TX_EN_S 3
|
||||
#define EMAC_EX_RX_125_CLK_EN (BIT(2))
|
||||
#define EMAC_EX_RX_125_CLK_EN_M (BIT(2))
|
||||
#define EMAC_EX_RX_125_CLK_EN_V 1
|
||||
#define EMAC_EX_RX_125_CLK_EN_S 2
|
||||
#define EMAC_EX_INT_OSC_EN (BIT(1))
|
||||
#define EMAC_EX_INT_OSC_EN_M (BIT(1))
|
||||
#define EMAC_EX_INT_OSC_EN_V 1
|
||||
#define EMAC_EX_INT_OSC_EN_S 1
|
||||
#define EMAC_EX_EXT_OSC_EN (BIT(0))
|
||||
#define EMAC_EX_EXT_OSC_EN_M (BIT(0))
|
||||
#define EMAC_EX_EXT_OSC_EN_V 1
|
||||
#define EMAC_EX_EXT_OSC_EN_S 0
|
||||
|
||||
#define EMAC_EX_PHYINF_CONF_REG (REG_EMAC_EX_BASE + 0x000c)
|
||||
#define EMAC_EX_TX_ERR_OUT_EN (BIT(20))
|
||||
#define EMAC_EX_TX_ERR_OUT_EN_M (BIT(20))
|
||||
#define EMAC_EX_TX_ERR_OUT_EN_V 1
|
||||
#define EMAC_EX_TX_ERR_OUT_EN_S 20
|
||||
#define EMAC_EX_SCR_SMI_DLY_RX_SYNC (BIT(19))
|
||||
#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_M (BIT(19))
|
||||
#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_V 1
|
||||
#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_S 19
|
||||
#define EMAC_EX_PMT_CTRL_EN (BIT(18))
|
||||
#define EMAC_EX_PMT_CTRL_EN_M (BIT(18))
|
||||
#define EMAC_EX_PMT_CTRL_EN_V 1
|
||||
#define EMAC_EX_PMT_CTRL_EN_S 18
|
||||
#define EMAC_EX_SBD_CLK_GATING_EN (BIT(17))
|
||||
#define EMAC_EX_SBD_CLK_GATING_EN_M (BIT(17))
|
||||
#define EMAC_EX_SBD_CLK_GATING_EN_V 1
|
||||
#define EMAC_EX_SBD_CLK_GATING_EN_S 17
|
||||
#define EMAC_EX_SS_MODE (BIT(16))
|
||||
#define EMAC_EX_SS_MODE_M (BIT(16))
|
||||
#define EMAC_EX_SS_MODE_V 1
|
||||
#define EMAC_EX_SS_MODE_S 16
|
||||
#define EMAC_EX_PHY_INTF_SEL 0x00000007
|
||||
#define EMAC_EX_PHY_INTF_SEL_M (EMAC_EX_PHY_INTF_SEL_V << EMAC_EX_PHY_INTF_SEL_S)
|
||||
#define EMAC_EX_PHY_INTF_SEL_V 0x00000007
|
||||
#define EMAC_EX_PHY_INTF_SEL_S 13
|
||||
#define EMAC_EX_REVMII_PHY_ADDR 0x0000001F
|
||||
#define EMAC_EX_REVMII_PHY_ADDR_M (EMAC_EX_REVMII_PHY_ADDR_V << EMAC_EX_REVMII_PHY_ADDR_S)
|
||||
#define EMAC_EX_REVMII_PHY_ADDR_V 0x0000001F
|
||||
#define EMAC_EX_REVMII_PHY_ADDR_S 8
|
||||
#define EMAC_EX_CORE_PHY_ADDR 0x0000001F
|
||||
#define EMAC_EX_CORE_PHY_ADDR_M (EMAC_EX_CORE_PHY_ADDR_V << EMAC_EX_CORE_PHY_ADDR_S)
|
||||
#define EMAC_EX_CORE_PHY_ADDR_V 0x0000001F
|
||||
#define EMAC_EX_CORE_PHY_ADDR_S 3
|
||||
#define EMAC_EX_SBD_FLOWCTRL (BIT(2))
|
||||
#define EMAC_EX_SBD_FLOWCTRL_M (BIT(2))
|
||||
#define EMAC_EX_SBD_FLOWCTRL_V 1
|
||||
#define EMAC_EX_SBD_FLOWCTRL_S 2
|
||||
#define EMAC_EX_EXT_REVMII_RX_CLK_SEL (BIT(1))
|
||||
#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_M (BIT(1))
|
||||
#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_V 1
|
||||
#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_S 1
|
||||
#define EMAC_EX_INT_REVMII_RX_CLK_SEL (BIT(0))
|
||||
#define EMAC_EX_INT_REVMII_RX_CLK_SEL_M (BIT(0))
|
||||
#define EMAC_EX_INT_REVMII_RX_CLK_SEL_V 1
|
||||
#define EMAC_EX_INT_REVMII_RX_CLK_SEL_S 0
|
||||
|
||||
#define EMAC_EX_PHY_INTF_RMII 4
|
||||
|
||||
#define EMAC_EX_EMAC_PD_SEL_REG (REG_EMAC_EX_BASE + 0x0010)
|
||||
#define EMAC_EX_RAM_PD_EN 0x00000003
|
||||
#define EMAC_EX_RAM_PD_EN_M (EMAC_EX_RAM_PD_EN_V << EMAC_EX_RAM_PD_EN_S)
|
||||
#define EMAC_EX_RAM_PD_EN_V 0x00000003
|
||||
#define EMAC_EX_RAM_PD_EN_S 0
|
||||
|
||||
#define EMAC_EX_DATE_REG (REG_EMAC_EX_BASE + 0x00fc)
|
||||
#define EMAC_EX_DATE 0xFFFFFFFF
|
||||
#define EMAC_EX_DATE_M (EMAC_EX_DATE_V << EMAC_EX_DATE_S)
|
||||
#define EMAC_EX_DATE_V 0xFFFFFFFF
|
||||
#define EMAC_EX_DATE_S 0
|
||||
#define EMAC_EX_DATE_VERSION 0x16042200
|
||||
#define EMAC_EX_DATE_VERSION_M (EMAC_EX_DATE_VERSION_V << EMAC_EX_DATE_VERSION_S)
|
||||
#define EMAC_EX_DATE_VERSION_V 0x16042200
|
||||
|
||||
#define EMAC_CLK_EN_REG 0x3ff000cc
|
||||
#define EMAC_CLK_EN_REG_M (EMAC_CLK_EN_REG_V << EMAC_CLK_EN_REG_S)
|
||||
#define EMAC_CLK_EN_REG_V 0x3ff000cc
|
||||
#define EMAC_CLK_EN (BIT(14))
|
||||
#define EMAC_CLK_EN_M (BIT(14))
|
||||
#define EMAC_CLK_EN_V 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -22,12 +22,20 @@
|
||||
|
||||
#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
|
||||
#define FE_IQ_EST_FORCE_PU (BIT(5))
|
||||
#define FE_IQ_EST_FORCE_PU_M (BIT(5))
|
||||
#define FE_IQ_EST_FORCE_PU_V 1
|
||||
#define FE_IQ_EST_FORCE_PU_S 5
|
||||
#define FE_IQ_EST_FORCE_PD (BIT(4))
|
||||
#define FE_IQ_EST_FORCE_PD_M (BIT(4))
|
||||
#define FE_IQ_EST_FORCE_PD_V 1
|
||||
#define FE_IQ_EST_FORCE_PD_S 4
|
||||
|
||||
#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
|
||||
#define FE2_TX_INF_FORCE_PU (BIT(10))
|
||||
#define FE2_TX_INF_FORCE_PU_M (BIT(10))
|
||||
#define FE2_TX_INF_FORCE_PU_V 1
|
||||
#define FE2_TX_INF_FORCE_PU_S 10
|
||||
#define FE2_TX_INF_FORCE_PD (BIT(9))
|
||||
#define FE2_TX_INF_FORCE_PD_M (BIT(9))
|
||||
#define FE2_TX_INF_FORCE_PD_V 1
|
||||
#define FE2_TX_INF_FORCE_PD_S 9
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
@ -16,20 +16,63 @@
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
|
||||
/* Output enable in sleep mode */
|
||||
#define SLP_OE (BIT(0))
|
||||
#define SLP_OE_M (BIT(0))
|
||||
#define SLP_OE_V 1
|
||||
#define SLP_OE_S 0
|
||||
/* Pin used for wakeup from sleep */
|
||||
#define SLP_SEL (BIT(1))
|
||||
#define SLP_SEL_M (BIT(1))
|
||||
#define SLP_SEL_V 1
|
||||
#define SLP_SEL_S 1
|
||||
/* Pulldown enable in sleep mode */
|
||||
#define SLP_PD (BIT(2))
|
||||
#define SLP_PD_M (BIT(2))
|
||||
#define SLP_PD_V 1
|
||||
#define SLP_PD_S 2
|
||||
/* Pullup enable in sleep mode */
|
||||
#define SLP_PU (BIT(3))
|
||||
#define SLP_PU_M (BIT(3))
|
||||
#define SLP_PU_V 1
|
||||
#define SLP_PU_S 3
|
||||
/* Input enable in sleep mode */
|
||||
#define SLP_IE (BIT(4))
|
||||
#define SLP_IE_M (BIT(4))
|
||||
#define SLP_IE_V 1
|
||||
#define SLP_IE_S 4
|
||||
/* Drive strength in sleep mode */
|
||||
#define SLP_DRV 0x3
|
||||
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
|
||||
#define SLP_DRV_V 0x3
|
||||
#define SLP_DRV_S 5
|
||||
/* Pulldown enable */
|
||||
#define FUN_PD (BIT(7))
|
||||
#define FUN_PD_M (BIT(7))
|
||||
#define FUN_PD_V 1
|
||||
#define FUN_PD_S 7
|
||||
/* Pullup enable */
|
||||
#define FUN_PU (BIT(8))
|
||||
#define FUN_PU_M (BIT(8))
|
||||
#define FUN_PU_V 1
|
||||
#define FUN_PU_S 8
|
||||
/* Input enable */
|
||||
#define FUN_IE (BIT(9))
|
||||
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
|
||||
#define FUN_IE_V 1
|
||||
#define FUN_IE_S 9
|
||||
/* Drive strength */
|
||||
#define FUN_DRV 0x3
|
||||
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
|
||||
#define FUN_DRV_V 0x3
|
||||
#define FUN_DRV_S 10
|
||||
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
|
||||
#define MCU_SEL 0x7
|
||||
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
|
||||
#define MCU_SEL_V 0x7
|
||||
#define MCU_SEL_S 12
|
||||
#define MCU_SEL_V 0x7
|
||||
|
||||
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
|
||||
@ -22,18 +22,34 @@
|
||||
|
||||
#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
|
||||
#define NRX_CHAN_EST_FORCE_PU (BIT(7))
|
||||
#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
|
||||
#define NRX_CHAN_EST_FORCE_PU_V 1
|
||||
#define NRX_CHAN_EST_FORCE_PU_S 7
|
||||
#define NRX_CHAN_EST_FORCE_PD (BIT(6))
|
||||
#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
|
||||
#define NRX_CHAN_EST_FORCE_PD_V 1
|
||||
#define NRX_CHAN_EST_FORCE_PD_S 6
|
||||
#define NRX_RX_ROT_FORCE_PU (BIT(5))
|
||||
#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
|
||||
#define NRX_RX_ROT_FORCE_PU_V 1
|
||||
#define NRX_RX_ROT_FORCE_PU_S 5
|
||||
#define NRX_RX_ROT_FORCE_PD (BIT(4))
|
||||
#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
|
||||
#define NRX_RX_ROT_FORCE_PD_V 1
|
||||
#define NRX_RX_ROT_FORCE_PD_S 4
|
||||
#define NRX_VIT_FORCE_PU (BIT(3))
|
||||
#define NRX_VIT_FORCE_PU_M (BIT(3))
|
||||
#define NRX_VIT_FORCE_PU_V 1
|
||||
#define NRX_VIT_FORCE_PU_S 3
|
||||
#define NRX_VIT_FORCE_PD (BIT(2))
|
||||
#define NRX_VIT_FORCE_PD_M (BIT(2))
|
||||
#define NRX_VIT_FORCE_PD_V 1
|
||||
#define NRX_VIT_FORCE_PD_S 2
|
||||
#define NRX_DEMAP_FORCE_PU (BIT(1))
|
||||
#define NRX_DEMAP_FORCE_PU_M (BIT(1))
|
||||
#define NRX_DEMAP_FORCE_PU_V 1
|
||||
#define NRX_DEMAP_FORCE_PU_S 1
|
||||
#define NRX_DEMAP_FORCE_PD (BIT(0))
|
||||
#define NRX_DEMAP_FORCE_PD_M (BIT(0))
|
||||
#define NRX_DEMAP_FORCE_PD_V 1
|
||||
#define NRX_DEMAP_FORCE_PD_S 0
|
||||
|
||||
@ -92,6 +92,9 @@ typedef enum {
|
||||
RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator
|
||||
} rtc_fast_freq_t;
|
||||
|
||||
/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX 8500000
|
||||
|
||||
/**
|
||||
* @brief Clock source to be calibrated using rtc_clk_cal function
|
||||
*/
|
||||
@ -165,6 +168,15 @@ void rtc_clk_32k_enable(bool en);
|
||||
*/
|
||||
bool rtc_clk_32k_enabled();
|
||||
|
||||
/**
|
||||
* @brief Enable 32k oscillator, configuring it for fast startup time.
|
||||
* Note: to achieve higher frequency stability, rtc_clk_32k_enable function
|
||||
* must be called one the 32k XTAL oscillator has started up. This function
|
||||
* will initially disable the 32k XTAL oscillator, so it should not be called
|
||||
* when the system is using 32k XTAL as RTC_SLOW_CLK.
|
||||
*/
|
||||
void rtc_clk_32k_bootstrap();
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 8 MHz internal oscillator
|
||||
*
|
||||
@ -226,6 +238,20 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
|
||||
*/
|
||||
rtc_slow_freq_t rtc_clk_slow_freq_get();
|
||||
|
||||
/**
|
||||
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
|
||||
*
|
||||
* - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
|
||||
* - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
|
||||
* - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
|
||||
*
|
||||
* rtc_clk_cal function can be used to get more precise value by comparing
|
||||
* RTC_SLOW_CLK frequency to the frequency of main XTAL.
|
||||
*
|
||||
* @return RTC_SLOW_CLK frequency, in Hz
|
||||
*/
|
||||
uint32_t rtc_clk_slow_freq_get_hz();
|
||||
|
||||
/**
|
||||
* @brief Select source for RTC_FAST_CLK
|
||||
* @param fast_freq clock source (one of rtc_fast_freq_t values)
|
||||
@ -307,6 +333,15 @@ uint32_t rtc_clk_apb_freq_get();
|
||||
*/
|
||||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
|
||||
|
||||
/**
|
||||
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
|
||||
* @param cal_clk slow clock to be measured
|
||||
* @param slow_clk_cycles number of slow clock cycles to average
|
||||
* @return average ratio between XTAL frequency and slow clock frequency,
|
||||
* Q13.19 fixed point format, or 0 if calibration has timed out.
|
||||
*/
|
||||
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
|
||||
|
||||
/**
|
||||
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
|
||||
* @param time_in_us Time interval in microseconds
|
||||
|
||||
@ -239,9 +239,6 @@
|
||||
#define RTC_CNTL_TIME_VALID_V 0x1
|
||||
#define RTC_CNTL_TIME_VALID_S 30
|
||||
|
||||
/* frequency of RTC slow clock, Hz */
|
||||
#define RTC_CNTL_SLOWCLK_FREQ 150000
|
||||
|
||||
#define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10)
|
||||
/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: RTC timer low 32 bits*/
|
||||
|
||||
@ -511,6 +511,7 @@
|
||||
#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S))
|
||||
#define RTC_IO_DEBUG_SEL0_V 0x1F
|
||||
#define RTC_IO_DEBUG_SEL0_S 0
|
||||
#define RTC_IO_DEBUG_SEL0_8M 1
|
||||
#define RTC_IO_DEBUG_SEL0_32K_XTAL 4
|
||||
#define RTC_IO_DEBUG_SEL0_150K_OSC 5
|
||||
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
@ -65,8 +65,9 @@
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
#else
|
||||
#define BIT(nr) (1 << (nr))
|
||||
#endif //__ASSEMBLER__
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
//write value to register
|
||||
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
|
||||
|
||||
@ -88,8 +89,8 @@
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
|
||||
|
||||
//set field to register, used when _f is not left shifted by _f##_S
|
||||
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S)))))
|
||||
//set field of a register from variable, uses field _S & _V to determine mask
|
||||
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
@ -134,6 +135,8 @@
|
||||
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
|
||||
//}}
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
//Periheral Clock {{
|
||||
#define APB_CLK_FREQ_ROM ( 26*1000000 )
|
||||
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
|
||||
@ -146,6 +149,16 @@
|
||||
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
|
||||
//}}
|
||||
|
||||
/* Overall memory map */
|
||||
#define SOC_IROM_LOW 0x400D0000
|
||||
#define SOC_IROM_HIGH 0x40400000
|
||||
#define SOC_DROM_LOW 0x3F400000
|
||||
#define SOC_DROM_HIGH 0x3F800000
|
||||
#define SOC_RTC_IRAM_LOW 0x400C0000
|
||||
#define SOC_RTC_IRAM_HIGH 0x400C2000
|
||||
#define SOC_RTC_DATA_LOW 0x50000000
|
||||
#define SOC_RTC_DATA_HIGH 0x50002000
|
||||
|
||||
#define DR_REG_DPORT_BASE 0x3ff00000
|
||||
#define DR_REG_RSA_BASE 0x3ff02000
|
||||
#define DR_REG_SHA_BASE 0x3ff03000
|
||||
@ -273,14 +286,14 @@
|
||||
/*************************************************************************************************************
|
||||
* Intr num Level Type PRO CPU usage APP CPU uasge
|
||||
* 0 1 extern level WMAC Reserved
|
||||
* 1 1 extern level BT/BLE Host VHCI Reserved
|
||||
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
|
||||
* 2 1 extern level
|
||||
* 3 1 extern level
|
||||
* 4 1 extern level WBB
|
||||
* 5 1 extern level BT/BLE Controller
|
||||
* 5 1 extern level BT/BLE Controller BT/BLE Controller
|
||||
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
|
||||
* 7 1 software Reserved Reserved
|
||||
* 8 1 extern level BT/BLE BB(RX/TX)
|
||||
* 7 1 software BT/BLE VHCI BT/BLE VHCI
|
||||
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
|
||||
* 9 1 extern level
|
||||
* 10 1 extern edge Internal Timer
|
||||
* 11 3 profiling
|
||||
@ -297,7 +310,7 @@
|
||||
* 22 3 extern edge FRC1 timer
|
||||
* 23 3 extern level
|
||||
* 24 4 extern level TG1_WDT
|
||||
* 25 4 extern level Reserved Reserved
|
||||
* 25 4 extern level CACHEERR
|
||||
* 26 5 extern level Reserved Reserved
|
||||
* 27 3 extern level Reserved Reserved
|
||||
* 28 4 extern edge
|
||||
@ -314,6 +327,7 @@
|
||||
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
|
||||
#define ETS_FRC1_INUM 22
|
||||
#define ETS_T1_WDT_INUM 24
|
||||
#define ETS_CACHEERR_INUM 25
|
||||
|
||||
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
|
||||
#define ETS_SLC_INUM 1
|
||||
|
||||
Reference in New Issue
Block a user