espressif/arduino-esp32
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update IDF libs and includes

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This commit is contained in:
me-no-dev
2017-01-16 16:03:13 +02:00
parent 49a476c5f0
commit 3b874d51e8
127 changed files with 8996 additions and 331 deletions
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2
tools/sdk/include/esp32/esp_attr.h
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@ -26,7 +26,7 @@
// Forces data into DRAM instead of flash
#define DRAM_ATTR __attribute__((section(".dram1")))
// Forces a string into DRAM instrad of flash
// Forces a string into DRAM instead of flash
// Use as ets_printf(DRAM_STR("Hello world!\n"));
#define DRAM_STR(str) (__extension__({static const DRAM_ATTR char __c[] = (str); (const char *)&__c;}))

64
tools/sdk/include/esp32/esp_core_dump.h Normal file
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@ -0,0 +1,64 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef ESP_CORE_DUMP_H_
#define ESP_CORE_DUMP_H_
/**
* @brief Initializes core dump module internal data.
*
* @note Should be called at system startup.
*/
void esp_core_dump_init();
/**
* @brief Saves core dump to flash.
*
* The structure of data stored in flash is as follows:
* | MAGIC1 |
* | TOTAL_LEN | TASKS_NUM | TCB_SIZE |
* | TCB_ADDR_1 | STACK_TOP_1 | STACK_END_1 | TCB_1 | STACK_1 |
* . . . .
* . . . .
* | TCB_ADDR_N | STACK_TOP_N | STACK_END_N | TCB_N | STACK_N |
* | MAGIC2 |
* Core dump in flash consists of header and data for every task in the system at the moment of crash.
* For flash data integrity control two magic numbers are used at the beginning and the end of core dump.
* The structure of core dump data is described below in details.
* 1) MAGIC1 and MAGIC2 are special numbers stored at the beginning and the end of core dump.
* They are used to control core dump data integrity. Size of every number is 4 bytes.
* 2) Core dump starts with header:
* 2.1) TOTAL_LEN is total length of core dump data in flash including magic numbers. Size is 4 bytes.
* 2.2) TASKS_NUM is the number of tasks for which data are stored. Size is 4 bytes.
* 2.3) TCB_SIZE is the size of task's TCB structure. Size is 4 bytes.
* 3) Core dump header is followed by the data for every task in the system.
* Task data are started with task header:
* 3.1) TCB_ADDR is the address of TCB in memory. Size is 4 bytes.
* 3.2) STACK_TOP is the top of task's stack (address of the topmost stack item). Size is 4 bytes.
* 3.2) STACK_END is the end of task's stack (address from which task's stack starts). Size is 4 bytes.
* 4) Task header is followed by TCB data. Size is TCB_SIZE bytes.
* 5) Task's stack is placed after TCB data. Size is (STACK_END - STACK_TOP) bytes.
*/
void esp_core_dump_to_flash();
/**
* @brief Print base64-encoded core dump to UART.
*
* The structure of core dump data is the same as for data stored in flash (@see esp_core_dump_to_flash) with some notes:
* 1) Magic numbers are not present in core dump printed to UART.
* 2) Since magic numbers are omitted TOTAL_LEN does not include their size.
* 3) Printed base64 data are surrounded with special messages to help user recognize the start and end of actual data.
*/
void esp_core_dump_to_uart();
#endif

3
tools/sdk/include/esp32/esp_err.h
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@ -35,7 +35,8 @@ typedef int32_t esp_err_t;
#define ESP_ERR_NOT_FOUND 0x105
#define ESP_ERR_NOT_SUPPORTED 0x106
#define ESP_ERR_TIMEOUT 0x107
#define ESP_ERR_INVALID_RESPONSE 0x108
#define ESP_ERR_INVALID_CRC 0x109
#define ESP_ERR_WIFI_BASE 0x3000 /*!< Starting number of WiFi error codes */

5
tools/sdk/include/esp32/esp_intr_alloc.h
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@ -124,6 +124,9 @@ esp_err_t esp_intr_reserve(int intno, int cpu);
*
* The interrupt will always be allocated on the core that runs this function.
*
* If ESP_INTR_FLAG_IRAM flag is used, and handler address is not in IRAM or
* RTC_FAST_MEM, then ESP_ERR_INVALID_ARG is returned.
*
* @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux
* sources, as defined in soc/soc.h, or one of the internal
* ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header.
@ -264,4 +267,4 @@ void esp_intr_noniram_enable();
}
#endif
#endif
#endif

43
tools/sdk/include/esp32/esp_panic.h
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@ -14,8 +14,49 @@
#ifndef __ASSEMBLER__
#include "esp_err.h"
/**
* @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function
* address. Do nothing otherwise.
* @param data Pointer to the target breakpoint position
*/
void esp_set_breakpoint_if_jtag(void *fn);
#define ESP_WATCHPOINT_LOAD 0x40000000
#define ESP_WATCHPOINT_STORE 0x80000000
#define ESP_WATCHPOINT_ACCESS 0xC0000000
/**
* @brief Set a watchpoint to break/panic when a certain memory range is accessed.
*
* @param no Watchpoint number. On the ESP32, this can be 0 or 1.
* @param adr Base address to watch
* @param size Size of the region, starting at the base address, to watch. Must
* be one of 2^n, with n in [0..6].
* @param flags One of ESP_WATCHPOINT_* flags
*
* @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
*
* @warning The ESP32 watchpoint hardware watches a region of bytes by effectively
* masking away the lower n bits for a region with size 2^n. If adr does
* not have zero for these lower n bits, you may not be watching the
* region you intended.
*/
esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags);
/**
* @brief Clear a watchpoint
*
* @param no Watchpoint to clear
*
*/
void esp_clear_watchpoint(int no);
#endif
#endif
#endif

2
tools/sdk/include/esp32/esp_phy_init.h
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@ -229,7 +229,7 @@ esp_err_t esp_phy_store_cal_data_to_nvs(const esp_phy_calibration_data_t* cal_da
*
* Applications which don't need to enable PHY on every start up should
* disable this menuconfig option and call esp_phy_init before calling
* esp_wifi_init or bt_controller_init. See do_phy_init function in
* esp_wifi_init or esp_bt_controller_init. See do_phy_init function in
* cpu_start.c for an example of using this function.
*
* @param init_data PHY parameters. Default set of parameters can

28
tools/sdk/include/esp32/esp_wifi.h
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@ -62,6 +62,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#include "rom/queue.h"
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_wifi_types.h"
#include "esp_event.h"
@ -76,8 +77,8 @@ extern "C" {
#define ESP_ERR_WIFI_ARG ESP_ERR_INVALID_ARG /*!< Invalid argument */
#define ESP_ERR_WIFI_NOT_SUPPORT ESP_ERR_NOT_SUPPORTED /*!< Indicates that API is not supported yet */
#define ESP_ERR_WIFI_NOT_INIT (ESP_ERR_WIFI_BASE + 1) /*!< WiFi driver is not installed by esp_wifi_init */
#define ESP_ERR_WIFI_NOT_START (ESP_ERR_WIFI_BASE + 2) /*!< WiFi driver is not started by esp_wifi_start */
#define ESP_ERR_WIFI_NOT_INIT (ESP_ERR_WIFI_BASE + 1) /*!< WiFi driver was not installed by esp_wifi_init */
#define ESP_ERR_WIFI_NOT_STARTED (ESP_ERR_WIFI_BASE + 2) /*!< WiFi driver was not started by esp_wifi_start */
#define ESP_ERR_WIFI_IF (ESP_ERR_WIFI_BASE + 3) /*!< WiFi interface error */
#define ESP_ERR_WIFI_MODE (ESP_ERR_WIFI_BASE + 4) /*!< WiFi mode error */
#define ESP_ERR_WIFI_STATE (ESP_ERR_WIFI_BASE + 5) /*!< WiFi internal state error */
@ -85,7 +86,7 @@ extern "C" {
#define ESP_ERR_WIFI_NVS (ESP_ERR_WIFI_BASE + 7) /*!< WiFi internal NVS module error */
#define ESP_ERR_WIFI_MAC (ESP_ERR_WIFI_BASE + 8) /*!< MAC address is invalid */
#define ESP_ERR_WIFI_SSID (ESP_ERR_WIFI_BASE + 9) /*!< SSID is invalid */
#define ESP_ERR_WIFI_PASSWORD (ESP_ERR_WIFI_BASE + 10) /*!< Passord is invalid */
#define ESP_ERR_WIFI_PASSWORD (ESP_ERR_WIFI_BASE + 10) /*!< Password is invalid */
#define ESP_ERR_WIFI_TIMEOUT (ESP_ERR_WIFI_BASE + 11) /*!< Timeout error */
#define ESP_ERR_WIFI_WAKE_FAIL (ESP_ERR_WIFI_BASE + 12) /*!< WiFi is in sleep state(RF closed) and wakeup fail */
@ -94,12 +95,17 @@ extern "C" {
*/
typedef struct {
system_event_handler_t event_handler; /**< WiFi event handler */
uint32_t rx_buf_num; /**< WiFi RX buffer number */
} wifi_init_config_t;
#ifdef CONFIG_WIFI_ENABLED
#define WIFI_INIT_CONFIG_DEFAULT() { \
.event_handler = &esp_event_send, \
.rx_buf_num = CONFIG_ESP32_WIFI_RX_BUFFER_NUM, \
};
#else
#define WIFI_INIT_CONFIG_DEFAULT #error Wifi is disabled in config, WIFI_INIT_CONFIG_DEFAULT will not work
#endif
/**
* @brief Init WiFi
@ -220,8 +226,8 @@ esp_err_t esp_wifi_connect(void);
*
* @return
* - ESP_OK: succeed
* - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by eps_wifi_init
* - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
* - ESP_ERR_WIFI_NOT_INIT: WiFi was not initialized by eps_wifi_init
* - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
* - ESP_ERR_WIFI_FAIL: other WiFi internal errors
*/
esp_err_t esp_wifi_disconnect(void);
@ -244,7 +250,7 @@ esp_err_t esp_wifi_clear_fast_connect(void);
* @return
* - ESP_OK: succeed
* - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by eps_wifi_init
* - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
* - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
* - ESP_ERR_WIFI_ARG: invalid argument
* - ESP_ERR_WIFI_MODE: WiFi mode is wrong
*/
@ -264,7 +270,7 @@ esp_err_t esp_wifi_deauth_sta(uint16_t aid);
* @return
* - ESP_OK: succeed
* - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by eps_wifi_init
* - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
* - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
* - ESP_ERR_WIFI_TIMEOUT: blocking scan is timeout
* - others: refer to error code in esp_err.h
*/
@ -276,7 +282,7 @@ esp_err_t esp_wifi_scan_start(wifi_scan_config_t *config, bool block);
* @return
* - ESP_OK: succeed
* - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by eps_wifi_init
* - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
* - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
*/
esp_err_t esp_wifi_scan_stop(void);
@ -290,7 +296,7 @@ esp_err_t esp_wifi_scan_stop(void);
* @return
* - ESP_OK: succeed
* - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by eps_wifi_init
* - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
* - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
* - ESP_ERR_WIFI_ARG: invalid argument
*/
esp_err_t esp_wifi_scan_get_ap_num(uint16_t *number);
@ -305,7 +311,7 @@ esp_err_t esp_wifi_scan_get_ap_num(uint16_t *number);
* @return
* - ESP_OK: succeed
* - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by eps_wifi_init
* - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
* - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
* - ESP_ERR_WIFI_ARG: invalid argument
* - ESP_ERR_WIFI_NO_MEM: out of memory
*/

5
tools/sdk/include/esp32/esp_wifi_types.h
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@ -109,6 +109,8 @@ typedef struct {
wifi_second_chan_t second; /**< second channel of AP */
int8_t rssi; /**< signal strength of AP */
wifi_auth_mode_t authmode; /**< authmode of AP */
uint32_t low_rate_enable:1; /**< bit: 0 flag to identify if low rate is enabled or not */
uint32_t reserved:31; /**< bit: 1..31 reserved */
} wifi_ap_record_t;
typedef enum {
@ -119,9 +121,10 @@ typedef enum {
#define WIFI_PROTOCOL_11B 1
#define WIFI_PROTOCOL_11G 2
#define WIFI_PROTOCOL_11N 4
#define WIFI_PROTOCOL_LR 8
typedef enum {
WIFI_BW_HT20 = 0, /* Bandwidth is HT20 */
WIFI_BW_HT20 = 1, /* Bandwidth is HT20 */
WIFI_BW_HT40, /* Bandwidth is HT40 */
} wifi_bandwidth_t;

101
tools/sdk/include/esp32/esp_wpa2.h
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@ -24,35 +24,58 @@ extern "C" {
/**
* @brief Enable wpa2 enterprise authentication.
*
* @attention wpa2 enterprise authentication can only be used when ESP32 station is enabled.
* wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
* @attention 1. wpa2 enterprise authentication can only be used when ESP32 station is enabled.
* @attention 2. wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
*
* @return ESP_ERR_WIFI_OK: succeed.
* ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
* @return
* - ESP_ERR_WIFI_OK: succeed.
* - ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_enable(void);
/**
* @brief Disable wpa2 enterprise authentication.
*
* @attention wpa2 enterprise authentication can only be used when ESP32 station is enabled.
* wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
* @attention 1. wpa2 enterprise authentication can only be used when ESP32 station is enabled.
* @attention 2. wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
*
* @return ESP_ERR_WIFI_OK: succeed.
* @return
* - ESP_ERR_WIFI_OK: succeed.
*/
esp_err_t esp_wifi_sta_wpa2_ent_disable(void);
/**
* @brief Set identity for PEAP/TTLS method.
*
* @attention The API only passes the parameter identity to the global pointer variable in wpa2 enterprise module.
*
* @param identity: point to address where stores the identity;
* @param len: length of identity, limited to 1~127
*
* @return
* - ESP_ERR_WIFI_OK: succeed
* - ESP_ERR_WIFI_ARG: fail(len <= 0 or len >= 128)
* - ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_identity(unsigned char *identity, int len);
/**
* @brief Clear identity for PEAP/TTLS method.
*/
void esp_wifi_sta_wpa2_ent_clear_identity(void);
/**
* @brief Set username for PEAP/TTLS method.
*
* @attention The API only passes the parameter username to the global pointer variable in wpa2 enterprise module.
*
* @param username: point to address where stores the username;
* len: length of username, limited to 1~127
* @param len: length of username, limited to 1~127
*
* @return ESP_ERR_WIFI_OK: succeed
* ESP_ERR_WIFI_ARG: fail(len <= 0 or len >= 128)
* ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
* @return
* - ESP_ERR_WIFI_OK: succeed
* - ESP_ERR_WIFI_ARG: fail(len <= 0 or len >= 128)
* - ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_username(unsigned char *username, int len);
@ -67,11 +90,12 @@ void esp_wifi_sta_wpa2_ent_clear_username(void);
* @attention The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
*
* @param password: point to address where stores the password;
* len: length of password(len > 0)
* @param len: length of password(len > 0)
*
* @return ESP_ERR_WIFI_OK: succeed
* ESP_ERR_WIFI_ARG: fail(len <= 0)
* ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
* @return
* - ESP_ERR_WIFI_OK: succeed
* - ESP_ERR_WIFI_ARG: fail(len <= 0)
* - ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_password(unsigned char *password, int len);
@ -83,15 +107,16 @@ void esp_wifi_sta_wpa2_ent_clear_password(void);
/**
* @brief Set new password for MSCHAPv2 method..
*
* @attention The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
* The new password is used to substitute the old password when eap-mschapv2 failure request message with error code ERROR_PASSWD_EXPIRED is received.
* @attention 1. The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
* @attention 2. The new password is used to substitute the old password when eap-mschapv2 failure request message with error code ERROR_PASSWD_EXPIRED is received.
*
* @param password: point to address where stores the password;
* len: length of password
* @param len: length of password
*
* @return ESP_ERR_WIFI_OK: succeed
* ESP_ERR_WIFI_ARG: fail(len <= 0)
* ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
* @return
* - ESP_ERR_WIFI_OK: succeed
* - ESP_ERR_WIFI_ARG: fail(len <= 0)
* - ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_new_password(unsigned char *password, int len);
@ -104,13 +129,14 @@ void esp_wifi_sta_wpa2_ent_clear_new_password(void);
/**
* @brief Set CA certificate for PEAP/TTLS method.
*
* @attention The API only passes the parameter ca_cert to the global pointer variable in wpa2 enterprise module.
* The ca_cert should be zero terminated.
* @attention 1. The API only passes the parameter ca_cert to the global pointer variable in wpa2 enterprise module.
* @attention 2. The ca_cert should be zero terminated.
*
* @param ca_cert: point to address where stores the CA certificate;
* len: length of ca_cert
* @param len: length of ca_cert
*
* @return ESP_ERR_WIFI_OK: succeed
* @return
* - ESP_ERR_WIFI_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_ca_cert(unsigned char *ca_cert, int len);
@ -122,17 +148,18 @@ void esp_wifi_sta_wpa2_ent_clear_ca_cert(void);
/**
* @brief Set client certificate and key.
*
* @attention The API only passes the parameter client_cert, private_key and private_key_passwd to the global pointer variable in wpa2 enterprise module.
* The client_cert, private_key and private_key_passwd should be zero terminated.
* @attention 1. The API only passes the parameter client_cert, private_key and private_key_passwd to the global pointer variable in wpa2 enterprise module.
* @attention 2. The client_cert, private_key and private_key_passwd should be zero terminated.
*
* @param client_cert: point to address where stores the client certificate;
* client_cert_len: length of client certificate;
* private_key: point to address where stores the private key;
* private_key_len: length of private key, limited to 1~2048;
* private_key_password: point to address where stores the private key password;
* private_key_password_len: length of private key password;
* @param client_cert_len: length of client certificate;
* @param private_key: point to address where stores the private key;
* @param private_key_len: length of private key, limited to 1~2048;
* @param private_key_password: point to address where stores the private key password;
* @param private_key_password_len: length of private key password;
*
* @return ESP_ERR_WIFI_OK: succeed
* @return
* - ESP_ERR_WIFI_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_cert_key(unsigned char *client_cert, int client_cert_len, unsigned char *private_key, int private_key_len, unsigned char *private_key_passwd, int private_key_passwd_len);
@ -145,9 +172,10 @@ void esp_wifi_sta_wpa2_ent_clear_cert_key(void);
* @brief Set wpa2 enterprise certs time check(disable or not).
*
* @param true: disable wpa2 enterprise certs time check
* false: enable wpa2 enterprise certs time check
* @param false: enable wpa2 enterprise certs time check
*
* @return ESP_OK: succeed
* @return
* - ESP_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_disable_time_check(bool disable);
@ -156,7 +184,8 @@ esp_err_t esp_wifi_sta_wpa2_ent_set_disable_time_check(bool disable);
*
* @param disable: store disable value
*
* @return ESP_OK: succeed
* @return
* - ESP_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_get_disable_time_check(bool *disable);

12
tools/sdk/include/esp32/rom/ets_sys.h
View File

@ -383,6 +383,18 @@ void ets_delay_us(uint32_t us);
*/
void ets_update_cpu_frequency(uint32_t ticks_per_us);
/**
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
*
* @note This function only sets the tick rate for the current CPU. It is located in ROM,
* so the deep sleep stub can use it even if IRAM is not initialized yet.
*
* @param uint32_t ticks_per_us : CPU ticks per us.
*
* @return None
*/
void ets_update_cpu_frequency_rom(uint32_t ticks_per_us);
/**
* @brief Get the real CPU ticks per us to the ets.
* This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.

20
tools/sdk/include/esp32/rom/rtc.h
View File

@ -53,16 +53,18 @@ extern "C" {
* Rtc store registers usage
* RTC_CNTL_STORE0_REG
* RTC_CNTL_STORE1_REG
* RTC_CNTL_STORE2_REG
* RTC_CNTL_STORE3_REG
* RTC_CNTL_STORE4_REG Reserved
* RTC_CNTL_STORE5_REG External Xtal Frequency
* RTC_CNTL_STORE2_REG Boot time, low word
* RTC_CNTL_STORE3_REG Boot time, high word
* RTC_CNTL_STORE4_REG External XTAL frequency
* RTC_CNTL_STORE5_REG APB bus frequency
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
*************************************************************************************
*/
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
typedef enum {
@ -179,6 +181,9 @@ void set_rtc_memory_crc(void);
/**
* @brief Software Reset digital core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param None
*
* @return None
@ -188,6 +193,9 @@ void software_reset(void);
/**
* @brief Software Reset digital core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
*
* @return None

18
tools/sdk/include/esp32/soc/dport_reg.h
View File

@ -1035,14 +1035,20 @@
#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF
#define DPORT_WIFI_CLK_EN_S 0
#define DPORT_WIFI_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0)
/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
#define DPORT_CORE_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0)
/* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPROT_RW_BTLP_RST (BIT(10))
#define DPROT_RW_BTMAC_RST (BIT(9))
#define DPORT_MACPWR_RST (BIT(8))
#define DPORT_EMAC_RST (BIT(7))
#define DPORT_SDIO_HOST_RST (BIT(6))
#define DPORT_SDIO_RST (BIT(5))
#define DPORT_BTMAC_RST (BIT(4))
#define DPORT_BT_RST (BIT(3))
#define DPORT_MAC_RST (BIT(2))
#define DPORT_WIFI_RST 0xFFFFFFFF
#define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S))
#define DPORT_WIFI_RST_V 0xFFFFFFFF
#define DPORT_WIFI_RST_S 0
#define DPORT_FE_RST (BIT(1))
#define DPORT_BB_RST (BIT(0))
#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4)
/* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */

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tools/sdk/include/esp32/soc/sdmmc_reg.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SDMMC_REG_H_
#define _SOC_SDMMC_REG_H_
#include "soc.h"
#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00)
#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04)
#define SDMMC_CLKDIV_REG (DR_REG_SDMMC_BASE + 0x08)
#define SDMMC_CLKSRC_REG (DR_REG_SDMMC_BASE + 0x0c)
#define SDMMC_CLKENA_REG (DR_REG_SDMMC_BASE + 0x10)
#define SDMMC_TMOUT_REG (DR_REG_SDMMC_BASE + 0x14)
#define SDMMC_CTYPE_REG (DR_REG_SDMMC_BASE + 0x18)
#define SDMMC_BLKSIZ_REG (DR_REG_SDMMC_BASE + 0x1c)
#define SDMMC_BYTCNT_REG (DR_REG_SDMMC_BASE + 0x20)
#define SDMMC_INTMASK_REG (DR_REG_SDMMC_BASE + 0x24)
#define SDMMC_CMDARG_REG (DR_REG_SDMMC_BASE + 0x28)
#define SDMMC_CMD_REG (DR_REG_SDMMC_BASE + 0x2c)
#define SDMMC_RESP0_REG (DR_REG_SDMMC_BASE + 0x30)
#define SDMMC_RESP1_REG (DR_REG_SDMMC_BASE + 0x34)
#define SDMMC_RESP2_REG (DR_REG_SDMMC_BASE + 0x38)
#define SDMMC_RESP3_REG (DR_REG_SDMMC_BASE + 0x3c)
#define SDMMC_MINTSTS_REG (DR_REG_SDMMC_BASE + 0x40)
#define SDMMC_RINTSTS_REG (DR_REG_SDMMC_BASE + 0x44)
#define SDMMC_STATUS_REG (DR_REG_SDMMC_BASE + 0x48)
#define SDMMC_FIFOTH_REG (DR_REG_SDMMC_BASE + 0x4c)
#define SDMMC_CDETECT_REG (DR_REG_SDMMC_BASE + 0x50)
#define SDMMC_WRTPRT_REG (DR_REG_SDMMC_BASE + 0x54)
#define SDMMC_GPIO_REG (DR_REG_SDMMC_BASE + 0x58)
#define SDMMC_TCBCNT_REG (DR_REG_SDMMC_BASE + 0x5c)
#define SDMMC_TBBCNT_REG (DR_REG_SDMMC_BASE + 0x60)
#define SDMMC_DEBNCE_REG (DR_REG_SDMMC_BASE + 0x64)
#define SDMMC_USRID_REG (DR_REG_SDMMC_BASE + 0x68)
#define SDMMC_VERID_REG (DR_REG_SDMMC_BASE + 0x6c)
#define SDMMC_HCON_REG (DR_REG_SDMMC_BASE + 0x70)
#define SDMMC_UHS_REG_REG (DR_REG_SDMMC_BASE + 0x74)
#define SDMMC_RST_N_REG (DR_REG_SDMMC_BASE + 0x78)
#define SDMMC_BMOD_REG (DR_REG_SDMMC_BASE + 0x80)
#define SDMMC_PLDMND_REG (DR_REG_SDMMC_BASE + 0x84)
#define SDMMC_DBADDR_REG (DR_REG_SDMMC_BASE + 0x88)
#define SDMMC_DBADDRU_REG (DR_REG_SDMMC_BASE + 0x8c)
#define SDMMC_IDSTS_REG (DR_REG_SDMMC_BASE + 0x8c)
#define SDMMC_IDINTEN_REG (DR_REG_SDMMC_BASE + 0x90)
#define SDMMC_DSCADDR_REG (DR_REG_SDMMC_BASE + 0x94)
#define SDMMC_DSCADDRL_REG (DR_REG_SDMMC_BASE + 0x98)
#define SDMMC_DSCADDRU_REG (DR_REG_SDMMC_BASE + 0x9c)
#define SDMMC_BUFADDRL_REG (DR_REG_SDMMC_BASE + 0xa0)
#define SDMMC_BUFADDRU_REG (DR_REG_SDMMC_BASE + 0xa4)
#define SDMMC_CARDTHRCTL_REG (DR_REG_SDMMC_BASE + 0x100)
#define SDMMC_BACK_END_POWER_REG (DR_REG_SDMMC_BASE + 0x104)
#define SDMMC_UHS_REG_EXT_REG (DR_REG_SDMMC_BASE + 0x108)
#define SDMMC_EMMC_DDR_REG_REG (DR_REG_SDMMC_BASE + 0x10c)
#define SDMMC_ENABLE_SHIFT_REG (DR_REG_SDMMC_BASE + 0x110)
#define SDMMC_CLOCK_REG (DR_REG_SDMMC_BASE + 0x800)
#define SDMMC_INTMASK_EBE BIT(15)
#define SDMMC_INTMASK_ACD BIT(14)
#define SDMMC_INTMASK_SBE BIT(13)
#define SDMMC_INTMASK_HLE BIT(12)
#define SDMMC_INTMASK_FRUN BIT(11)
#define SDMMC_INTMASK_HTO BIT(10)
#define SDMMC_INTMASK_DTO BIT(9)
#define SDMMC_INTMASK_RTO BIT(8)
#define SDMMC_INTMASK_DCRC BIT(7)
#define SDMMC_INTMASK_RCRC BIT(6)
#define SDMMC_INTMASK_RXDR BIT(5)
#define SDMMC_INTMASK_TXDR BIT(4)
#define SDMMC_INTMASK_DATA_OVER BIT(3)
#define SDMMC_INTMASK_CMD_DONE BIT(2)
#define SDMMC_INTMASK_RESP_ERR BIT(1)
#define SDMMC_INTMASK_CD BIT(0)
#define SDMMC_IDMAC_INTMASK_AI BIT(9)
#define SDMMC_IDMAC_INTMASK_NI BIT(8)
#define SDMMC_IDMAC_INTMASK_CES BIT(5)
#define SDMMC_IDMAC_INTMASK_DU BIT(4)
#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
#define SDMMC_IDMAC_INTMASK_RI BIT(1)
#define SDMMC_IDMAC_INTMASK_TI BIT(0)
#endif /* _SOC_SDMMC_REG_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SDMMC_STRUCT_H_
#define _SOC_SDMMC_STRUCT_H_
#include <stdint.h>
typedef struct {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
void* buffer1_ptr;
union {
void* buffer2_ptr;
void* next_desc_ptr;
};
} sdmmc_desc_t;
#define SDMMC_DMA_MAX_BUF_LEN 4096
_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
typedef struct {
uint32_t cmd_index: 6; ///< Command index
uint32_t response_expect: 1; ///< set if response is expected
uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected
uint32_t check_response_crc: 1; ///< set if controller should check response CRC
uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected
uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected)
uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected)
uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer
uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete
uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer
uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1)
uint32_t card_num: 5; ///< card number
uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers
uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device
uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device
uint32_t enable_boot: 1; ///< set for mandatory boot mode
uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern
uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot)
uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation
uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only)
uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register
uint32_t reserved: 1;
uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared.
} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values
_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
typedef volatile struct {
union {
struct {
uint32_t controller_reset: 1;
uint32_t fifo_reset: 1;
uint32_t dma_reset: 1;
uint32_t reserved1: 1;
uint32_t int_enable: 1;
uint32_t dma_enable: 1;
uint32_t read_wait: 1;
uint32_t send_irq_response: 1;
uint32_t abort_read_data: 1;
uint32_t send_ccsd: 1;
uint32_t send_auto_stop_ccsd: 1;
uint32_t ceata_device_interrupt_status: 1;
uint32_t reserved2: 4;
uint32_t card_voltage_a: 4;
uint32_t card_voltage_b: 4;
uint32_t enable_od_pullup: 1;
uint32_t use_internal_dma: 1;
uint32_t reserved3: 6;
};
uint32_t val;
} ctrl;
uint32_t pwren; ///< 1: enable power to card, 0: disable power to card
union {
struct {
uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
};
uint32_t val;
} clkdiv;
union {
struct {
uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3
uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3
uint32_t reserved: 28;
};
uint32_t val;
} clksrc;
union {
struct {
uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock
uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating
};
uint32_t val;
} clkena;
union {
struct {
uint32_t response: 8; ///< response timeout, in card output clock cycles
uint32_t data: 24; ///< data read timeout, in card output clock cycles
};
uint32_t val;
} tmout;
union {
struct {
uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode
uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored)
};
uint32_t val;
} ctype;
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t : 16;
uint32_t bytcnt; ///< number of bytes to be transferred
union {
struct {
uint32_t cd: 1; ///< Card detect interrupt enable
uint32_t re: 1; ///< Response error interrupt enable
uint32_t cmd_done: 1; ///< Command done interrupt enable
uint32_t dto: 1; ///< Data transfer over interrupt enable
uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable
uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable
uint32_t rcrc: 1; ///< Response CRC error interrupt enable
uint32_t dcrc: 1; ///< Data CRC error interrupt enable
uint32_t rto: 1; ///< Response timeout interrupt enable
uint32_t drto: 1; ///< Data read timeout interrupt enable
uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable
uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable
uint32_t hle: 1; ///< Hardware locked write error interrupt enable
uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable
uint32_t acd: 1; ///< Auto command done interrupt enable
uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable
uint32_t sdio: 16; ///< SDIO interrupt enable
};
uint32_t val;
} intmask;
uint32_t cmdarg; ///< Command argument to be passed to card
sdmmc_hw_cmd_t cmd;
uint32_t resp[4]; ///< Response from card
union {
struct {
uint32_t cd: 1; ///< Card detect interrupt masked status
uint32_t re: 1; ///< Response error interrupt masked status
uint32_t cmd_done: 1; ///< Command done interrupt masked status
uint32_t dto: 1; ///< Data transfer over interrupt masked status
uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status
uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status
uint32_t rcrc: 1; ///< Response CRC error interrupt masked status
uint32_t dcrc: 1; ///< Data CRC error interrupt masked status
uint32_t rto: 1; ///< Response timeout interrupt masked status
uint32_t drto: 1; ///< Data read timeout interrupt masked status
uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status
uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status
uint32_t hle: 1; ///< Hardware locked write error interrupt masked status
uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status
uint32_t acd: 1; ///< Auto command done interrupt masked status
uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status
uint32_t sdio: 16; ///< SDIO interrupt masked status
};
uint32_t val;
} mintsts;
union {
struct {
uint32_t cd: 1; ///< Card detect raw interrupt status
uint32_t re: 1; ///< Response error raw interrupt status
uint32_t cmd_done: 1; ///< Command done raw interrupt status
uint32_t dto: 1; ///< Data transfer over raw interrupt status
uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status
uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status
uint32_t rcrc: 1; ///< Response CRC error raw interrupt status
uint32_t dcrc: 1; ///< Data CRC error raw interrupt status
uint32_t rto: 1; ///< Response timeout raw interrupt status
uint32_t drto: 1; ///< Data read timeout raw interrupt status
uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status
uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status
uint32_t hle: 1; ///< Hardware locked write error raw interrupt status
uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status
uint32_t acd: 1; ///< Auto command done raw interrupt status
uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status
uint32_t sdio: 16; ///< SDIO raw interrupt status
};
uint32_t val;
} rintsts; ///< interrupts can be cleared by writing this register
union {
struct {
uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level
uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level
uint32_t fifo_empty: 1; ///< FIFO is empty
uint32_t fifo_full: 1; ///< FIFO is full
uint32_t cmd_fsm_state: 4; ///< command FSM state
uint32_t data3_status: 1; ///< this bit reads 1 if card is present
uint32_t data_busy: 1; ///< this bit reads 1 if card is busy
uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy
uint32_t response_index: 6; ///< index of the previous response
uint32_t fifo_count: 13; ///< number of filled locations in the FIFO
uint32_t dma_ack: 1; ///< DMA acknowledge signal
uint32_t dma_req: 1; ///< DMA request signal
};
uint32_t val;
} status;
union {
struct {
uint32_t tx_watermark: 12; ///< FIFO TX watermark level
uint32_t reserved1: 4;
uint32_t rx_watermark: 12; ///< FIFO RX watermark level
uint32_t dw_dma_mts: 3;
uint32_t reserved2: 1;
};
uint32_t val;
} fifoth;
union {
struct {
uint32_t cards: 2; ///< bit N reads 1 if card N is present
uint32_t reserved: 30;
};
uint32_t val;
} cdetect;
union {
struct {
uint32_t card0: 2; ///< bit N reads 1 if card N is write protected
uint32_t reserved: 30;
};
uint32_t val;
} wrtprt;
uint32_t gpio; ///< unused
uint32_t tcbcnt; ///< transferred (to card) byte count
uint32_t tbbcnt; ///< transferred from host to FIFO byte count
union {
struct {
uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms
uint32_t reserved: 8;
};
} debnce;
uint32_t usrid; ///< user ID
uint32_t verid; ///< IP block version
uint32_t hcon; ///< compile-time IP configuration
uint32_t uhs; ///< TBD
union {
struct {
uint32_t cards: 2; ///< bit N resets card N, active low
uint32_t reserved: 30;
};
} rst_n;
uint32_t reserved_7c;
union {
struct {
uint32_t sw_reset: 1; ///< set to reset DMA controller
uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers
uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors
uint32_t enable: 1; ///< set to enable IDMAC
uint32_t pbl: 3; ///< programmable burst length
uint32_t reserved: 21;
};
uint32_t val;
} bmod;
uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state
sdmmc_desc_t* dbaddr; ///< descriptor list base
union {
struct {
uint32_t ti: 1; ///< transmit interrupt status
uint32_t ri: 1; ///< receive interrupt status
uint32_t fbe: 1; ///< fatal bus error
uint32_t reserved1: 1;
uint32_t du: 1; ///< descriptor unavailable
uint32_t ces: 1; ///< card error summary
uint32_t reserved2: 2;
uint32_t nis: 1; ///< normal interrupt summary
uint32_t fbe_code: 3; ///< code of fatal bus error
uint32_t fsm: 4; ///< DMAC FSM state
uint32_t reserved3: 15;
};
uint32_t val;
} idsts;
union {
struct {
uint32_t ti: 1; ///< transmit interrupt enable
uint32_t ri: 1; ///< receive interrupt enable
uint32_t fbe: 1; ///< fatal bus error interrupt enable
uint32_t reserved1: 1;
uint32_t du: 1; ///< descriptor unavailable interrupt enable
uint32_t ces: 1; ///< card error interrupt enable
uint32_t reserved2: 2;
uint32_t ni: 1; ///< normal interrupt interrupt enable
uint32_t ai: 1; ///< abnormal interrupt enable
uint32_t reserved3: 22;
};
uint32_t val;
} idinten;
uint32_t dscaddr; ///< current host descriptor address
uint32_t dscaddrl; ///< unused
uint32_t dscaddru; ///< unused
uint32_t bufaddrl; ///< unused
uint32_t bufaddru; ///< unused
uint32_t reserved_a8[22];
uint32_t cardthrctl;
uint32_t back_end_power;
uint32_t uhs_reg_ext;
uint32_t emmc_ddr_reg;
uint32_t enable_shift;
uint32_t reserved_114[443];
union {
struct {
uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270)
uint32_t phase_din: 3; ///< phase of data input clock
uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral
uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
};
uint32_t val;
} clock;
} sdmmc_dev_t;
extern sdmmc_dev_t SDMMC;
_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure");
#endif //_SOC_SDMMC_STRUCT_H_

3
tools/sdk/include/esp32/soc/soc.h
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@ -153,11 +153,12 @@
#define DR_REG_FRC_TIMER_BASE 0x3ff47000
#define DR_REG_RTCCNTL_BASE 0x3ff48000
#define DR_REG_RTCIO_BASE 0x3ff48400
#define DR_REG_SENS_BASE 0x3ff48800
#define DR_REG_SENS_BASE 0x3ff48800
#define DR_REG_IO_MUX_BASE 0x3ff49000
#define DR_REG_RTCMEM0_BASE 0x3ff61000
#define DR_REG_RTCMEM1_BASE 0x3ff62000
#define DR_REG_RTCMEM2_BASE 0x3ff63000
#define DR_REG_SYSCON_BASE 0x3ff66000
#define DR_REG_HINF_BASE 0x3ff4B000
#define DR_REG_UHCI1_BASE 0x3ff4C000
#define DR_REG_I2S_BASE 0x3ff4F000

20
tools/sdk/include/esp32/soc/spi_reg.h
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@ -133,12 +133,8 @@
#define SPI_FLASH_PER_S 16
#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: [31:8]:address to slave [7:0]:Reserved.*/
#define SPI_USR_ADDR_VALUE 0xFFFFFFFF
#define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF
#define SPI_USR_ADDR_VALUE_S 0
//The CSV actually is wrong here. It indicates that the lower 8 bits of this register are reserved. This is not true,
//all 32 bits of SPI_ADDR_REG are usable/used.
#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */
@ -601,19 +597,19 @@
#define SPI_CK_IDLE_EDGE_M (BIT(29))
#define SPI_CK_IDLE_EDGE_V 0x1
#define SPI_CK_IDLE_EDGE_S 29
/* SPI_MASTER_CK_SEL : R/W ;bitpos:[15:11] ;default: 5'b0 ; */
/* SPI_MASTER_CK_SEL : R/W ;bitpos:[13:11] ;default: 3'b0 ; */
/*description: In the master mode spi cs line is enable as spi clk it is combined
with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/
#define SPI_MASTER_CK_SEL 0x0000001F
#define SPI_MASTER_CK_SEL 0x00000007
#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S))
#define SPI_MASTER_CK_SEL_V 0x1F
#define SPI_MASTER_CK_SEL_V 0x07
#define SPI_MASTER_CK_SEL_S 11
/* SPI_MASTER_CS_POL : R/W ;bitpos:[10:6] ;default: 5'b0 ; */
/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */
/*description: In the master mode the bits are the polarity of spi cs line
the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
#define SPI_MASTER_CS_POL 0x0000001F
#define SPI_MASTER_CS_POL 0x00000007
#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
#define SPI_MASTER_CS_POL_V 0x1F
#define SPI_MASTER_CS_POL_V 0x7
#define SPI_MASTER_CS_POL_S 6
/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: 1: spi clk out disable 0: spi clk out enable*/

21
tools/sdk/include/esp32/soc/spi_struct.h
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@ -36,13 +36,7 @@ typedef volatile struct {
};
uint32_t val;
} cmd;
union {
struct {
uint32_t reserved : 8;
uint32_t usr_addr_value:24; /*[31:8]:address to slave [7:0]:Reserved.*/
};
uint32_t val;
} addr;
uint32_t addr; /*addr to slave / from master */
union {
struct {
uint32_t reserved0: 10; /*reserved*/
@ -177,9 +171,10 @@ typedef volatile struct {
uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/
uint32_t reserved3: 2; /*reserved*/
uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/
uint32_t master_cs_pol: 5; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
uint32_t master_ck_sel: 5; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/
uint32_t reserved16: 13; /*reserved*/
uint32_t master_cs_pol: 3; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
uint32_t reserved9: 2; /*reserved*/
uint32_t master_ck_sel: 3; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/
uint32_t reserved14: 15; /*reserved*/
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/
uint32_t reserved31: 1; /*reserved*/
@ -193,7 +188,11 @@ typedef volatile struct {
uint32_t rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/
uint32_t wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/
uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/
uint32_t rd_buf_inten: 1; /*The interrupt enable bit for the completion of read-buffer operation in the slave mode.*/
uint32_t wr_buf_inten: 1; /*The interrupt enable bit for the completion of write-buffer operation in the slave mode.*/
uint32_t rd_sta_inten: 1; /*The interrupt enable bit for the completion of read-status operation in the slave mode.*/
uint32_t wr_sta_inten: 1; /*The interrupt enable bit for the completion of write-status operation in the slave mode.*/
uint32_t trans_inten: 1; /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/
uint32_t reserved12: 5; /*reserved*/
uint32_t last_command: 3; /*In the slave mode it is the value of command.*/

294
tools/sdk/include/esp32/soc/syscon_reg.h Normal file
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@ -0,0 +1,294 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SYSCON_REG_H_
#define _SOC_SYSCON_REG_H_
#include "soc.h"
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
/* SYSCON_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: */
#define SYSCON_QUICK_CLK_CHNG (BIT(13))
#define SYSCON_QUICK_CLK_CHNG_M (BIT(13))
#define SYSCON_QUICK_CLK_CHNG_V 0x1
#define SYSCON_QUICK_CLK_CHNG_S 13
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define SYSCON_RST_TICK_CNT (BIT(12))
#define SYSCON_RST_TICK_CNT_M (BIT(12))
#define SYSCON_RST_TICK_CNT_V 0x1
#define SYSCON_RST_TICK_CNT_S 12
/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define SYSCON_CLK_EN (BIT(11))
#define SYSCON_CLK_EN_M (BIT(11))
#define SYSCON_CLK_EN_V 0x1
#define SYSCON_CLK_EN_S 11
/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define SYSCON_CLK_320M_EN (BIT(10))
#define SYSCON_CLK_320M_EN_M (BIT(10))
#define SYSCON_CLK_320M_EN_V 0x1
#define SYSCON_CLK_320M_EN_S 10
/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
/*description: */
#define SYSCON_PRE_DIV_CNT 0x000003FF
#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
#define SYSCON_PRE_DIV_CNT_V 0x3FF
#define SYSCON_PRE_DIV_CNT_S 0
#define SYSCON_XTAL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4)
/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
/*description: */
#define SYSCON_XTAL_TICK_NUM 0x000000FF
#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
#define SYSCON_XTAL_TICK_NUM_V 0xFF
#define SYSCON_XTAL_TICK_NUM_S 0
#define SYSCON_PLL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x8)
/* SYSCON_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */
/*description: */
#define SYSCON_PLL_TICK_NUM 0x000000FF
#define SYSCON_PLL_TICK_NUM_M ((SYSCON_PLL_TICK_NUM_V)<<(SYSCON_PLL_TICK_NUM_S))
#define SYSCON_PLL_TICK_NUM_V 0xFF
#define SYSCON_PLL_TICK_NUM_S 0
#define SYSCON_CK8M_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0xC)
/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */
/*description: */
#define SYSCON_CK8M_TICK_NUM 0x000000FF
#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
#define SYSCON_CK8M_TICK_NUM_V 0xFF
#define SYSCON_CK8M_TICK_NUM_S 0
#define SYSCON_SARADC_CTRL_REG (DR_REG_SYSCON_BASE + 0x10)
/* SYSCON_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data
is from GPIO matrix*/
#define SYSCON_SARADC_DATA_TO_I2S (BIT(26))
#define SYSCON_SARADC_DATA_TO_I2S_M (BIT(26))
#define SYSCON_SARADC_DATA_TO_I2S_V 0x1
#define SYSCON_SARADC_DATA_TO_I2S_S 26
/* SYSCON_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
in this case the resolution should not be larger than 11 bits.*/
#define SYSCON_SARADC_DATA_SAR_SEL (BIT(25))
#define SYSCON_SARADC_DATA_SAR_SEL_M (BIT(25))
#define SYSCON_SARADC_DATA_SAR_SEL_V 0x1
#define SYSCON_SARADC_DATA_SAR_SEL_S 25
/* SYSCON_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_V 0x1
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_S 24
/* SYSCON_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_V 0x1
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_S 23
/* SYSCON_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define SYSCON_SARADC_SAR2_PATT_LEN 0x0000000F
#define SYSCON_SARADC_SAR2_PATT_LEN_M ((SYSCON_SARADC_SAR2_PATT_LEN_V)<<(SYSCON_SARADC_SAR2_PATT_LEN_S))
#define SYSCON_SARADC_SAR2_PATT_LEN_V 0xF
#define SYSCON_SARADC_SAR2_PATT_LEN_S 19
/* SYSCON_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define SYSCON_SARADC_SAR1_PATT_LEN 0x0000000F
#define SYSCON_SARADC_SAR1_PATT_LEN_M ((SYSCON_SARADC_SAR1_PATT_LEN_V)<<(SYSCON_SARADC_SAR1_PATT_LEN_S))
#define SYSCON_SARADC_SAR1_PATT_LEN_V 0xF
#define SYSCON_SARADC_SAR1_PATT_LEN_S 15
/* SYSCON_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
/*description: SAR clock divider*/
#define SYSCON_SARADC_SAR_CLK_DIV 0x000000FF
#define SYSCON_SARADC_SAR_CLK_DIV_M ((SYSCON_SARADC_SAR_CLK_DIV_V)<<(SYSCON_SARADC_SAR_CLK_DIV_S))
#define SYSCON_SARADC_SAR_CLK_DIV_V 0xFF
#define SYSCON_SARADC_SAR_CLK_DIV_S 7
/* SYSCON_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define SYSCON_SARADC_SAR_CLK_GATED (BIT(6))
#define SYSCON_SARADC_SAR_CLK_GATED_M (BIT(6))
#define SYSCON_SARADC_SAR_CLK_GATED_V 0x1
#define SYSCON_SARADC_SAR_CLK_GATED_S 6
/* SYSCON_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/
#define SYSCON_SARADC_SAR_SEL (BIT(5))
#define SYSCON_SARADC_SAR_SEL_M (BIT(5))
#define SYSCON_SARADC_SAR_SEL_V 0x1
#define SYSCON_SARADC_SAR_SEL_S 5
/* SYSCON_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
/*description: 0: single mode 1: double mode 2: alternate mode*/
#define SYSCON_SARADC_WORK_MODE 0x00000003
#define SYSCON_SARADC_WORK_MODE_M ((SYSCON_SARADC_WORK_MODE_V)<<(SYSCON_SARADC_WORK_MODE_S))
#define SYSCON_SARADC_WORK_MODE_V 0x3
#define SYSCON_SARADC_WORK_MODE_S 3
/* SYSCON_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */
/*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled
by PWDET CTRL*/
#define SYSCON_SARADC_SAR2_MUX (BIT(2))
#define SYSCON_SARADC_SAR2_MUX_M (BIT(2))
#define SYSCON_SARADC_SAR2_MUX_V 0x1
#define SYSCON_SARADC_SAR2_MUX_S 2
/* SYSCON_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define SYSCON_SARADC_START (BIT(1))
#define SYSCON_SARADC_START_M (BIT(1))
#define SYSCON_SARADC_START_V 0x1
#define SYSCON_SARADC_START_S 1
/* SYSCON_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define SYSCON_SARADC_START_FORCE (BIT(0))
#define SYSCON_SARADC_START_FORCE_M (BIT(0))
#define SYSCON_SARADC_START_FORCE_V 0x1
#define SYSCON_SARADC_START_FORCE_S 0
#define SYSCON_SARADC_CTRL2_REG (DR_REG_SYSCON_BASE + 0x14)
/* SYSCON_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
#define SYSCON_SARADC_SAR2_INV (BIT(10))
#define SYSCON_SARADC_SAR2_INV_M (BIT(10))
#define SYSCON_SARADC_SAR2_INV_V 0x1
#define SYSCON_SARADC_SAR2_INV_S 10
/* SYSCON_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
#define SYSCON_SARADC_SAR1_INV (BIT(9))
#define SYSCON_SARADC_SAR1_INV_M (BIT(9))
#define SYSCON_SARADC_SAR1_INV_V 0x1
#define SYSCON_SARADC_SAR1_INV_S 9
/* SYSCON_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
/*description: max conversion number*/
#define SYSCON_SARADC_MAX_MEAS_NUM 0x000000FF
#define SYSCON_SARADC_MAX_MEAS_NUM_M ((SYSCON_SARADC_MAX_MEAS_NUM_V)<<(SYSCON_SARADC_MAX_MEAS_NUM_S))
#define SYSCON_SARADC_MAX_MEAS_NUM_V 0xFF
#define SYSCON_SARADC_MAX_MEAS_NUM_S 1
/* SYSCON_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define SYSCON_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define SYSCON_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define SYSCON_SARADC_MEAS_NUM_LIMIT_V 0x1
#define SYSCON_SARADC_MEAS_NUM_LIMIT_S 0
#define SYSCON_SARADC_FSM_REG (DR_REG_SYSCON_BASE + 0x18)
/* SYSCON_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
/*description: sample cycles*/
#define SYSCON_SARADC_SAMPLE_CYCLE 0x000000FF
#define SYSCON_SARADC_SAMPLE_CYCLE_M ((SYSCON_SARADC_SAMPLE_CYCLE_V)<<(SYSCON_SARADC_SAMPLE_CYCLE_S))
#define SYSCON_SARADC_SAMPLE_CYCLE_V 0xFF
#define SYSCON_SARADC_SAMPLE_CYCLE_S 24
/* SYSCON_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */
/*description: */
#define SYSCON_SARADC_START_WAIT 0x000000FF
#define SYSCON_SARADC_START_WAIT_M ((SYSCON_SARADC_START_WAIT_V)<<(SYSCON_SARADC_START_WAIT_S))
#define SYSCON_SARADC_START_WAIT_V 0xFF
#define SYSCON_SARADC_START_WAIT_S 16
/* SYSCON_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */
/*description: */
#define SYSCON_SARADC_STANDBY_WAIT 0x000000FF
#define SYSCON_SARADC_STANDBY_WAIT_M ((SYSCON_SARADC_STANDBY_WAIT_V)<<(SYSCON_SARADC_STANDBY_WAIT_S))
#define SYSCON_SARADC_STANDBY_WAIT_V 0xFF
#define SYSCON_SARADC_STANDBY_WAIT_S 8
/* SYSCON_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
/*description: */
#define SYSCON_SARADC_RSTB_WAIT 0x000000FF
#define SYSCON_SARADC_RSTB_WAIT_M ((SYSCON_SARADC_RSTB_WAIT_V)<<(SYSCON_SARADC_RSTB_WAIT_S))
#define SYSCON_SARADC_RSTB_WAIT_V 0xFF
#define SYSCON_SARADC_RSTB_WAIT_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x1C)
/* SYSCON_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB1_M ((SYSCON_SARADC_SAR1_PATT_TAB1_V)<<(SYSCON_SARADC_SAR1_PATT_TAB1_S))
#define SYSCON_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB1_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x20)
/* SYSCON_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB2_M ((SYSCON_SARADC_SAR1_PATT_TAB2_V)<<(SYSCON_SARADC_SAR1_PATT_TAB2_S))
#define SYSCON_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB2_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x24)
/* SYSCON_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB3_M ((SYSCON_SARADC_SAR1_PATT_TAB3_V)<<(SYSCON_SARADC_SAR1_PATT_TAB3_S))
#define SYSCON_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB3_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x28)
/* SYSCON_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB4_M ((SYSCON_SARADC_SAR1_PATT_TAB4_V)<<(SYSCON_SARADC_SAR1_PATT_TAB4_S))
#define SYSCON_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB4_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x2C)
/* SYSCON_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB1_M ((SYSCON_SARADC_SAR2_PATT_TAB1_V)<<(SYSCON_SARADC_SAR2_PATT_TAB1_S))
#define SYSCON_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB1_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x30)
/* SYSCON_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB2_M ((SYSCON_SARADC_SAR2_PATT_TAB2_V)<<(SYSCON_SARADC_SAR2_PATT_TAB2_S))
#define SYSCON_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB2_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x34)
/* SYSCON_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB3_M ((SYSCON_SARADC_SAR2_PATT_TAB3_V)<<(SYSCON_SARADC_SAR2_PATT_TAB3_S))
#define SYSCON_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB3_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x38)
/* SYSCON_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB4_M ((SYSCON_SARADC_SAR2_PATT_TAB4_V)<<(SYSCON_SARADC_SAR2_PATT_TAB4_S))
#define SYSCON_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB4_S 0
#define SYSCON_APLL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x3C)
/* SYSCON_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */
/*description: */
#define SYSCON_APLL_TICK_NUM 0x000000FF
#define SYSCON_APLL_TICK_NUM_M ((SYSCON_APLL_TICK_NUM_V)<<(SYSCON_APLL_TICK_NUM_S))
#define SYSCON_APLL_TICK_NUM_V 0xFF
#define SYSCON_APLL_TICK_NUM_S 0
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x7C)
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */
/*description: */
#define SYSCON_DATE 0xFFFFFFFF
#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
#define SYSCON_DATE_V 0xFFFFFFFF
#define SYSCON_DATE_S 0
#endif /*_SOC_SYSCON_REG_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SYSCON_STRUCT_H_
#define _SOC_SYSCON_STRUCT_H_
typedef struct {
union {
struct {
volatile uint32_t pre_div: 10;
volatile uint32_t clk_320m_en: 1;
volatile uint32_t clk_en: 1;
volatile uint32_t rst_tick: 1;
volatile uint32_t quick_clk_chng: 1;
volatile uint32_t reserved14: 18;
};
volatile uint32_t val;
}clk_conf;
union {
struct {
volatile uint32_t xtal_tick: 8;
volatile uint32_t reserved8: 24;
};
volatile uint32_t val;
}xtal_tick_conf;
union {
struct {
volatile uint32_t pll_tick: 8;
volatile uint32_t reserved8: 24;
};
volatile uint32_t val;
}pll_tick_conf;
union {
struct {
volatile uint32_t ck8m_tick: 8;
volatile uint32_t reserved8: 24;
};
volatile uint32_t val;
}ck8m_tick_conf;
union {
struct {
volatile uint32_t start_force: 1;
volatile uint32_t start: 1;
volatile uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/
volatile uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
volatile uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
volatile uint32_t sar_clk_gated: 1;
volatile uint32_t sar_clk_div: 8; /*SAR clock divider*/
volatile uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
volatile uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
volatile uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
volatile uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
volatile uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
volatile uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
volatile uint32_t reserved27: 5;
};
volatile uint32_t val;
}saradc_ctrl;
union {
struct {
volatile uint32_t meas_num_limit: 1;
volatile uint32_t max_meas_num: 8; /*max conversion number*/
volatile uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
volatile uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
volatile uint32_t reserved11: 21;
};
volatile uint32_t val;
}saradc_ctrl2;
union {
struct {
volatile uint32_t rstb_wait: 8;
volatile uint32_t standby_wait: 8;
volatile uint32_t start_wait: 8;
volatile uint32_t sample_cycle: 8; /*sample cycles*/
};
volatile uint32_t val;
}saradc_fsm;
volatile uint32_t saradc_sar1_patt_tab1; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
volatile uint32_t saradc_sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
volatile uint32_t saradc_sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
volatile uint32_t saradc_sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
volatile uint32_t saradc_sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
volatile uint32_t saradc_sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
volatile uint32_t saradc_sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
volatile uint32_t saradc_sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
union {
struct {
volatile uint32_t apll_tick: 8;
volatile uint32_t reserved8: 24;
};
volatile uint32_t val;
}apll_tick_conf;
volatile uint32_t reserved_40;
volatile uint32_t reserved_44;
volatile uint32_t reserved_48;
volatile uint32_t reserved_4c;
volatile uint32_t reserved_50;
volatile uint32_t reserved_54;
volatile uint32_t reserved_58;
volatile uint32_t reserved_5c;
volatile uint32_t reserved_60;
volatile uint32_t reserved_64;
volatile uint32_t reserved_68;
volatile uint32_t reserved_6c;
volatile uint32_t reserved_70;
volatile uint32_t reserved_74;
volatile uint32_t reserved_78;
volatile uint32_t date; /**/
} syscon_dev_t;
#endif /* _SOC_SYSCON_STRUCT_H_ */