update IDF libraries and includes

tools/sdk/include/esp32/soc/cpu.h

@@ -15,6 +15,9 @@
 #ifndef _SOC_CPU_H
 #define _SOC_CPU_H
 
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
 #include "xtensa/corebits.h"
 
 /* C macros for xtensa special register read/write/exchange */

tools/sdk/include/esp32/soc/rmt_struct.h

@@ -225,4 +225,22 @@ typedef volatile struct {
     uint32_t date;                                      /*This is the version register.*/
 } rmt_dev_t;
 extern rmt_dev_t RMT;
+
+//Allow access to RMT memory using RMTMEM.chan[0].data[8]
+typedef volatile struct {
+    struct {
+        union {
+            struct {
+                uint32_t level1:       1;
+                uint32_t duration1:    15;
+                uint32_t level0:       1;
+                uint32_t duration0:    15;
+
+            };
+            uint32_t val;
+        } data[64];
+    } chan[8];
+} rmt_mem_t;
+extern rmt_mem_t RMTMEM;
+
 #endif  /* _SOC_RMT_STRUCT_H_ */

tools/sdk/include/esp32/soc/rtc_cntl_reg.h

@@ -14,6 +14,9 @@
 #ifndef _SOC_RTC_CNTL_REG_H_
 #define _SOC_RTC_CNTL_REG_H_
 
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+
 
 #include "soc.h"
 #define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0)

tools/sdk/include/esp32/soc/timer_group_reg.h

@@ -15,6 +15,16 @@
 #define __TIMG_REG_H__
 #include "soc.h"
 
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+
 #define REG_TIMG_BASE(i)       (DR_REG_TIMERGROUP0_BASE + i*0x1000)
 #define TIMG_T0CONFIG_REG(i)          (REG_TIMG_BASE(i) + 0x0000)
 /* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */