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IDF release/v4.0 08219f3cf

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me-no-dev
2020-01-25 14:51:58 +00:00
parent 8c723be135
commit 41ba143063
858 changed files with 37940 additions and 49396 deletions
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0
tools/sdk/include/esp32/esp_brownout.h → tools/sdk/include/esp32/esp32/brownout.h
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0
tools/sdk/include/esp32/esp_cache_err_int.h → tools/sdk/include/esp32/esp32/cache_err_int.h
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87
tools/sdk/include/esp32/esp32/clk.h Normal file
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@ -0,0 +1,87 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
/**
* @file esp32/clk.h
*
* This file contains declarations of clock related functions.
*/
/**
* @brief Get the calibration value of RTC slow clock
*
* The value is in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get();
/**
* @brief Update the calibration value of RTC slow clock
*
* The value has to be in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
* This value is used by timekeeping functions (such as gettimeofday) to
* calculate current time based on RTC counter value.
* @param value calibration value obtained using rtc_clk_cal
*/
void esp_clk_slowclk_cal_set(uint32_t value);
/**
* @brief Return current CPU clock frequency
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return CPU clock frequency, in Hz
*/
int esp_clk_cpu_freq(void);
/**
* @brief Return current APB clock frequency
*
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return APB clock frequency, in Hz
*/
int esp_clk_apb_freq(void);
/**
* @brief Return frequency of the main XTAL
*
* Frequency of the main XTAL can be either auto-detected or set at compile
* time (see CONFIG_ESP32_XTAL_FREQ_SEL sdkconfig option). In both cases, this
* function returns the actual value at run time.
*
* @return XTAL frequency, in Hz
*/
int esp_clk_xtal_freq(void);
/**
* @brief Read value of RTC counter, converting it to microseconds
* @attention The value returned by this function may change abruptly when
* calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
* function. This should not happen unless application calls esp_clk_slowclk_cal_set.
* In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time();

0
tools/sdk/include/esp32/esp_dport_access.h → tools/sdk/include/esp32/esp32/dport_access.h
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152
tools/sdk/include/esp32/esp32/himem.h Normal file
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@ -0,0 +1,152 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stddef.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
//Opaque pointers as handles for ram/range data
typedef struct esp_himem_ramdata_t *esp_himem_handle_t;
typedef struct esp_himem_rangedata_t *esp_himem_rangehandle_t;
//ESP32 MMU block size
#define ESP_HIMEM_BLKSZ (0x8000)
#define ESP_HIMEM_MAPFLAG_RO 1 /*!< Indicates that a mapping will only be read from. Note that this is unused for now. */
/**
* @brief Allocate a block in high memory
*
* @param size Size of the to-be-allocated block, in bytes. Note that this needs to be
* a multiple of the external RAM mmu block size (32K).
* @param[out] handle_out Handle to be returned
* @returns - ESP_OK if succesful
* - ESP_ERR_NO_MEM if out of memory
* - ESP_ERR_INVALID_SIZE if size is not a multiple of 32K
*/
esp_err_t esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out);
/**
* @brief Allocate a memory region to map blocks into
*
* This allocates a contiguous CPU memory region that can be used to map blocks
* of physical memory into.
*
* @param size Size of the range to be allocated. Note this needs to be a multiple of
* the external RAM mmu block size (32K).
* @param[out] handle_out Handle to be returned
* @returns - ESP_OK if succesful
* - ESP_ERR_NO_MEM if out of memory or address space
* - ESP_ERR_INVALID_SIZE if size is not a multiple of 32K
*/
esp_err_t esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t *handle_out);
/**
* @brief Map a block of high memory into the CPUs address space
*
* This effectively makes the block available for read/write operations.
*
* @note The region to be mapped needs to have offsets and sizes that are aligned to the
* SPI RAM MMU block size (32K)
*
* @param handle Handle to the block of memory, as given by esp_himem_alloc
* @param range Range handle to map the memory in
* @param ram_offset Offset into the block of physical memory of the block to map
* @param range_offset Offset into the address range where the block will be mapped
* @param len Length of region to map
* @param flags One of ESP_HIMEM_MAPFLAG_*
* @param[out] out_ptr Pointer to variable to store resulting memory pointer in
* @returns - ESP_OK if the memory could be mapped
* - ESP_ERR_INVALID_ARG if offset, range or len aren't MMU-block-aligned (32K)
* - ESP_ERR_INVALID_SIZE if the offsets/lengths don't fit in the allocated memory or range
* - ESP_ERR_INVALID_STATE if a block in the selected ram offset/length is already mapped, or
* if a block in the selected range offset/length already has a mapping.
*/
esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range, size_t ram_offset, size_t range_offset, size_t len, int flags, void **out_ptr);
/**
* @brief Free a block of physical memory
*
* This clears out the associated handle making the memory available for re-allocation again.
* This will only succeed if none of the memory blocks currently have a mapping.
*
* @param handle Handle to the block of memory, as given by esp_himem_alloc
* @returns - ESP_OK if the memory is succesfully freed
* - ESP_ERR_INVALID_ARG if the handle still is (partially) mapped
*/
esp_err_t esp_himem_free(esp_himem_handle_t handle);
/**
* @brief Free a mapping range
*
* This clears out the associated handle making the range available for re-allocation again.
* This will only succeed if none of the range blocks currently are used for a mapping.
*
* @param handle Handle to the range block, as given by esp_himem_alloc_map_range
* @returns - ESP_OK if the memory is succesfully freed
* - ESP_ERR_INVALID_ARG if the handle still is (partially) mapped to
*/
esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle);
/**
* @brief Unmap a region
*
* @param range Range handle
* @param ptr Pointer returned by esp_himem_map
* @param len Length of the block to be unmapped. Must be aligned to the SPI RAM MMU blocksize (32K)
* @returns - ESP_OK if the memory is succesfully unmapped,
* - ESP_ERR_INVALID_ARG if ptr or len are invalid.
*/
esp_err_t esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, size_t len);
/**
* @brief Get total amount of memory under control of himem API
*
* @returns Amount of memory, in bytes
*/
size_t esp_himem_get_phys_size();
/**
* @brief Get free amount of memory under control of himem API
*
* @returns Amount of free memory, in bytes
*/
size_t esp_himem_get_free_size();
/**
* @brief Get amount of SPI memory address space needed for bankswitching
*
* @note This is also weakly defined in esp32/spiram.c and returns 0 there, so
* if no other function in this file is used, no memory is reserved.
*
* @returns Amount of reserved area, in bytes
*/
size_t esp_himem_reserved_area_size();
#ifdef __cplusplus
}
#endif

2
tools/sdk/include/esp32/esp32/pm.h
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@ -31,9 +31,7 @@ extern "C" {
* Pass a pointer to this structure as an argument to esp_pm_configure function.
*/
typedef struct {
rtc_cpu_freq_t max_cpu_freq __attribute__((deprecated)); /*!< Maximum CPU frequency to use. Deprecated, use max_freq_mhz instead. */
int max_freq_mhz; /*!< Maximum CPU frequency, in MHz */
rtc_cpu_freq_t min_cpu_freq __attribute__((deprecated)); /*!< Minimum CPU frequency to use when no frequency locks are taken. Deprecated, use min_freq_mhz instead. */
int min_freq_mhz; /*!< Minimum CPU frequency to use when no locks are taken, in MHz */
bool light_sleep_enable; /*!< Enter light sleep when no locks are taken */
} esp_pm_config_esp32_t;

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tools/sdk/include/esp32/esp32/spiram.h Normal file
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@ -0,0 +1,116 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_SPIRAM_H
#define __ESP_SPIRAM_H
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
typedef enum {
ESP_SPIRAM_SIZE_16MBITS = 0, /*!< SPI RAM size is 16 MBits */
ESP_SPIRAM_SIZE_32MBITS = 1, /*!< SPI RAM size is 32 MBits */
ESP_SPIRAM_SIZE_64MBITS = 2, /*!< SPI RAM size is 64 MBits */
ESP_SPIRAM_SIZE_INVALID, /*!< SPI RAM size is invalid */
} esp_spiram_size_t;
/**
* @brief get SPI RAM size
* @return
* - ESP_SPIRAM_SIZE_INVALID if SPI RAM not enabled or not valid
* - SPI RAM size
*/
esp_spiram_size_t esp_spiram_get_chip_size();
/**
* @brief Initialize spiram interface/hardware. Normally called from cpu_start.c.
*
* @return ESP_OK on success
*/
esp_err_t esp_spiram_init();
/**
* @brief Configure Cache/MMU for access to external SPI RAM.
*
* Normally this function is called from cpu_start, if CONFIG_SPIRAM_BOOT_INIT
* option is enabled. Applications which need to enable SPI RAM at run time
* can disable CONFIG_SPIRAM_BOOT_INIT, and call this function later.
*
* @attention this function must be called with flash cache disabled.
*/
void esp_spiram_init_cache();
/**
* @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
* (in case of a dual-core system) the app CPU is online. This test overwrites the
* memory with crap, so do not call after e.g. the heap allocator has stored important
* stuff in SPI RAM.
*
* @return true on success, false on failed memory test
*/
bool esp_spiram_test();
/**
* @brief Add the initialized SPI RAM to the heap allocator.
*/
esp_err_t esp_spiram_add_to_heapalloc();
/**
* @brief Get the size of the attached SPI RAM chip selected in menuconfig
*
* @return Size in bytes, or 0 if no external RAM chip support compiled in.
*/
size_t esp_spiram_get_size();
/**
* @brief Force a writeback of the data in the SPI RAM cache. This is to be called whenever
* cache is disabled, because disabling cache on the ESP32 discards the data in the SPI
* RAM cache.
*
* This is meant for use from within the SPI flash code.
*/
void esp_spiram_writeback_cache();
/**
* @brief Reserve a pool of internal memory for specific DMA/internal allocations
*
* @param size Size of reserved pool in bytes
*
* @return
* - ESP_OK on success
* - ESP_ERR_NO_MEM when no memory available for pool
*/
esp_err_t esp_spiram_reserve_dma_pool(size_t size);
/**
* @brief If SPI RAM(PSRAM) has been initialized
*
* @return
* - true SPI RAM has been initialized successfully
* - false SPI RAM hasn't been initialized or initialized failed
*/
bool esp_spiram_is_initialized(void);
#endif

37
tools/sdk/include/esp32/esp_assert.h
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@ -1,37 +0,0 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_ASSERT_H__
#define __ESP_ASSERT_H__
#include "assert.h"
/* Assert at compile time if possible, runtime otherwise */
#ifndef __cplusplus
/* __builtin_choose_expr() is only in C, makes this a lot cleaner */
#define TRY_STATIC_ASSERT(CONDITION, MSG) do { \
_Static_assert(__builtin_choose_expr(__builtin_constant_p(CONDITION), (CONDITION), 1), #MSG); \
assert(#MSG && (CONDITION)); \
} while(0)
#else
/* for C++, use __attribute__((error)) - works almost as well as _Static_assert */
#define TRY_STATIC_ASSERT(CONDITION, MSG) do { \
if (__builtin_constant_p(CONDITION) && !(CONDITION)) { \
extern __attribute__((error(#MSG))) void failed_compile_time_assert(void); \
failed_compile_time_assert(); \
} \
assert(#MSG && (CONDITION)); \
} while(0)
#endif /* __cplusplus */
#endif /* __ESP_ASSERT_H__ */

9
tools/sdk/include/esp32/esp_attr.h
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@ -84,4 +84,13 @@
#define _COUNTER_STRINGIFY(COUNTER) #COUNTER
/* Use IDF_DEPRECATED attribute to mark anything deprecated from use in
ESP-IDF's own source code, but not deprecated for external users.
*/
#ifdef IDF_CI_BUILD
#define IDF_DEPRECATED(REASON) __attribute__((deprecated(REASON)))
#else
#define IDF_DEPRECATED(REASON)
#endif
#endif /* __ESP_ATTR_H__ */

89
tools/sdk/include/esp32/esp_clk.h
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@ -1,87 +1,2 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
/**
* @file esp_clk.h
*
* This file contains declarations of clock related functions.
*/
/**
* @brief Get the calibration value of RTC slow clock
*
* The value is in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get();
/**
* @brief Update the calibration value of RTC slow clock
*
* The value has to be in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
* This value is used by timekeeping functions (such as gettimeofday) to
* calculate current time based on RTC counter value.
* @param value calibration value obtained using rtc_clk_cal
*/
void esp_clk_slowclk_cal_set(uint32_t value);
/**
* @brief Return current CPU clock frequency
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return CPU clock frequency, in Hz
*/
int esp_clk_cpu_freq(void);
/**
* @brief Return current APB clock frequency
*
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return APB clock frequency, in Hz
*/
int esp_clk_apb_freq(void);
/**
* @brief Return frequency of the main XTAL
*
* Frequency of the main XTAL can be either auto-detected or set at compile
* time (see CONFIG_ESP32_XTAL_FREQ_SEL sdkconfig option). In both cases, this
* function returns the actual value at run time.
*
* @return XTAL frequency, in Hz
*/
int esp_clk_xtal_freq(void);
/**
* @brief Read value of RTC counter, converting it to microseconds
* @attention The value returned by this function may change abruptly when
* calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
* function. This should not happen unless application calls esp_clk_slowclk_cal_set.
* In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time();
#warning esp_clk.h has been replaced by esp32/clk.h, please include esp32/clk.h instead
#include "esp32/clk.h"

59
tools/sdk/include/esp32/esp_coexist.h
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@ -1,59 +0,0 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_COEXIST_H__
#define __ESP_COEXIST_H__
#include <stdbool.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief coex prefer value
*/
typedef enum {
ESP_COEX_PREFER_WIFI = 0, /*!< Prefer to WiFi, WiFi will have more opportunity to use RF */
ESP_COEX_PREFER_BT, /*!< Prefer to bluetooth, bluetooth will have more opportunity to use RF */
ESP_COEX_PREFER_BALANCE, /*!< Do balance of WiFi and bluetooth */
ESP_COEX_PREFER_NUM, /*!< Prefer value numbers */
} esp_coex_prefer_t;
/**
* @brief Get software coexist version string
*
* @return : version string
*/
const char *esp_coex_version_get(void);
/**
* @brief Set coexist preference of performance
* For example, if prefer to bluetooth, then it will make A2DP(play audio via classic bt)
* more smooth while wifi is runnning something.
* If prefer to wifi, it will do similar things as prefer to bluetooth.
* Default, it prefer to balance.
*
* @param prefer : the prefer enumeration value
* @return : ESP_OK - success, other - failed
*/
esp_err_t esp_coex_preference_set(esp_coex_prefer_t prefer);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_COEXIST_H__ */

59
tools/sdk/include/esp32/esp_coexist_adapter.h
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@ -1,59 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_COEXIST_ADAPTER_H__
#define __ESP_COEXIST_ADAPTER_H__
#include <stdarg.h>
#ifdef __cplusplus
extern "C" {
#endif
#define COEX_ADAPTER_VERSION 0x00000001
#define COEX_ADAPTER_MAGIC 0xDEADBEAF
#define COEX_ADAPTER_FUNCS_TIME_BLOCKING 0xffffffff
typedef struct {
int32_t _version;
void *(* _spin_lock_create)(void);
void (* _spin_lock_delete)(void *lock);
uint32_t (*_int_disable)(void *mux);
void (*_int_enable)(void *mux, uint32_t tmp);
void (*_task_yield_from_isr)(void);
void *(*_semphr_create)(uint32_t max, uint32_t init);
void (*_semphr_delete)(void *semphr);
int32_t (*_semphr_take_from_isr)(void *semphr, void *hptw);
int32_t (*_semphr_give_from_isr)(void *semphr, void *hptw);
int32_t (*_semphr_take)(void *semphr, uint32_t block_time_tick);
int32_t (*_semphr_give)(void *semphr);
int32_t (* _is_in_isr)(void);
void * (* _malloc_internal)(size_t size);
void (* _free)(void *p);
void (* _timer_disarm)(void *timer);
void (* _timer_done)(void *ptimer);
void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg);
void (* _timer_arm_us)(void *ptimer, uint32_t us, bool repeat);
int64_t (* _esp_timer_get_time)(void);
int32_t _magic;
} coex_adapter_funcs_t;
extern coex_adapter_funcs_t g_coex_adapter_funcs;
#ifdef __cplusplus
}
#endif
#endif /* __ESP_COEXIST_ADAPTER_H__ */

177
tools/sdk/include/esp32/esp_coexist_internal.h
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@ -1,177 +0,0 @@
// Copyright 2018-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_COEXIST_INTERNAL_H__
#define __ESP_COEXIST_INTERNAL_H__
#include <stdbool.h>
#include "esp_coexist_adapter.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
COEX_PREFER_WIFI = 0,
COEX_PREFER_BT,
COEX_PREFER_BALANCE,
COEX_PREFER_NUM,
} coex_prefer_t;
typedef void (* coex_func_cb_t)(uint32_t event, int sched_cnt);
/**
* @brief Pre-Init software coexist
* extern function for internal use.
*
* @return Init ok or failed.
*/
esp_err_t coex_pre_init(void);
/**
* @brief Init software coexist
* extern function for internal use.
*
* @return Init ok or failed.
*/
esp_err_t coex_init(void);
/**
* @brief De-init software coexist
* extern function for internal use.
*/
void coex_deinit(void);
/**
* @brief Pause software coexist
* extern function for internal use.
*/
void coex_pause(void);
/**
* @brief Resume software coexist
* extern function for internal use.
*/
void coex_resume(void);
/**
* @brief Get software coexist version string
* extern function for internal use.
* @return : version string
*/
const char *coex_version_get(void);
/**
* @brief Coexist performance preference set from libbt.a
* extern function for internal use.
*
* @param prefer : the prefer enumeration value
* @return : ESP_OK - success, other - failed
*/
esp_err_t coex_preference_set(coex_prefer_t prefer);
/**
* @brief Get software coexist status.
* @return : software coexist status
*/
uint32_t coex_status_get(void);
/**
* @brief Set software coexist condition.
* @return : software coexist condition
*/
void coex_condition_set(uint32_t type, bool dissatisfy);
/**
* @brief WiFi requests coexistence.
*
* @param event : WiFi event
* @param latency : WiFi will request coexistence after latency
* @param duration : duration for WiFi to request coexistence
* @return : 0 - success, other - failed
*/
int coex_wifi_request(uint32_t event, uint32_t latency, uint32_t duration);
/**
* @brief WiFi release coexistence.
*
* @param event : WiFi event
* @return : 0 - success, other - failed
*/
int coex_wifi_release(uint32_t event);
/**
* @brief Blue tooth requests coexistence.
*
* @param event : blue tooth event
* @param latency : blue tooth will request coexistence after latency
* @param duration : duration for blue tooth to request coexistence
* @return : 0 - success, other - failed
*/
int coex_bt_request(uint32_t event, uint32_t latency, uint32_t duration);
/**
* @brief Blue tooth release coexistence.
*
* @param event : blue tooth event
* @return : 0 - success, other - failed
*/
int coex_bt_release(uint32_t event);
/**
* @brief Register callback function for blue tooth.
*
* @param cb : callback function
* @return : 0 - success, other - failed
*/
int coex_register_bt_cb(coex_func_cb_t cb);
/**
* @brief Lock before reset base band.
*
* @return : lock value
*/
uint32_t coex_bb_reset_lock(void);
/**
* @brief Unlock after reset base band.
*
* @param restore : lock value
*/
void coex_bb_reset_unlock(uint32_t restore);
/**
* @brief Register coexistence adapter functions.
*
* @param funcs : coexistence adapter functions
* @return : ESP_OK - success, other - failed
*/
esp_err_t esp_coex_adapter_register(coex_adapter_funcs_t *funcs);
/**
* @brief Check the MD5 values of the coexistence adapter header files in IDF and WiFi library
*
* @attention 1. It is used for internal CI version check
*
* @return
* - ESP_OK : succeed
* - ESP_WIFI_INVALID_ARG : MD5 check fail
*/
esp_err_t esp_coex_adapter_funcs_md5_check(const char *md5);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_COEXIST_INTERNAL_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_CROSSCORE_INT_H
#define __ESP_CROSSCORE_INT_H
/**
* Initialize the crosscore interrupt system for this CPU.
* This needs to be called once on every CPU that is used
* by FreeRTOS.
*
* If multicore FreeRTOS support is enabled, this will be
* called automatically by the startup code and should not
* be called manually.
*/
void esp_crosscore_int_init();
/**
* Send an interrupt to a CPU indicating it should yield its
* currently running task in favour of a higher-priority task
* that presumably just woke up.
*
* This is used internally by FreeRTOS in multicore mode
* and should not be called by the user.
*
* @param core_id Core that should do the yielding
*/
void esp_crosscore_int_send_yield(int core_id);
/**
* Send an interrupt to a CPU indicating it should update its
* CCOMPARE1 value due to a frequency switch.
*
* This is used internally when dynamic frequency switching is
* enabled, and should not be called from application code.
*
* @param core_id Core that should update its CCOMPARE1 value
*/
void esp_crosscore_int_send_freq_switch(int core_id);
#endif

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tools/sdk/include/esp32/esp_dbg_stubs.h
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// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef ESP_DBG_STUBS_H_
#define ESP_DBG_STUBS_H_
#include "esp_err.h"
/**
* Debug stubs entries IDs
*/
typedef enum {
ESP_DBG_STUB_CONTROL_DATA, ///< stubs descriptor entry
ESP_DBG_STUB_ENTRY_FIRST,
ESP_DBG_STUB_ENTRY_GCOV ///< GCOV entry
= ESP_DBG_STUB_ENTRY_FIRST,
ESP_DBG_STUB_ENTRY_MAX
} esp_dbg_stub_id_t;
/**
* @brief Initializes debug stubs.
*
* @note Must be called after esp_apptrace_init() if app tracing is enabled.
*/
void esp_dbg_stubs_init(void);
/**
* @brief Initializes application tracing module.
*
* @note Should be called before any esp_apptrace_xxx call.
*
* @param id Stub ID.
* @param entry Stub entry. Usually it is stub entry function address,
* but can be any value meaningfull for OpenOCD command/code.
*
* @return ESP_OK on success, otherwise see esp_err_t
*/
esp_err_t esp_dbg_stub_entry_set(esp_dbg_stub_id_t id, uint32_t entry);
#endif //ESP_DBG_STUBS_H_

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tools/sdk/include/esp32/esp_deep_sleep.h
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file esp_deep_sleep.h
* @brief legacy definitions of esp_deep_sleep APIs
*
* This file provides compatibility for applications using esp_deep_sleep_* APIs.
* New applications should use functions defined in "esp_sleep.h" instead.
* These functions and types will be deprecated at some point.
*/
#warning esp_deep_sleep.h will be deprecated in the next release. Use esp_sleep.h instead.
#include "esp_sleep.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef esp_sleep_pd_domain_t esp_deep_sleep_pd_domain_t;
typedef esp_sleep_pd_option_t esp_deep_sleep_pd_option_t;
typedef esp_sleep_ext1_wakeup_mode_t esp_ext1_wakeup_mode_t;
typedef esp_sleep_wakeup_cause_t esp_deep_sleep_wakeup_cause_t;
inline static esp_err_t esp_deep_sleep_enable_ulp_wakeup(void)
{
return esp_sleep_enable_ulp_wakeup();
}
inline static esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us)
{
return esp_sleep_enable_timer_wakeup(time_in_us);
}
inline static esp_err_t esp_deep_sleep_enable_touchpad_wakeup(void)
{
return esp_sleep_enable_touchpad_wakeup();
}
inline static touch_pad_t esp_deep_sleep_get_touchpad_wakeup_status()
{
return esp_sleep_get_touchpad_wakeup_status();
}
inline static esp_err_t esp_deep_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
{
return esp_sleep_enable_ext0_wakeup(gpio_num, level);
}
inline static esp_err_t esp_deep_sleep_enable_ext1_wakeup(uint64_t mask, esp_ext1_wakeup_mode_t mode)
{
return esp_sleep_enable_ext1_wakeup(mask, mode);
}
inline static esp_err_t esp_deep_sleep_pd_config(
esp_deep_sleep_pd_domain_t domain,
esp_deep_sleep_pd_option_t option)
{
return esp_sleep_pd_config(domain, option);
}
inline static esp_deep_sleep_wakeup_cause_t esp_deep_sleep_get_wakeup_cause()
{
return esp_sleep_get_wakeup_cause();
}
#define ESP_DEEP_SLEEP_WAKEUP_UNDEFINED ESP_SLEEP_WAKEUP_UNDEFINED
#define ESP_DEEP_SLEEP_WAKEUP_EXT0 ESP_SLEEP_WAKEUP_EXT0
#define ESP_DEEP_SLEEP_WAKEUP_EXT1 ESP_SLEEP_WAKEUP_EXT1
#define ESP_DEEP_SLEEP_WAKEUP_TIMER ESP_SLEEP_WAKEUP_TIMER
#define ESP_DEEP_SLEEP_WAKEUP_TOUCHPAD ESP_SLEEP_WAKEUP_TOUCHPAD
#define ESP_DEEP_SLEEP_WAKEUP_ULP ESP_SLEEP_WAKEUP_ULP
#ifdef __cplusplus
}
#endif

2
tools/sdk/include/esp32/esp_deepsleep.h
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#warning esp_deepsleep.h has been renamed to esp_sleep.h, please update include directives
#include "esp_sleep.h"

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tools/sdk/include/esp32/esp_err.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef int32_t esp_err_t;
/* Definitions for error constants. */
#define ESP_OK 0 /*!< esp_err_t value indicating success (no error) */
#define ESP_FAIL -1 /*!< Generic esp_err_t code indicating failure */
#define ESP_ERR_NO_MEM 0x101 /*!< Out of memory */
#define ESP_ERR_INVALID_ARG 0x102 /*!< Invalid argument */
#define ESP_ERR_INVALID_STATE 0x103 /*!< Invalid state */
#define ESP_ERR_INVALID_SIZE 0x104 /*!< Invalid size */
#define ESP_ERR_NOT_FOUND 0x105 /*!< Requested resource not found */
#define ESP_ERR_NOT_SUPPORTED 0x106 /*!< Operation or feature not supported */
#define ESP_ERR_TIMEOUT 0x107 /*!< Operation timed out */
#define ESP_ERR_INVALID_RESPONSE 0x108 /*!< Received response was invalid */
#define ESP_ERR_INVALID_CRC 0x109 /*!< CRC or checksum was invalid */
#define ESP_ERR_INVALID_VERSION 0x10A /*!< Version was invalid */
#define ESP_ERR_INVALID_MAC 0x10B /*!< MAC address was invalid */
#define ESP_ERR_WIFI_BASE 0x3000 /*!< Starting number of WiFi error codes */
#define ESP_ERR_MESH_BASE 0x4000 /*!< Starting number of MESH error codes */
/**
* @brief Returns string for esp_err_t error codes
*
* This function finds the error code in a pre-generated lookup-table and
* returns its string representation.
*
* The function is generated by the Python script
* tools/gen_esp_err_to_name.py which should be run each time an esp_err_t
* error is modified, created or removed from the IDF project.
*
* @param code esp_err_t error code
* @return string error message
*/
const char *esp_err_to_name(esp_err_t code);
/**
* @brief Returns string for esp_err_t and system error codes
*
* This function finds the error code in a pre-generated lookup-table of
* esp_err_t errors and returns its string representation. If the error code
* is not found then it is attempted to be found among system errors.
*
* The function is generated by the Python script
* tools/gen_esp_err_to_name.py which should be run each time an esp_err_t
* error is modified, created or removed from the IDF project.
*
* @param code esp_err_t error code
* @param[out] buf buffer where the error message should be written
* @param buflen Size of buffer buf. At most buflen bytes are written into the buf buffer (including the terminating null byte).
* @return buf containing the string error message
*/
const char *esp_err_to_name_r(esp_err_t code, char *buf, size_t buflen);
/** @cond */
void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const char *function, const char *expression) __attribute__((noreturn));
/** @cond */
void _esp_error_check_failed_without_abort(esp_err_t rc, const char *file, int line, const char *function, const char *expression);
#ifndef __ASSERT_FUNC
/* This won't happen on IDF, which defines __ASSERT_FUNC in assert.h, but it does happen when building on the host which
uses /usr/include/assert.h or equivalent.
*/
#ifdef __ASSERT_FUNCTION
#define __ASSERT_FUNC __ASSERT_FUNCTION /* used in glibc assert.h */
#else
#define __ASSERT_FUNC "??"
#endif
#endif
/** @endcond */
/**
* Macro which can be used to check the error code,
* and terminate the program in case the code is not ESP_OK.
* Prints the error code, error location, and the failed statement to serial output.
*
* Disabled if assertions are disabled.
*/
#ifdef NDEBUG
#define ESP_ERROR_CHECK(x) do { \
esp_err_t __err_rc = (x); \
(void) sizeof(__err_rc); \
} while(0);
#elif defined(CONFIG_OPTIMIZATION_ASSERTIONS_SILENT)
#define ESP_ERROR_CHECK(x) do { \
esp_err_t __err_rc = (x); \
if (__err_rc != ESP_OK) { \
abort(); \
} \
} while(0);
#else
#define ESP_ERROR_CHECK(x) do { \
esp_err_t __err_rc = (x); \
if (__err_rc != ESP_OK) { \
_esp_error_check_failed(__err_rc, __FILE__, __LINE__, \
__ASSERT_FUNC, #x); \
} \
} while(0);
#endif
/**
* Macro which can be used to check the error code. Prints the error code, error location, and the failed statement to
* serial output.
* In comparison with ESP_ERROR_CHECK(), this prints the same error message but isn't terminating the program.
*/
#ifdef NDEBUG
#define ESP_ERROR_CHECK_WITHOUT_ABORT(x) ({ \
esp_err_t __err_rc = (x); \
__err_rc; \
})
#else
#define ESP_ERROR_CHECK_WITHOUT_ABORT(x) ({ \
esp_err_t __err_rc = (x); \
if (__err_rc != ESP_OK) { \
_esp_error_check_failed_without_abort(__err_rc, __FILE__, __LINE__, \
__ASSERT_FUNC, #x); \
} \
__err_rc; \
})
#endif //NDEBUG
#ifdef __cplusplus
}
#endif

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tools/sdk/include/esp32/esp_event_legacy.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_EVENT_H__
#define __ESP_EVENT_H__
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "esp_wifi_types.h"
#include "tcpip_adapter.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SYSTEM_EVENT_WIFI_READY = 0, /**< ESP32 WiFi ready */
SYSTEM_EVENT_SCAN_DONE, /**< ESP32 finish scanning AP */
SYSTEM_EVENT_STA_START, /**< ESP32 station start */
SYSTEM_EVENT_STA_STOP, /**< ESP32 station stop */
SYSTEM_EVENT_STA_CONNECTED, /**< ESP32 station connected to AP */
SYSTEM_EVENT_STA_DISCONNECTED, /**< ESP32 station disconnected from AP */
SYSTEM_EVENT_STA_AUTHMODE_CHANGE, /**< the auth mode of AP connected by ESP32 station changed */
SYSTEM_EVENT_STA_GOT_IP, /**< ESP32 station got IP from connected AP */
SYSTEM_EVENT_STA_LOST_IP, /**< ESP32 station lost IP and the IP is reset to 0 */
SYSTEM_EVENT_STA_WPS_ER_SUCCESS, /**< ESP32 station wps succeeds in enrollee mode */
SYSTEM_EVENT_STA_WPS_ER_FAILED, /**< ESP32 station wps fails in enrollee mode */
SYSTEM_EVENT_STA_WPS_ER_TIMEOUT, /**< ESP32 station wps timeout in enrollee mode */
SYSTEM_EVENT_STA_WPS_ER_PIN, /**< ESP32 station wps pin code in enrollee mode */
SYSTEM_EVENT_STA_WPS_ER_PBC_OVERLAP, /*!< ESP32 station wps overlap in enrollee mode */
SYSTEM_EVENT_AP_START, /**< ESP32 soft-AP start */
SYSTEM_EVENT_AP_STOP, /**< ESP32 soft-AP stop */
SYSTEM_EVENT_AP_STACONNECTED, /**< a station connected to ESP32 soft-AP */
SYSTEM_EVENT_AP_STADISCONNECTED, /**< a station disconnected from ESP32 soft-AP */
SYSTEM_EVENT_AP_STAIPASSIGNED, /**< ESP32 soft-AP assign an IP to a connected station */
SYSTEM_EVENT_AP_PROBEREQRECVED, /**< Receive probe request packet in soft-AP interface */
SYSTEM_EVENT_GOT_IP6, /**< ESP32 station or ap or ethernet interface v6IP addr is preferred */
SYSTEM_EVENT_ETH_START, /**< ESP32 ethernet start */
SYSTEM_EVENT_ETH_STOP, /**< ESP32 ethernet stop */
SYSTEM_EVENT_ETH_CONNECTED, /**< ESP32 ethernet phy link up */
SYSTEM_EVENT_ETH_DISCONNECTED, /**< ESP32 ethernet phy link down */
SYSTEM_EVENT_ETH_GOT_IP, /**< ESP32 ethernet got IP from connected AP */
SYSTEM_EVENT_MAX
} system_event_id_t;
/* add this macro define for compatible with old IDF version */
#ifndef SYSTEM_EVENT_AP_STA_GOT_IP6
#define SYSTEM_EVENT_AP_STA_GOT_IP6 SYSTEM_EVENT_GOT_IP6
#endif
typedef enum {
WPS_FAIL_REASON_NORMAL = 0, /**< ESP32 WPS normal fail reason */
WPS_FAIL_REASON_RECV_M2D, /**< ESP32 WPS receive M2D frame */
WPS_FAIL_REASON_MAX
}system_event_sta_wps_fail_reason_t;
typedef struct {
uint32_t status; /**< status of scanning APs */
uint8_t number;
uint8_t scan_id;
} system_event_sta_scan_done_t;
typedef struct {
uint8_t ssid[32]; /**< SSID of connected AP */
uint8_t ssid_len; /**< SSID length of connected AP */
uint8_t bssid[6]; /**< BSSID of connected AP*/
uint8_t channel; /**< channel of connected AP*/
wifi_auth_mode_t authmode;
} system_event_sta_connected_t;
typedef struct {
uint8_t ssid[32]; /**< SSID of disconnected AP */
uint8_t ssid_len; /**< SSID length of disconnected AP */
uint8_t bssid[6]; /**< BSSID of disconnected AP */
uint8_t reason; /**< reason of disconnection */
} system_event_sta_disconnected_t;
typedef struct {
wifi_auth_mode_t old_mode; /**< the old auth mode of AP */
wifi_auth_mode_t new_mode; /**< the new auth mode of AP */
} system_event_sta_authmode_change_t;
typedef struct {
tcpip_adapter_ip_info_t ip_info;
bool ip_changed;
} system_event_sta_got_ip_t;
typedef struct {
uint8_t pin_code[8]; /**< PIN code of station in enrollee mode */
} system_event_sta_wps_er_pin_t;
typedef struct {
tcpip_adapter_if_t if_index;
tcpip_adapter_ip6_info_t ip6_info;
} system_event_got_ip6_t;
typedef struct {
uint8_t mac[6]; /**< MAC address of the station connected to ESP32 soft-AP */
uint8_t aid; /**< the aid that ESP32 soft-AP gives to the station connected to */
} system_event_ap_staconnected_t;
typedef struct {
uint8_t mac[6]; /**< MAC address of the station disconnects to ESP32 soft-AP */
uint8_t aid; /**< the aid that ESP32 soft-AP gave to the station disconnects to */
} system_event_ap_stadisconnected_t;
typedef struct {
int rssi; /**< Received probe request signal strength */
uint8_t mac[6]; /**< MAC address of the station which send probe request */
} system_event_ap_probe_req_rx_t;
typedef struct {
ip4_addr_t ip;
} system_event_ap_staipassigned_t;
typedef union {
system_event_sta_connected_t connected; /**< ESP32 station connected to AP */
system_event_sta_disconnected_t disconnected; /**< ESP32 station disconnected to AP */
system_event_sta_scan_done_t scan_done; /**< ESP32 station scan (APs) done */
system_event_sta_authmode_change_t auth_change; /**< the auth mode of AP ESP32 station connected to changed */
system_event_sta_got_ip_t got_ip; /**< ESP32 station got IP, first time got IP or when IP is changed */
system_event_sta_wps_er_pin_t sta_er_pin; /**< ESP32 station WPS enrollee mode PIN code received */
system_event_sta_wps_fail_reason_t sta_er_fail_reason;/**< ESP32 station WPS enrollee mode failed reason code received */
system_event_ap_staconnected_t sta_connected; /**< a station connected to ESP32 soft-AP */
system_event_ap_stadisconnected_t sta_disconnected; /**< a station disconnected to ESP32 soft-AP */
system_event_ap_probe_req_rx_t ap_probereqrecved; /**< ESP32 soft-AP receive probe request packet */
system_event_ap_staipassigned_t ap_staipassigned; /**< ESP32 soft-AP assign an IP to the station*/
system_event_got_ip6_t got_ip6; /**< ESP32 station　or ap or ethernet ipv6 addr state change to preferred */
} system_event_info_t;
typedef struct {
system_event_id_t event_id; /**< event ID */
system_event_info_t event_info; /**< event information */
} system_event_t;
typedef esp_err_t (*system_event_handler_t)(system_event_t *event);
/**
* @brief Send a event to event task
*
* @attention 1. Other task/modules, such as the TCPIP module, can call this API to send an event to event task
*
* @param system_event_t * event : event
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_event_send(system_event_t *event);
/**
* @brief Default event handler for system events
*
* This function performs default handling of system events.
* When using esp_event_loop APIs, it is called automatically before invoking the user-provided
* callback function.
*
* Applications which implement a custom event loop must call this function
* as part of event processing.
*
* @param event pointer to event to be handled
* @return ESP_OK if an event was handled successfully
*/
esp_err_t esp_event_process_default(system_event_t *event);
/**
* @brief Install default event handlers for Ethernet interface
*
*/
void esp_event_set_default_eth_handlers();
/**
* @brief Install default event handlers for Wi-Fi interfaces (station and AP)
*
*/
void esp_event_set_default_wifi_handlers();
#ifdef __cplusplus
}
#endif
#endif /* __ESP_EVENT_H__ */

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tools/sdk/include/esp32/esp_event_loop.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_EVENT_LOOP_H__
#define __ESP_EVENT_LOOP_H__
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "esp_event.h"
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Application specified event callback function
*
* @param void *ctx : reserved for user
* @param system_event_t *event : event type defined in this file
*
* @return ESP_OK : succeed
* @return others : fail
*/
typedef esp_err_t (*system_event_cb_t)(void *ctx, system_event_t *event);
/**
* @brief Initialize event loop
* Create the event handler and task
*
* @param system_event_cb_t cb : application specified event callback, it can be modified by call esp_event_set_cb
* @param void *ctx : reserved for user
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_event_loop_init(system_event_cb_t cb, void *ctx);
/**
* @brief Set application specified event callback function
*
* @attention 1. If cb is NULL, means application don't need to handle
* If cb is not NULL, it will be call when an event is received, after the default event callback is completed
*
* @param system_event_cb_t cb : callback
* @param void *ctx : reserved for user
*
* @return system_event_cb_t : old callback
*/
system_event_cb_t esp_event_loop_set_cb(system_event_cb_t cb, void *ctx);
/**
* @brief Get the queue used by event loop
*
* @attention : currently this API is used to initialize "q" parameter
* of wifi_init structure.
*
* @return QueueHandle_t : event queue handle
*/
QueueHandle_t esp_event_loop_get_queue(void);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_EVENT_LOOP_H__ */

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tools/sdk/include/esp32/esp_flash_data_types.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_BIN_TYPES_H__
#define __ESP_BIN_TYPES_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C"
{
#endif
#define ESP_PARTITION_MAGIC 0x50AA
#define ESP_PARTITION_MAGIC_MD5 0xEBEB
/// OTA_DATA states for checking operability of the app.
typedef enum {
ESP_OTA_IMG_NEW = 0x0U, /*!< Monitor the first boot. In bootloader this state is changed to ESP_OTA_IMG_PENDING_VERIFY. */
ESP_OTA_IMG_PENDING_VERIFY = 0x1U, /*!< First boot for this app was. If while the second boot this state is then it will be changed to ABORTED. */
ESP_OTA_IMG_VALID = 0x2U, /*!< App was confirmed as workable. App can boot and work without limits. */
ESP_OTA_IMG_INVALID = 0x3U, /*!< App was confirmed as non-workable. This app will not selected to boot at all. */
ESP_OTA_IMG_ABORTED = 0x4U, /*!< App could not confirm the workable or non-workable. In bootloader IMG_PENDING_VERIFY state will be changed to IMG_ABORTED. This app will not selected to boot at all. */
ESP_OTA_IMG_UNDEFINED = 0xFFFFFFFFU, /*!< Undefined. App can boot and work without limits. */
} esp_ota_img_states_t;
/* OTA selection structure (two copies in the OTA data partition.)
Size of 32 bytes is friendly to flash encryption */
typedef struct {
uint32_t ota_seq;
uint8_t seq_label[20];
uint32_t ota_state;
uint32_t crc; /* CRC32 of ota_seq field only */
} esp_ota_select_entry_t;
typedef struct {
uint32_t offset;
uint32_t size;
} esp_partition_pos_t;
/* Structure which describes the layout of partition table entry.
* See docs/partition_tables.rst for more information about individual fields.
*/
typedef struct {
uint16_t magic;
uint8_t type;
uint8_t subtype;
esp_partition_pos_t pos;
uint8_t label[16];
uint32_t flags;
} esp_partition_info_t;
#define PART_TYPE_APP 0x00
#define PART_SUBTYPE_FACTORY 0x00
#define PART_SUBTYPE_OTA_FLAG 0x10
#define PART_SUBTYPE_OTA_MASK 0x0f
#define PART_SUBTYPE_TEST 0x20
#define PART_TYPE_DATA 0x01
#define PART_SUBTYPE_DATA_OTA 0x00
#define PART_SUBTYPE_DATA_RF 0x01
#define PART_SUBTYPE_DATA_WIFI 0x02
#define PART_SUBTYPE_DATA_NVS_KEYS 0x04
#define PART_SUBTYPE_DATA_EFUSE_EM 0x05
#define PART_TYPE_END 0xff
#define PART_SUBTYPE_END 0xff
#define PART_FLAG_ENCRYPTED (1<<0)
#ifdef __cplusplus
}
#endif
#endif //__ESP_BIN_TYPES_H__

131
tools/sdk/include/esp32/esp_freertos_hooks.h
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@ -1,131 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_FREERTOS_HOOKS_H__
#define __ESP_FREERTOS_HOOKS_H__
#include <stdbool.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C"
{
#endif
/*
Definitions for the tickhook and idlehook callbacks
*/
typedef bool (*esp_freertos_idle_cb_t)();
typedef void (*esp_freertos_tick_cb_t)();
/**
* @brief Register a callback to be called from the specified core's idle hook.
* The callback should return true if it should be called by the idle hook
* once per interrupt (or FreeRTOS tick), and return false if it should
* be called repeatedly as fast as possible by the idle hook.
*
* @warning Idle callbacks MUST NOT, UNDER ANY CIRCUMSTANCES, CALL
* A FUNCTION THAT MIGHT BLOCK.
*
* @param[in] new_idle_cb Callback to be called
* @param[in] cpuid id of the core
*
* @return
* - ESP_OK: Callback registered to the specified core's idle hook
* - ESP_ERR_NO_MEM: No more space on the specified core's idle hook to register callback
* - ESP_ERR_INVALID_ARG: cpuid is invalid
*/
esp_err_t esp_register_freertos_idle_hook_for_cpu(esp_freertos_idle_cb_t new_idle_cb, UBaseType_t cpuid);
/**
* @brief Register a callback to the idle hook of the core that calls this function.
* The callback should return true if it should be called by the idle hook
* once per interrupt (or FreeRTOS tick), and return false if it should
* be called repeatedly as fast as possible by the idle hook.
*
* @warning Idle callbacks MUST NOT, UNDER ANY CIRCUMSTANCES, CALL
* A FUNCTION THAT MIGHT BLOCK.
*
* @param[in] new_idle_cb Callback to be called
*
* @return
* - ESP_OK: Callback registered to the calling core's idle hook
* - ESP_ERR_NO_MEM: No more space on the calling core's idle hook to register callback
*/
esp_err_t esp_register_freertos_idle_hook(esp_freertos_idle_cb_t new_idle_cb);
/**
* @brief Register a callback to be called from the specified core's tick hook.
*
* @param[in] new_tick_cb Callback to be called
* @param[in] cpuid id of the core
*
* @return
* - ESP_OK: Callback registered to specified core's tick hook
* - ESP_ERR_NO_MEM: No more space on the specified core's tick hook to register the callback
* - ESP_ERR_INVALID_ARG: cpuid is invalid
*/
esp_err_t esp_register_freertos_tick_hook_for_cpu(esp_freertos_tick_cb_t new_tick_cb, UBaseType_t cpuid);
/**
* @brief Register a callback to be called from the calling core's tick hook.
*
* @param[in] new_tick_cb Callback to be called
*
* @return
* - ESP_OK: Callback registered to the calling core's tick hook
* - ESP_ERR_NO_MEM: No more space on the calling core's tick hook to register the callback
*/
esp_err_t esp_register_freertos_tick_hook(esp_freertos_tick_cb_t new_tick_cb);
/**
* @brief Unregister an idle callback from the idle hook of the specified core
*
* @param[in] old_idle_cb Callback to be unregistered
* @param[in] cpuid id of the core
*/
void esp_deregister_freertos_idle_hook_for_cpu(esp_freertos_idle_cb_t old_idle_cb, UBaseType_t cpuid);
/**
* @brief Unregister an idle callback. If the idle callback is registered to
* the idle hooks of both cores, the idle hook will be unregistered from
* both cores
*
* @param[in] old_idle_cb Callback to be unregistered
*/
void esp_deregister_freertos_idle_hook(esp_freertos_idle_cb_t old_idle_cb);
/**
* @brief Unregister a tick callback from the tick hook of the specified core
*
* @param[in] old_tick_cb Callback to be unregistered
* @param[in] cpuid id of the core
*/
void esp_deregister_freertos_tick_hook_for_cpu(esp_freertos_tick_cb_t old_tick_cb, UBaseType_t cpuid);
/**
* @brief Unregister a tick callback. If the tick callback is registered to the
* tick hooks of both cores, the tick hook will be unregistered from
* both cores
*
* @param[in] old_tick_cb Callback to be unregistered
*/
void esp_deregister_freertos_tick_hook(esp_freertos_tick_cb_t old_tick_cb);
#ifdef __cplusplus
}
#endif
#endif

22
tools/sdk/include/esp32/esp_gdbstub.h
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@ -1,22 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef GDBSTUB_H
#define GDBSTUB_H
#include <xtensa/config/core.h>
#include "freertos/xtensa_api.h"
void esp_gdbstub_panic_handler(XtExcFrame *frame) __attribute__((noreturn));
#endif

154
tools/sdk/include/esp32/esp_himem.h
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@ -1,152 +1,2 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stddef.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
//Opaque pointers as handles for ram/range data
typedef struct esp_himem_ramdata_t *esp_himem_handle_t;
typedef struct esp_himem_rangedata_t *esp_himem_rangehandle_t;
//ESP32 MMU block size
#define ESP_HIMEM_BLKSZ (0x8000)
#define ESP_HIMEM_MAPFLAG_RO 1 /*!< Indicates that a mapping will only be read from. Note that this is unused for now. */
/**
* @brief Allocate a block in high memory
*
* @param size Size of the to-be-allocated block, in bytes. Note that this needs to be
* a multiple of the external RAM mmu block size (32K).
* @param[out] handle_out Handle to be returned
* @returns - ESP_OK if succesful
* - ESP_ERR_NO_MEM if out of memory
* - ESP_ERR_INVALID_SIZE if size is not a multiple of 32K
*/
esp_err_t esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out);
/**
* @brief Allocate a memory region to map blocks into
*
* This allocates a contiguous CPU memory region that can be used to map blocks
* of physical memory into.
*
* @param size Size of the range to be allocated. Note this needs to be a multiple of
* the external RAM mmu block size (32K).
* @param[out] handle_out Handle to be returned
* @returns - ESP_OK if succesful
* - ESP_ERR_NO_MEM if out of memory or address space
* - ESP_ERR_INVALID_SIZE if size is not a multiple of 32K
*/
esp_err_t esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t *handle_out);
/**
* @brief Map a block of high memory into the CPUs address space
*
* This effectively makes the block available for read/write operations.
*
* @note The region to be mapped needs to have offsets and sizes that are aligned to the
* SPI RAM MMU block size (32K)
*
* @param handle Handle to the block of memory, as given by esp_himem_alloc
* @param range Range handle to map the memory in
* @param ram_offset Offset into the block of physical memory of the block to map
* @param range_offset Offset into the address range where the block will be mapped
* @param len Length of region to map
* @param flags One of ESP_HIMEM_MAPFLAG_*
* @param[out] out_ptr Pointer to variable to store resulting memory pointer in
* @returns - ESP_OK if the memory could be mapped
* - ESP_ERR_INVALID_ARG if offset, range or len aren't MMU-block-aligned (32K)
* - ESP_ERR_INVALID_SIZE if the offsets/lengths don't fit in the allocated memory or range
* - ESP_ERR_INVALID_STATE if a block in the selected ram offset/length is already mapped, or
* if a block in the selected range offset/length already has a mapping.
*/
esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range, size_t ram_offset, size_t range_offset, size_t len, int flags, void **out_ptr);
/**
* @brief Free a block of physical memory
*
* This clears out the associated handle making the memory available for re-allocation again.
* This will only succeed if none of the memory blocks currently have a mapping.
*
* @param handle Handle to the block of memory, as given by esp_himem_alloc
* @returns - ESP_OK if the memory is succesfully freed
* - ESP_ERR_INVALID_ARG if the handle still is (partially) mapped
*/
esp_err_t esp_himem_free(esp_himem_handle_t handle);
/**
* @brief Free a mapping range
*
* This clears out the associated handle making the range available for re-allocation again.
* This will only succeed if none of the range blocks currently are used for a mapping.
*
* @param handle Handle to the range block, as given by esp_himem_alloc_map_range
* @returns - ESP_OK if the memory is succesfully freed
* - ESP_ERR_INVALID_ARG if the handle still is (partially) mapped to
*/
esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle);
/**
* @brief Unmap a region
*
* @param range Range handle
* @param ptr Pointer returned by esp_himem_map
* @param len Length of the block to be unmapped. Must be aligned to the SPI RAM MMU blocksize (32K)
* @returns - ESP_OK if the memory is succesfully unmapped,
* - ESP_ERR_INVALID_ARG if ptr or len are invalid.
*/
esp_err_t esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, size_t len);
/**
* @brief Get total amount of memory under control of himem API
*
* @returns Amount of memory, in bytes
*/
size_t esp_himem_get_phys_size();
/**
* @brief Get free amount of memory under control of himem API
*
* @returns Amount of free memory, in bytes
*/
size_t esp_himem_get_free_size();
/**
* @brief Get amount of SPI memory address space needed for bankswitching
*
* @note This is also weakly defined in esp32/spiram.c and returns 0 there, so
* if no other function in this file is used, no memory is reserved.
*
* @returns Amount of reserved area, in bytes
*/
size_t esp_himem_reserved_area_size();
#ifdef __cplusplus
}
#endif
#warning esp_himem.h has been replaced by esp32/himem.h, please include esp32/himem.h instead
#include "esp32/himem.h"

67
tools/sdk/include/esp32/esp_int_wdt.h
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@ -1,67 +0,0 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_INT_WDT_H
#define __ESP_INT_WDT_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Watchdog_APIs
* @{
*/
/*
This routine enables a watchdog to catch instances of processes disabling
interrupts for too long, or code within interrupt handlers taking too long.
It does this by setting up a watchdog which gets fed from the FreeRTOS
task switch interrupt. When this watchdog times out, initially it will call
a high-level interrupt routine that will panic FreeRTOS in order to allow
for forensic examination of the state of the both CPUs. When this interrupt
handler is not called and the watchdog times out a second time, it will
reset the SoC.
This uses the TIMERG1 WDT.
*/
/**
* @brief Initialize the non-CPU-specific parts of interrupt watchdog.
* This is called in the init code if the interrupt watchdog
* is enabled in menuconfig.
*
*/
void esp_int_wdt_init();
/**
* @brief Enable the interrupt watchdog on the current CPU. This is called
* in the init code by both CPUs if the interrupt watchdog is enabled
* in menuconfig.
*
*/
void esp_int_wdt_cpu_init();
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

37
tools/sdk/include/esp32/esp_interface.h
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@ -1,37 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_INTERFACE_H__
#define __ESP_INTERFACE_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ESP_IF_WIFI_STA = 0, /**< ESP32 station interface */
ESP_IF_WIFI_AP, /**< ESP32 soft-AP interface */
ESP_IF_ETH, /**< ESP32 ethernet interface */
ESP_IF_MAX
} esp_interface_t;
#ifdef __cplusplus
}
#endif
#endif /* __ESP_INTERFACE_TYPES_H__ */

78
tools/sdk/include/esp32/esp_intr.h
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@ -12,78 +12,6 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_INTR_H__
#define __ESP_INTR_H__
#include "rom/ets_sys.h"
#include "freertos/xtensa_api.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ESP_CCOMPARE_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_CCOMPARE_INUM, (func), (void *)(arg))
#define ESP_EPWM_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_EPWM_INUM, (func), (void *)(arg))
#define ESP_MPWM_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_MPWM_INUM, (func), (void *)(arg))
#define ESP_SPI1_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SPI1_INUM, (func), (void *)(arg))
#define ESP_SPI2_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SPI2_INUM, (func), (void *)(arg))
#define ESP_SPI3_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SPI3_INUM, (func), (void *)(arg))
#define ESP_I2S0_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_I2S0_INUM, (func), (void *)(arg))
#define ESP_PCNT_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_PCNT_INUM, (func), (void *)(arg))
#define ESP_LEDC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_LEDC_INUM, (func), (void *)(arg))
#define ESP_WMAC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_WMAC_INUM, (func), (void *)(arg))
#define ESP_FRC_TIMER1_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_FRC_TIMER1_INUM, (func), (void *)(arg))
#define ESP_FRC_TIMER2_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_FRC_TIMER2_INUM, (func), (void *)(arg))
#define ESP_GPIO_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_GPIO_INUM, (func), (void *)(arg))
#define ESP_UART0_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_UART0_INUM, (func), (void *)(arg))
#define ESP_WDT_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_WDT_INUM, (func), (void *)(arg))
#define ESP_RTC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_RTC_INUM, (func), (void *)(arg))
#define ESP_SLC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SLC_INUM, (func), (void *)(arg))
#define ESP_RMT_CTRL_INTRL(func,arg)\
xt_set_interrupt_handler(ETS_RMT_CTRL_INUM, (func), (void *)(arg))
#define ESP_INTR_ENABLE(inum) \
xt_ints_on((1<<inum))
#define ESP_INTR_DISABLE(inum) \
xt_ints_off((1<<inum))
#ifdef __cplusplus
}
#endif
#endif /* __ESP_INTR_H__ */
#pragma once
#warning esp_intr.h is deprecated, please include esp_intr_alloc.h instead
#include "esp_intr_alloc.h"

34
tools/sdk/include/esp32/esp_intr_alloc.h
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@ -18,6 +18,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "freertos/xtensa_api.h"
#ifdef __cplusplus
extern "C" {
@ -80,7 +81,10 @@ extern "C" {
// This is used to provide SystemView with positive IRQ IDs, otherwise sheduler events are not shown properly
#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
typedef void (*intr_handler_t)(void *arg);
#define ESP_INTR_ENABLE(inum) xt_ints_on((1<<inum))
#define ESP_INTR_DISABLE(inum) xt_ints_off((1<<inum))
typedef void (*intr_handler_t)(void *arg);
typedef struct intr_handle_data_t intr_handle_data_t;
@ -88,7 +92,7 @@ typedef intr_handle_data_t* intr_handle_t ;
/**
* @brief Mark an interrupt as a shared interrupt
*
*
* This will mark a certain interrupt on the specified CPU as
* an interrupt that can be used to hook shared interrupt handlers
* to.
@ -105,7 +109,7 @@ esp_err_t esp_intr_mark_shared(int intno, int cpu, bool is_in_iram);
/**
* @brief Reserve an interrupt to be used outside of this framework
*
*
* This will mark a certain interrupt on the specified CPU as
* reserved, not to be allocated for any reason.
*
@ -137,7 +141,7 @@ esp_err_t esp_intr_reserve(int intno, int cpu);
* choice of interrupts that this routine can choose from. If this value
* is 0, it will default to allocating a non-shared interrupt of level
* 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
* from this function with the interrupt disabled.
* @param handler The interrupt handler. Must be NULL when an interrupt of level >3
* is requested, because these types of interrupts aren't C-callable.
@ -158,7 +162,7 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *ar
*
*
* This essentially does the same as esp_intr_alloc, but allows specifying a register and mask
* combo. For shared interrupts, the handler is only called if a read from the specified
* combo. For shared interrupts, the handler is only called if a read from the specified
* register, ANDed with the mask, returns non-zero. By passing an interrupt status register
* address and a fitting mask, this can be used to accelerate interrupt handling in the case
* a shared interrupt is triggered; by checking the interrupt statuses first, the code can
@ -171,7 +175,7 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *ar
* choice of interrupts that this routine can choose from. If this value
* is 0, it will default to allocating a non-shared interrupt of level
* 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
* from this function with the interrupt disabled.
* @param intrstatusreg The address of an interrupt status register
* @param intrstatusmask A mask. If a read of address intrstatusreg has any of the bits
@ -198,9 +202,9 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
* If the current core is not the core that registered this interrupt, this routine will be assigned to
* the core that allocated this interrupt, blocking and waiting until the resource is successfully released.
*
* @note
* When the handler shares its source with other handlers, the interrupt status
* bits it's responsible for should be managed properly before freeing it. see
* @note
* When the handler shares its source with other handlers, the interrupt status
* bits it's responsible for should be managed properly before freeing it. see
* ``esp_intr_disable`` for more details. Please do not call this function in ``esp_ipc_call_blocking``.
*
* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
@ -214,7 +218,7 @@ esp_err_t esp_intr_free(intr_handle_t handle);
/**
* @brief Get CPU number an interrupt is tied to
*
*
* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
*
* @return The core number where the interrupt is allocated
@ -223,7 +227,7 @@ int esp_intr_get_cpu(intr_handle_t handle);
/**
* @brief Get the allocated interrupt for a certain handle
*
*
* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
*
* @return The interrupt number
@ -232,13 +236,13 @@ int esp_intr_get_intno(intr_handle_t handle);
/**
* @brief Disable the interrupt associated with the handle
*
* @note
*
* @note
* 1. For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
* CPU the interrupt is allocated on. Other interrupts have no such restriction.
* 2. When several handlers sharing a same interrupt source, interrupt status bits, which are
* 2. When several handlers sharing a same interrupt source, interrupt status bits, which are
* handled in the handler to be disabled, should be masked before the disabling, or handled
* in other enabled interrupts properly. Miss of interrupt status handling will cause infinite
* in other enabled interrupts properly. Miss of interrupt status handling will cause infinite
* interrupt calls and finally system crash.
*
* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_IPC_H__
#define __ESP_IPC_H__
#include <esp_err.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond */
typedef void (*esp_ipc_func_t)(void* arg);
/** @endcond */
/*
* Inter-processor call APIs
*
* FreeRTOS provides several APIs which can be used to communicate between
* different tasks, including tasks running on different CPUs.
* This module provides additional APIs to run some code on the other CPU.
*
* These APIs can only be used when FreeRTOS scheduler is running.
*/
/**
* @brief Execute a function on the given CPU
*
* Run a given function on a particular CPU. The given function must accept a
* void* argument and return void. The given function is run in the context of
* the IPC task of the CPU specified by the cpu_id parameter. The calling task
* will be blocked until the IPC task begins executing the given function. If
* another IPC call is ongoing, the calling task will block until the other IPC
* call completes. The stack size allocated for the IPC task can be configured
* in the "Inter-Processor Call (IPC) task stack size" setting in menuconfig.
* Increase this setting if the given function requires more stack than default.
*
* @note In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1.
*
* @param[in] cpu_id CPU where the given function should be executed (0 or 1)
* @param[in] func Pointer to a function of type void func(void* arg) to be executed
* @param[in] arg Arbitrary argument of type void* to be passed into the function
*
* @return
* - ESP_ERR_INVALID_ARG if cpu_id is invalid
* - ESP_ERR_INVALID_STATE if the FreeRTOS scheduler is not running
* - ESP_OK otherwise
*/
esp_err_t esp_ipc_call(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
/**
* @brief Execute a function on the given CPU and blocks until it completes
*
* Run a given function on a particular CPU. The given function must accept a
* void* argument and return void. The given function is run in the context of
* the IPC task of the CPU specified by the cpu_id parameter. The calling task
* will be blocked until the IPC task completes execution of the given function.
* If another IPC call is ongoing, the calling task will block until the other
* IPC call completes. The stack size allocated for the IPC task can be
* configured in the "Inter-Processor Call (IPC) task stack size" setting in
* menuconfig. Increase this setting if the given function requires more stack
* than default.
*
* @note In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1.
*
* @param[in] cpu_id CPU where the given function should be executed (0 or 1)
* @param[in] func Pointer to a function of type void func(void* arg) to be executed
* @param[in] arg Arbitrary argument of type void* to be passed into the function
*
* @return
* - ESP_ERR_INVALID_ARG if cpu_id is invalid
* - ESP_ERR_INVALID_STATE if the FreeRTOS scheduler is not running
* - ESP_OK otherwise
*/
esp_err_t esp_ipc_call_blocking(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_IPC_H__ */

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tools/sdk/include/esp32/esp_mesh.h
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tools/sdk/include/esp32/esp_mesh_internal.h
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_MESH_INTERNAL_H__
#define __ESP_MESH_INTERNAL_H__
#include "esp_err.h"
#include "esp_wifi.h"
#include "esp_wifi_types.h"
#include "esp_wifi_internal.h"
#include "esp_wifi_crypto_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************
* Constants
*******************************************************/
/*******************************************************
* Structures
*******************************************************/
typedef struct {
int scan; /**< minimum scan times before being a root, default:10 */
int vote; /**< max vote times in self-healing, default:1000 */
int fail; /**< parent selection fail times, if the scan times reach this value,
device will disconnect with associated children and join self-healing. default:60 */
int monitor_ie; /**< acceptable times of parent networking IE change before update its own networking IE. default:3 */
} mesh_attempts_t;
typedef struct {
int duration_ms; /* parent weak RSSI monitor duration, if the RSSI continues to be weak during this duration_ms,
device will search for a new parent. */
int cnx_rssi; /* RSSI threshold for keeping a good connection with parent.
If set a value greater than -120 dBm, a timer will be armed to monitor parent RSSI at a period time of duration_ms. */
int select_rssi; /* RSSI threshold for parent selection. It should be a value greater than switch_rssi. */
int switch_rssi; /* Disassociate with current parent and switch to a new parent when the RSSI is greater than this set threshold. */
int backoff_rssi; /* RSSI threshold for connecting to the root */
} mesh_switch_parent_t;
typedef struct {
int high;
int medium;
int low;
} mesh_rssi_threshold_t;
/**
* @brief Mesh networking IE
*/
typedef struct {
/**< mesh networking IE head */
uint8_t eid; /**< element ID */
uint8_t len; /**< element length */
uint8_t oui[3]; /**< organization identifier */
/**< mesh networking IE content */
uint8_t type; /** ESP defined IE type */
uint8_t encrypted : 1; /**< whether mesh networking IE is encrypted */
uint8_t version : 7; /**< mesh networking IE version */
/**< content */
uint8_t mesh_type; /**< mesh device type */
uint8_t mesh_id[6]; /**< mesh ID */
uint8_t layer_cap; /**< max layer */
uint8_t layer; /**< current layer */
uint8_t assoc_cap; /**< max connections of mesh AP */
uint8_t assoc; /**< current connections */
uint8_t leaf_cap; /**< leaf capacity */
uint8_t leaf_assoc; /**< the number of current connected leaf */
uint16_t root_cap; /**< root capacity */
uint16_t self_cap; /**< self capacity */
uint16_t layer2_cap; /**< layer2 capacity */
uint16_t scan_ap_num; /**< the number of scanning APs */
int8_t rssi; /**< RSSI of the parent */
int8_t router_rssi; /**< RSSI of the router */
uint8_t flag; /**< flag of networking */
uint8_t rc_addr[6]; /**< root address */
int8_t rc_rssi; /**< root RSSI */
uint8_t vote_addr[6]; /**< voter address */
int8_t vote_rssi; /**< vote RSSI of the router */
uint8_t vote_ttl; /**< vote ttl */
uint16_t votes; /**< votes */
uint16_t my_votes; /**< my votes */
uint8_t reason; /**< reason */
uint8_t child[6]; /**< child address */
uint8_t toDS; /**< toDS state */
} __attribute__((packed)) mesh_assoc_t;
/*******************************************************
* Function Definitions
*******************************************************/
/**
* @brief Set mesh softAP beacon interval
*
* @param[in] interval beacon interval (msecs) (100 msecs ~ 60000 msecs)
*
* @return
* - ESP_OK
* - ESP_FAIL
* - ESP_ERR_WIFI_ARG
*/
esp_err_t esp_mesh_set_beacon_interval(int interval_ms);
/**
* @brief Get mesh softAP beacon interval
*
* @param[out] interval beacon interval (msecs)
*
* @return
* - ESP_OK
*/
esp_err_t esp_mesh_get_beacon_interval(int *interval_ms);
/**
* @brief Set attempts for mesh self-organized networking
*
* @param[in] attempts
*
* @return
* - ESP_OK
* - ESP_FAIL
*/
esp_err_t esp_mesh_set_attempts(mesh_attempts_t *attempts);
/**
* @brief Get attempts for mesh self-organized networking
*
* @param[out] attempts
*
* @return
* - ESP_OK
* - ESP_ERR_MESH_ARGUMENT
*/
esp_err_t esp_mesh_get_attempts(mesh_attempts_t *attempts);
/**
* @brief Set parameters for parent switch
*
* @param[in] paras parameters for parent switch
*
* @return
* - ESP_OK
* - ESP_ERR_MESH_ARGUMENT
*/
esp_err_t esp_mesh_set_switch_parent_paras(mesh_switch_parent_t *paras);
/**
* @brief Get parameters for parent switch
*
* @param[out] paras parameters for parent switch
*
* @return
* - ESP_OK
* - ESP_ERR_MESH_ARGUMENT
*/
esp_err_t esp_mesh_get_switch_parent_paras(mesh_switch_parent_t *paras);
/**
* @brief Set RSSI threshold
* - The default high RSSI threshold value is -78 dBm.
* - The default medium RSSI threshold value is -82 dBm.
* - The default low RSSI threshold value is -85 dBm.
*
* @param[in] threshold RSSI threshold
*
* @return
* - ESP_OK
* - ESP_ERR_MESH_ARGUMENT
*/
esp_err_t esp_mesh_set_rssi_threshold(const mesh_rssi_threshold_t *threshold);
/**
* @brief Get RSSI threshold
*
* @param[out] threshold RSSI threshold
*
* @return
* - ESP_OK
* - ESP_ERR_MESH_ARGUMENT
*/
esp_err_t esp_mesh_get_rssi_threshold(mesh_rssi_threshold_t *threshold);
/**
* @brief Enable the minimum rate to 6 Mbps
*
* @attention This API shall be called before Wi-Fi is started.
*
* @param[in] is_6m enable or not
*
* @return
* - ESP_OK
*/
esp_err_t esp_mesh_set_6m_rate(bool is_6m);
/**
* @brief Print the number of txQ waiting
*
* @return
* - ESP_OK
* - ESP_FAIL
*/
esp_err_t esp_mesh_print_txQ_waiting(void);
/**
* @brief Print the number of rxQ waiting
*
* @return
* - ESP_OK
* - ESP_FAIL
*/
esp_err_t esp_mesh_print_rxQ_waiting(void);
/**
* @brief Set passive scan time
*
* @param[in] interval_ms passive scan time (msecs)
*
* @return
* - ESP_OK
* - ESP_FAIL
* - ESP_ERR_ARGUMENT
*/
esp_err_t esp_mesh_set_passive_scan_time(int time_ms);
/**
* @brief Get passive scan time
*
* @return interval_ms passive scan time (msecs)
*/
int esp_mesh_get_passive_scan_time(void);
/**
* @brief Set announce interval
* - The default short interval is 500 milliseconds.
* - The default long interval is 3000 milliseconds.
*
* @param[in] short_ms shall be greater than the default value
* @param[in] long_ms shall be greater than the default value
*
* @return
* - ESP_OK
*/
esp_err_t esp_mesh_set_announce_interval(int short_ms, int long_ms);
/**
* @brief Get announce interval
*
* @param[out] short_ms short interval
* @param[out] long_ms long interval
*
* @return
* - ESP_OK
*/
esp_err_t esp_mesh_get_announce_interval(int *short_ms, int *long_ms);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_MESH_INTERNAL_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_NOW_H__
#define __ESP_NOW_H__
#include <stdbool.h>
#include "esp_err.h"
#include "esp_wifi_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup WiFi_APIs WiFi Related APIs
* @brief WiFi APIs
*/
/** @addtogroup WiFi_APIs
* @{
*/
/** \defgroup ESPNOW_APIs ESPNOW APIs
* @brief ESP32 ESPNOW APIs
*
*/
/** @addtogroup ESPNOW_APIs
* @{
*/
#define ESP_ERR_ESPNOW_BASE (ESP_ERR_WIFI_BASE + 100) /*!< ESPNOW error number base. */
#define ESP_ERR_ESPNOW_NOT_INIT (ESP_ERR_ESPNOW_BASE + 1) /*!< ESPNOW is not initialized. */
#define ESP_ERR_ESPNOW_ARG (ESP_ERR_ESPNOW_BASE + 2) /*!< Invalid argument */
#define ESP_ERR_ESPNOW_NO_MEM (ESP_ERR_ESPNOW_BASE + 3) /*!< Out of memory */
#define ESP_ERR_ESPNOW_FULL (ESP_ERR_ESPNOW_BASE + 4) /*!< ESPNOW peer list is full */
#define ESP_ERR_ESPNOW_NOT_FOUND (ESP_ERR_ESPNOW_BASE + 5) /*!< ESPNOW peer is not found */
#define ESP_ERR_ESPNOW_INTERNAL (ESP_ERR_ESPNOW_BASE + 6) /*!< Internal error */
#define ESP_ERR_ESPNOW_EXIST (ESP_ERR_ESPNOW_BASE + 7) /*!< ESPNOW peer has existed */
#define ESP_ERR_ESPNOW_IF (ESP_ERR_ESPNOW_BASE + 8) /*!< Interface error */
#define ESP_NOW_ETH_ALEN 6 /*!< Length of ESPNOW peer MAC address */
#define ESP_NOW_KEY_LEN 16 /*!< Length of ESPNOW peer local master key */
#define ESP_NOW_MAX_TOTAL_PEER_NUM 20 /*!< Maximum number of ESPNOW total peers */
#define ESP_NOW_MAX_ENCRYPT_PEER_NUM 6 /*!< Maximum number of ESPNOW encrypted peers */
#define ESP_NOW_MAX_DATA_LEN 250 /*!< Maximum length of ESPNOW data which is sent very time */
/**
* @brief Status of sending ESPNOW data .
*/
typedef enum {
ESP_NOW_SEND_SUCCESS = 0, /**< Send ESPNOW data successfully */
ESP_NOW_SEND_FAIL, /**< Send ESPNOW data fail */
} esp_now_send_status_t;
/**
* @brief ESPNOW peer information parameters.
*/
typedef struct esp_now_peer_info {
uint8_t peer_addr[ESP_NOW_ETH_ALEN]; /**< ESPNOW peer MAC address that is also the MAC address of station or softap */
uint8_t lmk[ESP_NOW_KEY_LEN]; /**< ESPNOW peer local master key that is used to encrypt data */
uint8_t channel; /**< Wi-Fi channel that peer uses to send/receive ESPNOW data. If the value is 0,
use the current channel which station or softap is on. Otherwise, it must be
set as the channel that station or softap is on. */
wifi_interface_t ifidx; /**< Wi-Fi interface that peer uses to send/receive ESPNOW data */
bool encrypt; /**< ESPNOW data that this peer sends/receives is encrypted or not */
void *priv; /**< ESPNOW peer private data */
} esp_now_peer_info_t;
/**
* @brief Number of ESPNOW peers which exist currently.
*/
typedef struct esp_now_peer_num {
int total_num; /**< Total number of ESPNOW peers, maximum value is ESP_NOW_MAX_TOTAL_PEER_NUM */
int encrypt_num; /**< Number of encrypted ESPNOW peers, maximum value is ESP_NOW_MAX_ENCRYPT_PEER_NUM */
} esp_now_peer_num_t;
/**
* @brief Callback function of receiving ESPNOW data
* @param mac_addr peer MAC address
* @param data received data
* @param data_len length of received data
*/
typedef void (*esp_now_recv_cb_t)(const uint8_t *mac_addr, const uint8_t *data, int data_len);
/**
* @brief Callback function of sending ESPNOW data
* @param mac_addr peer MAC address
* @param status status of sending ESPNOW data (succeed or fail)
*/
typedef void (*esp_now_send_cb_t)(const uint8_t *mac_addr, esp_now_send_status_t status);
/**
* @brief Initialize ESPNOW function
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_INTERNAL : Internal error
*/
esp_err_t esp_now_init(void);
/**
* @brief De-initialize ESPNOW function
*
* @return
* - ESP_OK : succeed
*/
esp_err_t esp_now_deinit(void);
/**
* @brief Get the version of ESPNOW
*
* @param version ESPNOW version
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_ARG : invalid argument
*/
esp_err_t esp_now_get_version(uint32_t *version);
/**
* @brief Register callback function of receiving ESPNOW data
*
* @param cb callback function of receiving ESPNOW data
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
* - ESP_ERR_ESPNOW_INTERNAL : internal error
*/
esp_err_t esp_now_register_recv_cb(esp_now_recv_cb_t cb);
/**
* @brief Unregister callback function of receiving ESPNOW data
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
*/
esp_err_t esp_now_unregister_recv_cb(void);
/**
* @brief Register callback function of sending ESPNOW data
*
* @param cb callback function of sending ESPNOW data
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
* - ESP_ERR_ESPNOW_INTERNAL : internal error
*/
esp_err_t esp_now_register_send_cb(esp_now_send_cb_t cb);
/**
* @brief Unregister callback function of sending ESPNOW data
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
*/
esp_err_t esp_now_unregister_send_cb(void);
/**
* @brief Send ESPNOW data
*
* @attention 1. If peer_addr is not NULL, send data to the peer whose MAC address matches peer_addr
* @attention 2. If peer_addr is NULL, send data to all of the peers that are added to the peer list
* @attention 3. The maximum length of data must be less than ESP_NOW_MAX_DATA_LEN
* @attention 4. The buffer pointed to by data argument does not need to be valid after esp_now_send returns
*
* @param peer_addr peer MAC address
* @param data data to send
* @param len length of data
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
* - ESP_ERR_ESPNOW_ARG : invalid argument
* - ESP_ERR_ESPNOW_INTERNAL : internal error
* - ESP_ERR_ESPNOW_NO_MEM : out of memory
* - ESP_ERR_ESPNOW_NOT_FOUND : peer is not found
* - ESP_ERR_ESPNOW_IF : current WiFi interface doesn't match that of peer
*/
esp_err_t esp_now_send(const uint8_t *peer_addr, const uint8_t *data, size_t len);
/**
* @brief Add a peer to peer list
*
* @param peer peer information
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
* - ESP_ERR_ESPNOW_ARG : invalid argument
* - ESP_ERR_ESPNOW_FULL : peer list is full
* - ESP_ERR_ESPNOW_NO_MEM : out of memory
* - ESP_ERR_ESPNOW_EXIST : peer has existed
*/
esp_err_t esp_now_add_peer(const esp_now_peer_info_t *peer);
/**
* @brief Delete a peer from peer list
*
* @param peer_addr peer MAC address
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
* - ESP_ERR_ESPNOW_ARG : invalid argument
* - ESP_ERR_ESPNOW_NOT_FOUND : peer is not found
*/
esp_err_t esp_now_del_peer(const uint8_t *peer_addr);
/**
* @brief Modify a peer
*
* @param peer peer information
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
* - ESP_ERR_ESPNOW_ARG : invalid argument
* - ESP_ERR_ESPNOW_FULL : peer list is full
*/
esp_err_t esp_now_mod_peer(const esp_now_peer_info_t *peer);
/**
* @brief Get a peer whose MAC address matches peer_addr from peer list
*
* @param peer_addr peer MAC address
* @param peer peer information
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
* - ESP_ERR_ESPNOW_ARG : invalid argument
* - ESP_ERR_ESPNOW_NOT_FOUND : peer is not found
*/
esp_err_t esp_now_get_peer(const uint8_t *peer_addr, esp_now_peer_info_t *peer);
/**
* @brief Fetch a peer from peer list
*
* @param from_head fetch from head of list or not
* @param peer peer information
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
* - ESP_ERR_ESPNOW_ARG : invalid argument
* - ESP_ERR_ESPNOW_NOT_FOUND : peer is not found
*/
esp_err_t esp_now_fetch_peer(bool from_head, esp_now_peer_info_t *peer);
/**
* @brief Peer exists or not
*
* @param peer_addr peer MAC address
*
* @return
* - true : peer exists
* - false : peer not exists
*/
bool esp_now_is_peer_exist(const uint8_t *peer_addr);
/**
* @brief Get the number of peers
*
* @param num number of peers
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
* - ESP_ERR_ESPNOW_ARG : invalid argument
*/
esp_err_t esp_now_get_peer_num(esp_now_peer_num_t *num);
/**
* @brief Set the primary master key
*
* @param pmk primary master key
*
* @attention 1. primary master key is used to encrypt local master key
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
* - ESP_ERR_ESPNOW_ARG : invalid argument
*/
esp_err_t esp_now_set_pmk(const uint8_t *pmk);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ESP_NOW_H__ */

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#ifndef PANIC_H
#define PANIC_H
#ifdef __cplusplus
extern "C"
{
#endif
#define PANIC_RSN_NONE 0
#define PANIC_RSN_DEBUGEXCEPTION 1
#define PANIC_RSN_DOUBLEEXCEPTION 2
#define PANIC_RSN_KERNELEXCEPTION 3
#define PANIC_RSN_COPROCEXCEPTION 4
#define PANIC_RSN_INTWDT_CPU0 5
#define PANIC_RSN_INTWDT_CPU1 6
#define PANIC_RSN_CACHEERR 7
#define PANIC_RSN_MAX 7
#ifndef __ASSEMBLER__
#include "esp_err.h"
/**
* @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function
* address. Do nothing otherwise.
* @param data Pointer to the target breakpoint position
*/
void esp_set_breakpoint_if_jtag(void *fn);
#define ESP_WATCHPOINT_LOAD 0x40000000
#define ESP_WATCHPOINT_STORE 0x80000000
#define ESP_WATCHPOINT_ACCESS 0xC0000000
/**
* @brief Set a watchpoint to break/panic when a certain memory range is accessed.
*
* @param no Watchpoint number. On the ESP32, this can be 0 or 1.
* @param adr Base address to watch
* @param size Size of the region, starting at the base address, to watch. Must
* be one of 2^n, with n in [0..6].
* @param flags One of ESP_WATCHPOINT_* flags
*
* @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
*
* @warning The ESP32 watchpoint hardware watches a region of bytes by effectively
* masking away the lower n bits for a region with size 2^n. If adr does
* not have zero for these lower n bits, you may not be watching the
* region you intended.
*/
esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags);
/**
* @brief Clear a watchpoint
*
* @param no Watchpoint to clear
*
*/
void esp_clear_watchpoint(int no);
/**
* @brief Checks stack pointer
*/
static inline bool esp_stack_ptr_is_sane(uint32_t sp)
{
return !(sp < 0x3ffae010UL || sp > 0x3ffffff0UL || ((sp & 0xf) != 0));
}
#endif
#ifdef __cplusplus
}
#endif
#endif

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @file PHY init parameters and API
*/
/**
* @brief Structure holding PHY init parameters
*/
typedef struct {
uint8_t params[128]; /*!< opaque PHY initialization parameters */
} esp_phy_init_data_t;
/**
* @brief Opaque PHY calibration data
*/
typedef struct {
uint8_t version[4]; /*!< PHY version */
uint8_t mac[6]; /*!< The MAC address of the station */
uint8_t opaque[1894]; /*!< calibration data */
} esp_phy_calibration_data_t;
typedef enum {
PHY_RF_CAL_PARTIAL = 0x00000000, /*!< Do part of RF calibration. This should be used after power-on reset. */
PHY_RF_CAL_NONE = 0x00000001, /*!< Don't do any RF calibration. This mode is only suggested to be used after deep sleep reset. */
PHY_RF_CAL_FULL = 0x00000002 /*!< Do full RF calibration. Produces best results, but also consumes a lot of time and current. Suggested to be used once. */
} esp_phy_calibration_mode_t;
/**
* @brief Modules for modem sleep
*/
typedef enum{
MODEM_BLE_MODULE, //!< BLE controller used
MODEM_CLASSIC_BT_MODULE, //!< Classic BT controller used
MODEM_WIFI_STATION_MODULE, //!< Wi-Fi Station used
MODEM_WIFI_SOFTAP_MODULE, //!< Wi-Fi SoftAP used
MODEM_WIFI_SNIFFER_MODULE, //!< Wi-Fi Sniffer used
MODEM_WIFI_NULL_MODULE, //!< Wi-Fi Null mode used
MODEM_USER_MODULE, //!< User used
MODEM_MODULE_COUNT //!< Number of items
}modem_sleep_module_t;
/**
* @brief Module WIFI mask for medem sleep
*/
#define MODEM_BT_MASK ((1<<MODEM_BLE_MODULE) | \
(1<<MODEM_CLASSIC_BT_MODULE))
/**
* @brief Module WIFI mask for medem sleep
*/
#define MODEM_WIFI_MASK ((1<<MODEM_WIFI_STATION_MODULE) | \
(1<<MODEM_WIFI_SOFTAP_MODULE) | \
(1<<MODEM_WIFI_SNIFFER_MODULE) | \
(1<<MODEM_WIFI_NULL_MODULE))
/**
* @brief Modules needing to call phy_rf_init
*/
typedef enum{
PHY_BT_MODULE, //!< Bluetooth used
PHY_WIFI_MODULE, //!< Wi-Fi used
PHY_MODEM_MODULE, //!< Modem sleep used
PHY_MODULE_COUNT //!< Number of items
}phy_rf_module_t;
/**
* @brief Get PHY init data
*
* If "Use a partition to store PHY init data" option is set in menuconfig,
* This function will load PHY init data from a partition. Otherwise,
* PHY init data will be compiled into the application itself, and this function
* will return a pointer to PHY init data located in read-only memory (DROM).
*
* If "Use a partition to store PHY init data" option is enabled, this function
* may return NULL if the data loaded from flash is not valid.
*
* @note Call esp_phy_release_init_data to release the pointer obtained using
* this function after the call to esp_wifi_init.
*
* @return pointer to PHY init data structure
*/
const esp_phy_init_data_t* esp_phy_get_init_data();
/**
* @brief Release PHY init data
* @param data pointer to PHY init data structure obtained from
* esp_phy_get_init_data function
*/
void esp_phy_release_init_data(const esp_phy_init_data_t* data);
/**
* @brief Function called by esp_phy_init to load PHY calibration data
*
* This is a convenience function which can be used to load PHY calibration
* data from NVS. Data can be stored to NVS using esp_phy_store_cal_data_to_nvs
* function.
*
* If calibration data is not present in the NVS, or
* data is not valid (was obtained for a chip with a different MAC address,
* or obtained for a different version of software), this function will
* return an error.
*
* If "Initialize PHY in startup code" option is set in menuconfig, this
* function will be used to load calibration data. To provide a different
* mechanism for loading calibration data, disable
* "Initialize PHY in startup code" option in menuconfig and call esp_phy_init
* function from the application. For an example usage of esp_phy_init and
* this function, see esp_phy_store_cal_data_to_nvs function in cpu_start.c
*
* @param out_cal_data pointer to calibration data structure to be filled with
* loaded data.
* @return ESP_OK on success
*/
esp_err_t esp_phy_load_cal_data_from_nvs(esp_phy_calibration_data_t* out_cal_data);
/**
* @brief Function called by esp_phy_init to store PHY calibration data
*
* This is a convenience function which can be used to store PHY calibration
* data to the NVS. Calibration data is returned by esp_phy_init function.
* Data saved using this function to the NVS can later be loaded using
* esp_phy_store_cal_data_to_nvs function.
*
* If "Initialize PHY in startup code" option is set in menuconfig, this
* function will be used to store calibration data. To provide a different
* mechanism for storing calibration data, disable
* "Initialize PHY in startup code" option in menuconfig and call esp_phy_init
* function from the application.
*
* @param cal_data pointer to calibration data which has to be saved.
* @return ESP_OK on success
*/
esp_err_t esp_phy_store_cal_data_to_nvs(const esp_phy_calibration_data_t* cal_data);
/**
* @brief Erase PHY calibration data which is stored in the NVS
*
* This is a function which can be used to trigger full calibration as a last-resort remedy
* if partial calibration is used. It can be called in the application based on some conditions
* (e.g. an option provided in some diagnostic mode).
*
* @return ESP_OK on success
* @return others on fail. Please refer to NVS API return value error number.
*/
esp_err_t esp_phy_erase_cal_data_in_nvs(void);
/**
* @brief Initialize PHY and RF module
*
* PHY and RF module should be initialized in order to use WiFi or BT.
* Now PHY and RF initializing job is done automatically when start WiFi or BT. Users should not
* call this API in their application.
*
* @param init_data PHY parameters. Default set of parameters can
* be obtained by calling esp_phy_get_default_init_data
* function.
* @param mode Calibration mode (Full, partial, or no calibration)
* @param[inout] calibration_data
* @return ESP_OK on success.
* @return ESP_FAIL on fail.
*/
esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data,esp_phy_calibration_mode_t mode,
esp_phy_calibration_data_t* calibration_data, phy_rf_module_t module);
/**
* @brief De-initialize PHY and RF module
*
* PHY module should be de-initialized in order to shutdown WiFi or BT.
* Now PHY and RF de-initializing job is done automatically when stop WiFi or BT. Users should not
* call this API in their application.
*
* @return ESP_OK on success.
*/
esp_err_t esp_phy_rf_deinit(phy_rf_module_t module);
/**
* @brief Load calibration data from NVS and initialize PHY and RF module
*/
void esp_phy_load_cal_and_init(phy_rf_module_t module);
/**
* @brief Module requires to enter modem sleep
*/
esp_err_t esp_modem_sleep_enter(modem_sleep_module_t module);
/**
* @brief Module requires to exit modem sleep
*/
esp_err_t esp_modem_sleep_exit(modem_sleep_module_t module);
/**
* @brief Register module to make it be able to require to enter/exit modem sleep
* Although the module has no sleep function, as long as the module use RF,
* it must call esp_modem_sleep_regsiter. Otherwise, other modules with sleep
* function will disable RF without checking the module which doesn't call
* esp_modem_sleep_regsiter.
*/
esp_err_t esp_modem_sleep_register(modem_sleep_module_t module);
/**
* @brief De-register module from modem sleep list
*/
esp_err_t esp_modem_sleep_deregister(modem_sleep_module_t module);
/**
* @brief Get the time stamp when PHY/RF was switched on
* @return return 0 if PHY/RF is never switched on. Otherwise return time in
* microsecond since boot when phy/rf was last switched on
*/
int64_t esp_phy_rf_get_on_ts(void);
#ifdef __cplusplus
}
#endif

179
tools/sdk/include/esp32/esp_pm.h
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@ -1,179 +0,0 @@
// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
// Include SoC-specific definitions. Only ESP32 supported for now.
#include "esp32/pm.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Power management constraints
*/
typedef enum {
/**
* Require CPU frequency to be at the maximum value set via esp_pm_configure.
* Argument is unused and should be set to 0.
*/
ESP_PM_CPU_FREQ_MAX,
/**
* Require APB frequency to be at the maximum value supported by the chip.
* Argument is unused and should be set to 0.
*/
ESP_PM_APB_FREQ_MAX,
/**
* Prevent the system from going into light sleep.
* Argument is unused and should be set to 0.
*/
ESP_PM_NO_LIGHT_SLEEP,
} esp_pm_lock_type_t;
/**
* @brief Set implementation-specific power management configuration
* @param config pointer to implementation-specific configuration structure (e.g. esp_pm_config_esp32)
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if the configuration values are not correct
* - ESP_ERR_NOT_SUPPORTED if certain combination of values is not supported,
* or if CONFIG_PM_ENABLE is not enabled in sdkconfig
*/
esp_err_t esp_pm_configure(const void* config);
/**
* @brief Opaque handle to the power management lock
*/
typedef struct esp_pm_lock* esp_pm_lock_handle_t;
/**
* @brief Initialize a lock handle for certain power management parameter
*
* When lock is created, initially it is not taken.
* Call esp_pm_lock_acquire to take the lock.
*
* This function must not be called from an ISR.
*
* @param lock_type Power management constraint which the lock should control
* @param arg argument, value depends on lock_type, see esp_pm_lock_type_t
* @param name arbitrary string identifying the lock (e.g. "wifi" or "spi").
* Used by the esp_pm_dump_locks function to list existing locks.
* May be set to NULL. If not set to NULL, must point to a string which is valid
* for the lifetime of the lock.
* @param[out] out_handle handle returned from this function. Use this handle when calling
* esp_pm_lock_delete, esp_pm_lock_acquire, esp_pm_lock_release.
* Must not be NULL.
* @return
* - ESP_OK on success
* - ESP_ERR_NO_MEM if the lock structure can not be allocated
* - ESP_ERR_INVALID_ARG if out_handle is NULL or type argument is not valid
* - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig
*/
esp_err_t esp_pm_lock_create(esp_pm_lock_type_t lock_type, int arg,
const char* name, esp_pm_lock_handle_t* out_handle);
/**
* @brief Take a power management lock
*
* Once the lock is taken, power management algorithm will not switch to the
* mode specified in a call to esp_pm_lock_create, or any of the lower power
* modes (higher numeric values of 'mode').
*
* The lock is recursive, in the sense that if esp_pm_lock_acquire is called
* a number of times, esp_pm_lock_release has to be called the same number of
* times in order to release the lock.
*
* This function may be called from an ISR.
*
* This function is not thread-safe w.r.t. calls to other esp_pm_lock_*
* functions for the same handle.
*
* @param handle handle obtained from esp_pm_lock_create function
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if the handle is invalid
* - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig
*/
esp_err_t esp_pm_lock_acquire(esp_pm_lock_handle_t handle);
/**
* @brief Release the lock taken using esp_pm_lock_acquire.
*
* Call to this functions removes power management restrictions placed when
* taking the lock.
*
* Locks are recursive, so if esp_pm_lock_acquire is called a number of times,
* esp_pm_lock_release has to be called the same number of times in order to
* actually release the lock.
*
* This function may be called from an ISR.
*
* This function is not thread-safe w.r.t. calls to other esp_pm_lock_*
* functions for the same handle.
*
* @param handle handle obtained from esp_pm_lock_create function
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if the handle is invalid
* - ESP_ERR_INVALID_STATE if lock is not acquired
* - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig
*/
esp_err_t esp_pm_lock_release(esp_pm_lock_handle_t handle);
/**
* @brief Delete a lock created using esp_pm_lock
*
* The lock must be released before calling this function.
*
* This function must not be called from an ISR.
*
* @param handle handle obtained from esp_pm_lock_create function
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if the handle argument is NULL
* - ESP_ERR_INVALID_STATE if the lock is still acquired
* - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig
*/
esp_err_t esp_pm_lock_delete(esp_pm_lock_handle_t handle);
/**
* Dump the list of all locks to stderr
*
* This function dumps debugging information about locks created using
* esp_pm_lock_create to an output stream.
*
* This function must not be called from an ISR. If esp_pm_lock_acquire/release
* are called while this function is running, inconsistent results may be
* reported.
*
* @param stream stream to print information to; use stdout or stderr to print
* to the console; use fmemopen/open_memstream to print to a
* string buffer.
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig
*/
esp_err_t esp_pm_dump_locks(FILE* stream);
#ifdef __cplusplus
}
#endif

24
tools/sdk/include/esp32/esp_private/esp_wifi_private.h
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@ -1,24 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ESP_WIFI_PRIVATE_H
#define _ESP_WIFI_PRIVATE_H
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#include "rom/queue.h"
#include "sdkconfig.h"
#include "esp_wifi_crypto_types.h"
#include "esp_wifi_os_adapter.h"
#endif /* _ESP_WIFI_PRIVATE_H */

21
tools/sdk/include/esp32/esp_private/esp_wifi_types_private.h
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@ -1,21 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ESP_WIFI_TYPES_PRIVATE_H
#define _ESP_WIFI_TYPES_PRIVATE_H
#include "rom/queue.h"
#include "esp_interface.h"
#endif

14
tools/sdk/include/esp32/esp_sleep.h
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@ -95,7 +95,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source);
* source is used.
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled.
* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled.
* - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
*/
esp_err_t esp_sleep_enable_ulp_wakeup();
@ -122,7 +122,7 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
*
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled.
* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled.
* - ESP_ERR_INVALID_STATE if wakeup triggers conflict
*/
esp_err_t esp_sleep_enable_touchpad_wakeup();
@ -295,16 +295,6 @@ esp_err_t esp_light_sleep_start();
*/
void esp_deep_sleep(uint64_t time_in_us) __attribute__((noreturn));
/**
* @brief Enter deep-sleep mode
*
* Function has been renamed to esp_deep_sleep.
* This name is deprecated and will be removed in a future version.
*
* @param time_in_us deep-sleep time, unit: microsecond
*/
void system_deep_sleep(uint64_t time_in_us) __attribute__((noreturn, deprecated));
/**
* @brief Get the wakeup source which caused wakeup from sleep

136
tools/sdk/include/esp32/esp_smartconfig.h
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@ -1,136 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_SMARTCONFIG_H__
#define __ESP_SMARTCONFIG_H__
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SC_STATUS_WAIT = 0, /**< Waiting to start connect */
SC_STATUS_FIND_CHANNEL, /**< Finding target channel */
SC_STATUS_GETTING_SSID_PSWD, /**< Getting SSID and password of target AP */
SC_STATUS_LINK, /**< Connecting to target AP */
SC_STATUS_LINK_OVER, /**< Connected to AP successfully */
} smartconfig_status_t;
typedef enum {
SC_TYPE_ESPTOUCH = 0, /**< protocol: ESPTouch */
SC_TYPE_AIRKISS, /**< protocol: AirKiss */
SC_TYPE_ESPTOUCH_AIRKISS, /**< protocol: ESPTouch and AirKiss */
} smartconfig_type_t;
/**
* @brief The callback of SmartConfig, executed when smart-config status changed.
*
* @param status Status of SmartConfig:
* - SC_STATUS_GETTING_SSID_PSWD : pdata is a pointer of smartconfig_type_t, means config type.
* - SC_STATUS_LINK : pdata is a pointer to wifi_config_t.
* - SC_STATUS_LINK_OVER : pdata is a pointer of phone's IP address(4 bytes) if pdata unequal NULL.
* - otherwise : parameter void *pdata is NULL.
* @param pdata According to the different status have different values.
*
*/
typedef void (*sc_callback_t)(smartconfig_status_t status, void *pdata);
/**
* @brief Get the version of SmartConfig.
*
* @return
* - SmartConfig version const char.
*/
const char *esp_smartconfig_get_version(void);
/**
* @brief Start SmartConfig, config ESP device to connect AP. You need to broadcast information by phone APP.
* Device sniffer special packets from the air that containing SSID and password of target AP.
*
* @attention 1. This API can be called in station or softAP-station mode.
* @attention 2. Can not call esp_smartconfig_start twice before it finish, please call
* esp_smartconfig_stop first.
*
* @param cb SmartConfig callback function.
* @param ... log 1: UART output logs; 0: UART only outputs the result.
*
* @return
* - ESP_OK: succeed
* - others: fail
*/
esp_err_t esp_smartconfig_start(sc_callback_t cb, ...);
/**
* @brief Stop SmartConfig, free the buffer taken by esp_smartconfig_start.
*
* @attention Whether connect to AP succeed or not, this API should be called to free
* memory taken by smartconfig_start.
*
* @return
* - ESP_OK: succeed
* - others: fail
*/
esp_err_t esp_smartconfig_stop(void);
/**
* @brief Set timeout of SmartConfig process.
*
* @attention Timing starts from SC_STATUS_FIND_CHANNEL status. SmartConfig will restart if timeout.
*
* @param time_s range 15s~255s, offset:45s.
*
* @return
* - ESP_OK: succeed
* - others: fail
*/
esp_err_t esp_esptouch_set_timeout(uint8_t time_s);
/**
* @brief Set protocol type of SmartConfig.
*
* @attention If users need to set the SmartConfig type, please set it before calling
* esp_smartconfig_start.
*
* @param type Choose from the smartconfig_type_t.
*
* @return
* - ESP_OK: succeed
* - others: fail
*/
esp_err_t esp_smartconfig_set_type(smartconfig_type_t type);
/**
* @brief Set mode of SmartConfig. default normal mode.
*
* @attention 1. Please call it before API esp_smartconfig_start.
* @attention 2. Fast mode have corresponding APP(phone).
* @attention 3. Two mode is compatible.
*
* @param enable false-disable(default); true-enable;
*
* @return
* - ESP_OK: succeed
* - others: fail
*/
esp_err_t esp_smartconfig_fast_mode(bool enable);
#ifdef __cplusplus
}
#endif
#endif

118
tools/sdk/include/esp32/esp_spiram.h
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@ -1,116 +1,2 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_SPIRAM_H
#define __ESP_SPIRAM_H
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
typedef enum {
ESP_SPIRAM_SIZE_16MBITS = 0, /*!< SPI RAM size is 16 MBits */
ESP_SPIRAM_SIZE_32MBITS = 1, /*!< SPI RAM size is 32 MBits */
ESP_SPIRAM_SIZE_64MBITS = 2, /*!< SPI RAM size is 64 MBits */
ESP_SPIRAM_SIZE_INVALID, /*!< SPI RAM size is invalid */
} esp_spiram_size_t;
/**
* @brief get SPI RAM size
* @return
* - ESP_SPIRAM_SIZE_INVALID if SPI RAM not enabled or not valid
* - SPI RAM size
*/
esp_spiram_size_t esp_spiram_get_chip_size();
/**
* @brief Initialize spiram interface/hardware. Normally called from cpu_start.c.
*
* @return ESP_OK on success
*/
esp_err_t esp_spiram_init();
/**
* @brief Configure Cache/MMU for access to external SPI RAM.
*
* Normally this function is called from cpu_start, if CONFIG_SPIRAM_BOOT_INIT
* option is enabled. Applications which need to enable SPI RAM at run time
* can disable CONFIG_SPIRAM_BOOT_INIT, and call this function later.
*
* @attention this function must be called with flash cache disabled.
*/
void esp_spiram_init_cache();
/**
* @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
* (in case of a dual-core system) the app CPU is online. This test overwrites the
* memory with crap, so do not call after e.g. the heap allocator has stored important
* stuff in SPI RAM.
*
* @return true on success, false on failed memory test
*/
bool esp_spiram_test();
/**
* @brief Add the initialized SPI RAM to the heap allocator.
*/
esp_err_t esp_spiram_add_to_heapalloc();
/**
* @brief Get the size of the attached SPI RAM chip selected in menuconfig
*
* @return Size in bytes, or 0 if no external RAM chip support compiled in.
*/
size_t esp_spiram_get_size();
/**
* @brief Force a writeback of the data in the SPI RAM cache. This is to be called whenever
* cache is disabled, because disabling cache on the ESP32 discards the data in the SPI
* RAM cache.
*
* This is meant for use from within the SPI flash code.
*/
void esp_spiram_writeback_cache();
/**
* @brief Reserve a pool of internal memory for specific DMA/internal allocations
*
* @param size Size of reserved pool in bytes
*
* @return
* - ESP_OK on success
* - ESP_ERR_NO_MEM when no memory available for pool
*/
esp_err_t esp_spiram_reserve_dma_pool(size_t size);
/**
* @brief If SPI RAM(PSRAM) has been initialized
*
* @return
* - true SPI RAM has been initialized successfully
* - false SPI RAM hasn't been initialized or initialized failed
*/
bool esp_spiram_is_initialized(void);
#endif
#warning esp_spiram.h has been replaced by esp32/spiram.h, please include esp32/spiram.h instead
#include "esp32/spiram.h"

336
tools/sdk/include/esp32/esp_system.h
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@ -1,336 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_SYSTEM_H__
#define __ESP_SYSTEM_H__
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "esp_sleep.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ESP_MAC_WIFI_STA,
ESP_MAC_WIFI_SOFTAP,
ESP_MAC_BT,
ESP_MAC_ETH,
} esp_mac_type_t;
/** @cond */
#define TWO_UNIVERSAL_MAC_ADDR 2
#define FOUR_UNIVERSAL_MAC_ADDR 4
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS
/** @endcond */
/**
* @brief Reset reasons
*/
typedef enum {
ESP_RST_UNKNOWN, //!< Reset reason can not be determined
ESP_RST_POWERON, //!< Reset due to power-on event
ESP_RST_EXT, //!< Reset by external pin (not applicable for ESP32)
ESP_RST_SW, //!< Software reset via esp_restart
ESP_RST_PANIC, //!< Software reset due to exception/panic
ESP_RST_INT_WDT, //!< Reset (software or hardware) due to interrupt watchdog
ESP_RST_TASK_WDT, //!< Reset due to task watchdog
ESP_RST_WDT, //!< Reset due to other watchdogs
ESP_RST_DEEPSLEEP, //!< Reset after exiting deep sleep mode
ESP_RST_BROWNOUT, //!< Brownout reset (software or hardware)
ESP_RST_SDIO, //!< Reset over SDIO
} esp_reset_reason_t;
/** @cond */
/**
* @attention Applications don't need to call this function anymore. It does nothing and will
* be removed in future version.
*/
void system_init(void) __attribute__ ((deprecated));
/**
* @brief Reset to default settings.
*
* Function has been deprecated, please use esp_wifi_restore instead.
* This name will be removed in a future release.
*/
void system_restore(void) __attribute__ ((deprecated));
/** @endcond */
/**
* Shutdown handler type
*/
typedef void (*shutdown_handler_t)(void);
/**
* @brief Register shutdown handler
*
* This function allows you to register a handler that gets invoked before
* the application is restarted using esp_restart function.
*/
esp_err_t esp_register_shutdown_handler(shutdown_handler_t handle);
/**
* @brief Restart PRO and APP CPUs.
*
* This function can be called both from PRO and APP CPUs.
* After successful restart, CPU reset reason will be SW_CPU_RESET.
* Peripherals (except for WiFi, BT, UART0, SPI1, and legacy timers) are not reset.
* This function does not return.
*/
void esp_restart(void) __attribute__ ((noreturn));
/** @cond */
/**
* @brief Restart system.
*
* Function has been renamed to esp_restart.
* This name will be removed in a future release.
*/
void system_restart(void) __attribute__ ((deprecated, noreturn));
/** @endcond */
/**
* @brief Get reason of last reset
* @return See description of esp_reset_reason_t for explanation of each value.
*/
esp_reset_reason_t esp_reset_reason(void);
/** @cond */
/**
* @brief Get system time, unit: microsecond.
*
* This function is deprecated. Use 'gettimeofday' function for 64-bit precision.
* This definition will be removed in a future release.
*/
uint32_t system_get_time(void) __attribute__ ((deprecated));
/** @endcond */
/**
* @brief Get the size of available heap.
*
* Note that the returned value may be larger than the maximum contiguous block
* which can be allocated.
*
* @return Available heap size, in bytes.
*/
uint32_t esp_get_free_heap_size(void);
/** @cond */
/**
* @brief Get the size of available heap.
*
* Function has been renamed to esp_get_free_heap_size.
* This name will be removed in a future release.
*
* @return Available heap size, in bytes.
*/
uint32_t system_get_free_heap_size(void) __attribute__ ((deprecated));
/** @endcond */
/**
* @brief Get the minimum heap that has ever been available
*
* @return Minimum free heap ever available
*/
uint32_t esp_get_minimum_free_heap_size( void );
/**
* @brief Get one random 32-bit word from hardware RNG
*
* The hardware RNG is fully functional whenever an RF subsystem is running (ie Bluetooth or WiFi is enabled). For
* random values, call this function after WiFi or Bluetooth are started.
*
* If the RF subsystem is not used by the program, the function bootloader_random_enable() can be called to enable an
* entropy source. bootloader_random_disable() must be called before RF subsystem or I2S peripheral are used. See these functions'
* documentation for more details.
*
* Any time the app is running without an RF subsystem (or bootloader_random) enabled, RNG hardware should be
* considered a PRNG. A very small amount of entropy is available due to pre-seeding while the IDF
* bootloader is running, but this should not be relied upon for any use.
*
* @return Random value between 0 and UINT32_MAX
*/
uint32_t esp_random(void);
/**
* @brief Fill a buffer with random bytes from hardware RNG
*
* @note This function has the same restrictions regarding available entropy as esp_random()
*
* @param buf Pointer to buffer to fill with random numbers.
* @param len Length of buffer in bytes
*/
void esp_fill_random(void *buf, size_t len);
/**
* @brief Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or
* external storage e.g. flash and EEPROM.
*
* Base MAC address is used to generate the MAC addresses used by the networking interfaces.
* If using base MAC address stored in BLK3 of EFUSE or external storage, call this API to set base MAC
* address with the MAC address which is stored in BLK3 of EFUSE or external storage before initializing
* WiFi/BT/Ethernet.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
*/
esp_err_t esp_base_mac_addr_set(uint8_t *mac);
/**
* @brief Return base MAC address which is set using esp_base_mac_addr_set.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
* ESP_ERR_INVALID_MAC base MAC address has not been set
*/
esp_err_t esp_base_mac_addr_get(uint8_t *mac);
/**
* @brief Return base MAC address which was previously written to BLK3 of EFUSE.
*
* Base MAC address is used to generate the MAC addresses used by the networking interfaces.
* This API returns the custom base MAC address which was previously written to BLK3 of EFUSE.
* Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also
* possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
* ESP_ERR_INVALID_VERSION An invalid MAC version field was read from BLK3 of EFUSE
* ESP_ERR_INVALID_CRC An invalid MAC CRC was read from BLK3 of EFUSE
*/
esp_err_t esp_efuse_mac_get_custom(uint8_t *mac);
/**
* @brief Return base MAC address which is factory-programmed by Espressif in BLK0 of EFUSE.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
*/
esp_err_t esp_efuse_mac_get_default(uint8_t *mac);
/** @cond */
/**
* @brief Read hardware MAC address from efuse.
*
* Function has been renamed to esp_efuse_mac_get_default.
* This name will be removed in a future release.
*
* @param mac hardware MAC address, length: 6 bytes.
*
* @return ESP_OK on success
*/
esp_err_t esp_efuse_read_mac(uint8_t *mac) __attribute__ ((deprecated));
/**
* @brief Read hardware MAC address.
*
* Function has been renamed to esp_efuse_mac_get_default.
* This name will be removed in a future release.
*
* @param mac hardware MAC address, length: 6 bytes.
* @return ESP_OK on success
*/
esp_err_t system_efuse_read_mac(uint8_t *mac) __attribute__ ((deprecated));
/** @endcond */
/**
* @brief Read base MAC address and set MAC address of the interface.
*
* This function first get base MAC address using esp_base_mac_addr_get or reads base MAC address
* from BLK0 of EFUSE. Then set the MAC address of the interface including wifi station, wifi softap,
* bluetooth and ethernet.
*
* @param mac MAC address of the interface, length: 6 bytes.
* @param type type of MAC address, 0:wifi station, 1:wifi softap, 2:bluetooth, 3:ethernet.
*
* @return ESP_OK on success
*/
esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type);
/**
* @brief Derive local MAC address from universal MAC address.
*
* This function derives a local MAC address from an universal MAC address.
* A `definition of local vs universal MAC address can be found on Wikipedia
* <https://en.wikipedia.org/wiki/MAC_address#Universal_vs._local>`.
* In ESP32, universal MAC address is generated from base MAC address in EFUSE or other external storage.
* Local MAC address is derived from the universal MAC address.
*
* @param local_mac Derived local MAC address, length: 6 bytes.
* @param universal_mac Source universal MAC address, length: 6 bytes.
*
* @return ESP_OK on success
*/
esp_err_t esp_derive_local_mac(uint8_t* local_mac, const uint8_t* universal_mac);
/** @cond */
/**
* Get SDK version
*
* This function is deprecated and will be removed in a future release.
*
* @return constant string "master"
*/
const char* system_get_sdk_version(void) __attribute__ ((deprecated));
/** @endcond */
/**
* Get IDF version
*
* @return constant string from IDF_VER
*/
const char* esp_get_idf_version(void);
/**
* @brief Chip models
*/
typedef enum {
CHIP_ESP32 = 1, //!< ESP32
} esp_chip_model_t;
/* Chip feature flags, used in esp_chip_info_t */
#define CHIP_FEATURE_EMB_FLASH BIT(0) //!< Chip has embedded flash memory
#define CHIP_FEATURE_WIFI_BGN BIT(1) //!< Chip has 2.4GHz WiFi
#define CHIP_FEATURE_BLE BIT(4) //!< Chip has Bluetooth LE
#define CHIP_FEATURE_BT BIT(5) //!< Chip has Bluetooth Classic
/**
* @brief The structure represents information about the chip
*/
typedef struct {
esp_chip_model_t model; //!< chip model, one of esp_chip_model_t
uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags
uint8_t cores; //!< number of CPU cores
uint8_t revision; //!< chip revision number
} esp_chip_info_t;
/**
* @brief Fill an esp_chip_info_t structure with information about the chip
* @param[out] out_info structure to be filled
*/
void esp_chip_info(esp_chip_info_t* out_info);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_SYSTEM_H__ */

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tools/sdk/include/esp32/esp_task.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/* Notes:
* 1. Put all task priority and stack size definition in this file
* 2. If the task priority is less than 10, use ESP_TASK_PRIO_MIN + X style,
* otherwise use ESP_TASK_PRIO_MAX - X style
* 3. If this is a daemon task, the macro prefix is ESP_TASKD_, otherwise
* it's ESP_TASK_
* 4. If the configMAX_PRIORITIES is modified, please make all priority are
* greater than 0
* 5. Make sure esp_task.h is consistent between wifi lib and idf
*/
#ifndef _ESP_TASK_H_
#define _ESP_TASK_H_
#include "sdkconfig.h"
#include "freertos/FreeRTOSConfig.h"
#define ESP_TASK_PRIO_MAX (configMAX_PRIORITIES)
#define ESP_TASK_PRIO_MIN (0)
/* Bt contoller Task */
/* controller */
#define ESP_TASK_BT_CONTROLLER_PRIO (ESP_TASK_PRIO_MAX - 2)
#ifdef CONFIG_NEWLIB_NANO_FORMAT
#define TASK_EXTRA_STACK_SIZE (0)
#else
#define TASK_EXTRA_STACK_SIZE (512)
#endif
#define BT_TASK_EXTRA_STACK_SIZE TASK_EXTRA_STACK_SIZE
#define ESP_TASK_BT_CONTROLLER_STACK (3584 + TASK_EXTRA_STACK_SIZE)
/* idf task */
#define ESP_TASK_TIMER_PRIO (ESP_TASK_PRIO_MAX - 3)
#define ESP_TASK_TIMER_STACK (CONFIG_TIMER_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#define ESP_TASKD_EVENT_PRIO (ESP_TASK_PRIO_MAX - 5)
#define ESP_TASKD_EVENT_STACK (CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#define ESP_TASK_TCPIP_PRIO (ESP_TASK_PRIO_MAX - 7)
#define ESP_TASK_TCPIP_STACK (CONFIG_TCPIP_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#define ESP_TASK_MAIN_PRIO (ESP_TASK_PRIO_MIN + 1)
#define ESP_TASK_MAIN_STACK (CONFIG_MAIN_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
#endif

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tools/sdk/include/esp32/esp_task_wdt.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize the Task Watchdog Timer (TWDT)
*
* This function configures and initializes the TWDT. If the TWDT is already
* initialized when this function is called, this function will update the
* TWDT's timeout period and panic configurations instead. After initializing
* the TWDT, any task can elect to be watched by the TWDT by subscribing to it
* using esp_task_wdt_add().
*
* @param[in] timeout Timeout period of TWDT in seconds
* @param[in] panic Flag that controls whether the panic handler will be
* executed when the TWDT times out
*
* @return
* - ESP_OK: Initialization was successful
* - ESP_ERR_NO_MEM: Initialization failed due to lack of memory
*
* @note esp_task_wdt_init() must only be called after the scheduler
* started
*/
esp_err_t esp_task_wdt_init(uint32_t timeout, bool panic);
/**
* @brief Deinitialize the Task Watchdog Timer (TWDT)
*
* This function will deinitialize the TWDT. Calling this function whilst tasks
* are still subscribed to the TWDT, or when the TWDT is already deinitialized,
* will result in an error code being returned.
*
* @return
* - ESP_OK: TWDT successfully deinitialized
* - ESP_ERR_INVALID_STATE: Error, tasks are still subscribed to the TWDT
* - ESP_ERR_NOT_FOUND: Error, TWDT has already been deinitialized
*/
esp_err_t esp_task_wdt_deinit();
/**
* @brief Subscribe a task to the Task Watchdog Timer (TWDT)
*
* This function subscribes a task to the TWDT. Each subscribed task must
* periodically call esp_task_wdt_reset() to prevent the TWDT from elapsing its
* timeout period. Failure to do so will result in a TWDT timeout. If the task
* being subscribed is one of the Idle Tasks, this function will automatically
* enable esp_task_wdt_reset() to called from the Idle Hook of the Idle Task.
* Calling this function whilst the TWDT is uninitialized or attempting to
* subscribe an already subscribed task will result in an error code being
* returned.
*
* @param[in] handle Handle of the task. Input NULL to subscribe the current
* running task to the TWDT
*
* @return
* - ESP_OK: Successfully subscribed the task to the TWDT
* - ESP_ERR_INVALID_ARG: Error, the task is already subscribed
* - ESP_ERR_NO_MEM: Error, could not subscribe the task due to lack of
* memory
* - ESP_ERR_INVALID_STATE: Error, the TWDT has not been initialized yet
*/
esp_err_t esp_task_wdt_add(TaskHandle_t handle);
/**
* @brief Reset the Task Watchdog Timer (TWDT) on behalf of the currently
* running task
*
* This function will reset the TWDT on behalf of the currently running task.
* Each subscribed task must periodically call this function to prevent the
* TWDT from timing out. If one or more subscribed tasks fail to reset the
* TWDT on their own behalf, a TWDT timeout will occur. If the IDLE tasks have
* been subscribed to the TWDT, they will automatically call this function from
* their idle hooks. Calling this function from a task that has not subscribed
* to the TWDT, or when the TWDT is uninitialized will result in an error code
* being returned.
*
* @return
* - ESP_OK: Successfully reset the TWDT on behalf of the currently
* running task
* - ESP_ERR_NOT_FOUND: Error, the current running task has not subscribed
* to the TWDT
* - ESP_ERR_INVALID_STATE: Error, the TWDT has not been initialized yet
*/
esp_err_t esp_task_wdt_reset();
/**
* @brief Unsubscribes a task from the Task Watchdog Timer (TWDT)
*
* This function will unsubscribe a task from the TWDT. After being
* unsubscribed, the task should no longer call esp_task_wdt_reset(). If the
* task is an IDLE task, this function will automatically disable the calling
* of esp_task_wdt_reset() from the Idle Hook. Calling this function whilst the
* TWDT is uninitialized or attempting to unsubscribe an already unsubscribed
* task from the TWDT will result in an error code being returned.
*
* @param[in] handle Handle of the task. Input NULL to unsubscribe the
* current running task.
*
* @return
* - ESP_OK: Successfully unsubscribed the task from the TWDT
* - ESP_ERR_INVALID_ARG: Error, the task is already unsubscribed
* - ESP_ERR_INVALID_STATE: Error, the TWDT has not been initialized yet
*/
esp_err_t esp_task_wdt_delete(TaskHandle_t handle);
/**
* @brief Query whether a task is subscribed to the Task Watchdog Timer (TWDT)
*
* This function will query whether a task is currently subscribed to the TWDT,
* or whether the TWDT is initialized.
*
* @param[in] handle Handle of the task. Input NULL to query the current
* running task.
*
* @return:
* - ESP_OK: The task is currently subscribed to the TWDT
* - ESP_ERR_NOT_FOUND: The task is currently not subscribed to the TWDT
* - ESP_ERR_INVALID_STATE: The TWDT is not initialized, therefore no tasks
* can be subscribed
*/
esp_err_t esp_task_wdt_status(TaskHandle_t handle);
/**
* @brief Reset the TWDT on behalf of the current running task, or
* subscribe the TWDT to if it has not done so already
*
* @warning This function is deprecated, use esp_task_wdt_add() and
* esp_task_wdt_reset() instead
*
* This function is similar to esp_task_wdt_reset() and will reset the TWDT on
* behalf of the current running task. However if this task has not subscribed
* to the TWDT, this function will automatically subscribe the task. Therefore,
* an unsubscribed task will subscribe to the TWDT on its first call to this
* function, then proceed to reset the TWDT on subsequent calls of this
* function.
*/
void esp_task_wdt_feed() __attribute__ ((deprecated));
#ifdef __cplusplus
}
#endif

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tools/sdk/include/esp32/esp_timer.h
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// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file esp_timer.h
* @brief microsecond-precision 64-bit timer API, replacement for ets_timer
*
* esp_timer APIs allow components to receive callbacks when a hardware timer
* reaches certain value. The timer provides microsecond accuracy and
* up to 64 bit range. Note that while the timer itself provides microsecond
* accuracy, callbacks are dispatched from an auxiliary task. Some time is
* needed to notify this task from timer ISR, and then to invoke the callback.
* If more than one callback needs to be dispatched at any particular time,
* each subsequent callback will be dispatched only when the previous callback
* returns. Therefore, callbacks should not do much work; instead, they should
* use RTOS notification mechanisms (queues, semaphores, event groups, etc.) to
* pass information to other tasks.
*
* To be implemented: it should be possible to request the callback to be called
* directly from the ISR. This reduces the latency, but has potential impact on
* all other callbacks which need to be dispatched. This option should only be
* used for simple callback functions, which do not take longer than a few
* microseconds to run.
*
* Implementation note: on the ESP32, esp_timer APIs use the "legacy" FRC2
* timer. Timer callbacks are called from a task running on the PRO CPU.
*/
#include <stdint.h>
#include <stdio.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Opaque type representing a single esp_timer
*/
typedef struct esp_timer* esp_timer_handle_t;
/**
* @brief Timer callback function type
* @param arg pointer to opaque user-specific data
*/
typedef void (*esp_timer_cb_t)(void* arg);
/**
* @brief Method for dispatching timer callback
*/
typedef enum {
ESP_TIMER_TASK, //!< Callback is called from timer task
/* Not supported for now, provision to allow callbacks to run directly
* from an ISR:
ESP_TIMER_ISR, //!< Callback is called from timer ISR
*/
} esp_timer_dispatch_t;
/**
* @brief Timer configuration passed to esp_timer_create
*/
typedef struct {
esp_timer_cb_t callback; //!< Function to call when timer expires
void* arg; //!< Argument to pass to the callback
esp_timer_dispatch_t dispatch_method; //!< Call the callback from task or from ISR
const char* name; //!< Timer name, used in esp_timer_dump function
} esp_timer_create_args_t;
/**
* @brief Initialize esp_timer library
*
* @note This function is called from startup code. Applications do not need
* to call this function before using other esp_timer APIs.
*
* @return
* - ESP_OK on success
* - ESP_ERR_NO_MEM if allocation has failed
* - ESP_ERR_INVALID_STATE if already initialized
* - other errors from interrupt allocator
*/
esp_err_t esp_timer_init();
/**
* @brief De-initialize esp_timer library
*
* @note Normally this function should not be called from applications
*
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_STATE if not yet initialized
*/
esp_err_t esp_timer_deinit();
/**
* @brief Create an esp_timer instance
*
* @note When done using the timer, delete it with esp_timer_delete function.
*
* @param create_args Pointer to a structure with timer creation arguments.
* Not saved by the library, can be allocated on the stack.
* @param[out] out_handle Output, pointer to esp_timer_handle_t variable which
* will hold the created timer handle.
*
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if some of the create_args are not valid
* - ESP_ERR_INVALID_STATE if esp_timer library is not initialized yet
* - ESP_ERR_NO_MEM if memory allocation fails
*/
esp_err_t esp_timer_create(const esp_timer_create_args_t* create_args,
esp_timer_handle_t* out_handle);
/**
* @brief Start one-shot timer
*
* Timer should not be running when this function is called.
*
* @param timer timer handle created using esp_timer_create
* @param timeout_us timer timeout, in microseconds relative to the current moment
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if the handle is invalid
* - ESP_ERR_INVALID_STATE if the timer is already running
*/
esp_err_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us);
/**
* @brief Start a periodic timer
*
* Timer should not be running when this function is called. This function will
* start the timer which will trigger every 'period' microseconds.
*
* @param timer timer handle created using esp_timer_create
* @param period timer period, in microseconds
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if the handle is invalid
* - ESP_ERR_INVALID_STATE if the timer is already running
*/
esp_err_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period);
/**
* @brief Stop the timer
*
* This function stops the timer previously started using esp_timer_start_once
* or esp_timer_start_periodic.
*
* @param timer timer handle created using esp_timer_create
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_STATE if the timer is not running
*/
esp_err_t esp_timer_stop(esp_timer_handle_t timer);
/**
* @brief Delete an esp_timer instance
*
* The timer must be stopped before deleting. A one-shot timer which has expired
* does not need to be stopped.
*
* @param timer timer handle allocated using esp_timer_create
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_STATE if the timer is not running
*/
esp_err_t esp_timer_delete(esp_timer_handle_t timer);
/**
* @brief Get time in microseconds since boot
* @return number of microseconds since esp_timer_init was called (this normally
* happens early during application startup).
*/
int64_t esp_timer_get_time();
/**
* @brief Get the timestamp when the next timeout is expected to occur
* @return Timestamp of the nearest timer event, in microseconds.
* The timebase is the same as for the values returned by esp_timer_get_time.
*/
int64_t esp_timer_get_next_alarm();
/**
* @brief Dump the list of timers to a stream
*
* If CONFIG_ESP_TIMER_PROFILING option is enabled, this prints the list of all
* the existing timers. Otherwise, only the list active timers is printed.
*
* The format is:
*
* name period alarm times_armed times_triggered total_callback_run_time
*
* where:
*
* name — timer name (if CONFIG_ESP_TIMER_PROFILING is defined), or timer pointer
* period — period of timer, in microseconds, or 0 for one-shot timer
* alarm - time of the next alarm, in microseconds since boot, or 0 if the timer
* is not started
*
* The following fields are printed if CONFIG_ESP_TIMER_PROFILING is defined:
*
* times_armed — number of times the timer was armed via esp_timer_start_X
* times_triggered - number of times the callback was called
* total_callback_run_time - total time taken by callback to execute, across all calls
*
* @param stream stream (such as stdout) to dump the information to
* @return
* - ESP_OK on success
* - ESP_ERR_NO_MEM if can not allocate temporary buffer for the output
*/
esp_err_t esp_timer_dump(FILE* stream);
#ifdef __cplusplus
}
#endif

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_TYPES_H__
#define __ESP_TYPES_H__
#ifdef __GNUC__
#include <sys/cdefs.h>
#endif /*__GNUC__*/
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#endif /* __ESP_TYPES_H__ */

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tools/sdk/include/esp32/esp_wifi.h
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// Hardware crypto support Copyright 2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_WIFI_CRYPTO_TYPES_H__
#define __ESP_WIFI_CRYPTO_TYPES_H__
/* This is an internal API header for configuring the implementation used for WiFi cryptographic
operations.
During normal operation, you don't need to use any of these types or functions in this header.
See esp_wifi.h & esp_wifi_types.h instead.
*/
#ifdef __cplusplus
extern "C" {
#endif
#define ESP_WIFI_CRYPTO_VERSION 0x00000001
/*
* Enumeration for hash operations.
* When WPA2 is connecting, this enum is used to
* request a hash algorithm via crypto_hash_xxx functions.
*/
typedef enum {
ESP_CRYPTO_HASH_ALG_MD5, ESP_CRYPTO_HASH_ALG_SHA1,
ESP_CRYPTO_HASH_ALG_HMAC_MD5, ESP_CRYPTO_HASH_ALG_HMAC_SHA1,
ESP_CRYPTO_HASH_ALG_SHA256, ESP_CRYPTO_HASH_ALG_HMAC_SHA256
}esp_crypto_hash_alg_t;
/*
* Enumeration for block cipher operations.
* When WPA2 is connecting, this enum is used to request a block
* cipher algorithm via crypto_cipher_xxx functions.
*/
typedef enum {
ESP_CRYPTO_CIPHER_NULL, ESP_CRYPTO_CIPHER_ALG_AES, ESP_CRYPTO_CIPHER_ALG_3DES,
ESP_CRYPTO_CIPHER_ALG_DES, ESP_CRYPTO_CIPHER_ALG_RC2, ESP_CRYPTO_CIPHER_ALG_RC4
} esp_crypto_cipher_alg_t;
/*
* This structure is about the algorithm when do crypto_hash operation, for detail,
* please reference to the structure crypto_hash.
*/
typedef struct crypto_hash esp_crypto_hash_t;
/*
* This structure is about the algorithm when do crypto_cipher operation, for detail,
* please reference to the structure crypto_cipher.
*/
typedef struct crypto_cipher esp_crypto_cipher_t;
/**
* @brief The crypto callback function used in wpa enterprise hash operation when connect.
* Initialize a esp_crypto_hash_t structure.
*
* @param alg Hash algorithm.
* @param key Key for keyed hash (e.g., HMAC) or %NULL if not needed.
* @param key_len Length of the key in bytes
*
*/
typedef esp_crypto_hash_t * (*esp_crypto_hash_init_t)(esp_crypto_hash_alg_t alg, const unsigned char *key, int key_len);
/**
* @brief The crypto callback function used in wpa enterprise hash operation when connect.
* Add data to hash calculation.
*
* @param ctz Context pointer from esp_crypto_hash_init_t function.
* @param data Data buffer to add.
* @param len Length of the buffer.
*
*/
typedef void (*esp_crypto_hash_update_t)(esp_crypto_hash_t *ctx, const unsigned char *data, int len);
/**
* @brief The crypto callback function used in wpa enterprise hash operation when connect.
* Complete hash calculation.
*
* @param ctz Context pointer from esp_crypto_hash_init_t function.
* @param hash Buffer for hash value or %NULL if caller is just freeing the hash
* context.
* @param len Pointer to length of the buffer or %NULL if caller is just freeing the
* hash context; on return, this is set to the actual length of the hash value
* Returns: 0 on success, -1 if buffer is too small (len set to needed length),
* or -2 on other failures (including failed crypto_hash_update() operations)
*
*/
typedef int (*esp_crypto_hash_finish_t)(esp_crypto_hash_t *ctx, unsigned char *hash, int *len);
/**
* @brief The AES callback function when do WPS connect.
*
* @param key Encryption key.
* @param iv Encryption IV for CBC mode (16 bytes).
* @param data Data to encrypt in-place.
* @param data_len Length of data in bytes (must be divisible by 16)
*/
typedef int (*esp_aes_128_encrypt_t)(const unsigned char *key, const unsigned char *iv, unsigned char *data, int data_len);
/**
* @brief The AES callback function when do WPS connect.
*
* @param key Decryption key.
* @param iv Decryption IV for CBC mode (16 bytes).
* @param data Data to decrypt in-place.
* @param data_len Length of data in bytes (must be divisible by 16)
*
*/
typedef int (*esp_aes_128_decrypt_t)(const unsigned char *key, const unsigned char *iv, unsigned char *data, int data_len);
/**
* @brief The AES callback function when do STA connect.
*
* @param kek 16-octet Key encryption key (KEK).
* @param n Length of the plaintext key in 64-bit units;
* @param plain Plaintext key to be wrapped, n * 64 bits
* @param cipher Wrapped key, (n + 1) * 64 bits
*
*/
typedef int (*esp_aes_wrap_t)(const unsigned char *kek, int n, const unsigned char *plain, unsigned char *cipher);
/**
* @brief The AES callback function when do STA connect.
*
* @param kek 16-octet Key decryption key (KEK).
* @param n Length of the plaintext key in 64-bit units;
* @param cipher Wrapped key to be unwrapped, (n + 1) * 64 bits
* @param plain Plaintext key, n * 64 bits
*
*/
typedef int (*esp_aes_unwrap_t)(const unsigned char *kek, int n, const unsigned char *cipher, unsigned char *plain);
/**
* @brief The crypto callback function used in wpa enterprise cipher operation when connect.
* Initialize a esp_crypto_cipher_t structure.
*
* @param alg cipher algorithm.
* @param iv Initialization vector for block ciphers or %NULL for stream ciphers.
* @param key Cipher key
* @param key_len Length of key in bytes
*
*/
typedef esp_crypto_cipher_t * (*esp_crypto_cipher_init_t)(esp_crypto_cipher_alg_t alg, const unsigned char *iv, const unsigned char *key, int key_len);
/**
* @brief The crypto callback function used in wpa enterprise cipher operation when connect.
* Cipher encrypt.
*
* @param ctx Context pointer from esp_crypto_cipher_init_t callback function.
* @param plain Plaintext to cipher.
* @param crypt Resulting ciphertext.
* @param len Length of the plaintext.
*
*/
typedef int (*esp_crypto_cipher_encrypt_t)(esp_crypto_cipher_t *ctx,
const unsigned char *plain, unsigned char *crypt, int len);
/**
* @brief The crypto callback function used in wpa enterprise cipher operation when connect.
* Cipher decrypt.
*
* @param ctx Context pointer from esp_crypto_cipher_init_t callback function.
* @param crypt Ciphertext to decrypt.
* @param plain Resulting plaintext.
* @param len Length of the cipher text.
*
*/
typedef int (*esp_crypto_cipher_decrypt_t)(esp_crypto_cipher_t *ctx,
const unsigned char *crypt, unsigned char *plain, int len);
/**
* @brief The crypto callback function used in wpa enterprise cipher operation when connect.
* Free cipher context.
*
* @param ctx Context pointer from esp_crypto_cipher_init_t callback function.
*
*/
typedef void (*esp_crypto_cipher_deinit_t)(esp_crypto_cipher_t *ctx);
/**
* @brief The SHA256 callback function when do WPS connect.
*
* @param key Key for HMAC operations.
* @param key_len Length of the key in bytes.
* @param data Pointers to the data area.
* @param data_len Length of the data area.
* @param mac Buffer for the hash (20 bytes).
*
*/
typedef void (*esp_hmac_sha256_t)(const unsigned char *key, int key_len, const unsigned char *data,
int data_len, unsigned char *mac);
/**
* @brief The SHA256 callback function when do WPS connect.
*
* @param key Key for HMAC operations.
* @param key_len Length of the key in bytes.
* @param num_elem Number of elements in the data vector.
* @param addr Pointers to the data areas.
* @param len Lengths of the data blocks.
* @param mac Buffer for the hash (32 bytes).
*
*/
typedef void (*esp_hmac_sha256_vector_t)(const unsigned char *key, int key_len, int num_elem,
const unsigned char *addr[], const int *len, unsigned char *mac);
/**
* @brief The AES callback function when do STA connect.
*
* @param key Key for PRF.
* @param key_len Length of the key in bytes.
* @param label A unique label for each purpose of the PRF.
* @param data Extra data to bind into the key.
* @param data_len Length of the data.
* @param buf Buffer for the generated pseudo-random key.
* @param buf_len Number of bytes of key to generate.
*
*/
typedef void (*esp_sha256_prf_t)(const unsigned char *key, int key_len, const char *label,
const unsigned char *data, int data_len, unsigned char *buf, int buf_len);
/**
* @brief The SHA256 callback function when do WPS connect.
*
* @param num_elem Number of elements in the data vector.
* @param addr Pointers to the data areas.
* @param len Lengths of the data blocks.
* @paramac Buffer for the hash.
*
*/
typedef int (*esp_sha256_vector_t)(int num_elem, const unsigned char *addr[], const int *len,
unsigned char *mac);
/**
* @brief The bignum calculate callback function used when do connect.
* In WPS process, it used to calculate public key and private key.
*
* @param base Base integer (big endian byte array).
* @param base_len Length of base integer in bytes.
* @param power Power integer (big endian byte array).
* @param power_len Length of power integer in bytes.
* @param modulus Modulus integer (big endian byte array).
* @param modulus_len Length of modulus integer in bytes.
* @param result Buffer for the result.
* @param result_len Result length (max buffer size on input, real len on output).
*
*/
typedef int (*esp_crypto_mod_exp_t)(const unsigned char *base, int base_len,
const unsigned char *power, int power_len,
const unsigned char *modulus, int modulus_len,
unsigned char *result, unsigned int *result_len);
/**
* @brief HMAC-MD5 over data buffer (RFC 2104)'
*
* @key: Key for HMAC operations
* @key_len: Length of the key in bytes
* @data: Pointers to the data area
* @data_len: Length of the data area
* @mac: Buffer for the hash (16 bytes)
* Returns: 0 on success, -1 on failure
*/
typedef int (*esp_hmac_md5_t)(const unsigned char *key, unsigned int key_len, const unsigned char *data,
unsigned int data_len, unsigned char *mac);
/**
* @brief HMAC-MD5 over data vector (RFC 2104)
*
* @key: Key for HMAC operations
* @key_len: Length of the key in bytes
* @num_elem: Number of elements in the data vector
* @addr: Pointers to the data areas
* @len: Lengths of the data blocks
* @mac: Buffer for the hash (16 bytes)
* Returns: 0 on success, -1 on failure
*/
typedef int (*esp_hmac_md5_vector_t)(const unsigned char *key, unsigned int key_len, unsigned int num_elem,
const unsigned char *addr[], const unsigned int *len, unsigned char *mac);
/**
* @brief HMAC-SHA1 over data buffer (RFC 2104)
*
* @key: Key for HMAC operations
* @key_len: Length of the key in bytes
* @data: Pointers to the data area
* @data_len: Length of the data area
* @mac: Buffer for the hash (20 bytes)
* Returns: 0 on success, -1 of failure
*/
typedef int (*esp_hmac_sha1_t)(const unsigned char *key, unsigned int key_len, const unsigned char *data,
unsigned int data_len, unsigned char *mac);
/**
* @brief HMAC-SHA1 over data vector (RFC 2104)
*
* @key: Key for HMAC operations
* @key_len: Length of the key in bytes
* @num_elem: Number of elements in the data vector
* @addr: Pointers to the data areas
* @len: Lengths of the data blocks
* @mac: Buffer for the hash (20 bytes)
* Returns: 0 on success, -1 on failure
*/
typedef int (*esp_hmac_sha1_vector_t)(const unsigned char *key, unsigned int key_len, unsigned int num_elem,
const unsigned char *addr[], const unsigned int *len, unsigned char *mac);
/**
* @brief SHA1-based Pseudo-Random Function (PRF) (IEEE 802.11i, 8.5.1.1)
*
* @key: Key for PRF
* @key_len: Length of the key in bytes
* @label: A unique label for each purpose of the PRF
* @data: Extra data to bind into the key
* @data_len: Length of the data
* @buf: Buffer for the generated pseudo-random key
* @buf_len: Number of bytes of key to generate
* Returns: 0 on success, -1 of failure
*
* This function is used to derive new, cryptographically separate keys from a
* given key (e.g., PMK in IEEE 802.11i).
*/
typedef int (*esp_sha1_prf_t)(const unsigned char *key, unsigned int key_len, const char *label,
const unsigned char *data, unsigned int data_len, unsigned char *buf, unsigned int buf_len);
/**
* @brief SHA-1 hash for data vector
*
* @num_elem: Number of elements in the data vector
* @addr: Pointers to the data areas
* @len: Lengths of the data blocks
* @mac: Buffer for the hash
* Returns: 0 on success, -1 on failure
*/
typedef int (*esp_sha1_vector_t)(unsigned int num_elem, const unsigned char *addr[], const unsigned int *len,
unsigned char *mac);
/**
* @brief SHA1-based key derivation function (PBKDF2) for IEEE 802.11i
*
* @passphrase: ASCII passphrase
* @ssid: SSID
* @ssid_len: SSID length in bytes
* @iterations: Number of iterations to run
* @buf: Buffer for the generated key
* @buflen: Length of the buffer in bytes
* Returns: 0 on success, -1 of failure
*
* This function is used to derive PSK for WPA-PSK. For this protocol,
* iterations is set to 4096 and buflen to 32. This function is described in
* IEEE Std 802.11-2004, Clause H.4. The main construction is from PKCS#5 v2.0.
*/
typedef int (*esp_pbkdf2_sha1_t)(const char *passphrase, const char *ssid, unsigned int ssid_len,
int iterations, unsigned char *buf, unsigned int buflen);
/**
* @brief XOR RC4 stream to given data with skip-stream-start
*
* @key: RC4 key
* @keylen: RC4 key length
* @skip: number of bytes to skip from the beginning of the RC4 stream
* @data: data to be XOR'ed with RC4 stream
* @data_len: buf length
* Returns: 0 on success, -1 on failure
*
* Generate RC4 pseudo random stream for the given key, skip beginning of the
* stream, and XOR the end result with the data buffer to perform RC4
* encryption/decryption.
*/
typedef int (*esp_rc4_skip_t)(const unsigned char *key, unsigned int keylen, unsigned int skip,
unsigned char *data, unsigned int data_len);
/**
* @brief MD5 hash for data vector
*
* @num_elem: Number of elements in the data vector
* @addr: Pointers to the data areas
* @len: Lengths of the data blocks
* @mac: Buffer for the hash
* Returns: 0 on success, -1 on failure
*/
typedef int (*esp_md5_vector_t)(unsigned int num_elem, const unsigned char *addr[], const unsigned int *len,
unsigned char *mac);
/**
* @brief Encrypt one AES block
*
* @ctx: Context pointer from aes_encrypt_init()
* @plain: Plaintext data to be encrypted (16 bytes)
* @crypt: Buffer for the encrypted data (16 bytes)
*/
typedef void (*esp_aes_encrypt_t)(void *ctx, const unsigned char *plain, unsigned char *crypt);
/**
* @brief Initialize AES for encryption
*
* @key: Encryption key
* @len: Key length in bytes (usually 16, i.e., 128 bits)
* Returns: Pointer to context data or %NULL on failure
*/
typedef void * (*esp_aes_encrypt_init_t)(const unsigned char *key, unsigned int len);
/**
* @brief Deinitialize AES encryption
*
* @ctx: Context pointer from aes_encrypt_init()
*/
typedef void (*esp_aes_encrypt_deinit_t)(void *ctx);
/**
* @brief Decrypt one AES block
*
* @ctx: Context pointer from aes_encrypt_init()
* @crypt: Encrypted data (16 bytes)
* @plain: Buffer for the decrypted data (16 bytes)
*/
typedef void (*esp_aes_decrypt_t)(void *ctx, const unsigned char *crypt, unsigned char *plain);
/**
* @brief Initialize AES for decryption
*
* @key: Decryption key
* @len: Key length in bytes (usually 16, i.e., 128 bits)
* Returns: Pointer to context data or %NULL on failure
*/
typedef void * (*esp_aes_decrypt_init_t)(const unsigned char *key, unsigned int len);
/**
* @brief Deinitialize AES decryption
*
* @ctx: Context pointer from aes_encrypt_init()
*/
typedef void (*esp_aes_decrypt_deinit_t)(void *ctx);
/**
* @brief Initialize TLS library
*
* @conf: Configuration data for TLS library
* Returns: Context data to be used as tls_ctx in calls to other functions,
* or %NULL on failure.
*
* Called once during program startup and once for each RSN pre-authentication
* session. In other words, there can be two concurrent TLS contexts. If global
* library initialization is needed (i.e., one that is shared between both
* authentication types), the TLS library wrapper should maintain a reference
* counter and do global initialization only when moving from 0 to 1 reference.
*/
typedef void * (*esp_tls_init_t)(void);
/**
* @brief Deinitialize TLS library
*
* @tls_ctx: TLS context data from tls_init()
*
* Called once during program shutdown and once for each RSN pre-authentication
* session. If global library deinitialization is needed (i.e., one that is
* shared between both authentication types), the TLS library wrapper should
* maintain a reference counter and do global deinitialization only when moving
* from 1 to 0 references.
*/
typedef void (*esp_tls_deinit_t)(void *tls_ctx);
/**
* @brief Add certificate and private key for connect
* @sm: eap state machine
*
* Returns: 0 for success, -1 state machine didn't exist, -2 short of certificate or key
*/
typedef int (*esp_eap_peer_blob_init_t)(void *sm);
/**
* @brief delete the certificate and private
*
* @sm: eap state machine
*
*/
typedef void (*esp_eap_peer_blob_deinit_t)(void *sm);
/**
* @brief Initialize the eap state machine
*
* @sm: eap state machine
* @private_key_passwd: the start address of private_key_passwd
* @private_key_passwd_len: length of private_key_password
*
* Returns: 0 is success, -1 state machine didn't exist, -2 short of parameters
*
*/
typedef int (*esp_eap_peer_config_init_t)(void *sm, unsigned char *private_key_passwd,int private_key_passwd_len);
/**
* @brief Deinit the eap state machine
*
* @sm: eap state machine
*
*/
typedef void (*esp_eap_peer_config_deinit_t)(void *sm);
/**
* @brief Register the eap method
*
* Note: ESP32 only support PEAP/TTLS/TLS three eap methods now.
*
*/
typedef int (*esp_eap_peer_register_methods_t)(void);
/**
* @brief remove the eap method
*
* Note: ESP32 only support PEAP/TTLS/TLS three eap methods now.
*
*/
typedef void (*esp_eap_peer_unregister_methods_t)(void);
/**
* @brief remove the eap method before build new connect
*
* @sm: eap state machine
* @txt: not used now
*/
typedef void (*esp_eap_deinit_prev_method_t)(void *sm, const char *txt);
/**
* @brief Get EAP method based on type number
*
* @vendor: EAP Vendor-Id (0 = IETF)
* @method: EAP type number
* Returns: Pointer to EAP method or %NULL if not found
*/
typedef const void * (*esp_eap_peer_get_eap_method_t)(int vendor, int method);
/**
* @brief Abort EAP authentication
*
* @sm: Pointer to EAP state machine allocated with eap_peer_sm_init()
*
* Release system resources that have been allocated for the authentication
* session without fully deinitializing the EAP state machine.
*/
typedef void (*esp_eap_sm_abort_t)(void *sm);
/**
* @brief Build EAP-NAK for the current network
*
* @sm: Pointer to EAP state machine allocated with eap_peer_sm_init()
* @type: EAP type of the fail reason
* @id: EAP identifier for the packet
*
* This function allocates and builds a nak packet for the
* current network. The caller is responsible for freeing the returned data.
*/
typedef void * (*esp_eap_sm_build_nak_t)(void *sm, int type, unsigned char id);
/**
* @brief Build EAP-Identity/Response for the current network
*
* @sm: Pointer to EAP state machine allocated with eap_peer_sm_init()
* @id: EAP identifier for the packet
* @encrypted: Whether the packet is for encrypted tunnel (EAP phase 2)
* Returns: Pointer to the allocated EAP-Identity/Response packet or %NULL on
* failure
*
* This function allocates and builds an EAP-Identity/Response packet for the
* current network. The caller is responsible for freeing the returned data.
*/
typedef void * (*esp_eap_sm_build_identity_resp_t)(void *sm, unsigned char id, int encrypted);
/**
* @brief Allocate a buffer for an EAP message
*
* @vendor: Vendor-Id (0 = IETF)
* @type: EAP type
* @payload_len: Payload length in bytes (data after Type)
* @code: Message Code (EAP_CODE_*)
* @identifier: Identifier
* Returns: Pointer to the allocated message buffer or %NULL on error
*
* This function can be used to allocate a buffer for an EAP message and fill
* in the EAP header. This function is automatically using expanded EAP header
* if the selected Vendor-Id is not IETF. In other words, most EAP methods do
* not need to separately select which header type to use when using this
* function to allocate the message buffers. The returned buffer has room for
* payload_len bytes and has the EAP header and Type field already filled in.
*/
typedef void * (*esp_eap_msg_alloc_t)(int vendor, int type, unsigned int payload_len,
unsigned char code, unsigned char identifier);
/**
* @brief get the enrollee mac address
* @mac_addr: instore the mac address of enrollee
* @uuid: Universally Unique Identifer of the enrollee
*
*/
typedef void (*esp_uuid_gen_mac_addr_t)(const unsigned char *mac_addr, unsigned char *uuid);
/**
* @brief free the message after finish DH
*
*/
typedef void (*esp_dh5_free_t)(void *ctx);
/**
* @brief Build WPS IE for (Re)Association Request
*
* @req_type: Value for Request Type attribute
* Returns: WPS IE or %NULL on failure
*
* The caller is responsible for freeing the buffer.
*/
typedef void * (*esp_wps_build_assoc_req_ie_t)(int req_type);
/**
* @brief Build WPS IE for (Re)Association Response
*
* Returns: WPS IE or %NULL on failure
*
* The caller is responsible for freeing the buffer.
*/
typedef void * (*esp_wps_build_assoc_resp_ie_t)(void);
/**
* @brief Build WPS IE for Probe Request
*
* @pw_id: Password ID (DEV_PW_PUSHBUTTON for active PBC and DEV_PW_DEFAULT for
* most other use cases)
* @dev: Device attributes
* @uuid: Own UUID
* @req_type: Value for Request Type attribute
* @num_req_dev_types: Number of requested device types
* @req_dev_types: Requested device types (8 * num_req_dev_types octets) or
* %NULL if none
* Returns: WPS IE or %NULL on failure
*
* The caller is responsible for freeing the buffer.
*/
typedef void * (*esp_wps_build_probe_req_ie_t)(uint16_t pw_id, void *dev, const unsigned char *uuid,
int req_type, unsigned int num_req_dev_types, const unsigned char *req_dev_types);
/**
* @brief build public key for exchange in M1
*
*
*/
typedef int (*esp_wps_build_public_key_t)(void *wps, void *msg, int mode);
/**
* @brief get the wps information in exchange password
*
*
*/
typedef void * (*esp_wps_enrollee_get_msg_t)(void *wps, void *op_code);
/**
* @brief deal with the wps information in exchange password
*
*
*/
typedef int (*esp_wps_enrollee_process_msg_t)(void *wps, int op_code, const void *msg);
/**
* @brief Generate a random PIN
*
* Returns: Eight digit PIN (i.e., including the checksum digit)
*/
typedef unsigned int (*esp_wps_generate_pin_t)(void);
/**
* @brief Check whether WPS IE indicates active PIN
*
* @msg: WPS IE contents from Beacon or Probe Response frame
* Returns: 1 if PIN Registrar is active, 0 if not
*/
typedef int (*esp_wps_is_selected_pin_registrar_t)(const void *msg, unsigned char *bssid);
/**
* @brief Check whether WPS IE indicates active PBC
*
* @msg: WPS IE contents from Beacon or Probe Response frame
* Returns: 1 if PBC Registrar is active, 0 if not
*/
typedef int (*esp_wps_is_selected_pbc_registrar_t)(const void *msg, unsigned char *bssid);
/**
* @brief The crypto callback function structure used when do station security connect.
* The structure can be set as software crypto or the crypto optimized by ESP32
* hardware.
*/
typedef struct {
uint32_t size;
uint32_t version;
esp_aes_wrap_t aes_wrap; /**< station connect function used when send EAPOL frame */
esp_aes_unwrap_t aes_unwrap; /**< station connect function used when decrypt key data */
esp_hmac_sha256_vector_t hmac_sha256_vector; /**< station connect function used when check MIC */
esp_sha256_prf_t sha256_prf; /**< station connect function used when check MIC */
esp_hmac_md5_t hmac_md5;
esp_hmac_md5_vector_t hamc_md5_vector;
esp_hmac_sha1_t hmac_sha1;
esp_hmac_sha1_vector_t hmac_sha1_vector;
esp_sha1_prf_t sha1_prf;
esp_sha1_vector_t sha1_vector;
esp_pbkdf2_sha1_t pbkdf2_sha1;
esp_rc4_skip_t rc4_skip;
esp_md5_vector_t md5_vector;
esp_aes_encrypt_t aes_encrypt;
esp_aes_encrypt_init_t aes_encrypt_init;
esp_aes_encrypt_deinit_t aes_encrypt_deinit;
esp_aes_decrypt_t aes_decrypt;
esp_aes_decrypt_init_t aes_decrypt_init;
esp_aes_decrypt_deinit_t aes_decrypt_deinit;
}wpa_crypto_funcs_t;
/**
* @brief The crypto callback function structure used when do WPS process. The
* structure can be set as software crypto or the crypto optimized by ESP32
* hardware.
*/
typedef struct{
uint32_t size;
uint32_t version;
esp_aes_128_encrypt_t aes_128_encrypt; /**< function used to process message when do WPS */
esp_aes_128_decrypt_t aes_128_decrypt; /**< function used to process message when do WPS */
esp_crypto_mod_exp_t crypto_mod_exp; /**< function used to calculate public key and private key */
esp_hmac_sha256_t hmac_sha256; /**< function used to get attribute */
esp_hmac_sha256_vector_t hmac_sha256_vector; /**< function used to process message when do WPS */
esp_sha256_vector_t sha256_vector; /**< function used to process message when do WPS */
esp_uuid_gen_mac_addr_t uuid_gen_mac_addr;
esp_dh5_free_t dh5_free;
esp_wps_build_assoc_req_ie_t wps_build_assoc_req_ie;
esp_wps_build_assoc_resp_ie_t wps_build_assoc_resp_ie;
esp_wps_build_probe_req_ie_t wps_build_probe_req_ie;
esp_wps_build_public_key_t wps_build_public_key;
esp_wps_enrollee_get_msg_t wps_enrollee_get_msg;
esp_wps_enrollee_process_msg_t wps_enrollee_process_msg;
esp_wps_generate_pin_t wps_generate_pin;
esp_wps_is_selected_pin_registrar_t wps_is_selected_pin_registrar;
esp_wps_is_selected_pbc_registrar_t wps_is_selected_pbc_registrar;
esp_eap_msg_alloc_t eap_msg_alloc;
}wps_crypto_funcs_t;
/**
* @brief The crypto callback function structure used when do WPA enterprise connect.
* The structure can be set as software crypto or the crypto optimized by ESP32
* hardware.
*/
typedef struct {
uint32_t size;
uint32_t version;
esp_crypto_hash_init_t crypto_hash_init; /**< function used to initialize a crypto_hash structure when use TLSV1 */
esp_crypto_hash_update_t crypto_hash_update; /**< function used to calculate hash data when use TLSV1 */
esp_crypto_hash_finish_t crypto_hash_finish; /**< function used to finish the hash calculate when use TLSV1 */
esp_crypto_cipher_init_t crypto_cipher_init; /**< function used to initialize a crypt_cipher structure when use TLSV1 */
esp_crypto_cipher_encrypt_t crypto_cipher_encrypt; /**< function used to encrypt cipher when use TLSV1 */
esp_crypto_cipher_decrypt_t crypto_cipher_decrypt; /**< function used to decrypt cipher when use TLSV1 */
esp_crypto_cipher_deinit_t crypto_cipher_deinit; /**< function used to free context when use TLSV1 */
esp_crypto_mod_exp_t crypto_mod_exp; /**< function used to do key exchange when use TLSV1 */
esp_sha256_vector_t sha256_vector; /**< function used to do X.509v3 certificate parsing and processing */
esp_tls_init_t tls_init;
esp_tls_deinit_t tls_deinit;
esp_eap_peer_blob_init_t eap_peer_blob_init;
esp_eap_peer_blob_deinit_t eap_peer_blob_deinit;
esp_eap_peer_config_init_t eap_peer_config_init;
esp_eap_peer_config_deinit_t eap_peer_config_deinit;
esp_eap_peer_register_methods_t eap_peer_register_methods;
esp_eap_peer_unregister_methods_t eap_peer_unregister_methods;
esp_eap_deinit_prev_method_t eap_deinit_prev_method;
esp_eap_peer_get_eap_method_t eap_peer_get_eap_method;
esp_eap_sm_abort_t eap_sm_abort;
esp_eap_sm_build_nak_t eap_sm_build_nak;
esp_eap_sm_build_identity_resp_t eap_sm_build_identity_resp;
esp_eap_msg_alloc_t eap_msg_alloc;
} wpa2_crypto_funcs_t;
/**
* @brief The crypto callback function structure used in mesh vendor IE encryption. The
* structure can be set as software crypto or the crypto optimized by ESP32
* hardware.
*/
typedef struct{
esp_aes_128_encrypt_t aes_128_encrypt; /**< function used in mesh vendor IE encryption */
esp_aes_128_decrypt_t aes_128_decrypt; /**< function used in mesh vendor IE decryption */
} mesh_crypto_funcs_t;
#ifdef __cplusplus
}
#endif
#endif

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tools/sdk/include/esp32/esp_wifi_internal.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* All the APIs declared here are internal only APIs, it can only be used by
* espressif internal modules, such as SSC, LWIP, TCPIP adapter etc, espressif
* customers are not recommended to use them.
*
* If someone really want to use specified APIs declared in here, please contact
* espressif AE/developer to make sure you know the limitations or risk of
* the API, otherwise you may get unexpected behavior!!!
*
*/
#ifndef __ESP_WIFI_INTERNAL_H__
#define __ESP_WIFI_INTERNAL_H__
#include <stdint.h>
#include <stdbool.h>
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#include "rom/queue.h"
#include "esp_err.h"
#include "esp_wifi_types.h"
#include "esp_event.h"
#include "esp_wifi.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
QueueHandle_t handle; /**< FreeRTOS queue handler */
void *storage; /**< storage for FreeRTOS queue */
} wifi_static_queue_t;
/**
* @brief WiFi log level
*
*/
typedef enum {
WIFI_LOG_ERROR = 0, /*enabled by default*/
WIFI_LOG_WARNING, /*enabled by default*/
WIFI_LOG_INFO, /*enabled by default*/
WIFI_LOG_DEBUG, /*can be set in menuconfig*/
WIFI_LOG_VERBOSE, /*can be set in menuconfig*/
} wifi_log_level_t;
/**
* @brief WiFi log module definition
*
*/
typedef enum {
WIFI_LOG_MODULE_ALL = 0, /*all log modules */
WIFI_LOG_MODULE_WIFI, /*logs related to WiFi*/
WIFI_LOG_MODULE_COEX, /*logs related to WiFi and BT(or BLE) coexist*/
WIFI_LOG_MODULE_MESH, /*logs related to Mesh*/
} wifi_log_module_t;
/**
* @brief WiFi log submodule definition
*
*/
#define WIFI_LOG_SUBMODULE_ALL (0) /*all log submodules*/
#define WIFI_LOG_SUBMODULE_INIT (1) /*logs related to initialization*/
#define WIFI_LOG_SUBMODULE_IOCTL (1<<1) /*logs related to API calling*/
#define WIFI_LOG_SUBMODULE_CONN (1<<2) /*logs related to connecting*/
#define WIFI_LOG_SUBMODULE_SCAN (1<<3) /*logs related to scaning*/
/**
* @brief Initialize Wi-Fi Driver
* Alloc resource for WiFi driver, such as WiFi control structure, RX/TX buffer,
* WiFi NVS structure among others.
*
* For the most part, you need not call this function directly. It gets called
* from esp_wifi_init().
*
* This function may be called, if you only need to initialize the Wi-Fi driver
* without having to use the network stack on top.
*
* @param config provide WiFi init configuration
*
* @return
* - ESP_OK: succeed
* - ESP_ERR_NO_MEM: out of memory
* - others: refer to error code esp_err.h
*/
esp_err_t esp_wifi_init_internal(const wifi_init_config_t *config);
/**
* @brief get whether the wifi driver is allowed to transmit data or not
*
* @return
* - true : upper layer should stop to transmit data to wifi driver
* - false : upper layer can transmit data to wifi driver
*/
bool esp_wifi_internal_tx_is_stop(void);
/**
* @brief free the rx buffer which allocated by wifi driver
*
* @param void* buffer: rx buffer pointer
*/
void esp_wifi_internal_free_rx_buffer(void* buffer);
/**
* @brief transmit the buffer via wifi driver
*
* @param wifi_interface_t wifi_if : wifi interface id
* @param void *buffer : the buffer to be tansmit
* @param uint16_t len : the length of buffer
*
* @return
* - ERR_OK : Successfully transmit the buffer to wifi driver
* - ERR_MEM : Out of memory
* - ERR_IF : WiFi driver error
* - ERR_ARG : Invalid argument
*/
int esp_wifi_internal_tx(wifi_interface_t wifi_if, void *buffer, uint16_t len);
/**
* @brief The WiFi RX callback function
*
* Each time the WiFi need to forward the packets to high layer, the callback function will be called
*/
typedef esp_err_t (*wifi_rxcb_t)(void *buffer, uint16_t len, void *eb);
/**
* @brief Set the WiFi RX callback
*
* @attention 1. Currently we support only one RX callback for each interface
*
* @param wifi_interface_t ifx : interface
* @param wifi_rxcb_t fn : WiFi RX callback
*
* @return
* - ESP_OK : succeed
* - others : fail
*/
esp_err_t esp_wifi_internal_reg_rxcb(wifi_interface_t ifx, wifi_rxcb_t fn);
/**
* @brief Notify WIFI driver that the station got ip successfully
*
* @return
* - ESP_OK : succeed
* - others : fail
*/
esp_err_t esp_wifi_internal_set_sta_ip(void);
/**
* @brief enable or disable transmitting WiFi MAC frame with fixed rate
*
* @attention 1. If fixed rate is enabled, both management and data frame are transmitted with fixed rate
* @attention 2. Make sure that the receiver is able to receive the frame with the fixed rate if you want the frame to be received
*
* @param ifx : wifi interface
* @param en : false - disable, true - enable
* @param rate : PHY rate
*
* @return
* - ERR_OK : succeed
* - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
* - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
* - ESP_ERR_WIFI_IF : invalid WiFi interface
* - ESP_ERR_INVALID_ARG : invalid rate
* - ESP_ERR_NOT_SUPPORTED : do not support to set fixed rate if TX AMPDU is enabled
*/
esp_err_t esp_wifi_internal_set_fix_rate(wifi_interface_t ifx, bool en, wifi_phy_rate_t rate);
/**
* @brief Check the MD5 values of the OS adapter header files in IDF and WiFi library
*
* @attention 1. It is used for internal CI version check
*
* @return
* - ESP_OK : succeed
* - ESP_WIFI_INVALID_ARG : MD5 check fail
*/
esp_err_t esp_wifi_internal_osi_funcs_md5_check(const char *md5);
/**
* @brief Check the MD5 values of the crypto types header files in IDF and WiFi library
*
* @attention 1. It is used for internal CI version check
*
* @return
* - ESP_OK : succeed
* - ESP_WIFI_INVALID_ARG : MD5 check fail
*/
esp_err_t esp_wifi_internal_crypto_funcs_md5_check(const char *md5);
/**
* @brief Check the MD5 values of the esp_wifi_types.h in IDF and WiFi library
*
* @attention 1. It is used for internal CI version check
*
* @return
* - ESP_OK : succeed
* - ESP_WIFI_INVALID_ARG : MD5 check fail
*/
esp_err_t esp_wifi_internal_wifi_type_md5_check(const char *md5);
/**
* @brief Check the MD5 values of the esp_wifi.h in IDF and WiFi library
*
* @attention 1. It is used for internal CI version check
*
* @return
* - ESP_OK : succeed
* - ESP_WIFI_INVALID_ARG : MD5 check fail
*/
esp_err_t esp_wifi_internal_esp_wifi_md5_check(const char *md5);
/**
* @brief Allocate a chunk of memory for WiFi driver
*
* @attention This API is not used for DMA memory allocation.
*
* @param size_t size : Size, in bytes, of the amount of memory to allocate
*
* @return A pointer to the memory allocated on success, NULL on failure
*/
void *wifi_malloc( size_t size );
/**
* @brief Reallocate a chunk of memory for WiFi driver
*
* @attention This API is not used for DMA memory allocation.
*
* @param void * ptr : Pointer to previously allocated memory, or NULL for a new allocation.
* @param size_t size : Size, in bytes, of the amount of memory to allocate
*
* @return A pointer to the memory allocated on success, NULL on failure
*/
void *wifi_realloc( void *ptr, size_t size );
/**
* @brief Callocate memory for WiFi driver
*
* @attention This API is not used for DMA memory allocation.
*
* @param size_t n : Number of continuing chunks of memory to allocate
* @param size_t size : Size, in bytes, of the amount of memory to allocate
*
* @return A pointer to the memory allocated on success, NULL on failure
*/
void *wifi_calloc( size_t n, size_t size );
/**
* @brief Update WiFi MAC time
*
* @param uint32_t time_delta : time duration since the WiFi/BT common clock is disabled
*
* @return Always returns ESP_OK
*/
typedef esp_err_t (* wifi_mac_time_update_cb_t)( uint32_t time_delta );
/**
* @brief Update WiFi MAC time
*
* @param uint32_t time_delta : time duration since the WiFi/BT common clock is disabled
*
* @return Always returns ESP_OK
*/
esp_err_t esp_wifi_internal_update_mac_time( uint32_t time_delta );
/**
* @brief Set current WiFi log level
*
* @param level Log level.
*
* @return
* - ESP_OK: succeed
* - ESP_FAIL: level is invalid
*/
esp_err_t esp_wifi_internal_set_log_level(wifi_log_level_t level);
/**
* @brief Set current log module and submodule
*
* @param module Log module
* @param submodule Log submodule
* @param enable enable or disable
* If module == 0 && enable == 0, all log modules are disabled.
* If module == 0 && enable == 1, all log modules are enabled.
* If submodule == 0 && enable == 0, all log submodules are disabled.
* If submodule == 0 && enable == 1, all log submodules are enabled.
*
* @return
* - ESP_OK: succeed
* - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
* - ESP_ERR_WIFI_ARG: invalid argument
*/
esp_err_t esp_wifi_internal_set_log_mod(wifi_log_module_t module, uint32_t submodule, bool enable);
/**
* @brief Get current WiFi log info
*
* @param log_level the return log level.
* @param log_mod the return log module and submodule
*
* @return
* - ESP_OK: succeed
*/
esp_err_t esp_wifi_internal_get_log(wifi_log_level_t *log_level, uint32_t *log_mod);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_WIFI_H__ */

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// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef ESP_WIFI_OS_ADAPTER_H_
#define ESP_WIFI_OS_ADAPTER_H_
#include <stdarg.h>
#ifdef __cplusplus
extern "C" {
#endif
#define ESP_WIFI_OS_ADAPTER_VERSION 0x00000004
#define ESP_WIFI_OS_ADAPTER_MAGIC 0xDEADBEAF
#define OSI_FUNCS_TIME_BLOCKING 0xffffffff
#define OSI_QUEUE_SEND_FRONT 0
#define OSI_QUEUE_SEND_BACK 1
#define OSI_QUEUE_SEND_OVERWRITE 2
typedef struct {
int32_t _version;
void (*_set_isr)(int32_t n, void *f, void *arg);
void (*_ints_on)(uint32_t mask);
void (*_ints_off)(uint32_t mask);
void *(* _spin_lock_create)(void);
void (* _spin_lock_delete)(void *lock);
uint32_t (*_wifi_int_disable)(void *wifi_int_mux);
void (*_wifi_int_restore)(void *wifi_int_mux, uint32_t tmp);
void (*_task_yield_from_isr)(void);
void *(*_semphr_create)(uint32_t max, uint32_t init);
void (*_semphr_delete)(void *semphr);
int32_t (*_semphr_take)(void *semphr, uint32_t block_time_tick);
int32_t (*_semphr_give)(void *semphr);
void *(*_wifi_thread_semphr_get)(void);
void *(*_mutex_create)(void);
void *(*_recursive_mutex_create)(void);
void (*_mutex_delete)(void *mutex);
int32_t (*_mutex_lock)(void *mutex);
int32_t (*_mutex_unlock)(void *mutex);
void *(* _queue_create)(uint32_t queue_len, uint32_t item_size);
void (* _queue_delete)(void *queue);
int32_t (* _queue_send)(void *queue, void *item, uint32_t block_time_tick);
int32_t (* _queue_send_from_isr)(void *queue, void *item, void *hptw);
int32_t (* _queue_send_to_back)(void *queue, void *item, uint32_t block_time_tick);
int32_t (* _queue_send_to_front)(void *queue, void *item, uint32_t block_time_tick);
int32_t (* _queue_recv)(void *queue, void *item, uint32_t block_time_tick);
uint32_t (* _queue_msg_waiting)(void *queue);
void *(* _event_group_create)(void);
void (* _event_group_delete)(void *event);
uint32_t (* _event_group_set_bits)(void *event, uint32_t bits);
uint32_t (* _event_group_clear_bits)(void *event, uint32_t bits);
uint32_t (* _event_group_wait_bits)(void *event, uint32_t bits_to_wait_for, int32_t clear_on_exit, int32_t wait_for_all_bits, uint32_t block_time_tick);
int32_t (* _task_create_pinned_to_core)(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id);
int32_t (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle);
void (* _task_delete)(void *task_handle);
void (* _task_delay)(uint32_t tick);
int32_t (* _task_ms_to_tick)(uint32_t ms);
void *(* _task_get_current_task)(void);
int32_t (* _task_get_max_priority)(void);
void *(* _malloc)(uint32_t size);
void (* _free)(void *p);
uint32_t (* _get_free_heap_size)(void);
uint32_t (* _rand)(void);
void (* _dport_access_stall_other_cpu_start_wrap)(void);
void (* _dport_access_stall_other_cpu_end_wrap)(void);
int32_t (* _phy_rf_deinit)(uint32_t module);
void (* _phy_load_cal_and_init)(uint32_t module);
int32_t (* _read_mac)(uint8_t* mac, uint32_t type);
void (* _timer_arm)(void *timer, uint32_t tmout, bool repeat);
void (* _timer_disarm)(void *timer);
void (* _timer_done)(void *ptimer);
void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg);
void (* _timer_arm_us)(void *ptimer, uint32_t us, bool repeat);
void (* _periph_module_enable)(uint32_t periph);
void (* _periph_module_disable)(uint32_t periph);
int64_t (* _esp_timer_get_time)(void);
int32_t (* _nvs_set_i8)(uint32_t handle, const char* key, int8_t value);
int32_t (* _nvs_get_i8)(uint32_t handle, const char* key, int8_t* out_value);
int32_t (* _nvs_set_u8)(uint32_t handle, const char* key, uint8_t value);
int32_t (* _nvs_get_u8)(uint32_t handle, const char* key, uint8_t* out_value);
int32_t (* _nvs_set_u16)(uint32_t handle, const char* key, uint16_t value);
int32_t (* _nvs_get_u16)(uint32_t handle, const char* key, uint16_t* out_value);
int32_t (* _nvs_open)(const char* name, uint32_t open_mode, uint32_t *out_handle);
void (* _nvs_close)(uint32_t handle);
int32_t (* _nvs_commit)(uint32_t handle);
int32_t (* _nvs_set_blob)(uint32_t handle, const char* key, const void* value, size_t length);
int32_t (* _nvs_get_blob)(uint32_t handle, const char* key, void* out_value, size_t* length);
int32_t (* _nvs_erase_key)(uint32_t handle, const char* key);
int32_t (* _get_random)(uint8_t *buf, size_t len);
int32_t (* _get_time)(void *t);
unsigned long (* _random)(void);
void (* _log_write)(uint32_t level, const char* tag, const char* format, ...);
uint32_t (* _log_timestamp)(void);
void * (* _malloc_internal)(size_t size);
void * (* _realloc_internal)(void *ptr, size_t size);
void * (* _calloc_internal)(size_t n, size_t size);
void * (* _zalloc_internal)(size_t size);
void * (* _wifi_malloc)(size_t size);
void * (* _wifi_realloc)(void *ptr, size_t size);
void * (* _wifi_calloc)(size_t n, size_t size);
void * (* _wifi_zalloc)(size_t size);
void * (* _wifi_create_queue)(int32_t queue_len, int32_t item_size);
void (* _wifi_delete_queue)(void * queue);
int32_t (* _modem_sleep_enter)(uint32_t module);
int32_t (* _modem_sleep_exit)(uint32_t module);
int32_t (* _modem_sleep_register)(uint32_t module);
int32_t (* _modem_sleep_deregister)(uint32_t module);
void (* _sc_ack_send)(void *param);
void (* _sc_ack_send_stop)(void);
uint32_t (* _coex_status_get)(void);
void (* _coex_condition_set)(uint32_t type, bool dissatisfy);
int32_t (* _coex_wifi_request)(uint32_t event, uint32_t latency, uint32_t duration);
int32_t (* _coex_wifi_release)(uint32_t event);
int32_t _magic;
} wifi_osi_funcs_t;
extern wifi_osi_funcs_t g_wifi_osi_funcs;
#ifdef __cplusplus
}
#endif
#endif /* ESP_WIFI_OS_ADAPTER_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_WIFI_TYPES_H__
#define __ESP_WIFI_TYPES_H__
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "esp_private/esp_wifi_types_private.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WIFI_MODE_NULL = 0, /**< null mode */
WIFI_MODE_STA, /**< WiFi station mode */
WIFI_MODE_AP, /**< WiFi soft-AP mode */
WIFI_MODE_APSTA, /**< WiFi station + soft-AP mode */
WIFI_MODE_MAX
} wifi_mode_t;
typedef esp_interface_t wifi_interface_t;
#define WIFI_IF_STA ESP_IF_WIFI_STA
#define WIFI_IF_AP ESP_IF_WIFI_AP
typedef enum {
WIFI_COUNTRY_POLICY_AUTO, /**< Country policy is auto, use the country info of AP to which the station is connected */
WIFI_COUNTRY_POLICY_MANUAL, /**< Country policy is manual, always use the configured country info */
} wifi_country_policy_t;
/** @brief Structure describing WiFi country-based regional restrictions. */
typedef struct {
char cc[3]; /**< country code string */
uint8_t schan; /**< start channel */
uint8_t nchan; /**< total channel number */
int8_t max_tx_power; /**< This field is used for getting WiFi maximum transmitting power, call esp_wifi_set_max_tx_power to set the maximum transmitting power. */
wifi_country_policy_t policy; /**< country policy */
} wifi_country_t;
typedef enum {
WIFI_AUTH_OPEN = 0, /**< authenticate mode : open */
WIFI_AUTH_WEP, /**< authenticate mode : WEP */
WIFI_AUTH_WPA_PSK, /**< authenticate mode : WPA_PSK */
WIFI_AUTH_WPA2_PSK, /**< authenticate mode : WPA2_PSK */
WIFI_AUTH_WPA_WPA2_PSK, /**< authenticate mode : WPA_WPA2_PSK */
WIFI_AUTH_WPA2_ENTERPRISE, /**< authenticate mode : WPA2_ENTERPRISE */
WIFI_AUTH_MAX
} wifi_auth_mode_t;
typedef enum {
WIFI_REASON_UNSPECIFIED = 1,
WIFI_REASON_AUTH_EXPIRE = 2,
WIFI_REASON_AUTH_LEAVE = 3,
WIFI_REASON_ASSOC_EXPIRE = 4,
WIFI_REASON_ASSOC_TOOMANY = 5,
WIFI_REASON_NOT_AUTHED = 6,
WIFI_REASON_NOT_ASSOCED = 7,
WIFI_REASON_ASSOC_LEAVE = 8,
WIFI_REASON_ASSOC_NOT_AUTHED = 9,
WIFI_REASON_DISASSOC_PWRCAP_BAD = 10,
WIFI_REASON_DISASSOC_SUPCHAN_BAD = 11,
WIFI_REASON_IE_INVALID = 13,
WIFI_REASON_MIC_FAILURE = 14,
WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,
WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT = 16,
WIFI_REASON_IE_IN_4WAY_DIFFERS = 17,
WIFI_REASON_GROUP_CIPHER_INVALID = 18,
WIFI_REASON_PAIRWISE_CIPHER_INVALID = 19,
WIFI_REASON_AKMP_INVALID = 20,
WIFI_REASON_UNSUPP_RSN_IE_VERSION = 21,
WIFI_REASON_INVALID_RSN_IE_CAP = 22,
WIFI_REASON_802_1X_AUTH_FAILED = 23,
WIFI_REASON_CIPHER_SUITE_REJECTED = 24,
WIFI_REASON_BEACON_TIMEOUT = 200,
WIFI_REASON_NO_AP_FOUND = 201,
WIFI_REASON_AUTH_FAIL = 202,
WIFI_REASON_ASSOC_FAIL = 203,
WIFI_REASON_HANDSHAKE_TIMEOUT = 204,
WIFI_REASON_CONNECTION_FAIL = 205,
} wifi_err_reason_t;
typedef enum {
WIFI_SECOND_CHAN_NONE = 0, /**< the channel width is HT20 */
WIFI_SECOND_CHAN_ABOVE, /**< the channel width is HT40 and the secondary channel is above the primary channel */
WIFI_SECOND_CHAN_BELOW, /**< the channel width is HT40 and the secondary channel is below the primary channel */
} wifi_second_chan_t;
typedef enum {
WIFI_SCAN_TYPE_ACTIVE = 0, /**< active scan */
WIFI_SCAN_TYPE_PASSIVE, /**< passive scan */
} wifi_scan_type_t;
/** @brief Range of active scan times per channel */
typedef struct {
uint32_t min; /**< minimum active scan time per channel, units: millisecond */
uint32_t max; /**< maximum active scan time per channel, units: millisecond, values above 1500ms may
cause station to disconnect from AP and are not recommended. */
} wifi_active_scan_time_t;
/** @brief Aggregate of active & passive scan time per channel */
typedef union {
wifi_active_scan_time_t active; /**< active scan time per channel, units: millisecond. */
uint32_t passive; /**< passive scan time per channel, units: millisecond, values above 1500ms may
cause station to disconnect from AP and are not recommended. */
} wifi_scan_time_t;
/** @brief Parameters for an SSID scan. */
typedef struct {
uint8_t *ssid; /**< SSID of AP */
uint8_t *bssid; /**< MAC address of AP */
uint8_t channel; /**< channel, scan the specific channel */
bool show_hidden; /**< enable to scan AP whose SSID is hidden */
wifi_scan_type_t scan_type; /**< scan type, active or passive */
wifi_scan_time_t scan_time; /**< scan time per channel */
} wifi_scan_config_t;
typedef enum {
WIFI_CIPHER_TYPE_NONE = 0, /**< the cipher type is none */
WIFI_CIPHER_TYPE_WEP40, /**< the cipher type is WEP40 */
WIFI_CIPHER_TYPE_WEP104, /**< the cipher type is WEP104 */
WIFI_CIPHER_TYPE_TKIP, /**< the cipher type is TKIP */
WIFI_CIPHER_TYPE_CCMP, /**< the cipher type is CCMP */
WIFI_CIPHER_TYPE_TKIP_CCMP, /**< the cipher type is TKIP and CCMP */
WIFI_CIPHER_TYPE_UNKNOWN, /**< the cipher type is unknown */
} wifi_cipher_type_t;
/**
* @brief WiFi antenna
*
*/
typedef enum {
WIFI_ANT_ANT0, /**< WiFi antenna 0 */
WIFI_ANT_ANT1, /**< WiFi antenna 1 */
WIFI_ANT_MAX, /**< Invalid WiFi antenna */
} wifi_ant_t;
/** @brief Description of a WiFi AP */
typedef struct {
uint8_t bssid[6]; /**< MAC address of AP */
uint8_t ssid[33]; /**< SSID of AP */
uint8_t primary; /**< channel of AP */
wifi_second_chan_t second; /**< secondary channel of AP */
int8_t rssi; /**< signal strength of AP */
wifi_auth_mode_t authmode; /**< authmode of AP */
wifi_cipher_type_t pairwise_cipher; /**< pairwise cipher of AP */
wifi_cipher_type_t group_cipher; /**< group cipher of AP */
wifi_ant_t ant; /**< antenna used to receive beacon from AP */
uint32_t phy_11b:1; /**< bit: 0 flag to identify if 11b mode is enabled or not */
uint32_t phy_11g:1; /**< bit: 1 flag to identify if 11g mode is enabled or not */
uint32_t phy_11n:1; /**< bit: 2 flag to identify if 11n mode is enabled or not */
uint32_t phy_lr:1; /**< bit: 3 flag to identify if low rate is enabled or not */
uint32_t wps:1; /**< bit: 4 flag to identify if WPS is supported or not */
uint32_t reserved:27; /**< bit: 5..31 reserved */
wifi_country_t country; /**< country information of AP */
} wifi_ap_record_t;
typedef enum {
WIFI_FAST_SCAN = 0, /**< Do fast scan, scan will end after find SSID match AP */
WIFI_ALL_CHANNEL_SCAN, /**< All channel scan, scan will end after scan all the channel */
}wifi_scan_method_t;
typedef enum {
WIFI_CONNECT_AP_BY_SIGNAL = 0, /**< Sort match AP in scan list by RSSI */
WIFI_CONNECT_AP_BY_SECURITY, /**< Sort match AP in scan list by security mode */
}wifi_sort_method_t;
/** @brief Structure describing parameters for a WiFi fast scan */
typedef struct {
int8_t rssi; /**< The minimum rssi to accept in the fast scan mode */
wifi_auth_mode_t authmode; /**< The weakest authmode to accept in the fast scan mode */
}wifi_fast_scan_threshold_t;
typedef wifi_fast_scan_threshold_t wifi_scan_threshold_t; /**< wifi_fast_scan_threshold_t only used in fast scan mode once, now it enabled in all channel scan, the wifi_fast_scan_threshold_t will be remove in version 4.0 */
typedef enum {
WIFI_PS_NONE, /**< No power save */
WIFI_PS_MIN_MODEM, /**< Minimum modem power saving. In this mode, station wakes up to receive beacon every DTIM period */
WIFI_PS_MAX_MODEM, /**< Maximum modem power saving. In this mode, interval to receive beacons is determined by the listen_interval parameter in wifi_sta_config_t */
} wifi_ps_type_t;
#define WIFI_PS_MODEM WIFI_PS_MIN_MODEM /**< @deprecated Use WIFI_PS_MIN_MODEM or WIFI_PS_MAX_MODEM instead */
#define WIFI_PROTOCOL_11B 1
#define WIFI_PROTOCOL_11G 2
#define WIFI_PROTOCOL_11N 4
#define WIFI_PROTOCOL_LR 8
typedef enum {
WIFI_BW_HT20 = 1, /* Bandwidth is HT20 */
WIFI_BW_HT40, /* Bandwidth is HT40 */
} wifi_bandwidth_t;
/** @brief Soft-AP configuration settings for the ESP32 */
typedef struct {
uint8_t ssid[32]; /**< SSID of ESP32 soft-AP */
uint8_t password[64]; /**< Password of ESP32 soft-AP */
uint8_t ssid_len; /**< Length of SSID. If softap_config.ssid_len==0, check the SSID until there is a termination character; otherwise, set the SSID length according to softap_config.ssid_len. */
uint8_t channel; /**< Channel of ESP32 soft-AP */
wifi_auth_mode_t authmode; /**< Auth mode of ESP32 soft-AP. Do not support AUTH_WEP in soft-AP mode */
uint8_t ssid_hidden; /**< Broadcast SSID or not, default 0, broadcast the SSID */
uint8_t max_connection; /**< Max number of stations allowed to connect in, default 4, max 4 */
uint16_t beacon_interval; /**< Beacon interval, 100 ~ 60000 ms, default 100 ms */
} wifi_ap_config_t;
/** @brief STA configuration settings for the ESP32 */
typedef struct {
uint8_t ssid[32]; /**< SSID of target AP*/
uint8_t password[64]; /**< password of target AP*/
wifi_scan_method_t scan_method; /**< do all channel scan or fast scan */
bool bssid_set; /**< whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/
uint8_t bssid[6]; /**< MAC address of target AP*/
uint8_t channel; /**< channel of target AP. Set to 1~13 to scan starting from the specified channel before connecting to AP. If the channel of AP is unknown, set it to 0.*/
uint16_t listen_interval; /**< Listen interval for ESP32 station to receive beacon when WIFI_PS_MAX_MODEM is set. Units: AP beacon intervals. Defaults to 3 if set to 0. */
wifi_sort_method_t sort_method; /**< sort the connect AP in the list by rssi or security mode */
wifi_scan_threshold_t threshold; /**< When scan_method is set, only APs which have an auth mode that is more secure than the selected auth mode and a signal stronger than the minimum RSSI will be used. */
} wifi_sta_config_t;
/** @brief Configuration data for ESP32 AP or STA.
*
* The usage of this union (for ap or sta configuration) is determined by the accompanying
* interface argument passed to esp_wifi_set_config() or esp_wifi_get_config()
*
*/
typedef union {
wifi_ap_config_t ap; /**< configuration of AP */
wifi_sta_config_t sta; /**< configuration of STA */
} wifi_config_t;
/** @brief Description of STA associated with AP */
typedef struct {
uint8_t mac[6]; /**< mac address */
int8_t rssi; /**< current average rssi of sta connected */
uint32_t phy_11b:1; /**< bit: 0 flag to identify if 11b mode is enabled or not */
uint32_t phy_11g:1; /**< bit: 1 flag to identify if 11g mode is enabled or not */
uint32_t phy_11n:1; /**< bit: 2 flag to identify if 11n mode is enabled or not */
uint32_t phy_lr:1; /**< bit: 3 flag to identify if low rate is enabled or not */
uint32_t reserved:28; /**< bit: 4..31 reserved */
} wifi_sta_info_t;
#define ESP_WIFI_MAX_CONN_NUM (10) /**< max number of stations which can connect to ESP32 soft-AP */
/** @brief List of stations associated with the ESP32 Soft-AP */
typedef struct {
wifi_sta_info_t sta[ESP_WIFI_MAX_CONN_NUM]; /**< station list */
int num; /**< number of stations in the list (other entries are invalid) */
} wifi_sta_list_t;
typedef enum {
WIFI_STORAGE_FLASH, /**< all configuration will strore in both memory and flash */
WIFI_STORAGE_RAM, /**< all configuration will only store in the memory */
} wifi_storage_t;
/**
* @brief Vendor Information Element type
*
* Determines the frame type that the IE will be associated with.
*/
typedef enum {
WIFI_VND_IE_TYPE_BEACON,
WIFI_VND_IE_TYPE_PROBE_REQ,
WIFI_VND_IE_TYPE_PROBE_RESP,
WIFI_VND_IE_TYPE_ASSOC_REQ,
WIFI_VND_IE_TYPE_ASSOC_RESP,
} wifi_vendor_ie_type_t;
/**
* @brief Vendor Information Element index
*
* Each IE type can have up to two associated vendor ID elements.
*/
typedef enum {
WIFI_VND_IE_ID_0,
WIFI_VND_IE_ID_1,
} wifi_vendor_ie_id_t;
#define WIFI_VENDOR_IE_ELEMENT_ID 0xDD
/**
* @brief Vendor Information Element header
*
* The first bytes of the Information Element will match this header. Payload follows.
*/
typedef struct {
uint8_t element_id; /**< Should be set to WIFI_VENDOR_IE_ELEMENT_ID (0xDD) */
uint8_t length; /**< Length of all bytes in the element data following this field. Minimum 4. */
uint8_t vendor_oui[3]; /**< Vendor identifier (OUI). */
uint8_t vendor_oui_type; /**< Vendor-specific OUI type. */
uint8_t payload[0]; /**< Payload. Length is equal to value in 'length' field, minus 4. */
} vendor_ie_data_t;
/** @brief Received packet radio metadata header, this is the common header at the beginning of all promiscuous mode RX callback buffers */
typedef struct {
signed rssi:8; /**< Received Signal Strength Indicator(RSSI) of packet. unit: dBm */
unsigned rate:5; /**< PHY rate encoding of the packet. Only valid for non HT(11bg) packet */
unsigned :1; /**< reserve */
unsigned sig_mode:2; /**< 0: non HT(11bg) packet; 1: HT(11n) packet; 3: VHT(11ac) packet */
unsigned :16; /**< reserve */
unsigned mcs:7; /**< Modulation Coding Scheme. If is HT(11n) packet, shows the modulation, range from 0 to 76(MSC0 ~ MCS76) */
unsigned cwb:1; /**< Channel Bandwidth of the packet. 0: 20MHz; 1: 40MHz */
unsigned :16; /**< reserve */
unsigned smoothing:1; /**< reserve */
unsigned not_sounding:1; /**< reserve */
unsigned :1; /**< reserve */
unsigned aggregation:1; /**< Aggregation. 0: MPDU packet; 1: AMPDU packet */
unsigned stbc:2; /**< Space Time Block Code(STBC). 0: non STBC packet; 1: STBC packet */
unsigned fec_coding:1; /**< Flag is set for 11n packets which are LDPC */
unsigned sgi:1; /**< Short Guide Interval(SGI). 0: Long GI; 1: Short GI */
signed noise_floor:8; /**< noise floor of Radio Frequency Module(RF). unit: 0.25dBm*/
unsigned ampdu_cnt:8; /**< ampdu cnt */
unsigned channel:4; /**< primary channel on which this packet is received */
unsigned secondary_channel:4; /**< secondary channel on which this packet is received. 0: none; 1: above; 2: below */
unsigned :8; /**< reserve */
unsigned timestamp:32; /**< timestamp. The local time when this packet is received. It is precise only if modem sleep or light sleep is not enabled. unit: microsecond */
unsigned :32; /**< reserve */
unsigned :31; /**< reserve */
unsigned ant:1; /**< antenna number from which this packet is received. 0: WiFi antenna 0; 1: WiFi antenna 1 */
unsigned sig_len:12; /**< length of packet including Frame Check Sequence(FCS) */
unsigned :12; /**< reserve */
unsigned rx_state:8; /**< state of the packet. 0: no error; others: error numbers which are not public */
} wifi_pkt_rx_ctrl_t;
/** @brief Payload passed to 'buf' parameter of promiscuous mode RX callback.
*/
typedef struct {
wifi_pkt_rx_ctrl_t rx_ctrl; /**< metadata header */
uint8_t payload[0]; /**< Data or management payload. Length of payload is described by rx_ctrl.sig_len. Type of content determined by packet type argument of callback. */
} wifi_promiscuous_pkt_t;
/**
* @brief Promiscuous frame type
*
* Passed to promiscuous mode RX callback to indicate the type of parameter in the buffer.
*
*/
typedef enum {
WIFI_PKT_MGMT, /**< Management frame, indicates 'buf' argument is wifi_promiscuous_pkt_t */
WIFI_PKT_CTRL, /**< Control frame, indicates 'buf' argument is wifi_promiscuous_pkt_t */
WIFI_PKT_DATA, /**< Data frame, indiciates 'buf' argument is wifi_promiscuous_pkt_t */
WIFI_PKT_MISC, /**< Other type, such as MIMO etc. 'buf' argument is wifi_promiscuous_pkt_t but the payload is zero length. */
} wifi_promiscuous_pkt_type_t;
#define WIFI_PROMIS_FILTER_MASK_ALL (0xFFFFFFFF) /**< filter all packets */
#define WIFI_PROMIS_FILTER_MASK_MGMT (1) /**< filter the packets with type of WIFI_PKT_MGMT */
#define WIFI_PROMIS_FILTER_MASK_CTRL (1<<1) /**< filter the packets with type of WIFI_PKT_CTRL */
#define WIFI_PROMIS_FILTER_MASK_DATA (1<<2) /**< filter the packets with type of WIFI_PKT_DATA */
#define WIFI_PROMIS_FILTER_MASK_MISC (1<<3) /**< filter the packets with type of WIFI_PKT_MISC */
#define WIFI_PROMIS_FILTER_MASK_DATA_MPDU (1<<4) /**< filter the MPDU which is a kind of WIFI_PKT_DATA */
#define WIFI_PROMIS_FILTER_MASK_DATA_AMPDU (1<<5) /**< filter the AMPDU which is a kind of WIFI_PKT_DATA */
#define WIFI_PROMIS_CTRL_FILTER_MASK_ALL (0xFF800000) /**< filter all control packets */
#define WIFI_PROMIS_CTRL_FILTER_MASK_WRAPPER (1<<23) /**< filter the control packets with subtype of Control Wrapper */
#define WIFI_PROMIS_CTRL_FILTER_MASK_BAR (1<<24) /**< filter the control packets with subtype of Block Ack Request */
#define WIFI_PROMIS_CTRL_FILTER_MASK_BA (1<<25) /**< filter the control packets with subtype of Block Ack */
#define WIFI_PROMIS_CTRL_FILTER_MASK_PSPOLL (1<<26) /**< filter the control packets with subtype of PS-Poll */
#define WIFI_PROMIS_CTRL_FILTER_MASK_RTS (1<<27) /**< filter the control packets with subtype of RTS */
#define WIFI_PROMIS_CTRL_FILTER_MASK_CTS (1<<28) /**< filter the control packets with subtype of CTS */
#define WIFI_PROMIS_CTRL_FILTER_MASK_ACK (1<<29) /**< filter the control packets with subtype of ACK */
#define WIFI_PROMIS_CTRL_FILTER_MASK_CFEND (1<<30) /**< filter the control packets with subtype of CF-END */
#define WIFI_PROMIS_CTRL_FILTER_MASK_CFENDACK (1<<31) /**< filter the control packets with subtype of CF-END+CF-ACK */
/** @brief Mask for filtering different packet types in promiscuous mode. */
typedef struct {
uint32_t filter_mask; /**< OR of one or more filter values WIFI_PROMIS_FILTER_* */
} wifi_promiscuous_filter_t;
#define WIFI_EVENT_MASK_ALL (0xFFFFFFFF) /**< mask all WiFi events */
#define WIFI_EVENT_MASK_NONE (0) /**< mask none of the WiFi events */
#define WIFI_EVENT_MASK_AP_PROBEREQRECVED (BIT(0)) /**< mask SYSTEM_EVENT_AP_PROBEREQRECVED event */
/**
* @brief Channel state information(CSI) configuration type
*
*/
typedef struct {
bool lltf_en; /**< enable to receive legacy long training field(lltf) data. Default enabled */
bool htltf_en; /**< enable to receive HT long training field(htltf) data. Default enabled */
bool stbc_htltf2_en; /**< enable to receive space time block code HT long training field(stbc-htltf2) data. Default enabled */
bool ltf_merge_en; /**< enable to generate htlft data by averaging lltf and ht_ltf data when receiving HT packet. Otherwise, use ht_ltf data directly. Default enabled */
bool channel_filter_en; /**< enable to turn on channel filter to smooth adjacent sub-carrier. Disable it to keep independence of adjacent sub-carrier. Default enabled */
bool manu_scale; /**< manually scale the CSI data by left shifting or automatically scale the CSI data. If set true, please set the shift bits. false: automatically. true: manually. Default false */
uint8_t shift; /**< manually left shift bits of the scale of the CSI data. The range of the left shift bits is 0~15 */
} wifi_csi_config_t;
/**
* @brief CSI data type
*
*/
typedef struct {
wifi_pkt_rx_ctrl_t rx_ctrl;/**< received packet radio metadata header of the CSI data */
uint8_t mac[6]; /**< source MAC address of the CSI data */
bool first_word_invalid; /**< first four bytes of the CSI data is invalid or not */
int8_t *buf; /**< buffer of CSI data */
uint16_t len; /**< length of CSI data */
} wifi_csi_info_t;
/**
* @brief WiFi GPIO configuration for antenna selection
*
*/
typedef struct {
uint8_t gpio_select: 1, /**< Whether this GPIO is connected to external antenna switch */
gpio_num: 7; /**< The GPIO number that connects to external antenna switch */
} wifi_ant_gpio_t;
/**
* @brief WiFi GPIOs configuration for antenna selection
*
*/
typedef struct {
wifi_ant_gpio_t gpio_cfg[4]; /**< The configurations of GPIOs that connect to external antenna switch */
} wifi_ant_gpio_config_t;
/**
* @brief WiFi antenna mode
*
*/
typedef enum {
WIFI_ANT_MODE_ANT0, /**< Enable WiFi antenna 0 only */
WIFI_ANT_MODE_ANT1, /**< Enable WiFi antenna 1 only */
WIFI_ANT_MODE_AUTO, /**< Enable WiFi antenna 0 and 1, automatically select an antenna */
WIFI_ANT_MODE_MAX, /**< Invalid WiFi enabled antenna */
} wifi_ant_mode_t;
/**
* @brief WiFi antenna configuration
*
*/
typedef struct {
wifi_ant_mode_t rx_ant_mode; /**< WiFi antenna mode for receiving */
wifi_ant_t rx_ant_default; /**< Default antenna mode for receiving, it's ignored if rx_ant_mode is not WIFI_ANT_MODE_AUTO */
wifi_ant_mode_t tx_ant_mode; /**< WiFi antenna mode for transmission, it can be set to WIFI_ANT_MODE_AUTO only if rx_ant_mode is set to WIFI_ANT_MODE_AUTO */
uint8_t enabled_ant0: 4, /**< Index (in antenna GPIO configuration) of enabled WIFI_ANT_MODE_ANT0 */
enabled_ant1: 4; /**< Index (in antenna GPIO configuration) of enabled WIFI_ANT_MODE_ANT1 */
} wifi_ant_config_t;
/**
* @brief WiFi PHY rate encodings
*
*/
typedef enum {
WIFI_PHY_RATE_1M_L = 0x00, /**< 1 Mbps with long preamble */
WIFI_PHY_RATE_2M_L = 0x01, /**< 2 Mbps with long preamble */
WIFI_PHY_RATE_5M_L = 0x02, /**< 5.5 Mbps with long preamble */
WIFI_PHY_RATE_11M_L = 0x03, /**< 11 Mbps with long preamble */
WIFI_PHY_RATE_2M_S = 0x05, /**< 2 Mbps with short preamble */
WIFI_PHY_RATE_5M_S = 0x06, /**< 5.5 Mbps with short preamble */
WIFI_PHY_RATE_11M_S = 0x07, /**< 11 Mbps with short preamble */
WIFI_PHY_RATE_48M = 0x08, /**< 48 Mbps */
WIFI_PHY_RATE_24M = 0x09, /**< 24 Mbps */
WIFI_PHY_RATE_12M = 0x0A, /**< 12 Mbps */
WIFI_PHY_RATE_6M = 0x0B, /**< 6 Mbps */
WIFI_PHY_RATE_54M = 0x0C, /**< 54 Mbps */
WIFI_PHY_RATE_36M = 0x0D, /**< 36 Mbps */
WIFI_PHY_RATE_18M = 0x0E, /**< 18 Mbps */
WIFI_PHY_RATE_9M = 0x0F, /**< 9 Mbps */
WIFI_PHY_RATE_MCS0_LGI = 0x10, /**< MCS0 with long GI, 6.5 Mbps for 20MHz, 13.5 Mbps for 40MHz */
WIFI_PHY_RATE_MCS1_LGI = 0x11, /**< MCS1 with long GI, 13 Mbps for 20MHz, 27 Mbps for 40MHz */
WIFI_PHY_RATE_MCS2_LGI = 0x12, /**< MCS2 with long GI, 19.5 Mbps for 20MHz, 40.5 Mbps for 40MHz */
WIFI_PHY_RATE_MCS3_LGI = 0x13, /**< MCS3 with long GI, 26 Mbps for 20MHz, 54 Mbps for 40MHz */
WIFI_PHY_RATE_MCS4_LGI = 0x14, /**< MCS4 with long GI, 39 Mbps for 20MHz, 81 Mbps for 40MHz */
WIFI_PHY_RATE_MCS5_LGI = 0x15, /**< MCS5 with long GI, 52 Mbps for 20MHz, 108 Mbps for 40MHz */
WIFI_PHY_RATE_MCS6_LGI = 0x16, /**< MCS6 with long GI, 58.5 Mbps for 20MHz, 121.5 Mbps for 40MHz */
WIFI_PHY_RATE_MCS7_LGI = 0x17, /**< MCS7 with long GI, 65 Mbps for 20MHz, 135 Mbps for 40MHz */
WIFI_PHY_RATE_MCS0_SGI = 0x18, /**< MCS0 with short GI, 7.2 Mbps for 20MHz, 15 Mbps for 40MHz */
WIFI_PHY_RATE_MCS1_SGI = 0x19, /**< MCS1 with short GI, 14.4 Mbps for 20MHz, 30 Mbps for 40MHz */
WIFI_PHY_RATE_MCS2_SGI = 0x1A, /**< MCS2 with short GI, 21.7 Mbps for 20MHz, 45 Mbps for 40MHz */
WIFI_PHY_RATE_MCS3_SGI = 0x1B, /**< MCS3 with short GI, 28.9 Mbps for 20MHz, 60 Mbps for 40MHz */
WIFI_PHY_RATE_MCS4_SGI = 0x1C, /**< MCS4 with short GI, 43.3 Mbps for 20MHz, 90 Mbps for 40MHz */
WIFI_PHY_RATE_MCS5_SGI = 0x1D, /**< MCS5 with short GI, 57.8 Mbps for 20MHz, 120 Mbps for 40MHz */
WIFI_PHY_RATE_MCS6_SGI = 0x1E, /**< MCS6 with short GI, 65 Mbps for 20MHz, 135 Mbps for 40MHz */
WIFI_PHY_RATE_MCS7_SGI = 0x1F, /**< MCS7 with short GI, 72.2 Mbps for 20MHz, 150 Mbps for 40MHz */
WIFI_PHY_RATE_LORA_250K = 0x29, /**< 250 Kbps */
WIFI_PHY_RATE_LORA_500K = 0x2A, /**< 500 Kbps */
WIFI_PHY_RATE_MAX,
} wifi_phy_rate_t;
/**
* @brief WiFi ioctl command type
*
*/
typedef enum {
WIFI_IOCTL_SET_STA_HT2040_COEX = 1, /**< Set the configuration of STA's HT2040 coexist management */
WIFI_IOCTL_GET_STA_HT2040_COEX, /**< Get the configuration of STA's HT2040 coexist management */
WIFI_IOCTL_MAX,
} wifi_ioctl_cmd_t;
/**
* @brief Configuration for STA's HT2040 coexist management
*
*/
typedef struct {
int enable; /**< Indicate whether STA's HT2040 coexist management is enabled or not */
} wifi_ht2040_coex_t;
/**
* @brief Configuration for WiFi ioctl
*
*/
typedef struct {
union {
wifi_ht2040_coex_t ht2040_coex; /**< Configuration of STA's HT2040 coexist management */
} data; /**< Configuration of ioctl command */
} wifi_ioctl_config_t;
#ifdef __cplusplus
}
#endif
#endif /* __ESP_WIFI_TYPES_H__ */

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// Hardware crypto support Copyright 2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef ESP_WPA2_H
#define ESP_WPA2_H
#include <stdbool.h>
#include "esp_err.h"
#include "esp_wifi_crypto_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const wpa2_crypto_funcs_t g_wifi_default_wpa2_crypto_funcs;
typedef struct {
const wpa2_crypto_funcs_t *crypto_funcs;
}esp_wpa2_config_t;
#define WPA2_CONFIG_INIT_DEFAULT() { \
.crypto_funcs = &g_wifi_default_wpa2_crypto_funcs \
}
/**
* @brief Enable wpa2 enterprise authentication.
*
* @attention 1. wpa2 enterprise authentication can only be used when ESP32 station is enabled.
* @attention 2. wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
*
* @return
* - ESP_OK: succeed.
* - ESP_ERR_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_enable(const esp_wpa2_config_t *config);
/**
* @brief Disable wpa2 enterprise authentication.
*
* @attention 1. wpa2 enterprise authentication can only be used when ESP32 station is enabled.
* @attention 2. wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
*
* @return
* - ESP_OK: succeed.
*/
esp_err_t esp_wifi_sta_wpa2_ent_disable(void);
/**
* @brief Set identity for PEAP/TTLS method.
*
* @attention The API only passes the parameter identity to the global pointer variable in wpa2 enterprise module.
*
* @param identity: point to address where stores the identity;
* @param len: length of identity, limited to 1~127
*
* @return
* - ESP_OK: succeed
* - ESP_ERR_INVALID_ARG: fail(len <= 0 or len >= 128)
* - ESP_ERR_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_identity(const unsigned char *identity, int len);
/**
* @brief Clear identity for PEAP/TTLS method.
*/
void esp_wifi_sta_wpa2_ent_clear_identity(void);
/**
* @brief Set username for PEAP/TTLS method.
*
* @attention The API only passes the parameter username to the global pointer variable in wpa2 enterprise module.
*
* @param username: point to address where stores the username;
* @param len: length of username, limited to 1~127
*
* @return
* - ESP_OK: succeed
* - ESP_ERR_INVALID_ARG: fail(len <= 0 or len >= 128)
* - ESP_ERR_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_username(const unsigned char *username, int len);
/**
* @brief Clear username for PEAP/TTLS method.
*/
void esp_wifi_sta_wpa2_ent_clear_username(void);
/**
* @brief Set password for PEAP/TTLS method..
*
* @attention The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
*
* @param password: point to address where stores the password;
* @param len: length of password(len > 0)
*
* @return
* - ESP_OK: succeed
* - ESP_ERR_INVALID_ARG: fail(len <= 0)
* - ESP_ERR_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_password(const unsigned char *password, int len);
/**
* @brief Clear password for PEAP/TTLS method..
*/
void esp_wifi_sta_wpa2_ent_clear_password(void);
/**
* @brief Set new password for MSCHAPv2 method..
*
* @attention 1. The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
* @attention 2. The new password is used to substitute the old password when eap-mschapv2 failure request message with error code ERROR_PASSWD_EXPIRED is received.
*
* @param new_password: point to address where stores the password;
* @param len: length of password
*
* @return
* - ESP_OK: succeed
* - ESP_ERR_INVALID_ARG: fail(len <= 0)
* - ESP_ERR_NO_MEM: fail(internal memory malloc fail)
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_new_password(const unsigned char *new_password, int len);
/**
* @brief Clear new password for MSCHAPv2 method..
*/
void esp_wifi_sta_wpa2_ent_clear_new_password(void);
/**
* @brief Set CA certificate for PEAP/TTLS method.
*
* @attention 1. The API only passes the parameter ca_cert to the global pointer variable in wpa2 enterprise module.
* @attention 2. The ca_cert should be zero terminated.
*
* @param ca_cert: point to address where stores the CA certificate;
* @param ca_cert_len: length of ca_cert
*
* @return
* - ESP_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_ca_cert(const unsigned char *ca_cert, int ca_cert_len);
/**
* @brief Clear CA certificate for PEAP/TTLS method.
*/
void esp_wifi_sta_wpa2_ent_clear_ca_cert(void);
/**
* @brief Set client certificate and key.
*
* @attention 1. The API only passes the parameter client_cert, private_key and private_key_passwd to the global pointer variable in wpa2 enterprise module.
* @attention 2. The client_cert, private_key and private_key_passwd should be zero terminated.
*
* @param client_cert: point to address where stores the client certificate;
* @param client_cert_len: length of client certificate;
* @param private_key: point to address where stores the private key;
* @param private_key_len: length of private key, limited to 1~2048;
* @param private_key_password: point to address where stores the private key password;
* @param private_key_password_len: length of private key password;
*
* @return
* - ESP_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_cert_key(const unsigned char *client_cert, int client_cert_len, const unsigned char *private_key, int private_key_len, const unsigned char *private_key_passwd, int private_key_passwd_len);
/**
* @brief Clear client certificate and key.
*/
void esp_wifi_sta_wpa2_ent_clear_cert_key(void);
/**
* @brief Set wpa2 enterprise certs time check(disable or not).
*
* @param true: disable wpa2 enterprise certs time check
* @param false: enable wpa2 enterprise certs time check
*
* @return
* - ESP_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_set_disable_time_check(bool disable);
/**
* @brief Get wpa2 enterprise certs time check(disable or not).
*
* @param disable: store disable value
*
* @return
* - ESP_OK: succeed
*/
esp_err_t esp_wifi_sta_wpa2_ent_get_disable_time_check(bool *disable);
#ifdef __cplusplus
}
#endif
#endif

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_WPS_H__
#define __ESP_WPS_H__
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "esp_wifi_crypto_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup WiFi_APIs WiFi Related APIs
* @brief WiFi APIs
*/
/** @addtogroup WiFi_APIs
* @{
*/
/** \defgroup WPS_APIs WPS APIs
* @brief ESP32 WPS APIs
*
* WPS can only be used when ESP32 station is enabled.
*
*/
/** @addtogroup WPS_APIs
* @{
*/
#define ESP_ERR_WIFI_REGISTRAR (ESP_ERR_WIFI_BASE + 51) /*!< WPS registrar is not supported */
#define ESP_ERR_WIFI_WPS_TYPE (ESP_ERR_WIFI_BASE + 52) /*!< WPS type error */
#define ESP_ERR_WIFI_WPS_SM (ESP_ERR_WIFI_BASE + 53) /*!< WPS state machine is not initialized */
typedef enum wps_type {
WPS_TYPE_DISABLE = 0,
WPS_TYPE_PBC,
WPS_TYPE_PIN,
WPS_TYPE_MAX,
} wps_type_t;
extern const wps_crypto_funcs_t g_wifi_default_wps_crypto_funcs;
#define WPS_MAX_MANUFACTURER_LEN 65
#define WPS_MAX_MODEL_NUMBER_LEN 33
#define WPS_MAX_MODEL_NAME_LEN 33
#define WPS_MAX_DEVICE_NAME_LEN 33
typedef struct {
char manufacturer[WPS_MAX_MANUFACTURER_LEN]; /*!< Manufacturer, null-terminated string. The default manufcturer is used if the string is empty */
char model_number[WPS_MAX_MODEL_NUMBER_LEN]; /*!< Model number, null-terminated string. The default model number is used if the string is empty */
char model_name[WPS_MAX_MODEL_NAME_LEN]; /*!< Model name, null-terminated string. The default model name is used if the string is empty */
char device_name[WPS_MAX_DEVICE_NAME_LEN]; /*!< Device name, null-terminated string. The default device name is used if the string is empty */
} wps_factory_information_t;
typedef struct {
wps_type_t wps_type;
const wps_crypto_funcs_t *crypto_funcs;
wps_factory_information_t factory_info;
} esp_wps_config_t;
#define WPS_CONFIG_INIT_DEFAULT(type) { \
.wps_type = type, \
.crypto_funcs = &g_wifi_default_wps_crypto_funcs, \
.factory_info = { \
.manufacturer = "ESPRESSIF", \
.model_number = "ESP32", \
.model_name = "ESPRESSIF IOT", \
.device_name = "ESP STATION", \
} \
}
/**
* @brief Enable Wi-Fi WPS function.
*
* @attention WPS can only be used when ESP32 station is enabled.
*
* @param wps_type_t wps_type : WPS type, so far only WPS_TYPE_PBC and WPS_TYPE_PIN is supported
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_WIFI_WPS_TYPE : wps type is invalid
* - ESP_ERR_WIFI_WPS_MODE : wifi is not in station mode or sniffer mode is on
* - ESP_FAIL : wps initialization fails
*/
esp_err_t esp_wifi_wps_enable(const esp_wps_config_t *config);
/**
* @brief Disable Wi-Fi WPS function and release resource it taken.
*
* @param null
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_WIFI_WPS_MODE : wifi is not in station mode or sniffer mode is on
*/
esp_err_t esp_wifi_wps_disable(void);
/**
* @brief WPS starts to work.
*
* @attention WPS can only be used when ESP32 station is enabled.
*
* @param timeout_ms : maximum blocking time before API return.
* - 0 : non-blocking
* - 1~120000 : blocking time (not supported in IDF v1.0)
*
* @return
* - ESP_OK : succeed
* - ESP_ERR_WIFI_WPS_TYPE : wps type is invalid
* - ESP_ERR_WIFI_WPS_MODE : wifi is not in station mode or sniffer mode is on
* - ESP_ERR_WIFI_WPS_SM : wps state machine is not initialized
* - ESP_FAIL : wps initialization fails
*/
esp_err_t esp_wifi_wps_start(int timeout_ms);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ESP_WPS_H__ */

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/**
* \brief AES block cipher, ESP32 hardware accelerated version
* Based on mbedTLS FIPS-197 compliant version.
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*
*/
#ifndef ESP_AES_H
#define ESP_AES_H
#include "esp_types.h"
#include "rom/aes.h"
#ifdef __cplusplus
extern "C" {
#endif
/* padlock.c and aesni.c rely on these values! */
#define ESP_AES_ENCRYPT 1
#define ESP_AES_DECRYPT 0
#define ERR_ESP_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */
#define ERR_ESP_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */
/**
* \brief AES context structure
*
*/
typedef struct {
uint8_t key_bytes;
volatile uint8_t key_in_hardware; /* This variable is used for fault injection checks, so marked volatile to avoid optimisation */
uint8_t key[32];
} esp_aes_context;
/**
* \brief The AES XTS context-type definition.
*/
typedef struct
{
esp_aes_context crypt; /*!< The AES context to use for AES block
encryption or decryption. */
esp_aes_context tweak; /*!< The AES context used for tweak
computation. */
} esp_aes_xts_context;
/**
* \brief Lock access to AES hardware unit
*
* AES hardware unit can only be used by one
* consumer at a time.
*
* esp_aes_xxx API calls automatically manage locking & unlocking of
* hardware, this function is only needed if you want to call
* ets_aes_xxx functions directly.
*/
void esp_aes_acquire_hardware( void );
/**
* \brief Unlock access to AES hardware unit
*
* esp_aes_xxx API calls automatically manage locking & unlocking of
* hardware, this function is only needed if you want to call
* ets_aes_xxx functions directly.
*/
void esp_aes_release_hardware( void );
/**
* \brief Initialize AES context
*
* \param ctx AES context to be initialized
*/
void esp_aes_init( esp_aes_context *ctx );
/**
* \brief Clear AES context
*
* \param ctx AES context to be cleared
*/
void esp_aes_free( esp_aes_context *ctx );
/**
* \brief This function initializes the specified AES XTS context.
*
* It must be the first API called before using
* the context.
*
* \param ctx The AES XTS context to initialize.
*/
void esp_aes_xts_init( esp_aes_xts_context *ctx );
/**
* \brief This function releases and clears the specified AES XTS context.
*
* \param ctx The AES XTS context to clear.
*/
void esp_aes_xts_free( esp_aes_xts_context *ctx );
/**
* \brief AES set key schedule (encryption or decryption)
*
* \param ctx AES context to be initialized
* \param key encryption key
* \param keybits must be 128, 192 or 256
*
* \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH
*/
int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits );
/**
* \brief AES-ECB block encryption/decryption
*
* \param ctx AES context
* \param mode AES_ENCRYPT or AES_DECRYPT
* \param input 16-byte input block
* \param output 16-byte output block
*
* \return 0 if successful
*/
int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] );
/**
* \brief AES-CBC buffer encryption/decryption
* Length should be a multiple of the block
* size (16 bytes)
*
* \note Upon exit, the content of the IV is updated so that you can
* call the function same function again on the following
* block(s) of data and get the same result as if it was
* encrypted in one call. This allows a "streaming" usage.
* If on the other hand you need to retain the contents of the
* IV, you should either save it manually or use the cipher
* module instead.
*
* \param ctx AES context
* \param mode AES_ENCRYPT or AES_DECRYPT
* \param length length of the input data
* \param iv initialization vector (updated after use)
* \param input buffer holding the input data
* \param output buffer holding the output data
*
* \return 0 if successful, or ERR_AES_INVALID_INPUT_LENGTH
*/
int esp_aes_crypt_cbc( esp_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
/**
* \brief AES-CFB128 buffer encryption/decryption.
*
* Note: Due to the nature of CFB you should use the same key schedule for
* both encryption and decryption. So a context initialized with
* esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
*
* \note Upon exit, the content of the IV is updated so that you can
* call the function same function again on the following
* block(s) of data and get the same result as if it was
* encrypted in one call. This allows a "streaming" usage.
* If on the other hand you need to retain the contents of the
* IV, you should either save it manually or use the cipher
* module instead.
*
* \param ctx AES context
* \param mode AES_ENCRYPT or AES_DECRYPT
* \param length length of the input data
* \param iv_off offset in IV (updated after use)
* \param iv initialization vector (updated after use)
* \param input buffer holding the input data
* \param output buffer holding the output data
*
* \return 0 if successful
*/
int esp_aes_crypt_cfb128( esp_aes_context *ctx,
int mode,
size_t length,
size_t *iv_off,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
/**
* \brief AES-CFB8 buffer encryption/decryption.
*
* Note: Due to the nature of CFB you should use the same key schedule for
* both encryption and decryption. So a context initialized with
* esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
*
* \note Upon exit, the content of the IV is updated so that you can
* call the function same function again on the following
* block(s) of data and get the same result as if it was
* encrypted in one call. This allows a "streaming" usage.
* If on the other hand you need to retain the contents of the
* IV, you should either save it manually or use the cipher
* module instead.
*
* \param ctx AES context
* \param mode AES_ENCRYPT or AES_DECRYPT
* \param length length of the input data
* \param iv initialization vector (updated after use)
* \param input buffer holding the input data
* \param output buffer holding the output data
*
* \return 0 if successful
*/
int esp_aes_crypt_cfb8( esp_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
/**
* \brief AES-CTR buffer encryption/decryption
*
* Warning: You have to keep the maximum use of your counter in mind!
*
* Note: Due to the nature of CTR you should use the same key schedule for
* both encryption and decryption. So a context initialized with
* esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
*
* \param ctx AES context
* \param length The length of the data
* \param nc_off The offset in the current stream_block (for resuming
* within current cipher stream). The offset pointer to
* should be 0 at the start of a stream.
* \param nonce_counter The 128-bit nonce and counter.
* \param stream_block The saved stream-block for resuming. Is overwritten
* by the function.
* \param input The input data stream
* \param output The output data stream
*
* \return 0 if successful
*/
int esp_aes_crypt_ctr( esp_aes_context *ctx,
size_t length,
size_t *nc_off,
unsigned char nonce_counter[16],
unsigned char stream_block[16],
const unsigned char *input,
unsigned char *output );
/**
* \brief This function prepares an XTS context for encryption and
* sets the encryption key.
*
* \param ctx The AES XTS context to which the key should be bound.
* \param key The encryption key. This is comprised of the XTS key1
* concatenated with the XTS key2.
* \param keybits The size of \p key passed in bits. Valid options are:
* <ul><li>256 bits (each of key1 and key2 is a 128-bit key)</li>
* <li>512 bits (each of key1 and key2 is a 256-bit key)</li></ul>
*
* \return \c 0 on success.
* \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
*/
int esp_aes_xts_setkey_enc( esp_aes_xts_context *ctx,
const unsigned char *key,
unsigned int keybits );
/**
* \brief This function prepares an XTS context for decryption and
* sets the decryption key.
*
* \param ctx The AES XTS context to which the key should be bound.
* \param key The decryption key. This is comprised of the XTS key1
* concatenated with the XTS key2.
* \param keybits The size of \p key passed in bits. Valid options are:
* <ul><li>256 bits (each of key1 and key2 is a 128-bit key)</li>
* <li>512 bits (each of key1 and key2 is a 256-bit key)</li></ul>
*
* \return \c 0 on success.
* \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
*/
int esp_aes_xts_setkey_dec( esp_aes_xts_context *ctx,
const unsigned char *key,
unsigned int keybits );
/**
* \brief Internal AES block encryption function
* (Only exposed to allow overriding it,
* see AES_ENCRYPT_ALT)
*
* \param ctx AES context
* \param input Plaintext block
* \param output Output (ciphertext) block
*/
int esp_internal_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] );
/** Deprecated, see esp_aes_internal_encrypt */
void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated));
/**
* \brief Internal AES block decryption function
* (Only exposed to allow overriding it,
* see AES_DECRYPT_ALT)
*
* \param ctx AES context
* \param input Ciphertext block
* \param output Output (plaintext) block
*/
int esp_internal_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] );
/** Deprecated, see esp_aes_internal_decrypt */
void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated));
#ifdef __cplusplus
}
#endif
#endif /* aes.h */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ESP_SHA_H_
#define _ESP_SHA_H_
#include "rom/sha.h"
#include "esp_types.h"
/** @brief Low-level support functions for the hardware SHA engine
*
* @note If you're looking for a SHA API to use, try mbedtls component
* mbedtls/shaXX.h. That API supports hardware acceleration.
*
* The API in this header provides some building blocks for implementing a
* full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha().
*
* Some technical details about the hardware SHA engine:
*
* - SHA accelerator engine calculates one digest at a time, per SHA
* algorithm type. It initialises and maintains the digest state
* internally. It is possible to read out an in-progress SHA digest
* state, but it is not possible to restore a SHA digest state
* into the engine.
*
* - The memory block SHA_TEXT_BASE is shared between all SHA digest
* engines, so all engines must be idle before this memory block is
* modified.
*
*/
#ifdef __cplusplus
extern "C" {
#endif
/* Defined in rom/sha.h */
typedef enum SHA_TYPE esp_sha_type;
/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine
*
* @note For more versatile SHA calculations, where data doesn't need
* to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. The
* hardware-accelerated mbedTLS implementation is also faster when
* hashing large amounts of data.
*
* @note It is not necessary to lock any SHA hardware before calling
* this function, thread safety is managed internally.
*
* @note If a TLS connection is open then this function may block
* indefinitely waiting for a SHA engine to become available. Use the
* mbedTLS SHA API to avoid this problem.
*
* @param sha_type SHA algorithm to use.
*
* @param input Input data buffer.
*
* @param ilen Length of input data in bytes.
*
* @param output Buffer for output SHA digest. Output is 20 bytes for
* sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for
* sha_type SHA2_384, 64 bytes for sha_type SHA2_512.
*/
void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output);
/* @brief Begin to execute a single SHA block operation
*
* @note This is a piece of a SHA algorithm, rather than an entire SHA
* algorithm.
*
* @note Call esp_sha_try_lock_engine() before calling this
* function. Do not call esp_sha_lock_memory_block() beforehand, this
* is done inside the function.
*
* @param sha_type SHA algorithm to use.
*
* @param data_block Pointer to block of data. Block size is
* determined by algorithm (SHA1/SHA2_256 = 64 bytes,
* SHA2_384/SHA2_512 = 128 bytes)
*
* @param is_first_block If this parameter is true, the SHA state will
* be initialised (with the initial state of the given SHA algorithm)
* before the block is calculated. If false, the existing state of the
* SHA engine will be used.
*
* @return As a performance optimisation, this function returns before
* the SHA block operation is complete. Both this function and
* esp_sha_read_state() will automatically wait for any previous
* operation to complete before they begin. If using the SHA registers
* directly in another way, call esp_sha_wait_idle() after calling this
* function but before accessing the SHA registers.
*/
void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block);
/** @brief Read out the current state of the SHA digest loaded in the engine.
*
* @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm.
*
* @note Call esp_sha_try_lock_engine() before calling this
* function. Do not call esp_sha_lock_memory_block() beforehand, this
* is done inside the function.
*
* If the SHA suffix padding block has been executed already, the
* value that is read is the SHA digest (in big endian
* format). Otherwise, the value that is read is an interim SHA state.
*
* @note If sha_type is SHA2_384, only 48 bytes of state will be read.
* This is enough for the final SHA2_384 digest, but if you want the
* interim SHA-384 state (to continue digesting) then pass SHA2_512 instead.
*
* @param sha_type SHA algorithm in use.
*
* @param state Pointer to a memory buffer to hold the SHA state. Size
* is 20 bytes (SHA1), 32 bytes (SHA2_256), 48 bytes (SHA2_384) or 64 bytes (SHA2_512).
*
*/
void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state);
/**
* @brief Obtain exclusive access to a particular SHA engine
*
* @param sha_type Type of SHA engine to use.
*
* Blocks until engine is available. Note: Can block indefinitely
* while a TLS connection is open, suggest using
* esp_sha_try_lock_engine() and failing over to software SHA.
*/
void esp_sha_lock_engine(esp_sha_type sha_type);
/**
* @brief Try and obtain exclusive access to a particular SHA engine
*
* @param sha_type Type of SHA engine to use.
*
* @return Returns true if the SHA engine is locked for exclusive
* use. Call esp_sha_unlock_sha_engine() when done. Returns false if
* the SHA engine is already in use, caller should use software SHA
* algorithm for this digest.
*/
bool esp_sha_try_lock_engine(esp_sha_type sha_type);
/**
* @brief Unlock an engine previously locked with esp_sha_lock_engine() or esp_sha_try_lock_engine()
*
* @param sha_type Type of engine to release.
*/
void esp_sha_unlock_engine(esp_sha_type sha_type);
/**
* @brief Acquire exclusive access to the SHA shared memory block at SHA_TEXT_BASE
*
* This memory block is shared across all the SHA algorithm types.
*
* Caller should have already locked a SHA engine before calling this function.
*
* Note that it is possible to obtain exclusive access to the memory block even
* while it is in use by the SHA engine. Caller should use esp_sha_wait_idle()
* to ensure the SHA engine is not reading from the memory block in hardware.
*
* @note This function enters a critical section. Do not block while holding this lock.
*
* @note You do not need to lock the memory block before calling esp_sha_block() or esp_sha_read_digest_state(), these functions handle memory block locking internally.
*
* Call esp_sha_unlock_memory_block() when done.
*/
void esp_sha_lock_memory_block(void);
/**
* @brief Release exclusive access to the SHA register memory block at SHA_TEXT_BASE
*
* Caller should have already locked a SHA engine before calling this function.
*
* This function releases the critical section entered by esp_sha_lock_memory_block().
*
* Call following esp_sha_lock_memory_block().
*/
void esp_sha_unlock_memory_block(void);
/** @brief Wait for the SHA engine to finish any current operation
*
* @note This function does not ensure exclusive access to any SHA
* engine. Caller should use esp_sha_try_lock_engine() and
* esp_sha_lock_memory_block() as required.
*
* @note Functions declared in this header file wait for SHA engine
* completion automatically, so you don't need to use this API for
* these. However if accessing SHA registers directly, you will need
* to call this before accessing SHA registers if using the
* esp_sha_block() function.
*
* @note This function busy-waits, so wastes CPU resources.
* Best to delay calling until you are about to need it.
*
*/
void esp_sha_wait_idle(void);
#ifdef __cplusplus
}
#endif
#endif

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tools/sdk/include/esp32/rom/aes.h
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@ -1,57 +1,2 @@
/*
ROM functions for hardware AES support.
It is not recommended to use these functions directly,
use the wrapper functions in hwcrypto/aes.h instead.
*/
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_AES_H_
#define _ROM_AES_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
//TODO, add comment for aes apis
enum AES_BITS {
AES128,
AES192,
AES256
};
void ets_aes_enable(void);
void ets_aes_disable(void);
void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap,
bool in_word_swap, bool in_byte_swap,
bool out_word_swap, bool out_byte_swap);
bool ets_aes_setkey_enc(const uint8_t *key, enum AES_BITS bits);
bool ets_aes_setkey_dec(const uint8_t *key, enum AES_BITS bits);
void ets_aes_crypt(const uint8_t input[16], uint8_t output[16]);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_AES_H_ */
#warning rom/aes.h is deprecated, please use esp32/rom/aes.h instead
#include "esp32/rom/aes.h"

64
tools/sdk/include/esp32/rom/bigint.h
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@ -1,62 +1,2 @@
/*
ROM functions for hardware bigint support.
It is not recommended to use these functions directly,
use the wrapper functions in hwcrypto/mpi.h instead.
*/
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_BIGINT_H_
#define _ROM_BIGINT_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
//TODO: add comment here
void ets_bigint_enable(void);
void ets_bigint_disable(void);
void ets_bigint_wait_finish(void);
bool ets_bigint_mod_power_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
bool ets_bigint_mod_power_getz(uint32_t *z, uint32_t len);
bool ets_bigint_mult_prepare(uint32_t *x, uint32_t *y, uint32_t len);
bool ets_bigint_mult_getz(uint32_t *z, uint32_t len);
bool ets_bigint_montgomery_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
uint32_t m_dash, uint32_t len, bool again);
bool ets_bigint_montgomery_mult_getz(uint32_t *z, uint32_t len);
bool ets_bigint_mod_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
bool ets_bigint_mod_mult_getz(uint32_t *m, uint32_t *z, uint32_t len);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_BIGINT_H_ */
#warning rom/bigint.h is deprecated, please use esp32/rom/bigint.h instead
#include "esp32/rom/bigint.h"

188
tools/sdk/include/esp32/rom/cache.h
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@ -1,186 +1,2 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_CACHE_H_
#define _ROM_CACHE_H_
#include "soc/dport_access.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
/**
* @brief Initialise cache mmu, mark all entries as invalid.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void mmu_init(int cpu_no);
/**
* @brief Set Flash-Cache mmu mapping.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
*
* @param int pod : process identifier. Range 0~7.
*
* @param unsigned int vaddr : virtual address in CPU address space.
* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
* Should be aligned by psize.
*
* @param unsigned int paddr : physical address in Flash.
* Should be aligned by psize.
*
* @param int psize : page size of flash, in kilobytes. Should be 64 here.
*
* @param int num : pages to be set.
*
* @return unsigned int: error status
* 0 : mmu set success
* 1 : vaddr or paddr is not aligned
* 2 : pid error
* 3 : psize error
* 4 : mmu table to be written is out of range
* 5 : vaddr is out of range
*/
static inline unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
{
extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
unsigned int ret;
DPORT_STALL_OTHER_CPU_START();
ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
DPORT_STALL_OTHER_CPU_END();
return ret;
}
/**
* @brief Set Ext-SRAM-Cache mmu mapping.
* Please do not call this function in your SDK application.
*
* Note that this code lives in IRAM and has a bugfix in respect to the ROM version
* of this function (which erroneously refused a vaddr > 2MiB
*
* @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
*
* @param int pod : process identifier. Range 0~7.
*
* @param unsigned int vaddr : virtual address in CPU address space.
* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
* Should be aligned by psize.
*
* @param unsigned int paddr : physical address in Ext-SRAM.
* Should be aligned by psize.
*
* @param int psize : page size of flash, in kilobytes. Should be 32 here.
*
* @param int num : pages to be set.
*
* @return unsigned int: error status
* 0 : mmu set success
* 1 : vaddr or paddr is not aligned
* 2 : pid error
* 3 : psize error
* 4 : mmu table to be written is out of range
* 5 : vaddr is out of range
*/
unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
/**
* @brief Initialise cache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
static inline void IRAM_ATTR Cache_Read_Init(int cpu_no)
{
extern void Cache_Read_Init_rom(int cpu_no);
DPORT_STALL_OTHER_CPU_START();
Cache_Read_Init_rom(cpu_no);
DPORT_STALL_OTHER_CPU_END();
}
/**
* @brief Flush the cache value for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
static inline void IRAM_ATTR Cache_Flush(int cpu_no)
{
extern void Cache_Flush_rom(int cpu_no);
DPORT_STALL_OTHER_CPU_START();
Cache_Flush_rom(cpu_no);
DPORT_STALL_OTHER_CPU_END();
}
/**
* @brief Disable Cache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no)
{
extern void Cache_Read_Disable_rom(int cpu_no);
DPORT_STALL_OTHER_CPU_START();
Cache_Read_Disable_rom(cpu_no);
DPORT_STALL_OTHER_CPU_END();
}
/**
* @brief Enable Cache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
static inline void IRAM_ATTR Cache_Read_Enable(int cpu_no)
{
extern void Cache_Read_Enable_rom(int cpu_no);
DPORT_STALL_OTHER_CPU_START();
Cache_Read_Enable_rom(cpu_no);
DPORT_STALL_OTHER_CPU_END();
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_CACHE_H_ */
#warning rom/cache.h is deprecated, please use esp32/rom/cache.h instead
#include "esp32/rom/cache.h"

162
tools/sdk/include/esp32/rom/crc.h
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@ -1,160 +1,2 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef ROM_CRC_H
#define ROM_CRC_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
/* Notes about CRC APIs usage
* The ESP32 ROM include some CRC tables and CRC APIs to speed up CRC calculation.
* The CRC APIs include CRC8, CRC16, CRC32 algorithms for both little endian and big endian modes.
* Here are the polynomials for the algorithms:
* CRC-8 x8+x2+x1+1 0x07
* CRC16-CCITT x16+x12+x5+1 0x1021
* CRC32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1 0x04c11db7
*
* These group of CRC APIs are designed to calculate the data in buffers either continuous or not.
* To make it easy, we had added a `~` at the beginning and the end of the functions.
* To calculate non-continuous buffers, we can write the code like this:
* init = ~init;
* crc = crc32_le(init, buf0, length0);
* crc = crc32_le(crc, buf1, length1);
* crc = ~crc;
*
* However, it is not easy to select which API to use and give the correct parameters.
* A specific CRC algorithm will include this parameters: width, polynomials, init, refin, refout, xorout
* refin and refout show the endian of the algorithm:
* if both of them are true, please use the little endian API.
* if both of them are false, please use the big endian API.
* xorout is the value which you need to be xored to the raw result.
* However, these group of APIs need one '~' before and after the APIs.
*
* Here are some examples for CRC16:
* CRC-16/CCITT, poly = 0x1021, init = 0x0000, refin = true, refout = true, xorout = 0x0000
* crc = ~crc16_le((uint16_t)~0x0000, buf, length);
*
* CRC-16/CCITT-FALSE, poly = 0x1021, init = 0xffff, refin = false, refout = false, xorout = 0x0000
* crc = ~crc16_be((uint16_t)~0xffff, buf, length);
*
* CRC-16/X25, poly = 0x1021, init = 0xffff, refin = true, refout = true, xorout = 0xffff
* crc = (~crc16_le((uint16_t)~(0xffff), buf, length))^0xffff;
*
* CRC-16/XMODEM, poly= 0x1021, init = 0x0000, refin = false, refout = false, xorout = 0x0000
* crc = ~crc16_be((uint16_t)~0x0000, buf, length);
*
*
*/
/**
* @brief CRC32 value that is in little endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief CRC32 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief CRC16 value that is in little endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief CRC16 value that is in big endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief CRC8 value that is in little endian.
*
* @param uint8_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief CRC8 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
#warning rom/crc.h is deprecated, please use esp32/rom/crc.h instead
#include "esp32/rom/crc.h"

119
tools/sdk/include/esp32/rom/efuse.h
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@ -1,117 +1,2 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_EFUSE_H_
#define _ROM_EFUSE_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup efuse_APIs efuse APIs
* @brief ESP32 efuse read/write APIs
* @attention
*
*/
/** @addtogroup efuse_APIs
* @{
*/
/**
* @brief Do a efuse read operation, to update the efuse value to efuse read registers.
*
* @param null
*
* @return null
*/
void ets_efuse_read_op(void);
/**
* @brief Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again.
*
* @param null
*
* @return null
*/
void ets_efuse_program_op(void);
/**
* @brief Read 8M Analog Clock value(8 bit) in efuse, the analog clock will not change with temperature.
* It can be used to test the external xtal frequency, do not touch this efuse field.
*
* @param null
*
* @return u32: 1 for 100KHZ, range is 0 to 255.
*/
uint32_t ets_efuse_get_8M_clock(void);
/**
* @brief Read spi flash pin configuration from Efuse
*
* @return
* - 0 for default SPI pins.
* - 1 for default HSPI pins.
* - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
* EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
* WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
*/
uint32_t ets_efuse_get_spiconfig(void);
#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0
#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6
#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12
#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18
#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24
#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
/**
* @brief A crc8 algorithm used in efuse check.
*
* @param unsigned char const *p : Pointer to original data.
*
* @param unsigned int len : Data length in byte.
*
* @return unsigned char: Crc value.
*/
unsigned char esp_crc8(unsigned char const *p, unsigned int len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_EFUSE_H_ */
#warning rom/efuse.h is deprecated, please use esp32/rom/efuse.h instead
#include "esp32/rom/efuse.h"

647
tools/sdk/include/esp32/rom/ets_sys.h
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@ -1,645 +1,2 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_ETS_SYS_H_
#define _ROM_ETS_SYS_H_
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup ets_sys_apis, ets system related apis
* @brief ets system apis
*/
/** @addtogroup ets_sys_apis
* @{
*/
/************************************************************************
* NOTE
* Many functions in this header files can't be run in FreeRTOS.
* Please see the comment of the Functions.
* There are also some functions that doesn't work on FreeRTOS
* without listed in the header, such as:
* xtos functions start with "_xtos_" in ld file.
*
***********************************************************************
*/
/** \defgroup ets_apis, Espressif Task Scheduler related apis
* @brief ets apis
*/
/** @addtogroup ets_apis
* @{
*/
typedef enum {
ETS_OK = 0, /**< return successful in ets*/
ETS_FAILED = 1 /**< return failed in ets*/
} ETS_STATUS;
typedef uint32_t ETSSignal;
typedef uint32_t ETSParam;
typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/
struct ETSEventTag {
ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/
ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/
};
typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/
typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/
/**
* @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it.
*
* @param none
*
* @return none
*/
void ets_run(void);
/**
* @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep.
*
* @param ets_idle_cb_t func : The callback function.
*
* @param void *arg : Argument of the callback.
*
* @return None
*/
void ets_set_idle_cb(ets_idle_cb_t func, void *arg);
/**
* @brief Init a task with processer, priority, queue to receive Event, queue length.
*
* @param ETSTask task : The task processer.
*
* @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task.
*
* @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used.
*
* @param uint8_t qlen : Queue length.
*
* @return None
*/
void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen);
/**
* @brief Post an event to an Task.
*
* @param uint8_t prio : Priority of the Task.
*
* @param ETSSignal sig : Event signal.
*
* @param ETSParam par : Event parameter
*
* @return ETS_OK : post successful
* @return ETS_FAILED : post failed
*/
ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
/**
* @}
*/
/** \defgroup ets_boot_apis, Boot routing related apis
* @brief ets boot apis
*/
/** @addtogroup ets_apis
* @{
*/
extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/
/**
* @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
* When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
*
* @param uint32_t start : the PRO Entry code address value in uint32_t
*
* @return None
*/
void ets_set_user_start(uint32_t start);
/**
* @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code.
* When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run.
*
* @param uint32_t callback : the Startup code address value in uint32_t
*
* @return None : post successful
*/
void ets_set_startup_callback(uint32_t callback);
/**
* @brief Set App cpu Entry code, code can be called in PRO CPU.
* When APP booting is completed, APP CPU will call the Entry code if not NULL.
*
* @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D.
*
* @return None
*/
void ets_set_appcpu_boot_addr(uint32_t start);
/**
* @brief unpack the image in flash to iram and dram, no using cache.
*
* @param uint32_t pos : Flash physical address.
*
* @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
*
* @param bool jump : Jump into the code in the function or not.
*
* @param bool config : Config the flash when unpacking the image, config should be done only once.
*
* @return ETS_OK : unpack successful
* @return ETS_FAILED : unpack failed
*/
ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config);
/**
* @brief unpack the image in flash to iram and dram, using cache, maybe decrypting.
*
* @param uint32_t pos : Flash physical address.
*
* @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
*
* @param bool jump : Jump into the code in the function or not.
*
* @param bool sb_need_check : Do security boot check or not.
*
* @param bool config : Config the flash when unpacking the image, config should be done only once.
*
* @return ETS_OK : unpack successful
* @return ETS_FAILED : unpack failed
*/
ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config);
/**
* @}
*/
/** \defgroup ets_printf_apis, ets_printf related apis used in ets
* @brief ets printf apis
*/
/** @addtogroup ets_printf_apis
* @{
*/
/**
* @brief Printf the strings to uart or other devices, similar with printf, simple than printf.
* Can not print float point data format, or longlong data format.
* So we maybe only use this in ROM.
*
* @param const char *fmt : See printf.
*
* @param ... : See printf.
*
* @return int : the length printed to the output device.
*/
int ets_printf(const char *fmt, ...);
/**
* @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
* Can not print float point data format, or longlong data format
*
* @param char c : char to output.
*
* @return None
*/
void ets_write_char_uart(char c);
/**
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
* To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
*
* @param void (*)(char) p: Output function to install.
*
* @return None
*/
void ets_install_putc1(void (*p)(char c));
/**
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
* To install putc2, which is defaulted installed as NULL.
*
* @param void (*)(char) p: Output function to install.
*
* @return None
*/
void ets_install_putc2(void (*p)(char c));
/**
* @brief Install putc1 as ets_write_char_uart.
* In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
*
* @param None
*
* @return None
*/
void ets_install_uart_printf(void);
#define ETS_PRINTF(...) ets_printf(...)
#define ETS_ASSERT(v) do { \
if (!(v)) { \
ets_printf("%s %u \n", __FILE__, __LINE__); \
while (1) {}; \
} \
} while (0);
/**
* @}
*/
/** \defgroup ets_timer_apis, ets_timer related apis used in ets
* @brief ets timer apis
*/
/** @addtogroup ets_timer_apis
* @{
*/
typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
typedef struct _ETSTIMER_ {
struct _ETSTIMER_ *timer_next; /**< timer linker*/
uint32_t timer_expire; /**< abstruct time when timer expire*/
uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/
ETSTimerFunc *timer_func; /**< timer handler*/
void *timer_arg; /**< timer handler argument*/
} ETSTimer;
/**
* @brief Init ets timer, this timer range is 640 us to 429496 ms
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_timer_init(void);
/**
* @brief In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_timer_deinit(void);
/**
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param uint32_t tmout : Timer value in ms, range is 1 to 429496.
*
* @param bool repeat : Timer is periodic repeated.
*
* @return None
*/
void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
/**
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param uint32_t tmout : Timer value in us, range is 1 to 429496729.
*
* @param bool repeat : Timer is periodic repeated.
*
* @return None
*/
void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
/**
* @brief Disarm an ets timer.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @return None
*/
void ets_timer_disarm(ETSTimer *timer);
/**
* @brief Set timer callback and argument.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param ETSTimerFunc *pfunction : Timer callback.
*
* @param void *parg : Timer callback argument.
*
* @return None
*/
void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
/**
* @brief Unset timer callback and argument to NULL.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @return None
*/
void ets_timer_done(ETSTimer *ptimer);
/**
* @brief CPU do while loop for some time.
* In FreeRTOS task, please call FreeRTOS apis.
*
* @param uint32_t us : Delay time in us.
*
* @return None
*/
void ets_delay_us(uint32_t us);
/**
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
* Call this function when CPU frequency is changed.
*
* @param uint32_t ticks_per_us : CPU ticks per us.
*
* @return None
*/
void ets_update_cpu_frequency(uint32_t ticks_per_us);
/**
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
*
* @note This function only sets the tick rate for the current CPU. It is located in ROM,
* so the deep sleep stub can use it even if IRAM is not initialized yet.
*
* @param uint32_t ticks_per_us : CPU ticks per us.
*
* @return None
*/
void ets_update_cpu_frequency_rom(uint32_t ticks_per_us);
/**
* @brief Get the real CPU ticks per us to the ets.
* This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
*
* @param None
*
* @return uint32_t : CPU ticks per us record in ets.
*/
uint32_t ets_get_cpu_frequency(void);
/**
* @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module.
*
* @param None
*
* @return uint32_t : xtal_freq/analog_8M*256.
*/
uint32_t ets_get_xtal_scale(void);
/**
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
*
* @param None
*
* @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
* clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
* else if analog_8M in efuse
* clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40;
* else clock = 26M.
*/
uint32_t ets_get_detected_xtal_freq(void);
/**
* @}
*/
/** \defgroup ets_intr_apis, ets interrupt configure related apis
* @brief ets intr apis
*/
/** @addtogroup ets_intr_apis
* @{
*/
typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
/**
* @brief Attach a interrupt handler to a CPU interrupt number.
* This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param int i : CPU interrupt number.
*
* @param ets_isr_t func : Interrupt handler.
*
* @param void *arg : argument of the handler.
*
* @return None
*/
void ets_isr_attach(int i, ets_isr_t func, void *arg);
/**
* @brief Mask the interrupts which show in mask bits.
* This function equals to _xtos_ints_off(mask).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
*
* @return None
*/
void ets_isr_mask(uint32_t mask);
/**
* @brief Unmask the interrupts which show in mask bits.
* This function equals to _xtos_ints_on(mask).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
*
* @return None
*/
void ets_isr_unmask(uint32_t unmask);
/**
* @brief Lock the interrupt to level 2.
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_intr_lock(void);
/**
* @brief Unlock the interrupt to level 0.
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_intr_unlock(void);
/**
* @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt).
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_waiti0(void);
/**
* @brief Attach an CPU interrupt to a hardware source.
* We have 4 steps to use an interrupt:
* 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
* 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
* 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);
* 4.Enable interrupt in the module.
*
* @param int cpu_no : The CPU which the interrupt number belongs.
*
* @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
*
* @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
*
* @return None
*/
void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
#define _ETSTR(v) # v
#define _ETS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \
__asm__ __volatile__( "rsil %0, " _ETSTR(intlevel) "\n" \
: "=a" (__tmp) : : "memory" ); \
})
#ifdef CONFIG_NONE_OS
#define ETS_INTR_LOCK() \
ets_intr_lock()
#define ETS_INTR_UNLOCK() \
ets_intr_unlock()
#define ETS_ISR_ATTACH \
ets_isr_attach
#define ETS_INTR_ENABLE(inum) \
ets_isr_unmask((1<<inum))
#define ETS_INTR_DISABLE(inum) \
ets_isr_mask((1<<inum))
#define ETS_WMAC_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_WMAC_INUM, (func), (void *)(arg))
#define ETS_TG0_T0_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_TG0_T0_INUM, (func), (void *)(arg))
#define ETS_GPIO_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_GPIO_INUM, (func), (void *)(arg))
#define ETS_UART0_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_UART0_INUM, (func), (void *)(arg))
#define ETS_WDT_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_WDT_INUM, (func), (void *)(arg))
#define ETS_SLC_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_SLC_INUM, (func), (void *)(arg))
#define ETS_BB_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_BB_INUM)
#define ETS_BB_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_BB_INUM)
#define ETS_UART0_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_UART0_INUM)
#define ETS_UART0_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_UART0_INUM)
#define ETS_GPIO_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_GPIO_INUM)
#define ETS_GPIO_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_GPIO_INUM)
#define ETS_WDT_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_WDT_INUM)
#define ETS_WDT_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_WDT_INUM)
#define ETS_TG0_T0_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_TG0_T0_INUM)
#define ETS_TG0_T0_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_TG0_T0_INUM)
#define ETS_SLC_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_SLC_INUM)
#define ETS_SLC_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_SLC_INUM)
#endif
/**
* @}
*/
#ifndef MAC2STR
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
#endif
#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
typedef enum {
OK = 0,
FAIL,
PENDING,
BUSY,
CANCEL,
} STATUS;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_ETS_SYS_H_ */
#warning rom/ets_sys.h is deprecated, please use esp32/rom/ets_sys.h instead
#include "esp32/rom/ets_sys.h"

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tools/sdk/include/esp32/rom/gpio.h
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@ -1,303 +1,2 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_GPIO_H_
#define _ROM_GPIO_H_
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/gpio_reg.h"
#include "soc/gpio_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup gpio_apis, uart configuration and communication related apis
* @brief gpio apis
*/
/** @addtogroup gpio_apis
* @{
*/
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
#define GPIO_ID_PIN0 0
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
#define GPIO_FUNC_IN_HIGH 0x38
#define GPIO_FUNC_IN_LOW 0x30
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
typedef enum {
GPIO_PIN_INTR_DISABLE = 0,
GPIO_PIN_INTR_POSEDGE = 1,
GPIO_PIN_INTR_NEGEDGE = 2,
GPIO_PIN_INTR_ANYEDGE = 3,
GPIO_PIN_INTR_LOLEVEL = 4,
GPIO_PIN_INTR_HILEVEL = 5
} GPIO_INT_TYPE;
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
((gpio_no < 32) ? gpio_output_set(bit_value<<gpio_no, (bit_value ? 0 : 1)<<gpio_no, 1<<gpio_no,0) : \
gpio_output_set_high(bit_value<<(gpio_no - 32), (bit_value ? 0 : 1)<<(gpio_no - 32), 1<<(gpio_no -32),0))
#define GPIO_DIS_OUTPUT(gpio_no) ((gpio_no < 32) ? gpio_output_set(0,0,0, 1<<gpio_no) : gpio_output_set_high(0,0,0, 1<<(gpio_no - 32)))
#define GPIO_INPUT_GET(gpio_no) ((gpio_no < 32) ? ((gpio_input_get()>>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0))
/* GPIO interrupt handler, registered through gpio_intr_handler_register */
typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg);
/**
* @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet
* to initialize "output enables" and pin configurations for each gpio pin.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void gpio_init(void);
/**
* @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
*
* @param uint32_t clear_mask : the gpios that need low level.
*
* @param uint32_t enable_mask : the gpios that need be changed.
*
* @param uint32_t disable_mask : the gpios that need diable output.
*
* @return None
*/
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
*
* @param uint32_t clear_mask : the gpios that need low level.
*
* @param uint32_t enable_mask : the gpios that need be changed.
*
* @param uint32_t disable_mask : the gpios that need diable output.
*
* @return None
*/
void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
*
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
*/
uint32_t gpio_input_get(void);
/**
* @brief Sample the value of GPIO input pins(32-39) and returns a bitmask.
*
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32.
*/
uint32_t gpio_input_get_high(void);
/**
* @brief Register an application-specific interrupt handler for GPIO pin interrupts.
* Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack.
* Please do not call this function in SDK.
*
* @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler
*
* @param void *arg : gpio application-specific interrupt handler argument.
*
* @return None
*/
void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg);
/**
* @brief Get gpio interrupts which happens but not processed.
* Please do not call this function in SDK.
*
* @param None
*
* @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0.
*/
uint32_t gpio_intr_pending(void);
/**
* @brief Get gpio interrupts which happens but not processed.
* Please do not call this function in SDK.
*
* @param None
*
* @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32.
*/
uint32_t gpio_intr_pending_high(void);
/**
* @brief Ack gpio interrupts to process pending interrupts.
* Please do not call this function in SDK.
*
* @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0.
*
* @return None
*/
void gpio_intr_ack(uint32_t ack_mask);
/**
* @brief Ack gpio interrupts to process pending interrupts.
* Please do not call this function in SDK.
*
* @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32.
*
* @return None
*/
void gpio_intr_ack_high(uint32_t ack_mask);
/**
* @brief Set GPIO to wakeup the ESP32.
* Please do not call this function in SDK.
*
* @param uint32_t i: gpio number.
*
* @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
*
* @return None
*/
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
/**
* @brief disable GPIOs to wakeup the ESP32.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~0x27
* gpio == 0x30, input 0 to signal
* gpio == 0x34, ???
* gpio == 0x38, input 1 to signal
*
* @param uint32_t signal_idx : signal index.
*
* @param bool inv : the signal is inv or not
*
* @return None
*/
void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~0x27
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x100, cancel output put to the gpio
*
* @param bool out_inv : the signal output is inv or not
*
* @param bool oen_inv : the signal output enable is inv or not
*
* @return None
*/
void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_select_gpio(uint8_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @param uint8_t drv : 0-3
*
* @return None
*/
void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_pullup(uint8_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_pulldown(uint8_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_unhold(uint8_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_hold(uint8_t gpio_num);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_GPIO_H_ */
#warning rom/gpio.h is deprecated, please use esp32/rom/gpio.h instead
#include "esp32/rom/gpio.h"

91
tools/sdk/include/esp32/rom/libc_stubs.h
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@ -1,89 +1,2 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_LIBC_STUBS_H_
#define _ROM_LIBC_STUBS_H_
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <stdarg.h>
#include <reent.h>
#include <errno.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32 ROM code contains implementations of some of C library functions.
Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
implementation defined in the following struct.
The table itself, by default, is not allocated in RAM. There are two pointers, `syscall_table_ptr_pro` and
`syscall_table_ptr_app`, which can be set to point to the locations of syscall tables of CPU 0 (aka PRO CPU)
and CPU 1 (aka APP CPU). Location of these pointers in .bss segment of ROM code is defined in linker script.
So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
application must allocate syscall table structure for each CPU being used, and populate it with pointers
to actual implementations of corresponding syscalls.
*/
struct syscall_stub_table
{
struct _reent* (*__getreent)(void);
void* (*_malloc_r)(struct _reent *r, size_t);
void (*_free_r)(struct _reent *r, void*);
void* (*_realloc_r)(struct _reent *r, void*, size_t);
void* (*_calloc_r)(struct _reent *r, size_t, size_t);
void (*_abort)(void);
int (*_system_r)(struct _reent *r, const char*);
int (*_rename_r)(struct _reent *r, const char*, const char*);
clock_t (*_times_r)(struct _reent *r, struct tms *);
int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
void (*_raise_r)(struct _reent *r); /* function signature is incorrect in ROM */
int (*_unlink_r)(struct _reent *r, const char*);
int (*_link_r)(struct _reent *r, const char*, const char*);
int (*_stat_r)(struct _reent *r, const char*, struct stat *);
int (*_fstat_r)(struct _reent *r, int, struct stat *);
void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
int (*_getpid_r)(struct _reent *r);
int (*_kill_r)(struct _reent *r, int, int);
void (*_exit_r)(struct _reent *r, int);
int (*_close_r)(struct _reent *r, int);
int (*_open_r)(struct _reent *r, const char *, int, int);
int (*_write_r)(struct _reent *r, int, const void *, int);
int (*_lseek_r)(struct _reent *r, int, int, int);
int (*_read_r)(struct _reent *r, int, void *, int);
void (*_lock_init)(_lock_t *lock);
void (*_lock_init_recursive)(_lock_t *lock);
void (*_lock_close)(_lock_t *lock);
void (*_lock_close_recursive)(_lock_t *lock);
void (*_lock_acquire)(_lock_t *lock);
void (*_lock_acquire_recursive)(_lock_t *lock);
int (*_lock_try_acquire)(_lock_t *lock);
int (*_lock_try_acquire_recursive)(_lock_t *lock);
void (*_lock_release)(_lock_t *lock);
void (*_lock_release_recursive)(_lock_t *lock);
int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, _CONST char *, size_t len), va_list * ap);
int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
};
extern struct syscall_stub_table* syscall_table_ptr_pro;
extern struct syscall_stub_table* syscall_table_ptr_app;
#ifdef __cplusplus
} // extern "C"
#endif
#endif /* _ROM_LIBC_STUBS_H_ */
#warning rom/libc_stubs.h is deprecated, please use esp32/rom/libc_stubs.h instead
#include "esp32/rom/libc_stubs.h"

178
tools/sdk/include/esp32/rom/lldesc.h
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@ -1,176 +1,2 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_LLDESC_H_
#define _ROM_LLDESC_H_
#include <stdint.h>
#include "queue.h"
#ifdef __cplusplus
extern "C" {
#endif
#define LLDESC_TX_MBLK_SIZE 268 /* */
#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */
#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/
#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/
#ifdef ESP_MAC_5
#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */
#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12
#else
#ifdef SBUF_RXTX
#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */
#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */
#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */
#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */
#endif
#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */
#ifdef IEEE80211_RX_AMPDU
#define LLDESC_RX_MBLK_NUM 30
#else
#define LLDESC_RX_MBLK_NUM 10
#endif /*IEEE80211_RX_AMPDU*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8
#endif /* !ESP_MAC_5 */
/*
* SLC2 DMA Desc struct, aka lldesc_t
*
* --------------------------------------------------------------
* | own | EoF | sub_sof | 5'b0 | length [11:0] | size [11:0] |
* --------------------------------------------------------------
* | buf_ptr [31:0] |
* --------------------------------------------------------------
* | next_desc_ptr [31:0] |
* --------------------------------------------------------------
*/
/* this bitfield is start from the LSB!!! */
typedef struct lldesc_s {
volatile uint32_t size :12,
length:12,
offset: 5, /* h/w reserved 5bit, s/w use it as offset in buffer */
sosf : 1, /* start of sub-frame */
eof : 1, /* end of frame */
owner : 1; /* hw or sw */
volatile uint8_t *buf; /* point to buffer data */
union{
volatile uint32_t empty;
STAILQ_ENTRY(lldesc_s) qe; /* pointing to the next desc */
};
} lldesc_t;
typedef struct tx_ampdu_entry_s{
uint32_t sub_len :12,
dili_num : 7,
: 1,
null_byte: 2,
data : 1,
enc : 1,
seq : 8;
} tx_ampdu_entry_t;
typedef struct lldesc_chain_s {
lldesc_t *head;
lldesc_t *tail;
} lldesc_chain_t;
#ifdef SBUF_RXTX
enum sbuf_mask_s {
SBUF_MOVE_NO = 0,
SBUF_MOVE_TX2RX,
SBUF_MOVE_RX2TX,
} ;
#define SBUF_MOVE_STEP 8
#endif
#define LLDESC_SIZE sizeof(struct lldesc_s)
/* SLC Descriptor */
#define LLDESC_OWNER_MASK 0x80000000
#define LLDESC_OWNER_SHIFT 31
#define LLDESC_SW_OWNED 0
#define LLDESC_HW_OWNED 1
#define LLDESC_EOF_MASK 0x40000000
#define LLDESC_EOF_SHIFT 30
#define LLDESC_SOSF_MASK 0x20000000
#define LLDESC_SOSF_SHIFT 29
#define LLDESC_LENGTH_MASK 0x00fff000
#define LLDESC_LENGTH_SHIFT 12
#define LLDESC_SIZE_MASK 0x00000fff
#define LLDESC_SIZE_SHIFT 0
#define LLDESC_ADDR_MASK 0x000fffff
void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t * mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner,
lldesc_t **head,
#ifdef TO_HOST_RESTART
lldesc_t ** one_before_tail,
#endif
lldesc_t **tail);
lldesc_t *lldesc_num2link(lldesc_t * head, uint16_t nblks);
lldesc_t *lldesc_set_owner(lldesc_t * head, uint16_t nblks, uint8_t owner);
static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
{
lldesc_t *ds = head;
uint32_t len = 0;
while (ds) {
len += ds->length;
ds = STAILQ_NEXT(ds, qe);
}
return len;
}
static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
{
ds->owner = owner;
ds->eof = eof;
ds->sosf = sosf;
ds->length = len;
}
#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \
(_desc)->owner = (_owner); \
(_desc)->eof = (_eof); \
(_desc)->sosf = (_sosf); \
(_desc)->length = (_len); \
} while(0)
#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
#ifdef __cplusplus
}
#endif
#endif /* _ROM_LLDESC_H_ */
#warning rom/lldesc.h is deprecated, please use esp32/rom/lldesc.h instead
#include "esp32/rom/lldesc.h"

40
tools/sdk/include/esp32/rom/md5_hash.h
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@ -1,38 +1,2 @@
/*
* MD5 internal definitions
* Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Alternatively, this software may be distributed under the terms of BSD
* license.
*
* See README and COPYING for more details.
*/
#ifndef _ROM_MD5_HASH_H_
#define _ROM_MD5_HASH_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
struct MD5Context {
uint32_t buf[4];
uint32_t bits[2];
uint8_t in[64];
};
void MD5Init(struct MD5Context *context);
void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
void MD5Final(unsigned char digest[16], struct MD5Context *context);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_MD5_HASH_H_ */
#warning rom/md5_hash.h is deprecated, please use esp32/rom/md5_hash.h instead
#include "esp32/rom/md5_hash.h"

779
tools/sdk/include/esp32/rom/miniz.h
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@ -1,777 +1,2 @@
#ifndef MINIZ_HEADER_INCLUDED
#define MINIZ_HEADER_INCLUDED
#include <stdlib.h>
// Defines to completely disable specific portions of miniz.c:
// If all macros here are defined the only functionality remaining will be CRC-32, adler-32, tinfl, and tdefl.
// Define MINIZ_NO_STDIO to disable all usage and any functions which rely on stdio for file I/O.
#define MINIZ_NO_STDIO
// If MINIZ_NO_TIME is specified then the ZIP archive functions will not be able to get the current time, or
// get/set file times, and the C run-time funcs that get/set times won't be called.
// The current downside is the times written to your archives will be from 1979.
#define MINIZ_NO_TIME
// Define MINIZ_NO_ARCHIVE_APIS to disable all ZIP archive API's.
#define MINIZ_NO_ARCHIVE_APIS
// Define MINIZ_NO_ARCHIVE_APIS to disable all writing related ZIP archive API's.
#define MINIZ_NO_ARCHIVE_WRITING_APIS
// Define MINIZ_NO_ZLIB_APIS to remove all ZLIB-style compression/decompression API's.
#define MINIZ_NO_ZLIB_APIS
// Define MINIZ_NO_ZLIB_COMPATIBLE_NAME to disable zlib names, to prevent conflicts against stock zlib.
#define MINIZ_NO_ZLIB_COMPATIBLE_NAMES
// Define MINIZ_NO_MALLOC to disable all calls to malloc, free, and realloc.
// Note if MINIZ_NO_MALLOC is defined then the user must always provide custom user alloc/free/realloc
// callbacks to the zlib and archive API's, and a few stand-alone helper API's which don't provide custom user
// functions (such as tdefl_compress_mem_to_heap() and tinfl_decompress_mem_to_heap()) won't work.
#define MINIZ_NO_MALLOC
#if defined(__TINYC__) && (defined(__linux) || defined(__linux__))
// TODO: Work around "error: include file 'sys\utime.h' when compiling with tcc on Linux
#define MINIZ_NO_TIME
#endif
#if !defined(MINIZ_NO_TIME) && !defined(MINIZ_NO_ARCHIVE_APIS)
#include <time.h>
#endif
//Hardcoded options for Xtensa - JD
#define MINIZ_X86_OR_X64_CPU 0
#define MINIZ_LITTLE_ENDIAN 1
#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 0
#define MINIZ_HAS_64BIT_REGISTERS 0
#define TINFL_USE_64BIT_BITBUF 0
#if defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i486) || defined(i386) || defined(__ia64__) || defined(__x86_64__)
// MINIZ_X86_OR_X64_CPU is only used to help set the below macros.
#define MINIZ_X86_OR_X64_CPU 1
#endif
#if (__BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) || MINIZ_X86_OR_X64_CPU
// Set MINIZ_LITTLE_ENDIAN to 1 if the processor is little endian.
#define MINIZ_LITTLE_ENDIAN 1
#endif
#if MINIZ_X86_OR_X64_CPU
// Set MINIZ_USE_UNALIGNED_LOADS_AND_STORES to 1 on CPU's that permit efficient integer loads and stores from unaligned addresses.
#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 1
#endif
#if defined(_M_X64) || defined(_WIN64) || defined(__MINGW64__) || defined(_LP64) || defined(__LP64__) || defined(__ia64__) || defined(__x86_64__)
// Set MINIZ_HAS_64BIT_REGISTERS to 1 if operations on 64-bit integers are reasonably fast (and don't involve compiler generated calls to helper functions).
#define MINIZ_HAS_64BIT_REGISTERS 1
#endif
#ifdef __cplusplus
extern "C" {
#endif
// ------------------- zlib-style API Definitions.
// For more compatibility with zlib, miniz.c uses unsigned long for some parameters/struct members. Beware: mz_ulong can be either 32 or 64-bits!
typedef unsigned long mz_ulong;
// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap.
void mz_free(void *p);
#define MZ_ADLER32_INIT (1)
// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL.
mz_ulong mz_adler32(mz_ulong adler, const unsigned char *ptr, size_t buf_len);
#define MZ_CRC32_INIT (0)
// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL.
mz_ulong mz_crc32(mz_ulong crc, const unsigned char *ptr, size_t buf_len);
// Compression strategies.
enum { MZ_DEFAULT_STRATEGY = 0, MZ_FILTERED = 1, MZ_HUFFMAN_ONLY = 2, MZ_RLE = 3, MZ_FIXED = 4 };
// Method
#define MZ_DEFLATED 8
#ifndef MINIZ_NO_ZLIB_APIS
// Heap allocation callbacks.
// Note that mz_alloc_func parameter types purpsosely differ from zlib's: items/size is size_t, not unsigned long.
typedef void *(*mz_alloc_func)(void *opaque, size_t items, size_t size);
typedef void (*mz_free_func)(void *opaque, void *address);
typedef void *(*mz_realloc_func)(void *opaque, void *address, size_t items, size_t size);
#define MZ_VERSION "9.1.15"
#define MZ_VERNUM 0x91F0
#define MZ_VER_MAJOR 9
#define MZ_VER_MINOR 1
#define MZ_VER_REVISION 15
#define MZ_VER_SUBREVISION 0
// Flush values. For typical usage you only need MZ_NO_FLUSH and MZ_FINISH. The other values are for advanced use (refer to the zlib docs).
enum { MZ_NO_FLUSH = 0, MZ_PARTIAL_FLUSH = 1, MZ_SYNC_FLUSH = 2, MZ_FULL_FLUSH = 3, MZ_FINISH = 4, MZ_BLOCK = 5 };
// Return status codes. MZ_PARAM_ERROR is non-standard.
enum { MZ_OK = 0, MZ_STREAM_END = 1, MZ_NEED_DICT = 2, MZ_ERRNO = -1, MZ_STREAM_ERROR = -2, MZ_DATA_ERROR = -3, MZ_MEM_ERROR = -4, MZ_BUF_ERROR = -5, MZ_VERSION_ERROR = -6, MZ_PARAM_ERROR = -10000 };
// Compression levels: 0-9 are the standard zlib-style levels, 10 is best possible compression (not zlib compatible, and may be very slow), MZ_DEFAULT_COMPRESSION=MZ_DEFAULT_LEVEL.
enum { MZ_NO_COMPRESSION = 0, MZ_BEST_SPEED = 1, MZ_BEST_COMPRESSION = 9, MZ_UBER_COMPRESSION = 10, MZ_DEFAULT_LEVEL = 6, MZ_DEFAULT_COMPRESSION = -1 };
// Window bits
#define MZ_DEFAULT_WINDOW_BITS 15
struct mz_internal_state;
// Compression/decompression stream struct.
typedef struct mz_stream_s
{
const unsigned char *next_in; // pointer to next byte to read
unsigned int avail_in; // number of bytes available at next_in
mz_ulong total_in; // total number of bytes consumed so far
unsigned char *next_out; // pointer to next byte to write
unsigned int avail_out; // number of bytes that can be written to next_out
mz_ulong total_out; // total number of bytes produced so far
char *msg; // error msg (unused)
struct mz_internal_state *state; // internal state, allocated by zalloc/zfree
mz_alloc_func zalloc; // optional heap allocation function (defaults to malloc)
mz_free_func zfree; // optional heap free function (defaults to free)
void *opaque; // heap alloc function user pointer
int data_type; // data_type (unused)
mz_ulong adler; // adler32 of the source or uncompressed data
mz_ulong reserved; // not used
} mz_stream;
typedef mz_stream *mz_streamp;
// Returns the version string of miniz.c.
const char *mz_version(void);
// mz_deflateInit() initializes a compressor with default options:
// Parameters:
// pStream must point to an initialized mz_stream struct.
// level must be between [MZ_NO_COMPRESSION, MZ_BEST_COMPRESSION].
// level 1 enables a specially optimized compression function that's been optimized purely for performance, not ratio.
// (This special func. is currently only enabled when MINIZ_USE_UNALIGNED_LOADS_AND_STORES and MINIZ_LITTLE_ENDIAN are defined.)
// Return values:
// MZ_OK on success.
// MZ_STREAM_ERROR if the stream is bogus.
// MZ_PARAM_ERROR if the input parameters are bogus.
// MZ_MEM_ERROR on out of memory.
int mz_deflateInit(mz_streamp pStream, int level);
// mz_deflateInit2() is like mz_deflate(), except with more control:
// Additional parameters:
// method must be MZ_DEFLATED
// window_bits must be MZ_DEFAULT_WINDOW_BITS (to wrap the deflate stream with zlib header/adler-32 footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate/no header or footer)
// mem_level must be between [1, 9] (it's checked but ignored by miniz.c)
int mz_deflateInit2(mz_streamp pStream, int level, int method, int window_bits, int mem_level, int strategy);
// Quickly resets a compressor without having to reallocate anything. Same as calling mz_deflateEnd() followed by mz_deflateInit()/mz_deflateInit2().
int mz_deflateReset(mz_streamp pStream);
// mz_deflate() compresses the input to output, consuming as much of the input and producing as much output as possible.
// Parameters:
// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
// flush may be MZ_NO_FLUSH, MZ_PARTIAL_FLUSH/MZ_SYNC_FLUSH, MZ_FULL_FLUSH, or MZ_FINISH.
// Return values:
// MZ_OK on success (when flushing, or if more input is needed but not available, and/or there's more output to be written but the output buffer is full).
// MZ_STREAM_END if all input has been consumed and all output bytes have been written. Don't call mz_deflate() on the stream anymore.
// MZ_STREAM_ERROR if the stream is bogus.
// MZ_PARAM_ERROR if one of the parameters is invalid.
// MZ_BUF_ERROR if no forward progress is possible because the input and/or output buffers are empty. (Fill up the input buffer or free up some output space and try again.)
int mz_deflate(mz_streamp pStream, int flush);
// mz_deflateEnd() deinitializes a compressor:
// Return values:
// MZ_OK on success.
// MZ_STREAM_ERROR if the stream is bogus.
int mz_deflateEnd(mz_streamp pStream);
// mz_deflateBound() returns a (very) conservative upper bound on the amount of data that could be generated by deflate(), assuming flush is set to only MZ_NO_FLUSH or MZ_FINISH.
mz_ulong mz_deflateBound(mz_streamp pStream, mz_ulong source_len);
// Single-call compression functions mz_compress() and mz_compress2():
// Returns MZ_OK on success, or one of the error codes from mz_deflate() on failure.
int mz_compress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
int mz_compress2(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len, int level);
// mz_compressBound() returns a (very) conservative upper bound on the amount of data that could be generated by calling mz_compress().
mz_ulong mz_compressBound(mz_ulong source_len);
// Initializes a decompressor.
int mz_inflateInit(mz_streamp pStream);
// mz_inflateInit2() is like mz_inflateInit() with an additional option that controls the window size and whether or not the stream has been wrapped with a zlib header/footer:
// window_bits must be MZ_DEFAULT_WINDOW_BITS (to parse zlib header/footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate).
int mz_inflateInit2(mz_streamp pStream, int window_bits);
// Decompresses the input stream to the output, consuming only as much of the input as needed, and writing as much to the output as possible.
// Parameters:
// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
// flush may be MZ_NO_FLUSH, MZ_SYNC_FLUSH, or MZ_FINISH.
// On the first call, if flush is MZ_FINISH it's assumed the input and output buffers are both sized large enough to decompress the entire stream in a single call (this is slightly faster).
// MZ_FINISH implies that there are no more source bytes available beside what's already in the input buffer, and that the output buffer is large enough to hold the rest of the decompressed data.
// Return values:
// MZ_OK on success. Either more input is needed but not available, and/or there's more output to be written but the output buffer is full.
// MZ_STREAM_END if all needed input has been consumed and all output bytes have been written. For zlib streams, the adler-32 of the decompressed data has also been verified.
// MZ_STREAM_ERROR if the stream is bogus.
// MZ_DATA_ERROR if the deflate stream is invalid.
// MZ_PARAM_ERROR if one of the parameters is invalid.
// MZ_BUF_ERROR if no forward progress is possible because the input buffer is empty but the inflater needs more input to continue, or if the output buffer is not large enough. Call mz_inflate() again
// with more input data, or with more room in the output buffer (except when using single call decompression, described above).
int mz_inflate(mz_streamp pStream, int flush);
// Deinitializes a decompressor.
int mz_inflateEnd(mz_streamp pStream);
// Single-call decompression.
// Returns MZ_OK on success, or one of the error codes from mz_inflate() on failure.
int mz_uncompress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
// Returns a string description of the specified error code, or NULL if the error code is invalid.
const char *mz_error(int err);
// Redefine zlib-compatible names to miniz equivalents, so miniz.c can be used as a drop-in replacement for the subset of zlib that miniz.c supports.
// Define MINIZ_NO_ZLIB_COMPATIBLE_NAMES to disable zlib-compatibility if you use zlib in the same project.
#ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
typedef unsigned char Byte;
typedef unsigned int uInt;
typedef mz_ulong uLong;
typedef Byte Bytef;
typedef uInt uIntf;
typedef char charf;
typedef int intf;
typedef void *voidpf;
typedef uLong uLongf;
typedef void *voidp;
typedef void *const voidpc;
#define Z_NULL 0
#define Z_NO_FLUSH MZ_NO_FLUSH
#define Z_PARTIAL_FLUSH MZ_PARTIAL_FLUSH
#define Z_SYNC_FLUSH MZ_SYNC_FLUSH
#define Z_FULL_FLUSH MZ_FULL_FLUSH
#define Z_FINISH MZ_FINISH
#define Z_BLOCK MZ_BLOCK
#define Z_OK MZ_OK
#define Z_STREAM_END MZ_STREAM_END
#define Z_NEED_DICT MZ_NEED_DICT
#define Z_ERRNO MZ_ERRNO
#define Z_STREAM_ERROR MZ_STREAM_ERROR
#define Z_DATA_ERROR MZ_DATA_ERROR
#define Z_MEM_ERROR MZ_MEM_ERROR
#define Z_BUF_ERROR MZ_BUF_ERROR
#define Z_VERSION_ERROR MZ_VERSION_ERROR
#define Z_PARAM_ERROR MZ_PARAM_ERROR
#define Z_NO_COMPRESSION MZ_NO_COMPRESSION
#define Z_BEST_SPEED MZ_BEST_SPEED
#define Z_BEST_COMPRESSION MZ_BEST_COMPRESSION
#define Z_DEFAULT_COMPRESSION MZ_DEFAULT_COMPRESSION
#define Z_DEFAULT_STRATEGY MZ_DEFAULT_STRATEGY
#define Z_FILTERED MZ_FILTERED
#define Z_HUFFMAN_ONLY MZ_HUFFMAN_ONLY
#define Z_RLE MZ_RLE
#define Z_FIXED MZ_FIXED
#define Z_DEFLATED MZ_DEFLATED
#define Z_DEFAULT_WINDOW_BITS MZ_DEFAULT_WINDOW_BITS
#define alloc_func mz_alloc_func
#define free_func mz_free_func
#define internal_state mz_internal_state
#define z_stream mz_stream
#define deflateInit mz_deflateInit
#define deflateInit2 mz_deflateInit2
#define deflateReset mz_deflateReset
#define deflate mz_deflate
#define deflateEnd mz_deflateEnd
#define deflateBound mz_deflateBound
#define compress mz_compress
#define compress2 mz_compress2
#define compressBound mz_compressBound
#define inflateInit mz_inflateInit
#define inflateInit2 mz_inflateInit2
#define inflate mz_inflate
#define inflateEnd mz_inflateEnd
#define uncompress mz_uncompress
#define crc32 mz_crc32
#define adler32 mz_adler32
#define MAX_WBITS 15
#define MAX_MEM_LEVEL 9
#define zError mz_error
#define ZLIB_VERSION MZ_VERSION
#define ZLIB_VERNUM MZ_VERNUM
#define ZLIB_VER_MAJOR MZ_VER_MAJOR
#define ZLIB_VER_MINOR MZ_VER_MINOR
#define ZLIB_VER_REVISION MZ_VER_REVISION
#define ZLIB_VER_SUBREVISION MZ_VER_SUBREVISION
#define zlibVersion mz_version
#define zlib_version mz_version()
#endif // #ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
#endif // MINIZ_NO_ZLIB_APIS
// ------------------- Types and macros
typedef unsigned char mz_uint8;
typedef signed short mz_int16;
typedef unsigned short mz_uint16;
typedef unsigned int mz_uint32;
typedef unsigned int mz_uint;
typedef long long mz_int64;
typedef unsigned long long mz_uint64;
typedef int mz_bool;
#define MZ_FALSE (0)
#define MZ_TRUE (1)
// An attempt to work around MSVC's spammy "warning C4127: conditional expression is constant" message.
#ifdef _MSC_VER
#define MZ_MACRO_END while (0, 0)
#else
#define MZ_MACRO_END while (0)
#endif
// ------------------- ZIP archive reading/writing
#ifndef MINIZ_NO_ARCHIVE_APIS
enum
{
MZ_ZIP_MAX_IO_BUF_SIZE = 64*1024,
MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE = 260,
MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE = 256
};
typedef struct
{
mz_uint32 m_file_index;
mz_uint32 m_central_dir_ofs;
mz_uint16 m_version_made_by;
mz_uint16 m_version_needed;
mz_uint16 m_bit_flag;
mz_uint16 m_method;
#ifndef MINIZ_NO_TIME
time_t m_time;
#endif
mz_uint32 m_crc32;
mz_uint64 m_comp_size;
mz_uint64 m_uncomp_size;
mz_uint16 m_internal_attr;
mz_uint32 m_external_attr;
mz_uint64 m_local_header_ofs;
mz_uint32 m_comment_size;
char m_filename[MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE];
char m_comment[MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE];
} mz_zip_archive_file_stat;
typedef size_t (*mz_file_read_func)(void *pOpaque, mz_uint64 file_ofs, void *pBuf, size_t n);
typedef size_t (*mz_file_write_func)(void *pOpaque, mz_uint64 file_ofs, const void *pBuf, size_t n);
struct mz_zip_internal_state_tag;
typedef struct mz_zip_internal_state_tag mz_zip_internal_state;
typedef enum
{
MZ_ZIP_MODE_INVALID = 0,
MZ_ZIP_MODE_READING = 1,
MZ_ZIP_MODE_WRITING = 2,
MZ_ZIP_MODE_WRITING_HAS_BEEN_FINALIZED = 3
} mz_zip_mode;
typedef struct mz_zip_archive_tag
{
mz_uint64 m_archive_size;
mz_uint64 m_central_directory_file_ofs;
mz_uint m_total_files;
mz_zip_mode m_zip_mode;
mz_uint m_file_offset_alignment;
mz_alloc_func m_pAlloc;
mz_free_func m_pFree;
mz_realloc_func m_pRealloc;
void *m_pAlloc_opaque;
mz_file_read_func m_pRead;
mz_file_write_func m_pWrite;
void *m_pIO_opaque;
mz_zip_internal_state *m_pState;
} mz_zip_archive;
typedef enum
{
MZ_ZIP_FLAG_CASE_SENSITIVE = 0x0100,
MZ_ZIP_FLAG_IGNORE_PATH = 0x0200,
MZ_ZIP_FLAG_COMPRESSED_DATA = 0x0400,
MZ_ZIP_FLAG_DO_NOT_SORT_CENTRAL_DIRECTORY = 0x0800
} mz_zip_flags;
// ZIP archive reading
// Inits a ZIP archive reader.
// These functions read and validate the archive's central directory.
mz_bool mz_zip_reader_init(mz_zip_archive *pZip, mz_uint64 size, mz_uint32 flags);
mz_bool mz_zip_reader_init_mem(mz_zip_archive *pZip, const void *pMem, size_t size, mz_uint32 flags);
#ifndef MINIZ_NO_STDIO
mz_bool mz_zip_reader_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint32 flags);
#endif
// Returns the total number of files in the archive.
mz_uint mz_zip_reader_get_num_files(mz_zip_archive *pZip);
// Returns detailed information about an archive file entry.
mz_bool mz_zip_reader_file_stat(mz_zip_archive *pZip, mz_uint file_index, mz_zip_archive_file_stat *pStat);
// Determines if an archive file entry is a directory entry.
mz_bool mz_zip_reader_is_file_a_directory(mz_zip_archive *pZip, mz_uint file_index);
mz_bool mz_zip_reader_is_file_encrypted(mz_zip_archive *pZip, mz_uint file_index);
// Retrieves the filename of an archive file entry.
// Returns the number of bytes written to pFilename, or if filename_buf_size is 0 this function returns the number of bytes needed to fully store the filename.
mz_uint mz_zip_reader_get_filename(mz_zip_archive *pZip, mz_uint file_index, char *pFilename, mz_uint filename_buf_size);
// Attempts to locates a file in the archive's central directory.
// Valid flags: MZ_ZIP_FLAG_CASE_SENSITIVE, MZ_ZIP_FLAG_IGNORE_PATH
// Returns -1 if the file cannot be found.
int mz_zip_reader_locate_file(mz_zip_archive *pZip, const char *pName, const char *pComment, mz_uint flags);
// Extracts a archive file to a memory buffer using no memory allocation.
mz_bool mz_zip_reader_extract_to_mem_no_alloc(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
mz_bool mz_zip_reader_extract_file_to_mem_no_alloc(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
// Extracts a archive file to a memory buffer.
mz_bool mz_zip_reader_extract_to_mem(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags);
mz_bool mz_zip_reader_extract_file_to_mem(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags);
// Extracts a archive file to a dynamically allocated heap buffer.
void *mz_zip_reader_extract_to_heap(mz_zip_archive *pZip, mz_uint file_index, size_t *pSize, mz_uint flags);
void *mz_zip_reader_extract_file_to_heap(mz_zip_archive *pZip, const char *pFilename, size_t *pSize, mz_uint flags);
// Extracts a archive file using a callback function to output the file's data.
mz_bool mz_zip_reader_extract_to_callback(mz_zip_archive *pZip, mz_uint file_index, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
mz_bool mz_zip_reader_extract_file_to_callback(mz_zip_archive *pZip, const char *pFilename, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
#ifndef MINIZ_NO_STDIO
// Extracts a archive file to a disk file and sets its last accessed and modified times.
// This function only extracts files, not archive directory records.
mz_bool mz_zip_reader_extract_to_file(mz_zip_archive *pZip, mz_uint file_index, const char *pDst_filename, mz_uint flags);
mz_bool mz_zip_reader_extract_file_to_file(mz_zip_archive *pZip, const char *pArchive_filename, const char *pDst_filename, mz_uint flags);
#endif
// Ends archive reading, freeing all allocations, and closing the input archive file if mz_zip_reader_init_file() was used.
mz_bool mz_zip_reader_end(mz_zip_archive *pZip);
// ZIP archive writing
#ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
// Inits a ZIP archive writer.
mz_bool mz_zip_writer_init(mz_zip_archive *pZip, mz_uint64 existing_size);
mz_bool mz_zip_writer_init_heap(mz_zip_archive *pZip, size_t size_to_reserve_at_beginning, size_t initial_allocation_size);
#ifndef MINIZ_NO_STDIO
mz_bool mz_zip_writer_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint64 size_to_reserve_at_beginning);
#endif
// Converts a ZIP archive reader object into a writer object, to allow efficient in-place file appends to occur on an existing archive.
// For archives opened using mz_zip_reader_init_file, pFilename must be the archive's filename so it can be reopened for writing. If the file can't be reopened, mz_zip_reader_end() will be called.
// For archives opened using mz_zip_reader_init_mem, the memory block must be growable using the realloc callback (which defaults to realloc unless you've overridden it).
// Finally, for archives opened using mz_zip_reader_init, the mz_zip_archive's user provided m_pWrite function cannot be NULL.
// Note: In-place archive modification is not recommended unless you know what you're doing, because if execution stops or something goes wrong before
// the archive is finalized the file's central directory will be hosed.
mz_bool mz_zip_writer_init_from_reader(mz_zip_archive *pZip, const char *pFilename);
// Adds the contents of a memory buffer to an archive. These functions record the current local time into the archive.
// To add a directory entry, call this method with an archive name ending in a forwardslash with empty buffer.
// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
mz_bool mz_zip_writer_add_mem(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, mz_uint level_and_flags);
mz_bool mz_zip_writer_add_mem_ex(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags, mz_uint64 uncomp_size, mz_uint32 uncomp_crc32);
#ifndef MINIZ_NO_STDIO
// Adds the contents of a disk file to an archive. This function also records the disk file's modified time into the archive.
// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
mz_bool mz_zip_writer_add_file(mz_zip_archive *pZip, const char *pArchive_name, const char *pSrc_filename, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
#endif
// Adds a file to an archive by fully cloning the data from another archive.
// This function fully clones the source file's compressed data (no recompression), along with its full filename, extra data, and comment fields.
mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive *pSource_zip, mz_uint file_index);
// Finalizes the archive by writing the central directory records followed by the end of central directory record.
// After an archive is finalized, the only valid call on the mz_zip_archive struct is mz_zip_writer_end().
// An archive must be manually finalized by calling this function for it to be valid.
mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip);
mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **pBuf, size_t *pSize);
// Ends archive writing, freeing all allocations, and closing the output file if mz_zip_writer_init_file() was used.
// Note for the archive to be valid, it must have been finalized before ending.
mz_bool mz_zip_writer_end(mz_zip_archive *pZip);
// Misc. high-level helper functions:
// mz_zip_add_mem_to_archive_file_in_place() efficiently (but not atomically) appends a memory blob to a ZIP archive.
// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
mz_bool mz_zip_add_mem_to_archive_file_in_place(const char *pZip_filename, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
// Reads a single file from an archive into a heap block.
// Returns NULL on failure.
void *mz_zip_extract_archive_file_to_heap(const char *pZip_filename, const char *pArchive_name, size_t *pSize, mz_uint zip_flags);
#endif // #ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
#endif // #ifndef MINIZ_NO_ARCHIVE_APIS
// ------------------- Low-level Decompression API Definitions
// Decompression flags used by tinfl_decompress().
// TINFL_FLAG_PARSE_ZLIB_HEADER: If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib stream). Otherwise, the input is a raw deflate stream.
// TINFL_FLAG_HAS_MORE_INPUT: If set, there are more input bytes available beyond the end of the supplied input buffer. If clear, the input buffer contains all remaining input.
// TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: If set, the output buffer is large enough to hold the entire decompressed stream. If clear, the output buffer is at least the size of the dictionary (typically 32KB).
// TINFL_FLAG_COMPUTE_ADLER32: Force adler-32 checksum computation of the decompressed bytes.
enum
{
TINFL_FLAG_PARSE_ZLIB_HEADER = 1,
TINFL_FLAG_HAS_MORE_INPUT = 2,
TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF = 4,
TINFL_FLAG_COMPUTE_ADLER32 = 8
};
// High level decompression functions:
// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc().
// On entry:
// pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress.
// On return:
// Function returns a pointer to the decompressed data, or NULL on failure.
// *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data.
// The caller must call mz_free() on the returned block when it's no longer needed.
void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
// tinfl_decompress_mem_to_mem() decompresses a block in memory to another block in memory.
// Returns TINFL_DECOMPRESS_MEM_TO_MEM_FAILED on failure, or the number of bytes written on success.
#define TINFL_DECOMPRESS_MEM_TO_MEM_FAILED ((size_t)(-1))
size_t tinfl_decompress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
// tinfl_decompress_mem_to_callback() decompresses a block in memory to an internal 32KB buffer, and a user provided callback function will be called to flush the buffer.
// Returns 1 on success or 0 on failure.
typedef int (*tinfl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser);
int tinfl_decompress_mem_to_callback(const void *pIn_buf, size_t *pIn_buf_size, tinfl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
struct tinfl_decompressor_tag; typedef struct tinfl_decompressor_tag tinfl_decompressor;
// Max size of LZ dictionary.
#define TINFL_LZ_DICT_SIZE 32768
// Return status.
typedef enum
{
TINFL_STATUS_BAD_PARAM = -3,
TINFL_STATUS_ADLER32_MISMATCH = -2,
TINFL_STATUS_FAILED = -1,
TINFL_STATUS_DONE = 0,
TINFL_STATUS_NEEDS_MORE_INPUT = 1,
TINFL_STATUS_HAS_MORE_OUTPUT = 2
} tinfl_status;
// Initializes the decompressor to its initial state.
#define tinfl_init(r) do { (r)->m_state = 0; } MZ_MACRO_END
#define tinfl_get_adler32(r) (r)->m_check_adler32
// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability.
// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output.
tinfl_status tinfl_decompress(tinfl_decompressor *r, const mz_uint8 *pIn_buf_next, size_t *pIn_buf_size, mz_uint8 *pOut_buf_start, mz_uint8 *pOut_buf_next, size_t *pOut_buf_size, const mz_uint32 decomp_flags);
// Internal/private bits follow.
enum
{
TINFL_MAX_HUFF_TABLES = 3, TINFL_MAX_HUFF_SYMBOLS_0 = 288, TINFL_MAX_HUFF_SYMBOLS_1 = 32, TINFL_MAX_HUFF_SYMBOLS_2 = 19,
TINFL_FAST_LOOKUP_BITS = 10, TINFL_FAST_LOOKUP_SIZE = 1 << TINFL_FAST_LOOKUP_BITS
};
typedef struct
{
mz_uint8 m_code_size[TINFL_MAX_HUFF_SYMBOLS_0];
mz_int16 m_look_up[TINFL_FAST_LOOKUP_SIZE], m_tree[TINFL_MAX_HUFF_SYMBOLS_0 * 2];
} tinfl_huff_table;
#if MINIZ_HAS_64BIT_REGISTERS
#define TINFL_USE_64BIT_BITBUF 1
#endif
#if TINFL_USE_64BIT_BITBUF
typedef mz_uint64 tinfl_bit_buf_t;
#define TINFL_BITBUF_SIZE (64)
#else
typedef mz_uint32 tinfl_bit_buf_t;
#define TINFL_BITBUF_SIZE (32)
#endif
struct tinfl_decompressor_tag
{
mz_uint32 m_state, m_num_bits, m_zhdr0, m_zhdr1, m_z_adler32, m_final, m_type, m_check_adler32, m_dist, m_counter, m_num_extra, m_table_sizes[TINFL_MAX_HUFF_TABLES];
tinfl_bit_buf_t m_bit_buf;
size_t m_dist_from_out_buf_start;
tinfl_huff_table m_tables[TINFL_MAX_HUFF_TABLES];
mz_uint8 m_raw_header[4], m_len_codes[TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137];
};
// ------------------- Low-level Compression API Definitions
// Set TDEFL_LESS_MEMORY to 1 to use less memory (compression will be slightly slower, and raw/dynamic blocks will be output more frequently).
#define TDEFL_LESS_MEMORY 1
// tdefl_init() compression flags logically OR'd together (low 12 bits contain the max. number of probes per dictionary search):
// TDEFL_DEFAULT_MAX_PROBES: The compressor defaults to 128 dictionary probes per dictionary search. 0=Huffman only, 1=Huffman+LZ (fastest/crap compression), 4095=Huffman+LZ (slowest/best compression).
enum
{
TDEFL_HUFFMAN_ONLY = 0, TDEFL_DEFAULT_MAX_PROBES = 128, TDEFL_MAX_PROBES_MASK = 0xFFF
};
// TDEFL_WRITE_ZLIB_HEADER: If set, the compressor outputs a zlib header before the deflate data, and the Adler-32 of the source data at the end. Otherwise, you'll get raw deflate data.
// TDEFL_COMPUTE_ADLER32: Always compute the adler-32 of the input data (even when not writing zlib headers).
// TDEFL_GREEDY_PARSING_FLAG: Set to use faster greedy parsing, instead of more efficient lazy parsing.
// TDEFL_NONDETERMINISTIC_PARSING_FLAG: Enable to decrease the compressor's initialization time to the minimum, but the output may vary from run to run given the same input (depending on the contents of memory).
// TDEFL_RLE_MATCHES: Only look for RLE matches (matches with a distance of 1)
// TDEFL_FILTER_MATCHES: Discards matches <= 5 chars if enabled.
// TDEFL_FORCE_ALL_STATIC_BLOCKS: Disable usage of optimized Huffman tables.
// TDEFL_FORCE_ALL_RAW_BLOCKS: Only use raw (uncompressed) deflate blocks.
// The low 12 bits are reserved to control the max # of hash probes per dictionary lookup (see TDEFL_MAX_PROBES_MASK).
enum
{
TDEFL_WRITE_ZLIB_HEADER = 0x01000,
TDEFL_COMPUTE_ADLER32 = 0x02000,
TDEFL_GREEDY_PARSING_FLAG = 0x04000,
TDEFL_NONDETERMINISTIC_PARSING_FLAG = 0x08000,
TDEFL_RLE_MATCHES = 0x10000,
TDEFL_FILTER_MATCHES = 0x20000,
TDEFL_FORCE_ALL_STATIC_BLOCKS = 0x40000,
TDEFL_FORCE_ALL_RAW_BLOCKS = 0x80000
};
// High level compression functions:
// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc().
// On entry:
// pSrc_buf, src_buf_len: Pointer and size of source block to compress.
// flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression.
// On return:
// Function returns a pointer to the compressed data, or NULL on failure.
// *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data.
// The caller must free() the returned block when it's no longer needed.
void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory.
// Returns 0 on failure.
size_t tdefl_compress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
// Compresses an image to a compressed PNG file in memory.
// On entry:
// pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4.
// The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory.
// level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL
// If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps).
// On return:
// Function returns a pointer to the compressed data, or NULL on failure.
// *pLen_out will be set to the size of the PNG image file.
// The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed.
void *tdefl_write_image_to_png_file_in_memory_ex(const void *pImage, int w, int h, int num_chans, size_t *pLen_out, mz_uint level, mz_bool flip);
void *tdefl_write_image_to_png_file_in_memory(const void *pImage, int w, int h, int num_chans, size_t *pLen_out);
// Output stream interface. The compressor uses this interface to write compressed data. It'll typically be called TDEFL_OUT_BUF_SIZE at a time.
typedef mz_bool (*tdefl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser);
// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally.
mz_bool tdefl_compress_mem_to_output(const void *pBuf, size_t buf_len, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
enum { TDEFL_MAX_HUFF_TABLES = 3, TDEFL_MAX_HUFF_SYMBOLS_0 = 288, TDEFL_MAX_HUFF_SYMBOLS_1 = 32, TDEFL_MAX_HUFF_SYMBOLS_2 = 19, TDEFL_LZ_DICT_SIZE = 32768, TDEFL_LZ_DICT_SIZE_MASK = TDEFL_LZ_DICT_SIZE - 1, TDEFL_MIN_MATCH_LEN = 3, TDEFL_MAX_MATCH_LEN = 258 };
// TDEFL_OUT_BUF_SIZE MUST be large enough to hold a single entire compressed output block (using static/fixed Huffman codes).
#if TDEFL_LESS_MEMORY
enum { TDEFL_LZ_CODE_BUF_SIZE = 24 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 12, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
#else
enum { TDEFL_LZ_CODE_BUF_SIZE = 64 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 15, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
#endif
// The low-level tdefl functions below may be used directly if the above helper functions aren't flexible enough. The low-level functions don't make any heap allocations, unlike the above helper functions.
typedef enum
{
TDEFL_STATUS_BAD_PARAM = -2,
TDEFL_STATUS_PUT_BUF_FAILED = -1,
TDEFL_STATUS_OKAY = 0,
TDEFL_STATUS_DONE = 1,
} tdefl_status;
// Must map to MZ_NO_FLUSH, MZ_SYNC_FLUSH, etc. enums
typedef enum
{
TDEFL_NO_FLUSH = 0,
TDEFL_SYNC_FLUSH = 2,
TDEFL_FULL_FLUSH = 3,
TDEFL_FINISH = 4
} tdefl_flush;
// tdefl's compression state structure.
typedef struct
{
tdefl_put_buf_func_ptr m_pPut_buf_func;
void *m_pPut_buf_user;
mz_uint m_flags, m_max_probes[2];
int m_greedy_parsing;
mz_uint m_adler32, m_lookahead_pos, m_lookahead_size, m_dict_size;
mz_uint8 *m_pLZ_code_buf, *m_pLZ_flags, *m_pOutput_buf, *m_pOutput_buf_end;
mz_uint m_num_flags_left, m_total_lz_bytes, m_lz_code_buf_dict_pos, m_bits_in, m_bit_buffer;
mz_uint m_saved_match_dist, m_saved_match_len, m_saved_lit, m_output_flush_ofs, m_output_flush_remaining, m_finished, m_block_index, m_wants_to_finish;
tdefl_status m_prev_return_status;
const void *m_pIn_buf;
void *m_pOut_buf;
size_t *m_pIn_buf_size, *m_pOut_buf_size;
tdefl_flush m_flush;
const mz_uint8 *m_pSrc;
size_t m_src_buf_left, m_out_buf_ofs;
mz_uint8 m_dict[TDEFL_LZ_DICT_SIZE + TDEFL_MAX_MATCH_LEN - 1];
mz_uint16 m_huff_count[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
mz_uint16 m_huff_codes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
mz_uint8 m_huff_code_sizes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
mz_uint8 m_lz_code_buf[TDEFL_LZ_CODE_BUF_SIZE];
mz_uint16 m_next[TDEFL_LZ_DICT_SIZE];
mz_uint16 m_hash[TDEFL_LZ_HASH_SIZE];
mz_uint8 m_output_buf[TDEFL_OUT_BUF_SIZE];
} tdefl_compressor;
// Initializes the compressor.
// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory.
// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression.
// If pBut_buf_func is NULL the user should always call the tdefl_compress() API.
// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.)
tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible.
tdefl_status tdefl_compress(tdefl_compressor *d, const void *pIn_buf, size_t *pIn_buf_size, void *pOut_buf, size_t *pOut_buf_size, tdefl_flush flush);
// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr.
// tdefl_compress_buffer() always consumes the entire input buffer.
tdefl_status tdefl_compress_buffer(tdefl_compressor *d, const void *pIn_buf, size_t in_buf_size, tdefl_flush flush);
tdefl_status tdefl_get_prev_return_status(tdefl_compressor *d);
mz_uint32 tdefl_get_adler32(tdefl_compressor *d);
// Can't use tdefl_create_comp_flags_from_zip_params if MINIZ_NO_ZLIB_APIS isn't defined, because it uses some of its macros.
#ifndef MINIZ_NO_ZLIB_APIS
// Create tdefl_compress() flags given zlib-style compression parameters.
// level may range from [0,10] (where 10 is absolute max compression, but may be much slower on some files)
// window_bits may be -15 (raw deflate) or 15 (zlib)
// strategy may be either MZ_DEFAULT_STRATEGY, MZ_FILTERED, MZ_HUFFMAN_ONLY, MZ_RLE, or MZ_FIXED
mz_uint tdefl_create_comp_flags_from_zip_params(int level, int window_bits, int strategy);
#endif // #ifndef MINIZ_NO_ZLIB_APIS
#ifdef __cplusplus
}
#endif
#endif // MINIZ_HEADER_INCLUDED
#warning rom/miniz.h is deprecated, please use esp32/rom/miniz.h instead
#include "esp32/rom/miniz.h"

647
tools/sdk/include/esp32/rom/queue.h
View File

@ -1,645 +1,2 @@
/*-
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)queue.h 8.5 (Berkeley) 8/20/94
* $FreeBSD$
*/
#ifndef _SYS_QUEUE_H_
#define _SYS_QUEUE_H_
#include <sys/cdefs.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file defines four types of data structures: singly-linked lists,
* singly-linked tail queues, lists and tail queues.
*
* A singly-linked list is headed by a single forward pointer. The elements
* are singly linked for minimum space and pointer manipulation overhead at
* the expense of O(n) removal for arbitrary elements. New elements can be
* added to the list after an existing element or at the head of the list.
* Elements being removed from the head of the list should use the explicit
* macro for this purpose for optimum efficiency. A singly-linked list may
* only be traversed in the forward direction. Singly-linked lists are ideal
* for applications with large datasets and few or no removals or for
* implementing a LIFO queue.
*
* A singly-linked tail queue is headed by a pair of pointers, one to the
* head of the list and the other to the tail of the list. The elements are
* singly linked for minimum space and pointer manipulation overhead at the
* expense of O(n) removal for arbitrary elements. New elements can be added
* to the list after an existing element, at the head of the list, or at the
* end of the list. Elements being removed from the head of the tail queue
* should use the explicit macro for this purpose for optimum efficiency.
* A singly-linked tail queue may only be traversed in the forward direction.
* Singly-linked tail queues are ideal for applications with large datasets
* and few or no removals or for implementing a FIFO queue.
*
* A list is headed by a single forward pointer (or an array of forward
* pointers for a hash table header). The elements are doubly linked
* so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before
* or after an existing element or at the head of the list. A list
* may only be traversed in the forward direction.
*
* A tail queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or
* after an existing element, at the head of the list, or at the end of
* the list. A tail queue may be traversed in either direction.
*
* For details on the use of these macros, see the queue(3) manual page.
*
*
* SLIST LIST STAILQ TAILQ
* _HEAD + + + +
* _HEAD_INITIALIZER + + + +
* _ENTRY + + + +
* _INIT + + + +
* _EMPTY + + + +
* _FIRST + + + +
* _NEXT + + + +
* _PREV - - - +
* _LAST - - + +
* _FOREACH + + + +
* _FOREACH_SAFE + + + +
* _FOREACH_REVERSE - - - +
* _FOREACH_REVERSE_SAFE - - - +
* _INSERT_HEAD + + + +
* _INSERT_BEFORE - + - +
* _INSERT_AFTER + + + +
* _INSERT_TAIL - - + +
* _CONCAT - - + +
* _REMOVE_AFTER + - + -
* _REMOVE_HEAD + - + -
* _REMOVE + + + +
*
*/
#ifdef QUEUE_MACRO_DEBUG
/* Store the last 2 places the queue element or head was altered */
struct qm_trace {
char * lastfile;
int lastline;
char * prevfile;
int prevline;
};
#define TRACEBUF struct qm_trace trace;
#define TRASHIT(x) do {(x) = (void *)-1;} while (0)
#define QMD_SAVELINK(name, link) void **name = (void *)&(link)
#define QMD_TRACE_HEAD(head) do { \
(head)->trace.prevline = (head)->trace.lastline; \
(head)->trace.prevfile = (head)->trace.lastfile; \
(head)->trace.lastline = __LINE__; \
(head)->trace.lastfile = __FILE__; \
} while (0)
#define QMD_TRACE_ELEM(elem) do { \
(elem)->trace.prevline = (elem)->trace.lastline; \
(elem)->trace.prevfile = (elem)->trace.lastfile; \
(elem)->trace.lastline = __LINE__; \
(elem)->trace.lastfile = __FILE__; \
} while (0)
#else
#define QMD_TRACE_ELEM(elem)
#define QMD_TRACE_HEAD(head)
#define QMD_SAVELINK(name, link)
#define TRACEBUF
#define TRASHIT(x)
#endif /* QUEUE_MACRO_DEBUG */
/*
* Singly-linked List declarations.
*/
#define SLIST_HEAD(name, type) \
struct name { \
struct type *slh_first; /* first element */ \
}
#define SLIST_HEAD_INITIALIZER(head) \
{ NULL }
#define SLIST_ENTRY(type) \
struct { \
struct type *sle_next; /* next element */ \
}
/*
* Singly-linked List functions.
*/
#define SLIST_EMPTY(head) ((head)->slh_first == NULL)
#define SLIST_FIRST(head) ((head)->slh_first)
#define SLIST_FOREACH(var, head, field) \
for ((var) = SLIST_FIRST((head)); \
(var); \
(var) = SLIST_NEXT((var), field))
#define SLIST_FOREACH_SAFE(var, head, field, tvar) \
for ((var) = SLIST_FIRST((head)); \
(var) && ((tvar) = SLIST_NEXT((var), field), 1); \
(var) = (tvar))
#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \
for ((varp) = &SLIST_FIRST((head)); \
((var) = *(varp)) != NULL; \
(varp) = &SLIST_NEXT((var), field))
#define SLIST_INIT(head) do { \
SLIST_FIRST((head)) = NULL; \
} while (0)
#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \
SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \
SLIST_NEXT((slistelm), field) = (elm); \
} while (0)
#define SLIST_INSERT_HEAD(head, elm, field) do { \
SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \
SLIST_FIRST((head)) = (elm); \
} while (0)
#define SLIST_NEXT(elm, field) ((elm)->field.sle_next)
#define SLIST_REMOVE(head, elm, type, field) do { \
QMD_SAVELINK(oldnext, (elm)->field.sle_next); \
if (SLIST_FIRST((head)) == (elm)) { \
SLIST_REMOVE_HEAD((head), field); \
} \
else { \
struct type *curelm = SLIST_FIRST((head)); \
while (SLIST_NEXT(curelm, field) != (elm)) \
curelm = SLIST_NEXT(curelm, field); \
SLIST_REMOVE_AFTER(curelm, field); \
} \
TRASHIT(*oldnext); \
} while (0)
#define SLIST_REMOVE_AFTER(elm, field) do { \
SLIST_NEXT(elm, field) = \
SLIST_NEXT(SLIST_NEXT(elm, field), field); \
} while (0)
#define SLIST_REMOVE_HEAD(head, field) do { \
SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \
} while (0)
/*
* Singly-linked Tail queue declarations.
*/
#define STAILQ_HEAD(name, type) \
struct name { \
struct type *stqh_first;/* first element */ \
struct type **stqh_last;/* addr of last next element */ \
}
#define STAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).stqh_first }
#define STAILQ_ENTRY(type) \
struct { \
struct type *stqe_next; /* next element */ \
}
/*
* Singly-linked Tail queue functions.
*/
#define STAILQ_CONCAT(head1, head2) do { \
if (!STAILQ_EMPTY((head2))) { \
*(head1)->stqh_last = (head2)->stqh_first; \
(head1)->stqh_last = (head2)->stqh_last; \
STAILQ_INIT((head2)); \
} \
} while (0)
#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL)
#define STAILQ_FIRST(head) ((head)->stqh_first)
#define STAILQ_FOREACH(var, head, field) \
for((var) = STAILQ_FIRST((head)); \
(var); \
(var) = STAILQ_NEXT((var), field))
#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \
for ((var) = STAILQ_FIRST((head)); \
(var) && ((tvar) = STAILQ_NEXT((var), field), 1); \
(var) = (tvar))
#define STAILQ_INIT(head) do { \
STAILQ_FIRST((head)) = NULL; \
(head)->stqh_last = &STAILQ_FIRST((head)); \
} while (0)
#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \
if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
STAILQ_NEXT((tqelm), field) = (elm); \
} while (0)
#define STAILQ_INSERT_HEAD(head, elm, field) do { \
if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
STAILQ_FIRST((head)) = (elm); \
} while (0)
#define STAILQ_INSERT_TAIL(head, elm, field) do { \
STAILQ_NEXT((elm), field) = NULL; \
*(head)->stqh_last = (elm); \
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
} while (0)
#define STAILQ_LAST(head, type, field) \
(STAILQ_EMPTY((head)) ? \
NULL : \
((struct type *)(void *) \
((char *)((head)->stqh_last) - __offsetof(struct type, field))))
#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
#define STAILQ_REMOVE(head, elm, type, field) do { \
QMD_SAVELINK(oldnext, (elm)->field.stqe_next); \
if (STAILQ_FIRST((head)) == (elm)) { \
STAILQ_REMOVE_HEAD((head), field); \
} \
else { \
struct type *curelm = STAILQ_FIRST((head)); \
while (STAILQ_NEXT(curelm, field) != (elm)) \
curelm = STAILQ_NEXT(curelm, field); \
STAILQ_REMOVE_AFTER(head, curelm, field); \
} \
TRASHIT(*oldnext); \
} while (0)
#define STAILQ_REMOVE_HEAD(head, field) do { \
if ((STAILQ_FIRST((head)) = \
STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \
(head)->stqh_last = &STAILQ_FIRST((head)); \
} while (0)
#define STAILQ_REMOVE_AFTER(head, elm, field) do { \
if ((STAILQ_NEXT(elm, field) = \
STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL) \
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
} while (0)
#define STAILQ_SWAP(head1, head2, type) do { \
struct type *swap_first = STAILQ_FIRST(head1); \
struct type **swap_last = (head1)->stqh_last; \
STAILQ_FIRST(head1) = STAILQ_FIRST(head2); \
(head1)->stqh_last = (head2)->stqh_last; \
STAILQ_FIRST(head2) = swap_first; \
(head2)->stqh_last = swap_last; \
if (STAILQ_EMPTY(head1)) \
(head1)->stqh_last = &STAILQ_FIRST(head1); \
if (STAILQ_EMPTY(head2)) \
(head2)->stqh_last = &STAILQ_FIRST(head2); \
} while (0)
#define STAILQ_INSERT_CHAIN_HEAD(head, elm_chead, elm_ctail, field) do { \
if ((STAILQ_NEXT(elm_ctail, field) = STAILQ_FIRST(head)) == NULL ) { \
(head)->stqh_last = &STAILQ_NEXT(elm_ctail, field); \
} \
STAILQ_FIRST(head) = (elm_chead); \
} while (0)
/*
* List declarations.
*/
#define LIST_HEAD(name, type) \
struct name { \
struct type *lh_first; /* first element */ \
}
#define LIST_HEAD_INITIALIZER(head) \
{ NULL }
#define LIST_ENTRY(type) \
struct { \
struct type *le_next; /* next element */ \
struct type **le_prev; /* address of previous next element */ \
}
/*
* List functions.
*/
#if (defined(_KERNEL) && defined(INVARIANTS))
#define QMD_LIST_CHECK_HEAD(head, field) do { \
if (LIST_FIRST((head)) != NULL && \
LIST_FIRST((head))->field.le_prev != \
&LIST_FIRST((head))) \
panic("Bad list head %p first->prev != head", (head)); \
} while (0)
#define QMD_LIST_CHECK_NEXT(elm, field) do { \
if (LIST_NEXT((elm), field) != NULL && \
LIST_NEXT((elm), field)->field.le_prev != \
&((elm)->field.le_next)) \
panic("Bad link elm %p next->prev != elm", (elm)); \
} while (0)
#define QMD_LIST_CHECK_PREV(elm, field) do { \
if (*(elm)->field.le_prev != (elm)) \
panic("Bad link elm %p prev->next != elm", (elm)); \
} while (0)
#else
#define QMD_LIST_CHECK_HEAD(head, field)
#define QMD_LIST_CHECK_NEXT(elm, field)
#define QMD_LIST_CHECK_PREV(elm, field)
#endif /* (_KERNEL && INVARIANTS) */
#define LIST_EMPTY(head) ((head)->lh_first == NULL)
#define LIST_FIRST(head) ((head)->lh_first)
#define LIST_FOREACH(var, head, field) \
for ((var) = LIST_FIRST((head)); \
(var); \
(var) = LIST_NEXT((var), field))
#define LIST_FOREACH_SAFE(var, head, field, tvar) \
for ((var) = LIST_FIRST((head)); \
(var) && ((tvar) = LIST_NEXT((var), field), 1); \
(var) = (tvar))
#define LIST_INIT(head) do { \
LIST_FIRST((head)) = NULL; \
} while (0)
#define LIST_INSERT_AFTER(listelm, elm, field) do { \
QMD_LIST_CHECK_NEXT(listelm, field); \
if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
LIST_NEXT((listelm), field)->field.le_prev = \
&LIST_NEXT((elm), field); \
LIST_NEXT((listelm), field) = (elm); \
(elm)->field.le_prev = &LIST_NEXT((listelm), field); \
} while (0)
#define LIST_INSERT_BEFORE(listelm, elm, field) do { \
QMD_LIST_CHECK_PREV(listelm, field); \
(elm)->field.le_prev = (listelm)->field.le_prev; \
LIST_NEXT((elm), field) = (listelm); \
*(listelm)->field.le_prev = (elm); \
(listelm)->field.le_prev = &LIST_NEXT((elm), field); \
} while (0)
#define LIST_INSERT_HEAD(head, elm, field) do { \
QMD_LIST_CHECK_HEAD((head), field); \
if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \
LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
LIST_FIRST((head)) = (elm); \
(elm)->field.le_prev = &LIST_FIRST((head)); \
} while (0)
#define LIST_NEXT(elm, field) ((elm)->field.le_next)
#define LIST_REMOVE(elm, field) do { \
QMD_SAVELINK(oldnext, (elm)->field.le_next); \
QMD_SAVELINK(oldprev, (elm)->field.le_prev); \
QMD_LIST_CHECK_NEXT(elm, field); \
QMD_LIST_CHECK_PREV(elm, field); \
if (LIST_NEXT((elm), field) != NULL) \
LIST_NEXT((elm), field)->field.le_prev = \
(elm)->field.le_prev; \
*(elm)->field.le_prev = LIST_NEXT((elm), field); \
TRASHIT(*oldnext); \
TRASHIT(*oldprev); \
} while (0)
#define LIST_SWAP(head1, head2, type, field) do { \
struct type *swap_tmp = LIST_FIRST((head1)); \
LIST_FIRST((head1)) = LIST_FIRST((head2)); \
LIST_FIRST((head2)) = swap_tmp; \
if ((swap_tmp = LIST_FIRST((head1))) != NULL) \
swap_tmp->field.le_prev = &LIST_FIRST((head1)); \
if ((swap_tmp = LIST_FIRST((head2))) != NULL) \
swap_tmp->field.le_prev = &LIST_FIRST((head2)); \
} while (0)
/*
* Tail queue declarations.
*/
#define TAILQ_HEAD(name, type) \
struct name { \
struct type *tqh_first; /* first element */ \
struct type **tqh_last; /* addr of last next element */ \
TRACEBUF \
}
#define TAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).tqh_first }
#define TAILQ_ENTRY(type) \
struct { \
struct type *tqe_next; /* next element */ \
struct type **tqe_prev; /* address of previous next element */ \
TRACEBUF \
}
/*
* Tail queue functions.
*/
#if (defined(_KERNEL) && defined(INVARIANTS))
#define QMD_TAILQ_CHECK_HEAD(head, field) do { \
if (!TAILQ_EMPTY(head) && \
TAILQ_FIRST((head))->field.tqe_prev != \
&TAILQ_FIRST((head))) \
panic("Bad tailq head %p first->prev != head", (head)); \
} while (0)
#define QMD_TAILQ_CHECK_TAIL(head, field) do { \
if (*(head)->tqh_last != NULL) \
panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); \
} while (0)
#define QMD_TAILQ_CHECK_NEXT(elm, field) do { \
if (TAILQ_NEXT((elm), field) != NULL && \
TAILQ_NEXT((elm), field)->field.tqe_prev != \
&((elm)->field.tqe_next)) \
panic("Bad link elm %p next->prev != elm", (elm)); \
} while (0)
#define QMD_TAILQ_CHECK_PREV(elm, field) do { \
if (*(elm)->field.tqe_prev != (elm)) \
panic("Bad link elm %p prev->next != elm", (elm)); \
} while (0)
#else
#define QMD_TAILQ_CHECK_HEAD(head, field)
#define QMD_TAILQ_CHECK_TAIL(head, headname)
#define QMD_TAILQ_CHECK_NEXT(elm, field)
#define QMD_TAILQ_CHECK_PREV(elm, field)
#endif /* (_KERNEL && INVARIANTS) */
#define TAILQ_CONCAT(head1, head2, field) do { \
if (!TAILQ_EMPTY(head2)) { \
*(head1)->tqh_last = (head2)->tqh_first; \
(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \
(head1)->tqh_last = (head2)->tqh_last; \
TAILQ_INIT((head2)); \
QMD_TRACE_HEAD(head1); \
QMD_TRACE_HEAD(head2); \
} \
} while (0)
#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
#define TAILQ_FIRST(head) ((head)->tqh_first)
#define TAILQ_FOREACH(var, head, field) \
for ((var) = TAILQ_FIRST((head)); \
(var); \
(var) = TAILQ_NEXT((var), field))
#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \
for ((var) = TAILQ_FIRST((head)); \
(var) && ((tvar) = TAILQ_NEXT((var), field), 1); \
(var) = (tvar))
#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
for ((var) = TAILQ_LAST((head), headname); \
(var); \
(var) = TAILQ_PREV((var), headname, field))
#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \
for ((var) = TAILQ_LAST((head), headname); \
(var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \
(var) = (tvar))
#define TAILQ_INIT(head) do { \
TAILQ_FIRST((head)) = NULL; \
(head)->tqh_last = &TAILQ_FIRST((head)); \
QMD_TRACE_HEAD(head); \
} while (0)
#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
QMD_TAILQ_CHECK_NEXT(listelm, field); \
if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
TAILQ_NEXT((elm), field)->field.tqe_prev = \
&TAILQ_NEXT((elm), field); \
else { \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
QMD_TRACE_HEAD(head); \
} \
TAILQ_NEXT((listelm), field) = (elm); \
(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \
QMD_TRACE_ELEM(&(elm)->field); \
QMD_TRACE_ELEM(&listelm->field); \
} while (0)
#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
QMD_TAILQ_CHECK_PREV(listelm, field); \
(elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
TAILQ_NEXT((elm), field) = (listelm); \
*(listelm)->field.tqe_prev = (elm); \
(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \
QMD_TRACE_ELEM(&(elm)->field); \
QMD_TRACE_ELEM(&listelm->field); \
} while (0)
#define TAILQ_INSERT_HEAD(head, elm, field) do { \
QMD_TAILQ_CHECK_HEAD(head, field); \
if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \
TAILQ_FIRST((head))->field.tqe_prev = \
&TAILQ_NEXT((elm), field); \
else \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
TAILQ_FIRST((head)) = (elm); \
(elm)->field.tqe_prev = &TAILQ_FIRST((head)); \
QMD_TRACE_HEAD(head); \
QMD_TRACE_ELEM(&(elm)->field); \
} while (0)
#define TAILQ_INSERT_TAIL(head, elm, field) do { \
QMD_TAILQ_CHECK_TAIL(head, field); \
TAILQ_NEXT((elm), field) = NULL; \
(elm)->field.tqe_prev = (head)->tqh_last; \
*(head)->tqh_last = (elm); \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
QMD_TRACE_HEAD(head); \
QMD_TRACE_ELEM(&(elm)->field); \
} while (0)
#define TAILQ_LAST(head, headname) \
(*(((struct headname *)((head)->tqh_last))->tqh_last))
#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
#define TAILQ_PREV(elm, headname, field) \
(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
#define TAILQ_REMOVE(head, elm, field) do { \
QMD_SAVELINK(oldnext, (elm)->field.tqe_next); \
QMD_SAVELINK(oldprev, (elm)->field.tqe_prev); \
QMD_TAILQ_CHECK_NEXT(elm, field); \
QMD_TAILQ_CHECK_PREV(elm, field); \
if ((TAILQ_NEXT((elm), field)) != NULL) \
TAILQ_NEXT((elm), field)->field.tqe_prev = \
(elm)->field.tqe_prev; \
else { \
(head)->tqh_last = (elm)->field.tqe_prev; \
QMD_TRACE_HEAD(head); \
} \
*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \
TRASHIT(*oldnext); \
TRASHIT(*oldprev); \
QMD_TRACE_ELEM(&(elm)->field); \
} while (0)
#define TAILQ_SWAP(head1, head2, type, field) do { \
struct type *swap_first = (head1)->tqh_first; \
struct type **swap_last = (head1)->tqh_last; \
(head1)->tqh_first = (head2)->tqh_first; \
(head1)->tqh_last = (head2)->tqh_last; \
(head2)->tqh_first = swap_first; \
(head2)->tqh_last = swap_last; \
if ((swap_first = (head1)->tqh_first) != NULL) \
swap_first->field.tqe_prev = &(head1)->tqh_first; \
else \
(head1)->tqh_last = &(head1)->tqh_first; \
if ((swap_first = (head2)->tqh_first) != NULL) \
swap_first->field.tqe_prev = &(head2)->tqh_first; \
else \
(head2)->tqh_last = &(head2)->tqh_first; \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* !_SYS_QUEUE_H_ */
#warning rom/queue.h is deprecated, please use sys/queue.h instead
#include "sys/queue.h"

222
tools/sdk/include/esp32/rom/rtc.h
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@ -1,220 +1,2 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_RTC_H_
#define _ROM_RTC_H_
#include "ets_sys.h"
#include <stdbool.h>
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup rtc_apis, rtc registers and memory related apis
* @brief rtc apis
*/
/** @addtogroup rtc_apis
* @{
*/
/**************************************************************************************
* Note: *
* Some Rtc memory and registers are used, in ROM or in internal library. *
* Please do not use reserved or used rtc memory or registers. *
* *
*************************************************************************************
* RTC Memory & Store Register usage
*************************************************************************************
* rtc memory addr type size usage
* 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
* 0x3ff61000+SIZE_CP Slow 4096-SIZE_CP
* 0x3ff62800 Slow 4096 Reserved
*
* 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code
*
*************************************************************************************
* RTC store registers usage
* RTC_CNTL_STORE0_REG Reserved
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
* RTC_CNTL_STORE2_REG Boot time, low word
* RTC_CNTL_STORE3_REG Boot time, high word
* RTC_CNTL_STORE4_REG External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code.
* RTC_CNTL_STORE5_REG APB bus frequency
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
*************************************************************************************
*/
#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
typedef enum {
AWAKE = 0, //<CPU ON
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
} SLEEP_MODE;
typedef enum {
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Vbat power on reset*/
SW_RESET = 3, /**<3, Software reset digital core*/
OWDT_RESET = 4, /**<4, Legacy watch dog reset digital core*/
DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
TGWDT_CPU_RESET = 11, /**<11, Time Group reset CPU*/
SW_CPU_RESET = 12, /**<12, Software reset CPU*/
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
EXT_CPU_RESET = 14, /**<14, for APP CPU, reseted by PRO CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/
} RESET_REASON;
typedef enum {
NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0,
EXT_EVENT1_TRIG = BIT1,
GPIO_TRIG = BIT2,
TIMER_EXPIRE = BIT3,
SDIO_TRIG = BIT4,
MAC_TRIG = BIT5,
UART0_TRIG = BIT6,
UART1_TRIG = BIT7,
TOUCH_TRIG = BIT8,
SAR_TRIG = BIT9,
BT_TRIG = BIT10
} WAKEUP_REASON;
typedef enum {
DISEN_WAKEUP = NO_SLEEP,
EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
GPIO_TRIG_EN = GPIO_TRIG,
TIMER_EXPIRE_EN = TIMER_EXPIRE,
SDIO_TRIG_EN = SDIO_TRIG,
MAC_TRIG_EN = MAC_TRIG,
UART0_TRIG_EN = UART0_TRIG,
UART1_TRIG_EN = UART1_TRIG,
TOUCH_TRIG_EN = TOUCH_TRIG,
SAR_TRIG_EN = SAR_TRIG,
BT_TRIG_EN = BT_TRIG
} WAKEUP_ENABLE;
typedef enum {
NO_INT = 0,
WAKEUP_INT = BIT0,
REJECT_INT = BIT1,
SDIO_IDLE_INT = BIT2,
RTC_WDT_INT = BIT3,
RTC_TIME_VALID_INT = BIT4
} RTC_INT_REASON;
typedef enum {
DISEN_INT = 0,
WAKEUP_INT_EN = WAKEUP_INT,
REJECT_INT_EN = REJECT_INT,
SDIO_IDLE_INT_EN = SDIO_IDLE_INT,
RTC_WDT_INT_EN = RTC_WDT_INT,
RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
} RTC_INT_EN;
/**
* @brief Get the reset reason for CPU.
*
* @param int cpu_no : CPU no.
*
* @return RESET_REASON
*/
RESET_REASON rtc_get_reset_reason(int cpu_no);
/**
* @brief Get the wakeup cause for CPU.
*
* @param int cpu_no : CPU no.
*
* @return WAKEUP_REASON
*/
WAKEUP_REASON rtc_get_wakeup_cause(void);
/**
* @brief Get CRC for Fast RTC Memory.
*
* @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
*
* @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
*
* @return uint32_t : CRC32 result
*/
uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
/**
* @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
*
* @param None
*
* @return None
*/
void set_rtc_memory_crc(void);
/**
* @brief Software Reset digital core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param None
*
* @return None
*/
void __attribute__((noreturn)) software_reset(void);
/**
* @brief Software Reset digital core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
*
* @return None
*/
void software_reset_cpu(int cpu_no);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_RTC_H_ */
#warning rom/rtc.h is deprecated, please use esp32/rom/rtc.h instead
#include "esp32/rom/rtc.h"

48
tools/sdk/include/esp32/rom/secure_boot.h
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@ -1,46 +1,2 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SECURE_BOOT_H_
#define _ROM_SECURE_BOOT_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
void ets_secure_boot_start(void);
void ets_secure_boot_finish(void);
void ets_secure_boot_hash(const uint32_t *buf);
void ets_secure_boot_obtain(void);
int ets_secure_boot_check(uint32_t *buf);
void ets_secure_boot_rd_iv(uint32_t *buf);
void ets_secure_boot_rd_abstract(uint32_t *buf);
bool ets_secure_boot_check_start(uint8_t abs_index, uint32_t iv_addr);
int ets_secure_boot_check_finish(uint32_t *abstract);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SECURE_BOOT_H_ */
#warning rom/secure_boot.h is deprecated, please use esp32/rom/secure_boot.h instead
#include "esp32/rom/secure_boot.h"

63
tools/sdk/include/esp32/rom/sha.h
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@ -1,61 +1,2 @@
/*
ROM functions for hardware SHA support.
It is not recommended to use these functions directly. If using
them from esp-idf then use the esp_sha_lock_engine() and
esp_sha_lock_memory_block() functions in hwcrypto/sha.h to ensure
exclusive access.
*/
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SHA_H_
#define _ROM_SHA_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct SHAContext {
bool start;
uint32_t total_input_bits[4];
} SHA_CTX;
enum SHA_TYPE {
SHA1 = 0,
SHA2_256,
SHA2_384,
SHA2_512,
SHA_INVALID = -1,
};
void ets_sha_init(SHA_CTX *ctx);
void ets_sha_enable(void);
void ets_sha_disable(void);
void ets_sha_update(SHA_CTX *ctx, enum SHA_TYPE type, const uint8_t *input, size_t input_bits);
void ets_sha_finish(SHA_CTX *ctx, enum SHA_TYPE type, uint8_t *output);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SHA_H_ */
#warning rom/sha.h is deprecated, please use esp32/rom/sha.h instead
#include "esp32/rom/sha.h"

556
tools/sdk/include/esp32/rom/spi_flash.h
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@ -1,554 +1,2 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/spi_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup spi_flash_apis, spi flash operation related apis
* @brief spi_flash apis
*/
/** @addtogroup spi_flash_apis
* @{
*/
/*************************************************************
* Note
*************************************************************
* 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
* used as an SPI master to access Flash and ext-SRAM by
* Cache module. It will support Decryto read for Flash,
* read/write for ext-SRAM. And SPI1 is also used as an
* SPI master for Flash read/write and ext-SRAM read/write.
* It will support Encrypto write for Flash.
* 2. As an SPI master, SPI support Highest clock to 80M,
* however, Flash with 80M Clock should be configured
* for different Flash chips. If you want to use 80M
* clock We should use the SPI that is certified by
* Espressif. However, the certification is not started
* at the time, so please use 40M clock at the moment.
* 3. SPI Flash can use 2 lines or 4 lines mode. If you
* use 2 lines mode, you can save two pad SPIHD and
* SPIWP for gpio. ESP32 support configured SPI pad for
* Flash, the configuration is stored in efuse and flash.
* However, the configurations of pads should be certified
* by Espressif. If you use this function, please use 40M
* clock at the moment.
* 4. ESP32 support to use Common SPI command to configure
* Flash to QIO mode, if you failed to configure with fix
* command. With Common SPI Command, ESP32 can also provide
* a way to use same Common SPI command groups on different
* Flash chips.
* 5. This functions are not protected by packeting, Please use the
*************************************************************
*/
#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1)
#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1)
#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1)
#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1)
#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1)
#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1)
#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1)
#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1)
#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1)
#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1)
#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1)
#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1)
#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1)
#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1)
#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1)
#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1)
#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1)
#define SPI0_R_QIO_DUMMY_CYCLELEN 3
#define SPI0_R_QIO_ADDR_BITSLEN 31
#define SPI0_R_FAST_DUMMY_CYCLELEN 7
#define SPI0_R_DIO_DUMMY_CYCLELEN 1
#define SPI0_R_DIO_ADDR_BITSLEN 27
#define SPI0_R_FAST_ADDR_BITSLEN 23
#define SPI0_R_SIO_ADDR_BITSLEN 23
#define SPI1_R_QIO_DUMMY_CYCLELEN 3
#define SPI1_R_QIO_ADDR_BITSLEN 31
#define SPI1_R_FAST_DUMMY_CYCLELEN 7
#define SPI1_R_DIO_DUMMY_CYCLELEN 3
#define SPI1_R_DIO_ADDR_BITSLEN 31
#define SPI1_R_FAST_ADDR_BITSLEN 23
#define SPI1_R_SIO_ADDR_BITSLEN 23
#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B
//SPI address register
#define ESP_ROM_SPIFLASH_BYTES_LEN 24
#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f
//SPI status register
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
//Extra dummy for flash read
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
ESP_ROM_SPIFLASH_DIO_MODE,
ESP_ROM_SPIFLASH_DOUT_MODE,
ESP_ROM_SPIFLASH_FASTRD_MODE,
ESP_ROM_SPIFLASH_SLOWRD_MODE
} esp_rom_spiflash_read_mode_t;
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef struct {
uint32_t device_id;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
uint32_t sector_size;
uint32_t page_size;
uint32_t status_mask;
} esp_rom_spiflash_chip_t;
typedef struct {
uint8_t data_length;
uint8_t read_cmd0;
uint8_t read_cmd1;
uint8_t write_cmd;
uint16_t data_mask;
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
*
* @return None
*/
void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
/**
* @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief Write status to Falsh status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t status_value : Value to .
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
/**
* @brief Use a command to Read Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t*status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
/**
* @brief Config SPI Flash read mode when init.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
*
* This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
/**
* @brief Config SPI Flash clock divisor.
* Please do not call this function in SDK.
*
* @param uint8_t freqdiv: clock divisor.
*
* @param uint8_t spi: 0 for SPI0, 1 for SPI1.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
/**
* @brief Unlock SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
/**
* @brief SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Lock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
*
* @param uint32_t deviceId : Device ID read from SPI, the low 32 bit.
*
* @param uint32_t chip_size : The Flash size.
*
* @param uint32_t block_size : The Flash block size.
*
* @param uint32_t sector_size : The Flash sector size.
*
* @param uint32_t page_size : The Flash page size.
*
* @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
/**
* @brief Erase whole flash chip.
* Please do not call this function in SDK.
*
* @param None
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
/**
* @brief Erase a 64KB block of flash
* Uses SPI flash command D8H.
* Please do not call this function in SDK.
*
* @param uint32_t block_num : Which block to erase.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
/**
* @brief Erase a sector of flash.
* Uses SPI flash command 20H.
* Please do not call this function in SDK.
*
* @param uint32_t sector_num : Which sector to erase.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
/**
* @brief Erase some sectors.
* Please do not call this function in SDK.
*
* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
*
* @param uint32_t area_len : Length to erase, should be sector aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
/**
* @brief Write Data to Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
*
* @param const uint32_t *src : The pointer to data which is to write.
*
* @param uint32_t len : Length to write, should be 4 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
/**
* @brief Read Data from Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
*
* @param uint32_t *dest : The buf to read the data.
*
* @param uint32_t len : Length to read, should be 4 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
/**
* @brief SPI1 go into encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void esp_rom_spiflash_write_encrypted_enable(void);
/**
* @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
*
* @param uint32_t *data : The pointer to data which is to write.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data);
/**
* @brief SPI1 go out of encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void esp_rom_spiflash_write_encrypted_disable(void);
/**
* @brief Write data to flash with transparent encryption.
* @note Sectors to be written should already be erased.
*
* @note Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 byte aligned.
*
* @param uint32_t *data : The pointer to data to write. Note, this pointer must
* be 32 bit aligned and the content of the data will be
* modified by the encryption function.
*
* @param uint32_t len : Length to write, should be 32 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
* ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
/** @brief Wait until SPI flash write operation is complete
*
* @note Please do not call this function in SDK.
*
* Reads the Write In Progress bit of the SPI flash status register,
* repeats until this bit is zero (indicating write complete).
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
* ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
/** @brief Enable Quad I/O pin functions
*
* @note Please do not call this function in SDK.
*
* Sets the HD & WP pin functions for Quad I/O modes, based on the
* efuse SPI pin configuration.
*
* @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
*
* @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
* - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
* - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
* - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
* to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
* Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
*/
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
/** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions
*
*/
extern esp_rom_spiflash_chip_t g_rom_flashchip;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */
#warning rom/spi_flash.h is deprecated, please use esp32/rom/spi_flash.h instead
#include "esp32/rom/spi_flash.h"

29
tools/sdk/include/esp32/rom/tbconsole.h
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@ -1,27 +1,2 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_TBCONSOLE_H_
#define _ROM_TBCONSOLE_H_
#ifdef __cplusplus
extern "C" {
#endif
void start_tb_console();
#ifdef __cplusplus
}
#endif
#endif /* _ROM_TBCONSOLE_H_ */
#warning rom/tbconsole.h is deprecated, please use esp32/rom/tbconsole.h instead
#include "esp32/rom/tbconsole.h"

101
tools/sdk/include/esp32/rom/tjpgd.h
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@ -1,99 +1,2 @@
/*----------------------------------------------------------------------------/
/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012
/----------------------------------------------------------------------------*/
#ifndef _TJPGDEC
#define _TJPGDEC
/*---------------------------------------------------------------------------*/
/* System Configurations */
#define JD_SZBUF 512 /* Size of stream input buffer */
#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
#define JD_USE_SCALE 1 /* Use descaling feature for output */
#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
/*---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
/* These types must be 16-bit, 32-bit or larger integer */
typedef int INT;
typedef unsigned int UINT;
/* These types must be 8-bit integer */
typedef char CHAR;
typedef unsigned char UCHAR;
typedef unsigned char BYTE;
/* These types must be 16-bit integer */
typedef short SHORT;
typedef unsigned short USHORT;
typedef unsigned short WORD;
typedef unsigned short WCHAR;
/* These types must be 32-bit integer */
typedef long LONG;
typedef unsigned long ULONG;
typedef unsigned long DWORD;
/* Error code */
typedef enum {
JDR_OK = 0, /* 0: Succeeded */
JDR_INTR, /* 1: Interrupted by output function */
JDR_INP, /* 2: Device error or wrong termination of input stream */
JDR_MEM1, /* 3: Insufficient memory pool for the image */
JDR_MEM2, /* 4: Insufficient stream input buffer */
JDR_PAR, /* 5: Parameter error */
JDR_FMT1, /* 6: Data format error (may be damaged data) */
JDR_FMT2, /* 7: Right format but not supported */
JDR_FMT3 /* 8: Not supported JPEG standard */
} JRESULT;
/* Rectangular structure */
typedef struct {
WORD left, right, top, bottom;
} JRECT;
/* Decompressor object structure */
typedef struct JDEC JDEC;
struct JDEC {
UINT dctr; /* Number of bytes available in the input buffer */
BYTE* dptr; /* Current data read ptr */
BYTE* inbuf; /* Bit stream input buffer */
BYTE dmsk; /* Current bit in the current read byte */
BYTE scale; /* Output scaling ratio */
BYTE msx, msy; /* MCU size in unit of block (width, height) */
BYTE qtid[3]; /* Quantization table ID of each component */
SHORT dcv[3]; /* Previous DC element of each component */
WORD nrst; /* Restart inverval */
UINT width, height; /* Size of the input image (pixel) */
BYTE* huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */
WORD* huffcode[2][2]; /* Huffman code word tables [id][dcac] */
BYTE* huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */
LONG* qttbl[4]; /* Dequaitizer tables [id] */
void* workbuf; /* Working buffer for IDCT and RGB output */
BYTE* mcubuf; /* Working buffer for the MCU */
void* pool; /* Pointer to available memory pool */
UINT sz_pool; /* Size of momory pool (bytes available) */
UINT (*infunc)(JDEC*, BYTE*, UINT);/* Pointer to jpeg stream input function */
void* device; /* Pointer to I/O device identifiler for the session */
};
/* TJpgDec API functions */
JRESULT jd_prepare (JDEC*, UINT(*)(JDEC*,BYTE*,UINT), void*, UINT, void*);
JRESULT jd_decomp (JDEC*, UINT(*)(JDEC*,void*,JRECT*), BYTE);
#ifdef __cplusplus
}
#endif
#endif /* _TJPGDEC */
#warning rom/tjpgd.h is deprecated, please use esp32/rom/tjpgd.h instead
#include "esp32/rom/tjpgd.h"

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tools/sdk/include/esp32/rom/uart.h
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@ -1,420 +1,2 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_UART_H_
#define _ROM_UART_H_
#include "esp_types.h"
#include "esp_attr.h"
#include "ets_sys.h"
#include "soc/soc.h"
#include "soc/uart_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
#define RX_BUFF_SIZE 0x100
#define TX_BUFF_SIZE 100
//uart int enable register ctrl bits
#define UART_RCV_INTEN BIT0
#define UART_TRX_INTEN BIT1
#define UART_LINE_STATUS_INTEN BIT2
//uart int identification ctrl bits
#define UART_INT_FLAG_MASK 0x0E
//uart fifo ctrl bits
#define UART_CLR_RCV_FIFO BIT1
#define UART_CLR_TRX_FIFO BIT2
#define UART_RCVFIFO_TRG_LVL_BITS BIT6
//uart line control bits
#define UART_DIV_LATCH_ACCESS_BIT BIT7
//uart line status bits
#define UART_RCV_DATA_RDY_FLAG BIT0
#define UART_RCV_OVER_FLOW_FLAG BIT1
#define UART_RCV_PARITY_ERR_FLAG BIT2
#define UART_RCV_FRAME_ERR_FLAG BIT3
#define UART_BRK_INT_FLAG BIT4
#define UART_TRX_FIFO_EMPTY_FLAG BIT5
#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg
#define UART_RCV_ERR_FLAG BIT7
//send and receive message frame head
#define FRAME_FLAG 0x7E
typedef enum {
UART_LINE_STATUS_INT_FLAG = 0x06,
UART_RCV_FIFO_INT_FLAG = 0x04,
UART_RCV_TMOUT_INT_FLAG = 0x0C,
UART_TXBUFF_EMPTY_INT_FLAG = 0x02
} UartIntType; //consider bit0 for int_flag
typedef enum {
RCV_ONE_BYTE = 0x0,
RCV_FOUR_BYTE = 0x1,
RCV_EIGHT_BYTE = 0x2,
RCV_FOURTEEN_BYTE = 0x3
} UartRcvFifoTrgLvl;
typedef enum {
FIVE_BITS = 0x0,
SIX_BITS = 0x1,
SEVEN_BITS = 0x2,
EIGHT_BITS = 0x3
} UartBitsNum4Char;
typedef enum {
ONE_STOP_BIT = 1,
ONE_HALF_STOP_BIT = 2,
TWO_STOP_BIT = 3
} UartStopBitsNum;
typedef enum {
NONE_BITS = 0,
ODD_BITS = 2,
EVEN_BITS = 3
} UartParityMode;
typedef enum {
STICK_PARITY_DIS = 0,
STICK_PARITY_EN = 2
} UartExistParity;
typedef enum {
BIT_RATE_9600 = 9600,
BIT_RATE_19200 = 19200,
BIT_RATE_38400 = 38400,
BIT_RATE_57600 = 57600,
BIT_RATE_115200 = 115200,
BIT_RATE_230400 = 230400,
BIT_RATE_460800 = 460800,
BIT_RATE_921600 = 921600
} UartBautRate;
typedef enum {
NONE_CTRL,
HARDWARE_CTRL,
XON_XOFF_CTRL
} UartFlowCtrl;
typedef enum {
EMPTY,
UNDER_WRITE,
WRITE_OVER
} RcvMsgBuffState;
typedef struct {
uint8_t *pRcvMsgBuff;
uint8_t *pWritePos;
uint8_t *pReadPos;
uint8_t TrigLvl;
RcvMsgBuffState BuffState;
} RcvMsgBuff;
typedef struct {
uint32_t TrxBuffSize;
uint8_t *pTrxBuff;
} TrxMsgBuff;
typedef enum {
BAUD_RATE_DET,
WAIT_SYNC_FRM,
SRCH_MSG_HEAD,
RCV_MSG_BODY,
RCV_ESC_CHAR,
} RcvMsgState;
typedef struct {
UartBautRate baut_rate;
UartBitsNum4Char data_bits;
UartExistParity exist_parity;
UartParityMode parity; // chip size in byte
UartStopBitsNum stop_bits;
UartFlowCtrl flow_ctrl;
uint8_t buff_uart_no; //indicate which uart use tx/rx buffer
uint8_t tx_uart_no;
RcvMsgBuff rcv_buff;
// TrxMsgBuff trx_buff;
RcvMsgState rcv_state;
int received;
} UartDevice;
/**
* @brief Init uart device struct value and reset uart0/uart1 rx.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void uartAttach(void);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, else for UART1.
*
* @param uint32_t clock : clock used by uart module, to adjust baudrate.
*
* @return None
*/
void Uart_Init(uint8_t uart_no, uint32_t clock);
/**
* @brief Modify uart baudrate.
* This function will reset RX/TX fifo for uart.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @param uint32_t DivLatchValue : (clock << 4)/baudrate.
*
* @return None
*/
void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected;
* 1, two UART modules, hard to detect, detect and return.
*
* @return None
*/
int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync);
/**
* @brief Switch printf channel of uart_tx_one_char.
* Please do not call this function when printf.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None
*/
void uart_tx_switch(uint8_t uart_no);
/**
* @brief Switch message exchange channel for UART download booting.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None
*/
void uart_buff_switch(uint8_t uart_no);
/**
* @brief Output a char to printf channel, wait until fifo not full.
*
* @param None
*
* @return OK.
*/
STATUS uart_tx_one_char(uint8_t TxChar);
/**
* @brief Output a char to message exchange channel, wait until fifo not full.
* Please do not call this function in SDK.
*
* @param None
*
* @return OK.
*/
STATUS uart_tx_one_char2(uint8_t TxChar);
/**
* @brief Wait until uart tx full empty.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None.
*/
void uart_tx_flush(uint8_t uart_no);
/**
* @brief Wait until uart tx full empty and the last char send ok.
*
* @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2
*
* The function defined in ROM code has a bug, so we define the correct version
* here for compatibility.
*/
static inline void IRAM_ATTR uart_tx_wait_idle(uint8_t uart_no) {
uint32_t status;
do {
status = READ_PERI_REG(UART_STATUS_REG(uart_no));
/* either tx count or state is non-zero */
} while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0);
}
/**
* @brief Get an input char from message channel.
* Please do not call this function in SDK.
*
* @param uint8_t *pRxChar : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS uart_rx_one_char(uint8_t *pRxChar);
/**
* @brief Get an input char from message channel, wait until successful.
* Please do not call this function in SDK.
*
* @param None
*
* @return char : input char value.
*/
char uart_rx_one_char_block(void);
/**
* @brief Get an input string line from message channel.
* Please do not call this function in SDK.
*
* @param uint8_t *pString : the pointer to store the string.
*
* @param uint8_t MaxStrlen : the max string length, include '\0'.
*
* @return OK.
*/
STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
/**
* @brief Process uart received information in the interrupt handler.
* Please do not call this function in SDK.
*
* @param void *para : the message receive buffer.
*
* @return None
*/
void uart_rx_intr_handler(void *para);
/**
* @brief Get an char from receive buffer.
* Please do not call this function in SDK.
*
* @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
*
* @param uint8_t *pRxByte : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
/**
* @brief Get all chars from receive buffer.
* Please do not call this function in SDK.
*
* @param uint8_t *pCmdLn : the pointer to store the string.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS UartGetCmdLn(uint8_t *pCmdLn);
/**
* @brief Get uart configuration struct.
* Please do not call this function in SDK.
*
* @param None
*
* @return UartDevice * : uart configuration struct pointer.
*/
UartDevice *GetUartDevice(void);
/**
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to output string.
*
* @param int len : the string length.
*
* @return None.
*/
void send_packet(uint8_t *p, int len);
/**
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to input string.
*
* @param int len : If string length > len, the string will be truncated.
*
* @param uint8_t is_sync : 0, only one UART module;
* 1, two UART modules.
*
* @return int : the length of the string.
*/
int recv_packet(uint8_t *p, int len, uint8_t is_sync);
/**
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *pData : the pointer to input string.
*
* @param uint16_t DataLen : the string length.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
/**
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *pData : the pointer to input string.
*
* @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated.
*
* @param uint8_t is_sync : 0, only one UART module;
* 1, two UART modules.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync);
extern UartDevice UartDev;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_UART_H_ */
#warning rom/uart.h is deprecated, please use esp32/rom/uart.h instead
#include "esp32/rom/uart.h"

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tools/sdk/include/esp32/xtensa/cacheasm.h
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/*
* xtensa/cacheasm.h -- assembler-specific cache related definitions
* that depend on CORE configuration
*
* This file is logically part of xtensa/coreasm.h ,
* but is kept separate for modularity / compilation-performance.
*/
/*
* Copyright (c) 2001-2014 Cadence Design Systems, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_CACHEASM_H
#define XTENSA_CACHEASM_H
#include <xtensa/coreasm.h>
#include <xtensa/corebits.h>
#include <xtensa/xtensa-xer.h>
#include <xtensa/xtensa-versions.h>
/*
* This header file defines assembler macros of the form:
* <x>cache_<func>
* where <x> is 'i' or 'd' for instruction and data caches,
* and <func> indicates the function of the macro.
*
* The following functions <func> are defined,
* and apply only to the specified cache (I or D):
*
* reset
* Resets the cache.
*
* sync
* Makes sure any previous cache instructions have been completed;
* ie. makes sure any previous cache control operations
* have had full effect and been synchronized to memory.
* Eg. any invalidate completed [so as not to generate a hit],
* any writebacks or other pipelined writes written to memory, etc.
*
* invalidate_line (single cache line)
* invalidate_region (specified memory range)
* invalidate_all (entire cache)
* Invalidates all cache entries that cache
* data from the specified memory range.
* NOTE: locked entries are not invalidated.
*
* writeback_line (single cache line)
* writeback_region (specified memory range)
* writeback_all (entire cache)
* Writes back to memory all dirty cache entries
* that cache data from the specified memory range,
* and marks these entries as clean.
* NOTE: on some future implementations, this might
* also invalidate.
* NOTE: locked entries are written back, but never invalidated.
* NOTE: instruction caches never implement writeback.
*
* writeback_inv_line (single cache line)
* writeback_inv_region (specified memory range)
* writeback_inv_all (entire cache)
* Writes back to memory all dirty cache entries
* that cache data from the specified memory range,
* and invalidates these entries (including all clean
* cache entries that cache data from that range).
* NOTE: locked entries are written back but not invalidated.
* NOTE: instruction caches never implement writeback.
*
* lock_line (single cache line)
* lock_region (specified memory range)
* Prefetch and lock the specified memory range into cache.
* NOTE: if any part of the specified memory range cannot
* be locked, a Load/Store Error (for dcache) or Instruction
* Fetch Error (for icache) exception occurs. These macros don't
* do anything special (yet anyway) to handle this situation.
*
* unlock_line (single cache line)
* unlock_region (specified memory range)
* unlock_all (entire cache)
* Unlock cache entries that cache the specified memory range.
* Entries not already locked are unaffected.
*
* coherence_on
* coherence_off
* Turn off and on cache coherence
*
*/
/*************************** GENERIC -- ALL CACHES ***************************/
/*
* The following macros assume the following cache size/parameter limits
* in the current Xtensa core implementation:
* cache size: 1024 bytes minimum
* line size: 16 - 64 bytes
* way count: 1 - 4
*
* Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
* Hence the assumption that each loop can execute four cache instructions.
*
* Correspondingly, the offset range of instructions is assumed able to cover
* four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
* both hit and indexed cache instructions. Ie. these offsets are all
* valid: 0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
* This is true of all original cache instructions
* (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
* of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
* This is also true of subsequent cache instructions
* (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
* of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
*
* (Maximum cache size, currently 32k, doesn't affect the following macros.
* Cache ways > MMU min page size cause aliasing but that's another matter.)
*/
/*
* Macro to apply an 'indexed' cache instruction to the entire cache.
*
* Parameters:
* cainst instruction/ that takes an address register parameter
* and an offset parameter (in range 0 .. 3*linesize).
* size size of cache in bytes
* linesize size of cache line in bytes (always power-of-2)
* assoc_or1 number of associativities (ways/sets) in cache
* if all sets affected by cainst,
* or 1 if only one set (or not all sets) of the cache
* is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
* aa, ab unique address registers (temporaries).
* awb set to other than a0 if wb type of instruction
* loopokay 1 allows use of zero-overhead loops, 0 does not
* immrange range (max value) of cainst's immediate offset parameter, in bytes
* (NOTE: macro assumes immrange allows power-of-2 number of lines)
*/
.macro cache_index_all cainst, size, linesize, assoc_or1, aa, ab, loopokay, maxofs, awb=a0
// Number of indices in cache (lines per way):
.set .Lindices, (\size / (\linesize * \assoc_or1))
// Number of indices processed per loop iteration (max 4):
.set .Lperloop, .Lindices
.ifgt .Lperloop - 4
.set .Lperloop, 4
.endif
// Also limit instructions per loop if cache line size exceeds immediate range:
.set .Lmaxperloop, (\maxofs / \linesize) + 1
.ifgt .Lperloop - .Lmaxperloop
.set .Lperloop, .Lmaxperloop
.endif
// Avoid addi of 128 which takes two instructions (addmi,addi):
.ifeq .Lperloop*\linesize - 128
.ifgt .Lperloop - 1
.set .Lperloop, .Lperloop / 2
.endif
.endif
// \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
// XCHAL_ERRATUM_497 - don't execute using loop, to reduce the amount of added code
.ifne (\loopokay & XCHAL_HAVE_LOOPS && !XCHAL_ERRATUM_497)
movi \aa, .Lindices / .Lperloop // number of loop iterations
// Possible improvement: need only loop if \aa > 1 ;
// however \aa == 1 is highly unlikely.
movi \ab, 0 // to iterate over cache
loop \aa, .Lend_cachex\@
.set .Li, 0 ; .rept .Lperloop
\cainst \ab, .Li*\linesize
.set .Li, .Li+1 ; .endr
addi \ab, \ab, .Lperloop*\linesize // move to next line
.Lend_cachex\@:
.else
movi \aa, (\size / \assoc_or1)
// Possible improvement: need only loop if \aa > 1 ;
// however \aa == 1 is highly unlikely.
movi \ab, 0 // to iterate over cache
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0
movi \awb, 0
.endif
.Lstart_cachex\@:
.set .Li, 0 ; .rept .Lperloop
\cainst \ab, .Li*\linesize
.set .Li, .Li+1 ; .endr
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions
addi \awb, \awb, .Lperloop
blti \awb, 8, .Lstart_memw\@
memw
movi \awb, 0
.Lstart_memw\@:
.endif
addi \ab, \ab, .Lperloop*\linesize // move to next line
bltu \ab, \aa, .Lstart_cachex\@
.endif
.endm
/*
* Macro to apply a 'hit' cache instruction to a memory region,
* ie. to any cache entries that cache a specified portion (region) of memory.
* Takes care of the unaligned cases, ie. may apply to one
* more cache line than $asize / lineSize if $aaddr is not aligned.
*
*
* Parameters are:
* cainst instruction/macro that takes an address register parameter
* and an offset parameter (currently always zero)
* and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
* linesize_log2 log2(size of cache line in bytes)
* addr register containing start address of region (clobbered)
* asize register containing size of the region in bytes (clobbered)
* askew unique register used as temporary
* awb unique register used as temporary for erratum 497.
*
* Note: A possible optimization to this macro is to apply the operation
* to the entire cache if the region exceeds the size of the cache
* by some empirically determined amount or factor. Some experimentation
* is required to determine the appropriate factors, which also need
* to be tunable if required.
*/
.macro cache_hit_region cainst, linesize_log2, addr, asize, askew, awb=a0
// Make \asize the number of iterations:
extui \askew, \addr, 0, \linesize_log2 // get unalignment amount of \addr
add \asize, \asize, \askew // ... and add it to \asize
addi \asize, \asize, (1 << \linesize_log2) - 1 // round up!
srli \asize, \asize, \linesize_log2
// Iterate over region:
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0
movi \awb, 0
.endif
floopnez \asize, cacheh\@
\cainst \addr, 0
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions
addi \awb, \awb, 1
blti \awb, 8, .Lstart_memw\@
memw
movi \awb, 0
.Lstart_memw\@:
.endif
addi \addr, \addr, (1 << \linesize_log2) // move to next line
floopend \asize, cacheh\@
.endm
/*************************** INSTRUCTION CACHE ***************************/
/*
* Reset/initialize the instruction cache by simply invalidating it:
* (need to unlock first also, if cache locking implemented):
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro icache_reset aa, ab, loopokay=0
icache_unlock_all \aa, \ab, \loopokay
icache_invalidate_all \aa, \ab, \loopokay
.endm
/*
* Synchronize after an instruction cache operation,
* to be sure everything is in sync with memory as to be
* expected following any previous instruction cache control operations.
*
* Even if a config doesn't have caches, an isync is still needed
* when instructions in any memory are modified, whether by a loader
* or self-modifying code. Therefore, this macro always produces
* an isync, whether or not an icache is present.
*
* Parameters are:
* ar an address register (temporary) (currently unused, but may be used in future)
*/
.macro icache_sync ar
isync
.endm
/*
* Invalidate a single line of the instruction cache.
* Parameters are:
* ar address register that contains (virtual) address to invalidate
* (may get clobbered in a future implementation, but not currently)
* offset (optional) offset to add to \ar to compute effective address to invalidate
* (note: some number of lsbits are ignored)
*/
.macro icache_invalidate_line ar, offset
#if XCHAL_ICACHE_SIZE > 0
ihi \ar, \offset // invalidate icache line
icache_sync \ar
#endif
.endm
/*
* Invalidate instruction cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro icache_invalidate_region astart, asize, ac
#if XCHAL_ICACHE_SIZE > 0
// Instruction cache region invalidation:
cache_hit_region ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
icache_sync \ac
// End of instruction cache region invalidation
#endif
.endm
/*
* Invalidate entire instruction cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro icache_invalidate_all aa, ab, loopokay=1
#if XCHAL_ICACHE_SIZE > 0
// Instruction cache invalidation:
cache_index_all iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loopokay, 1020
icache_sync \aa
// End of instruction cache invalidation
#endif
.endm
/*
* Lock (prefetch & lock) a single line of the instruction cache.
*
* Parameters are:
* ar address register that contains (virtual) address to lock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to lock
* (note: some number of lsbits are ignored)
*/
.macro icache_lock_line ar, offset
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
ipfl \ar, \offset /* prefetch and lock icache line */
icache_sync \ar
#endif
.endm
/*
* Lock (prefetch & lock) a specified portion of memory into the instruction cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro icache_lock_region astart, asize, ac
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
// Instruction cache region lock:
cache_hit_region ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
icache_sync \ac
// End of instruction cache region lock
#endif
.endm
/*
* Unlock a single line of the instruction cache.
*
* Parameters are:
* ar address register that contains (virtual) address to unlock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to unlock
* (note: some number of lsbits are ignored)
*/
.macro icache_unlock_line ar, offset
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
ihu \ar, \offset /* unlock icache line */
icache_sync \ar
#endif
.endm
/*
* Unlock a specified portion of memory from the instruction cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro icache_unlock_region astart, asize, ac
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
// Instruction cache region unlock:
cache_hit_region ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
icache_sync \ac
// End of instruction cache region unlock
#endif
.endm
/*
* Unlock entire instruction cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro icache_unlock_all aa, ab, loopokay=1
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
// Instruction cache unlock:
cache_index_all iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
icache_sync \aa
// End of instruction cache unlock
#endif
.endm
/*************************** DATA CACHE ***************************/
/*
* Reset/initialize the data cache by simply invalidating it
* (need to unlock first also, if cache locking implemented):
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_reset aa, ab, loopokay=0
dcache_unlock_all \aa, \ab, \loopokay
dcache_invalidate_all \aa, \ab, \loopokay
.endm
/*
* Synchronize after a data cache operation,
* to be sure everything is in sync with memory as to be
* expected following any previous data cache control operations.
*
* Parameters are:
* ar an address register (temporary) (currently unused, but may be used in future)
*/
.macro dcache_sync ar, wbtype=0
#if XCHAL_DCACHE_SIZE > 0
// No synchronization is needed.
// (memw may be desired e.g. after writeback operation to help ensure subsequent
// external accesses are seen to follow that writeback, however that's outside
// the scope of this macro)
//dsync
.ifne (\wbtype & XCHAL_ERRATUM_497)
memw
.endif
#endif
.endm
/*
* Turn on cache coherence.
*
* WARNING: for RE-201x.x and later hardware, any interrupt that tries
* to change MEMCTL will see its changes dropped if the interrupt comes
* in the middle of this routine. If this might be an issue, call this
* routine with interrupts disabled.
*
* Parameters are:
* ar,at two scratch address registers (both clobbered)
*/
.macro cache_coherence_on ar at
#if XCHAL_DCACHE_IS_COHERENT
# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
/* Have MEMCTL. Enable snoop responses. */
rsr.memctl \ar
movi \at, MEMCTL_SNOOP_EN
or \ar, \ar, \at
wsr.memctl \ar
# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
/* Opt into coherence for MX (for backward compatibility / testing). */
movi \ar, 1
movi \at, XER_CCON
wer \ar, \at
extw
# endif
#endif
.endm
/*
* Turn off cache coherence.
*
* NOTE: this is generally preceded by emptying the cache;
* see xthal_cache_coherence_optout() in hal/coherence.c for details.
*
* WARNING: for RE-201x.x and later hardware, any interrupt that tries
* to change MEMCTL will see its changes dropped if the interrupt comes
* in the middle of this routine. If this might be an issue, call this
* routine with interrupts disabled.
*
* Parameters are:
* ar,at two scratch address registers (both clobbered)
*/
.macro cache_coherence_off ar at
#if XCHAL_DCACHE_IS_COHERENT
# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
/* Have MEMCTL. Disable snoop responses. */
rsr.memctl \ar
movi \at, ~MEMCTL_SNOOP_EN
and \ar, \ar, \at
wsr.memctl \ar
# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
/* Opt out of coherence, for MX (for backward compatibility / testing). */
extw
movi \at, 0
movi \ar, XER_CCON
wer \at, \ar
extw
# endif
#endif
.endm
/*
* Synchronize after a data store operation,
* to be sure the stored data is completely off the processor
* (and assuming there is no buffering outside the processor,
* that the data is in memory). This may be required to
* ensure that the processor's write buffers are emptied.
* A MEMW followed by a read guarantees this, by definition.
* We also try to make sure the read itself completes.
*
* Parameters are:
* ar an address register (temporary)
*/
.macro write_sync ar
memw // ensure previous memory accesses are complete prior to subsequent memory accesses
l32i \ar, sp, 0 // completing this read ensures any previous write has completed, because of MEMW
//slot
add \ar, \ar, \ar // use the result of the read to help ensure the read completes (in future architectures)
.endm
/*
* Invalidate a single line of the data cache.
* Parameters are:
* ar address register that contains (virtual) address to invalidate
* (may get clobbered in a future implementation, but not currently)
* offset (optional) offset to add to \ar to compute effective address to invalidate
* (note: some number of lsbits are ignored)
*/
.macro dcache_invalidate_line ar, offset
#if XCHAL_DCACHE_SIZE > 0
dhi \ar, \offset
dcache_sync \ar
#endif
.endm
/*
* Invalidate data cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_invalidate_region astart, asize, ac
#if XCHAL_DCACHE_SIZE > 0
// Data cache region invalidation:
cache_hit_region dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
dcache_sync \ac
// End of data cache region invalidation
#endif
.endm
/*
* Invalidate entire data cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_invalidate_all aa, ab, loopokay=1
#if XCHAL_DCACHE_SIZE > 0
// Data cache invalidation:
cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loopokay, 1020
dcache_sync \aa
// End of data cache invalidation
#endif
.endm
/*
* Writeback a single line of the data cache.
* Parameters are:
* ar address register that contains (virtual) address to writeback
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to writeback
* (note: some number of lsbits are ignored)
*/
.macro dcache_writeback_line ar, offset
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
dhwb \ar, \offset
dcache_sync \ar, wbtype=1
#endif
.endm
/*
* Writeback dirty data cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_writeback_region astart, asize, ac, awb
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
// Data cache region writeback:
cache_hit_region dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
dcache_sync \ac, wbtype=1
// End of data cache region writeback
#endif
.endm
/*
* Writeback entire data cache.
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_writeback_all aa, ab, awb, loopokay=1
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
// Data cache writeback:
cache_index_all diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb,
dcache_sync \aa, wbtype=1
// End of data cache writeback
#endif
.endm
/*
* Writeback and invalidate a single line of the data cache.
* Parameters are:
* ar address register that contains (virtual) address to writeback and invalidate
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to writeback and invalidate
* (note: some number of lsbits are ignored)
*/
.macro dcache_writeback_inv_line ar, offset
#if XCHAL_DCACHE_SIZE > 0
dhwbi \ar, \offset /* writeback and invalidate dcache line */
dcache_sync \ar, wbtype=1
#endif
.endm
/*
* Writeback and invalidate data cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_writeback_inv_region astart, asize, ac, awb
#if XCHAL_DCACHE_SIZE > 0
// Data cache region writeback and invalidate:
cache_hit_region dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
dcache_sync \ac, wbtype=1
// End of data cache region writeback and invalidate
#endif
.endm
/*
* Writeback and invalidate entire data cache.
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_writeback_inv_all aa, ab, awb, loopokay=1
#if XCHAL_DCACHE_SIZE > 0
// Data cache writeback and invalidate:
#if XCHAL_DCACHE_IS_WRITEBACK
cache_index_all diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb
dcache_sync \aa, wbtype=1
#else /*writeback*/
// Data cache does not support writeback, so just invalidate: */
dcache_invalidate_all \aa, \ab, \loopokay
#endif /*writeback*/
// End of data cache writeback and invalidate
#endif
.endm
/*
* Lock (prefetch & lock) a single line of the data cache.
*
* Parameters are:
* ar address register that contains (virtual) address to lock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to lock
* (note: some number of lsbits are ignored)
*/
.macro dcache_lock_line ar, offset
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
dpfl \ar, \offset /* prefetch and lock dcache line */
dcache_sync \ar
#endif
.endm
/*
* Lock (prefetch & lock) a specified portion of memory into the data cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_lock_region astart, asize, ac
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
// Data cache region lock:
cache_hit_region dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
dcache_sync \ac
// End of data cache region lock
#endif
.endm
/*
* Unlock a single line of the data cache.
*
* Parameters are:
* ar address register that contains (virtual) address to unlock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to unlock
* (note: some number of lsbits are ignored)
*/
.macro dcache_unlock_line ar, offset
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
dhu \ar, \offset /* unlock dcache line */
dcache_sync \ar
#endif
.endm
/*
* Unlock a specified portion of memory from the data cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_unlock_region astart, asize, ac
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
// Data cache region unlock:
cache_hit_region dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
dcache_sync \ac
// End of data cache region unlock
#endif
.endm
/*
* Unlock entire data cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_unlock_all aa, ab, loopokay=1
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
// Data cache unlock:
cache_index_all diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
dcache_sync \aa
// End of data cache unlock
#endif
.endm
/*
* Get the number of enabled icache ways. Note that this may
* be different from the value read from the MEMCTL register.
*
* Parameters:
* aa address register where value is returned
*/
.macro icache_get_ways aa
#if XCHAL_ICACHE_SIZE > 0
#if XCHAL_HAVE_ICACHE_DYN_WAYS
// Read from MEMCTL and shift/mask
rsr \aa, MEMCTL
extui \aa, \aa, MEMCTL_ICWU_SHIFT, MEMCTL_ICWU_BITS
blti \aa, XCHAL_ICACHE_WAYS, .Licgw
movi \aa, XCHAL_ICACHE_WAYS
.Licgw:
#else
// All ways are always enabled
movi \aa, XCHAL_ICACHE_WAYS
#endif
#else
// No icache
movi \aa, 0
#endif
.endm
/*
* Set the number of enabled icache ways.
*
* Parameters:
* aa address register specifying number of ways (trashed)
* ab,ac address register for scratch use (trashed)
*/
.macro icache_set_ways aa, ab, ac
#if XCHAL_ICACHE_SIZE > 0
#if XCHAL_HAVE_ICACHE_DYN_WAYS
movi \ac, MEMCTL_ICWU_CLR_MASK // set up to clear bits 18-22
rsr \ab, MEMCTL
and \ab, \ab, \ac
movi \ac, MEMCTL_INV_EN // set bit 23
slli \aa, \aa, MEMCTL_ICWU_SHIFT // move to right spot
or \ab, \ab, \aa
or \ab, \ab, \ac
wsr \ab, MEMCTL
isync
#else
// All ways are always enabled
#endif
#else
// No icache
#endif
.endm
/*
* Get the number of enabled dcache ways. Note that this may
* be different from the value read from the MEMCTL register.
*
* Parameters:
* aa address register where value is returned
*/
.macro dcache_get_ways aa
#if XCHAL_DCACHE_SIZE > 0
#if XCHAL_HAVE_DCACHE_DYN_WAYS
// Read from MEMCTL and shift/mask
rsr \aa, MEMCTL
extui \aa, \aa, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS
blti \aa, XCHAL_DCACHE_WAYS, .Ldcgw
movi \aa, XCHAL_DCACHE_WAYS
.Ldcgw:
#else
// All ways are always enabled
movi \aa, XCHAL_DCACHE_WAYS
#endif
#else
// No dcache
movi \aa, 0
#endif
.endm
/*
* Set the number of enabled dcache ways.
*
* Parameters:
* aa address register specifying number of ways (trashed)
* ab,ac address register for scratch use (trashed)
*/
.macro dcache_set_ways aa, ab, ac
#if (XCHAL_DCACHE_SIZE > 0) && XCHAL_HAVE_DCACHE_DYN_WAYS
movi \ac, MEMCTL_DCWA_CLR_MASK // set up to clear bits 13-17
rsr \ab, MEMCTL
and \ab, \ab, \ac // clear ways allocatable
slli \ac, \aa, MEMCTL_DCWA_SHIFT
or \ab, \ab, \ac // set ways allocatable
wsr \ab, MEMCTL
#if XCHAL_DCACHE_IS_WRITEBACK
// Check if the way count is increasing or decreasing
extui \ac, \ab, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS // bits 8-12 - ways in use
bge \aa, \ac, .Ldsw3 // equal or increasing
slli \ab, \aa, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // start way number
slli \ac, \ac, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // end way number
.Ldsw1:
diwbui.p \ab // auto-increments ab
bge \ab, \ac, .Ldsw2
beqz \ab, .Ldsw2
j .Ldsw1
.Ldsw2:
rsr \ab, MEMCTL
#endif
.Ldsw3:
// No dirty data to write back, just set the new number of ways
movi \ac, MEMCTL_DCWU_CLR_MASK // set up to clear bits 8-12
and \ab, \ab, \ac // clear ways in use
movi \ac, MEMCTL_INV_EN
or \ab, \ab, \ac // set bit 23
slli \aa, \aa, MEMCTL_DCWU_SHIFT
or \ab, \ab, \aa // set ways in use
wsr \ab, MEMCTL
#else
// No dcache or no way disable support
#endif
.endm
#endif /*XTENSA_CACHEASM_H*/

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tools/sdk/include/esp32/xtensa/cacheattrasm.h
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@ -1,436 +0,0 @@
/*
* xtensa/cacheattrasm.h -- assembler-specific CACHEATTR register related definitions
* that depend on CORE configuration
*
* This file is logically part of xtensa/coreasm.h (or perhaps xtensa/cacheasm.h),
* but is kept separate for modularity / compilation-performance.
*/
/*
* Copyright (c) 2001-2009 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_CACHEATTRASM_H
#define XTENSA_CACHEATTRASM_H
#include <xtensa/coreasm.h>
/* Determine whether cache attributes are controlled using eight 512MB entries: */
#define XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY))
/*
* This header file defines assembler macros of the form:
* <x>cacheattr_<func>
* where:
* <x> is 'i', 'd' or absent for instruction, data
* or both caches; and
* <func> indicates the function of the macro.
*
* The following functions are defined:
*
* icacheattr_get
* Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
*
* dcacheattr_get
* Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
* (Note: for configs with a real CACHEATTR register, the
* above two macros are identical.)
*
* cacheattr_set
* Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
* Works even when changing one's own code's attributes.
*
* icacheattr_is_enabled label
* Branches to \label if I-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* dcacheattr_is_enabled label
* Branches to \label if D-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* cacheattr_is_enabled label
* Branches to \label if either I-cache or D-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* The following macros are only defined under certain conditions:
*
* icacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
* Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
*
* dcacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
* Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
*/
/*************************** GENERIC -- ALL CACHES ***************************/
/*
* _cacheattr_get
*
* (Internal macro.)
* Returns value of CACHEATTR register (or closest equivalent) in a2.
*
* Entry:
* (none)
* Exit:
* a2 value read from CACHEATTR
* a3-a5 clobbered (temporaries)
*/
.macro _cacheattr_get tlb
#if XCHAL_HAVE_CACHEATTR
rsr a2, CACHEATTR
#elif XCHAL_CA_8X512
// We have a config that "mimics" CACHEATTR using a simplified
// "MMU" composed of a single statically-mapped way.
// DTLB and ITLB are independent, so there's no single
// cache attribute that can describe both. So for now
// just return the DTLB state.
movi a5, 0xE0000000
movi a2, 0
movi a3, XCHAL_SPANNING_WAY
1: add a3, a3, a5 // next segment
r&tlb&1 a4, a3 // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
dsync // interlock???
slli a2, a2, 4
extui a4, a4, 0, 4 // extract CA
or a2, a2, a4
bgeui a3, 16, 1b
#else
// This macro isn't applicable to arbitrary MMU configurations.
// Just return zero.
movi a2, 0
#endif
.endm
.macro icacheattr_get
_cacheattr_get itlb
.endm
.macro dcacheattr_get
_cacheattr_get dtlb
.endm
/* Default (powerup/reset) value of CACHEATTR,
all BYPASS mode (ie. disabled/bypassed caches): */
#if XCHAL_HAVE_PTP_MMU
# define XCHAL_CACHEATTR_ALL_BYPASS 0x33333333
#else
# define XCHAL_CACHEATTR_ALL_BYPASS 0x22222222
#endif
#if XCHAL_CA_8X512
#if XCHAL_HAVE_PTP_MMU
# define XCHAL_FCA_ENAMASK 0x0AA0 /* bitmap of fetch attributes that require enabled icache */
# define XCHAL_LCA_ENAMASK 0x0FF0 /* bitmap of load attributes that require enabled dcache */
# define XCHAL_SCA_ENAMASK 0x0CC0 /* bitmap of store attributes that require enabled dcache */
#else
# define XCHAL_FCA_ENAMASK 0x003A /* bitmap of fetch attributes that require enabled icache */
# define XCHAL_LCA_ENAMASK 0x0033 /* bitmap of load attributes that require enabled dcache */
# define XCHAL_SCA_ENAMASK 0x0033 /* bitmap of store attributes that require enabled dcache */
#endif
#define XCHAL_LSCA_ENAMASK (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK) /* l/s attrs requiring enabled dcache */
#define XCHAL_ALLCA_ENAMASK (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK) /* all attrs requiring enabled caches */
/*
* _cacheattr_is_enabled
*
* (Internal macro.)
* Branches to \label if CACHEATTR in a2 indicates an enabled
* cache, using mask in a3.
*
* Parameters:
* label where to branch to if cache is enabled
* Entry:
* a2 contains CACHEATTR value used to determine whether
* caches are enabled
* a3 16-bit constant where each bit correspond to
* one of the 16 possible CA values (in a CACHEATTR mask);
* CA values that indicate the cache is enabled
* have their corresponding bit set in this mask
* (eg. use XCHAL_xCA_ENAMASK , above)
* Exit:
* a2,a4,a5 clobbered
* SAR clobbered
*/
.macro _cacheattr_is_enabled label
movi a4, 8 // loop 8 times
.Lcaife\@:
extui a5, a2, 0, 4 // get CA nibble
ssr a5 // index into mask according to CA...
srl a5, a3 // ...and get CA's mask bit in a5 bit 0
bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label
srli a2, a2, 4 // next nibble
addi a4, a4, -1
bnez a4, .Lcaife\@ // loop for each nibble
.endm
#else /* XCHAL_CA_8X512 */
.macro _cacheattr_is_enabled label
j \label // macro not applicable, assume caches always enabled
.endm
#endif /* XCHAL_CA_8X512 */
/*
* icacheattr_is_enabled
*
* Branches to \label if I-cache is enabled.
*
* Parameters:
* label where to branch to if icache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro icacheattr_is_enabled label
#if XCHAL_CA_8X512
icacheattr_get
movi a3, XCHAL_FCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* dcacheattr_is_enabled
*
* Branches to \label if D-cache is enabled.
*
* Parameters:
* label where to branch to if dcache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro dcacheattr_is_enabled label
#if XCHAL_CA_8X512
dcacheattr_get
movi a3, XCHAL_LSCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* cacheattr_is_enabled
*
* Branches to \label if either I-cache or D-cache is enabled.
*
* Parameters:
* label where to branch to if a cache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro cacheattr_is_enabled label
#if XCHAL_HAVE_CACHEATTR
rsr a2, CACHEATTR
movi a3, XCHAL_ALLCA_ENAMASK
#elif XCHAL_CA_8X512
icacheattr_get
movi a3, XCHAL_FCA_ENAMASK
_cacheattr_is_enabled \label
dcacheattr_get
movi a3, XCHAL_LSCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* The ISA does not have a defined way to change the
* instruction cache attributes of the running code,
* ie. of the memory area that encloses the current PC.
* However, each micro-architecture (or class of
* configurations within a micro-architecture)
* provides a way to deal with this issue.
*
* Here are a few macros used to implement the relevant
* approach taken.
*/
#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR
// We have a config that "mimics" CACHEATTR using a simplified
// "MMU" composed of a single statically-mapped way.
/*
* icacheattr_set
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro icacheattr_set
movi a5, 0xE0000000 // mask of upper 3 bits
movi a6, 3f // PC where ITLB is set
movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
mov a7, a2 // copy a2 so it doesn't get clobbered
and a6, a6, a5 // upper 3 bits of local PC area
j 3f
// Use micro-architecture specific method.
// The following 4-instruction sequence is aligned such that
// it all fits within a single I-cache line. Sixteen byte
// alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
// actually causes problems because that can be greater than
// the alignment of the reset vector, where this macro is often
// invoked, which would cause the linker to align the reset
// vector code away from the reset vector!!).
.begin no-transform
.align 16 /*XCHAL_ICACHE_LINESIZE*/
1: witlb a4, a3 // write wired PTE (CA, no PPN) of 512MB segment to ITLB
isync
.end no-transform
nop
nop
sub a3, a3, a5 // next segment (add 0x20000000)
bltui a3, 16, 4f // done?
// Note that in the WITLB loop, we don't do any load/stores
// (may not be an issue here, but it is important in the DTLB case).
2: srli a7, a7, 4 // next CA
3:
# if XCHAL_HAVE_MIMIC_CACHEATTR
extui a4, a7, 0, 4 // extract CA to set
# else /* have translation, preserve it: */
ritlb1 a8, a3 // get current PPN+CA of segment
//dsync // interlock???
extui a4, a7, 0, 4 // extract CA to set
srli a8, a8, 4 // clear CA but keep PPN ...
slli a8, a8, 4 // ...
add a4, a4, a8 // combine new CA with PPN to preserve
# endif
beq a3, a6, 1b // current PC's region? if so, do it in a safe way
witlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to ITLB
sub a3, a3, a5 // next segment (add 0x20000000)
bgeui a3, 16, 2b
isync // make sure all ifetch changes take effect
4:
.endm // icacheattr_set
/*
* dcacheattr_set
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro dcacheattr_set
movi a5, 0xE0000000 // mask of upper 3 bits
movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
mov a7, a2 // copy a2 so it doesn't get clobbered
// Note that in the WDTLB loop, we don't do any load/stores
2: // (including implicit l32r via movi) because it isn't safe.
# if XCHAL_HAVE_MIMIC_CACHEATTR
extui a4, a7, 0, 4 // extract CA to set
# else /* have translation, preserve it: */
rdtlb1 a8, a3 // get current PPN+CA of segment
//dsync // interlock???
extui a4, a7, 0, 4 // extract CA to set
srli a8, a8, 4 // clear CA but keep PPN ...
slli a8, a8, 4 // ...
add a4, a4, a8 // combine new CA with PPN to preserve
# endif
wdtlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to DTLB
sub a3, a3, a5 // next segment (add 0x20000000)
srli a7, a7, 4 // next CA
bgeui a3, 16, 2b
dsync // make sure all data path changes take effect
.endm // dcacheattr_set
#endif /* XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR */
/*
* cacheattr_set
*
* Macro that sets the current CACHEATTR safely
* (both i and d) according to the current contents of a2.
* It works even when changing the cache attributes of
* the currently running code.
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro cacheattr_set
#if XCHAL_HAVE_CACHEATTR
# if XCHAL_ICACHE_LINESIZE < 4
// No i-cache, so can always safely write to CACHEATTR:
wsr a2, CACHEATTR
# else
// The Athens micro-architecture, when using the old
// exception architecture option (ie. with the CACHEATTR register)
// allows changing the cache attributes of the running code
// using the following exact sequence aligned to be within
// an instruction cache line. (NOTE: using XCHAL_ICACHE_LINESIZE
// alignment actually causes problems because that can be greater
// than the alignment of the reset vector, where this macro is often
// invoked, which would cause the linker to align the reset
// vector code away from the reset vector!!).
j 1f
.begin no-transform
.align 16 /*XCHAL_ICACHE_LINESIZE*/ // align to within an I-cache line
1: wsr a2, CACHEATTR
isync
.end no-transform
nop
nop
# endif
#elif XCHAL_CA_8X512
// DTLB and ITLB are independent, but to keep semantics
// of this macro we simply write to both.
icacheattr_set
dcacheattr_set
#else
// This macro isn't applicable to arbitrary MMU configurations.
// Do nothing in this case.
#endif
.endm
#endif /*XTENSA_CACHEATTRASM_H*/

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tools/sdk/include/esp32/xtensa/config/core-isa.h
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@ -1,655 +0,0 @@
/*
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
* processor CORE configuration
*
* See <xtensa/config/core.h>, which includes this file, for more details.
*/
/* Xtensa processor core configuration information.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
/*
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
* configured, and a value of 0 otherwise. These macros are always defined.
*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS 1 /* */
#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID 1 /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
#define XCHAL_HAVE_HIFI_MINI 0
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_FP 1 /* single prec floating point */
#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay
(1 = 5-stage, 2 = 7-stage) */
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
/* In T1050, applies to selected core load and store instructions (see ISA): */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
#define XCHAL_SW_VERSION 1100003 /* sw version of this header */
#define XCHAL_CORE_ID "esp32_v3_49_prod" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x0005FE96 /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
#define XCHAL_HW_CONFIGID0 0xC2BCFFFE /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x1CC5FE96 /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 260003 /* major*100+minor */
#define XCHAL_HW_REL_LX6 1
#define XCHAL_HW_REL_LX6_0 1
#define XCHAL_HW_REL_LX6_0_3 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a *range* of hardware versions, these are the bounds: */
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */
#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
#define XCHAL_HAVE_AXI 0 /* AXI bus */
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 0
#define XCHAL_DCACHE_SETWIDTH 0
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 1
#define XCHAL_DCACHE_WAYS 1
/* Cache features: */
#define XCHAL_ICACHE_LINE_LOCKABLE 0
#define XCHAL_DCACHE_LINE_LOCKABLE 0
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_BANKS 0 /* number of banks */
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */
#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
/* Instruction ROM 0: */
#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */
#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */
#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Instruction RAM 1: */
#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */
#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */
#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Data ROM 0: */
#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */
#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */
#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */
#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATAROM0_BANKS 1 /* number of banks */
/* Data RAM 0: */
#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */
#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */
#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
/* Data RAM 1: */
#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */
#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */
#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */
#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM1_BANKS 1 /* number of banks */
/* XLMI Port 0: */
#define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */
#define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */
#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */
#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
(not including level zero) */
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x000637FF
#define XCHAL_INTLEVEL2_MASK 0x00380000
#define XCHAL_INTLEVEL3_MASK 0x28C08800
#define XCHAL_INTLEVEL4_MASK 0x53000000
#define XCHAL_INTLEVEL5_MASK 0x84010000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00004000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 1
#define XCHAL_INT2_LEVEL 1
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 1
#define XCHAL_INT5_LEVEL 1
#define XCHAL_INT6_LEVEL 1
#define XCHAL_INT7_LEVEL 1
#define XCHAL_INT8_LEVEL 1
#define XCHAL_INT9_LEVEL 1
#define XCHAL_INT10_LEVEL 1
#define XCHAL_INT11_LEVEL 3
#define XCHAL_INT12_LEVEL 1
#define XCHAL_INT13_LEVEL 1
#define XCHAL_INT14_LEVEL 7
#define XCHAL_INT15_LEVEL 3
#define XCHAL_INT16_LEVEL 5
#define XCHAL_INT17_LEVEL 1
#define XCHAL_INT18_LEVEL 1
#define XCHAL_INT19_LEVEL 2
#define XCHAL_INT20_LEVEL 2
#define XCHAL_INT21_LEVEL 2
#define XCHAL_INT22_LEVEL 3
#define XCHAL_INT23_LEVEL 3
#define XCHAL_INT24_LEVEL 4
#define XCHAL_INT25_LEVEL 4
#define XCHAL_INT26_LEVEL 5
#define XCHAL_INT27_LEVEL 3
#define XCHAL_INT28_LEVEL 4
#define XCHAL_INT29_LEVEL 3
#define XCHAL_INT30_LEVEL 4
#define XCHAL_INT31_LEVEL 5
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F
#define XCHAL_INTTYPE_MASK_TIMER 0x00018040
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800
/* Interrupt numbers assigned to specific interrupt sources: */
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
#define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */
/* Interrupt numbers for levels at which only one interrupt is configured: */
#define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
/*
* External interrupt mapping.
* These macros describe how Xtensa processor interrupt numbers
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
* map to external BInterrupt<n> pins, for those interrupts
* configured as external (level-triggered, edge-triggered, or NMI).
* See the Xtensa processor databook for more details.
*/
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */
#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */
#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */
#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */
#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */
#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */
#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */
#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */
#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */
#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */
#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */
#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */
#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */
#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */
#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */
#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */
#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */
#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */
#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */
#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */
#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */
#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */
#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */
#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */
#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
number: 1 == XEA1 (old)
2 == XEA2 (new)
0 == XEAX (extern) or TX */
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
#define XCHAL_RESET_VECBASE_OVERLAP 0
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
#define XCHAL_RESET_VECTOR_VADDR 0x40000400
#define XCHAL_RESET_VECTOR_PADDR 0x40000400
#define XCHAL_USER_VECOFS 0x00000340
#define XCHAL_USER_VECTOR_VADDR 0x40000340
#define XCHAL_USER_VECTOR_PADDR 0x40000340
#define XCHAL_KERNEL_VECOFS 0x00000300
#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
#define XCHAL_NMI_VECOFS 0x000002C0
#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/*----------------------------------------------------------------------
DEBUG MODULE
----------------------------------------------------------------------*/
/* Misc */
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
/* On-Chip Debug (OCD) */
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
/* TRAX (in core) */
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
/* Perf counters */
#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
[autorefill] and protection)
usable for an MMU-based OS */
/* If none of the above last 4 are set, it's a custom TLB configuration. */
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */

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tools/sdk/include/esp32/xtensa/config/core-matmap.h
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/*
* xtensa/config/core-matmap.h -- Memory access and translation mapping
* parameters (CHAL) of the Xtensa processor core configuration.
*
* If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
* this file) for more details.
*
* In the Xtensa processor products released to date, all parameters
* defined in this file are derivable (at least in theory) from
* information contained in the core-isa.h header file.
* In particular, the following core configuration parameters are relevant:
* XCHAL_HAVE_CACHEATTR
* XCHAL_HAVE_MIMIC_CACHEATTR
* XCHAL_HAVE_XLT_CACHEATTR
* XCHAL_HAVE_PTP_MMU
* XCHAL_ITLB_ARF_ENTRIES_LOG2
* XCHAL_DTLB_ARF_ENTRIES_LOG2
* XCHAL_DCACHE_IS_WRITEBACK
* XCHAL_ICACHE_SIZE (presence of I-cache)
* XCHAL_DCACHE_SIZE (presence of D-cache)
* XCHAL_HW_VERSION_MAJOR
* XCHAL_HW_VERSION_MINOR
*/
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_CONFIG_CORE_MATMAP_H
#define XTENSA_CONFIG_CORE_MATMAP_H
/*----------------------------------------------------------------------
CACHE (MEMORY ACCESS) ATTRIBUTES
----------------------------------------------------------------------*/
/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION
#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION
#define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION
/*
* Specific encoded cache attribute values of general interest.
* If a specific cache mode is not available, the closest available
* one is returned instead (eg. writethru instead of writeback,
* bypass instead of writethru).
*/
#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */
#define XCHAL_CA_WRITETHRU 2 /* cache enabled (write-through) mode */
#define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */
#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */
#define XCHAL_CA_WRITEBACK_NOALLOC 2 /* cache enabled (write-back no-allocate) mode */
#define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */
#define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) */
#define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */
#define XCHAL_CA_WRITEBACK_NOALLOC_RW 0 /* cache enabled (write-back no-allocate) mode (no exec) */
#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
#define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/*
* General notes on MMU parameters.
*
* Terminology:
* ASID = address-space ID (acts as an "extension" of virtual addresses)
* VPN = virtual page number
* PPN = physical page number
* CA = encoded cache attribute (access modes)
* TLB = translation look-aside buffer (term is stretched somewhat here)
* I = instruction (fetch accesses)
* D = data (load and store accesses)
* way = each TLB (ITLB and DTLB) consists of a number of "ways"
* that simultaneously match the virtual address of an access;
* a TLB successfully translates a virtual address if exactly
* one way matches the vaddr; if none match, it is a miss;
* if multiple match, one gets a "multihit" exception;
* each way can be independently configured in terms of number of
* entries, page sizes, which fields are writable or constant, etc.
* set = group of contiguous ways with exactly identical parameters
* ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
* from the page table and storing it in one of the auto-refill ways;
* if this PTE load also misses, a miss exception is posted for s/w.
* min-wired = a "min-wired" way can be used to map a single (minimum-sized)
* page arbitrarily under program control; it has a single entry,
* is non-auto-refill (some other way(s) must be auto-refill),
* all its fields (VPN, PPN, ASID, CA) are all writable, and it
* supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
* restriction is that this be the only page size it supports).
*
* TLB way entries are virtually indexed.
* TLB ways that support multiple page sizes:
* - must have all writable VPN and PPN fields;
* - can only use one page size at any given time (eg. setup at startup),
* selected by the respective ITLBCFG or DTLBCFG special register,
* whose bits n*4+3 .. n*4 index the list of page sizes for way n
* (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
* this list may be sparse for auto-refill ways because auto-refill
* ways have independent lists of supported page sizes sharing a
* common encoding with PTE entries; the encoding is the index into
* this list; unsupported sizes for a given way are zero in the list;
* selecting unsupported sizes results in undefined hardware behaviour;
* - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
*/
#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
/*** Instruction TLB: ***/
#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
/* Way set to which each way belongs: */
#define XCHAL_ITLB_WAY0_SET 0
/* Ways sets that are used by hardware auto-refill (ARF): */
#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
/* Way sets that are "min-wired" (see terminology comment above): */
#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
/* ITLB way set 0 (group of ways 0 thru 0): */
#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
/*** Data TLB: ***/
#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
/* Way set to which each way belongs: */
#define XCHAL_DTLB_WAY0_SET 0
/* Ways sets that are used by hardware auto-refill (ARF): */
#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
/* Way sets that are "min-wired" (see terminology comment above): */
#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
/* DTLB way set 0 (group of ways 0 thru 0): */
#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/

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tools/sdk/include/esp32/xtensa/config/core.h
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tools/sdk/include/esp32/xtensa/config/defs.h
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/* Definitions for Xtensa instructions, types, and protos. */
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2003-2004 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
/* NOTE: This file exists only for backward compatibility with T1050
and earlier Xtensa releases. It includes only a subset of the
available header files. */
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
#include <xtensa/tie/xt_core.h>
#include <xtensa/tie/xt_misc.h>
#include <xtensa/tie/xt_booleans.h>
#endif /* __XTENSA__ */
#endif /* !_XTENSA_BASE_HEADER */

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tools/sdk/include/esp32/xtensa/config/specreg.h
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/*
* Xtensa Special Register symbolic names
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1998-2002 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Include these special register bitfield definitions, for historical reasons: */
#include <xtensa/corebits.h>
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define SCOMPARE1 12
#define ACCLO 16
#define ACCHI 17
#define MR_0 32
#define MR_1 33
#define MR_2 34
#define MR_3 35
#define WINDOWBASE 72
#define WINDOWSTART 73
#define IBREAKENABLE 96
#define MEMCTL 97
#define ATOMCTL 99
#define DDR 104
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define EPC_5 181
#define EPC_6 182
#define EPC_7 183
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EPS_5 197
#define EPS_6 198
#define EPS_7 199
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define EXCSAVE_5 213
#define EXCSAVE_6 214
#define EXCSAVE_7 215
#define CPENABLE 224
#define INTERRUPT 226
#define INTENABLE 228
#define PS 230
#define VECBASE 231
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
#define MISC_REG_2 246
#define MISC_REG_3 247
/* Special cases (bases of special register series): */
#define MR 32
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
/* Special names for read-only and write-only interrupt registers: */
#define INTREAD 226
#define INTSET 226
#define INTCLEAR 227
#endif /* XTENSA_SPECREG_H */

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tools/sdk/include/esp32/xtensa/config/system.h
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/*
* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
*
* NOTE: The location and contents of this file are highly subject to change.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* The HAL itself has historically included this file in some instances,
* but this is not appropriate either, because the HAL is meant to be
* core-specific but system independent.
*/
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2000-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H
/*#include <xtensa/hal.h>*/
/*----------------------------------------------------------------------
CONFIGURED SOFTWARE OPTIONS
----------------------------------------------------------------------*/
#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */
/* The above maps to one of the following constants: */
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
/* Alternatives: */
/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
/* The above maps to one of the following constants: */
#define XTHAL_CLIB_NEWLIB 0
#define XTHAL_CLIB_UCLIBC 1
#define XTHAL_CLIB_XCLIB 2
/* Alternatives: */
/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
#define XSHAL_USE_FLOATING_POINT 1
#define XSHAL_FLOATING_POINT_ABI 0
/* SW workarounds enabled for HW errata: */
/*----------------------------------------------------------------------
DEVICE ADDRESSES
----------------------------------------------------------------------*/
/*
* Strange place to find these, but the configuration GUI
* allows moving these around to account for various core
* configurations. Specific boards (and their BSP software)
* will have specific meanings for these components.
*/
/* I/O Block areas: */
#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
/* System ROM: */
#define XSHAL_ROM_VADDR 0x50000000
#define XSHAL_ROM_PADDR 0x50000000
#define XSHAL_ROM_SIZE 0x01000000
/* Largest available area (free of vectors): */
#define XSHAL_ROM_AVAIL_VADDR 0x50000000
#define XSHAL_ROM_AVAIL_VSIZE 0x01000000
/* System RAM: */
#define XSHAL_RAM_VADDR 0x60000000
#define XSHAL_RAM_PADDR 0x60000000
#define XSHAL_RAM_VSIZE 0x20000000
#define XSHAL_RAM_PSIZE 0x20000000
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
/* Largest available area (free of vectors): */
#define XSHAL_RAM_AVAIL_VADDR 0x60000000
#define XSHAL_RAM_AVAIL_VSIZE 0x20000000
/*
* Shadow system RAM (same device as system RAM, at different address).
* (Emulation boards need this for the SONIC Ethernet driver
* when data caches are configured for writeback mode.)
* NOTE: on full MMU configs, this points to the BYPASS virtual address
* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
* addresses are viewed through the BYPASS static map rather than
* the CACHED static map.
*/
#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
#define XSHAL_RAM_BYPASS_PSIZE 0x20000000
/* Alternate system RAM (different device than system RAM): */
/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
/* Some available location in which to place devices in a simulation (eg. XTMP): */
#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
#define XSHAL_SIMIO_PADDR 0xC0000000
#define XSHAL_SIMIO_SIZE 0x20000000
/*----------------------------------------------------------------------
* For use by reference testbench exit and diagnostic routines.
*/
#define XSHAL_MAGIC_EXIT 0x0
/*----------------------------------------------------------------------
* DEVICE-ADDRESS DEPENDENT...
*
* Values written to CACHEATTR special register (or its equivalent)
* to enable and disable caches in various modes.
*----------------------------------------------------------------------*/
/*----------------------------------------------------------------------
BACKWARD COMPATIBILITY ...
----------------------------------------------------------------------*/
/*
* NOTE: the following two macros are DEPRECATED. Use the latter
* board-specific macros instead, which are specially tuned for the
* particular target environments' memory maps.
*/
#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
/*----------------------------------------------------------------------
GENERIC
----------------------------------------------------------------------*/
/* For the following, a 512MB region is used if it contains a system (PIF) RAM,
* system (PIF) ROM, local memory, or XLMI. */
/* These set any unused 512MB region to cache-BYPASS attribute: */
#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22221112 /* enable caches in write-back mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
/* These set any unused 512MB region to ILLEGAL attribute: */
#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF111F /* enable caches in write-back mode */
#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
* NULL-pointer dereference bugs; all other unused 512MB regions are set
* to cache-BYPASS attribute: */
#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
/*----------------------------------------------------------------------
ISS (Instruction Set Simulator) SPECIFIC ...
----------------------------------------------------------------------*/
/* For now, ISS defaults to the TRAPNULL settings: */
#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
#define XSHAL_ISS_PIPE_REGIONS 0
#define XSHAL_ISS_SDRAM_REGIONS 0
/*----------------------------------------------------------------------
XT2000 BOARD SPECIFIC ...
----------------------------------------------------------------------*/
/* For the following, a 512MB region is used if it contains any system RAM,
* system ROM, local memory, XLMI, or other XT2000 board device or memory.
* Regions containing devices are forced to cache-BYPASS mode regardless
* of whether the macro is _WRITEBACK vs. _BYPASS etc. */
/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22111F /* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
/*----------------------------------------------------------------------
VECTOR INFO AND SIZES
----------------------------------------------------------------------*/
#define XSHAL_VECTORS_PACKED 0
#define XSHAL_STATIC_VECTOR_SELECT 1
#define XSHAL_RESET_VECTOR_VADDR 0x40000400
#define XSHAL_RESET_VECTOR_PADDR 0x40000400
/*
* Sizes allocated to vectors by the system (memory map) configuration.
* These sizes are constrained by core configuration (eg. one vector's
* code cannot overflow into another vector) but are dependent on the
* system or board (or LSP) memory map configuration.
*
* Whether or not each vector happens to be in a system ROM is also
* a system configuration matter, sometimes useful, included here also:
*/
#define XSHAL_RESET_VECTOR_SIZE 0x00000300
#define XSHAL_RESET_VECTOR_ISROM 0
#define XSHAL_USER_VECTOR_SIZE 0x00000038
#define XSHAL_USER_VECTOR_ISROM 0
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
#define XSHAL_KERNEL_VECTOR_ISROM 0
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
#define XSHAL_WINDOW_VECTORS_ISROM 0
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
#define XSHAL_NMI_VECTOR_SIZE 0x00000038
#define XSHAL_NMI_VECTOR_ISROM 0
#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
#endif /*XTENSA_CONFIG_SYSTEM_H*/

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/*
* tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
*
* NOTE: This header file is not meant to be included directly.
*/
/* This header file contains assembly-language definitions (assembly
macros, etc.) for this specific Xtensa processor's TIE extensions
and options. It is customized to this Xtensa processor configuration.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_TIE_ASM_H
#define _XTENSA_CORE_TIE_ASM_H
/* Selection parameter values for save-area save/restore macros: */
/* Option vs. TIE: */
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
/* Whether used automatically by compiler: */
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
/* ABI handling across function calls: */
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
/* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
| ((ccuse) & XTHAL_SAS_ANYCC) \
| ((abi) & XTHAL_SAS_ANYABI) )
/*
* Macro to store all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger store sequence, set to 1
* if this is not the first in the sequence. Defaults to 0.
* ofs Offset from start of larger sequence (from value of first ptr
* in sequence) at which to store. Defaults to next available space
* (or 0 if <continue> is 0).
* select Select what category(ies) of registers to store, as a bitmask
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
* alloc Select what category(ies) of registers to allocate; if any
* category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any store.
*/
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
rur.THREADPTR \at1 // threadptr option
s32i \at1, \ptr, .Lxchal_ofs_+0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
// Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4
rsr.ACCLO \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.ACCHI \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1012, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4
rsr.BR \at1 // boolean option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.SCOMPARE1 \at1 // conditional store option
s32i \at1, \ptr, .Lxchal_ofs_+4
rsr.M0 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+8
rsr.M1 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+12
rsr.M2 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+16
rsr.M3 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+20
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1008, 4, 4
rur.F64R_LO \at1 // ureg 234
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.F64R_HI \at1 // ureg 235
s32i \at1, \ptr, .Lxchal_ofs_+4
rur.F64S \at1 // ureg 236
s32i \at1, \ptr, .Lxchal_ofs_+8
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1008, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.endif
.endm // xchal_ncp_store
/*
* Macro to load all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger load sequence, set to 1
* if this is not the first in the sequence. Defaults to 0.
* ofs Offset from start of larger sequence (from value of first ptr
* in sequence) at which to load. Defaults to next available space
* (or 0 if <continue> is 0).
* select Select what category(ies) of registers to load, as a bitmask
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
* alloc Select what category(ies) of registers to allocate; if any
* category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any load.
*/
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.THREADPTR \at1 // threadptr option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
// Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.ACCLO \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.ACCHI \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1012, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.BR \at1 // boolean option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.SCOMPARE1 \at1 // conditional store option
l32i \at1, \ptr, .Lxchal_ofs_+8
wsr.M0 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+12
wsr.M1 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+16
wsr.M2 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+20
wsr.M3 \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1008, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.F64R_LO \at1 // ureg 234
l32i \at1, \ptr, .Lxchal_ofs_+4
wur.F64R_HI \at1 // ureg 235
l32i \at1, \ptr, .Lxchal_ofs_+8
wur.F64S \at1 // ureg 236
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1008, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.endif
.endm // xchal_ncp_load
#define XCHAL_NCP_NUM_ATMPS 1
/*
* Macro to store the state of TIE coprocessor FPU.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_store.
*/
#define xchal_cp_FPU_store xchal_cp0_store
.macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4
rur.FCR \at1 // ureg 232
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.FSR \at1 // ureg 233
s32i \at1, \ptr, .Lxchal_ofs_+4
ssi f0, \ptr, .Lxchal_ofs_+8
ssi f1, \ptr, .Lxchal_ofs_+12
ssi f2, \ptr, .Lxchal_ofs_+16
ssi f3, \ptr, .Lxchal_ofs_+20
ssi f4, \ptr, .Lxchal_ofs_+24
ssi f5, \ptr, .Lxchal_ofs_+28
ssi f6, \ptr, .Lxchal_ofs_+32
ssi f7, \ptr, .Lxchal_ofs_+36
ssi f8, \ptr, .Lxchal_ofs_+40
ssi f9, \ptr, .Lxchal_ofs_+44
ssi f10, \ptr, .Lxchal_ofs_+48
ssi f11, \ptr, .Lxchal_ofs_+52
ssi f12, \ptr, .Lxchal_ofs_+56
ssi f13, \ptr, .Lxchal_ofs_+60
ssi f14, \ptr, .Lxchal_ofs_+64
ssi f15, \ptr, .Lxchal_ofs_+68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 948, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_store
/*
* Macro to load the state of TIE coprocessor FPU.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_load.
*/
#define xchal_cp_FPU_load xchal_cp0_load
.macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.FCR \at1 // ureg 232
l32i \at1, \ptr, .Lxchal_ofs_+4
wur.FSR \at1 // ureg 233
lsi f0, \ptr, .Lxchal_ofs_+8
lsi f1, \ptr, .Lxchal_ofs_+12
lsi f2, \ptr, .Lxchal_ofs_+16
lsi f3, \ptr, .Lxchal_ofs_+20
lsi f4, \ptr, .Lxchal_ofs_+24
lsi f5, \ptr, .Lxchal_ofs_+28
lsi f6, \ptr, .Lxchal_ofs_+32
lsi f7, \ptr, .Lxchal_ofs_+36
lsi f8, \ptr, .Lxchal_ofs_+40
lsi f9, \ptr, .Lxchal_ofs_+44
lsi f10, \ptr, .Lxchal_ofs_+48
lsi f11, \ptr, .Lxchal_ofs_+52
lsi f12, \ptr, .Lxchal_ofs_+56
lsi f13, \ptr, .Lxchal_ofs_+60
lsi f14, \ptr, .Lxchal_ofs_+64
lsi f15, \ptr, .Lxchal_ofs_+68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 948, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_load
#define XCHAL_CP0_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
/* Empty macros for unconfigured coprocessors: */
.macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
#endif /*_XTENSA_CORE_TIE_ASM_H*/

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/*
* tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
*
* NOTE: This header file is not meant to be included directly.
*/
/* This header file describes this specific Xtensa processor's TIE extensions
that extend basic Xtensa core functionality. It is customized to this
Xtensa processor configuration.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_TIE_H
#define _XTENSA_CORE_TIE_H
#define XCHAL_CP_NUM 1 /* number of coprocessors */
#define XCHAL_CP_MAX 1 /* max CP ID + 1 (0 if none) */
#define XCHAL_CP_MASK 0x01 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
/* Basic parameters of each coprocessor: */
#define XCHAL_CP0_NAME "FPU"
#define XCHAL_CP0_IDENT FPU
#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_SIZE 0
#define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 48
#define XCHAL_NCP_SA_ALIGN 4
/* Total save area for optional and custom state (NCP + CPn): */
#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
/*
* Detailed contents of save areas.
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
* before expanding the XCHAL_xxx_SA_LIST() macros.
*
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
*
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
* ccused = set if used by compiler without special options or code
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
* name = lowercase reg name (no quotes)
* galign = group byte alignment (power of 2) (galign >= align)
* align = register byte alignment (power of 2)
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
* (not including any pad bytes required to galign this or next reg)
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
* regnum = reg index in regfile, or special/TIE-user reg number
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
* gapsz = intervening bits, if bitsz bits not stored contiguously
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
* reset = register reset value (or 0 if undefined at reset)
* x = reserved for future use (0 until then)
*
* To filter out certain registers, e.g. to expand only the non-global
* registers used by the compiler, you can do something like this:
*
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* ...what you want to expand...
*/
#define XCHAL_NCP_SA_NUM 12
#define XCHAL_NCP_SA_LIST(s) \
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64r_lo, 4, 4, 4,0x03EA, ur,234, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64r_hi, 4, 4, 4,0x03EB, ur,235, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64s, 4, 4, 4,0x03EC, ur,236, 32,0,0,0)
#define XCHAL_CP0_SA_NUM 18
#define XCHAL_CP0_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
#define XCHAL_CP1_SA_NUM 0
#define XCHAL_CP1_SA_LIST(s) /* empty */
#define XCHAL_CP2_SA_NUM 0
#define XCHAL_CP2_SA_LIST(s) /* empty */
#define XCHAL_CP3_SA_NUM 0
#define XCHAL_CP3_SA_LIST(s) /* empty */
#define XCHAL_CP4_SA_NUM 0
#define XCHAL_CP4_SA_LIST(s) /* empty */
#define XCHAL_CP5_SA_NUM 0
#define XCHAL_CP5_SA_LIST(s) /* empty */
#define XCHAL_CP6_SA_NUM 0
#define XCHAL_CP6_SA_LIST(s) /* empty */
#define XCHAL_CP7_SA_NUM 0
#define XCHAL_CP7_SA_LIST(s) /* empty */
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
/* Byte length of instruction from its first byte, per FLIX. */
#define XCHAL_BYTE0_FORMAT_LENGTHS \
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_XTENSA_CORE_TIE_H*/

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tools/sdk/include/esp32/xtensa/core-macros.h
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@ -1,456 +0,0 @@
/*
* xtensa/core-macros.h -- C specific definitions
* that depend on CORE configuration
*/
/*
* Copyright (c) 2012 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_CACHE_H
#define XTENSA_CACHE_H
#include <xtensa/config/core.h>
/* Only define things for C code. */
#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
/*************************** CACHE ***************************/
/* All the macros are in the lower case now and some of them
* share the name with the existing functions from hal.h.
* Including this header file will define XTHAL_USE_CACHE_MACROS
* which directs hal.h not to use the functions.
*/
/*
* Single-cache-line operations in C-callable inline assembly.
* Essentially macro versions (uppercase) of:
*
* xthal_icache_line_invalidate(void *addr);
* xthal_icache_line_lock(void *addr);
* xthal_icache_line_unlock(void *addr);
* xthal_icache_sync(void);
*
* NOTE: unlike the above functions, the following macros do NOT
* execute the xthal_icache_sync() as part of each line operation.
* This sync must be called explicitly by the caller. This is to
* allow better optimization when operating on more than one line.
*
* xthal_dcache_line_invalidate(void *addr);
* xthal_dcache_line_writeback(void *addr);
* xthal_dcache_line_writeback_inv(void *addr);
* xthal_dcache_line_lock(void *addr);
* xthal_dcache_line_unlock(void *addr);
* xthal_dcache_sync(void);
* xthal_dcache_line_prefetch_for_write(void *addr);
* xthal_dcache_line_prefetch_for_read(void *addr);
*
* All are made memory-barriers, given that's how they're typically used
* (ops operate on a whole line, so clobbers all memory not just *addr).
*
* NOTE: All the block block cache ops and line prefetches are implemented
* using intrinsics so they are better optimized regarding memory barriers etc.
*
* All block downgrade functions exist in two forms: with and without
* the 'max' parameter: This parameter allows compiler to optimize
* the functions whenever the parameter is smaller than the cache size.
*
* xthal_dcache_block_invalidate(void *addr, unsigned size);
* xthal_dcache_block_writeback(void *addr, unsigned size);
* xthal_dcache_block_writeback_inv(void *addr, unsigned size);
* xthal_dcache_block_invalidate_max(void *addr, unsigned size, unsigned max);
* xthal_dcache_block_writeback_max(void *addr, unsigned size, unsigned max);
* xthal_dcache_block_writeback_inv_max(void *addr, unsigned size, unsigned max);
*
* xthal_dcache_block_prefetch_for_read(void *addr, unsigned size);
* xthal_dcache_block_prefetch_for_write(void *addr, unsigned size);
* xthal_dcache_block_prefetch_modify(void *addr, unsigned size);
* xthal_dcache_block_prefetch_read_write(void *addr, unsigned size);
* xthal_dcache_block_prefetch_for_read_grp(void *addr, unsigned size);
* xthal_dcache_block_prefetch_for_write_grp(void *addr, unsigned size);
* xthal_dcache_block_prefetch_modify_grp(void *addr, unsigned size);
* xthal_dcache_block_prefetch_read_write_grp(void *addr, unsigned size)
*
* xthal_dcache_block_wait();
* xthal_dcache_block_required_wait();
* xthal_dcache_block_abort();
* xthal_dcache_block_prefetch_end();
* xthal_dcache_block_newgrp();
*/
/*** INSTRUCTION CACHE ***/
#define XTHAL_USE_CACHE_MACROS
#if XCHAL_ICACHE_SIZE > 0
# define xthal_icache_line_invalidate(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("ihi %0, 0" :: "a"(__a) : "memory"); \
} while(0)
#else
# define xthal_icache_line_invalidate(addr) do {/*nothing*/} while(0)
#endif
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
# define xthal_icache_line_lock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("ipfl %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_icache_line_unlock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("ihu %0, 0" :: "a"(__a) : "memory"); \
} while(0)
#else
# define xthal_icache_line_lock(addr) do {/*nothing*/} while(0)
# define xthal_icache_line_unlock(addr) do {/*nothing*/} while(0)
#endif
/*
* Even if a config doesn't have caches, an isync is still needed
* when instructions in any memory are modified, whether by a loader
* or self-modifying code. Therefore, this macro always produces
* an isync, whether or not an icache is present.
*/
#define xthal_icache_sync() \
__asm__ __volatile__("isync":::"memory")
/*** DATA CACHE ***/
#if XCHAL_DCACHE_SIZE > 0
# include <xtensa/tie/xt_datacache.h>
# define xthal_dcache_line_invalidate(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhi %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_line_writeback(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhwb %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_line_writeback_inv(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhwbi %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_sync() \
__asm__ __volatile__("" /*"dsync"?*/:::"memory")
# define xthal_dcache_line_prefetch_for_read(addr) do { \
XT_DPFR((const int*)addr, 0); \
} while(0)
#else
# define xthal_dcache_line_invalidate(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_writeback(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_writeback_inv(addr) do {/*nothing*/} while(0)
# define xthal_dcache_sync() __asm__ __volatile__("":::"memory")
# define xthal_dcache_line_prefetch_for_read(addr) do {/*nothing*/} while(0)
#endif
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
# define xthal_dcache_line_lock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dpfl %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_line_unlock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhu %0, 0" :: "a"(__a) : "memory"); \
} while(0)
#else
# define xthal_dcache_line_lock(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_unlock(addr) do {/*nothing*/} while(0)
#endif
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
# define xthal_dcache_line_prefetch_for_write(addr) do { \
XT_DPFW((const int*)addr, 0); \
} while(0)
#else
# define xthal_dcache_line_prefetch_for_write(addr) do {/*nothing*/} while(0)
#endif
/***** Block Operations *****/
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS
/* upgrades */
# define _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, type) \
{ \
type((const int*)addr, size); \
}
/*downgrades */
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type) \
unsigned _s = size; \
unsigned _a = addr; \
do { \
unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? \
XCHAL_DCACHE_SIZE : _s; \
type((const int*)_a, __s); \
_s -= __s; \
_a += __s; \
} while(_s > 0);
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max) \
if (max <= XCHAL_DCACHE_SIZE) { \
unsigned _s = size; \
unsigned _a = addr; \
type((const int*)_a, _s); \
} \
else { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type); \
}
# define xthal_dcache_block_invalidate(addr, size) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHI_B); \
} while(0)
# define xthal_dcache_block_writeback(addr, size) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWB_B); \
} while(0)
# define xthal_dcache_block_writeback_inv(addr, size) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWBI_B); \
} while(0)
# define xthal_dcache_block_invalidate_max(addr, size, max) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHI_B, max); \
} while(0)
# define xthal_dcache_block_writeback_max(addr, size, max) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWB_B, max); \
} while(0)
# define xthal_dcache_block_writeback_inv_max(addr, size, max) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWBI_B, max); \
} while(0)
/* upgrades that are performed even with write-thru caches */
# define xthal_dcache_block_prefetch_read_write(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
} while(0)
# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
} while(0)
# define xthal_dcache_block_prefetch_for_read(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_B); \
} while(0)
# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_BF); \
} while(0)
/* abort all or end optional block cache operations */
# define xthal_dcache_block_abort() do { \
XT_PFEND_A(); \
} while(0)
# define xthal_dcache_block_end() do { \
XT_PFEND_O(); \
} while(0)
/* wait for all/required block cache operations to finish */
# define xthal_dcache_block_wait() do { \
XT_PFWAIT_A(); \
} while(0)
# define xthal_dcache_block_required_wait() do { \
XT_PFWAIT_R(); \
} while(0)
/* Start a new group */
# define xthal_dcache_block_newgrp() do { \
XT_PFNXT_F(); \
} while(0)
#else
# define xthal_dcache_block_invalidate(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback_inv(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_invalidate_max(addr, size, max) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback_max(addr, size, max) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback_inv_max(addr, size, max) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_read_write(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_for_read(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_end() do {/*nothing*/} while(0)
# define xthal_dcache_block_abort() do {/*nothing*/} while(0)
# define xthal_dcache_block_wait() do {/*nothing*/} while(0)
# define xthal_dcache_block_required_wait() do {/*nothing*/} while(0)
# define xthal_dcache_block_newgrp() do {/*nothing*/} while(0)
#endif
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK
# define xthal_dcache_block_prefetch_for_write(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
} while(0)
# define xthal_dcache_block_prefetch_modify(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_B); \
} while(0)
# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
} while(0)
# define xthal_dcache_block_prefetch_modify_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_BF); \
} while(0)
#else
# define xthal_dcache_block_prefetch_for_write(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_modify(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_modify_grp(addr, size) do {/*nothing*/} while(0)
#endif
/*************************** INTERRUPTS ***************************/
/*
* Macro versions of:
* unsigned xthal_get_intenable( void );
* void xthal_set_intenable( unsigned );
* unsigned xthal_get_interrupt( void );
* void xthal_set_intset( unsigned );
* void xthal_set_intclear( unsigned );
* unsigned xthal_get_ccount(void);
* void xthal_set_ccompare(int, unsigned);
* unsigned xthal_get_ccompare(int);
*
* NOTE: for {set,get}_ccompare, the first argument MUST be a decimal constant.
*/
#if XCHAL_HAVE_INTERRUPTS
# define XTHAL_GET_INTENABLE() ({ int __intenable; \
__asm__("rsr.intenable %0" : "=a"(__intenable)); \
__intenable; })
# define XTHAL_SET_INTENABLE(v) do { int __intenable = (int)(v); \
__asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
} while(0)
# define XTHAL_GET_INTERRUPT() ({ int __interrupt; \
__asm__ __volatile__("rsr.interrupt %0" : "=a"(__interrupt)); \
__interrupt; })
# define XTHAL_SET_INTSET(v) do { int __interrupt = (int)(v); \
__asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \
} while(0)
# define XTHAL_SET_INTCLEAR(v) do { int __interrupt = (int)(v); \
__asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \
} while(0)
# define XTHAL_GET_CCOUNT() ({ int __ccount; \
__asm__ __volatile__("rsr.ccount %0" : "=a"(__ccount)); \
__ccount; })
# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \
__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \
} while(0)
# define _XTHAL_GET_CCOMPARE(n) ({ int __ccompare; \
__asm__("rsr.ccompare" #n " %0" : "=a"(__ccompare)); \
__ccompare; })
# define XTHAL_GET_CCOMPARE(n) _XTHAL_GET_CCOMPARE(n)
# define _XTHAL_SET_CCOMPARE(n,v) do { int __ccompare = (int)(v); \
__asm__ __volatile__("wsr.ccompare" #n " %0 ; esync" :: "a"(__ccompare):"memory"); \
} while(0)
# define XTHAL_SET_CCOMPARE(n,v) _XTHAL_SET_CCOMPARE(n,v)
#else
# define XTHAL_GET_INTENABLE() 0
# define XTHAL_SET_INTENABLE(v) do {/*nothing*/} while(0)
# define XTHAL_GET_INTERRUPT() 0
# define XTHAL_SET_INTSET(v) do {/*nothing*/} while(0)
# define XTHAL_SET_INTCLEAR(v) do {/*nothing*/} while(0)
# define XTHAL_GET_CCOUNT() 0
# define XTHAL_SET_CCOUNT(v) do {/*nothing*/} while(0)
# define XTHAL_GET_CCOMPARE(n) 0
# define XTHAL_SET_CCOMPARE(n,v) do {/*nothing*/} while(0)
#endif
/*************************** MISC ***************************/
/*
* Macro or inline versions of:
* void xthal_clear_regcached_code( void );
* unsigned xthal_get_prid( void );
* unsigned xthal_compare_and_set( int *addr, int testval, int setval );
*/
#if XCHAL_HAVE_LOOPS
# define XTHAL_CLEAR_REGCACHED_CODE() \
__asm__ __volatile__("wsr.lcount %0" :: "a"(0) : "memory")
#else
# define XTHAL_CLEAR_REGCACHED_CODE() do {/*nothing*/} while(0)
#endif
#if XCHAL_HAVE_PRID
# define XTHAL_GET_PRID() ({ int __prid; \
__asm__("rsr.prid %0" : "=a"(__prid)); \
__prid; })
#else
# define XTHAL_GET_PRID() 0
#endif
static inline unsigned XTHAL_COMPARE_AND_SET( int *addr, int testval, int setval )
{
int result;
#if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
__asm__ __volatile__ (
" wsr.scompare1 %2 \n"
" s32c1i %0, %3, 0 \n"
: "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
: "memory");
#elif XCHAL_HAVE_INTERRUPTS
int tmp;
__asm__ __volatile__ (
" rsil %4, 15 \n" // %4 == saved ps
" l32i %0, %3, 0 \n" // %0 == value to test, return val
" bne %2, %0, 9f \n" // test
" s32i %1, %3, 0 \n" // write the new value
"9: wsr.ps %4 ; rsync \n" // restore the PS
: "=a"(result)
: "0" (setval), "a" (testval), "a" (addr), "a" (tmp)
: "memory");
#else
__asm__ __volatile__ (
" l32i %0, %3, 0 \n" // %0 == value to test, return val
" bne %2, %0, 9f \n" // test
" s32i %1, %3, 0 \n" // write the new value
"9: \n"
: "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
: "memory");
#endif
return result;
}
#if XCHAL_HAVE_EXTERN_REGS
static inline unsigned XTHAL_RER (unsigned int reg)
{
unsigned result;
__asm__ __volatile__ (
" rer %0, %1"
: "=a" (result) : "a" (reg) : "memory");
return result;
}
static inline void XTHAL_WER (unsigned reg, unsigned value)
{
__asm__ __volatile__ (
" wer %0, %1"
: : "a" (value), "a" (reg) : "memory");
}
#endif /* XCHAL_HAVE_EXTERN_REGS */
#endif /* C code */
#endif /*XTENSA_CACHE_H*/

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tools/sdk/include/esp32/xtensa/coreasm.h
View File

@ -1,939 +0,0 @@
/*
* xtensa/coreasm.h -- assembler-specific definitions that depend on CORE configuration
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL itself to include this file.
*
* This file must NOT include xtensa/config/system.h. Any assembler
* header file that depends on system information should likely go
* in a new systemasm.h (or sysasm.h) header file.
*
* NOTE: macro beqi32 is NOT configuration-dependent, and is placed
* here until we have a proper configuration-independent header file.
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/coreasm.h#3 $ */
/*
* Copyright (c) 2000-2014 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_COREASM_H
#define XTENSA_COREASM_H
/*
* Tell header files this is assembly source, so they can avoid non-assembler
* definitions (eg. C types etc):
*/
#ifndef _ASMLANGUAGE /* conditionalize to avoid cpp warnings (3rd parties might use same macro) */
#define _ASMLANGUAGE
#endif
#include <xtensa/config/core.h>
#include <xtensa/config/specreg.h>
#include <xtensa/config/system.h>
/*
* Assembly-language specific definitions (assembly macros, etc.).
*/
/*----------------------------------------------------------------------
* find_ms_setbit
*
* This macro finds the most significant bit that is set in <as>
* and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
* The index counts starting at zero for the lsbit, so the return
* value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
*
* Parameters:
* <ad> destination address register (any register)
* <as> source address register
* <at> temporary address register (must be different than <as>)
* <base> constant value added to result (usually 0 or 1)
* On entry:
* <ad> = undefined if different than <as>
* <as> = value whose most significant set bit is to be found
* <at> = undefined
* no other registers are used by this macro.
* On exit:
* <ad> = <base> + index of msbit set in original <as>,
* = <base> - 1 if original <as> was zero.
* <as> clobbered (if not <ad>)
* <at> clobbered (if not <ad>)
* Example:
* find_ms_setbit a0, a4, a0, 0 -- return in a0 index of msbit set in a4
*/
.macro find_ms_setbit ad, as, at, base
#if XCHAL_HAVE_NSA
movi \at, 31+\base
nsau \as, \as // get index of \as, numbered from msbit (32 if absent)
sub \ad, \at, \as // get numbering from lsbit (0..31, -1 if absent)
#else /* XCHAL_HAVE_NSA */
movi \at, \base // start with result of 0 (point to lsbit of 32)
beqz \as, 2f // special case for zero argument: return -1
bltui \as, 0x10000, 1f // is it one of the 16 lsbits? (if so, check lower 16 bits)
addi \at, \at, 16 // no, increment result to upper 16 bits (of 32)
//srli \as, \as, 16 // check upper half (shift right 16 bits)
extui \as, \as, 16, 16 // check upper half (shift right 16 bits)
1: bltui \as, 0x100, 1f // is it one of the 8 lsbits? (if so, check lower 8 bits)
addi \at, \at, 8 // no, increment result to upper 8 bits (of 16)
srli \as, \as, 8 // shift right to check upper 8 bits
1: bltui \as, 0x10, 1f // is it one of the 4 lsbits? (if so, check lower 4 bits)
addi \at, \at, 4 // no, increment result to upper 4 bits (of 8)
srli \as, \as, 4 // shift right 4 bits to check upper half
1: bltui \as, 0x4, 1f // is it one of the 2 lsbits? (if so, check lower 2 bits)
addi \at, \at, 2 // no, increment result to upper 2 bits (of 4)
srli \as, \as, 2 // shift right 2 bits to check upper half
1: bltui \as, 0x2, 1f // is it the lsbit?
addi \at, \at, 2 // no, increment result to upper bit (of 2)
2: addi \at, \at, -1 // (from just above: add 1; from beqz: return -1)
//srli \as, \as, 1
1: // done! \at contains index of msbit set (or -1 if none set)
.if 0x\ad - 0x\at // destination different than \at ? (works because regs are a0-a15)
mov \ad, \at // then move result to \ad
.endif
#endif /* XCHAL_HAVE_NSA */
.endm // find_ms_setbit
/*----------------------------------------------------------------------
* find_ls_setbit
*
* This macro finds the least significant bit that is set in <as>,
* and return its index in <ad>.
* Usage is the same as for the find_ms_setbit macro.
* Example:
* find_ls_setbit a0, a4, a0, 0 -- return in a0 index of lsbit set in a4
*/
.macro find_ls_setbit ad, as, at, base
neg \at, \as // keep only the least-significant bit that is set...
and \as, \at, \as // ... in \as
find_ms_setbit \ad, \as, \at, \base
.endm // find_ls_setbit
/*----------------------------------------------------------------------
* find_ls_one
*
* Same as find_ls_setbit with base zero.
* Source (as) and destination (ad) registers must be different.
* Provided for backward compatibility.
*/
.macro find_ls_one ad, as
find_ls_setbit \ad, \as, \ad, 0
.endm // find_ls_one
/*----------------------------------------------------------------------
* floop, floopnez, floopgtz, floopend
*
* These macros are used for fast inner loops that
* work whether or not the Loops options is configured.
* If the Loops option is configured, they simply use
* the zero-overhead LOOP instructions; otherwise
* they use explicit decrement and branch instructions.
*
* They are used in pairs, with floop, floopnez or floopgtz
* at the beginning of the loop, and floopend at the end.
*
* Each pair of loop macro calls must be given the loop count
* address register and a unique label for that loop.
*
* Example:
*
* movi a3, 16 // loop 16 times
* floop a3, myloop1
* :
* bnez a7, end1 // exit loop if a7 != 0
* :
* floopend a3, myloop1
* end1:
*
* Like the LOOP instructions, these macros cannot be
* nested, must include at least one instruction,
* cannot call functions inside the loop, etc.
* The loop can be exited by jumping to the instruction
* following floopend (or elsewhere outside the loop),
* or continued by jumping to a NOP instruction placed
* immediately before floopend.
*
* Unlike LOOP instructions, the register passed to floop*
* cannot be used inside the loop, because it is used as
* the loop counter if the Loops option is not configured.
* And its value is undefined after exiting the loop.
* And because the loop counter register is active inside
* the loop, you can't easily use this construct to loop
* across a register file using ROTW as you might with LOOP
* instructions, unless you copy the loop register along.
*/
/* Named label version of the macros: */
.macro floop ar, endlabel
floop_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
.macro floopnez ar, endlabel
floopnez_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
.macro floopgtz ar, endlabel
floopgtz_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
.macro floopend ar, endlabel
floopend_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
/* Numbered local label version of the macros: */
#if 0 /*UNTESTED*/
.macro floop89 ar
floop_ \ar, 8, 9f
.endm
.macro floopnez89 ar
floopnez_ \ar, 8, 9f
.endm
.macro floopgtz89 ar
floopgtz_ \ar, 8, 9f
.endm
.macro floopend89 ar
floopend_ \ar, 8b, 9
.endm
#endif /*0*/
/* Underlying version of the macros: */
.macro floop_ ar, startlabel, endlabelref
.ifdef _infloop_
.if _infloop_
.err // Error: floop cannot be nested
.endif
.endif
.set _infloop_, 1
#if XCHAL_HAVE_LOOPS
loop \ar, \endlabelref
#else /* XCHAL_HAVE_LOOPS */
\startlabel:
addi \ar, \ar, -1
#endif /* XCHAL_HAVE_LOOPS */
.endm // floop_
.macro floopnez_ ar, startlabel, endlabelref
.ifdef _infloop_
.if _infloop_
.err // Error: floopnez cannot be nested
.endif
.endif
.set _infloop_, 1
#if XCHAL_HAVE_LOOPS
loopnez \ar, \endlabelref
#else /* XCHAL_HAVE_LOOPS */
beqz \ar, \endlabelref
\startlabel:
addi \ar, \ar, -1
#endif /* XCHAL_HAVE_LOOPS */
.endm // floopnez_
.macro floopgtz_ ar, startlabel, endlabelref
.ifdef _infloop_
.if _infloop_
.err // Error: floopgtz cannot be nested
.endif
.endif
.set _infloop_, 1
#if XCHAL_HAVE_LOOPS
loopgtz \ar, \endlabelref
#else /* XCHAL_HAVE_LOOPS */
bltz \ar, \endlabelref
beqz \ar, \endlabelref
\startlabel:
addi \ar, \ar, -1
#endif /* XCHAL_HAVE_LOOPS */
.endm // floopgtz_
.macro floopend_ ar, startlabelref, endlabel
.ifndef _infloop_
.err // Error: floopend without matching floopXXX
.endif
.ifeq _infloop_
.err // Error: floopend without matching floopXXX
.endif
.set _infloop_, 0
#if ! XCHAL_HAVE_LOOPS
bnez \ar, \startlabelref
#endif /* XCHAL_HAVE_LOOPS */
\endlabel:
.endm // floopend_
/*----------------------------------------------------------------------
* crsil -- conditional RSIL (read/set interrupt level)
*
* Executes the RSIL instruction if it exists, else just reads PS.
* The RSIL instruction does not exist in the new exception architecture
* if the interrupt option is not selected.
*/
.macro crsil ar, newlevel
#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
rsil \ar, \newlevel
#else
rsr \ar, PS
#endif
.endm // crsil
/*----------------------------------------------------------------------
* safe_movi_a0 -- move constant into a0 when L32R is not safe
*
* This macro is typically used by interrupt/exception handlers.
* Loads a 32-bit constant in a0, without using any other register,
* and without corrupting the LITBASE register, even when the
* value of the LITBASE register is unknown (eg. when application
* code and interrupt/exception handling code are built independently,
* and thus with independent values of the LITBASE register;
* debug monitors are one example of this).
*
* Worst-case size of resulting code: 17 bytes.
*/
.macro safe_movi_a0 constant
#if XCHAL_HAVE_ABSOLUTE_LITERALS
/* Contort a PC-relative literal load even though we may be in litbase-relative mode: */
j 1f
.begin no-transform // ensure what follows is assembled exactly as-is
.align 4 // ensure constant and call0 target ...
.byte 0 // ... are 4-byte aligned (call0 instruction is 3 bytes long)
1: call0 2f // read PC (that follows call0) in a0
.long \constant // 32-bit constant to load into a0
2:
.end no-transform
l32i a0, a0, 0 // load constant
#else
movi a0, \constant // no LITBASE, can assume PC-relative L32R
#endif
.endm
/*----------------------------------------------------------------------
* window_spill{4,8,12}
*
* These macros spill callers' register windows to the stack.
* They work for both privileged and non-privileged tasks.
* Must be called from a windowed ABI context, eg. within
* a windowed ABI function (ie. valid stack frame, window
* exceptions enabled, not in exception mode, etc).
*
* This macro requires a single invocation of the window_spill_common
* macro in the same assembly unit and section.
*
* Note that using window_spill{4,8,12} macros is more efficient
* than calling a function implemented using window_spill_function,
* because the latter needs extra code to figure out the size of
* the call to the spilling function.
*
* Example usage:
*
* .text
* .align 4
* .global some_function
* .type some_function,@function
* some_function:
* entry a1, 16
* :
* :
*
* window_spill4 // Spill windows of some_function's callers; preserves a0..a3 only;
* // to use window_spill{8,12} in this example function we'd have
* // to increase space allocated by the entry instruction, because
* // 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
* // for call8/window_spill8 or call12/window_spill12 respectively.
*
* :
*
* retw
*
* window_spill_common // instantiates code used by window_spill4
*
*
* On entry:
* none (if window_spill4)
* stack frame has enough space allocated for call8 (if window_spill8)
* stack frame has enough space allocated for call12 (if window_spill12)
* On exit:
* a4..a15 clobbered (if window_spill4)
* a8..a15 clobbered (if window_spill8)
* a12..a15 clobbered (if window_spill12)
* no caller windows are in live registers
*/
.macro window_spill4
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 16
movi a15, 0 // for 16-register files, no need to call to reach the end
# elif XCHAL_NUM_AREGS == 32
call4 .L__wdwspill_assist28 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call4 .L__wdwspill_assist60 // call deep enough to clear out any live callers
# endif
#endif
.endm // window_spill4
.macro window_spill8
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 16
movi a15, 0 // for 16-register files, no need to call to reach the end
# elif XCHAL_NUM_AREGS == 32
call8 .L__wdwspill_assist24 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call8 .L__wdwspill_assist56 // call deep enough to clear out any live callers
# endif
#endif
.endm // window_spill8
.macro window_spill12
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 16
movi a15, 0 // for 16-register files, no need to call to reach the end
# elif XCHAL_NUM_AREGS == 32
call12 .L__wdwspill_assist20 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call12 .L__wdwspill_assist52 // call deep enough to clear out any live callers
# endif
#endif
.endm // window_spill12
/*----------------------------------------------------------------------
* window_spill_function
*
* This macro outputs a function that will spill its caller's callers'
* register windows to the stack. Eg. it could be used to implement
* a version of xthal_window_spill() that works in non-privileged tasks.
* This works for both privileged and non-privileged tasks.
*
* Typical usage:
*
* .text
* .align 4
* .global my_spill_function
* .type my_spill_function,@function
* my_spill_function:
* window_spill_function
*
* On entry to resulting function:
* none
* On exit from resulting function:
* none (no caller windows are in live registers)
*/
.macro window_spill_function
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 32
entry sp, 48
bbci.l a0, 31, 1f // branch if called with call4
bbsi.l a0, 30, 2f // branch if called with call12
call8 .L__wdwspill_assist16 // called with call8, only need another 8
retw
1: call12 .L__wdwspill_assist16 // called with call4, only need another 12
retw
2: call4 .L__wdwspill_assist16 // called with call12, only need another 4
retw
# elif XCHAL_NUM_AREGS == 64
entry sp, 48
bbci.l a0, 31, 1f // branch if called with call4
bbsi.l a0, 30, 2f // branch if called with call12
call4 .L__wdwspill_assist52 // called with call8, only need a call4
retw
1: call8 .L__wdwspill_assist52 // called with call4, only need a call8
retw
2: call12 .L__wdwspill_assist40 // called with call12, can skip a call12
retw
# elif XCHAL_NUM_AREGS == 16
entry sp, 16
bbci.l a0, 31, 1f // branch if called with call4
bbsi.l a0, 30, 2f // branch if called with call12
movi a7, 0 // called with call8
retw
1: movi a11, 0 // called with call4
2: retw // if called with call12, everything already spilled
// movi a15, 0 // trick to spill all but the direct caller
// j 1f
// // The entry instruction is magical in the assembler (gets auto-aligned)
// // so we have to jump to it to avoid falling through the padding.
// // We need entry/retw to know where to return.
//1: entry sp, 16
// retw
# else
# error "unrecognized address register file size"
# endif
#endif /* XCHAL_HAVE_WINDOWED */
window_spill_common
.endm // window_spill_function
/*----------------------------------------------------------------------
* window_spill_common
*
* Common code used by any number of invocations of the window_spill##
* and window_spill_function macros.
*
* Must be instantiated exactly once within a given assembly unit,
* within call/j range of and same section as window_spill##
* macro invocations for that assembly unit.
* (Is automatically instantiated by the window_spill_function macro.)
*/
.macro window_spill_common
#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
.ifndef .L__wdwspill_defined
# if XCHAL_NUM_AREGS >= 64
.L__wdwspill_assist60:
entry sp, 32
call8 .L__wdwspill_assist52
retw
.L__wdwspill_assist56:
entry sp, 16
call4 .L__wdwspill_assist52
retw
.L__wdwspill_assist52:
entry sp, 48
call12 .L__wdwspill_assist40
retw
.L__wdwspill_assist40:
entry sp, 48
call12 .L__wdwspill_assist28
retw
# endif
.L__wdwspill_assist28:
entry sp, 48
call12 .L__wdwspill_assist16
retw
.L__wdwspill_assist24:
entry sp, 32
call8 .L__wdwspill_assist16
retw
.L__wdwspill_assist20:
entry sp, 16
call4 .L__wdwspill_assist16
retw
.L__wdwspill_assist16:
entry sp, 16
movi a15, 0
retw
.set .L__wdwspill_defined, 1
.endif
#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
.endm // window_spill_common
/*----------------------------------------------------------------------
* beqi32
*
* macro implements version of beqi for arbitrary 32-bit immediate value
*
* beqi32 ax, ay, imm32, label
*
* Compares value in register ax with imm32 value and jumps to label if
* equal. Clobbers register ay if needed
*
*/
.macro beqi32 ax, ay, imm, label
.ifeq ((\imm-1) & ~7) // 1..8 ?
beqi \ax, \imm, \label
.else
.ifeq (\imm+1) // -1 ?
beqi \ax, \imm, \label
.else
.ifeq (\imm) // 0 ?
beqz \ax, \label
.else
// We could also handle immediates 10,12,16,32,64,128,256
// but it would be a long macro...
movi \ay, \imm
beq \ax, \ay, \label
.endif
.endif
.endif
.endm // beqi32
/*----------------------------------------------------------------------
* isync_retw_nop
*
* This macro must be invoked immediately after ISYNC if ISYNC
* would otherwise be immediately followed by RETW (or other instruction
* modifying WindowBase or WindowStart), in a context where
* kernel vector mode may be selected, and level-one interrupts
* and window overflows may be enabled, on an XEA1 configuration.
*
* On hardware with erratum "XEA1KWIN" (see <xtensa/core.h> for details),
* XEA1 code must have at least one instruction between ISYNC and RETW if
* run in kernel vector mode with interrupts and window overflows enabled.
*/
.macro isync_retw_nop
#if XCHAL_MAYHAVE_ERRATUM_XEA1KWIN
nop
#endif
.endm
/*----------------------------------------------------------------------
* isync_erratum453
*
* This macro must be invoked at certain points in the code,
* such as in exception and interrupt vectors in particular,
* to work around erratum 453.
*/
.macro isync_erratum453
#if XCHAL_ERRATUM_453
isync
#endif
.endm
/*----------------------------------------------------------------------
* abs
*
* implements abs on machines that do not have it configured
*/
#if !XCHAL_HAVE_ABS
.macro abs arr, ars
.ifc \arr, \ars
//src equal dest is less efficient
bgez \arr, 1f
neg \arr, \arr
1:
.else
neg \arr, \ars
movgez \arr, \ars, \ars
.endif
.endm
#endif /* !XCHAL_HAVE_ABS */
/*----------------------------------------------------------------------
* addx2
*
* implements addx2 on machines that do not have it configured
*
*/
#if !XCHAL_HAVE_ADDX
.macro addx2 arr, ars, art
.ifc \arr, \art
.ifc \arr, \ars
// addx2 a, a, a (not common)
.err
.else
add \arr, \ars, \art
add \arr, \ars, \art
.endif
.else
//addx2 a, b, c
//addx2 a, a, b
//addx2 a, b, b
slli \arr, \ars, 1
add \arr, \arr, \art
.endif
.endm
#endif /* !XCHAL_HAVE_ADDX */
/*----------------------------------------------------------------------
* addx4
*
* implements addx4 on machines that do not have it configured
*
*/
#if !XCHAL_HAVE_ADDX
.macro addx4 arr, ars, art
.ifc \arr, \art
.ifc \arr, \ars
// addx4 a, a, a (not common)
.err
.else
//# addx4 a, b, a
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
.endif
.else
//addx4 a, b, c
//addx4 a, a, b
//addx4 a, b, b
slli \arr, \ars, 2
add \arr, \arr, \art
.endif
.endm
#endif /* !XCHAL_HAVE_ADDX */
/*----------------------------------------------------------------------
* addx8
*
* implements addx8 on machines that do not have it configured
*
*/
#if !XCHAL_HAVE_ADDX
.macro addx8 arr, ars, art
.ifc \arr, \art
.ifc \arr, \ars
//addx8 a, a, a (not common)
.err
.else
//addx8 a, b, a
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
.endif
.else
//addx8 a, b, c
//addx8 a, a, b
//addx8 a, b, b
slli \arr, \ars, 3
add \arr, \arr, \art
.endif
.endm
#endif /* !XCHAL_HAVE_ADDX */
/*----------------------------------------------------------------------
* rfe_rfue
*
* Maps to RFUE on XEA1, and RFE on XEA2. No mapping on XEAX.
*/
#if XCHAL_HAVE_XEA1
.macro rfe_rfue
rfue
.endm
#elif XCHAL_HAVE_XEA2
.macro rfe_rfue
rfe
.endm
#endif
/*----------------------------------------------------------------------
* abi_entry
*
* Generate proper function entry sequence for the current ABI
* (windowed or call0). Takes care of allocating stack space (up to 1kB)
* and saving the return PC, if necessary. The corresponding abi_return
* macro does the corresponding stack deallocation and restoring return PC.
*
* Parameters are:
*
* locsize Number of bytes to allocate on the stack
* for local variables (and for args to pass to
* callees, if any calls are made). Defaults to zero.
* The macro rounds this up to a multiple of 16.
* NOTE: large values are allowed (e.g. up to 1 GB).
*
* callsize Maximum call size made by this function.
* Leave zero (default) for leaf functions, i.e. if
* this function makes no calls to other functions.
* Otherwise must be set to 4, 8, or 12 according
* to whether the "largest" call made is a call[x]4,
* call[x]8, or call[x]12 (for call0 ABI, it makes
* no difference whether this is set to 4, 8 or 12,
* but it must be set to one of these values).
*
* NOTE: It is up to the caller to align the entry point, declare the
* function symbol, make it global, etc.
*
* NOTE: This macro relies on assembler relaxation for large values
* of locsize. It might not work with the no-transform directive.
* NOTE: For the call0 ABI, this macro ensures SP is allocated or
* de-allocated cleanly, i.e. without temporarily allocating too much
* (or allocating negatively!) due to addi relaxation.
*
* NOTE: Generating the proper sequence and register allocation for
* making calls in an ABI independent manner is a separate topic not
* covered by this macro.
*
* NOTE: To access arguments, you can't use a fixed offset from SP.
* The offset depends on the ABI, whether the function is leaf, etc.
* The simplest method is probably to use the .locsz symbol, which
* is set by this macro to the actual number of bytes allocated on
* the stack, in other words, to the offset from SP to the arguments.
* E.g. for a function whose arguments are all 32-bit integers, you
* can get the 7th and 8th arguments (1st and 2nd args stored on stack)
* using:
* l32i a2, sp, .locsz
* l32i a3, sp, .locsz+4
* (this example works as long as locsize is under L32I's offset limit
* of 1020 minus up to 48 bytes of ABI-specific stack usage;
* otherwise you might first need to do "addi a?, sp, .locsz"
* or similar sequence).
*
* NOTE: For call0 ABI, this macro (and abi_return) may clobber a9
* (a caller-saved register).
*
* Examples:
* abi_entry
* abi_entry 5
* abi_entry 22, 8
* abi_entry 0, 4
*/
/*
* Compute .locsz and .callsz without emitting any instructions.
* Used by both abi_entry and abi_return.
* Assumes locsize >= 0.
*/
.macro abi_entry_size locsize=0, callsize=0
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
.ifeq \callsize
.set .callsz, 16
.else
.ifeq \callsize-4
.set .callsz, 16
.else
.ifeq \callsize-8
.set .callsz, 32
.else
.ifeq \callsize-12
.set .callsz, 48
.else
.error "abi_entry: invalid call size \callsize"
.endif
.endif
.endif
.endif
.set .locsz, .callsz + ((\locsize + 15) & -16)
#else
.set .callsz, \callsize
.if .callsz /* if calls, need space for return PC */
.set .locsz, (\locsize + 4 + 15) & -16
.else
.set .locsz, (\locsize + 15) & -16
.endif
#endif
.endm
.macro abi_entry locsize=0, callsize=0
.iflt \locsize
.error "abi_entry: invalid negative size of locals (\locsize)"
.endif
abi_entry_size \locsize, \callsize
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
.ifgt .locsz - 32760 /* .locsz > 32760 (ENTRY's max range)? */
/* Funky computation to try to have assembler use addmi efficiently if possible: */
entry sp, 0x7F00 + (.locsz & 0xF0)
addi a12, sp, - ((.locsz & -0x100) - 0x7F00)
movsp sp, a12
.else
entry sp, .locsz
.endif
#else
.if .locsz
.ifle .locsz - 128 /* if locsz <= 128 */
addi sp, sp, -.locsz
.if .callsz
s32i a0, sp, .locsz - 4
.endif
.elseif .callsz /* locsz > 128, with calls: */
movi a9, .locsz - 16 /* note: a9 is caller-saved */
addi sp, sp, -16
s32i a0, sp, 12
sub sp, sp, a9
.else /* locsz > 128, no calls: */
movi a9, .locsz
sub sp, sp, a9
.endif /* end */
.endif
#endif
.endm
/*----------------------------------------------------------------------
* abi_return
*
* Generate proper function exit sequence for the current ABI
* (windowed or call0). Takes care of freeing stack space and
* restoring the return PC, if necessary.
* NOTE: This macro MUST be invoked following a corresponding
* abi_entry macro invocation. For call0 ABI in particular,
* all stack and PC restoration are done according to the last
* abi_entry macro invoked before this macro in the assembly file.
*
* Normally this macro takes no arguments. However to allow
* for placing abi_return *before* abi_entry (as must be done
* for some highly optimized assembly), it optionally takes
* exactly the same arguments as abi_entry.
*/
.macro abi_return locsize=-1, callsize=0
.ifge \locsize
abi_entry_size \locsize, \callsize
.endif
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
retw
#else
.if .locsz
.iflt .locsz - 128 /* if locsz < 128 */
.if .callsz
l32i a0, sp, .locsz - 4
.endif
addi sp, sp, .locsz
.elseif .callsz /* locsz >= 128, with calls: */
addi a9, sp, .locsz - 16
l32i a0, a9, 12
addi sp, a9, 16
.else /* locsz >= 128, no calls: */
movi a9, .locsz
add sp, sp, a9
.endif /* end */
.endif
ret
#endif
.endm
/*
* HW erratum fixes.
*/
.macro hw_erratum_487_fix
#if defined XSHAL_ERRATUM_487_FIX
isync
#endif
.endm
#endif /*XTENSA_COREASM_H*/

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tools/sdk/include/esp32/xtensa/corebits.h
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@ -1,185 +0,0 @@
/*
* xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
*
* (In previous releases, these were defined in specreg.h, a generated file.
* This file is not generated, ie. it is processor configuration independent.)
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/corebits.h#2 $ */
/*
* Copyright (c) 2005-2011 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_COREBITS_H
#define XTENSA_COREBITS_H
/* EXCCAUSE register fields: */
#define EXCCAUSE_EXCCAUSE_SHIFT 0
#define EXCCAUSE_EXCCAUSE_MASK 0x3F
/* EXCCAUSE register values: */
/*
* General Exception Causes
* (values of EXCCAUSE special register set by general exceptions,
* which vector to the user, kernel, or double-exception vectors).
*/
#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
/* Reserved 10..11 */
#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
/* Reserved 21..23 */
#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
/* Reserved 30..31 */
#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
/* Reserved 40..63 */
/* PS register fields: */
#define PS_WOE_SHIFT 18
#define PS_WOE_MASK 0x00040000
#define PS_WOE PS_WOE_MASK
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_MASK 0x00030000
#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
#define PS_OWB_SHIFT 8
#define PS_OWB_MASK 0x00000F00
#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
#define PS_RING_SHIFT 6
#define PS_RING_MASK 0x000000C0
#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
#define PS_UM_SHIFT 5
#define PS_UM_MASK 0x00000020
#define PS_UM PS_UM_MASK
#define PS_EXCM_SHIFT 4
#define PS_EXCM_MASK 0x00000010
#define PS_EXCM PS_EXCM_MASK
#define PS_INTLEVEL_SHIFT 0
#define PS_INTLEVEL_MASK 0x0000000F
#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
/* Backward compatibility (deprecated): */
#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
#define PS_PROGSTACK_MASK PS_UM_MASK
#define PS_PROG_SHIFT PS_UM_SHIFT
#define PS_PROG_MASK PS_UM_MASK
#define PS_PROG PS_UM
/* DBREAKCn register fields: */
#define DBREAKC_MASK_SHIFT 0
#define DBREAKC_MASK_MASK 0x0000003F
#define DBREAKC_LOADBREAK_SHIFT 30
#define DBREAKC_LOADBREAK_MASK 0x40000000
#define DBREAKC_STOREBREAK_SHIFT 31
#define DBREAKC_STOREBREAK_MASK 0x80000000
/* DEBUGCAUSE register fields: */
#define DEBUGCAUSE_DEBUGINT_SHIFT 5
#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
#define DEBUGCAUSE_BREAKN_SHIFT 4
#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
#define DEBUGCAUSE_BREAK_SHIFT 3
#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
#define DEBUGCAUSE_DBREAK_SHIFT 2
#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
#define DEBUGCAUSE_IBREAK_SHIFT 1
#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
#define DEBUGCAUSE_ICOUNT_SHIFT 0
#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
/* MESR register fields: */
#define MESR_MEME 0x00000001 /* memory error */
#define MESR_MEME_SHIFT 0
#define MESR_DME 0x00000002 /* double memory error */
#define MESR_DME_SHIFT 1
#define MESR_RCE 0x00000010 /* recorded memory error */
#define MESR_RCE_SHIFT 4
#define MESR_LCE
#define MESR_LCE_SHIFT ?
#define MESR_LCE_L
#define MESR_ERRENAB 0x00000100
#define MESR_ERRENAB_SHIFT 8
#define MESR_ERRTEST 0x00000200
#define MESR_ERRTEST_SHIFT 9
#define MESR_DATEXC 0x00000400
#define MESR_DATEXC_SHIFT 10
#define MESR_INSEXC 0x00000800
#define MESR_INSEXC_SHIFT 11
#define MESR_WAYNUM_SHIFT 16
#define MESR_ACCTYPE_SHIFT 20
#define MESR_MEMTYPE_SHIFT 24
#define MESR_ERRTYPE_SHIFT 30
/* MEMCTL register fields: */
#define MEMCTL_SNOOP_EN_SHIFT 1
#define MEMCTL_SNOOP_EN 0x02 /* enable snoop responses (default 0) */
#define MEMCTL_L0IBUF_EN_SHIFT 0
#define MEMCTL_L0IBUF_EN 0x01 /* enable loop instr. buffer (default 1) */
#define MEMCTL_INV_EN_SHIFT 23
#define MEMCTL_INV_EN 0x00800000 /* invalidate cache ways being increased */
#define MEMCTL_DCWU_SHIFT 8
#define MEMCTL_DCWU_BITS 5
#define MEMCTL_DCWA_SHIFT 13
#define MEMCTL_DCWA_BITS 5
#define MEMCTL_ICWU_SHIFT 18
#define MEMCTL_ICWU_BITS 5
#define MEMCTL_DCWU_MASK 0x00001F00 /* Bits 8-12 dcache ways in use */
#define MEMCTL_DCWA_MASK 0x0003E000 /* Bits 13-17 dcache ways allocatable */
#define MEMCTL_ICWU_MASK 0x007C0000 /* Bits 18-22 icache ways in use */
#define MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK)
#define MEMCTL_DCWA_CLR_MASK ~(MEMCTL_DCWA_MASK)
#define MEMCTL_ICWU_CLR_MASK ~(MEMCTL_ICWU_MASK)
#define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
#define MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
#endif /*XTENSA_COREBITS_H*/

1024
tools/sdk/include/esp32/xtensa/hal.h
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143
tools/sdk/include/esp32/xtensa/specreg.h
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@ -1,143 +0,0 @@
/*
* Xtensa Special Register symbolic names
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/specreg.h#2 $ */
/*
* Copyright (c) 2005-2011 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define LITBASE 5
#define SCOMPARE1 12
#define ACCLO 16
#define ACCHI 17
#define MR_0 32
#define MR_1 33
#define MR_2 34
#define MR_3 35
#define PREFCTL 40
#define WINDOWBASE 72
#define WINDOWSTART 73
#define PTEVADDR 83
#define RASID 90
#define ITLBCFG 91
#define DTLBCFG 92
#define IBREAKENABLE 96
#define MEMCTL 97
#define CACHEATTR 98
#define ATOMCTL 99
#define DDR 104
#define MECR 110
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define CONFIGID0 176
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define EPC_5 181
#define EPC_6 182
#define EPC_7 183
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EPS_5 197
#define EPS_6 198
#define EPS_7 199
#define CONFIGID1 208
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define EXCSAVE_5 213
#define EXCSAVE_6 214
#define EXCSAVE_7 215
#define CPENABLE 224
#define INTERRUPT 226
#define INTREAD INTERRUPT /* alternate name for backward compatibility */
#define INTSET INTERRUPT /* alternate name for backward compatibility */
#define INTCLEAR 227
#define INTENABLE 228
#define PS 230
#define VECBASE 231
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
#define MISC_REG_2 246
#define MISC_REG_3 247
/* Special cases (bases of special register series): */
#define MR 32
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
#define MISC_REG 244
/* Tensilica-defined user registers: */
#if 0
/*#define ... 21..24 */ /* (545CK) */
/*#define ... 140..143 */ /* (545CK) */
#define EXPSTATE 230 /* Diamond */
#define THREADPTR 231 /* threadptr option */
#define FCR 232 /* FPU */
#define FSR 233 /* FPU */
#define AE_OVF_SAR 240 /* HiFi2 */
#define AE_BITHEAD 241 /* HiFi2 */
#define AE_TS_FTS_BU_BP 242 /* HiFi2 */
#define AE_SD_NO 243 /* HiFi2 */
#define VSAR 240 /* VectraLX */
#define ROUND_LO 242 /* VectraLX */
#define ROUND_HI 243 /* VectraLX */
#define CBEGIN 246 /* VectraLX */
#define CEND 247 /* VectraLX */
#endif
#endif /* XTENSA_SPECREG_H */

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tools/sdk/include/esp32/xtensa/traxreg.h
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/* TRAX register definitions
Copyright (c) 2006-2012 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _TRAX_REGISTERS_H_
#define _TRAX_REGISTERS_H_
#define SHOW 1
#define HIDE 0
#define RO 0
#define RW 1
/* TRAX Register Numbers (from possible range of 0..127) */
#if 0
#define TRAXREG_ID 0
#define TRAXREG_CONTROL 1
#define TRAXREG_STATUS 2
#define TRAXREG_DATA 3
#define TRAXREG_ADDRESS 4
#define TRAXREG_TRIGGER 5
#define TRAXREG_MATCH 6
#define TRAXREG_DELAY 7
#define TRAXREG_STARTADDR 8
#define TRAXREG_ENDADDR 9
/* Internal use only (unpublished): */
#define TRAXREG_P4CHANGE 16
#define TRAXREG_P4REV 17
#define TRAXREG_P4DATE 18
#define TRAXREG_P4TIME 19
#define TRAXREG_PDSTATUS 20
#define TRAXREG_PDDATA 21
#define TRAXREG_STOP_PC 22
#define TRAXREG_STOP_ICNT 23
#define TRAXREG_MSG_STATUS 24
#define TRAXREG_FSM_STATUS 25
#define TRAXREG_IB_STATUS 26
#define TRAXREG_MAX 27
#define TRAXREG_ITCTRL 96
#endif
/* The registers above match the NAR addresses. So, their values are used for NAR access */
/* TRAX Register Fields */
/* TRAX ID register fields: */
#define TRAX_ID_PRODNO 0xf0000000 /* product number (0=TRAX) */
#define TRAX_ID_PRODOPT 0x0f000000 /* product options */
#define TRAX_ID_MIW64 0x08000000 /* opt: instruction width */
#define TRAX_ID_AMTRAX 0x04000000 /* opt: collection of options,
internal (VER_2_0 or later)*/
#define TRAX_ID_MAJVER(id) (((id) >> 20) & 0x0f)
#define TRAX_ID_MINVER(id) (((id) >> 17) & 0x07)
#define TRAX_ID_VER(id) ((TRAX_ID_MAJVER(id)<<4)|TRAX_ID_MINVER(id))
#define TRAX_ID_STDCFG 0x00010000 /* standard config */
#define TRAX_ID_CFGID 0x0000ffff /* TRAX configuration ID */
#define TRAX_ID_MEMSHARED 0x00001000 /* Memshared option in TRAX */
#define TRAX_ID_FROM_VER(ver) ((((ver) & 0xf0) << 16) | (((ver) & 0x7) << 17))
/* Other TRAX ID register macros: */
/* TRAX versions of interest (TRAX_ID_VER(), ie. MAJVER*16 + MINVER): */
#define TRAX_VER_1_0 0x10 /* RA */
#define TRAX_VER_1_1 0x11 /* RB thru RC-2010.1 */
#define TRAX_VER_2_0 0x20 /* RC-2010.2, RD-2010.0,
RD-2011.1 */
#define TRAX_VER_2_1 0x21 /* RC-2011.3 / RD-2011.2 and
later */
#define TRAX_VER_3_0 0x30 /* RE-2012.0 */
#define TRAX_VER_3_1 0x31 /* RE-2012.1 */
#define TRAX_VER_HUAWEI_3 TRAX_VER_3_0 /* For Huawei, PRs: 25223, 25224
, 24880 */
/* TRAX version 1.0 requires a couple software workarounds: */
#define TRAX_ID_1_0_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_1_0)
/* TRAX version 2.0 requires software workaround for PR 22161: */
#define TRAX_ID_MEMSZ_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_2_0)
/* TRAX Control register fields: */
#define TRAX_CONTROL_TREN 0x00000001
#define TRAX_CONTROL_TRSTP 0x00000002
#define TRAX_CONTROL_PCMEN 0x00000004
#define TRAX_CONTROL_PTIEN 0x00000010
#define TRAX_CONTROL_CTIEN 0x00000020
#define TRAX_CONTROL_TMEN 0x00000080 /* 2.0+ */
#define TRAX_CONTROL_CNTU 0x00000200
#define TRAX_CONTROL_BIEN 0x00000400
#define TRAX_CONTROL_BOEN 0x00000800
#define TRAX_CONTROL_TSEN 0x00000800
#define TRAX_CONTROL_SMPER 0x00007000
#define TRAX_CONTROL_SMPER_SHIFT 12
#define TRAX_CONTROL_PTOWT 0x00010000
#define TRAX_CONTROL_CTOWT 0x00020000
#define TRAX_CONTROL_PTOWS 0x00100000
#define TRAX_CONTROL_CTOWS 0x00200000
#define TRAX_CONTROL_ATID 0x7F000000 /* 2.0+, amtrax */
#define TRAX_CONTROL_ATID_SHIFT 24
#define TRAX_CONTROL_ATEN 0x80000000 /* 2.0+, amtrax */
#define TRAX_CONTROL_PTOWS_ER 0x00020000 /* For 3.0 */
#define TRAX_CONTROL_CTOWT_ER 0x00100000 /* For 3.0 */
#define TRAX_CONTROL_ITCTO 0x00400000 /* For 3.0 */
#define TRAX_CONTROL_ITCTIA 0x00800000 /* For 3.0 */
#define TRAX_CONTROL_ITATV 0x01000000 /* For 3.0 */
/* TRAX Status register fields: */
#define TRAX_STATUS_TRACT 0x00000001
#define TRAX_STATUS_TRIG 0x00000002
#define TRAX_STATUS_PCMTG 0x00000004
#define TRAX_STATUS_BUSY 0x00000008 /* ER ??? */
#define TRAX_STATUS_PTITG 0x00000010
#define TRAX_STATUS_CTITG 0x00000020
#define TRAX_STATUS_MEMSZ 0x00001F00
#define TRAX_STATUS_MEMSZ_SHIFT 8
#define TRAX_STATUS_PTO 0x00010000
#define TRAX_STATUS_CTO 0x00020000
#define TRAX_STATUS_ITCTOA 0x00400000 /* For 3.0 */
#define TRAX_STATUS_ITCTI 0x00800000 /* For 3.0 */
#define TRAX_STATUS_ITATR 0x01000000 /* For 3.0 */
/* TRAX Address register fields: */
#define TRAX_ADDRESS_TWSAT 0x80000000
#define TRAX_ADDRESS_TWSAT_SHIFT 31
#define TRAX_ADDRESS_TOTALMASK 0x00FFFFFF
// !!! VUakiVU. added for new TRAX:
#define TRAX_ADDRESS_WRAPCNT 0x7FE00000 /* version ???... */
#define TRAX_ADDRESS_WRAP_SHIFT 21
/* TRAX PCMatch register fields: */
#define TRAX_PCMATCH_PCML 0x0000001F
#define TRAX_PCMATCH_PCML_SHIFT 0
#define TRAX_PCMATCH_PCMS 0x80000000
/* Compute trace ram buffer size (in bytes) from status register: */
#define TRAX_MEM_SIZE(status) (1L << (((status) & TRAX_STATUS_MEMSZ) >> TRAX_STATUS_MEMSZ_SHIFT))
#if 0
/* Describes a field within a register: */
typedef struct {
const char* name;
// unsigned width;
// unsigned shift;
char width;
char shift;
char visible; /* 0 = internal use only, 1 = shown */
char reserved;
} trax_regfield_t;
#endif
/* Describes a TRAX register: */
typedef struct {
const char* name;
unsigned id;
char width;
char visible;
char writable;
char reserved;
//const trax_regfield_t * fieldset;
} trax_regdef_t;
extern const trax_regdef_t trax_reglist[];
extern const signed char trax_readable_regs[];
#ifdef __cplusplus
extern "C" {
#endif
/* Prototypes: */
extern int trax_find_reg(char * regname, char **errmsg);
extern const char * trax_regname(int regno);
#ifdef __cplusplus
}
#endif
#endif /* _TRAX_REGISTERS_H_ */

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tools/sdk/include/esp32/xtensa/xdm-regs.h
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@ -1,530 +0,0 @@
/* xdm-regs.h - Common register and related definitions for the XDM
(Xtensa Debug Module) */
/* Copyright (c) 2011-2012 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XDM_REGS_H_
#define _XDM_REGS_H_
/* NOTE: This header file is included by C, assembler, and other sources.
So any C-specific or asm-specific content must be appropriately #ifdef'd. */
/*
* XDM registers can be accessed using APB, ERI, or JTAG (via NAR).
* Address offsets for APB and ERI are the same, and for JTAG
* is different (due to the limited 7-bit NAR addressing).
*
* Here, we first provide the constants as APB / ERI address offsets.
* This is necessary for assembler code (which accesses XDM via ERI),
* because complex conversion macros between the two address maps
* don't work in the assembler.
* Conversion macros are used to convert these to/from JTAG (NAR),
* addresses, for software using JTAG.
*/
/* FIXME: maybe provide only MISC+CS registers here, and leave specific
subsystem registers in separate headers? eg. for TRAX, PERF, OCD */
/* XDM_.... ERI addr [NAR addr] Description...... */
/* TRAX */
#define XDM_TRAX_ID 0x0000 /*[0x00] ID */
#define XDM_TRAX_CONTROL 0x0004 /*[0x01] Control */
#define XDM_TRAX_STATUS 0x0008 /*[0x02] Status */
#define XDM_TRAX_DATA 0x000C /*[0x03] Data */
#define XDM_TRAX_ADDRESS 0x0010 /*[0x04] Address */
#define XDM_TRAX_TRIGGER 0x0014 /*[0x05] Stop PC */
#define XDM_TRAX_MATCH 0x0018 /*[0x06] Stop PC Range */
#define XDM_TRAX_DELAY 0x001C /*[0x07] Post Stop Trigger Capture Size */
#define XDM_TRAX_STARTADDR 0x0020 /*[0x08] Trace Memory Start */
#define XDM_TRAX_ENDADDR 0x0024 /*[0x09] Trace Memory End */
#define XDM_TRAX_DEBUGPC 0x003C /*[0x0F] Debug PC */
#define XDM_TRAX_P4CHANGE 0x0040 /*[0x10] X */
#define XDM_TRAX_TIME0 0x0040 /*[0x10] First Time Register */
#define XDM_TRAX_P4REV 0x0044 /*[0x11] X */
#define XDM_TRAX_TIME1 0x0044 /*[0x11] Second Time Register */
#define XDM_TRAX_P4DATE 0x0048 /*[0x12] X */
#define XDM_TRAX_INTTIME_MAX 0x0048 /*[0x12] maximal Value of Timestamp IntTime */
#define XDM_TRAX_P4TIME 0x004C /*[0x13] X */
#define XDM_TRAX_PDSTATUS 0x0050 /*[0x14] Sample of PDebugStatus */
#define XDM_TRAX_PDDATA 0x0054 /*[0x15] Sample of PDebugData */
#define XDM_TRAX_STOP_PC 0x0058 /*[0x16] X */
#define XDM_TRAX_STOP_ICNT 0x005C /*[0x16] X */
#define XDM_TRAX_MSG_STATUS 0x0060 /*[0x17] X */
#define XDM_TRAX_FSM_STATUS 0x0064 /*[0x18] X */
#define XDM_TRAX_IB_STATUS 0x0068 /*[0x19] X */
#define XDM_TRAX_STOPCNT 0x006C /*[0x1A] X */
/* Performance Monitoring Counters */
#define XDM_PERF_PMG 0x1000 /*[0x20] perf. mon. global control register */
#define XDM_PERF_INTPC 0x1010 /*[0x24] perf. mon. interrupt PC */
#define XDM_PERF_PM0 0x1080 /*[0x28] perf. mon. counter 0 value */
#define XDM_PERF_PM1 0x1084 /*[0x29] perf. mon. counter 1 value */
#define XDM_PERF_PM2 0x1088 /*[0x2A] perf. mon. counter 2 value */
#define XDM_PERF_PM3 0x108C /*[0x2B] perf. mon. counter 3 value */
#define XDM_PERF_PM4 0x1090 /*[0x2C] perf. mon. counter 4 value */
#define XDM_PERF_PM5 0x1094 /*[0x2D] perf. mon. counter 5 value */
#define XDM_PERF_PM6 0x1098 /*[0x2E] perf. mon. counter 6 value */
#define XDM_PERF_PM7 0x109C /*[0x2F] perf. mon. counter 7 value */
#define XDM_PERF_PM(n) (0x1080+((n)<<2)) /* perfmon cnt n=0..7 value */
#define XDM_PERF_PMCTRL0 0x1100 /*[0x30] perf. mon. counter 0 control */
#define XDM_PERF_PMCTRL1 0x1104 /*[0x31] perf. mon. counter 1 control */
#define XDM_PERF_PMCTRL2 0x1108 /*[0x32] perf. mon. counter 2 control */
#define XDM_PERF_PMCTRL3 0x110C /*[0x33] perf. mon. counter 3 control */
#define XDM_PERF_PMCTRL4 0x1110 /*[0x34] perf. mon. counter 4 control */
#define XDM_PERF_PMCTRL5 0x1114 /*[0x35] perf. mon. counter 5 control */
#define XDM_PERF_PMCTRL6 0x1118 /*[0x36] perf. mon. counter 6 control */
#define XDM_PERF_PMCTRL7 0x111C /*[0x37] perf. mon. counter 7 control */
#define XDM_PERF_PMCTRL(n) (0x1100+((n)<<2)) /* perfmon cnt n=0..7 control */
#define XDM_PERF_PMSTAT0 0x1180 /*[0x38] perf. mon. counter 0 status */
#define XDM_PERF_PMSTAT1 0x1184 /*[0x39] perf. mon. counter 1 status */
#define XDM_PERF_PMSTAT2 0x1188 /*[0x3A] perf. mon. counter 2 status */
#define XDM_PERF_PMSTAT3 0x118C /*[0x3B] perf. mon. counter 3 status */
#define XDM_PERF_PMSTAT4 0x1190 /*[0x3C] perf. mon. counter 4 status */
#define XDM_PERF_PMSTAT5 0x1194 /*[0x3D] perf. mon. counter 5 status */
#define XDM_PERF_PMSTAT6 0x1198 /*[0x3E] perf. mon. counter 6 status */
#define XDM_PERF_PMSTAT7 0x119C /*[0x3F] perf. mon. counter 7 status */
#define XDM_PERF_PMSTAT(n) (0x1180+((n)<<2)) /* perfmon cnt n=0..7 status */
/* On-Chip-Debug (OCD) */
#define XDM_OCD_ID 0x2000 /*[0x40] ID register */
#define XDM_OCD_DCR_CLR 0x2008 /*[0x42] Debug Control reg clear */
#define XDM_OCD_DCR_SET 0x200C /*[0x43] Debug Control reg set */
#define XDM_OCD_DSR 0x2010 /*[0x44] Debug Status reg */
#define XDM_OCD_DDR 0x2014 /*[0x45] Debug Data reg */
#define XDM_OCD_DDREXEC 0x2018 /*[0x46] Debug Data reg + execute-DIR */
#define XDM_OCD_DIR0EXEC 0x201C /*[0x47] Debug Instruction reg, word 0 + execute-DIR */
#define XDM_OCD_DIR0 0x2020 /*[0x48] Debug Instruction reg, word 1 */
#define XDM_OCD_DIR1 0x2024 /*[0x49] Debug Instruction reg, word 2 */
#define XDM_OCD_DIR2 0x2028 /*[0x4A] Debug Instruction reg, word 3 */
#define XDM_OCD_DIR3 0x202C /*[0x49] Debug Instruction reg, word 4 */
#define XDM_OCD_DIR4 0x2030 /*[0x4C] Debug Instruction reg, word 5 */
#define XDM_OCD_DIR5 0x2034 /*[0x4D] Debug Instruction reg, word 5 */
#define XDM_OCD_DIR6 0x2038 /*[0x4E] Debug Instruction reg, word 6 */
#define XDM_OCD_DIR7 0x203C /*[0x4F] Debug Instruction reg, word 7 */
/* Miscellaneous Registers */
#define XDM_MISC_PWRCTL 0x3020 /*[0x58] Power and Reset Control */
#define XDM_MISC_PWRSTAT 0x3024 /*[0x59] Power and Reset Status */
#define XDM_MISC_ERISTAT 0x3028 /*[0x5A] ERI Transaction Status */
#define XDM_MISC_DATETIME 0x3034 /*[0x5D] [INTERNAL] Timestamps of build */
#define XDM_MISC_UBID 0x3038 /*[0x5E] [INTERNAL] Build Unique ID */
#define XDM_MISC_CID 0x303C /*[0x5F] [INTERNAL] Customer ID */
/* CoreSight compatibility */
#define XDM_CS_ITCTRL 0x3F00 /*[0x60] InTegration Mode control reg */
#define XDM_CS_CLAIMSET 0x3FA0 /*[0x68] Claim Tag Set reg */
#define XDM_CS_CLAIMCLR 0x3FA4 /*[0x69] Claim Tag Clear reg */
#define XDM_CS_LOCK_ACCESS 0x3FB0 /*[0x6B] Lock Access (writing 0xC5ACCE55 unlocks) */
#define XDM_CS_LOCK_STATUS 0x3FB4 /*[0x6D] Lock Status */
#define XDM_CS_AUTH_STATUS 0x3FB8 /*[0x6E] Authentication Status */
#define XDM_CS_DEV_ID 0x3FC8 /*[0x72] Device ID */
#define XDM_CS_DEV_TYPE 0x3FCC /*[0x73] Device Type */
#define XDM_CS_PER_ID4 0x3FD0 /*[0x74] Peripheral ID reg byte 4 */
#define XDM_CS_PER_ID5 0x3FD4 /*[0x75] Peripheral ID reg byte 5 */
#define XDM_CS_PER_ID6 0x3FD8 /*[0x76] Peripheral ID reg byte 6 */
#define XDM_CS_PER_ID7 0x3FDC /*[0x77] Peripheral ID reg byte 7 */
#define XDM_CS_PER_ID0 0x3FE0 /*[0x78] Peripheral ID reg byte 0 */
#define XDM_CS_PER_ID1 0x3FE4 /*[0x79] Peripheral ID reg byte 1 */
#define XDM_CS_PER_ID2 0x3FE8 /*[0x7A] Peripheral ID reg byte 2 */
#define XDM_CS_PER_ID3 0x3FEC /*[0x7B] Peripheral ID reg byte 3 */
#define XDM_CS_COMP_ID0 0x3FF0 /*[0x7C] Component ID reg byte 0 */
#define XDM_CS_COMP_ID1 0x3FF4 /*[0x7D] Component ID reg byte 1 */
#define XDM_CS_COMP_ID2 0x3FF8 /*[0x7E] Component ID reg byte 2 */
#define XDM_CS_COMP_ID3 0x3FFC /*[0x7F] Component ID reg byte 3 */
#define CS_PER_ID0 0x00000003
#define CS_PER_ID1 0x00000021
#define CS_PER_ID2 0x0000000f
#define CS_PER_ID3 0x00000000
#define CS_PER_ID4 0x00000024
#define CS_COMP_ID0 0x0000000d
#define CS_COMP_ID1 0x00000090
#define CS_COMP_ID2 0x00000005
#define CS_COMP_ID3 0x000000b1
#define CS_DEV_TYPE 0x00000015
#define XTENSA_IDCODE 0x120034e5 // FIXME (upper bits not spec. out but BE is !)
#define XTENSA_MFC_ID (XTENSA_IDCODE & 0xFFF)
#define CS_DEV_ID XTENSA_IDCODE
#define NXS_OCD_REG(val) ((val >= 0x40) && (val <= 0x5F))
#define NXS_TRAX_REG(val) val <= 0x3F
#define ERI_TRAX_REG(val) ((val & 0xFFFF) < 0x1000)
#define ERI_OCD_REG(val) ((val & 0xFFFF) >= 0x2000) && ((val & 0xFFFF) < 0x4000))
/* Convert above 14-bit ERI/APB address/offset to 7-bit NAR address: */
#define _XDM_ERI_TO_NAR(a) ( ((a)&0x3F80)==0x0000 ? (((a)>>2) & 0x1F) \
: ((a)&0x3E00)==0x1000 ? (0x20 | (((a)>>2) & 7) | (((a)>>4) & 0x18)) \
: ((a)&0x3FC0)==0x2000 ? (0x40 | (((a)>>2) & 0xF)) \
: ((a)&0x3FE0)==0x3020 ? (0x50 | (((a)>>2) & 0xF)) \
: ((a)&0x3FFC)==0x3F00 ? 0x60 \
: ((a)&0x3F80)==0x3F80 ? (0x60 | (((a)>>2) & 0x1F)) \
: -1 )
#define XDM_ERI_TO_NAR(a) _XDM_ERI_TO_NAR(a & 0xFFFF)
/* Convert 7-bit NAR address back to ERI/APB address/offset: */
#define _XDM_NAR_TO_APB(a) ((a) <= 0x1f ? ((a) << 2) \
:(a) >= 0x20 && (a) <= 0x3F ? (0x1000 | (((a)& 7) << 2) | (((a)&0x18)<<4)) \
:(a) >= 0x40 && (a) <= 0x4F ? (0x2000 | (((a)&0xF) << 2)) \
:(a) >= 0x58 && (a) <= 0x5F ? (0x3000 | (((a)&0xF) << 2)) \
:(a) == 0x60 ? (0x3F00) \
:(a) >= 0x68 && (a) <= 0x7F ? (0x3F80 | (((a)&0x1F) << 2)) \
: -1)
#define XDM_NAR_TO_APB(a) _XDM_NAR_TO_APB((a & 0xFFFF))
#define XDM_NAR_TO_ERI(a) _XDM_NAR_TO_APB((a & 0xFFFF)) | 0x000000
/* Convert APB to ERI address */
#define XDM_APB_TO_ERI(a) ((a) | (0x100000))
#define XDM_ERI_TO_APB(a) ((a) & (0x0FFFFF))
/*********** Bit definitions within some of the above registers ***********/
#define OCD_ID_LSDDRP 0x01000000
#define OCD_ID_LSDDRP_SHIFT 24
#define OCD_ID_ENDIANESS 0x00000001
#define OCD_ID_ENDIANESS_SHIFT 0
#define OCD_ID_PSO 0x0000000C
#define OCD_ID_PSO_SHIFT 2
#define OCD_ID_TRACEPORT 0x00000080
#define OCD_ID_TRACEPORT_SHIFT 7
/* Power Status register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
/* ERI/APB: */
#define PWRSTAT_CORE_DOMAIN_ON 0x00000001 /* set if core is powered on */
#define PWRSTAT_CORE_DOMAIN_ON_SHIFT 0
#define PWRSTAT_WAKEUP_RESET 0x00000002 /* [ERI only] 0=cold start, 1=PSO wakeup */
#define PWRSTAT_WAKEUP_RESET_SHIFT 1
#define PWRSTAT_CACHES_LOST_POWER 0x00000004 /* [ERI only] set if caches (/localmems?) lost power */
/* FIXME: does this include local memories? */
#define PWRSTAT_CACHES_LOST_POWER_SHIFT 2
#define PWRSTAT_CORE_STILL_NEEDED 0x00000010 /* set if others keeping core awake */
#define PWRSTAT_CORE_STILL_NEEDED_SHIFT 4
#define PWRSTAT_MEM_DOMAIN_ON 0x00000100 /* set if memory domain is powered on */
#define PWRSTAT_MEM_DOMAIN_ON_SHIFT 8
#define PWRSTAT_DEBUG_DOMAIN_ON 0x00001000 /* set if debug domain is powered on */
#define PWRSTAT_DEBUG_DOMAIN_ON_SHIFT 12
#define PWRSTAT_ALL_ON PWRSTAT_CORE_DOMAIN_ON | PWRSTAT_MEM_DOMAIN_ON | PWRSTAT_DEBUG_DOMAIN_ON
#define PWRSTAT_CORE_WAS_RESET 0x00010000 /* [APB only] set if core got reset */
#define PWRSTAT_CORE_WAS_RESET_SHIFT 16
#define PWRSTAT_DEBUG_WAS_RESET 0x10000000 /* set if debug module got reset */
#define PWRSTAT_DEBUG_WAS_RESET_SHIFT 28
/* JTAG: */
#define J_PWRSTAT_CORE_DOMAIN_ON 0x01 /* set if core is powered on */
#define J_PWRSTAT_MEM_DOMAIN_ON 0x02 /* set if memory domain is powered on */
#define J_PWRSTAT_DEBUG_DOMAIN_ON 0x04 /* set if debug domain is powered on */
#define J_PWRSTAT_ALL_ON J_PWRSTAT_CORE_DOMAIN_ON | J_PWRSTAT_MEM_DOMAIN_ON | J_PWRSTAT_DEBUG_DOMAIN_ON
#define J_PWRSTAT_CORE_STILL_NEEDED 0x08 /* set if others keeping core awake */
#define J_PWRSTAT_CORE_WAS_RESET 0x10 /* set if core got reset */
#define J_PWRSTAT_DEBUG_WAS_RESET 0x40 /* set if debug module got reset */
/* Power Control register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
/* ERI/APB: */
#define PWRCTL_CORE_SHUTOFF 0x00000001 /* [ERI only] core wants to shut off on WAITI */
#define PWRCTL_CORE_SHUTOFF_SHIFT 0
#define PWRCTL_CORE_WAKEUP 0x00000001 /* [APB only] set to force core to stay powered on */
#define PWRCTL_CORE_WAKEUP_SHIFT 0
#define PWRCTL_MEM_WAKEUP 0x00000100 /* set to force memory domain to stay powered on */
#define PWRCTL_MEM_WAKEUP_SHIFT 8
#define PWRCTL_DEBUG_WAKEUP 0x00001000 /* set to force debug domain to stay powered on */
#define PWRCTL_DEBUG_WAKEUP_SHIFT 12
#define PWRCTL_ALL_ON PWRCTL_CORE_WAKEUP | PWRCTL_MEM_WAKEUP | PWRCTL_DEBUG_WAKEUP
#define PWRCTL_CORE_RESET 0x00010000 /* [APB only] set to assert core reset */
#define PWRCTL_CORE_RESET_SHIFT 16
#define PWRCTL_DEBUG_RESET 0x10000000 /* set to assert debug module reset */
#define PWRCTL_DEBUG_RESET_SHIFT 28
/* JTAG: */
#define J_PWRCTL_CORE_WAKEUP 0x01 /* set to force core to stay powered on */
#define J_PWRCTL_MEM_WAKEUP 0x02 /* set to force memory domain to stay powered on */
#define J_PWRCTL_DEBUG_WAKEUP 0x04 /* set to force debug domain to stay powered on */
#define J_DEBUG_USE 0x80 /* */
#define J_PWRCTL_ALL_ON J_DEBUG_USE | J_PWRCTL_CORE_WAKEUP | J_PWRCTL_MEM_WAKEUP | J_PWRCTL_DEBUG_WAKEUP
#define J_PWRCTL_DEBUG_ON J_DEBUG_USE | J_PWRCTL_DEBUG_WAKEUP
#define J_PWRCTL_CORE_RESET 0x10 /* set to assert core reset */
#define J_PWRCTL_DEBUG_RESET 0x40 /* set to assert debug module reset */
#define J_PWRCTL_WRITE_MASK 0xFF
#define J_PWRSTAT_WRITE_MASK 0xFF
#define PWRCTL_WRITE_MASK ~0
#define PWRSTAT_WRITE_MASK ~0
/************ The following are only relevant for JTAG, so perhaps belong in OCD only **************/
/* XDM 5-bit JTAG Instruction Register (IR) values: */
#define XDM_IR_PWRCTL 0x08 /* select 8-bit Power/Reset Control (PRC) */
#define XDM_IR_PWRSTAT 0x09 /* select 8-bit Power/Reset Status (PRS) */
#define XDM_IR_NAR_SEL 0x1c /* select altern. 8-bit NAR / 32-bit NDR (Nexus-style) */
#define XDM_IR_NDR_SEL 0x1d /* select altern. 32-bit NDR / 8-bit NAR
(FIXME - functionality not yet in HW) */
#define XDM_IR_IDCODE 0x1e /* select 32-bit JTAG IDCODE */
#define XDM_IR_BYPASS 0x1f /* select 1-bit bypass */
#define XDM_IR_WIDTH 5 /* width of IR for Xtensa TAP */
/* NAR register bits: */
#define XDM_NAR_WRITE 0x01
#define XDM_NAR_ADDR_MASK 0xFE
#define XDM_NAR_ADDR_SHIFT 1
#define XDM_NAR_BUSY 0x02
#define XDM_NAR_ERROR 0x01
#define NEXUS_DIR_READ 0x00
#define NEXUS_DIR_WRITE 0x01
/************ Define DCR register bits **************/
#define DCR_ENABLEOCD 0x0000001
#define DCR_ENABLEOCD_SHIFT 0
#define DCR_DEBUG_INT 0x0000002
#define DCR_DEBUG_INT_SHIFT 1
#define DCR_DEBUG_OVERRIDE 0x0000004
#define DCR_DEBUG_OVERRIDE_SHIFT 2
#define DCR_DEBUG_INTERCEPT 0x0000008
#define DCR_DEBUG_INTERCEPT_SHIFT 3
#define DCR_MASK_NMI 0x0000020
#define DCR_MASK_NMI_SHIFT 5
#define DCR_STEP_ENABLE 0x0000040
#define DCR_STEP_ENABLE_SHIFT 6
#define DCR_BREAK_IN_EN 0x0010000
#define DCR_BREAK_IN_EN_SHIFT 16
#define DCR_BREAK_OUT_EN 0x0020000
#define DCR_BREAK_OUT_EN_SHIFT 17
#define DCR_DEBUG_INT_EN 0x0040000
#define DCR_DEBUG_INT_EN_SHIFT 18
#define DCR_DBG_SW_ACTIVE 0x0100000
#define DCR_DBG_SW_ACTIVE_SHIFT 20
#define DCR_STALL_IN_EN 0x0200000
#define DCR_STALL_IN_EN_SHIFT 21
#define DCR_DEBUG_OUT_EN 0x0400000
#define DCR_DEBUG_OUT_EN_SHIFT 22
#define DCR_BREAK_OUT_ITO 0x1000000
#define DCR_STALL_OUT_ITO 0x2000000
#define DCR_STALL_OUT_ITO_SHIFT 25
/************ Define DSR register bits **************/
#define DOSR_EXECDONE_ER 0x01
#define DOSR_EXECDONE_SHIFT 0
#define DOSR_EXCEPTION_ER 0x02
#define DOSR_EXCEPTION_SHIFT 1
#define DOSR_BUSY 0x04
#define DOSR_BUSY_SHIFT 2
#define DOSR_OVERRUN 0x08
#define DOSR_OVERRUN_SHIFT 3
#define DOSR_INOCDMODE_ER 0x10
#define DOSR_INOCDMODE_SHIFT 4
#define DOSR_CORE_WROTE_DDR_ER 0x400
#define DOSR_CORE_WROTE_DDR_SHIFT 10
#define DOSR_CORE_READ_DDR_ER 0x800
#define DOSR_CORE_READ_DDR_SHIFT 11
#define DOSR_HOST_WROTE_DDR_ER 0x4000
#define DOSR_HOST_WROTE_DDR_SHIFT 14
#define DOSR_HOST_READ_DDR_ER 0x8000
#define DOSR_HOST_READ_DDR_SHIFT 15
#define DOSR_DEBUG_PEND_BIN 0x10000
#define DOSR_DEBUG_PEND_HOST 0x20000
#define DOSR_DEBUG_PEND_TRAX 0x40000
#define DOSR_DEBUG_BIN 0x100000
#define DOSR_DEBUG_HOST 0x200000
#define DOSR_DEBUG_TRAX 0x400000
#define DOSR_DEBUG_PEND_BIN_SHIFT 16
#define DOSR_DEBUG_PEND_HOST_SHIFT 17
#define DOSR_DEBUG_PEND_TRAX_SHIFT 18
#define DOSR_DEBUG_BREAKIN 0x0100000
#define DOSR_DEBUG_BREAKIN_SHIFT 20
#define DOSR_DEBUG_HOST_SHIFT 21
#define DOSR_DEBUG_TRAX_SHIFT 22
#define DOSR_DEBUG_STALL 0x1000000
#define DOSR_DEBUG_STALL_SHIFT 24
#define DOSR_CORE_ON 0x40000000
#define DOSR_CORE_ON_SHIFT 30
#define DOSR_DEBUG_ON 0x80000000
#define DOSR_DEBUG_ON_SHIFT 31
/********** Performance monitor registers bits **********/
#define PERF_PMG_ENABLE 0x00000001 /* global enable bit */
#define PERF_PMG_ENABLE_SHIFT 0
#define PERF_PMCTRL_INT_ENABLE 0x00000001 /* assert interrupt on overflow */
#define PERF_PMCTRL_INT_ENABLE_SHIFT 0
#define PERF_PMCTRL_KRNLCNT 0x00000008 /* ignore TRACELEVEL */
#define PERF_PMCTRL_KRNLCNT_SHIFT 3
#define PERF_PMCTRL_TRACELEVEL 0x000000F0 /* count when CINTLEVEL <= TRACELEVEL */
#define PERF_PMCTRL_TRACELEVEL_SHIFT 4
#define PERF_PMCTRL_SELECT 0x00001F00 /* events group selector */
#define PERF_PMCTRL_SELECT_SHIFT 8
#define PERF_PMCTRL_MASK 0xFFFF0000 /* events mask */
#define PERF_PMCTRL_MASK_SHIFT 16
#define PERF_PMSTAT_OVERFLOW 0x00000001 /* counter overflowed */
#define PERF_PMSTAT_OVERFLOW_SHIFT 0
#define PERF_PMSTAT_INT 0x00000010 /* interrupt asserted */
#define PERF_PMSTAT_INT_SHIFT 4
#if defined (USE_XDM_REGNAME) || defined (USE_DAP_REGNAME)
/* Describes XDM register: */
typedef struct {
int reg;
char* name;
} regdef_t;
/*char* regname(regdef_t* list, int regno)
{
unsigned i;
for(i = 0 ; i < (sizeof(list) / sizeof(regdef_t)); i++){
if(list[i].reg == regno)
return list[i].name;
}
return "???";
}*/
/*
* Returns the name of the specified XDM register number,
* or simply "???" if the register number is not recognized.
* FIXME - requires -1 as the last entry - change to compare the name to ???
* or even better, make the code above to work.
*/
static char * regname(regdef_t* list, int reg)
{
int i = 0;
while (list[i].reg != -1){
if (list[i].reg == reg)
break;
i++;
}
return list[i].name;
}
#if defined (USE_XDM_REGNAME)
regdef_t xdm_reglist[] =
{
{XDM_TRAX_ID ,"TRAX_ID" },
{XDM_TRAX_CONTROL ,"CONTROL" },
{XDM_TRAX_STATUS ,"STATUS" },
{XDM_TRAX_DATA ,"DATA" },
{XDM_TRAX_ADDRESS ,"ADDRESS" },
{XDM_TRAX_TRIGGER ,"TRIGGER PC" },
{XDM_TRAX_MATCH ,"PC MATCH" },
{XDM_TRAX_DELAY ,"DELAY CNT." },
{XDM_TRAX_STARTADDR ,"START ADDRESS"},
{XDM_TRAX_ENDADDR ,"END ADDRESS" },
{XDM_TRAX_DEBUGPC ,"DEBUG PC" },
{XDM_TRAX_P4CHANGE ,"P4 CHANGE" },
{XDM_TRAX_P4REV ,"P4 REV." },
{XDM_TRAX_P4DATE ,"P4 DATE" },
{XDM_TRAX_P4TIME ,"P4 TIME" },
{XDM_TRAX_PDSTATUS ,"PD STATUS" },
{XDM_TRAX_PDDATA ,"PD DATA" },
{XDM_TRAX_STOP_PC ,"STOP PC" },
{XDM_TRAX_STOP_ICNT ,"STOP ICNT" },
{XDM_TRAX_MSG_STATUS ,"MSG STAT." },
{XDM_TRAX_FSM_STATUS ,"FSM STAT." },
{XDM_TRAX_IB_STATUS ,"IB STAT." },
{XDM_OCD_ID ,"OCD_ID" },
{XDM_OCD_DCR_CLR ,"DCR_CLR" },
{XDM_OCD_DCR_SET ,"DCR_SET" },
{XDM_OCD_DSR ,"DOSR" },
{XDM_OCD_DDR ,"DDR" },
{XDM_OCD_DDREXEC ,"DDREXEC" },
{XDM_OCD_DIR0EXEC ,"DIR0EXEC"},
{XDM_OCD_DIR0 ,"DIR0" },
{XDM_OCD_DIR1 ,"DIR1" },
{XDM_OCD_DIR2 ,"DIR2" },
{XDM_OCD_DIR3 ,"DIR3" },
{XDM_OCD_DIR4 ,"DIR4" },
{XDM_OCD_DIR5 ,"DIR5" },
{XDM_OCD_DIR6 ,"DIR6" },
{XDM_OCD_DIR7 ,"DIR7" },
{XDM_PERF_PMG ,"PMG" },
{XDM_PERF_INTPC ,"INTPC" },
{XDM_PERF_PM0 ,"PM0 " },
{XDM_PERF_PM1 ,"PM1 " },
{XDM_PERF_PM2 ,"PM2 " },
{XDM_PERF_PM3 ,"PM3 " },
{XDM_PERF_PM4 ,"PM4 " },
{XDM_PERF_PM5 ,"PM5 " },
{XDM_PERF_PM6 ,"PM6 " },
{XDM_PERF_PM7 ,"PM7 " },
{XDM_PERF_PMCTRL0 ,"PMCTRL0"},
{XDM_PERF_PMCTRL1 ,"PMCTRL1"},
{XDM_PERF_PMCTRL2 ,"PMCTRL2"},
{XDM_PERF_PMCTRL3 ,"PMCTRL3"},
{XDM_PERF_PMCTRL4 ,"PMCTRL4"},
{XDM_PERF_PMCTRL5 ,"PMCTRL5"},
{XDM_PERF_PMCTRL6 ,"PMCTRL6"},
{XDM_PERF_PMCTRL7 ,"PMCTRL7"},
{XDM_PERF_PMSTAT0 ,"PMSTAT0"},
{XDM_PERF_PMSTAT1 ,"PMSTAT1"},
{XDM_PERF_PMSTAT2 ,"PMSTAT2"},
{XDM_PERF_PMSTAT3 ,"PMSTAT3"},
{XDM_PERF_PMSTAT4 ,"PMSTAT4"},
{XDM_PERF_PMSTAT5 ,"PMSTAT5"},
{XDM_PERF_PMSTAT6 ,"PMSTAT6"},
{XDM_PERF_PMSTAT7 ,"PMSTAT7"},
{XDM_MISC_PWRCTL ,"PWRCTL" },
{XDM_MISC_PWRSTAT ,"PWRSTAT" },
{XDM_MISC_ERISTAT ,"ERISTAT" },
{XDM_MISC_DATETIME ,"DATETIME"},
{XDM_MISC_UBID ,"UBID" },
{XDM_MISC_CID ,"CID" },
{XDM_CS_ITCTRL ,"ITCTRL" },
{XDM_CS_CLAIMSET ,"CLAIMSET" },
{XDM_CS_CLAIMCLR ,"CLAIMCLR" },
{XDM_CS_LOCK_ACCESS ,"LOCK_ACCESS"},
{XDM_CS_LOCK_STATUS ,"LOCK_STATUS"},
{XDM_CS_AUTH_STATUS ,"AUTH_STATUS"},
{XDM_CS_DEV_ID ,"DEV_ID" },
{XDM_CS_DEV_TYPE ,"DEV_TYPE" },
{XDM_CS_PER_ID4 ,"PER_ID4" },
{XDM_CS_PER_ID5 ,"PER_ID5" },
{XDM_CS_PER_ID6 ,"PER_ID6" },
{XDM_CS_PER_ID7 ,"PER_ID7" },
{XDM_CS_PER_ID0 ,"PER_ID0" },
{XDM_CS_PER_ID1 ,"PER_ID1" },
{XDM_CS_PER_ID2 ,"PER_ID2" },
{XDM_CS_PER_ID3 ,"PER_ID3" },
{XDM_CS_COMP_ID0 ,"COMP_ID0" },
{XDM_CS_COMP_ID1 ,"COMP_ID1" },
{XDM_CS_COMP_ID2 ,"COMP_ID2" },
{XDM_CS_COMP_ID3 ,"COMP_ID3" },
{-1 ,"???" },
};
#endif
#endif
#endif /* _XDM_REGS_H_ */

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tools/sdk/include/esp32/xtensa/xt_perf_consts.h
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/*
* Customer ID=11656; Build=0x5f626; Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef __XT_PERF_CONSTS_H__
#define __XT_PERF_CONSTS_H__
/*
* Performance monitor counter selectors
*/
#define XTPERF_CNT_COMMITTED_INSN 0x8002 /* Instructions committed */
#define XTPERF_CNT_BRANCH_PENALTY 0x8003 /* Branch penalty cycles */
#define XTPERF_CNT_PIPELINE_INTERLOCKS 0x8004 /* Pipeline interlocks cycles */
#define XTPERF_CNT_ICACHE_MISSES 0x8005 /* ICache misses penalty in cycles */
#define XTPERF_CNT_DCACHE_MISSES 0x8006 /* DCache misses penalty in cycles */
#define XTPERF_CNT_CYCLES 0 /* Count cycles */
#define XTPERF_CNT_OVERFLOW 1 /* Overflow of counter n-1 (assuming this is counter n) */
#define XTPERF_CNT_INSN 2 /* Successfully completed instructions */
#define XTPERF_CNT_D_STALL 3 /* Data-related GlobalStall cycles */
#define XTPERF_CNT_I_STALL 4 /* Instruction-related and other GlobalStall cycles */
#define XTPERF_CNT_EXR 5 /* Exceptions and pipeline replays */
#define XTPERF_CNT_BUBBLES 6 /* Hold and other bubble cycles */
#define XTPERF_CNT_I_TLB 7 /* Instruction TLB Accesses (per instruction retiring) */
#define XTPERF_CNT_I_MEM 8 /* Instruction memory accesses (per instruction retiring) */
#define XTPERF_CNT_D_TLB 9 /* Data TLB accesses */
#define XTPERF_CNT_D_LOAD_U1 10 /* Data memory load instruction (load-store unit 1) */
#define XTPERF_CNT_D_STORE_U1 11 /* Data memory store instruction (load-store unit 1) */
#define XTPERF_CNT_D_ACCESS_U1 12 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 1) */
#define XTPERF_CNT_D_LOAD_U2 13 /* Data memory load instruction (load-store unit 2) */
#define XTPERF_CNT_D_STORE_U2 14 /* Data memory store instruction (load-store unit 2) */
#define XTPERF_CNT_D_ACCESS_U2 15 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 2) */
#define XTPERF_CNT_D_LOAD_U3 16 /* Data memory load instruction (load-store unit 3) */
#define XTPERF_CNT_D_STORE_U3 17 /* Data memory store instruction (load-store unit 3) */
#define XTPERF_CNT_D_ACCESS_U3 18 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 3) */
#define XTPERF_CNT_MULTIPLE_LS 22 /* Multiple Load/Store */
#define XTPERF_CNT_OUTBOUND_PIF 23 /* Outbound PIF transactions */
#define XTPERF_CNT_INBOUND_PIF 24 /* Inbound PIF transactions */
#define XTPERF_CNT_PREFETCH 26 /* Prefetch events */
/*
* Masks for each of the selector listed above
*/
/* XTPERF_CNT_COMMITTED_INSN selector mask */
#define XTPERF_MASK_COMMITTED_INSN 0x0001
/* XTPERF_CNT_BRANCH_PENALTY selector mask */
#define XTPERF_MASK_BRANCH_PENALTY 0x0001
/* XTPERF_CNT_PIPELINE_INTERLOCKS selector mask */
#define XTPERF_MASK_PIPELINE_INTERLOCKS 0x0001
/* XTPERF_CNT_ICACHE_MISSES selector mask */
#define XTPERF_MASK_ICACHE_MISSES 0x0001
/* XTPERF_CNT_DCACHE_MISSES selector mask */
#define XTPERF_MASK_DCACHE_MISSES 0x0001
/* XTPERF_CNT_CYCLES selector mask */
#define XTPERF_MASK_CYCLES 0x0001
/* XTPERF_CNT_OVERFLOW selector mask */
#define XTPERF_MASK_OVERFLOW 0x0001
/*
* XTPERF_CNT_INSN selector mask
*/
#define XTPERF_MASK_INSN_ALL 0x8DFF
#define XTPERF_MASK_INSN_JX 0x0001 /* JX */
#define XTPERF_MASK_INSN_CALLX 0x0002 /* CALLXn */
#define XTPERF_MASK_INSN_RET 0x0004 /* call return i.e. RET, RETW */
#define XTPERF_MASK_INSN_RF 0x0008 /* supervisor return i.e. RFDE, RFE, RFI, RFWO, RFWU */
#define XTPERF_MASK_INSN_BRANCH_TAKEN 0x0010 /* Conditional branch taken, or loopgtz/loopnez skips loop */
#define XTPERF_MASK_INSN_J 0x0020 /* J */
#define XTPERF_MASK_INSN_CALL 0x0040 /* CALLn */
#define XTPERF_MASK_INSN_BRANCH_NOT_TAKEN 0x0080 /* Conditional branch fall through (aka. not-taken branch) */
#define XTPERF_MASK_INSN_LOOP_TAKEN 0x0100 /* Loop instr falls into loop (aka. taken loop) */
#define XTPERF_MASK_INSN_LOOP_BEG 0x0400 /* Loopback taken to LBEG */
#define XTPERF_MASK_INSN_LOOP_END 0x0800 /* Loopback falls through to LEND */
#define XTPERF_MASK_INSN_NON_BRANCH 0x8000 /* Non-branch instruction (aka. non-CTI) */
/*
* XTPERF_CNT_D_STALL selector mask
*/
#define XTPERF_MASK_D_STALL_ALL 0x01FE
#define XTPERF_MASK_D_STALL_STORE_BUF_FULL 0x0002 /* Store buffer full stall */
#define XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT 0x0004 /* Store buffer conflict stall */
#define XTPERF_MASK_D_STALL_CACHE_MISS 0x0008 /* DCache-miss stall */
#define XTPERF_MASK_D_STALL_BUSY 0x0010 /* Data RAM/ROM/XLMI busy stall */
#define XTPERF_MASK_D_STALL_IN_PIF 0x0020 /* Data inbound-PIF request stall (incl s32c1i) */
#define XTPERF_MASK_D_STALL_MHT_LOOKUP 0x0040 /* MHT lookup stall */
#define XTPERF_MASK_D_STALL_UNCACHED_LOAD 0x0080 /* Uncached load stall (included in MHT lookup stall) */
#define XTPERF_MASK_D_STALL_BANK_CONFLICT 0x0100 /* Bank-conflict stall */
/*
* XTPERF_CNT_I_STALL selector mask
*/
#define XTPERF_MASK_I_STALL_ALL 0x01FF
#define XTPERF_MASK_I_STALL_CACHE_MISS 0x0001 /* ICache-miss stall */
#define XTPERF_MASK_I_STALL_BUSY 0x0002 /* Instruction RAM/ROM busy stall */
#define XTPERF_MASK_I_STALL_IN_PIF 0x0004 /* Instruction RAM inbound-PIF request stall */
#define XTPERF_MASK_I_STALL_TIE_PORT 0x0008 /* TIE port stall */
#define XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL 0x0010 /* External RunStall signal status */
#define XTPERF_MASK_I_STALL_UNCACHED_FETCH 0x0020 /* Uncached fetch stall */
#define XTPERF_MASK_I_STALL_FAST_L32R 0x0040 /* FastL32R stall */
#define XTPERF_MASK_I_STALL_ITERATIVE_MUL 0x0080 /* Iterative multiply stall */
#define XTPERF_MASK_I_STALL_ITERATIVE_DIV 0x0100 /* Iterative divide stall */
/*
* XTPERF_CNT_EXR selector mask
*/
#define XTPERF_MASK_EXR_ALL 0x01FF
#define XTPERF_MASK_EXR_REPLAYS 0x0001 /* Other Pipeline Replay (i.e. excludes $ miss etc.) */
#define XTPERF_MASK_EXR_LEVEL1_INT 0x0002 /* Level-1 interrupt */
#define XTPERF_MASK_EXR_LEVELH_INT 0x0004 /* Greater-than-level-1 interrupt */
#define XTPERF_MASK_EXR_DEBUG 0x0008 /* Debug exception */
#define XTPERF_MASK_EXR_NMI 0x0010 /* NMI */
#define XTPERF_MASK_EXR_WINDOW 0x0020 /* Window exception */
#define XTPERF_MASK_EXR_ALLOCA 0x0040 /* Alloca exception */
#define XTPERF_MASK_EXR_OTHER 0x0080 /* Other exceptions */
#define XTPERF_MASK_EXR_MEM_ERR 0x0100 /* HW-corrected memory error */
/*
* XTPERF_CNT_BUBBLES selector mask
*/
#define XTPERF_MASK_BUBBLES_ALL 0x01FD
#define XTPERF_MASK_BUBBLES_PSO 0x0001 /* Processor domain PSO bubble */
#define XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS 0x0004 /* R hold caused by DCache miss */
#define XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE 0x0008 /* R hold caused by Store release */
#define XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP 0x0010 /* R hold caused by register dependency */
#define XTPERF_MASK_BUBBLES_R_HOLD_WAIT 0x0020 /* R hold caused by MEMW, EXTW or EXCW */
#define XTPERF_MASK_BUBBLES_R_HOLD_HALT 0x0040 /* R hold caused by Halt instruction (TX only) */
#define XTPERF_MASK_BUBBLES_CTI 0x0080 /* CTI bubble (e.g. branch delay slot) */
#define XTPERF_MASK_BUBBLES_WAITI 0x0100 /* WAITI bubble */
/*
* XTPERF_CNT_I_TLB selector mask
*/
#define XTPERF_MASK_I_TLB_ALL 0x000F
#define XTPERF_MASK_I_TLB_HITS 0x0001 /* Hit */
#define XTPERF_MASK_I_TLB_REPLAYS 0x0002 /* Replay of instruction due to ITLB miss */
#define XTPERF_MASK_I_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */
#define XTPERF_MASK_I_TLB_MISSES 0x0008 /* ITLB Miss Exception */
/*
* XTPERF_CNT_I_MEM selector mask
*/
#define XTPERF_MASK_I_MEM_ALL 0x000F
#define XTPERF_MASK_I_MEM_CACHE_HITS 0x0001 /* ICache Hit */
#define XTPERF_MASK_I_MEM_CACHE_MISSES 0x0002 /* ICache Miss (includes uncached) */
#define XTPERF_MASK_I_MEM_IRAM 0x0004 /* InstRAM or InstROM */
#define XTPERF_MASK_I_MEM_BYPASS 0x0008 /* Bypass (i.e. uncached) fetch */
/*
* XTPERF_CNT_D_TLB selector mask
*/
#define XTPERF_MASK_D_TLB_ALL 0x000F
#define XTPERF_MASK_D_TLB_HITS 0x0001 /* Hit */
#define XTPERF_MASK_D_TLB_REPLAYS 0x0002 /* Replay of instruction due to DTLB miss */
#define XTPERF_MASK_D_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */
#define XTPERF_MASK_D_TLB_MISSES 0x0008 /* DTLB Miss Exception */
/*
* XTPERF_CNT_D_LOAD_U* selector mask
*/
#define XTPERF_MASK_D_LOAD_ALL 0x000F
#define XTPERF_MASK_D_LOAD_CACHE_HITS 0x0001 /* Cache Hit */
#define XTPERF_MASK_D_LOAD_CACHE_MISSES 0x0002 /* Cache Miss */
#define XTPERF_MASK_D_LOAD_LOCAL_MEM 0x0004 /* Local memory hit */
#define XTPERF_MASK_D_LOAD_BYPASS 0x0008 /* Bypass (i.e. uncached) load */
/*
* XTPERF_CNT_D_STORE_U* selector mask
*/
#define XTPERF_MASK_D_STORE_ALL 0x000F
#define XTPERF_MASK_D_STORE_CACHE_HITS 0x0001 /* DCache Hit */
#define XTPERF_MASK_D_STORE_CACHE_MISSES 0x0002 /* DCache Miss */
#define XTPERF_MASK_D_STORE_LOCAL_MEM 0x0004 /* Local memory hit */
#define XTPERF_MASK_D_STORE_PIF 0x0008 /* PIF Store */
/*
* XTPERF_CNT_D_ACCESS_U* selector mask
*/
#define XTPERF_MASK_D_ACCESS_ALL 0x000F
#define XTPERF_MASK_D_ACCESS_CACHE_MISSES 0x0001 /* DCache Miss */
#define XTPERF_MASK_D_ACCESS_HITS_SHARED 0x0002 /* Hit Shared */
#define XTPERF_MASK_D_ACCESS_HITS_EXCLUSIVE 0x0004 /* Hit Exclusive */
#define XTPERF_MASK_D_ACCESS_HITS_MODIFIED 0x0008 /* Hit Modified */
/*
* XTPERF_CNT_MULTIPLE_LS selector mask
*/
#define XTPERF_MASK_MULTIPLE_LS_ALL 0x003F
#define XTPERF_MASK_MULTIPLE_LS_0S_0L 0x0001 /* 0 stores and 0 loads */
#define XTPERF_MASK_MULTIPLE_LS_0S_1L 0x0002 /* 0 stores and 1 loads */
#define XTPERF_MASK_MULTIPLE_LS_1S_0L 0x0004 /* 1 stores and 0 loads */
#define XTPERF_MASK_MULTIPLE_LS_1S_1L 0x0008 /* 1 stores and 1 loads */
#define XTPERF_MASK_MULTIPLE_LS_0S_2L 0x0010 /* 0 stores and 2 loads */
#define XTPERF_MASK_MULTIPLE_LS_2S_0L 0x0020 /* 2 stores and 0 loads */
/*
* XTPERF_CNT_OUTBOUND_PIF selector mask
*/
#define XTPERF_MASK_OUTBOUND_PIF_ALL 0x0003
#define XTPERF_MASK_OUTBOUND_PIF_CASTOUT 0x0001 /* Castout */
#define XTPERF_MASK_OUTBOUND_PIF_PREFETCH 0x0002 /* Prefetch */
/*
* XTPERF_CNT_INBOUND_PIF selector mask
*/
#define XTPERF_MASK_INBOUND_PIF_ALL 0x0003
#define XTPERF_MASK_INBOUND_PIF_I_DMA 0x0001 /* Instruction DMA */
#define XTPERF_MASK_INBOUND_PIF_D_DMA 0x0002 /* Data DMA */
/*
* XTPERF_CNT_PREFETCH selector mask
*/
#define XTPERF_MASK_PREFETCH_ALL 0x002F
#define XTPERF_MASK_PREFETCH_I_HIT 0x0001 /* I prefetch-buffer-lookup hit */
#define XTPERF_MASK_PREFETCH_D_HIT 0x0002 /* D prefetch-buffer-lookup hit */
#define XTPERF_MASK_PREFETCH_I_MISS 0x0004 /* I prefetch-buffer-lookup miss */
#define XTPERF_MASK_PREFETCH_D_MISS 0x0008 /* D prefetch-buffer-lookup miss */
#define XTPERF_MASK_PREFETCH_D_L1_FILL 0x0020 /* Fill directly to DCache L1 */
#endif /* __XT_PERF_CONSTS_H__ */

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tools/sdk/include/esp32/xtensa/xtensa-libdb-macros.h
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/*
* xtensa-libdb-macros.h
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/Software/libdb/xtensa-libdb-macros.h#1 $ */
/* Copyright (c) 2004-2008 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef __H_LIBDB_MACROS
#define __H_LIBDB_MACROS
/*
* This header file provides macros used to construct, identify and use
* "target numbers" that are assigned to various types of Xtensa processor
* registers and states. These target numbers are used by GDB in the remote
* protocol, and are thus used by all GDB debugger agents (targets).
* They are also used in ELF debugger information sections (stabs, dwarf, etc).
*
* These macros are separated from xtensa-libdb.h because they are needed
* by certain debugger agents that do not use or have access to libdb,
* e.g. the OCD daemon, RedBoot, XMON, etc.
*
* For the time being, for compatibility with certain 3rd party debugger
* software vendors, target numbers are limited to 16 bits. It is
* conceivable that this will be extended in the future to 32 bits.
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef uint32
#define uint32 unsigned int
#endif
#ifndef int32
#define int32 int
#endif
/*
* Macros to form register "target numbers" for various standard registers/states:
*/
#define XTENSA_DBREGN_INVALID -1 /* not a valid target number */
#define XTENSA_DBREGN_A(n) (0x0000+(n)) /* address registers a0..a15 */
#define XTENSA_DBREGN_B(n) (0x0010+(n)) /* boolean bits b0..b15 */
#define XTENSA_DBREGN_PC 0x0020 /* program counter */
/* 0x0021 RESERVED for use by Tensilica */
#define XTENSA_DBREGN_BO(n) (0x0022+(n)) /* boolean octuple-bits bo0..bo1 */
#define XTENSA_DBREGN_BQ(n) (0x0024+(n)) /* boolean quadruple-bits bq0..bq3 */
#define XTENSA_DBREGN_BD(n) (0x0028+(n)) /* boolean double-bits bd0..bd7 */
#define XTENSA_DBREGN_F(n) (0x0030+(n)) /* floating point registers f0..f15 */
#define XTENSA_DBREGN_VEC(n) (0x0040+(n)) /* Vectra vec regs v0..v15 */
#define XTENSA_DBREGN_VSEL(n) (0x0050+(n)) /* Vectra sel s0..s3 (V1) ..s7 (V2) */
#define XTENSA_DBREGN_VALIGN(n) (0x0058+(n)) /* Vectra valign regs u0..u3 */
#define XTENSA_DBREGN_VCOEFF(n) (0x005C+(n)) /* Vectra I vcoeff regs c0..c1 */
/* 0x005E..0x005F RESERVED for use by Tensilica */
#define XTENSA_DBREGN_AEP(n) (0x0060+(n)) /* HiFi2 Audio Engine regs aep0..aep7 */
#define XTENSA_DBREGN_AEQ(n) (0x0068+(n)) /* HiFi2 Audio Engine regs aeq0..aeq3 */
/* 0x006C..0x00FF RESERVED for use by Tensilica */
#define XTENSA_DBREGN_AR(n) (0x0100+(n)) /* physical address regs ar0..ar63
(note: only with window option) */
/* 0x0140..0x01FF RESERVED for use by Tensilica */
#define XTENSA_DBREGN_SREG(n) (0x0200+(n)) /* special registers 0..255 (core) */
#define XTENSA_DBREGN_BR XTENSA_DBREGN_SREG(0x04) /* all 16 boolean bits, BR */
#define XTENSA_DBREGN_MR(n) XTENSA_DBREGN_SREG(0x20+(n)) /* MAC16 registers m0..m3 */
#define XTENSA_DBREGN_UREG(n) (0x0300+(n)) /* user registers 0..255 (TIE) */
/* 0x0400..0x0FFF RESERVED for use by Tensilica */
/* 0x1000..0x1FFF user-defined regfiles */
/* 0x2000..0xEFFF other states (and regfiles) */
#define XTENSA_DBREGN_DBAGENT(n) (0xF000+(n)) /* non-processor "registers" 0..4095 for
3rd-party debugger agent defined use */
/* > 0xFFFF (32-bit) RESERVED for use by Tensilica */
/*#define XTENSA_DBREGN_CONTEXT(n) (0x02000000+((n)<<20))*/ /* add this macro's value to a target
number to identify a specific context 0..31
for context-replicated registers */
#define XTENSA_DBREGN_MASK 0xFFFF /* mask of valid target_number bits */
#define XTENSA_DBREGN_WRITE_SIDE 0x04000000 /* flag to request write half of a register
split into distinct read and write entries
with the same target number (currently only
valid in a couple of libdb API functions;
see xtensa-libdb.h for details) */
/*
* Macros to identify specific ranges of target numbers (formed above):
* NOTE: any context number (or other upper 12 bits) are considered
* modifiers and are thus stripped out for identification purposes.
*/
#define XTENSA_DBREGN_IS_VALID(tn) (((tn) & ~0xFFFF) == 0) /* just tests it's 16-bit unsigned */
#define XTENSA_DBREGN_IS_A(tn) (((tn) & 0xFFF0)==0x0000) /* is a0..a15 */
#define XTENSA_DBREGN_IS_B(tn) (((tn) & 0xFFF0)==0x0010) /* is b0..b15 */
#define XTENSA_DBREGN_IS_PC(tn) (((tn) & 0xFFFF)==0x0020) /* is program counter */
#define XTENSA_DBREGN_IS_BO(tn) (((tn) & 0xFFFE)==0x0022) /* is bo0..bo1 */
#define XTENSA_DBREGN_IS_BQ(tn) (((tn) & 0xFFFC)==0x0024) /* is bq0..bq3 */
#define XTENSA_DBREGN_IS_BD(tn) (((tn) & 0xFFF8)==0x0028) /* is bd0..bd7 */
#define XTENSA_DBREGN_IS_F(tn) (((tn) & 0xFFF0)==0x0030) /* is f0..f15 */
#define XTENSA_DBREGN_IS_VEC(tn) (((tn) & 0xFFF0)==0x0040) /* is v0..v15 */
#define XTENSA_DBREGN_IS_VSEL(tn) (((tn) & 0xFFF8)==0x0050) /* is s0..s7 (s0..s3 in V1) */
#define XTENSA_DBREGN_IS_VALIGN(tn) (((tn) & 0xFFFC)==0x0058) /* is u0..u3 */
#define XTENSA_DBREGN_IS_VCOEFF(tn) (((tn) & 0xFFFE)==0x005C) /* is c0..c1 */
#define XTENSA_DBREGN_IS_AEP(tn) (((tn) & 0xFFF8)==0x0060) /* is aep0..aep7 */
#define XTENSA_DBREGN_IS_AEQ(tn) (((tn) & 0xFFFC)==0x0068) /* is aeq0..aeq3 */
#define XTENSA_DBREGN_IS_AR(tn) (((tn) & 0xFFC0)==0x0100) /* is ar0..ar63 */
#define XTENSA_DBREGN_IS_SREG(tn) (((tn) & 0xFF00)==0x0200) /* is special register */
#define XTENSA_DBREGN_IS_BR(tn) (((tn) & 0xFFFF)==XTENSA_DBREGN_SREG(0x04)) /* is BR */
#define XTENSA_DBREGN_IS_MR(tn) (((tn) & 0xFFFC)==XTENSA_DBREGN_SREG(0x20)) /* m0..m3 */
#define XTENSA_DBREGN_IS_UREG(tn) (((tn) & 0xFF00)==0x0300) /* is user register */
#define XTENSA_DBREGN_IS_DBAGENT(tn) (((tn) & 0xF000)==0xF000) /* is non-processor */
/*#define XTENSA_DBREGN_IS_CONTEXT(tn) (((tn) & 0x02000000) != 0)*/ /* specifies context # */
/*
* Macros to extract register index from a register "target number"
* when a specific range has been identified using one of the _IS_ macros above.
* These macros only return a useful value if the corresponding _IS_ macro returns true.
*/
#define XTENSA_DBREGN_A_INDEX(tn) ((tn) & 0x0F) /* 0..15 for a0..a15 */
#define XTENSA_DBREGN_B_INDEX(tn) ((tn) & 0x0F) /* 0..15 for b0..b15 */
#define XTENSA_DBREGN_BO_INDEX(tn) ((tn) & 0x01) /* 0..1 for bo0..bo1 */
#define XTENSA_DBREGN_BQ_INDEX(tn) ((tn) & 0x03) /* 0..3 for bq0..bq3 */
#define XTENSA_DBREGN_BD_INDEX(tn) ((tn) & 0x07) /* 0..7 for bd0..bd7 */
#define XTENSA_DBREGN_F_INDEX(tn) ((tn) & 0x0F) /* 0..15 for f0..f15 */
#define XTENSA_DBREGN_VEC_INDEX(tn) ((tn) & 0x0F) /* 0..15 for v0..v15 */
#define XTENSA_DBREGN_VSEL_INDEX(tn) ((tn) & 0x07) /* 0..7 for s0..s7 */
#define XTENSA_DBREGN_VALIGN_INDEX(tn) ((tn) & 0x03) /* 0..3 for u0..u3 */
#define XTENSA_DBREGN_VCOEFF_INDEX(tn) ((tn) & 0x01) /* 0..1 for c0..c1 */
#define XTENSA_DBREGN_AEP_INDEX(tn) ((tn) & 0x07) /* 0..7 for aep0..aep7 */
#define XTENSA_DBREGN_AEQ_INDEX(tn) ((tn) & 0x03) /* 0..3 for aeq0..aeq3 */
#define XTENSA_DBREGN_AR_INDEX(tn) ((tn) & 0x3F) /* 0..63 for ar0..ar63 */
#define XTENSA_DBREGN_SREG_INDEX(tn) ((tn) & 0xFF) /* 0..255 for special registers */
#define XTENSA_DBREGN_MR_INDEX(tn) ((tn) & 0x03) /* 0..3 for m0..m3 */
#define XTENSA_DBREGN_UREG_INDEX(tn) ((tn) & 0xFF) /* 0..255 for user registers */
#define XTENSA_DBREGN_DBAGENT_INDEX(tn) ((tn) & 0xFFF) /* 0..4095 for non-processor */
/*#define XTENSA_DBREGN_CONTEXT_INDEX(tn) (((tn) >> 20) & 0x1F)*/ /* 0..31 context numbers */
#ifdef __cplusplus
}
#endif
#endif /* __H_LIBDB_MACROS */

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/*
xtensa-versions.h -- definitions of Xtensa version and release numbers
This file defines most Xtensa-related product versions and releases
that exist so far.
It also provides a bit of information about which ones are current.
This file changes every release, as versions/releases get added.
$Id: //depot/rel/Eaglenest/Xtensa/Software/misc/xtensa-versions.h.tpp#2 $
Copyright (c) 2006-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_VERSIONS_H
#define XTENSA_VERSIONS_H
/*
* NOTE: A "release" is a collection of product versions
* made available at once (together) to customers.
* In the past, release and version names all matched in T####.# form,
* making the distinction irrelevant.
* Starting with the RA-2004.1 release, this is no longer the case.
*/
/* Hardware (Xtensa/Diamond processor) versions: */
#define XTENSA_HWVERSION_T1020_0 102000 /* versions T1020.0 */
#define XTENSA_HWCIDSCHEME_T1020_0 10
#define XTENSA_HWCIDVERS_T1020_0 2
#define XTENSA_HWVERSION_T1020_1 102001 /* versions T1020.1 */
#define XTENSA_HWCIDSCHEME_T1020_1 10
#define XTENSA_HWCIDVERS_T1020_1 3
#define XTENSA_HWVERSION_T1020_2B 102002 /* versions T1020.2b */
#define XTENSA_HWCIDSCHEME_T1020_2B 10
#define XTENSA_HWCIDVERS_T1020_2B 5
#define XTENSA_HWVERSION_T1020_2 102002 /* versions T1020.2 */
#define XTENSA_HWCIDSCHEME_T1020_2 10
#define XTENSA_HWCIDVERS_T1020_2 4
#define XTENSA_HWVERSION_T1020_3 102003 /* versions T1020.3 */
#define XTENSA_HWCIDSCHEME_T1020_3 10
#define XTENSA_HWCIDVERS_T1020_3 6
#define XTENSA_HWVERSION_T1020_4 102004 /* versions T1020.4 */
#define XTENSA_HWCIDSCHEME_T1020_4 10
#define XTENSA_HWCIDVERS_T1020_4 7
#define XTENSA_HWVERSION_T1030_0 103000 /* versions T1030.0 */
#define XTENSA_HWCIDSCHEME_T1030_0 10
#define XTENSA_HWCIDVERS_T1030_0 9
#define XTENSA_HWVERSION_T1030_1 103001 /* versions T1030.1 */
#define XTENSA_HWCIDSCHEME_T1030_1 10
#define XTENSA_HWCIDVERS_T1030_1 10
#define XTENSA_HWVERSION_T1030_2 103002 /* versions T1030.2 */
#define XTENSA_HWCIDSCHEME_T1030_2 10
#define XTENSA_HWCIDVERS_T1030_2 11
#define XTENSA_HWVERSION_T1030_3 103003 /* versions T1030.3 */
#define XTENSA_HWCIDSCHEME_T1030_3 10
#define XTENSA_HWCIDVERS_T1030_3 12
#define XTENSA_HWVERSION_T1040_0 104000 /* versions T1040.0 */
#define XTENSA_HWCIDSCHEME_T1040_0 10
#define XTENSA_HWCIDVERS_T1040_0 15
#define XTENSA_HWVERSION_T1040_1 104001 /* versions T1040.1 */
#define XTENSA_HWCIDSCHEME_T1040_1 01
#define XTENSA_HWCIDVERS_T1040_1 32
#define XTENSA_HWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */
#define XTENSA_HWCIDSCHEME_T1040_1P 10
#define XTENSA_HWCIDVERS_T1040_1P 16
#define XTENSA_HWVERSION_T1040_2 104002 /* versions T1040.2 */
#define XTENSA_HWCIDSCHEME_T1040_2 01
#define XTENSA_HWCIDVERS_T1040_2 33
#define XTENSA_HWVERSION_T1040_3 104003 /* versions T1040.3 */
#define XTENSA_HWCIDSCHEME_T1040_3 01
#define XTENSA_HWCIDVERS_T1040_3 34
#define XTENSA_HWVERSION_T1050_0 105000 /* versions T1050.0 */
#define XTENSA_HWCIDSCHEME_T1050_0 1100
#define XTENSA_HWCIDVERS_T1050_0 1
#define XTENSA_HWVERSION_T1050_1 105001 /* versions T1050.1 */
#define XTENSA_HWCIDSCHEME_T1050_1 1100
#define XTENSA_HWCIDVERS_T1050_1 2
#define XTENSA_HWVERSION_T1050_2 105002 /* versions T1050.2 */
#define XTENSA_HWCIDSCHEME_T1050_2 1100
#define XTENSA_HWCIDVERS_T1050_2 4
#define XTENSA_HWVERSION_T1050_3 105003 /* versions T1050.3 */
#define XTENSA_HWCIDSCHEME_T1050_3 1100
#define XTENSA_HWCIDVERS_T1050_3 6
#define XTENSA_HWVERSION_T1050_4 105004 /* versions T1050.4 */
#define XTENSA_HWCIDSCHEME_T1050_4 1100
#define XTENSA_HWCIDVERS_T1050_4 7
#define XTENSA_HWVERSION_T1050_5 105005 /* versions T1050.5 */
#define XTENSA_HWCIDSCHEME_T1050_5 1100
#define XTENSA_HWCIDVERS_T1050_5 8
#define XTENSA_HWVERSION_RA_2004_1 210000 /* versions LX1.0.0 */
#define XTENSA_HWCIDSCHEME_RA_2004_1 1100
#define XTENSA_HWCIDVERS_RA_2004_1 3
#define XTENSA_HWVERSION_RA_2005_1 210001 /* versions LX1.0.1 */
#define XTENSA_HWCIDSCHEME_RA_2005_1 1100
#define XTENSA_HWCIDVERS_RA_2005_1 20
#define XTENSA_HWVERSION_RA_2005_2 210002 /* versions LX1.0.2 */
#define XTENSA_HWCIDSCHEME_RA_2005_2 1100
#define XTENSA_HWCIDVERS_RA_2005_2 21
#define XTENSA_HWVERSION_RA_2005_3 210003 /* versions LX1.0.3, X6.0.3 */
#define XTENSA_HWCIDSCHEME_RA_2005_3 1100
#define XTENSA_HWCIDVERS_RA_2005_3 22
#define XTENSA_HWVERSION_RA_2006_4 210004 /* versions LX1.0.4, X6.0.4 */
#define XTENSA_HWCIDSCHEME_RA_2006_4 1100
#define XTENSA_HWCIDVERS_RA_2006_4 23
#define XTENSA_HWVERSION_RA_2006_5 210005 /* versions LX1.0.5, X6.0.5 */
#define XTENSA_HWCIDSCHEME_RA_2006_5 1100
#define XTENSA_HWCIDVERS_RA_2006_5 24
#define XTENSA_HWVERSION_RA_2006_6 210006 /* versions LX1.0.6, X6.0.6 */
#define XTENSA_HWCIDSCHEME_RA_2006_6 1100
#define XTENSA_HWCIDVERS_RA_2006_6 25
#define XTENSA_HWVERSION_RA_2007_7 210007 /* versions LX1.0.7, X6.0.7 */
#define XTENSA_HWCIDSCHEME_RA_2007_7 1100
#define XTENSA_HWCIDVERS_RA_2007_7 26
#define XTENSA_HWVERSION_RA_2008_8 210008 /* versions LX1.0.8, X6.0.8 */
#define XTENSA_HWCIDSCHEME_RA_2008_8 1100
#define XTENSA_HWCIDVERS_RA_2008_8 27
#define XTENSA_HWVERSION_RB_2006_0 220000 /* versions LX2.0.0, X7.0.0 */
#define XTENSA_HWCIDSCHEME_RB_2006_0 1100
#define XTENSA_HWCIDVERS_RB_2006_0 48
#define XTENSA_HWVERSION_RB_2007_1 220001 /* versions LX2.0.1, X7.0.1 */
#define XTENSA_HWCIDSCHEME_RB_2007_1 1100
#define XTENSA_HWCIDVERS_RB_2007_1 49
#define XTENSA_HWVERSION_RB_2007_2 221000 /* versions LX2.1.0, X7.1.0 */
#define XTENSA_HWCIDSCHEME_RB_2007_2 1100
#define XTENSA_HWCIDVERS_RB_2007_2 52
#define XTENSA_HWVERSION_RB_2008_3 221001 /* versions LX2.1.1, X7.1.1 */
#define XTENSA_HWCIDSCHEME_RB_2008_3 1100
#define XTENSA_HWCIDVERS_RB_2008_3 53
#define XTENSA_HWVERSION_RB_2008_4 221002 /* versions LX2.1.2, X7.1.2 */
#define XTENSA_HWCIDSCHEME_RB_2008_4 1100
#define XTENSA_HWCIDVERS_RB_2008_4 54
#define XTENSA_HWVERSION_RB_2009_5 221003 /* versions LX2.1.3, X7.1.3 */
#define XTENSA_HWCIDSCHEME_RB_2009_5 1100
#define XTENSA_HWCIDVERS_RB_2009_5 55
#define XTENSA_HWVERSION_RB_2007_2_MP 221100 /* versions LX2.1.8-MP, X7.1.8-MP */
#define XTENSA_HWCIDSCHEME_RB_2007_2_MP 1100
#define XTENSA_HWCIDVERS_RB_2007_2_MP 64
#define XTENSA_HWVERSION_RC_2009_0 230000 /* versions LX3.0.0, X8.0.0, MX1.0.0 */
#define XTENSA_HWCIDSCHEME_RC_2009_0 1100
#define XTENSA_HWCIDVERS_RC_2009_0 65
#define XTENSA_HWVERSION_RC_2010_1 230001 /* versions LX3.0.1, X8.0.1, MX1.0.1 */
#define XTENSA_HWCIDSCHEME_RC_2010_1 1100
#define XTENSA_HWCIDVERS_RC_2010_1 66
#define XTENSA_HWVERSION_RC_2010_2 230002 /* versions LX3.0.2, X8.0.2, MX1.0.2 */
#define XTENSA_HWCIDSCHEME_RC_2010_2 1100
#define XTENSA_HWCIDVERS_RC_2010_2 67
#define XTENSA_HWVERSION_RC_2011_3 230003 /* versions LX3.0.3, X8.0.3, MX1.0.3 */
#define XTENSA_HWCIDSCHEME_RC_2011_3 1100
#define XTENSA_HWCIDVERS_RC_2011_3 68
#define XTENSA_HWVERSION_RD_2010_0 240000 /* versions LX4.0.0, X9.0.0, MX1.1.0, TX1.0.0 */
#define XTENSA_HWCIDSCHEME_RD_2010_0 1100
#define XTENSA_HWCIDVERS_RD_2010_0 80
#define XTENSA_HWVERSION_RD_2011_1 240001 /* versions LX4.0.1, X9.0.1, MX1.1.1, TX1.0.1 */
#define XTENSA_HWCIDSCHEME_RD_2011_1 1100
#define XTENSA_HWCIDVERS_RD_2011_1 81
#define XTENSA_HWVERSION_RD_2011_2 240002 /* versions LX4.0.2, X9.0.2, MX1.1.2, TX1.0.2 */
#define XTENSA_HWCIDSCHEME_RD_2011_2 1100
#define XTENSA_HWCIDVERS_RD_2011_2 82
#define XTENSA_HWVERSION_RD_2011_3 240003 /* versions LX4.0.3, X9.0.3, MX1.1.3, TX1.0.3 */
#define XTENSA_HWCIDSCHEME_RD_2011_3 1100
#define XTENSA_HWCIDVERS_RD_2011_3 83
#define XTENSA_HWVERSION_RD_2012_4 240004 /* versions LX4.0.4, X9.0.4, MX1.1.4, TX1.0.4 */
#define XTENSA_HWCIDSCHEME_RD_2012_4 1100
#define XTENSA_HWCIDVERS_RD_2012_4 84
#define XTENSA_HWVERSION_RD_2012_5 240005 /* versions LX4.0.5, X9.0.5, MX1.1.5, TX1.0.5 */
#define XTENSA_HWCIDSCHEME_RD_2012_5 1100
#define XTENSA_HWCIDVERS_RD_2012_5 85
#define XTENSA_HWVERSION_RE_2012_0 250000 /* versions LX5.0.0, X10.0.0, MX1.2.0, TX2.0.0 */
#define XTENSA_HWCIDSCHEME_RE_2012_0 1100
#define XTENSA_HWCIDVERS_RE_2012_0 96
#define XTENSA_HWVERSION_RE_2012_1 250001 /* versions LX5.0.1, X10.0.1, MX1.2.1, TX2.0.1 */
#define XTENSA_HWCIDSCHEME_RE_2012_1 1100
#define XTENSA_HWCIDVERS_RE_2012_1 97
#define XTENSA_HWVERSION_RE_2013_2 250002 /* versions LX5.0.2, X10.0.2, MX1.2.2, TX2.0.2 */
#define XTENSA_HWCIDSCHEME_RE_2013_2 1100
#define XTENSA_HWCIDVERS_RE_2013_2 98
#define XTENSA_HWVERSION_RE_2013_3 250003 /* versions LX5.0.3, X10.0.3, MX1.2.3, TX2.0.3 */
#define XTENSA_HWCIDSCHEME_RE_2013_3 1100
#define XTENSA_HWCIDVERS_RE_2013_3 99
#define XTENSA_HWVERSION_RE_2013_4 250004 /* versions LX5.0.4, X10.0.4, MX1.2.4, TX2.0.4 */
#define XTENSA_HWCIDSCHEME_RE_2013_4 1100
#define XTENSA_HWCIDVERS_RE_2013_4 100
#define XTENSA_HWVERSION_RE_2014_5 250005 /* versions LX5.0.5, X10.0.5, MX1.2.5, TX2.0.5 */
#define XTENSA_HWCIDSCHEME_RE_2014_5 1100
#define XTENSA_HWCIDVERS_RE_2014_5 101
#define XTENSA_HWVERSION_RE_2015_6 250006 /* versions LX5.0.6, X10.0.6, MX1.2.6, TX2.0.6 */
#define XTENSA_HWCIDSCHEME_RE_2015_6 1100
#define XTENSA_HWCIDVERS_RE_2015_6 102
#define XTENSA_HWVERSION_RF_2014_0 260000 /* versions LX6.0.0, X11.0.0, MX1.3.0, TX3.0.0 */
#define XTENSA_HWCIDSCHEME_RF_2014_0 1100
#define XTENSA_HWCIDVERS_RF_2014_0 112
#define XTENSA_HWVERSION_RF_2014_1 260001 /* versions LX6.0.1, X11.0.1 */
#define XTENSA_HWCIDSCHEME_RF_2014_1 1100
#define XTENSA_HWCIDVERS_RF_2014_1 113
#define XTENSA_HWVERSION_RF_2015_2 260002 /* versions LX6.0.2, X11.0.2 */
#define XTENSA_HWCIDSCHEME_RF_2015_2 1100
#define XTENSA_HWCIDVERS_RF_2015_2 114
#define XTENSA_HWVERSION_RF_2015_3 260003 /* versions LX6.0.3, X11.0.3 */
#define XTENSA_HWCIDSCHEME_RF_2015_3 1100
#define XTENSA_HWCIDVERS_RF_2015_3 115
#define XTENSA_HWVERSION_RG_2015_0 270000 /* versions LX7.0.0, X12.0.0, NX1.0.0, SX1.0.0, MX1.4.0, TX4.0.0 */
#define XTENSA_HWCIDSCHEME_RG_2015_0 1100
#define XTENSA_HWCIDVERS_RG_2015_0 128
/* Software (Xtensa Tools) versions: */
#define XTENSA_SWVERSION_T1020_0 102000 /* versions T1020.0 */
#define XTENSA_SWVERSION_T1020_1 102001 /* versions T1020.1 */
#define XTENSA_SWVERSION_T1020_2B 102002 /* versions T1020.2b */
#define XTENSA_SWVERSION_T1020_2 102002 /* versions T1020.2 */
#define XTENSA_SWVERSION_T1020_3 102003 /* versions T1020.3 */
#define XTENSA_SWVERSION_T1020_4 102004 /* versions T1020.4 */
#define XTENSA_SWVERSION_T1030_0 103000 /* versions T1030.0 */
#define XTENSA_SWVERSION_T1030_1 103001 /* versions T1030.1 */
#define XTENSA_SWVERSION_T1030_2 103002 /* versions T1030.2 */
#define XTENSA_SWVERSION_T1030_3 103003 /* versions T1030.3 */
#define XTENSA_SWVERSION_T1040_0 104000 /* versions T1040.0 */
#define XTENSA_SWVERSION_T1040_1 104001 /* versions T1040.1 */
#define XTENSA_SWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */
#define XTENSA_SWVERSION_T1040_2 104002 /* versions T1040.2 */
#define XTENSA_SWVERSION_T1040_3 104003 /* versions T1040.3 */
#define XTENSA_SWVERSION_T1050_0 105000 /* versions T1050.0 */
#define XTENSA_SWVERSION_T1050_1 105001 /* versions T1050.1 */
#define XTENSA_SWVERSION_T1050_2 105002 /* versions T1050.2 */
#define XTENSA_SWVERSION_T1050_3 105003 /* versions T1050.3 */
#define XTENSA_SWVERSION_T1050_4 105004 /* versions T1050.4 */
#define XTENSA_SWVERSION_T1050_5 105005 /* versions T1050.5 */
#define XTENSA_SWVERSION_RA_2004_1 600000 /* versions 6.0.0 */
#define XTENSA_SWVERSION_RA_2005_1 600001 /* versions 6.0.1 */
#define XTENSA_SWVERSION_RA_2005_2 600002 /* versions 6.0.2 */
#define XTENSA_SWVERSION_RA_2005_3 600003 /* versions 6.0.3 */
#define XTENSA_SWVERSION_RA_2006_4 600004 /* versions 6.0.4 */
#define XTENSA_SWVERSION_RA_2006_5 600005 /* versions 6.0.5 */
#define XTENSA_SWVERSION_RA_2006_6 600006 /* versions 6.0.6 */
#define XTENSA_SWVERSION_RA_2007_7 600007 /* versions 6.0.7 */
#define XTENSA_SWVERSION_RA_2008_8 600008 /* versions 6.0.8 */
#define XTENSA_SWVERSION_RB_2006_0 700000 /* versions 7.0.0 */
#define XTENSA_SWVERSION_RB_2007_1 700001 /* versions 7.0.1 */
#define XTENSA_SWVERSION_RB_2007_2 701000 /* versions 7.1.0 */
#define XTENSA_SWVERSION_RB_2008_3 701001 /* versions 7.1.1 */
#define XTENSA_SWVERSION_RB_2008_4 701002 /* versions 7.1.2 */
#define XTENSA_SWVERSION_RB_2009_5 701003 /* versions 7.1.3 */
#define XTENSA_SWVERSION_RB_2007_2_MP 701100 /* versions 7.1.8-MP */
#define XTENSA_SWVERSION_RC_2009_0 800000 /* versions 8.0.0 */
#define XTENSA_SWVERSION_RC_2010_1 800001 /* versions 8.0.1 */
#define XTENSA_SWVERSION_RC_2010_2 800002 /* versions 8.0.2 */
#define XTENSA_SWVERSION_RC_2011_3 800003 /* versions 8.0.3 */
#define XTENSA_SWVERSION_RD_2010_0 900000 /* versions 9.0.0 */
#define XTENSA_SWVERSION_RD_2011_1 900001 /* versions 9.0.1 */
#define XTENSA_SWVERSION_RD_2011_2 900002 /* versions 9.0.2 */
#define XTENSA_SWVERSION_RD_2011_3 900003 /* versions 9.0.3 */
#define XTENSA_SWVERSION_RD_2012_4 900004 /* versions 9.0.4 */
#define XTENSA_SWVERSION_RD_2012_5 900005 /* versions 9.0.5 */
#define XTENSA_SWVERSION_RE_2012_0 1000000 /* versions 10.0.0 */
#define XTENSA_SWVERSION_RE_2012_1 1000001 /* versions 10.0.1 */
#define XTENSA_SWVERSION_RE_2013_2 1000002 /* versions 10.0.2 */
#define XTENSA_SWVERSION_RE_2013_3 1000003 /* versions 10.0.3 */
#define XTENSA_SWVERSION_RE_2013_4 1000004 /* versions 10.0.4 */
#define XTENSA_SWVERSION_RE_2014_5 1000005 /* versions 10.0.5 */
#define XTENSA_SWVERSION_RE_2015_6 1000006 /* versions 10.0.6 */
#define XTENSA_SWVERSION_RF_2014_0 1100000 /* versions 11.0.0 */
#define XTENSA_SWVERSION_RF_2014_1 1100001 /* versions 11.0.1 */
#define XTENSA_SWVERSION_RF_2015_2 1100002 /* versions 11.0.2 */
#define XTENSA_SWVERSION_RF_2015_3 1100003 /* versions 11.0.3 */
#define XTENSA_SWVERSION_RG_2015_0 1200000 /* versions 12.0.0 */
#define XTENSA_SWVERSION_T1040_1_PREHOTFIX XTENSA_SWVERSION_T1040_1P /* T1040.1-prehotfix */
#define XTENSA_SWVERSION_6_0_0 XTENSA_SWVERSION_RA_2004_1 /* 6.0.0 */
#define XTENSA_SWVERSION_6_0_1 XTENSA_SWVERSION_RA_2005_1 /* 6.0.1 */
#define XTENSA_SWVERSION_6_0_2 XTENSA_SWVERSION_RA_2005_2 /* 6.0.2 */
#define XTENSA_SWVERSION_6_0_3 XTENSA_SWVERSION_RA_2005_3 /* 6.0.3 */
#define XTENSA_SWVERSION_6_0_4 XTENSA_SWVERSION_RA_2006_4 /* 6.0.4 */
#define XTENSA_SWVERSION_6_0_5 XTENSA_SWVERSION_RA_2006_5 /* 6.0.5 */
#define XTENSA_SWVERSION_6_0_6 XTENSA_SWVERSION_RA_2006_6 /* 6.0.6 */
#define XTENSA_SWVERSION_6_0_7 XTENSA_SWVERSION_RA_2007_7 /* 6.0.7 */
#define XTENSA_SWVERSION_6_0_8 XTENSA_SWVERSION_RA_2008_8 /* 6.0.8 */
#define XTENSA_SWVERSION_7_0_0 XTENSA_SWVERSION_RB_2006_0 /* 7.0.0 */
#define XTENSA_SWVERSION_7_0_1 XTENSA_SWVERSION_RB_2007_1 /* 7.0.1 */
#define XTENSA_SWVERSION_7_1_0 XTENSA_SWVERSION_RB_2007_2 /* 7.1.0 */
#define XTENSA_SWVERSION_7_1_1 XTENSA_SWVERSION_RB_2008_3 /* 7.1.1 */
#define XTENSA_SWVERSION_7_1_2 XTENSA_SWVERSION_RB_2008_4 /* 7.1.2 */
#define XTENSA_SWVERSION_7_1_3 XTENSA_SWVERSION_RB_2009_5 /* 7.1.3 */
#define XTENSA_SWVERSION_7_1_8_MP XTENSA_SWVERSION_RB_2007_2_MP /* 7.1.8-MP */
#define XTENSA_SWVERSION_8_0_0 XTENSA_SWVERSION_RC_2009_0 /* 8.0.0 */
#define XTENSA_SWVERSION_8_0_1 XTENSA_SWVERSION_RC_2010_1 /* 8.0.1 */
#define XTENSA_SWVERSION_8_0_2 XTENSA_SWVERSION_RC_2010_2 /* 8.0.2 */
#define XTENSA_SWVERSION_8_0_3 XTENSA_SWVERSION_RC_2011_3 /* 8.0.3 */
#define XTENSA_SWVERSION_9_0_0 XTENSA_SWVERSION_RD_2010_0 /* 9.0.0 */
#define XTENSA_SWVERSION_9_0_1 XTENSA_SWVERSION_RD_2011_1 /* 9.0.1 */
#define XTENSA_SWVERSION_9_0_2 XTENSA_SWVERSION_RD_2011_2 /* 9.0.2 */
#define XTENSA_SWVERSION_9_0_3 XTENSA_SWVERSION_RD_2011_3 /* 9.0.3 */
#define XTENSA_SWVERSION_9_0_4 XTENSA_SWVERSION_RD_2012_4 /* 9.0.4 */
#define XTENSA_SWVERSION_9_0_5 XTENSA_SWVERSION_RD_2012_5 /* 9.0.5 */
#define XTENSA_SWVERSION_10_0_0 XTENSA_SWVERSION_RE_2012_0 /* 10.0.0 */
#define XTENSA_SWVERSION_10_0_1 XTENSA_SWVERSION_RE_2012_1 /* 10.0.1 */
#define XTENSA_SWVERSION_10_0_2 XTENSA_SWVERSION_RE_2013_2 /* 10.0.2 */
#define XTENSA_SWVERSION_10_0_3 XTENSA_SWVERSION_RE_2013_3 /* 10.0.3 */
#define XTENSA_SWVERSION_10_0_4 XTENSA_SWVERSION_RE_2013_4 /* 10.0.4 */
#define XTENSA_SWVERSION_10_0_5 XTENSA_SWVERSION_RE_2014_5 /* 10.0.5 */
#define XTENSA_SWVERSION_10_0_6 XTENSA_SWVERSION_RE_2015_6 /* 10.0.6 */
#define XTENSA_SWVERSION_11_0_0 XTENSA_SWVERSION_RF_2014_0 /* 11.0.0 */
#define XTENSA_SWVERSION_11_0_1 XTENSA_SWVERSION_RF_2014_1 /* 11.0.1 */
#define XTENSA_SWVERSION_11_0_2 XTENSA_SWVERSION_RF_2015_2 /* 11.0.2 */
#define XTENSA_SWVERSION_11_0_3 XTENSA_SWVERSION_RF_2015_3 /* 11.0.3 */
#define XTENSA_SWVERSION_12_0_0 XTENSA_SWVERSION_RG_2015_0 /* 12.0.0 */
/* The current release: */
#define XTENSA_RELEASE_NAME "RF-2015.3"
#define XTENSA_RELEASE_CANONICAL_NAME "RF-2015.3"
/* The product versions within the current release: */
#define XTENSA_SWVERSION XTENSA_SWVERSION_RF_2015_3
#define XTENSA_SWVERSION_NAME "11.0.3"
#define XTENSA_SWVERSION_CANONICAL_NAME "11.0.3"
#define XTENSA_SWVERSION_MAJORMID_NAME "11.0"
#define XTENSA_SWVERSION_MAJOR_NAME "11"
/* For product licensing (not necessarily same as *_MAJORMID_NAME): */
#define XTENSA_SWVERSION_LICENSE_NAME "11.0"
/* Note: there may be multiple hardware products in one release,
and software can target older hardware, so the notion of
"current" hardware versions is partially configuration dependent.
For now, "current" hardware product version info is left out
to avoid confusion. */
#endif /*XTENSA_VERSIONS_H*/

149
tools/sdk/include/esp32/xtensa/xtensa-xer.h
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@ -1,149 +0,0 @@
/* xer-constants.h -- various constants describing external registers accessed
via wer and rer.
TODO: find a better prefix. Also conditionalize certain constants based
on number of cores and interrupts actually present.
*/
/*
* Copyright (c) 1999-2008 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <xtensa/config/core.h>
#define NUM_INTERRUPTS 27
#define NUM_CORES 4
/* Routing of NMI (BInterrupt2) and interrupts 0..n-1 (BInterrupt3+)
RER reads
WER writes
*/
#define XER_MIROUT 0x0000
#define XER_MIROUT_LAST (XER_MIROUT + NUM_INTERRUPTS)
/* IPI to core M (all 16 causes).
RER reads
WER clears
*/
#define XER_MIPICAUSE 0x0100
#define XER_MIPICAUSE_FIELD_A_FIRST 0x0
#define XER_MIPICAUSE_FIELD_A_LAST 0x0
#define XER_MIPICAUSE_FIELD_B_FIRST 0x1
#define XER_MIPICAUSE_FIELD_B_LAST 0x3
#define XER_MIPICAUSE_FIELD_C_FIRST 0x4
#define XER_MIPICAUSE_FIELD_C_LAST 0x7
#define XER_MIPICAUSE_FIELD_D_FIRST 0x8
#define XER_MIPICAUSE_FIELD_D_LAST 0xF
/* IPI from cause bit 0..15
RER invalid
WER sets
*/
#define XER_MIPISET 0x0140
#define XER_MIPISET_LAST 0x014F
/* Global enable
RER read
WER clear
*/
#define XER_MIENG 0x0180
/* Global enable
RER invalid
WER set
*/
#define XER_MIENG_SET 0x0184
/* Global assert
RER read
WER clear
*/
#define XER_MIASG 0x0188
/* Global enable
RER invalid
WER set
*/
#define XER_MIASG_SET 0x018C
/* IPI partition register
RER read
WER write
*/
#define XER_PART 0x0190
#define XER_IPI0 0x0
#define XER_IPI1 0x1
#define XER_IPI2 0x2
#define XER_IPI3 0x3
#define XER_PART_ROUTE_IPI(NUM, FIELD) ((NUM) << ((FIELD) << 2))
#define XER_PART_ROUTE_IPI_CAUSE(TO_A, TO_B, TO_C, TO_D) \
(XER_PART_ROUTE_IPI(TO_A, XER_IPI0) | \
XER_PART_ROUTE_IPI(TO_B, XER_IPI1) | \
XER_PART_ROUTE_IPI(TO_C, XER_IPI2) | \
XER_PART_ROUTE_IPI(TO_D, XER_IPI3))
#define XER_IPI_WAKE_EXT_INTERRUPT XCHAL_EXTINT0_NUM
#define XER_IPI_WAKE_CAUSE XER_MIPICAUSE_FIELD_C_FIRST
#define XER_IPI_WAKE_ADDRESS (XER_MIPISET + XER_IPI_WAKE_CAUSE)
#define XER_DEFAULT_IPI_ROUTING XER_PART_ROUTE_IPI_CAUSE(XER_IPI1, XER_IPI0, XER_IPI2, XER_IPI3)
/* System configuration ID
RER read
WER invalid
*/
#define XER_SYSCFGID 0x01A0
/* RunStall to slave processors
RER read
WER write
*/
#define XER_MPSCORE 0x0200
/* Cache coherency ON
RER read
WER write
*/
#define XER_CCON 0x0220

212
tools/sdk/include/esp32/xtensa/xtruntime-core-state.h
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@ -1,212 +0,0 @@
/* xtruntime-core-state.h - core state save area (used eg. by PSO) */
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/xtruntime-core-state.h#1 $ */
/*
* Copyright (c) 2012-2013 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _XTOS_CORE_STATE_H_
#define _XTOS_CORE_STATE_H_
/* Import STRUCT_xxx macros for defining structures: */
#include <xtensa/xtruntime-frames.h>
#include <xtensa/config/core.h>
#include <xtensa/config/tie.h>
//#define XTOS_PSO_TEST 1 // uncommented for internal PSO testing only
#define CORE_STATE_SIGNATURE 0xB1C5AFED // pattern that indicates state was saved
/*
* Save area for saving entire core state, such as across Power Shut-Off (PSO).
*/
STRUCT_BEGIN
STRUCT_FIELD (long,4,CS_SA_,signature) // for checking whether state was saved
STRUCT_FIELD (long,4,CS_SA_,restore_label)
STRUCT_FIELD (long,4,CS_SA_,aftersave_label)
STRUCT_AFIELD(long,4,CS_SA_,areg,XCHAL_NUM_AREGS)
#if XCHAL_HAVE_WINDOWED
STRUCT_AFIELD(long,4,CS_SA_,caller_regs,16) // save a max of 16 caller regs
STRUCT_FIELD (long,4,CS_SA_,caller_regs_saved) // flag to show if caller regs saved
#endif
#if XCHAL_HAVE_PSO_CDM
STRUCT_FIELD (long,4,CS_SA_,pwrctl)
#endif
#if XCHAL_HAVE_WINDOWED
STRUCT_FIELD (long,4,CS_SA_,windowbase)
STRUCT_FIELD (long,4,CS_SA_,windowstart)
#endif
STRUCT_FIELD (long,4,CS_SA_,sar)
#if XCHAL_HAVE_EXCEPTIONS
STRUCT_FIELD (long,4,CS_SA_,epc1)
STRUCT_FIELD (long,4,CS_SA_,ps)
STRUCT_FIELD (long,4,CS_SA_,excsave1)
# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
STRUCT_FIELD (long,4,CS_SA_,depc)
# endif
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
STRUCT_AFIELD(long,4,CS_SA_,epc, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
STRUCT_AFIELD(long,4,CS_SA_,eps, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
STRUCT_AFIELD(long,4,CS_SA_,excsave,XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
#endif
#if XCHAL_HAVE_LOOPS
STRUCT_FIELD (long,4,CS_SA_,lcount)
STRUCT_FIELD (long,4,CS_SA_,lbeg)
STRUCT_FIELD (long,4,CS_SA_,lend)
#endif
#if XCHAL_HAVE_ABSOLUTE_LITERALS
STRUCT_FIELD (long,4,CS_SA_,litbase)
#endif
#if XCHAL_HAVE_VECBASE
STRUCT_FIELD (long,4,CS_SA_,vecbase)
#endif
#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
STRUCT_FIELD (long,4,CS_SA_,atomctl)
#endif
#if XCHAL_HAVE_PREFETCH
STRUCT_FIELD (long,4,CS_SA_,prefctl)
#endif
#if XCHAL_USE_MEMCTL
STRUCT_FIELD (long,4,CS_SA_,memctl)
#endif
#if XCHAL_HAVE_CCOUNT
STRUCT_FIELD (long,4,CS_SA_,ccount)
STRUCT_AFIELD(long,4,CS_SA_,ccompare, XCHAL_NUM_TIMERS)
#endif
#if XCHAL_HAVE_INTERRUPTS
STRUCT_FIELD (long,4,CS_SA_,intenable)
STRUCT_FIELD (long,4,CS_SA_,interrupt)
#endif
#if XCHAL_HAVE_DEBUG
STRUCT_FIELD (long,4,CS_SA_,icount)
STRUCT_FIELD (long,4,CS_SA_,icountlevel)
STRUCT_FIELD (long,4,CS_SA_,debugcause)
// DDR not saved
# if XCHAL_NUM_DBREAK
STRUCT_AFIELD(long,4,CS_SA_,dbreakc, XCHAL_NUM_DBREAK)
STRUCT_AFIELD(long,4,CS_SA_,dbreaka, XCHAL_NUM_DBREAK)
# endif
# if XCHAL_NUM_IBREAK
STRUCT_AFIELD(long,4,CS_SA_,ibreaka, XCHAL_NUM_IBREAK)
STRUCT_FIELD (long,4,CS_SA_,ibreakenable)
# endif
#endif
#if XCHAL_NUM_MISC_REGS
STRUCT_AFIELD(long,4,CS_SA_,misc,XCHAL_NUM_MISC_REGS)
#endif
#if XCHAL_HAVE_MEM_ECC_PARITY
STRUCT_FIELD (long,4,CS_SA_,mepc)
STRUCT_FIELD (long,4,CS_SA_,meps)
STRUCT_FIELD (long,4,CS_SA_,mesave)
STRUCT_FIELD (long,4,CS_SA_,mesr)
STRUCT_FIELD (long,4,CS_SA_,mecr)
STRUCT_FIELD (long,4,CS_SA_,mevaddr)
#endif
/* We put this ahead of TLB and other TIE state,
to keep it within S32I/L32I offset range. */
#if XCHAL_HAVE_CP
STRUCT_FIELD (long,4,CS_SA_,cpenable)
#endif
/* TLB state */
#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
STRUCT_AFIELD(long,4,CS_SA_,tlbs,8*2)
#endif
#if XCHAL_HAVE_PTP_MMU
/* Compute number of auto-refill (ARF) entries as max of I and D,
to simplify TLB save logic. On the unusual configs with
ITLB ARF != DTLB ARF entries, we'll just end up
saving/restoring some extra entries redundantly. */
# if XCHAL_DTLB_ARF_ENTRIES_LOG2 + XCHAL_ITLB_ARF_ENTRIES_LOG2 > 4
# define ARF_ENTRIES 8
# else
# define ARF_ENTRIES 4
# endif
STRUCT_FIELD (long,4,CS_SA_,ptevaddr)
STRUCT_FIELD (long,4,CS_SA_,rasid)
STRUCT_FIELD (long,4,CS_SA_,dtlbcfg)
STRUCT_FIELD (long,4,CS_SA_,itlbcfg)
/*** WARNING: past this point, field offsets may be larger than S32I/L32I range ***/
STRUCT_AFIELD(long,4,CS_SA_,tlbs,((4*ARF_ENTRIES+4)*2+3)*2)
# if XCHAL_HAVE_SPANNING_WAY /* MMU v3 */
STRUCT_AFIELD(long,4,CS_SA_,tlbs_ways56,(4+8)*2*2)
# endif
#endif
/* TIE state */
/* NOTE: NCP area is aligned to XCHAL_TOTAL_SA_ALIGN not XCHAL_NCP_SA_ALIGN,
because the offsets of all subsequent coprocessor save areas are relative
to the NCP save area. */
STRUCT_AFIELD_A(char,1,XCHAL_TOTAL_SA_ALIGN,CS_SA_,ncp,XCHAL_NCP_SA_SIZE)
#if XCHAL_HAVE_CP
STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE)
STRUCT_AFIELD_A(char,1,XCHAL_CP1_SA_ALIGN,CS_SA_,cp1,XCHAL_CP1_SA_SIZE)
STRUCT_AFIELD_A(char,1,XCHAL_CP2_SA_ALIGN,CS_SA_,cp2,XCHAL_CP2_SA_SIZE)
STRUCT_AFIELD_A(char,1,XCHAL_CP3_SA_ALIGN,CS_SA_,cp3,XCHAL_CP3_SA_SIZE)
STRUCT_AFIELD_A(char,1,XCHAL_CP4_SA_ALIGN,CS_SA_,cp4,XCHAL_CP4_SA_SIZE)
STRUCT_AFIELD_A(char,1,XCHAL_CP5_SA_ALIGN,CS_SA_,cp5,XCHAL_CP5_SA_SIZE)
STRUCT_AFIELD_A(char,1,XCHAL_CP6_SA_ALIGN,CS_SA_,cp6,XCHAL_CP6_SA_SIZE)
STRUCT_AFIELD_A(char,1,XCHAL_CP7_SA_ALIGN,CS_SA_,cp7,XCHAL_CP7_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP8_SA_ALIGN,CS_SA_,cp8,XCHAL_CP8_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP9_SA_ALIGN,CS_SA_,cp9,XCHAL_CP9_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP10_SA_ALIGN,CS_SA_,cp10,XCHAL_CP10_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP11_SA_ALIGN,CS_SA_,cp11,XCHAL_CP11_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP12_SA_ALIGN,CS_SA_,cp12,XCHAL_CP12_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP13_SA_ALIGN,CS_SA_,cp13,XCHAL_CP13_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP14_SA_ALIGN,CS_SA_,cp14,XCHAL_CP14_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP15_SA_ALIGN,CS_SA_,cp15,XCHAL_CP15_SA_SIZE)
#endif
STRUCT_END(XtosCoreState)
// These are part of non-coprocessor state (ncp):
#if XCHAL_HAVE_MAC16
//STRUCT_FIELD (long,4,CS_SA_,acclo)
//STRUCT_FIELD (long,4,CS_SA_,acchi)
//STRUCT_AFIELD(long,4,CS_SA_,mr, 4)
#endif
#if XCHAL_HAVE_THREADPTR
//STRUCT_FIELD (long,4,CS_SA_,threadptr)
#endif
#if XCHAL_HAVE_S32C1I
//STRUCT_FIELD (long,4,CS_SA_,scompare1)
#endif
#if XCHAL_HAVE_BOOLEANS
//STRUCT_FIELD (long,4,CS_SA_,br)
#endif
// Not saved:
// EXCCAUSE ??
// DEBUGCAUSE ??
// EXCVADDR ??
// DDR
// INTERRUPT
// ... locked cache lines ...
#endif /* _XTOS_CORE_STATE_H_ */

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/* xtruntime-frames.h - exception stack frames for single-threaded run-time */
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/xtruntime-frames.h#1 $ */
/*
* Copyright (c) 2002-2012 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _XTRUNTIME_FRAMES_H_
#define _XTRUNTIME_FRAMES_H_
#include <xtensa/config/core.h>
/* Macros that help define structures for both C and assembler: */
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
#define STRUCT_BEGIN .pushsection .text; .struct 0
#define STRUCT_FIELD(ctype,size,pre,name) pre##name: .space size
#define STRUCT_AFIELD(ctype,size,pre,name,n) pre##name: .if n ; .space (size)*(n) ; .endif
#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n) .balign align ; pre##name: .if n ; .space (size)*(n) ; .endif
#define STRUCT_END(sname) sname##Size:; .popsection
#else /*_ASMLANGUAGE||__ASSEMBLER__*/
#define STRUCT_BEGIN typedef struct {
#define STRUCT_FIELD(ctype,size,pre,name) ctype name;
#define STRUCT_AFIELD(ctype,size,pre,name,n) ctype name[n];
#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n) ctype name[n] __attribute__((aligned(align)));
#define STRUCT_END(sname) } sname;
#endif /*_ASMLANGUAGE||__ASSEMBLER__*/
/*
* Kernel vector mode exception stack frame.
*
* NOTE: due to the limited range of addi used in the current
* kernel exception vector, and the fact that historically
* the vector is limited to 12 bytes, the size of this
* stack frame is limited to 128 bytes (currently at 64).
*/
STRUCT_BEGIN
STRUCT_FIELD (long,4,KEXC_,pc) /* "parm" */
STRUCT_FIELD (long,4,KEXC_,ps)
STRUCT_AFIELD(long,4,KEXC_,areg, 4) /* a12 .. a15 */
STRUCT_FIELD (long,4,KEXC_,sar) /* "save" */
#if XCHAL_HAVE_LOOPS
STRUCT_FIELD (long,4,KEXC_,lcount)
STRUCT_FIELD (long,4,KEXC_,lbeg)
STRUCT_FIELD (long,4,KEXC_,lend)
#endif
#if XCHAL_HAVE_MAC16
STRUCT_FIELD (long,4,KEXC_,acclo)
STRUCT_FIELD (long,4,KEXC_,acchi)
STRUCT_AFIELD(long,4,KEXC_,mr, 4)
#endif
STRUCT_END(KernelFrame)
/*
* User vector mode exception stack frame:
*
* WARNING: if you modify this structure, you MUST modify the
* computation of the pad size (ALIGNPAD) accordingly.
*/
STRUCT_BEGIN
STRUCT_FIELD (long,4,UEXC_,pc)
STRUCT_FIELD (long,4,UEXC_,ps)
STRUCT_FIELD (long,4,UEXC_,sar)
STRUCT_FIELD (long,4,UEXC_,vpri)
#ifdef __XTENSA_CALL0_ABI__
STRUCT_FIELD (long,4,UEXC_,a0)
#endif
STRUCT_FIELD (long,4,UEXC_,a2)
STRUCT_FIELD (long,4,UEXC_,a3)
STRUCT_FIELD (long,4,UEXC_,a4)
STRUCT_FIELD (long,4,UEXC_,a5)
#ifdef __XTENSA_CALL0_ABI__
STRUCT_FIELD (long,4,UEXC_,a6)
STRUCT_FIELD (long,4,UEXC_,a7)
STRUCT_FIELD (long,4,UEXC_,a8)
STRUCT_FIELD (long,4,UEXC_,a9)
STRUCT_FIELD (long,4,UEXC_,a10)
STRUCT_FIELD (long,4,UEXC_,a11)
STRUCT_FIELD (long,4,UEXC_,a12)
STRUCT_FIELD (long,4,UEXC_,a13)
STRUCT_FIELD (long,4,UEXC_,a14)
STRUCT_FIELD (long,4,UEXC_,a15)
#endif
STRUCT_FIELD (long,4,UEXC_,exccause) /* NOTE: can probably rid of this one (pass direct) */
#if XCHAL_HAVE_LOOPS
STRUCT_FIELD (long,4,UEXC_,lcount)
STRUCT_FIELD (long,4,UEXC_,lbeg)
STRUCT_FIELD (long,4,UEXC_,lend)
#endif
#if XCHAL_HAVE_MAC16
STRUCT_FIELD (long,4,UEXC_,acclo)
STRUCT_FIELD (long,4,UEXC_,acchi)
STRUCT_AFIELD(long,4,UEXC_,mr, 4)
#endif
/* ALIGNPAD is the 16-byte alignment padding. */
#ifdef __XTENSA_CALL0_ABI__
# define CALL0_ABI 1
#else
# define CALL0_ABI 0
#endif
#define ALIGNPAD ((3 + XCHAL_HAVE_LOOPS*1 + XCHAL_HAVE_MAC16*2 + CALL0_ABI*1) & 3)
#if ALIGNPAD
STRUCT_AFIELD(long,4,UEXC_,pad, ALIGNPAD) /* 16-byte alignment padding */
#endif
/*STRUCT_AFIELD_A(char,1,XCHAL_CPEXTRA_SA_ALIGN,UEXC_,ureg, (XCHAL_CPEXTRA_SA_SIZE+3)&-4)*/ /* not used */
STRUCT_END(UserFrame)
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
/* Check for UserFrameSize small enough not to require rounding...: */
/* Skip 16-byte save area, then 32-byte space for 8 regs of call12
* (which overlaps with 16-byte GCC nested func chaining area),
* then exception stack frame: */
.set UserFrameTotalSize, 16+32+UserFrameSize
/* Greater than 112 bytes? (max range of ADDI, both signs, when aligned to 16 bytes): */
.ifgt UserFrameTotalSize-112
/* Round up to 256-byte multiple to accelerate immediate adds: */
.set UserFrameTotalSize, ((UserFrameTotalSize+255) & 0xFFFFFF00)
.endif
# define ESF_TOTALSIZE UserFrameTotalSize
#endif /* _ASMLANGUAGE || __ASSEMBLER__ */
#if XCHAL_NUM_CONTEXTS > 1
/* Structure of info stored on new context's stack for setup: */
STRUCT_BEGIN
STRUCT_FIELD (long,4,INFO_,sp)
STRUCT_FIELD (long,4,INFO_,arg1)
STRUCT_FIELD (long,4,INFO_,funcpc)
STRUCT_FIELD (long,4,INFO_,prevps)
STRUCT_END(SetupInfo)
#endif
#define KERNELSTACKSIZE 1024
#endif /* _XTRUNTIME_FRAMES_H_ */

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/*
* xtruntime.h -- general C definitions for single-threaded run-time
*
* Copyright (c) 2002-2013 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTRUNTIME_H
#define XTRUNTIME_H
#include <xtensa/config/core.h>
#include <xtensa/config/specreg.h>
#include <xtensa/xtruntime-core-state.h>
#ifndef XTSTR
#define _XTSTR(x) # x
#define XTSTR(x) _XTSTR(x)
#endif
/* _xtos_core_shutoff() flags parameter values: */
#define XTOS_KEEPON_MEM 0x00000100 /* ==PWRCTL_MEM_WAKEUP */
#define XTOS_KEEPON_MEM_SHIFT 8
#define XTOS_KEEPON_DEBUG 0x00001000 /* ==PWRCTL_DEBUG_WAKEUP */
#define XTOS_KEEPON_DEBUG_SHIFT 12
#define XTOS_COREF_PSO 0x00000001 /* do power shutoff */
#define XTOS_COREF_PSO_SHIFT 0
#define _xtos_set_execption_handler _xtos_set_exception_handler /* backward compatibility */
#define _xtos_set_saved_intenable _xtos_ints_on /* backward compatibility */
#define _xtos_clear_saved_intenable _xtos_ints_off /* backward compatibility */
#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
#ifdef __cplusplus
extern "C" {
#endif
/*typedef void (_xtos_timerdelta_func)(int);*/
#ifdef __cplusplus
typedef void (_xtos_handler_func)(...);
#else
typedef void (_xtos_handler_func)();
#endif
typedef _xtos_handler_func *_xtos_handler;
/*
* unsigned XTOS_SET_INTLEVEL(int intlevel);
* This macro sets the current interrupt level.
* The 'intlevel' parameter must be a constant.
* This macro returns a 32-bit value that must be passed to
* XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level.
* XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs
* it restores only PS.INTLEVEL rather than the entire PS register
* and thus is slower.
*/
#if !XCHAL_HAVE_INTERRUPTS
# define XTOS_SET_INTLEVEL(intlevel) 0
# define XTOS_SET_MIN_INTLEVEL(intlevel) 0
# define XTOS_RESTORE_INTLEVEL(restoreval)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)
#elif XCHAL_HAVE_XEA2
/* In XEA2, we can simply safely set PS.INTLEVEL directly: */
/* NOTE: these asm macros don't modify memory, but they are marked
* as such to act as memory access barriers to the compiler because
* these macros are sometimes used to delineate critical sections;
* function calls are natural barriers (the compiler does not know
* whether a function modifies memory) unless declared to be inlined. */
# define XTOS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \
__asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \
: "=a" (__tmp) : : "memory" ); \
__tmp;})
# define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \
__asm__ __volatile__( "rsr %0, " XTSTR(PS) "\n" /* get old (current) PS.INTLEVEL */ \
"movi %2, " XTSTR(intlevel) "\n" \
"extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \
"blt %2, %1, 1f\n" \
"rsil %0, " XTSTR(intlevel) "\n" \
"1:\n" \
: "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \
__tmp;})
# define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \
__asm__ __volatile__( "wsr %0, " XTSTR(PS) " ; rsync\n" \
: : "a" (__tmp) : "memory" ); \
}while(0)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval)
#else
/* In XEA1, we have to rely on INTENABLE register virtualization: */
extern unsigned _xtos_set_vpri( unsigned vpri );
extern unsigned _xtos_vpri_enabled; /* current virtual priority */
# define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
# define XTOS_SET_MIN_INTLEVEL(intlevel) _xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
# define XTOS_RESTORE_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
#endif
/*
* The following macros build upon the above. They are generally used
* instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly.
* They all return a value that can be used with XTOS_RESTORE_INTLEVEL()
* or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore
* the effective interrupt level to what it was before the macro was invoked.
* In XEA2, the DISABLE macros are much faster than the MASK macros
* (in all configs, DISABLE sets the effective interrupt level, whereas MASK
* makes ensures the effective interrupt level is at least the level given
* without lowering it; in XEA2 with INTENABLE virtualization, these macros
* affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial
* MASK semantics).
*
* A typical critical section sequence might be:
* unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS;
* ... critical section ...
* XTOS_RESTORE_INTLEVEL(rval);
*/
/* Enable all interrupts (those activated with _xtos_ints_on()): */
#define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0)
/* Disable low priority level interrupts (they can interact with the OS): */
#define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
#define XTOS_MASK_LOWPRI_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
/* Disable interrupts that can interact with the OS: */
#define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
#define XTOS_MASK_EXCM_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL)
#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */
/* Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE: */
#define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL)
#define XTOS_MASK_LOCK_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL)
#endif
/* Disable ALL interrupts (not for common use, particularly if one's processor
* configuration has high-level interrupts and one cares about their latency): */
#define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15)
extern unsigned int _xtos_ints_off( unsigned int mask );
extern unsigned int _xtos_ints_on( unsigned int mask );
extern unsigned _xtos_set_intlevel( int intlevel );
extern unsigned _xtos_set_min_intlevel( int intlevel );
extern unsigned _xtos_restore_intlevel( unsigned restoreval );
extern unsigned _xtos_restore_just_intlevel( unsigned restoreval );
extern _xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f );
extern _xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg );
extern _xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f );
extern void _xtos_memep_initrams( void );
extern void _xtos_memep_enable( int flags );
/* For use with the tiny LSP (see LSP reference manual). */
#if XCHAL_NUM_INTLEVELS >= 1
extern void _xtos_dispatch_level1_interrupts( void );
#endif
#if XCHAL_NUM_INTLEVELS >= 2
extern void _xtos_dispatch_level2_interrupts( void );
#endif
#if XCHAL_NUM_INTLEVELS >= 3
extern void _xtos_dispatch_level3_interrupts( void );
#endif
#if XCHAL_NUM_INTLEVELS >= 4
extern void _xtos_dispatch_level4_interrupts( void );
#endif
#if XCHAL_NUM_INTLEVELS >= 5
extern void _xtos_dispatch_level5_interrupts( void );
#endif
#if XCHAL_NUM_INTLEVELS >= 6
extern void _xtos_dispatch_level6_interrupts( void );
#endif
/* Deprecated (but kept because they were documented): */
extern unsigned int _xtos_read_ints( void ); /* use xthal_get_interrupt() instead */
extern void _xtos_clear_ints( unsigned int mask ); /* use xthal_set_intclear() instead */
/* Power shut-off related routines. */
extern int _xtos_core_shutoff(unsigned flags);
extern int _xtos_core_save(unsigned flags, XtosCoreState *savearea, void *code);
extern void _xtos_core_restore(unsigned retvalue, XtosCoreState *savearea);
#if XCHAL_NUM_CONTEXTS > 1
extern unsigned _xtos_init_context(int context_num, int stack_size,
_xtos_handler_func *start_func, int arg1);
#endif
/* Deprecated: */
#if XCHAL_NUM_TIMERS > 0
extern void _xtos_timer_0_delta( int cycles );
#endif
#if XCHAL_NUM_TIMERS > 1
extern void _xtos_timer_1_delta( int cycles );
#endif
#if XCHAL_NUM_TIMERS > 2
extern void _xtos_timer_2_delta( int cycles );
#endif
#if XCHAL_NUM_TIMERS > 3
extern void _xtos_timer_3_delta( int cycles );
#endif
#ifdef __cplusplus
}
#endif
#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */
#endif /* XTRUNTIME_H */