IDF release/v4.0 08219f3cf

tools/sdk/include/esp32/esp_intr_alloc.h

@@ -18,6 +18,7 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include "esp_err.h"
+#include "freertos/xtensa_api.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -80,7 +81,10 @@ extern "C" {
 // This is used to provide SystemView with positive IRQ IDs, otherwise sheduler events are not shown properly
 #define ETS_INTERNAL_INTR_SOURCE_OFF		(-ETS_INTERNAL_PROFILING_INTR_SOURCE)
 
-typedef void (*intr_handler_t)(void *arg); 
+#define ESP_INTR_ENABLE(inum)  xt_ints_on((1<<inum))
+#define ESP_INTR_DISABLE(inum) xt_ints_off((1<<inum))
+
+typedef void (*intr_handler_t)(void *arg);
 
 
 typedef struct intr_handle_data_t intr_handle_data_t;
@@ -88,7 +92,7 @@ typedef intr_handle_data_t* intr_handle_t ;
 
 /**
  * @brief Mark an interrupt as a shared interrupt
- * 
+ *
  * This will mark a certain interrupt on the specified CPU as
  * an interrupt that can be used to hook shared interrupt handlers
  * to.
@@ -105,7 +109,7 @@ esp_err_t esp_intr_mark_shared(int intno, int cpu, bool is_in_iram);
 
 /**
  * @brief Reserve an interrupt to be used outside of this framework
- * 
+ *
  * This will mark a certain interrupt on the specified CPU as
  * reserved, not to be allocated for any reason.
  *
@@ -137,7 +141,7 @@ esp_err_t esp_intr_reserve(int intno, int cpu);
  *               choice of interrupts that this routine can choose from. If this value
  *               is 0, it will default to allocating a non-shared interrupt of level
  *               1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
- *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return 
+ *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
  *               from this function with the interrupt disabled.
  * @param handler The interrupt handler. Must be NULL when an interrupt of level >3
  *               is requested, because these types of interrupts aren't C-callable.
@@ -158,7 +162,7 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *ar
  *
  *
  * This essentially does the same as esp_intr_alloc, but allows specifying a register and mask
- * combo. For shared interrupts, the handler is only called if a read from the specified 
+ * combo. For shared interrupts, the handler is only called if a read from the specified
  * register, ANDed with the mask, returns non-zero. By passing an interrupt status register
  * address and a fitting mask, this can be used to accelerate interrupt handling in the case
  * a shared interrupt is triggered; by checking the interrupt statuses first, the code can
@@ -171,7 +175,7 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *ar
  *               choice of interrupts that this routine can choose from. If this value
  *               is 0, it will default to allocating a non-shared interrupt of level
  *               1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
- *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return 
+ *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
  *               from this function with the interrupt disabled.
  * @param intrstatusreg The address of an interrupt status register
  * @param intrstatusmask A mask. If a read of address intrstatusreg has any of the bits
@@ -198,9 +202,9 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
  * If the current core is not the core that registered this interrupt, this routine will be assigned to
  * the core that allocated this interrupt, blocking and waiting until the resource is successfully released.
  *
- * @note 
- * When the handler shares its source with other handlers, the interrupt status 
- * bits it's responsible for should be managed properly before freeing it. see 
+ * @note
+ * When the handler shares its source with other handlers, the interrupt status
+ * bits it's responsible for should be managed properly before freeing it. see
  * ``esp_intr_disable`` for more details. Please do not call this function in ``esp_ipc_call_blocking``.
  *
  * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
@@ -214,7 +218,7 @@ esp_err_t esp_intr_free(intr_handle_t handle);
 
 /**
  * @brief Get CPU number an interrupt is tied to
- * 
+ *
  * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
  *
  * @return The core number where the interrupt is allocated
@@ -223,7 +227,7 @@ int esp_intr_get_cpu(intr_handle_t handle);
 
 /**
  * @brief Get the allocated interrupt for a certain handle
- * 
+ *
  * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
  *
  * @return The interrupt number
@@ -232,13 +236,13 @@ int esp_intr_get_intno(intr_handle_t handle);
 
 /**
  * @brief Disable the interrupt associated with the handle
- * 
- * @note 
+ *
+ * @note
  * 1. For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
  * CPU the interrupt is allocated on. Other interrupts have no such restriction.
- * 2. When several handlers sharing a same interrupt source, interrupt status bits, which are 
+ * 2. When several handlers sharing a same interrupt source, interrupt status bits, which are
  * handled in the handler to be disabled, should be masked before the disabling, or handled
- * in other enabled interrupts properly. Miss of interrupt status handling will cause infinite 
+ * in other enabled interrupts properly. Miss of interrupt status handling will cause infinite
  * interrupt calls and finally system crash.
  *
  * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus