mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
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IDF release/v4.0 08219f3cf
This commit is contained in:
me-no-dev
399
tools/sdk/include/soc/hal/emac.h
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399
tools/sdk/include/soc/hal/emac.h
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@ -0,0 +1,399 @@
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_err.h"
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#include "soc/emac_dma_struct.h"
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#include "soc/emac_mac_struct.h"
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#include "soc/emac_ext_struct.h"
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#define EMAC_MEDIA_INTERFACE_MII (0)
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#define EMAC_MEDIA_INTERFACE_RMII (1)
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#define EMAC_WATCHDOG_ENABLE (0)
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#define EMAC_WATCHDOG_DISABLE (1)
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#define EMAC_JABBER_ENABLE (0)
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#define EMAC_JABBER_DISABLE (1)
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#define EMAC_INTERFRAME_GAP_96BIT (0)
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#define EMAC_INTERFRAME_GAP_88BIT (1)
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#define EMAC_INTERFRAME_GAP_80BIT (2)
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#define EMAC_INTERFRAME_GAP_72BIT (3)
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#define EMAC_INTERFRAME_GAP_64BIT (4)
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#define EMAC_INTERFRAME_GAP_56BIT (5)
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#define EMAC_INTERFRAME_GAP_48BIT (6)
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#define EMAC_INTERFRAME_GAP_40BIT (7)
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#define EMAC_CARRIERSENSE_ENABLE (0)
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#define EMAC_CARRIERSENSE_DISABLE (1)
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#define EMAC_PORT_1000MBPS (0)
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#define EMAC_PORT_10_100MBPS (1)
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#define EMAC_SPEED_10M (0)
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#define EMAC_SPEED_100M (1)
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#define EMAC_RECEIVE_OWN_ENABLE (0)
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#define EMAC_RECEIVE_OWN_DISABLE (1)
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#define EMAC_LOOPBACK_DISABLE (0)
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#define EMAC_LOOPBACK_ENABLE (1)
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#define EMAC_DUPLEX_HALF (0)
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#define EMAC_DUPLEX_FULL (1)
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#define EMAC_CHECKSUM_SW (0)
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#define EMAC_CHECKSUM_HW (1)
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#define EMAC_RETRY_TRANSMISSION_ENABLE (0)
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#define EMAC_RETRY_TRANSMISSION_DISABLE (1)
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#define EMAC_AUTO_PAD_CRC_STRIP_DISABLE (0)
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#define EMAC_AUTO_PAD_CRC_STRIP_ENABLE (1)
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#define EMAC_BACKOFF_LIMIT_10 (0)
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#define EMAC_BACKOFF_LIMIT_8 (1)
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#define EMAC_BACKOFF_LIMIT_4 (2)
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#define EMAC_BACKOFF_LIMIT_1 (3)
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#define EMAC_DEFERRAL_CHECK_DISABLE (0)
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#define EMAC_DEFERRAL_CHECK_ENABLE (1)
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#define EMAC_PREAMBLE_LENGTH_7 (0)
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#define EMAC_PREAMBLE_LENGTH_5 (1)
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#define EMAC_PREAMBLE_LENGTH_3 (2)
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#define EMAC_RECEIVE_ALL_DISABLE (0)
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#define EMAC_RECEIVE_ALL_ENABLE (1)
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#define EMAC_SOURCE_ADDR_FILTER_DISABLE (0)
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#define EMAC_SOURCE_ADDR_FILTER_NORMAL (2)
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#define EMAC_SOURCE_ADDR_FILTER_INVERSE (3)
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#define EMAC_CONTROL_FRAME_BLOCKALL (0)
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#define EMAC_CONTROL_FRAME_FORWARDALL_PAUSE (1)
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#define EMAC_CONTROL_FRAME_FORWARDALL (2)
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#define EMAC_CONTROL_FRAME_FORWARDFILT (3)
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#define EMAC_RECEPT_BROADCAST_ENABLE (0)
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#define EMAC_RECEPT_BROADCAST_DISABLE (1)
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#define EMAC_DEST_ADDR_FILTER_NORMAL (0)
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#define EMAC_DEST_ADDR_FILTER_INVERSE (1)
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#define EMAC_PROMISCUOUS_DISABLE (0)
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#define EMAC_PROMISCUOUS_ENABLE (1)
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#define EMAC_PAUSE_TIME 0x1648
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#define EMAC_ZERO_QUANTA_PAUSE_ENABLE (0)
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#define EMAC_ZERO_QUANTA_PAUSE_DISABLE (1)
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#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_4 (0)
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#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_28 (1)
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#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_144 (2)
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#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_256
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#define EMAC_UNICAST_PAUSE_DETECT_DISABLE (0)
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#define EMAC_UNICAST_PAUSE_DETECT_ENABLE (1)
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#define EMAC_RECEIVE_FLOW_CONTROL_DISABLE (0)
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#define EMAC_RECEIVE_FLOW_CONTROL_ENABLE (1)
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#define EMAC_TRANSMIT_FLOW_CONTROL_DISABLE (0)
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#define EMAC_TRANSMIT_FLOW_CONTROL_ENABLE (1)
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#define EMAC_DROP_TCPIP_CHECKSUM_ERROR_ENABLE (0)
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#define EMAC_DROP_TCPIP_CHECKSUM_ERROR_DISABLE (1)
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#define EMAC_RECEIVE_STORE_FORWARD_DISABLE (0)
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#define EMAC_RECEIVE_STORE_FORWARD_ENABLE (1)
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#define EMAC_FLUSH_RECEIVED_FRAME_ENABLE (0)
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#define EMAC_FLUSH_RECEIVED_FRAME_DISABLE (1)
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#define EMAC_TRANSMIT_STORE_FORWARD_DISABLE (0)
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#define EMAC_TRANSMIT_STORE_FORWARD_ENABLE (1)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_64 (0)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_128 (1)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_192 (2)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_256 (3)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_40 (4)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_32 (5)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_24 (6)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_16 (7)
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#define EMAC_FORWARD_ERROR_FRAME_DISABLE (0)
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#define EMAC_FORWARD_ERROR_FRAME_ENABLE (1)
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#define EMAC_FORWARD_UNDERSIZED_GOOD_FRAME_DISABLE (0)
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#define EMAC_FORWARD_UNDERSIZED_GOOD_FRAME_ENABLE (1)
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#define EMAC_RECEIVE_THRESHOLD_CONTROL_64 (0)
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#define EMAC_RECEIVE_THRESHOLD_CONTROL_32 (1)
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#define EMAC_RECEIVE_THRESHOLD_CONTROL_96 (2)
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#define EMAC_RECEIVE_THRESHOLD_CONTROL_128 (3)
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#define EMAC_OPERATE_SECOND_FRAME_DISABLE (0)
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#define EMAC_OPERATE_SECOND_FRAME_ENABLE (1)
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#define EMAC_MIXED_BURST_DISABLE (0)
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#define EMAC_MIXED_BURST_ENABLE (1)
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#define EMAC_ADDR_ALIGN_BEATS_DISABLE (0)
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#define EMAC_ADDR_ALIGN_BEATS_ENABLE (1)
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#define EMAC_UNUSE_SEPARATE_PBL (0)
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#define EMAC_USE_SEPARATE_PBL (1)
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#define EMAC_DMA_BURST_LENGTH_1BEAT (1)
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#define EMAC_DMA_BURST_LENGTH_2BEAT (2)
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#define EMAC_DMA_BURST_LENGTH_4BEAT (4)
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#define EMAC_DMA_BURST_LENGTH_8BEAT (8)
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#define EMAC_DMA_BURST_LENGTH_16BEAT (16)
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#define EMAC_DMA_BURST_LENGTH_32BEAT (32)
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#define EMAC_ENHANCED_DESCRIPTOR_DISABLE (0)
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#define EMAC_ENHANCED_DESCRIPTOR_ENABLE (1)
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#define EMAC_DMA_ARBITRATION_SCHEME_ROUNDROBIN (0)
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#define EMAC_DMA_ARBITRATION_SCHEME_FIXEDPRIO (1)
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#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_1_1 (0)
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#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_2_1 (1)
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#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_3_1 (2)
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#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_4_1 (3)
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/**
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* @brief Ethernet DMA TX Descriptor
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*
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*/
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typedef struct {
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volatile union {
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struct {
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uint32_t Deferred : 1; /*!< MAC defers before transmission */
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uint32_t UnderflowErr : 1; /*!< DMA encountered an empty transmit buffer */
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uint32_t ExcessiveDeferral : 1; /*!< Excessive deferral of over 24,288 bit times */
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uint32_t CollisionCount : 4; /*!< Number of collisions occurred before transmitted */
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uint32_t VLanFrame : 1; /*!< Transmitted frame is a VLAN-type frame */
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uint32_t ExcessiveCollision : 1; /*!< Transmission aborted after 16 successive collisions */
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uint32_t LateCollision : 1; /*!< Collision occurred after the collision window */
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uint32_t NoCarrier : 1; /*!< Carrier Sense signal from the PHY was not asserted */
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uint32_t LossCarrier : 1; /*!< Loss of carrier occurred during transmission */
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uint32_t PayloadChecksumErr : 1; /*!< Checksum error in TCP/UDP/ICMP datagram payload */
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uint32_t FrameFlushed : 1; /*!< DMA or MTL flushed the frame */
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uint32_t JabberTimeout : 1; /*!< MAC transmitter has experienced a jabber timeout */
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uint32_t ErrSummary : 1; /*!< Error Summary */
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uint32_t IPHeadErr : 1; /*!< IP Header Error */
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uint32_t TxTimestampStatus : 1; /*!< Timestamp captured for the transmit frame */
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uint32_t VLANInsertControl : 2; /*!< VLAN tagging or untagging before transmitting */
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uint32_t SecondAddressChained : 1; /*!< Second address in the descriptor is Next Descriptor address */
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uint32_t TransmitEndRing : 1; /*!< Descriptor list reached its final descriptor */
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uint32_t ChecksumInsertControl : 2; /*!< Control checksum calculation and insertion */
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uint32_t CRCReplacementControl : 1; /*!< Control CRC replace */
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uint32_t TransmitTimestampEnable : 1; /*!< Enable IEEE1588 harware timestamping */
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uint32_t DisablePad : 1; /*!< Control add padding when frame short than 64 bytes */
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uint32_t DisableCRC : 1; /*!< Control append CRC to the end of frame */
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uint32_t FirstSegment : 1; /*!< Buffer contains the first segment of a frame */
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uint32_t LastSegment : 1; /*!< Buffer contains the last segment of a frame */
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uint32_t InterruptOnComplete : 1; /*!< Interrupt after frame transmitted */
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uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */
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};
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uint32_t Value;
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} TDES0;
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union {
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struct {
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uint32_t TransmitBuffer1Size : 13; /*!< First data buffer byte size */
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uint32_t Reserved : 3; /*!< Reserved */
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uint32_t TransmitBuffer2Size : 13; /*!< Second data buffer byte size */
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uint32_t SAInsertControl : 3; /*!< Control MAC add or replace Source Address field */
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};
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uint32_t Value;
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} TDES1;
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uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
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uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
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uint32_t Reserved1; /*!< Reserved */
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uint32_t Reserved2; /*!< Reserved */
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uint32_t TimeStampLow; /*!< Transmit Frame Timestamp Low */
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uint32_t TimeStampHigh; /*!< Transmit Frame Timestamp High */
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} eth_dma_tx_descriptor_t;
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#define EMAC_DMATXDESC_CHECKSUM_BYPASS 0 /*!< Checksum engine bypass */
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#define EMAC_DMATXDESC_CHECKSUM_IPV4HEADER 1 /*!< IPv4 header checksum insertion */
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#define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPSEGMENT 2 /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
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#define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPFULL 3 /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
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/**
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* @brief Ethernet DMA RX Descriptor
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*
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*/
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typedef struct {
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volatile union {
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struct {
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uint32_t ExtendStatusAvailable : 1; /*!< Extended statsu is available in RDES4 */
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uint32_t CRCErr : 1; /*!< CRC error occurred on frame */
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uint32_t DribbleBitErr : 1; /*!< frame contains non int multiple of 8 bits */
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uint32_t ReceiveErr : 1; /*!< Receive error */
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uint32_t ReceiveWatchdogTimeout : 1; /*!< Receive Watchdog timeout */
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uint32_t FrameType : 1; /*!< Ethernet type or IEEE802.3 */
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uint32_t LateCollision : 1; /*!< Late collision occurred during reception */
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uint32_t TSAvailIPChecksumErrGiantFrame : 1; /*!< Timestamp available or IP Checksum error or Giant frame */
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uint32_t LastDescriptor : 1; /*!< Last buffer of the frame */
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uint32_t FirstDescriptor : 1; /*!< First buffer of the frame */
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uint32_t VLANTag : 1; /*!< VLAN Tag: received frame is a VLAN frame */
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uint32_t OverflowErr : 1; /*!< Frame was damaged due to buffer overflow */
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uint32_t LengthErr : 1; /*!< Frame size not matching with length field */
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uint32_t SourceAddrFilterFail : 1; /*!< SA field of frame failed the SA filter */
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uint32_t DescriptorErr : 1; /*!< Frame truncated and DMA doesn't own next descriptor */
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uint32_t ErrSummary : 1; /*!< Error Summary, OR of all errors in RDES */
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uint32_t FrameLength : 14; /*!< Byte length of received frame */
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uint32_t DestinationAddrFilterFail : 1; /*!< Frame failed in the DA Filter in the MAC */
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uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */
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};
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uint32_t Value;
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} RDES0;
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union {
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struct {
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uint32_t ReceiveBuffer1Size : 13; /*!< First data buffer size in bytes */
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uint32_t Reserved1 : 1; /*!< Reserved */
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uint32_t SecondAddressChained : 1; /*!< Seconde address is the Next Descriptor address */
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uint32_t ReceiveEndOfRing : 1; /*!< Descriptor reached its final descriptor */
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uint32_t ReceiveBuffer2Size : 13; /*!< Second data buffer size in bytes */
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uint32_t Reserved : 2; /*!< Reserved */
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uint32_t DisableInterruptOnComplete : 1; /*!< Disable the assertion of interrupt to host */
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};
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uint32_t Value;
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} RDES1;
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uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
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uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
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volatile union {
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struct {
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uint32_t IPPayloadType : 3; /*!< Type of payload in the IP datagram */
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uint32_t IPHeadErr : 1; /*!< IP header error */
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uint32_t IPPayloadErr : 1; /*!< IP payload error */
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uint32_t IPChecksumBypass : 1; /*!< Checksum offload engine is bypassed */
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uint32_t IPv4PacketReceived : 1; /*!< Received packet is an IPv4 packet */
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uint32_t IPv6PacketReceived : 1; /*!< Received packet is an IPv6 packet */
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uint32_t MessageType : 4; /*!< PTP Message Type */
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uint32_t PTPFrameType : 1; /*!< PTP message is over Ethernet or IPv4/IPv6 */
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uint32_t PTPVersion : 1; /*!< Version of PTP protocol */
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uint32_t TimestampDropped : 1; /*!< Timestamp dropped because of overflow */
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uint32_t Reserved1 : 1; /*!< Reserved */
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uint32_t AVPacketReceived : 1; /*!< AV packet is received */
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uint32_t AVTaggedPacketReceived : 1; /*!< AV tagged packet is received */
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uint32_t VLANTagPrioVal : 3; /*!< VLAN tag's user value in the received packekt */
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uint32_t Reserved2 : 3; /*!< Reserved */
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uint32_t Layer3FilterMatch : 1; /*!< Received frame matches one of the enabled Layer3 IP */
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uint32_t Layer4FilterMatch : 1; /*!< Received frame matches one of the enabled Layer4 IP */
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uint32_t Layer3Layer4FilterNumberMatch : 2; /*!< Number of Layer3 and Layer4 Filter that matches the received frame */
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uint32_t Reserved3 : 4; /*!< Reserved */
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};
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uint32_t Value;
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} ExtendedStatus;
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uint32_t Reserved; /*!< Reserved */
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uint32_t TimeStampLow; /*!< Receive frame timestamp low */
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uint32_t TimeStampHigh; /*!< Receive frame timestamp high */
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} eth_dma_rx_descriptor_t;
|
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#define EMAC_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
|
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#define EMAC_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
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#define EMAC_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
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#define EMAC_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
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#define EMAC_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
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#define EMAC_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
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#define EMAC_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
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#define EMAC_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
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#define EMAC_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
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#define EMAC_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
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||||
#define EMAC_DMADESC_OWNER_CPU (0)
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#define EMAC_DMADESC_OWNER_DMA (1)
|
||||
|
||||
typedef struct {
|
||||
emac_mac_dev_t *mac_regs;
|
||||
emac_dma_dev_t *dma_regs;
|
||||
emac_ext_dev_t *ext_regs;
|
||||
uint8_t **rx_buf;
|
||||
uint8_t **tx_buf;
|
||||
void *descriptors;
|
||||
eth_dma_rx_descriptor_t *rx_desc;
|
||||
eth_dma_tx_descriptor_t *tx_desc;
|
||||
} emac_hal_context_t;
|
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||||
void emac_hal_init(emac_hal_context_t *hal, void *descriptors,
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uint8_t **rx_buf, uint8_t **tx_buf);
|
||||
|
||||
void emac_hal_reset_desc_chain(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_lowlevel_init(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_reset(emac_hal_context_t *hal);
|
||||
|
||||
bool emac_hal_is_reset_done(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_csr_clock_range(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_init_mac_default(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_init_dma_default(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_speed(emac_hal_context_t *hal, uint32_t speed);
|
||||
|
||||
void emac_hal_set_duplex(emac_hal_context_t *hal, uint32_t duplex);
|
||||
|
||||
void emac_hal_set_promiscuous(emac_hal_context_t *hal, bool enable);
|
||||
|
||||
bool emac_hal_is_mii_busy(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write);
|
||||
|
||||
void emac_hal_set_phy_data(emac_hal_context_t *hal, uint32_t reg_value);
|
||||
|
||||
uint32_t emac_hal_get_phy_data(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr);
|
||||
|
||||
void emac_hal_start(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_stop(emac_hal_context_t *hal);
|
||||
|
||||
uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length);
|
||||
|
||||
uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *frames_remain);
|
||||
|
||||
void emac_hal_isr(void *arg);
|
||||
|
||||
void emac_hal_tx_complete_cb(void *arg);
|
||||
|
||||
void emac_hal_tx_unavail_cb (void *arg);
|
||||
|
||||
void emac_hal_rx_complete_cb (void *arg);
|
||||
|
||||
void emac_hal_rx_early_cb(void *arg);
|
||||
|
||||
void emac_hal_rx_unavail_cb(void *arg);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
48
tools/sdk/include/soc/hal/esp_flash_err.h
Normal file
48
tools/sdk/include/soc/hal/esp_flash_err.h
Normal file
@ -0,0 +1,48 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_err.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Possible errors returned from esp flash internal functions, these error codes
|
||||
* should be consistent with esp_err_t codes. But in order to make the source
|
||||
* files less dependent to esp_err_t, they use the error codes defined in this
|
||||
* replacable header. This header should ensure the consistency to esp_err_t.
|
||||
*/
|
||||
|
||||
enum {
|
||||
/* These codes should be consistent with esp_err_t errors. However, error codes with the same values are not
|
||||
* allowed in ESP-IDF. This is a workaround in order to not introduce a dependency between the "soc" and
|
||||
* "esp_common" components. The disadvantage is that the output of esp_err_to_name(ESP_ERR_FLASH_SIZE_NOT_MATCH)
|
||||
* will be ESP_ERR_INVALID_SIZE. */
|
||||
ESP_ERR_FLASH_SIZE_NOT_MATCH = ESP_ERR_INVALID_SIZE, ///< The chip doesn't have enough space for the current partition table
|
||||
ESP_ERR_FLASH_NO_RESPONSE = ESP_ERR_INVALID_RESPONSE, ///< Chip did not respond to the command, or timed out.
|
||||
};
|
||||
|
||||
//The ROM code has already taken 1 and 2, to avoid possible conflicts, start from 3.
|
||||
#define ESP_ERR_FLASH_NOT_INITIALISED (ESP_ERR_FLASH_BASE+3) ///< esp_flash_chip_t structure not correctly initialised by esp_flash_init().
|
||||
#define ESP_ERR_FLASH_UNSUPPORTED_HOST (ESP_ERR_FLASH_BASE+4) ///< Requested operation isn't supported via this host SPI bus (chip->spi field).
|
||||
#define ESP_ERR_FLASH_UNSUPPORTED_CHIP (ESP_ERR_FLASH_BASE+5) ///< Requested operation isn't supported by this model of SPI flash chip.
|
||||
#define ESP_ERR_FLASH_PROTECTED (ESP_ERR_FLASH_BASE+6) ///< Write operation failed due to chip's write protection being enabled.
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
28
tools/sdk/include/soc/hal/hal_defs.h
Normal file
28
tools/sdk/include/soc/hal/hal_defs.h
Normal file
@ -0,0 +1,28 @@
|
||||
// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_log.h"
|
||||
|
||||
// platform related stuff
|
||||
|
||||
#define HAL_SWAP32(word) __builtin_bswap32(word)
|
||||
#define HAL_SWAP64(word) __builtin_bswap64(word)
|
||||
|
||||
#define HAL_LOGE(...) ESP_LOGE(__VA_ARGS__)
|
||||
#define HAL_LOGW(...) ESP_LOGW(__VA_ARGS__)
|
||||
#define HAL_LOGI(...) ESP_LOGI(__VA_ARGS__)
|
||||
#define HAL_LOGD(...) ESP_LOGD(__VA_ARGS__)
|
||||
#define HAL_LOGV(...) ESP_LOGV(__VA_ARGS__)
|
||||
239
tools/sdk/include/soc/hal/spi_flash_hal.h
Normal file
239
tools/sdk/include/soc/hal/spi_flash_hal.h
Normal file
@ -0,0 +1,239 @@
|
||||
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The HAL is not public api, don't use in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The HAL layer for SPI Flash (common part)
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/spi_flash_ll.h"
|
||||
#include "hal/spi_types.h"
|
||||
#include "hal/spi_flash_types.h"
|
||||
#include "soc/soc_memory_layout.h"
|
||||
|
||||
/* Hardware host-specific constants */
|
||||
#define SPI_FLASH_HAL_MAX_WRITE_BYTES 64
|
||||
#define SPI_FLASH_HAL_MAX_READ_BYTES 64
|
||||
|
||||
/**
|
||||
* Generic driver context structure for all chips using the SPI peripheral.
|
||||
* Include this into the HEAD of the driver data for other driver
|
||||
* implementations that also use the SPI peripheral.
|
||||
*/
|
||||
typedef struct {
|
||||
spi_dev_t *spi; ///< Pointer to SPI peripheral registers (SP1, SPI2 or SPI3). Set before initialisation.
|
||||
int cs_num; ///< Which cs pin is used, 0-2.
|
||||
int extra_dummy;
|
||||
spi_flash_ll_clock_reg_t clock_conf;
|
||||
} spi_flash_memspi_data_t;
|
||||
|
||||
/// Configuration structure for the SPI driver.
|
||||
typedef struct {
|
||||
spi_host_device_t host_id; ///< SPI peripheral ID.
|
||||
int cs_num; ///< Which cs pin is used, 0-2.
|
||||
bool iomux; ///< Whether the IOMUX is used, used for timing compensation.
|
||||
int input_delay_ns; ///< Input delay on the MISO pin after the launch clock， used for timing compensation.
|
||||
esp_flash_speed_t speed;///< SPI flash clock speed to work at.
|
||||
} spi_flash_memspi_config_t;
|
||||
|
||||
/**
|
||||
* Configure SPI flash hal settings.
|
||||
*
|
||||
* @param data Buffer to hold configured data, the buffer should be in DRAM to be available when cache disabled
|
||||
* @param cfg Configurations to set
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: success
|
||||
* - ESP_ERR_INVALID_ARG: the data buffer is not in the DRAM.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_init(spi_flash_memspi_data_t *data_out, const spi_flash_memspi_config_t *cfg);
|
||||
|
||||
/**
|
||||
* Configure the device-related register before transactions.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
*
|
||||
* @return always return ESP_OK.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver);
|
||||
|
||||
/**
|
||||
* Send an user-defined spi transaction to the device.
|
||||
*
|
||||
* @note This is usually used when the memspi interface doesn't support some
|
||||
* particular commands. Since this function supports timing compensation, it is
|
||||
* also used to receive some data when the frequency is high.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param trans The transaction to send, also holds the received data.
|
||||
*
|
||||
* @return always return ESP_OK.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *driver, spi_flash_trans_t *trans);
|
||||
|
||||
/**
|
||||
* Erase whole flash chip by using the erase chip (C7h) command.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
*/
|
||||
void spi_flash_hal_erase_chip(spi_flash_host_driver_t *driver);
|
||||
|
||||
/**
|
||||
* Erase a specific sector by its start address through the sector erase (20h)
|
||||
* command.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param start_address Start address of the sector to erase.
|
||||
*/
|
||||
void spi_flash_hal_erase_sector(spi_flash_host_driver_t *driver, uint32_t start_address);
|
||||
|
||||
/**
|
||||
* Erase a specific 64KB block by its start address through the 64KB block
|
||||
* erase (D8h) command.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param start_address Start address of the block to erase.
|
||||
*/
|
||||
void spi_flash_hal_erase_block(spi_flash_host_driver_t *driver, uint32_t start_address);
|
||||
|
||||
/**
|
||||
* Program a page of the flash using the page program (02h) command.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param address Address of the page to program
|
||||
* @param buffer Data to program
|
||||
* @param length Size of the buffer in bytes, no larger than ``SPI_FLASH_HAL_MAX_WRITE_BYTES`` (64) bytes.
|
||||
*/
|
||||
void spi_flash_hal_program_page(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length);
|
||||
|
||||
/**
|
||||
* Read from the flash. Call ``spi_flash_hal_configure_host_read_mode`` to
|
||||
* configure the read command before calling this function.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param buffer Buffer to store the read data
|
||||
* @param address Address to read
|
||||
* @param length Length to read, no larger than ``SPI_FLASH_HAL_MAX_READ_BYTES`` (64) bytes.
|
||||
*
|
||||
* @return always return ESP_OK.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len);
|
||||
|
||||
/**
|
||||
* @brief Send the write enable (06h) or write disable (04h) command to the flash chip.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param wp true to enable the write protection, otherwise false.
|
||||
*
|
||||
* @return always return ESP_OK.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *chip_drv, bool wp);
|
||||
|
||||
/**
|
||||
* Check whether the SPI host is idle and can perform other operations.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
*
|
||||
* @return ture if idle, otherwise false.
|
||||
*/
|
||||
bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver);
|
||||
|
||||
/**
|
||||
* @brief Configure the SPI host hardware registers for the specified io mode.
|
||||
*
|
||||
* Note that calling this configures SPI host registers, so if running any
|
||||
* other commands as part of set_io_mode() then these must be run before
|
||||
* calling this function.
|
||||
*
|
||||
* The command value, address length and dummy cycles are configured according
|
||||
* to the format of read commands:
|
||||
*
|
||||
* - command: 8 bits, value set.
|
||||
* - address: 24 bits
|
||||
* - dummy: cycles to compensate the input delay
|
||||
* - out & in data: 0 bits.
|
||||
*
|
||||
* The following commands still need to:
|
||||
*
|
||||
* - Read data: set address value and data (length and contents), no need
|
||||
* to touch command and dummy phases.
|
||||
* - Common read: set command value, address value (or length to 0 if not used)
|
||||
* - Common write: set command value, address value (or length to 0 if not
|
||||
* used), disable dummy phase, and set output data.
|
||||
*
|
||||
* @param driver The driver context
|
||||
* @param io_mode The HW read mode to use
|
||||
* @param addr_bitlen Length of the address phase, in bits
|
||||
* @param dummy_cyclelen_base Base cycles of the dummy phase, some extra dummy cycles may be appended to compensate the timing.
|
||||
* @param command Actual reading command to send to flash chip on the bus.
|
||||
*
|
||||
* @return always return ESP_OK.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_configure_host_io_mode(spi_flash_host_driver_t *driver, uint32_t command, uint32_t addr_bitlen,
|
||||
int dummy_cyclelen_base, esp_flash_io_mode_t io_mode);
|
||||
|
||||
/**
|
||||
* Poll until the last operation is done.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
*/
|
||||
void spi_flash_hal_poll_cmd_done(spi_flash_host_driver_t *driver);
|
||||
|
||||
/**
|
||||
* Check whether the given buffer can be used as the write buffer directly. If 'chip' is connected to the main SPI bus, we can only write directly from
|
||||
* regions that are accessible ith cache disabled. *
|
||||
*
|
||||
* @param driver The driver context
|
||||
* @param p The buffer holding data to send.
|
||||
*
|
||||
* @return True if the buffer can be used to send data, otherwise false.
|
||||
*/
|
||||
static inline bool spi_flash_hal_supports_direct_write(spi_flash_host_driver_t *driver, const void *p)
|
||||
{
|
||||
#ifdef ESP_PLATFORM
|
||||
bool direct_write = ( ((spi_flash_memspi_data_t *)driver->driver_data)->spi != &SPI1
|
||||
|| esp_ptr_in_dram(p) );
|
||||
#else
|
||||
//If it is not on real chips, there is no limitation that the data has to be in DRAM.
|
||||
bool direct_write = true;
|
||||
#endif
|
||||
return direct_write;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether the given buffer can be used as the read buffer directly. If 'chip' is connected to the main SPI bus, we can only read directly from
|
||||
* regions that are accessible ith cache disabled. *
|
||||
*
|
||||
* @param driver The driver context
|
||||
* @param p The buffer to hold the received data.
|
||||
*
|
||||
* @return True if the buffer can be used to receive data, otherwise false.
|
||||
*/
|
||||
static inline bool spi_flash_hal_supports_direct_read(spi_flash_host_driver_t *driver, const void *p)
|
||||
{
|
||||
#ifdef ESP_PLATFORM
|
||||
//currently the driver doesn't support to read through DMA, no word-aligned requirements
|
||||
bool direct_read = ( ((spi_flash_memspi_data_t *)driver->driver_data)->spi != &SPI1
|
||||
|| esp_ptr_in_dram(p) );
|
||||
#else
|
||||
//If it is not on real chips, there is no limitation that the data has to be in DRAM.
|
||||
bool direct_read = true;
|
||||
#endif
|
||||
return direct_read;
|
||||
}
|
||||
342
tools/sdk/include/soc/hal/spi_flash_ll.h
Normal file
342
tools/sdk/include/soc/hal/spi_flash_ll.h
Normal file
@ -0,0 +1,342 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The ll is not public api, don't use in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The Lowlevel layer for SPI Flash
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "soc/spi_periph.h"
|
||||
#include "hal/spi_types.h"
|
||||
#include "hal/spi_flash_types.h"
|
||||
#include <sys/param.h> // For MIN/MAX
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
//Supported clock register values
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_5MHZ ((spi_flash_ll_clock_reg_t){.val=0x0000F1CF}) ///< Clock set to 5 MHz
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_10MHZ ((spi_flash_ll_clock_reg_t){.val=0x000070C7}) ///< Clock set to 10 MHz
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_20MHZ ((spi_flash_ll_clock_reg_t){.val=0x00003043}) ///< Clock set to 20 MHz
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_26MHZ ((spi_flash_ll_clock_reg_t){.val=0x00002002}) ///< Clock set to 26 MHz
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_40MHZ ((spi_flash_ll_clock_reg_t){.val=0x00001001}) ///< Clock set to 40 MHz
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_80MHZ ((spi_flash_ll_clock_reg_t){.val=0x80000000}) ///< Clock set to 80 MHz
|
||||
|
||||
/// Get the start address of SPI peripheral registers by the host ID
|
||||
#define spi_flash_ll_get_hw(host_id) ((host_id)==SPI1_HOST? &SPI1:((host_id)==SPI2_HOST?&SPI2:((host_id)==SPI3_HOST?&SPI3:({abort();(spi_dev_t*)0;}))))
|
||||
|
||||
/// type to store pre-calculated register value in above layers
|
||||
typedef typeof(SPI1.clock) spi_flash_ll_clock_reg_t;
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Control
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Reset peripheral registers before configuration and starting control
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_reset(spi_dev_t *dev)
|
||||
{
|
||||
dev->user.val = 0;
|
||||
dev->ctrl.val = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether the previous operation is done.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return true if last command is done, otherwise false.
|
||||
*/
|
||||
static inline bool spi_flash_ll_cmd_is_done(const spi_dev_t *dev)
|
||||
{
|
||||
return (dev->cmd.val == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* Erase the flash chip.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_erase_chip(spi_dev_t *dev)
|
||||
{
|
||||
dev->cmd.flash_ce = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Erase the sector, the address should be set by spi_flash_ll_set_address.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_erase_sector(spi_dev_t *dev)
|
||||
{
|
||||
dev->ctrl.val = 0;
|
||||
dev->cmd.flash_se = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Erase the block, the address should be set by spi_flash_ll_set_address.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_erase_block(spi_dev_t *dev)
|
||||
{
|
||||
dev->cmd.flash_be = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable write protection for the flash chip.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param wp true to enable the protection, false to disable (write enable).
|
||||
*/
|
||||
static inline void spi_flash_ll_set_write_protect(spi_dev_t *dev, bool wp)
|
||||
{
|
||||
if (wp) {
|
||||
dev->cmd.flash_wrdi = 1;
|
||||
} else {
|
||||
dev->cmd.flash_wren = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the read data from the buffer after ``spi_flash_ll_read`` is done.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param buffer Buffer to hold the output data
|
||||
* @param read_len Length to get out of the buffer
|
||||
*/
|
||||
static inline void spi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
|
||||
{
|
||||
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
|
||||
// If everything is word-aligned, do a faster memcpy
|
||||
memcpy(buffer, (void *)dev->data_buf, read_len);
|
||||
} else {
|
||||
// Otherwise, slow(er) path copies word by word
|
||||
int copy_len = read_len;
|
||||
for (int i = 0; i < (read_len + 3) / 4; i++) {
|
||||
int word_len = MIN(sizeof(uint32_t), copy_len);
|
||||
uint32_t word = dev->data_buf[i];
|
||||
memcpy(buffer, &word, word_len);
|
||||
buffer = (void *)((intptr_t)buffer + word_len);
|
||||
copy_len -= word_len;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Write a word to the data buffer.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param word Data to write at address 0.
|
||||
*/
|
||||
static inline void spi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
|
||||
{
|
||||
dev->data_buf[0] = word;
|
||||
}
|
||||
|
||||
/**
|
||||
* Program a page of the flash chip. Call ``spi_flash_ll_set_address`` before
|
||||
* this to set the address to program.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param buffer Buffer holding the data to program
|
||||
* @param length Length to program.
|
||||
*/
|
||||
static inline void spi_flash_ll_program_page(spi_dev_t *dev, const void *buffer, uint32_t length)
|
||||
{
|
||||
dev->user.usr_dummy = 0;
|
||||
|
||||
// Load data registers, word at a time
|
||||
int num_words = (length + 3) / 4;
|
||||
for (int i = 0; i < num_words; i++) {
|
||||
uint32_t word = 0;
|
||||
uint32_t word_len = MIN(length, sizeof(word));
|
||||
memcpy(&word, buffer, word_len);
|
||||
dev->data_buf[i] = word;
|
||||
length -= word_len;
|
||||
buffer = (void *)((intptr_t)buffer + word_len);
|
||||
}
|
||||
|
||||
dev->cmd.flash_pp = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases,
|
||||
* should be configured before this is called.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_user_start(spi_dev_t *dev)
|
||||
{
|
||||
dev->cmd.usr = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether the host is idle to perform new commands.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return true if the host is idle, otherwise false
|
||||
*/
|
||||
static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev)
|
||||
{
|
||||
return dev->ext2.st != 0;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Configs
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Select which pin to use for the flash
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
|
||||
{
|
||||
dev->pin.cs0_dis = (pin == 0) ? 0 : 1;
|
||||
dev->pin.cs1_dis = (pin == 1) ? 0 : 1;
|
||||
dev->pin.cs2_dis = (pin == 2) ? 0 : 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the read io mode.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param read_mode I/O mode to use in the following transactions.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
|
||||
{
|
||||
typeof (dev->ctrl) ctrl = dev->ctrl;
|
||||
ctrl.val &= ~(SPI_FREAD_QIO_M | SPI_FREAD_QUAD_M | SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M);
|
||||
ctrl.val |= SPI_FASTRD_MODE_M;
|
||||
switch (read_mode) {
|
||||
case SPI_FLASH_FASTRD:
|
||||
//the default option
|
||||
break;
|
||||
case SPI_FLASH_QIO:
|
||||
ctrl.fread_qio = 1;
|
||||
break;
|
||||
case SPI_FLASH_QOUT:
|
||||
ctrl.fread_quad = 1;
|
||||
break;
|
||||
case SPI_FLASH_DIO:
|
||||
ctrl.fread_dio = 1;
|
||||
break;
|
||||
case SPI_FLASH_DOUT:
|
||||
ctrl.fread_dual = 1;
|
||||
break;
|
||||
case SPI_FLASH_SLOWRD:
|
||||
ctrl.fastrd_mode = 0;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
dev->ctrl = ctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set clock frequency to work at.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param clock_val pointer to the clock value to set
|
||||
*/
|
||||
static inline void spi_flash_ll_set_clock(spi_dev_t *dev, spi_flash_ll_clock_reg_t *clock_val)
|
||||
{
|
||||
dev->clock = *clock_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the input length, in bits.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of input, in bits.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user.usr_miso = bitlen > 0;
|
||||
dev->miso_dlen.usr_miso_dbitlen = bitlen ? (bitlen - 1) : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the output length, in bits (not including command, address and dummy
|
||||
* phases)
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of output, in bits.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user.usr_mosi = bitlen > 0;
|
||||
dev->mosi_dlen.usr_mosi_dbitlen = bitlen ? (bitlen - 1) : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the command with fixed length (8 bits).
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param command Command to send
|
||||
*/
|
||||
static inline void spi_flash_ll_set_command8(spi_dev_t *dev, uint8_t command)
|
||||
{
|
||||
dev->user.usr_command = 1;
|
||||
typeof(dev->user2) user2 = {
|
||||
.usr_command_value = command,
|
||||
.usr_command_bitlen = (8 - 1),
|
||||
};
|
||||
dev->user2 = user2;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write...
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of the address, in bits
|
||||
*/
|
||||
static inline void spi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user1.usr_addr_bitlen = (bitlen - 1);
|
||||
dev->user.usr_addr = bitlen ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param addr Address to send
|
||||
*/
|
||||
static inline void spi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
|
||||
{
|
||||
dev->addr = addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the length of dummy cycles.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param dummy_n Cycles of dummy phases
|
||||
*/
|
||||
static inline void spi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
|
||||
{
|
||||
dev->user.usr_dummy = dummy_n ? 1 : 0;
|
||||
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
|
||||
}
|
||||
151
tools/sdk/include/soc/hal/spi_flash_types.h
Normal file
151
tools/sdk/include/soc/hal/spi_flash_types.h
Normal file
@ -0,0 +1,151 @@
|
||||
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <esp_types.h>
|
||||
#include "hal/esp_flash_err.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Definition of a common transaction. Also holds the return value. */
|
||||
typedef struct {
|
||||
uint8_t command; ///< Command to send, always 8bits
|
||||
uint8_t mosi_len; ///< Output data length, in bits
|
||||
uint8_t miso_len; ///< Input data length, in bits
|
||||
uint32_t mosi_data; ///< Output data to slave
|
||||
uint32_t miso_data[2]; ///< [out] Input data from slave, little endian
|
||||
} spi_flash_trans_t;
|
||||
|
||||
/**
|
||||
* @brief SPI flash clock speed values, always refer to them by the enum rather
|
||||
* than the actual value (more speed may be appended into the list).
|
||||
*
|
||||
* A strategy to select the maximum allowed speed is to enumerate from the
|
||||
* ``ESP_FLSH_SPEED_MAX-1`` or highest frequency supported by your flash, and
|
||||
* decrease the speed until the probing success.
|
||||
*/
|
||||
typedef enum {
|
||||
ESP_FLASH_5MHZ = 0, ///< The flash runs under 5MHz
|
||||
ESP_FLASH_10MHZ, ///< The flash runs under 10MHz
|
||||
ESP_FLASH_20MHZ, ///< The flash runs under 20MHz
|
||||
ESP_FLASH_26MHZ, ///< The flash runs under 26MHz
|
||||
ESP_FLASH_40MHZ, ///< The flash runs under 40MHz
|
||||
ESP_FLASH_80MHZ, ///< The flash runs under 80MHz
|
||||
ESP_FLASH_SPEED_MAX, ///< The maximum frequency supported by the host is ``ESP_FLASH_SPEED_MAX-1``.
|
||||
} esp_flash_speed_t;
|
||||
|
||||
///Lowest speed supported by the driver, currently 5 MHz
|
||||
#define ESP_FLASH_SPEED_MIN ESP_FLASH_5MHZ
|
||||
|
||||
/** @brief Mode used for reading from SPI flash */
|
||||
typedef enum {
|
||||
SPI_FLASH_SLOWRD = 0, ///< Data read using single I/O, some limits on speed
|
||||
SPI_FLASH_FASTRD, ///< Data read using single I/O, no limit on speed
|
||||
SPI_FLASH_DOUT, ///< Data read using dual I/O
|
||||
SPI_FLASH_DIO, ///< Both address & data transferred using dual I/O
|
||||
SPI_FLASH_QOUT, ///< Data read using quad I/O
|
||||
SPI_FLASH_QIO, ///< Both address & data transferred using quad I/O
|
||||
|
||||
SPI_FLASH_READ_MODE_MAX, ///< The fastest io mode supported by the host is ``ESP_FLASH_READ_MODE_MAX-1``.
|
||||
} esp_flash_io_mode_t;
|
||||
|
||||
///Slowest io mode supported by ESP32, currently SlowRd
|
||||
#define SPI_FLASH_READ_MODE_MIN SPI_FLASH_SLOWRD
|
||||
|
||||
struct spi_flash_host_driver_t;
|
||||
typedef struct spi_flash_host_driver_t spi_flash_host_driver_t;
|
||||
|
||||
/** Host driver configuration and context structure. */
|
||||
struct spi_flash_host_driver_t {
|
||||
/**
|
||||
* Configuration and static data used by the specific host driver. The type
|
||||
* is determined by the host driver.
|
||||
*/
|
||||
void *driver_data;
|
||||
/**
|
||||
* Configure the device-related register before transactions. This saves
|
||||
* some time to re-configure those registers when we send continuously
|
||||
*/
|
||||
esp_err_t (*dev_config)(spi_flash_host_driver_t *driver);
|
||||
/**
|
||||
* Send an user-defined spi transaction to the device.
|
||||
*/
|
||||
esp_err_t (*common_command)(spi_flash_host_driver_t *driver, spi_flash_trans_t *t);
|
||||
/**
|
||||
* Read flash ID.
|
||||
*/
|
||||
esp_err_t (*read_id)(spi_flash_host_driver_t *driver, uint32_t *id);
|
||||
/**
|
||||
* Erase whole flash chip.
|
||||
*/
|
||||
void (*erase_chip)(spi_flash_host_driver_t *driver);
|
||||
/**
|
||||
* Erase a specific sector by its start address.
|
||||
*/
|
||||
void (*erase_sector)(spi_flash_host_driver_t *driver, uint32_t start_address);
|
||||
/**
|
||||
* Erase a specific block by its start address.
|
||||
*/
|
||||
void (*erase_block)(spi_flash_host_driver_t *driver, uint32_t start_address);
|
||||
/**
|
||||
* Read the status of the flash chip.
|
||||
*/
|
||||
esp_err_t (*read_status)(spi_flash_host_driver_t *driver, uint8_t *out_sr);
|
||||
/**
|
||||
* Disable write protection.
|
||||
*/
|
||||
esp_err_t (*set_write_protect)(spi_flash_host_driver_t *driver, bool wp);
|
||||
/**
|
||||
* Program a page of the flash. Check ``max_write_bytes`` for the maximum allowed writing length.
|
||||
*/
|
||||
void (*program_page)(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length);
|
||||
/** Check whether need to allocate new buffer to write */
|
||||
bool (*supports_direct_write)(spi_flash_host_driver_t *driver, const void *p);
|
||||
/** Check whether need to allocate new buffer to read */
|
||||
bool (*supports_direct_read)(spi_flash_host_driver_t *driver, const void *p);
|
||||
/** maximum length of program_page */
|
||||
int max_write_bytes;
|
||||
/**
|
||||
* Read data from the flash. Check ``max_read_bytes`` for the maximum allowed reading length.
|
||||
*/
|
||||
esp_err_t (*read)(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len);
|
||||
/** maximum length of read */
|
||||
int max_read_bytes;
|
||||
/**
|
||||
* Check whether the host is idle to perform new operations.
|
||||
*/
|
||||
bool (*host_idle)(spi_flash_host_driver_t *driver);
|
||||
/**
|
||||
* Configure the host to work at different read mode. Responsible to compensate the timing and set IO mode.
|
||||
*/
|
||||
esp_err_t (*configure_host_io_mode)(spi_flash_host_driver_t *driver, uint32_t command,
|
||||
uint32_t addr_bitlen, int dummy_bitlen_base,
|
||||
esp_flash_io_mode_t io_mode);
|
||||
/**
|
||||
* Internal use, poll the HW until the last operation is done.
|
||||
*/
|
||||
void (*poll_cmd_done)(spi_flash_host_driver_t *driver);
|
||||
/**
|
||||
* For some host (SPI1), they are shared with a cache. When the data is
|
||||
* modified, the cache needs to be flushed. Left NULL if not supported.
|
||||
*/
|
||||
esp_err_t (*flush_cache)(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size);
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
222
tools/sdk/include/soc/hal/spi_hal.h
Normal file
222
tools/sdk/include/soc/hal/spi_hal.h
Normal file
@ -0,0 +1,222 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The hal is not public api, don't use in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The HAL layer for SPI master (common part)
|
||||
|
||||
// SPI HAL usages:
|
||||
// 1. initialize the bus
|
||||
// 2. initialize the DMA descriptors if DMA used
|
||||
// 3. setup the clock speed (since this takes long time)
|
||||
// 4. call setup_device to update parameters for the specific device
|
||||
// 5. call setup_trans to update parameters for the specific transaction
|
||||
// 6. prepare data to send, and prepare the receiving buffer
|
||||
// 7. trigger user defined SPI transaction to start
|
||||
// 8. wait until the user transaction is done
|
||||
// 9. fetch the received data
|
||||
// Parameter to be updated only during ``setup_device`` will be highlighted in the
|
||||
// field comments.
|
||||
|
||||
#pragma once
|
||||
#include "hal/spi_ll.h"
|
||||
#include <esp_err.h>
|
||||
#include "soc/lldesc.h"
|
||||
|
||||
/**
|
||||
* Timing configuration structure that should be calculated by
|
||||
* ``spi_hal_setup_clock`` at initialization and hold. Filled into the
|
||||
* ``timing_conf`` member of the context of HAL before setup a device.
|
||||
*/
|
||||
typedef struct {
|
||||
spi_ll_clock_val_t clock_reg; ///< Register value used by the LL layer
|
||||
int timing_dummy; ///< Extra dummy needed to compensate the timing
|
||||
int timing_miso_delay; ///< Extra miso delay clocks to compensate the timing
|
||||
} spi_hal_timing_conf_t;
|
||||
|
||||
/**
|
||||
* Context that should be maintained by both the driver and the HAL.
|
||||
*/
|
||||
typedef struct {
|
||||
/* configured by driver at initialization, don't touch */
|
||||
spi_dev_t *hw; ///< Beginning address of the peripheral registers.
|
||||
/* should be configured by driver at initialization */
|
||||
lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use.
|
||||
/*
|
||||
* Device specific, all these parameters will be updated to the peripheral
|
||||
* only when ``spi_hal_setup_device``. They may not get updated when
|
||||
* ``spi_hal_setup_trans``.
|
||||
*/
|
||||
int mode; ///< SPI mode, device specific
|
||||
int cs_setup; ///< Setup time of CS active edge before the first SPI clock, device specific
|
||||
int cs_hold; ///< Hold time of CS inactive edge after the last SPI clock, device specific
|
||||
int cs_pin_id; ///< CS pin to use, 0-2, otherwise all the CS pins are not used. Device specific
|
||||
spi_hal_timing_conf_t *timing_conf; /**< Pointer to an structure holding
|
||||
* the pre-calculated timing configuration for the device at initialization,
|
||||
* device specific
|
||||
*/
|
||||
struct {
|
||||
uint32_t sio : 1; ///< Whether to use SIO mode, device specific
|
||||
uint32_t half_duplex : 1; ///< Whether half duplex mode is used, device specific
|
||||
uint32_t tx_lsbfirst : 1; ///< Whether LSB is sent first for TX data, device specific
|
||||
uint32_t rx_lsbfirst : 1; ///< Whether LSB is received first for RX data, device specific
|
||||
uint32_t dma_enabled : 1; ///< Whether the DMA is enabled, do not update after initialization
|
||||
uint32_t no_compensate : 1; ///< No need to add dummy to compensate the timing, device specific
|
||||
#ifdef SOC_SPI_SUPPORT_AS_CS
|
||||
uint32_t as_cs : 1; ///< Whether to toggle the CS while the clock toggles, device specific
|
||||
#endif
|
||||
uint32_t positive_cs : 1; ///< Whether the postive CS feature is abled, device specific
|
||||
};//boolean configurations
|
||||
|
||||
/*
|
||||
* Transaction specific (data), all these parameters will be updated to the
|
||||
* peripheral every transaction.
|
||||
*/
|
||||
uint16_t cmd; ///< Command value to be sent
|
||||
int cmd_bits; ///< Length (in bits) of the command phase
|
||||
int addr_bits; ///< Length (in bits) of the address phase
|
||||
int dummy_bits; ///< Base length (in bits) of the dummy phase. Note when the compensation is enabled, some extra dummy bits may be appended.
|
||||
int tx_bitlen; ///< TX length, in bits
|
||||
int rx_bitlen; ///< RX length, in bits
|
||||
uint64_t addr; ///< Address value to be sent
|
||||
uint8_t *send_buffer; ///< Data to be sent
|
||||
uint8_t *rcv_buffer; ///< Buffer to hold the receive data.
|
||||
spi_ll_io_mode_t io_mode; ///< IO mode of the master
|
||||
|
||||
} spi_hal_context_t;
|
||||
|
||||
/**
|
||||
* Init the peripheral and the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
|
||||
*/
|
||||
void spi_hal_init(spi_hal_context_t *hal, int host_id);
|
||||
|
||||
/**
|
||||
* Deinit the peripheral (and the context if needed).
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_deinit(spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Setup device-related configurations according to the settings in the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_setup_device(const spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Setup transaction related configurations according to the settings in the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_setup_trans(const spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Prepare the data for the current transaction.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_prepare_data(const spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Trigger start a user-defined transaction.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_user_start(const spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Check whether the transaction is done (trans_done is set).
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
bool spi_hal_usr_is_done(const spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Post transaction operations, mainly fetch data from the buffer.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_fetch_result(const spi_hal_context_t *hal);
|
||||
|
||||
/*----------------------------------------------------------
|
||||
* Utils
|
||||
* ---------------------------------------------------------*/
|
||||
/**
|
||||
* Get the configuration of clock and timing. The configuration will be used when ``spi_hal_setup_device``.
|
||||
*
|
||||
* It is highly suggested to do this at initialization, since it takes long time.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
* @param speed_hz Desired frequency.
|
||||
* @param duty_cycle Desired duty cycle of SPI clock
|
||||
* @param use_gpio true if the GPIO matrix is used, otherwise false
|
||||
* @param input_delay_ns Maximum delay between SPI launch clock and the data to
|
||||
* be valid. This is used to compensate/calculate the maximum frequency
|
||||
* allowed. Left 0 if not known.
|
||||
* @param out_freq Output of the actual frequency, left NULL if not required.
|
||||
* @param timing_conf Output of the timing configuration.
|
||||
*
|
||||
* @return ESP_OK if desired is available, otherwise fail.
|
||||
*/
|
||||
esp_err_t spi_hal_get_clock_conf(const spi_hal_context_t *hal, int speed_hz, int duty_cycle, bool use_gpio, int input_delay_ns, int *out_freq, spi_hal_timing_conf_t *timing_conf);
|
||||
|
||||
/**
|
||||
* Get the frequency actual used.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
* @param fapb APB clock frequency.
|
||||
* @param hz Desired frequencyc.
|
||||
* @param duty_cycle Desired duty cycle.
|
||||
*/
|
||||
int spi_hal_master_cal_clock(int fapb, int hz, int duty_cycle);
|
||||
|
||||
/**
|
||||
* Get the timing configuration for given parameters.
|
||||
*
|
||||
* @param eff_clk Actual SPI clock frequency
|
||||
* @param gpio_is_used true if the GPIO matrix is used, otherwise false.
|
||||
* @param input_delay_ns Maximum delay between SPI launch clock and the data to
|
||||
* be valid. This is used to compensate/calculate the maximum frequency
|
||||
* allowed. Left 0 if not known.
|
||||
* @param dummy_n Dummy cycles required to correctly read the data.
|
||||
* @param miso_delay_n suggested delay on the MISO line, in APB clocks.
|
||||
*/
|
||||
void spi_hal_cal_timing(int eff_clk, bool gpio_is_used, int input_delay_ns, int *dummy_n, int *miso_delay_n);
|
||||
|
||||
/**
|
||||
* Get the maximum frequency allowed to read if no compensation is used.
|
||||
*
|
||||
* @param gpio_is_used true if the GPIO matrix is used, otherwise false.
|
||||
* @param input_delay_ns Maximum delay between SPI launch clock and the data to
|
||||
* be valid. This is used to compensate/calculate the maximum frequency
|
||||
* allowed. Left 0 if not known.
|
||||
*/
|
||||
int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns);
|
||||
|
||||
864
tools/sdk/include/soc/hal/spi_ll.h
Normal file
864
tools/sdk/include/soc/hal/spi_ll.h
Normal file
@ -0,0 +1,864 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The hal is not public api, don't use in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The LL layer for ESP32 SPI register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/hal_defs.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include "esp32/rom/lldesc.h"
|
||||
#include <string.h>
|
||||
#include <esp_types.h>
|
||||
#include <stdlib.h> //for abs()
|
||||
|
||||
/// Registers to reset during initialization. Don't use in app.
|
||||
#define SPI_LL_RST_MASK (SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST)
|
||||
/// Interrupt not used. Don't use in app.
|
||||
#define SPI_LL_UNUSED_INT_MASK (SPI_INT_EN | SPI_SLV_WR_STA_DONE | SPI_SLV_RD_STA_DONE | SPI_SLV_WR_BUF_DONE | SPI_SLV_RD_BUF_DONE)
|
||||
/// Swap the bit order to its correct place to send
|
||||
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
|
||||
|
||||
/**
|
||||
* The data structure holding calculated clock configuration. Since the
|
||||
* calculation needs long time, it should be calculated during initialization and
|
||||
* stored somewhere to be quickly used.
|
||||
*/
|
||||
typedef uint32_t spi_ll_clock_val_t;
|
||||
|
||||
/** IO modes supported by the master. */
|
||||
typedef enum {
|
||||
SPI_LL_IO_MODE_NORMAL = 0, ///< 1-bit mode for all phases
|
||||
SPI_LL_IO_MODE_DIO, ///< 2-bit mode for address and data phases, 1-bit mode for command phase
|
||||
SPI_LL_IO_MODE_DUAL, ///< 2-bit mode for data phases only, 1-bit mode for command and address phases
|
||||
SPI_LL_IO_MODE_QIO, ///< 4-bit mode for address and data phases, 1-bit mode for command phase
|
||||
SPI_LL_IO_MODE_QUAD, ///< 4-bit mode for data phases only, 1-bit mode for command and address phases
|
||||
} spi_ll_io_mode_t;
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Control
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Initialize SPI peripheral (master).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_master_init(spi_dev_t *hw)
|
||||
{
|
||||
//Reset DMA
|
||||
hw->dma_conf.val |= SPI_LL_RST_MASK;
|
||||
hw->dma_out_link.start = 0;
|
||||
hw->dma_in_link.start = 0;
|
||||
hw->dma_conf.val &= ~SPI_LL_RST_MASK;
|
||||
//Reset timing
|
||||
hw->ctrl2.val = 0;
|
||||
|
||||
//use all 64 bytes of the buffer
|
||||
hw->user.usr_miso_highpart = 0;
|
||||
hw->user.usr_mosi_highpart = 0;
|
||||
|
||||
//Disable unneeded ints
|
||||
hw->slave.val &= ~SPI_LL_UNUSED_INT_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize SPI peripheral (slave).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_slave_init(spi_dev_t *hw)
|
||||
{
|
||||
//Configure slave
|
||||
hw->clock.val = 0;
|
||||
hw->user.val = 0;
|
||||
hw->ctrl.val = 0;
|
||||
hw->slave.wr_rd_buf_en = 1; //no sure if needed
|
||||
hw->user.doutdin = 1; //we only support full duplex
|
||||
hw->user.sio = 0;
|
||||
hw->slave.slave_mode = 1;
|
||||
hw->dma_conf.val |= SPI_LL_RST_MASK;
|
||||
hw->dma_out_link.start = 0;
|
||||
hw->dma_in_link.start = 0;
|
||||
hw->dma_conf.val &= ~SPI_LL_RST_MASK;
|
||||
hw->slave.sync_reset = 1;
|
||||
hw->slave.sync_reset = 0;
|
||||
//use all 64 bytes of the buffer
|
||||
hw->user.usr_miso_highpart = 0;
|
||||
hw->user.usr_mosi_highpart = 0;
|
||||
|
||||
//Disable unneeded ints
|
||||
hw->slave.val &= ~SPI_LL_UNUSED_INT_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Reset TX and RX DMAs.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_reset_dma(spi_dev_t *hw)
|
||||
{
|
||||
//Reset DMA peripheral
|
||||
hw->dma_conf.val |= SPI_LL_RST_MASK;
|
||||
hw->dma_out_link.start = 0;
|
||||
hw->dma_in_link.start = 0;
|
||||
hw->dma_conf.val &= ~SPI_LL_RST_MASK;
|
||||
hw->dma_conf.out_data_burst_en = 1;
|
||||
hw->dma_conf.indscr_burst_en = 1;
|
||||
hw->dma_conf.outdscr_burst_en = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Start RX DMA.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param addr Address of the beginning DMA descriptor.
|
||||
*/
|
||||
static inline void spi_ll_rxdma_start(spi_dev_t *hw, lldesc_t *addr)
|
||||
{
|
||||
hw->dma_in_link.addr = (int) addr & 0xFFFFF;
|
||||
hw->dma_in_link.start = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Start TX DMA.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param addr Address of the beginning DMA descriptor.
|
||||
*/
|
||||
static inline void spi_ll_txdma_start(spi_dev_t *hw, lldesc_t *addr)
|
||||
{
|
||||
hw->dma_out_link.addr = (int) addr & 0xFFFFF;
|
||||
hw->dma_out_link.start = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to SPI buffer.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param buffer_to_send Data address to copy to the buffer.
|
||||
* @param bitlen Length to copy, in bits.
|
||||
*/
|
||||
static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen)
|
||||
{
|
||||
for (int x = 0; x < bitlen; x += 32) {
|
||||
//Use memcpy to get around alignment issues for txdata
|
||||
uint32_t word;
|
||||
memcpy(&word, &buffer_to_send[x / 8], 4);
|
||||
hw->data_buf[(x / 32)] = word;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Read from SPI buffer.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param buffer_to_rcv Address to copy buffer data to.
|
||||
* @param bitlen Length to copy, in bits.
|
||||
*/
|
||||
static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen)
|
||||
{
|
||||
for (int x = 0; x < bitlen; x += 32) {
|
||||
//Do a memcpy to get around possible alignment issues in rx_buffer
|
||||
uint32_t word = hw->data_buf[x / 32];
|
||||
int len = bitlen - x;
|
||||
if (len > 32) {
|
||||
len = 32;
|
||||
}
|
||||
memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether user-defined transaction is done.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return true if transaction is done, otherwise false.
|
||||
*/
|
||||
static inline bool spi_ll_usr_is_done(spi_dev_t *hw)
|
||||
{
|
||||
return hw->slave.trans_done;
|
||||
}
|
||||
|
||||
/**
|
||||
* Trigger start of user-defined transaction.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_user_start(spi_dev_t *hw)
|
||||
{
|
||||
hw->cmd.usr = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get current running command bit-mask. (Preview)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command.
|
||||
*/
|
||||
static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw)
|
||||
{
|
||||
return hw->cmd.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the trans_done interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_disable_int(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.trans_inten = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Clear the trans_done interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.trans_done = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the trans_done interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_set_int_stat(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.trans_done = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the trans_done interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_enable_int(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.trans_inten = 1;
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Configs: mode
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Enable/disable the postive-cs feature.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param cs One of the CS (0-2) to enable/disable the feature.
|
||||
* @param pos_cs true to enable the feature, otherwise disable (default).
|
||||
*/
|
||||
static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_cs)
|
||||
{
|
||||
if (pos_cs) {
|
||||
hw->pin.master_cs_pol |= (1 << cs);
|
||||
} else {
|
||||
hw->pin.master_cs_pol &= (1 << cs);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable the LSBFIRST feature for TX data.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param lsbfirst true if LSB of TX data to be sent first, otherwise MSB is sent first (default).
|
||||
*/
|
||||
static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst)
|
||||
{
|
||||
hw->ctrl.wr_bit_order = lsbfirst;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable the LSBFIRST feature for RX data.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param lsbfirst true if first bit received as LSB, otherwise as MSB (default).
|
||||
*/
|
||||
static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst)
|
||||
{
|
||||
hw->ctrl.rd_bit_order = lsbfirst;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set SPI mode for the peripheral as master.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode SPI mode to work at, 0-3.
|
||||
*/
|
||||
static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode)
|
||||
{
|
||||
//Configure polarity
|
||||
if (mode == 0) {
|
||||
hw->pin.ck_idle_edge = 0;
|
||||
hw->user.ck_out_edge = 0;
|
||||
} else if (mode == 1) {
|
||||
hw->pin.ck_idle_edge = 0;
|
||||
hw->user.ck_out_edge = 1;
|
||||
} else if (mode == 2) {
|
||||
hw->pin.ck_idle_edge = 1;
|
||||
hw->user.ck_out_edge = 1;
|
||||
} else if (mode == 3) {
|
||||
hw->pin.ck_idle_edge = 1;
|
||||
hw->user.ck_out_edge = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set SPI mode for the peripheral as slave.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode SPI mode to work at, 0-3.
|
||||
*/
|
||||
static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma_used)
|
||||
{
|
||||
if (mode == 0) {
|
||||
//The timing needs to be fixed to meet the requirements of DMA
|
||||
hw->pin.ck_idle_edge = 1;
|
||||
hw->user.ck_i_edge = 0;
|
||||
hw->ctrl2.miso_delay_mode = 0;
|
||||
hw->ctrl2.miso_delay_num = 0;
|
||||
hw->ctrl2.mosi_delay_mode = 2;
|
||||
hw->ctrl2.mosi_delay_num = 2;
|
||||
} else if (mode == 1) {
|
||||
hw->pin.ck_idle_edge = 1;
|
||||
hw->user.ck_i_edge = 1;
|
||||
hw->ctrl2.miso_delay_mode = 2;
|
||||
hw->ctrl2.miso_delay_num = 0;
|
||||
hw->ctrl2.mosi_delay_mode = 0;
|
||||
hw->ctrl2.mosi_delay_num = 0;
|
||||
} else if (mode == 2) {
|
||||
//The timing needs to be fixed to meet the requirements of DMA
|
||||
hw->pin.ck_idle_edge = 0;
|
||||
hw->user.ck_i_edge = 1;
|
||||
hw->ctrl2.miso_delay_mode = 0;
|
||||
hw->ctrl2.miso_delay_num = 0;
|
||||
hw->ctrl2.mosi_delay_mode = 1;
|
||||
hw->ctrl2.mosi_delay_num = 2;
|
||||
} else if (mode == 3) {
|
||||
hw->pin.ck_idle_edge = 0;
|
||||
hw->user.ck_i_edge = 0;
|
||||
hw->ctrl2.miso_delay_mode = 1;
|
||||
hw->ctrl2.miso_delay_num = 0;
|
||||
hw->ctrl2.mosi_delay_mode = 0;
|
||||
hw->ctrl2.mosi_delay_num = 0;
|
||||
}
|
||||
|
||||
/* Silicon issues exists in mode 0 and 2 with DMA, change clock phase to
|
||||
* avoid dma issue. This will cause slave output to appear at most half a
|
||||
* spi clock before
|
||||
*/
|
||||
if (dma_used) {
|
||||
if (mode == 0) {
|
||||
hw->pin.ck_idle_edge = 0;
|
||||
hw->user.ck_i_edge = 1;
|
||||
hw->ctrl2.miso_delay_mode = 0;
|
||||
hw->ctrl2.miso_delay_num = 2;
|
||||
hw->ctrl2.mosi_delay_mode = 0;
|
||||
hw->ctrl2.mosi_delay_num = 3;
|
||||
} else if (mode == 2) {
|
||||
hw->pin.ck_idle_edge = 1;
|
||||
hw->user.ck_i_edge = 0;
|
||||
hw->ctrl2.miso_delay_mode = 0;
|
||||
hw->ctrl2.miso_delay_num = 2;
|
||||
hw->ctrl2.mosi_delay_mode = 0;
|
||||
hw->ctrl2.mosi_delay_num = 3;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set SPI to work in full duplex or half duplex mode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param half_duplex true to work in half duplex mode, otherwise in full duplex mode.
|
||||
*/
|
||||
static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex)
|
||||
{
|
||||
hw->user.doutdin = !half_duplex;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set SPI to work in SIO mode or not.
|
||||
*
|
||||
* SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param sio_mode true to work in SIO mode, otherwise false.
|
||||
*/
|
||||
static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode)
|
||||
{
|
||||
hw->user.sio = sio_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* Configure the io mode for the master to work at.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param io_mode IO mode to work at, see ``spi_ll_io_mode_t``.
|
||||
*/
|
||||
static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_mode)
|
||||
{
|
||||
hw->ctrl.val &= ~(SPI_FREAD_DUAL | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_QIO);
|
||||
hw->user.val &= ~(SPI_FWRITE_DUAL | SPI_FWRITE_QUAD | SPI_FWRITE_DIO | SPI_FWRITE_QIO);
|
||||
switch (io_mode) {
|
||||
case SPI_LL_IO_MODE_DIO:
|
||||
hw->ctrl.fread_dio = 1;
|
||||
hw->user.fwrite_dio = 1;
|
||||
break;
|
||||
case SPI_LL_IO_MODE_DUAL:
|
||||
hw->ctrl.fread_dual = 1;
|
||||
hw->user.fwrite_dual = 1;
|
||||
break;
|
||||
case SPI_LL_IO_MODE_QIO:
|
||||
hw->ctrl.fread_qio = 1;
|
||||
hw->user.fwrite_qio = 1;
|
||||
break;
|
||||
case SPI_LL_IO_MODE_QUAD:
|
||||
hw->ctrl.fread_quad = 1;
|
||||
hw->user.fwrite_quad = 1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
};
|
||||
if (io_mode != SPI_LL_IO_MODE_NORMAL) {
|
||||
hw->ctrl.fastrd_mode = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Select one of the CS to use in current transaction.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param cs_id The cs to use, 0-2, otherwise none of them is used.
|
||||
*/
|
||||
static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id)
|
||||
{
|
||||
hw->pin.cs0_dis = (cs_id == 0) ? 0 : 1;
|
||||
hw->pin.cs1_dis = (cs_id == 1) ? 0 : 1;
|
||||
hw->pin.cs2_dis = (cs_id == 2) ? 0 : 1;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Configs: parameters
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Set the clock for master by stored value.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param val stored clock configuration calculated before (by ``spi_ll_cal_clock``).
|
||||
*/
|
||||
static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, spi_ll_clock_val_t *val)
|
||||
{
|
||||
hw->clock.val = *(uint32_t *)val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the frequency of given dividers. Don't use in app.
|
||||
*
|
||||
* @param fapb APB clock of the system.
|
||||
* @param pre Pre devider.
|
||||
* @param n main divider.
|
||||
*
|
||||
* @return Frequency of given dividers.
|
||||
*/
|
||||
static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n)
|
||||
{
|
||||
return (fapb / (pre * n));
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate the nearest frequency avaliable for master.
|
||||
*
|
||||
* @param fapb APB clock of the system.
|
||||
* @param hz Frequncy desired.
|
||||
* @param duty_cycle Duty cycle desired.
|
||||
* @param out_reg Output address to store the calculated clock configurations for the return frequency.
|
||||
*
|
||||
* @return Actual (nearest) frequency.
|
||||
*/
|
||||
static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg)
|
||||
{
|
||||
typeof(SPI1.clock) reg;
|
||||
int eff_clk;
|
||||
|
||||
//In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value.
|
||||
if (hz > ((fapb / 4) * 3)) {
|
||||
//Using Fapb directly will give us the best result here.
|
||||
reg.clkcnt_l = 0;
|
||||
reg.clkcnt_h = 0;
|
||||
reg.clkcnt_n = 0;
|
||||
reg.clkdiv_pre = 0;
|
||||
reg.clk_equ_sysclk = 1;
|
||||
eff_clk = fapb;
|
||||
} else {
|
||||
//For best duty cycle resolution, we want n to be as close to 32 as possible, but
|
||||
//we also need a pre/n combo that gets us as close as possible to the intended freq.
|
||||
//To do this, we bruteforce n and calculate the best pre to go along with that.
|
||||
//If there's a choice between pre/n combos that give the same result, use the one
|
||||
//with the higher n.
|
||||
int pre, n, h, l;
|
||||
int bestn = -1;
|
||||
int bestpre = -1;
|
||||
int besterr = 0;
|
||||
int errval;
|
||||
for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse.
|
||||
//Effectively, this does pre=round((fapb/n)/hz).
|
||||
pre = ((fapb / n) + (hz / 2)) / hz;
|
||||
if (pre <= 0) {
|
||||
pre = 1;
|
||||
}
|
||||
if (pre > 8192) {
|
||||
pre = 8192;
|
||||
}
|
||||
errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz);
|
||||
if (bestn == -1 || errval <= besterr) {
|
||||
besterr = errval;
|
||||
bestn = n;
|
||||
bestpre = pre;
|
||||
}
|
||||
}
|
||||
|
||||
n = bestn;
|
||||
pre = bestpre;
|
||||
l = n;
|
||||
//This effectively does round((duty_cycle*n)/256)
|
||||
h = (duty_cycle * n + 127) / 256;
|
||||
if (h <= 0) {
|
||||
h = 1;
|
||||
}
|
||||
|
||||
reg.clk_equ_sysclk = 0;
|
||||
reg.clkcnt_n = n - 1;
|
||||
reg.clkdiv_pre = pre - 1;
|
||||
reg.clkcnt_h = h - 1;
|
||||
reg.clkcnt_l = l - 1;
|
||||
eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n);
|
||||
}
|
||||
if (out_reg != NULL) {
|
||||
*(uint32_t *)out_reg = reg.val;
|
||||
}
|
||||
return eff_clk;
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate and set clock for SPI master according to desired parameters.
|
||||
*
|
||||
* This takes long, suggest to calculate the configuration during
|
||||
* initialization by ``spi_ll_master_cal_clock`` and store the result, then
|
||||
* configure the clock by stored value when used by
|
||||
* ``spi_ll_msater_set_clock_by_reg``.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param fapb APB clock of the system.
|
||||
* @param hz Frequncy desired.
|
||||
* @param duty_cycle Duty cycle desired.
|
||||
*
|
||||
* @return Actual frequency that is used.
|
||||
*/
|
||||
static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle)
|
||||
{
|
||||
spi_ll_clock_val_t reg_val;
|
||||
int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val);
|
||||
spi_ll_master_set_clock_by_reg(hw, ®_val);
|
||||
return freq;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable the CK sel feature for a CS pin.
|
||||
*
|
||||
* CK sel is a feature to toggle the CS line along with the clock.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param cs CS pin to enable/disable the feature, 0-2.
|
||||
* @param cksel true to enable the feature, otherwise false.
|
||||
*/
|
||||
static inline void spi_ll_master_set_cksel(spi_dev_t *hw, int cs, uint32_t cksel)
|
||||
{
|
||||
if (cksel) {
|
||||
hw->pin.master_ck_sel |= (1 << cs);
|
||||
} else {
|
||||
hw->pin.master_ck_sel &= (1 << cs);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the mosi delay after the output edge to the signal. (Preview)
|
||||
*
|
||||
* The delay mode/num is a Espressif conception, may change in the new chips.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param delay_mode Delay mode, see TRM.
|
||||
* @param delay_num APB clocks to delay.
|
||||
*/
|
||||
static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int delay_num)
|
||||
{
|
||||
hw->ctrl2.mosi_delay_mode = delay_mode;
|
||||
hw->ctrl2.mosi_delay_num = delay_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the miso delay applied to the input signal before the internal peripheral. (Preview)
|
||||
*
|
||||
* The delay mode/num is a Espressif conception, may change in the new chips.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param delay_mode Delay mode, see TRM.
|
||||
* @param delay_num APB clocks to delay.
|
||||
*/
|
||||
static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int delay_num)
|
||||
{
|
||||
hw->ctrl2.miso_delay_mode = delay_mode;
|
||||
hw->ctrl2.miso_delay_num = delay_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set dummy clocks to output before RX phase (master), or clocks to skip
|
||||
* before the data phase and after the address phase (slave).
|
||||
*
|
||||
* Note this phase is also used to compensate RX timing in half duplex mode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param dummy_n Dummy cycles used. 0 to disable the dummy phase.
|
||||
*/
|
||||
static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
|
||||
{
|
||||
hw->user.usr_dummy = dummy_n ? 1 : 0;
|
||||
hw->user1.usr_dummy_cyclelen = dummy_n - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the delay of SPI clocks before the CS inactive edge after the last SPI clock.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param hold Delay of SPI clocks after the last clock, 0 to disable the hold phase.
|
||||
*/
|
||||
static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold)
|
||||
{
|
||||
hw->ctrl2.hold_time = hold;
|
||||
hw->user.cs_hold = hold ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the delay of SPI clocks before the first SPI clock after the CS active edge.
|
||||
*
|
||||
* Note ESP32 doesn't support to use this feature when command/address phases
|
||||
* are used in full duplex mode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param setup Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
|
||||
*/
|
||||
static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup)
|
||||
{
|
||||
hw->ctrl2.setup_time = setup - 1;
|
||||
hw->user.cs_setup = setup ? 1 : 0;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Configs: data
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Set the input length (master).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen input length, in bits.
|
||||
*/
|
||||
static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen)
|
||||
{
|
||||
hw->miso_dlen.usr_miso_dbitlen = bitlen - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the output length (master).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen output length, in bits.
|
||||
*/
|
||||
static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen)
|
||||
{
|
||||
hw->mosi_dlen.usr_mosi_dbitlen = bitlen - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the maximum input length (slave).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen input length, in bits.
|
||||
*/
|
||||
static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
|
||||
{
|
||||
hw->slv_wrbuf_dlen.bit_len = bitlen - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the maximum output length (slave).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen output length, in bits.
|
||||
*/
|
||||
static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen)
|
||||
{
|
||||
hw->slv_rdbuf_dlen.bit_len = bitlen - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the length of command phase.
|
||||
*
|
||||
* When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit
|
||||
* command phases takes 4 cycles in 4-bit mode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of command phase, in bits. 0 to disable the command phase.
|
||||
*/
|
||||
static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen)
|
||||
{
|
||||
hw->user2.usr_command_bitlen = bitlen - 1;
|
||||
hw->user.usr_command = bitlen ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the length of address phase.
|
||||
*
|
||||
* When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit
|
||||
* address phases takes 4 cycles in 4-bit mode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of address phase, in bits. 0 to disable the address phase.
|
||||
*/
|
||||
static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen)
|
||||
{
|
||||
hw->user1.usr_addr_bitlen = bitlen - 1;
|
||||
hw->user.usr_addr = bitlen ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the address value in an intuitive way.
|
||||
*
|
||||
* The length and lsbfirst is required to shift and swap the address to the right place.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param address Address to set
|
||||
* @param addrlen Length of the address phase
|
||||
* @param lsbfirst whether the LSB first feature is enabled.
|
||||
*/
|
||||
static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, uint32_t lsbfirst)
|
||||
{
|
||||
if (lsbfirst) {
|
||||
/* The output address start from the LSB of the highest byte, i.e.
|
||||
* addr[24] -> addr[31]
|
||||
* ...
|
||||
* addr[0] -> addr[7]
|
||||
* slv_wr_status[24] -> slv_wr_status[31]
|
||||
* ...
|
||||
* slv_wr_status[0] -> slv_wr_status[7]
|
||||
* So swap the byte order to let the LSB sent first.
|
||||
*/
|
||||
addr = HAL_SWAP64(addr);
|
||||
hw->addr = addr >> 32;
|
||||
hw->slv_wr_status = addr;
|
||||
} else {
|
||||
// shift the address to MSB of addr (and maybe slv_wr_status) register.
|
||||
// output address will be sent from MSB to LSB of addr register, then comes the MSB to LSB of slv_wr_status register.
|
||||
if (addrlen > 32) {
|
||||
hw->addr = addr >> (addrlen - 32);
|
||||
hw->slv_wr_status = addr << (64 - addrlen);
|
||||
} else {
|
||||
hw->addr = addr << (32 - addrlen);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the command value in an intuitive way.
|
||||
*
|
||||
* The length and lsbfirst is required to shift and swap the command to the right place.
|
||||
*
|
||||
* @param hw Beginning command of the peripheral registers.
|
||||
* @param command Command to set
|
||||
* @param addrlen Length of the command phase
|
||||
* @param lsbfirst whether the LSB first feature is enabled.
|
||||
*/
|
||||
static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst)
|
||||
{
|
||||
if (lsbfirst) {
|
||||
// The output command start from bit0 to bit 15, kept as is.
|
||||
hw->user2.usr_command_value = cmd;
|
||||
} else {
|
||||
/* Output command will be sent from bit 7 to 0 of command_value, and
|
||||
* then bit 15 to 8 of the same register field. Shift and swap to send
|
||||
* more straightly.
|
||||
*/
|
||||
hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable the RX data phase.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param enable true if RX phase exist, otherwise false.
|
||||
*/
|
||||
static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable)
|
||||
{
|
||||
hw->user.usr_miso = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable the TX data phase.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param enable true if TX phase exist, otherwise false.
|
||||
*/
|
||||
static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable)
|
||||
{
|
||||
hw->user.usr_mosi = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* Reset the slave peripheral before next transaction.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_slave_reset(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.sync_reset = 1;
|
||||
hw->slave.sync_reset = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the received bit length of the slave.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return Received bits of the slave.
|
||||
*/
|
||||
static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
|
||||
{
|
||||
return hw->slv_rd_bit.slv_rdata_bit;
|
||||
}
|
||||
|
||||
|
||||
#undef SPI_LL_RST_MASK
|
||||
#undef SPI_LL_UNUSED_INT_MASK
|
||||
152
tools/sdk/include/soc/hal/spi_slave_hal.h
Normal file
152
tools/sdk/include/soc/hal/spi_slave_hal.h
Normal file
@ -0,0 +1,152 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The hal is not public api, don't use in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The HAL layer for SPI slave (common part)
|
||||
|
||||
// SPI slave HAL usages:
|
||||
// 1. initialize the bus
|
||||
// 2. initialize the DMA descriptors if DMA used
|
||||
// 3. call setup_device to update parameters for the device
|
||||
// 4. prepare data to send, and prepare the receiving buffer
|
||||
// 5. trigger user defined SPI transaction to start
|
||||
// 6. wait until the user transaction is done
|
||||
// 7. store the received data and get the length
|
||||
// 8. check and reset the DMA (if needed) before the next transaction
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/lldesc.h"
|
||||
#include "soc/spi_struct.h"
|
||||
#include <esp_types.h>
|
||||
#include "soc/spi_caps.h"
|
||||
|
||||
/**
|
||||
* Context that should be maintained by both the driver and the HAL.
|
||||
*/
|
||||
typedef struct {
|
||||
/* configured by driver at initialization, don't touch */
|
||||
spi_dev_t *hw; ///< Beginning address of the peripheral registers.
|
||||
/* should be configured by driver at initialization */
|
||||
lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the TX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the RX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use.
|
||||
|
||||
/*
|
||||
* configurations to be filled after ``spi_slave_hal_init``. Updated to
|
||||
* peripheral registers when ``spi_slave_hal_setup_device`` is called.
|
||||
*/
|
||||
struct {
|
||||
uint32_t rx_lsbfirst : 1;
|
||||
uint32_t tx_lsbfirst : 1;
|
||||
uint32_t use_dma : 1;
|
||||
};
|
||||
int mode;
|
||||
|
||||
/*
|
||||
* Transaction specific (data), all these parameters will be updated to the
|
||||
* peripheral every transaction.
|
||||
*/
|
||||
uint32_t bitlen; ///< Expected maximum length of the transaction, in bits.
|
||||
const void *tx_buffer; ///< Data to be sent
|
||||
void *rx_buffer; ///< Buffer to hold the received data.
|
||||
|
||||
/* Other transaction result after one transaction */
|
||||
uint32_t rcv_bitlen; ///< Length of the last transaction, in bits.
|
||||
} spi_slave_hal_context_t;
|
||||
|
||||
/**
|
||||
* Init the peripheral and the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
|
||||
*/
|
||||
void spi_slave_hal_init(spi_slave_hal_context_t *hal, int host_id);
|
||||
|
||||
/**
|
||||
* Deinit the peripheral (and the context if needed).
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_slave_hal_deinit(spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Setup device-related configurations according to the settings in the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_slave_hal_setup_device(const spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Prepare the data for the current transaction.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_slave_hal_prepare_data(const spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Trigger start a user-defined transaction.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_slave_hal_user_start(const spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Check whether the transaction is done (trans_done is set).
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
bool spi_slave_hal_usr_is_done(spi_slave_hal_context_t* hal);
|
||||
|
||||
/**
|
||||
* Post transaction operations, fetch data from the buffer and recored the length.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_slave_hal_store_result(spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Get the length of last transaction, in bits. Should be called after ``spi_slave_hal_store_result``.
|
||||
*
|
||||
* Note that if last transaction is longer than configured before, the return
|
||||
* value will be truncated to the configured length.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*
|
||||
* @return Length of the last transaction, in bits.
|
||||
*/
|
||||
uint32_t spi_slave_hal_get_rcv_bitlen(spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Check whether we need to reset the DMA according to the status of last transactions.
|
||||
*
|
||||
* In ESP32, sometimes we may need to reset the DMA for the slave before the
|
||||
* next transaction. Call this to check it.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*
|
||||
* @return true if reset is needed, else false.
|
||||
*/
|
||||
bool spi_slave_hal_dma_need_reset(const spi_slave_hal_context_t *hal);
|
||||
18
tools/sdk/include/soc/hal/spi_types.h
Normal file
18
tools/sdk/include/soc/hal/spi_types.h
Normal file
@ -0,0 +1,18 @@
|
||||
#pragma once
|
||||
|
||||
#include "soc/spi_caps.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
/**
|
||||
* @brief Enum with the three SPI peripherals that are software-accessible in it
|
||||
*/
|
||||
typedef enum {
|
||||
SPI1_HOST=0, ///< SPI1
|
||||
SPI2_HOST=1, ///< SPI2
|
||||
SPI3_HOST=2, ///< SPI3
|
||||
} spi_host_device_t;
|
||||
|
||||
//alias for different chips
|
||||
#define SPI_HOST SPI1_HOST
|
||||
#define HSPI_HOST SPI2_HOST
|
||||
#define VSPI_HOST SPI3_HOST
|
||||
16
tools/sdk/include/soc/soc/adc_periph.h
Normal file
16
tools/sdk/include/soc/soc/adc_periph.h
Normal file
@ -0,0 +1,16 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/adc_channel.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
typedef struct apb_ctrl_dev_s {
|
||||
union {
|
||||
struct {
|
||||
volatile uint32_t pre_div: 10;
|
||||
|
||||
16
tools/sdk/include/soc/soc/can_periph.h
Normal file
16
tools/sdk/include/soc/soc/can_periph.h
Normal file
@ -0,0 +1,16 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/can_struct.h"
|
||||
@ -139,7 +139,7 @@ typedef union {
|
||||
uint32_t val;
|
||||
} can_err_code_cap_reg_t;
|
||||
|
||||
typedef struct {
|
||||
typedef struct can_acc_filter_s {
|
||||
can_reg_t code_reg[4];
|
||||
can_reg_t mask_reg[4];
|
||||
uint32_t reserved32[5];
|
||||
@ -166,7 +166,7 @@ typedef union {
|
||||
|
||||
/* ---------------------------- Register Layout ------------------------------ */
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct can_dev_s {
|
||||
//Configuration and Control Registers
|
||||
can_mode_reg_t mode_reg; /* Address 0 */
|
||||
can_cmd_reg_t command_reg; /* Address 1 */
|
||||
|
||||
@ -110,4 +110,25 @@ void esp_cpu_reset(int cpu_id);
|
||||
*/
|
||||
bool esp_cpu_in_ocd_debug_mode();
|
||||
|
||||
/**
|
||||
* @brief Convert the PC register value to its true address
|
||||
*
|
||||
* The address of the current instruction is not stored as an exact uint32_t
|
||||
* representation in PC register. This function will convert the value stored in
|
||||
* the PC register to a uint32_t address.
|
||||
*
|
||||
* @param pc_raw The PC as stored in register format.
|
||||
*
|
||||
* @return Address in uint32_t format
|
||||
*/
|
||||
static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc)
|
||||
{
|
||||
if (pc & 0x80000000) {
|
||||
//Top two bits of a0 (return address) specify window increment. Overwrite to map to address space.
|
||||
pc = (pc & 0x3fffffff) | 0x40000000;
|
||||
}
|
||||
//Minus 3 to get PC of previous instruction (i.e. instruction executed before return address)
|
||||
return pc - 3;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
16
tools/sdk/include/soc/soc/dac_periph.h
Normal file
16
tools/sdk/include/soc/soc/dac_periph.h
Normal file
@ -0,0 +1,16 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/dac_channel.h"
|
||||
@ -17,7 +17,7 @@
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_attr.h"
|
||||
#include "esp_dport_access.h"
|
||||
#include "esp32/dport_access.h"
|
||||
#include "soc.h"
|
||||
#include "uart_reg.h"
|
||||
#include "xtensa/xtruntime.h"
|
||||
|
||||
@ -961,7 +961,6 @@
|
||||
#define DPORT_CAN_CLK_EN (BIT(19))
|
||||
#define DPORT_I2C_EXT1_CLK_EN (BIT(18))
|
||||
#define DPORT_PWM0_CLK_EN (BIT(17))
|
||||
#define DPORT_SPI_CLK_EN_2 (BIT(16)) /** Deprecated, please use DPORT_SPI3_CLK_EN **/
|
||||
#define DPORT_SPI3_CLK_EN (BIT(16))
|
||||
#define DPORT_TIMERGROUP1_CLK_EN (BIT(15))
|
||||
#define DPORT_EFUSE_CLK_EN (BIT(14))
|
||||
@ -972,13 +971,11 @@
|
||||
#define DPORT_RMT_CLK_EN (BIT(9))
|
||||
#define DPORT_UHCI0_CLK_EN (BIT(8))
|
||||
#define DPORT_I2C_EXT0_CLK_EN (BIT(7))
|
||||
#define DPORT_SPI_CLK_EN (BIT(6)) /** Deprecated, please use DPORT_SPI2_CLK_EN **/
|
||||
#define DPORT_SPI2_CLK_EN (BIT(6))
|
||||
#define DPORT_UART1_CLK_EN (BIT(5))
|
||||
#define DPORT_I2S0_CLK_EN (BIT(4))
|
||||
#define DPORT_WDG_CLK_EN (BIT(3))
|
||||
#define DPORT_UART_CLK_EN (BIT(2))
|
||||
#define DPORT_SPI_CLK_EN_1 (BIT(1)) /** Deprecated, please use DPORT_SPI01_CLK_EN **/
|
||||
#define DPORT_SPI01_CLK_EN (BIT(1))
|
||||
#define DPORT_TIMERS_CLK_EN (BIT(0))
|
||||
#define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4)
|
||||
@ -998,7 +995,6 @@
|
||||
#define DPORT_CAN_RST (BIT(19))
|
||||
#define DPORT_I2C_EXT1_RST (BIT(18))
|
||||
#define DPORT_PWM0_RST (BIT(17))
|
||||
#define DPORT_SPI_RST_2 (BIT(16)) /** Deprecated, please use DPORT_SPI3_RST **/
|
||||
#define DPORT_SPI3_RST (BIT(16))
|
||||
#define DPORT_TIMERGROUP1_RST (BIT(15))
|
||||
#define DPORT_EFUSE_RST (BIT(14))
|
||||
@ -1009,13 +1005,11 @@
|
||||
#define DPORT_RMT_RST (BIT(9))
|
||||
#define DPORT_UHCI0_RST (BIT(8))
|
||||
#define DPORT_I2C_EXT0_RST (BIT(7))
|
||||
#define DPORT_SPI_RST (BIT(6)) /** Deprecated, please use DPORT_SPI2_RST **/
|
||||
#define DPORT_SPI2_RST (BIT(6))
|
||||
#define DPORT_UART1_RST (BIT(5))
|
||||
#define DPORT_I2S0_RST (BIT(4))
|
||||
#define DPORT_WDG_RST (BIT(3))
|
||||
#define DPORT_UART_RST (BIT(2))
|
||||
#define DPORT_SPI_RST_1 (BIT(1)) /** Deprecated, please use DPORT_SPI01_RST **/
|
||||
#define DPORT_SPI01_RST (BIT(1))
|
||||
#define DPORT_TIMERS_RST (BIT(0))
|
||||
#define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8)
|
||||
|
||||
16
tools/sdk/include/soc/soc/efuse_periph.h
Normal file
16
tools/sdk/include/soc/soc/efuse_periph.h
Normal file
@ -0,0 +1,16 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/efuse_reg.h"
|
||||
162
tools/sdk/include/soc/soc/emac_dma_struct.h
Normal file
162
tools/sdk/include/soc/soc/emac_dma_struct.h
Normal file
@ -0,0 +1,162 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit.*/
|
||||
uint32_t dma_arb_sch : 1; /*This bit specifies the arbitration scheme between the transmit and receive paths.1'b0: weighted round-robin with RX:TX or TX:RX priority specified in PR (bit[15:14]). 1'b1 Fixed priority (Rx priority to Tx).*/
|
||||
uint32_t desc_skip_len : 5; /*This bit specifies the number of Word to skip between two unchained descriptors.The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL(DESC_SKIP_LEN) value is equal to zero the descriptor table is taken as contiguous by the DMA in Ring mode.*/
|
||||
uint32_t alt_desc_size : 1; /*When set the size of the alternate descriptor increases to 32 bytes.*/
|
||||
uint32_t prog_burst_len : 6; /*These bits indicate the maximum number of beats to be transferred in one DMA transaction. If the number of beats to be transferred is more than 32 then perform the following steps: 1. Set the PBLx8 mode 2. Set the PBL(PROG_BURST_LEN).*/
|
||||
uint32_t pri_ratio : 2; /*These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx represented by each bit: 2'b00 -- 1: 1 2'b01 -- 2: 0 2'b10 -- 3: 1 2'b11 -- 4: 1*/
|
||||
uint32_t fixed_burst : 1; /*This bit controls whether the AHB master interface performs fixed burst transfers or not. When set the AHB interface uses only SINGLE INCR4 INCR8 or INCR16 during start of the normal burst transfers. When reset the AHB interface uses SINGLE and INCR burst transfer Operations.*/
|
||||
uint32_t rx_dma_pbl : 6; /*This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst transfer on the host bus. You can program RPBL with values of 1 2 4 8 16 and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL) is set high.*/
|
||||
uint32_t use_sep_pbl : 1; /*When set high this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When reset to low the PBL value in Bits[13:8] is applicable for both DMA engines.*/
|
||||
uint32_t pblx8_mode : 1; /*When set high this bit multiplies the programmed PBL value (Bits[22:17] and Bits[13:8]) eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending on the PBL value.*/
|
||||
uint32_t dmaaddralibea : 1; /*When this bit is set high and the FIXED_BURST bit is 1 the AHB interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0 the first burst (accessing the start address of data buffer) is not aligned but subsequent bursts are aligned to the address.*/
|
||||
uint32_t dmamixedburst : 1; /*When this bit is set high and the FIXED_BURST bit is low the AHB master interface starts all bursts of a length more than 16 with INCR (undefined burst) whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less.*/
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t reserved28 : 2;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} dmabusmode;
|
||||
uint32_t dmatxpolldemand; /*When these bits are written with any value the DMA reads the current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes.*/
|
||||
uint32_t dmarxpolldemand; /*When these bits are written with any value the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host) the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available the Rx DMA returns to the active state.*/
|
||||
uint32_t dmarxbaseaddr; /*This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.*/
|
||||
uint32_t dmatxbaseaddr; /*This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore these LSB bits are read-only.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t trans_int : 1; /*This bit indicates that the frame transmission is complete. When transmission is complete Bit[31] (OWN) of TDES0 is reset and the specific frame status information is updated in the Descriptor.*/
|
||||
uint32_t trans_proc_stop : 1; /*This bit is set when the transmission is stopped.*/
|
||||
uint32_t trans_buf_unavail : 1; /*This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand Command.*/
|
||||
uint32_t trans_jabber_to : 1; /*This bit indicates that the Transmit Jabber Timer expired which happens when the frame size exceeds 2 048 (10 240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.*/
|
||||
uint32_t recv_ovflow : 1; /*This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application the overflow status is set in RDES0[11].*/
|
||||
uint32_t trans_undflow : 1; /*This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.*/
|
||||
uint32_t recv_int : 1; /*This bit indicates that the frame reception is complete. When reception is complete the Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor and the specific frame status information is updated in the descriptor. The reception remains in the Running state.*/
|
||||
uint32_t recv_buf_unavail : 1; /*This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA.*/
|
||||
uint32_t recv_proc_stop : 1; /*This bit is asserted when the Receive Process enters the Stopped state.*/
|
||||
uint32_t recv_wdt_to : 1; /*When set this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout.*/
|
||||
uint32_t early_trans_int : 1; /*This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO.*/
|
||||
uint32_t reserved11 : 2;
|
||||
uint32_t fatal_bus_err_int : 1; /*This bit indicates that a bus error occurred as described in Bits [25:23]. When this bit is set the corresponding DMA engine disables all of its bus accesses.*/
|
||||
uint32_t early_recv_int : 1; /*This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whichever occurs earlier).*/
|
||||
uint32_t abn_int_summ : 1; /*Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[1]: Transmit Process Stopped. Bit[3]: Transmit Jabber Timeout. Bit[4]: Receive FIFO Overflow. Bit[5]: Transmit Underflow. Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped. Bit[9]: Receive Watchdog Timeout. Bit[10]: Early Transmit Interrupt. Bit[13]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes AIS to be set is cleared.*/
|
||||
uint32_t norm_int_summ : 1; /*Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared.*/
|
||||
uint32_t recv_proc_state : 3; /*This field indicates the Receive DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Receive Command issued. 3'b001: Running. Fetching Receive Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for RX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Receive Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from receive buffer to host memory.*/
|
||||
uint32_t trans_proc_state : 3; /*This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Transmit Command issued. 3'b001: Running. Fetching Transmit Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for TX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Transmit Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from transmit buffer to host memory.*/
|
||||
uint32_t error_bits : 3; /*This field indicates the type of error that caused a Bus Error for example error response on the AHB interface. This field is valid only when Bit[13] (FBI) is set. This field does not generate an interrupt. 3'b000: Error during Rx DMA Write Data Transfer. 3'b011: Error during Tx DMA Read Data Transfer. 3'b100: Error during Rx DMA Descriptor Write Access. 3'b101: Error during Tx DMA Descriptor Write Access. 3'b110: Error during Rx DMA Descriptor Read Access. 3'b111: Error during Tx DMA Descriptor Read Access.*/
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t pmt_int : 1; /*This bit indicates an interrupt event in the PMT module of the ETH_MAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0.*/
|
||||
uint32_t ts_tri_int : 1; /*This bit indicates an interrupt event in the Timestamp Generator block of the ETH_MAC.The software must read the corresponding registers in the ETH_MAC to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0.*/
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} dmastatus;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 1;
|
||||
uint32_t start_stop_rx : 1; /*When this bit is set the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame.*/
|
||||
uint32_t opt_second_frame : 1; /*When this bit is set it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained.*/
|
||||
uint32_t rx_thresh_ctrl : 2; /*These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. 2'b00: 64， 2'b01: 32， 2'b10: 96， 2'b11: 128 .*/
|
||||
uint32_t drop_gfrm : 1; /*When set the MAC drops the received giant frames in the Rx FIFO that is frames that are larger than the computed giant frame limit.*/
|
||||
uint32_t fwd_under_gf : 1; /*When set the Rx FIFO forwards Undersized frames (that is frames with no Error and length less than 64 bytes) including pad-bytes and CRC.*/
|
||||
uint32_t fwd_err_frame : 1; /*When this bit is reset the Rx FIFO drops frames with error status (CRC error collision error giant frame watchdog timeout or overflow).*/
|
||||
uint32_t reserved8 : 1;
|
||||
uint32_t reserved9 : 2;
|
||||
uint32_t reserved11 : 2;
|
||||
uint32_t start_stop_transmission_command : 1; /*When this bit is set transmission is placed in the Running state and the DMA checks the Transmit List at the current position for a frame to be transmitted.When this bit is reset the transmission process is placed in the Stopped state after completing the transmission of the current frame.*/
|
||||
uint32_t tx_thresh_ctrl : 3; /*These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition full frames with a length less than the threshold are also transmitted. These bits are used only when Tx_Str_fwd is reset. 3'b000: 64 3'b001: 128 3'b010: 192 3'b011: 256 3'b100: 40 3'b101: 32 3'b110: 24 3'b111: 16 .*/
|
||||
uint32_t reserved17 : 3;
|
||||
uint32_t flush_tx_fifo : 1; /*When this bit is set the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete.*/
|
||||
uint32_t tx_str_fwd : 1; /*When this bit is set transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set the Tx_Thresh_Ctrl values specified in Tx_Thresh_Ctrl are ignored.*/
|
||||
uint32_t reserved22 : 1;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t dis_flush_recv_frames : 1; /*When this bit is set the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers.*/
|
||||
uint32_t rx_store_forward : 1; /*When this bit is set the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it.*/
|
||||
uint32_t dis_drop_tcpip_err_fram : 1; /*When this bit is set the MAC does not drop the frames which only have errors detected by the Receive Checksum engine.When this bit is reset all error frames are dropped if the Fwd_Err_Frame bit is reset.*/
|
||||
uint32_t reserved27 : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} dmaoperation_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dmain_tie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled.*/
|
||||
uint32_t dmain_tse : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmission Stopped Interrupt is enabled. When this bit is reset the Transmission Stopped Interrupt is disabled.*/
|
||||
uint32_t dmain_tbue : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit 16) the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable Interrupt is Disabled.*/
|
||||
uint32_t dmain_tjte : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset the Transmit Jabber Timeout Interrupt is disabled.*/
|
||||
uint32_t dmain_oie : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Overflow Interrupt is enabled. When this bit is reset the Overflow Interrupt is disabled.*/
|
||||
uint32_t dmain_uie : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmit Underflow Interrupt is enabled. When this bit is reset the Underflow Interrupt is disabled.*/
|
||||
uint32_t dmain_rie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled.*/
|
||||
uint32_t dmain_rbue : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset the Receive Buffer Unavailable Interrupt is disabled.*/
|
||||
uint32_t dmain_rse : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped Interrupt is disabled.*/
|
||||
uint32_t dmain_rwte : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset the Receive Watchdog Timeout Interrupt is disabled.*/
|
||||
uint32_t dmain_etie : 1; /*When this bit is set with an Abnormal Interrupt Summary Enable (Bit[15]) the Early Transmit Interrupt is enabled. When this bit is reset the Early Transmit Interrupt is disabled.*/
|
||||
uint32_t reserved11 : 2;
|
||||
uint32_t dmain_fbee : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Fatal Bus Error Interrupt is enabled. When this bit is reset the Fatal Bus Error Enable Interrupt is disabled.*/
|
||||
uint32_t dmain_erie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Early Receive Interrupt is enabled. When this bit is reset the Early Receive Interrupt is disabled.*/
|
||||
uint32_t dmain_aise : 1; /*When this bit is set abnormal interrupt summary is enabled. When this bit is reset the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit[1]: Transmit Process Stopped. Bit[3]: Transmit Jabber Timeout. Bit[4]: Receive Overflow. Bit[5]: Transmit Underflow. Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped. Bit[9]: Receive Watchdog Timeout. Bit[10]: Early Transmit Interrupt. Bit[13]: Fatal Bus Error.*/
|
||||
uint32_t dmain_nise : 1; /*When this bit is set normal interrupt summary is enabled. When this bit is reset normal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt.*/
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} dmain_en;
|
||||
union {
|
||||
struct {
|
||||
uint32_t missed_fc : 16; /*This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read.*/
|
||||
uint32_t overflow_bmfc : 1; /*This bit is set every time Missed Frame Counter (Bits[15:0]) overflows that is the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
|
||||
uint32_t overflow_fc : 11; /*This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read.*/
|
||||
uint32_t overflow_bfoc : 1; /*This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows that is the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
|
||||
uint32_t reserved29 : 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} dmamissedfr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t riwtc : 8; /*This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame.*/
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} dmarintwdtimer;
|
||||
uint32_t reserved_28;
|
||||
uint32_t reserved_2c;
|
||||
uint32_t reserved_30;
|
||||
uint32_t reserved_34;
|
||||
uint32_t reserved_38;
|
||||
uint32_t reserved_3c;
|
||||
uint32_t reserved_40;
|
||||
uint32_t reserved_44;
|
||||
uint32_t dmatxcurrdesc; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
|
||||
uint32_t dmarxcurrdesc; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
|
||||
uint32_t dmatxcurraddr_buf; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
|
||||
uint32_t dmarxcurraddr_buf; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
|
||||
} emac_dma_dev_t;
|
||||
|
||||
extern emac_dma_dev_t EMAC_DMA;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -1,161 +0,0 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _EMAC_EX_H_
|
||||
#define _EMAC_EX_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
#define REG_EMAC_EX_BASE (DR_REG_EMAC_BASE + 0x800)
|
||||
|
||||
#define EMAC_EX_CLKOUT_CONF_REG (REG_EMAC_EX_BASE + 0x0000)
|
||||
#define EMAC_EX_CLK_OUT_DLY_NUM 0x00000003
|
||||
#define EMAC_EX_CLK_OUT_DLY_NUM_M (EMAC_EX_CLK_OUT_DLY_NUM_V << EMAC_EX_CLK_OUT_DLY_NUM_S)
|
||||
#define EMAC_EX_CLK_OUT_DLY_NUM_V 0x00000003
|
||||
#define EMAC_EX_CLK_OUT_DLY_NUM_S 8
|
||||
#define EMAC_EX_CLK_OUT_H_DIV_NUM 0x0000000F
|
||||
#define EMAC_EX_CLK_OUT_H_DIV_NUM_M (EMAC_EX_CLK_OUT_H_DIV_NUM_V << EMAC_EX_CLK_OUT_H_DIV_NUM_S)
|
||||
#define EMAC_EX_CLK_OUT_H_DIV_NUM_V 0x0000000F
|
||||
#define EMAC_EX_CLK_OUT_H_DIV_NUM_S 4
|
||||
#define EMAC_EX_CLK_OUT_DIV_NUM 0x0000000F
|
||||
#define EMAC_EX_CLK_OUT_DIV_NUM_M (EMAC_EX_CLK_OUT_DIV_NUM_V << EMAC_EX_CLK_OUT_DIV_NUM_S)
|
||||
#define EMAC_EX_CLK_OUT_DIV_NUM_V 0x0000000F
|
||||
#define EMAC_EX_CLK_OUT_DIV_NUM_S 0
|
||||
|
||||
#define EMAC_EX_OSCCLK_CONF_REG (REG_EMAC_EX_BASE + 0x0004)
|
||||
#define EMAC_EX_OSC_CLK_SEL (BIT(24))
|
||||
#define EMAC_EX_OSC_CLK_SEL_M (BIT(24))
|
||||
#define EMAC_EX_OSC_CLK_SEL_V 1
|
||||
#define EMAC_EX_OSC_CLK_SEL_S 24
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_100M 0x0000003F
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_100M_M (EMAC_EX_OSC_H_DIV_NUM_100M_V << EMAC_EX_OSC_H_DIV_NUM_100M_S)
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_100M_V 0x0000003F
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_100M_S 18
|
||||
#define EMAC_EX_OSC_DIV_NUM_100M 0x0000003F
|
||||
#define EMAC_EX_OSC_DIV_NUM_100M_M (EMAC_EX_OSC_DIV_NUM_100M_V << EMAC_EX_OSC_DIV_NUM_100M_S)
|
||||
#define EMAC_EX_OSC_DIV_NUM_100M_V 0x0000003F
|
||||
#define EMAC_EX_OSC_DIV_NUM_100M_S 12
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_10M 0x0000003F
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_10M_M (EMAC_EX_OSC_H_DIV_NUM_10M_V << EMAC_EX_OSC_H_DIV_NUM_10M_S)
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_10M_V 0x0000003F
|
||||
#define EMAC_EX_OSC_H_DIV_NUM_10M_S 6
|
||||
#define EMAC_EX_OSC_DIV_NUM_10M 0x0000003F
|
||||
#define EMAC_EX_OSC_DIV_NUM_10M_M (EMAC_EX_OSC_DIV_NUM_10M_V << EMAC_EX_OSC_DIV_NUM_10M_S)
|
||||
#define EMAC_EX_OSC_DIV_NUM_10M_V 0x0000003F
|
||||
#define EMAC_EX_OSC_DIV_NUM_10M_S 0
|
||||
|
||||
#define EMAC_EX_CLK_CTRL_REG (REG_EMAC_EX_BASE + 0x0008)
|
||||
#define EMAC_EX_CLK_EN (BIT(5))
|
||||
#define EMAC_EX_CLK_EN_M (BIT(5))
|
||||
#define EMAC_EX_CLK_EN_V 1
|
||||
#define EMAC_EX_CLK_EN_S 5
|
||||
#define EMAC_EX_MII_CLK_RX_EN (BIT(4))
|
||||
#define EMAC_EX_MII_CLK_RX_EN_M (BIT(4))
|
||||
#define EMAC_EX_MII_CLK_RX_EN_V 1
|
||||
#define EMAC_EX_MII_CLK_RX_EN_S 4
|
||||
#define EMAC_EX_MII_CLK_TX_EN (BIT(3))
|
||||
#define EMAC_EX_MII_CLK_TX_EN_M (BIT(3))
|
||||
#define EMAC_EX_MII_CLK_TX_EN_V 1
|
||||
#define EMAC_EX_MII_CLK_TX_EN_S 3
|
||||
#define EMAC_EX_RX_125_CLK_EN (BIT(2))
|
||||
#define EMAC_EX_RX_125_CLK_EN_M (BIT(2))
|
||||
#define EMAC_EX_RX_125_CLK_EN_V 1
|
||||
#define EMAC_EX_RX_125_CLK_EN_S 2
|
||||
#define EMAC_EX_INT_OSC_EN (BIT(1))
|
||||
#define EMAC_EX_INT_OSC_EN_M (BIT(1))
|
||||
#define EMAC_EX_INT_OSC_EN_V 1
|
||||
#define EMAC_EX_INT_OSC_EN_S 1
|
||||
#define EMAC_EX_EXT_OSC_EN (BIT(0))
|
||||
#define EMAC_EX_EXT_OSC_EN_M (BIT(0))
|
||||
#define EMAC_EX_EXT_OSC_EN_V 1
|
||||
#define EMAC_EX_EXT_OSC_EN_S 0
|
||||
|
||||
#define EMAC_EX_PHYINF_CONF_REG (REG_EMAC_EX_BASE + 0x000c)
|
||||
#define EMAC_EX_TX_ERR_OUT_EN (BIT(20))
|
||||
#define EMAC_EX_TX_ERR_OUT_EN_M (BIT(20))
|
||||
#define EMAC_EX_TX_ERR_OUT_EN_V 1
|
||||
#define EMAC_EX_TX_ERR_OUT_EN_S 20
|
||||
#define EMAC_EX_SCR_SMI_DLY_RX_SYNC (BIT(19))
|
||||
#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_M (BIT(19))
|
||||
#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_V 1
|
||||
#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_S 19
|
||||
#define EMAC_EX_PMT_CTRL_EN (BIT(18))
|
||||
#define EMAC_EX_PMT_CTRL_EN_M (BIT(18))
|
||||
#define EMAC_EX_PMT_CTRL_EN_V 1
|
||||
#define EMAC_EX_PMT_CTRL_EN_S 18
|
||||
#define EMAC_EX_SBD_CLK_GATING_EN (BIT(17))
|
||||
#define EMAC_EX_SBD_CLK_GATING_EN_M (BIT(17))
|
||||
#define EMAC_EX_SBD_CLK_GATING_EN_V 1
|
||||
#define EMAC_EX_SBD_CLK_GATING_EN_S 17
|
||||
#define EMAC_EX_SS_MODE (BIT(16))
|
||||
#define EMAC_EX_SS_MODE_M (BIT(16))
|
||||
#define EMAC_EX_SS_MODE_V 1
|
||||
#define EMAC_EX_SS_MODE_S 16
|
||||
#define EMAC_EX_PHY_INTF_SEL 0x00000007
|
||||
#define EMAC_EX_PHY_INTF_SEL_M (EMAC_EX_PHY_INTF_SEL_V << EMAC_EX_PHY_INTF_SEL_S)
|
||||
#define EMAC_EX_PHY_INTF_SEL_V 0x00000007
|
||||
#define EMAC_EX_PHY_INTF_SEL_S 13
|
||||
#define EMAC_EX_REVMII_PHY_ADDR 0x0000001F
|
||||
#define EMAC_EX_REVMII_PHY_ADDR_M (EMAC_EX_REVMII_PHY_ADDR_V << EMAC_EX_REVMII_PHY_ADDR_S)
|
||||
#define EMAC_EX_REVMII_PHY_ADDR_V 0x0000001F
|
||||
#define EMAC_EX_REVMII_PHY_ADDR_S 8
|
||||
#define EMAC_EX_CORE_PHY_ADDR 0x0000001F
|
||||
#define EMAC_EX_CORE_PHY_ADDR_M (EMAC_EX_CORE_PHY_ADDR_V << EMAC_EX_CORE_PHY_ADDR_S)
|
||||
#define EMAC_EX_CORE_PHY_ADDR_V 0x0000001F
|
||||
#define EMAC_EX_CORE_PHY_ADDR_S 3
|
||||
#define EMAC_EX_SBD_FLOWCTRL (BIT(2))
|
||||
#define EMAC_EX_SBD_FLOWCTRL_M (BIT(2))
|
||||
#define EMAC_EX_SBD_FLOWCTRL_V 1
|
||||
#define EMAC_EX_SBD_FLOWCTRL_S 2
|
||||
#define EMAC_EX_EXT_REVMII_RX_CLK_SEL (BIT(1))
|
||||
#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_M (BIT(1))
|
||||
#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_V 1
|
||||
#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_S 1
|
||||
#define EMAC_EX_INT_REVMII_RX_CLK_SEL (BIT(0))
|
||||
#define EMAC_EX_INT_REVMII_RX_CLK_SEL_M (BIT(0))
|
||||
#define EMAC_EX_INT_REVMII_RX_CLK_SEL_V 1
|
||||
#define EMAC_EX_INT_REVMII_RX_CLK_SEL_S 0
|
||||
|
||||
#define EMAC_EX_PHY_INTF_RMII 4
|
||||
|
||||
#define EMAC_EX_EMAC_PD_SEL_REG (REG_EMAC_EX_BASE + 0x0010)
|
||||
#define EMAC_EX_RAM_PD_EN 0x00000003
|
||||
#define EMAC_EX_RAM_PD_EN_M (EMAC_EX_RAM_PD_EN_V << EMAC_EX_RAM_PD_EN_S)
|
||||
#define EMAC_EX_RAM_PD_EN_V 0x00000003
|
||||
#define EMAC_EX_RAM_PD_EN_S 0
|
||||
|
||||
#define EMAC_EX_DATE_REG (REG_EMAC_EX_BASE + 0x00fc)
|
||||
#define EMAC_EX_DATE 0xFFFFFFFF
|
||||
#define EMAC_EX_DATE_M (EMAC_EX_DATE_V << EMAC_EX_DATE_S)
|
||||
#define EMAC_EX_DATE_V 0xFFFFFFFF
|
||||
#define EMAC_EX_DATE_S 0
|
||||
#define EMAC_EX_DATE_VERSION 0x16042200
|
||||
#define EMAC_EX_DATE_VERSION_M (EMAC_EX_DATE_VERSION_V << EMAC_EX_DATE_VERSION_S)
|
||||
#define EMAC_EX_DATE_VERSION_V 0x16042200
|
||||
|
||||
#define EMAC_CLK_EN_REG 0x3ff000cc
|
||||
#define EMAC_CLK_EN_REG_M (EMAC_CLK_EN_REG_V << EMAC_CLK_EN_REG_S)
|
||||
#define EMAC_CLK_EN_REG_V 0x3ff000cc
|
||||
#define EMAC_CLK_EN (BIT(14))
|
||||
#define EMAC_CLK_EN_M (BIT(14))
|
||||
#define EMAC_CLK_EN_V 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
74
tools/sdk/include/soc/soc/emac_ext_struct.h
Normal file
74
tools/sdk/include/soc/soc/emac_ext_struct.h
Normal file
@ -0,0 +1,74 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t div_num : 4;
|
||||
uint32_t h_div_num : 4;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} ex_clkout_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t div_num_10m : 6;
|
||||
uint32_t h_div_num_10m : 6;
|
||||
uint32_t div_num_100m : 6;
|
||||
uint32_t h_div_num_100m : 6;
|
||||
uint32_t clk_sel : 1;
|
||||
uint32_t reserved25 : 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} ex_oscclk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ext_en : 1;
|
||||
uint32_t int_en : 1;
|
||||
uint32_t reserved2 : 1;
|
||||
uint32_t mii_clk_tx_en : 1;
|
||||
uint32_t mii_clk_rx_en : 1;
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} ex_clk_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 13;
|
||||
uint32_t phy_intf_sel : 3;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} ex_phyinf_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ram_pd_en : 2;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} pd_sel;
|
||||
} emac_ext_dev_t;
|
||||
|
||||
extern emac_ext_dev_t EMAC_EXT;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
345
tools/sdk/include/soc/soc/emac_mac_struct.h
Normal file
345
tools/sdk/include/soc/soc/emac_mac_struct.h
Normal file
@ -0,0 +1,345 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/
|
||||
uint32_t rx : 1; /*When this bit is set the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset the MAC receive state machine is disabled after the completion of the reception of the current frame and does not receive any further frames from the MII.*/
|
||||
uint32_t tx : 1; /*When this bit is set the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset the MAC transmit state machine is disabled after the completion of the transmission of the current frame and does not transmit any further frames.*/
|
||||
uint32_t deferralcheck : 1; /*Deferral Check.*/
|
||||
uint32_t backofflimit : 2; /*The Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode. 00: k= min (n 10). 01: k = min (n 8). 10: k = min (n 4). 11: k = min (n 1) n = retransmission attempt. The random integer r takes the value in the Range 0 ~ 2000.*/
|
||||
uint32_t padcrcstrip : 1; /*When this bit is set the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1 536 bytes. All received frames with length field greater than or equal to 1 536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset the MAC passes all incoming frames without modifying them to the Host.*/
|
||||
uint32_t reserved8 : 1;
|
||||
uint32_t retry : 1; /*When this bit is set the MAC attempts only one transmission. When a collision occurs on the MII interface the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex Mode.*/
|
||||
uint32_t rxipcoffload : 1; /*When this bit is set the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset this function is disabled.*/
|
||||
uint32_t duplex : 1; /*When this bit is set the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is read only with default value of 1'b1 in the full-duplex-mode.*/
|
||||
uint32_t loopback : 1; /*When this bit is set the MAC operates in the loopback mode MII. The MII Receive clock input (CLK_RX) is required for the loopback to work properly because the transmit clock is not looped-back internally.*/
|
||||
uint32_t rxown : 1; /*When this bit is set the MAC disables the reception of frames when the TX_EN is asserted in the half-duplex mode. When this bit is reset the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full duplex mode.*/
|
||||
uint32_t fespeed : 1; /*This bit selects the speed in the MII RMII interface. 0: 10 Mbps. 1: 100 Mbps.*/
|
||||
uint32_t mii : 1; /*This bit selects the Ethernet line speed. It should be set to 1 for 10 or 100 Mbps operations.In 10 or 100 Mbps operations this bit along with FES(EMACFESPEED) bit it selects the exact linespeed. In the 10/100 Mbps-only operations the bit is always 1.*/
|
||||
uint32_t disablecrs : 1; /*When set high this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions.*/
|
||||
uint32_t interframegap : 3; /*These bits control the minimum IFG between frames during transmission. 3'b000: 96 bit times. 3'b001: 88 bit times. 3'b010: 80 bit times. 3'b111: 40 bit times. In the half-duplex mode the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered.*/
|
||||
uint32_t jumboframe : 1; /*When this bit is set the MAC allows Jumbo frames of 9 018 bytes (9 022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.*/
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t jabber : 1; /*When this bit is set the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data (10 240 if JE is set high) during Transmission.*/
|
||||
uint32_t watchdog : 1; /*When this bit is set the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16 383 bytes. When this bit is reset the MAC does not allow a receive frame which more than 2 048 bytes (10 240 if JE is set high) or the value programmed in Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog limit number of bytes.*/
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t ass2kp : 1; /*When set the MAC considers all frames with up to 2 000 bytes length as normal packets.When Bit[20] (JE) is not set the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit[20] (JE) is not set the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit[20] is set setting this bit has no effect on Giant Frame status.*/
|
||||
uint32_t sairc : 3; /*This field controls the source address insertion or replacement for all transmitted frames.Bit[30] specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. 2'b10: If Bit[30] is set to 0 the MAC inserts the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC inserts the content of the MAC Address 1 registers in the SA field of all transmitted frames. 2'b11: If Bit[30] is set to 0 the MAC replaces the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames.*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} gmacconfig;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pmode : 1; /*When this bit is set the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set.*/
|
||||
uint32_t reserved1 : 1;
|
||||
uint32_t reserved2 : 1;
|
||||
uint32_t daif : 1; /*When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset normal filtering of frames is performed.*/
|
||||
uint32_t pam : 1; /*When set this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.*/
|
||||
uint32_t dbf : 1; /*When this bit is set the AFM(Address Filtering Module) module blocks all incoming broadcast frames. In addition it overrides all other filter settings. When this bit is reset the AFM module passes all received broadcast Frames.*/
|
||||
uint32_t pcf : 2; /*These bits control the forwarding of all control frames (including unicast and multicast Pause frames). 2'b00: MAC filters all control frames from reaching the application. 2'b01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. 2'b10: MAC forwards all control frames to application even if they fail the Address Filter. 2'b11: MAC forwards control frames that pass the Address Filter.The following conditions should be true for the Pause frames processing: Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register (Flow Control Register) to 1. Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set. Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.*/
|
||||
uint32_t saif : 1; /*When this bit is set the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset frames whose SA does not match the SA registers are marked as failing the SA Address filter.*/
|
||||
uint32_t safe : 1; /*When this bit is set the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails the MAC drops the frame. When this bit is reset the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison.*/
|
||||
uint32_t reserved10 : 1;
|
||||
uint32_t reserved11 : 5;
|
||||
uint32_t reserved16 : 1;
|
||||
uint32_t reserved17 : 3;
|
||||
uint32_t reserved20 : 1;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t reserved22 : 9;
|
||||
uint32_t receive_all : 1; /*When this bit is set the MAC Receiver module passes all received frames irrespective of whether they pass the address filter or not to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} gmacff;
|
||||
uint32_t reserved_1008;
|
||||
uint32_t reserved_100c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t miibusy : 1; /*This bit should read logic 0 before writing to PHY Addr Register and PHY data Register.During a PHY register access the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed there is no change in the functionality of this bit even when the PHY is not Present.*/
|
||||
uint32_t miiwrite : 1; /*When set this bit indicates to the PHY that this is a Write operation using the MII Data register. If this bit is not set it indicates that this is a Read operation that is placing the data in the MII Data register.*/
|
||||
uint32_t miicsrclk : 4; /*CSR clock range: 1.0 MHz ~ 2.5 MHz. 4'b0000: When the APB clock frequency is 80 MHz the MDC clock frequency is APB CLK/42 4'b0000: When the APB clock frequency is 40 MHz the MDC clock frequency is APB CLK/26.*/
|
||||
uint32_t miireg : 5; /*These bits select the desired MII register in the selected PHY device.*/
|
||||
uint32_t miidev : 5; /*This field indicates which of the 32 possible PHY devices are being accessed.*/
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} emacgmiiaddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t mii_data : 16; /*This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation.*/
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} emacmiidata;
|
||||
union {
|
||||
struct {
|
||||
uint32_t fcbba : 1; /*This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame the Application must set this bit to 1'b1. During a transfer of the Control Frame this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode when this bit is set (and TFCE is set) then backpressure is asserted by the MAC. During backpressure when the MAC receives a new frame the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode the BPA(backpressure activate) is automatically disabled.*/
|
||||
uint32_t tfce : 1; /*In the full-duplex mode when this bit is set the MAC enables the flow control operation to transmit Pause frames. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode when this bit is set the MAC enables the backpressure operation. When this bit is reset the backpressure feature is Disabled.*/
|
||||
uint32_t rfce : 1; /*When this bit is set the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset the decode function of the Pause frame is disabled.*/
|
||||
uint32_t upfd : 1; /*A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the EMACADDR0 High Register and EMACADDR0 Low Register. When this bit is reset the MAC only detects Pause frames with unique multicast address.*/
|
||||
uint32_t plt : 2; /*This field configures the threshold of the Pause timer automatic retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example if PT = 100H (256 slot-times) and PLT = 01 then a second Pause frame is automatically transmitted at 228 (256-28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: 2'b00: The threshold is Pause time minus 4 slot times (PT-4 slot times). 2'b01: The threshold is Pause time minus 28 slot times (PT-28 slot times). 2'b10: The threshold is Pause time minus 144 slot times (PT-144 slot times). 2'b11: The threshold is Pause time minus 256 slot times (PT-256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface.*/
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t dzpq : 1; /*When this bit is set it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer. When this bit is reset normal operation with automatic Zero-Quanta Pause frame generation is enabled.*/
|
||||
uint32_t reserved8 : 8;
|
||||
uint32_t pause_time : 16; /*This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} gmacfc;
|
||||
uint32_t reserved_101c;
|
||||
uint32_t reserved_1020;
|
||||
union {
|
||||
struct {
|
||||
uint32_t macrpes : 1; /*When high this bit indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state.*/
|
||||
uint32_t macrffcs : 2; /*When high this field indicates the active state of the FIFO Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller.*/
|
||||
uint32_t reserved3 : 1;
|
||||
uint32_t mtlrfwcas : 1; /*When high this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO.*/
|
||||
uint32_t mtlrfrcs : 2; /*This field gives the state of the Rx FIFO read Controller: 2'b00: IDLE state.2'b01: Reading frame data.2'b10: Reading frame status (or timestamp).2'b11: Flushing the frame data and status.*/
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t mtlrffls : 2; /*This field gives the status of the fill-level of the Rx FIFO: 2'b00: Rx FIFO Empty. 2'b01: Rx FIFO fill-level below flow-control deactivate threshold. 2'b10: Rx FIFO fill-level above flow-control activate threshold. 2'b11: Rx FIFO Full.*/
|
||||
uint32_t reserved10 : 6;
|
||||
uint32_t mactpes : 1; /*When high this bit indicates that the MAC MII transmit protocol engine is actively transmitting data and is not in the IDLE state.*/
|
||||
uint32_t mactfcs : 2; /*This field indicates the state of the MAC Transmit Frame Controller module: 2'b00: IDLE state. 2'b01: Waiting for status of previous frame or IFG or backoff period to be over. 2'b10: Generating and transmitting a Pause frame (in the full-duplex mode). 2'b11: Transferring input frame for transmission.*/
|
||||
uint32_t mactp : 1; /*When high this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-mode) and hence does not schedule any frame for transmission.*/
|
||||
uint32_t mtltfrcs : 2; /*This field indicates the state of the Tx FIFO Read Controller: 2'b00: IDLE state. 2'b01: READ state (transferring data to the MAC transmitter). 2'b10: Waiting for TxStatus from the MAC transmitter. 2'b11: Writing the received TxStatus or flushing the Tx FIFO.*/
|
||||
uint32_t mtltfwcs : 1; /*When high this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO.*/
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t mtltfnes : 1; /*When high this bit indicates that the MTL Tx FIFO is not empty and some data is left for Transmission.*/
|
||||
uint32_t mtltsffs : 1; /*When high this bit indicates that the MTL TxStatus FIFO is full. Therefore the MTL cannot accept any more frames for transmission.*/
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} emacdebug;
|
||||
uint32_t pmt_rwuffr; /*The MSB (31st bit) must be zero.Bit j[30:0] is the byte mask. If Bit 1/2/3/4 (byte number) of the byte mask is set the CRC block processes the Filter 1/2/3/4 Offset + j of the incoming packet(PWKPTR is 0/1/2/3).RWKPTR is 0:Filter 0 Byte Mask .RWKPTR is 1:Filter 1 Byte Mask RWKPTR is 2:Filter 2 Byte Mask RWKPTR is 3:Filter 3 Byte Mask RWKPTR is 4:Bit 3/11/19/27 specifies the address type defining the destination address type of the pattern.When the bit is set the pattern applies to only multicast packets*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t pwrdwn : 1; /*When set the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame.This bit must only be set when MGKPKTEN GLBLUCAST or RWKPKTEN bit is set high.*/
|
||||
uint32_t mgkpkten : 1; /*When set enables generation of a power management event because of magic packet reception.*/
|
||||
uint32_t rwkpkten : 1; /*When set enables generation of a power management event because of remote wake-up frame reception*/
|
||||
uint32_t reserved3 : 2;
|
||||
uint32_t mgkprcvd : 1; /*When set this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register.*/
|
||||
uint32_t rwkprcvd : 1; /*When set this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register.*/
|
||||
uint32_t reserved7 : 2;
|
||||
uint32_t glblucast : 1; /*When set enables any unicast packet filtered by the MAC (DAFilter) address recognition to be a remote wake-up frame.*/
|
||||
uint32_t reserved10 : 14;
|
||||
uint32_t rwkptr : 5; /*The maximum value of the pointer is 7 the detail information please refer to PMT_RWUFFR.*/
|
||||
uint32_t reserved29 : 2;
|
||||
uint32_t rwkfiltrst : 1; /*When this bit is set it resets the RWKPTR register to 3’b000.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} pmt_csr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tlpien : 1; /*When set this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register.*/
|
||||
uint32_t tlpiex : 1; /*When set this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI_TW_Timer has expired.This bit is cleared by a read into this register.*/
|
||||
uint32_t rlpien : 1; /*When set this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register.*/
|
||||
uint32_t rlpiex : 1; /*When set this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface exited the LPI state and resumed the normal reception. This bit is cleared by a read into this register.*/
|
||||
uint32_t reserved4 : 4;
|
||||
uint32_t tlpist : 1; /*When set this bit indicates that the MAC is transmitting the LPI pattern on the MII interface.*/
|
||||
uint32_t rlpist : 1; /*When set this bit indicates that the MAC is receiving the LPI pattern on the MII interface.*/
|
||||
uint32_t reserved10 : 6;
|
||||
uint32_t lpien : 1; /*When set this bit instructs the MAC Transmitter to enter the LPI state. When reset this bit instructs the MAC to exit the LPI state and resume normal transmission.This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.*/
|
||||
uint32_t pls : 1; /*This bit indicates the link status of the PHY.When set the link is considered to be okay (up) and when reset the link is considered to be down.*/
|
||||
uint32_t reserved18 : 1;
|
||||
uint32_t lpitxa : 1; /*This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side.If the LPITXA and LPIEN bits are set to 1 the MAC enters the LPI mode only after all outstanding frames and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame.When this bit is 0 the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.*/
|
||||
uint32_t reserved20 : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} gmaclpi_crs;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lpi_tw_timer : 16; /*This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer.*/
|
||||
uint32_t lpi_ls_timer : 10; /*This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI_LS_Timer reaches the programmed terminal count. The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard.*/
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} gmaclpitimerscontrol;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 1;
|
||||
uint32_t reserved1 : 1;
|
||||
uint32_t reserved2 : 1;
|
||||
uint32_t pmtints : 1; /*This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bit[5] and Bit[6] in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. This bit is valid only when you select the optional PMT module during core configuration.*/
|
||||
uint32_t reserved4 : 1;
|
||||
uint32_t reserved5 : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t reserved8 : 1;
|
||||
uint32_t reserved9 : 1;
|
||||
uint32_t lpiis : 1; /*When the Energy Efficient Ethernet feature is enabled this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit[0] of Register (LPI Control and Status Register).*/
|
||||
uint32_t reserved11 : 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} emacints;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 1;
|
||||
uint32_t reserved1 : 1;
|
||||
uint32_t reserved2 : 1;
|
||||
uint32_t pmtintmask : 1; /*When set this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register (Interrupt Status Register).*/
|
||||
uint32_t reserved4 : 5;
|
||||
uint32_t reserved9 : 1;
|
||||
uint32_t lpiintmask : 1; /*When set this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register (Interrupt Status Register).*/
|
||||
uint32_t reserved11 : 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} emacintmask;
|
||||
union {
|
||||
struct {
|
||||
uint32_t address0_hi : 16; /*This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
|
||||
uint32_t reserved16 : 15;
|
||||
uint32_t address_enable0 : 1; /*This bit is always set to 1.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} emacaddr0high;
|
||||
uint32_t emacaddr0low; /*This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t mac_address1_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the second 6-byte MAC Address.*/
|
||||
uint32_t reserved16 : 8;
|
||||
uint32_t mask_byte_control : 6; /*These bits are mask control bits for comparison of each of the EMACADDR1 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR1 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR1 High [15:8]. Bit[28]: EMACADDR1 High [7:0]. Bit[27]: EMACADDR1 Low [31:24]. Bit[24]: EMACADDR1 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
|
||||
uint32_t source_address : 1; /*When this bit is set the EMACADDR1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR1[47:0] is used to compare with the DA fields of the received frame.*/
|
||||
uint32_t address_enable1 : 1; /*When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} emacaddr1high;
|
||||
uint32_t emacaddr1low; /*This field contains the lower 32 bits of the second 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t mac_address2_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the third 6-byte MAC address.*/
|
||||
uint32_t reserved16 : 8;
|
||||
uint32_t mask_byte_control2 : 6; /*These bits are mask control bits for comparison of each of the EMACADDR2 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR2 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR2 High [15:8]. Bit[28]: EMACADDR2 High [7:0]. Bit[27]: EMACADDR2 Low [31:24]. Bit[24]: EMACADDR2 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
|
||||
uint32_t source_address2 : 1; /*When this bit is set the EMACADDR2[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR2[47:0] is used to compare with the DA fields of the received frame.*/
|
||||
uint32_t address_enable2 : 1; /*When this bit is set the address filter module uses the third MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} emacaddr2high;
|
||||
uint32_t emacaddr2low; /*This field contains the lower 32 bits of the third 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t mac_address3_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the fourth 6-byte MAC address.*/
|
||||
uint32_t reserved16 : 8;
|
||||
uint32_t mask_byte_control3 : 6; /*These bits are mask control bits for comparison of each of the EMACADDR3 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR3 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR3 High [15:8]. Bit[28]: EMACADDR3 High [7:0]. Bit[27]: EMACADDR3 Low [31:24]. Bit[24]: EMACADDR3 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
|
||||
uint32_t source_address3 : 1; /*When this bit is set the EMACADDR3[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR3[47:0] is used to compare with the DA fields of the received frame.*/
|
||||
uint32_t address_enable3 : 1; /*When this bit is set the address filter module uses the fourth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} emacaddr3high;
|
||||
uint32_t emacaddr3low; /*This field contains the lower 32 bits of the fourth 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t mac_address4_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the fifth 6-byte MAC address.*/
|
||||
uint32_t reserved16 : 8;
|
||||
uint32_t mask_byte_control4 : 6; /*These bits are mask control bits for comparison of each of the EMACADDR4 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR4 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR4 High [15:8]. Bit[28]: EMACADDR4 High [7:0]. Bit[27]: EMACADDR4 Low [31:24]. Bit[24]: EMACADDR4 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
|
||||
uint32_t source_address4 : 1; /*When this bit is set the EMACADDR4[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR4[47:0] is used to compare with the DA fields of the received frame.*/
|
||||
uint32_t address_enable4 : 1; /*When this bit is set the address filter module uses the fifth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} emacaddr4high;
|
||||
uint32_t emacaddr4low; /*This field contains the lower 32 bits of the fifth 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t mac_address5_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the sixth 6-byte MAC address.*/
|
||||
uint32_t reserved16 : 8;
|
||||
uint32_t mask_byte_control5 : 6; /*These bits are mask control bits for comparison of each of the EMACADDR5 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR5 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR5 High [15:8]. Bit[28]: EMACADDR5 High [7:0]. Bit[27]: EMACADDR5 Low [31:24]. Bit[24]: EMACADDR5 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
|
||||
uint32_t source_address5 : 1; /*When this bit is set the EMACADDR5[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR5[47:0] is used to compare with the DA fields of the received frame.*/
|
||||
uint32_t address_enable5 : 1; /*When this bit is set the address filter module uses the sixth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} emacaddr5high;
|
||||
uint32_t emacaddr5low; /*This field contains the lower 32 bits of the sixth 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t mac_address6_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the seventh 6-byte MAC Address.*/
|
||||
uint32_t reserved16 : 8;
|
||||
uint32_t mask_byte_control6 : 6; /*These bits are mask control bits for comparison of each of the EMACADDR6 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR6 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR6 High [15:8]. Bit[28]: EMACADDR6 High [7:0]. Bit[27]: EMACADDR6 Low [31:24]. Bit[24]: EMACADDR6 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
|
||||
uint32_t source_address6 : 1; /*When this bit is set the EMACADDR6[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR6[47:0] is used to compare with the DA fields of the received frame.*/
|
||||
uint32_t address_enable6 : 1; /*When this bit is set the address filter module uses the seventh MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} emacaddr6high;
|
||||
uint32_t emacaddr6low; /*This field contains the lower 32 bits of the seventh 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t mac_address7_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the eighth 6-byte MAC Address.*/
|
||||
uint32_t reserved16 : 8;
|
||||
uint32_t mask_byte_control7 : 6; /*These bits are mask control bits for comparison of each of the EMACADDR7 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR7 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR7 High [15:8]. Bit[28]: EMACADDR7 High [7:0]. Bit[27]: EMACADDR7 Low [31:24]. Bit[24]: EMACADDR7 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
|
||||
uint32_t source_address7 : 1; /*When this bit is set the EMACADDR7[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR7[47:0] is used to compare with the DA fields of the received frame.*/
|
||||
uint32_t address_enable7 : 1; /*When this bit is set the address filter module uses the eighth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} emacaddr7high;
|
||||
uint32_t emacaddr7low; /*This field contains the lower 32 bits of the eighth 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/
|
||||
uint32_t reserved_1080;
|
||||
uint32_t reserved_1084;
|
||||
uint32_t reserved_1088;
|
||||
uint32_t reserved_108c;
|
||||
uint32_t reserved_1090;
|
||||
uint32_t reserved_1094;
|
||||
uint32_t reserved_1098;
|
||||
uint32_t reserved_109c;
|
||||
uint32_t reserved_10a0;
|
||||
uint32_t reserved_10a4;
|
||||
uint32_t reserved_10a8;
|
||||
uint32_t reserved_10ac;
|
||||
uint32_t reserved_10b0;
|
||||
uint32_t reserved_10b4;
|
||||
uint32_t reserved_10b8;
|
||||
uint32_t reserved_10bc;
|
||||
uint32_t reserved_10c0;
|
||||
uint32_t reserved_10c4;
|
||||
uint32_t reserved_10c8;
|
||||
uint32_t reserved_10cc;
|
||||
uint32_t reserved_10d0;
|
||||
uint32_t reserved_10d4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t link_mode : 1; /*This bit indicates the current mode of operation of the link: 1'b0: Half-duplex mode. 1'b1: Full-duplex mode.*/
|
||||
uint32_t link_speed : 2; /*This bit indicates the current speed of the link: 2'b00: 2.5 MHz. 2'b01: 25 MHz. 2'b10: 125 MHz.*/
|
||||
uint32_t reserved3 : 1;
|
||||
uint32_t jabber_timeout : 1; /*This bit indicates whether there is jabber timeout error (1'b1) in the received Frame.*/
|
||||
uint32_t reserved5 : 1;
|
||||
uint32_t reserved6 : 10;
|
||||
uint32_t reserved16 : 1;
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} emaccstatus;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdogto : 14; /*When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG is reset this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field such frame is terminated and declared as an error frame.*/
|
||||
uint32_t reserved14 : 2;
|
||||
uint32_t pwdogen : 1; /*When this bit is set and Bit[23] (WD) of EMACCONFIG_REG is reset the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared the watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in EMACCONFIG_REG.*/
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} emacwdogto;
|
||||
} emac_mac_dev_t;
|
||||
|
||||
extern emac_mac_dev_t EMAC_MAC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
17
tools/sdk/include/soc/soc/emac_periph.h
Normal file
17
tools/sdk/include/soc/soc/emac_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/emac_reg_v2.h"
|
||||
#include "soc/emac_ex_reg.h"
|
||||
File diff suppressed because it is too large
Load Diff
@ -12,8 +12,7 @@
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_GPIO_PERIPH_H
|
||||
#define _SOC_GPIO_PERIPH_H
|
||||
#pragma once
|
||||
#include "stdint.h"
|
||||
#include "soc/gpio_pins.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
@ -31,5 +30,3 @@ extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT];
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _SOC_GPIO_PERIPH_H
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct gpio_sd_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty: 8;
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct gpio_dev_s {
|
||||
uint32_t bt_select; /*NA*/
|
||||
uint32_t out; /*GPIO0~31 output value*/
|
||||
uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct hinf_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t user_id_fn1: 16;
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct host_dev_s {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
uint32_t reserved_8;
|
||||
|
||||
17
tools/sdk/include/soc/soc/hwcrypto_periph.h
Normal file
17
tools/sdk/include/soc/soc/hwcrypto_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/dport_reg.h"
|
||||
#include "soc/hwcrypto_reg.h"
|
||||
17
tools/sdk/include/soc/soc/i2c_periph.h
Normal file
17
tools/sdk/include/soc/soc/i2c_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/i2c_struct.h"
|
||||
#include "soc/i2c_reg.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct i2c_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t period:14; /*This register is used to configure the low level width of SCL clock.*/
|
||||
|
||||
17
tools/sdk/include/soc/soc/i2s_periph.h
Normal file
17
tools/sdk/include/soc/soc/i2s_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/i2s_struct.h"
|
||||
#include "soc/i2s_reg.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct i2s_dev_s {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
union {
|
||||
|
||||
@ -77,40 +77,6 @@
|
||||
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
|
||||
|
||||
/*
|
||||
* @attention
|
||||
* The PIN_PULL[UP|DWN]_[EN|DIS]() functions used to exist as macros in previous SDK versions.
|
||||
* Unfortunately, however, they do not work for some GPIOs on the ESP32 chip, which needs pullups
|
||||
* and -downs turned on and off through RTC registers. The functions still exist for compatibility
|
||||
* with older code, but are marked as deprecated in order to generate a warning.
|
||||
* Please replace them in this fashion: (make sure to include driver/gpio.h as well)
|
||||
* PIN_PULLUP_EN(GPIO_PIN_MUX_REG[x]) -> gpio_pullup_en(x)
|
||||
* PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[x]) -> gpio_pullup_dis(x)
|
||||
* PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[x]) -> gpio_pulldown_en(x)
|
||||
* PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[x]) -> gpio_pulldown_dis(x)
|
||||
*
|
||||
*/
|
||||
static inline void __attribute__ ((deprecated)) PIN_PULLUP_DIS(uint32_t PIN_NAME)
|
||||
{
|
||||
REG_CLR_BIT(PIN_NAME, FUN_PU);
|
||||
}
|
||||
|
||||
static inline void __attribute__ ((deprecated)) PIN_PULLUP_EN(uint32_t PIN_NAME)
|
||||
{
|
||||
REG_SET_BIT(PIN_NAME, FUN_PU);
|
||||
}
|
||||
|
||||
static inline void __attribute__ ((deprecated)) PIN_PULLDWN_DIS(uint32_t PIN_NAME)
|
||||
{
|
||||
REG_CLR_BIT(PIN_NAME, FUN_PD);
|
||||
}
|
||||
|
||||
static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME)
|
||||
{
|
||||
REG_SET_BIT(PIN_NAME, FUN_PD);
|
||||
}
|
||||
|
||||
|
||||
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
|
||||
|
||||
#define PIN_FUNC_GPIO 2
|
||||
|
||||
17
tools/sdk/include/soc/soc/ledc_periph.h
Normal file
17
tools/sdk/include/soc/soc/ledc_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/ledc_reg.h"
|
||||
#include "soc/ledc_struct.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct ledc_dev_s {
|
||||
struct {
|
||||
struct {
|
||||
union {
|
||||
@ -79,11 +79,6 @@ typedef volatile struct {
|
||||
uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/
|
||||
uint32_t reserved26: 5;
|
||||
};
|
||||
struct {
|
||||
uint32_t bit_num: 5 __attribute__((deprecated)); /*Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1.*/
|
||||
uint32_t div_num: 18 __attribute__((deprecated)); /*Deprecated in ESP-IDF 3.0. This is an alias to 'clock_divider' for backward compatibility with ESP-IDF 2.1.*/
|
||||
uint32_t place_holder: 9 __attribute__((deprecated)); /*A place holder to accommodate deprecated members*/
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
union {
|
||||
|
||||
47
tools/sdk/include/soc/soc/lldesc.h
Normal file
47
tools/sdk/include/soc/soc/lldesc.h
Normal file
@ -0,0 +1,47 @@
|
||||
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include <stdbool.h>
|
||||
#include "esp32/rom/lldesc.h"
|
||||
|
||||
//the size field has 12 bits, but 0 not for 4096.
|
||||
//to avoid possible problem when the size is not word-aligned, we only use 4096-4 per desc.
|
||||
/** Maximum size of data in the buffer that a DMA descriptor can hold. */
|
||||
#define LLDESC_MAX_NUM_PER_DESC (4096-4)
|
||||
|
||||
/**
|
||||
* Generate a linked list pointing to a (huge) buffer in an descriptor array.
|
||||
*
|
||||
* The caller should ensure there is enough size to hold the array, by calling
|
||||
* ``lldesc_get_required_num``.
|
||||
*
|
||||
* @param out_desc_array Output of a descriptor array, the head should be fed to the DMA.
|
||||
* @param buffer Buffer for the descriptors to point to.
|
||||
* @param size Size (or length for TX) of the buffer
|
||||
* @param isrx The RX DMA may require the buffer to be word-aligned, set to true for a RX link, otherwise false.
|
||||
*/
|
||||
void lldesc_setup_link(lldesc_t *out_desc_array, const void *buffer, int size, bool isrx);
|
||||
|
||||
/**
|
||||
* Get the number of descriptors required for a given buffer size.
|
||||
*
|
||||
* @param data_size Size to check descriptor num.
|
||||
*
|
||||
* @return Numbers required.
|
||||
*/
|
||||
static inline int lldesc_get_required_num(int data_size)
|
||||
{
|
||||
return (data_size + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC;
|
||||
}
|
||||
17
tools/sdk/include/soc/soc/mcpwm_periph.h
Normal file
17
tools/sdk/include/soc/soc/mcpwm_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/mcpwm_reg.h"
|
||||
#include "soc/mcpwm_struct.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct mcpwm_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
|
||||
|
||||
17
tools/sdk/include/soc/soc/pcnt_periph.h
Normal file
17
tools/sdk/include/soc/soc/pcnt_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/pcnt_reg.h"
|
||||
#include "soc/pcnt_struct.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct pcnt_dev_s {
|
||||
struct{
|
||||
union {
|
||||
struct {
|
||||
|
||||
17
tools/sdk/include/soc/soc/rmt_periph.h
Normal file
17
tools/sdk/include/soc/soc/rmt_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/rmt_reg.h"
|
||||
#include "soc/rmt_struct.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct rmt_dev_s {
|
||||
uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.
|
||||
Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue
|
||||
and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/
|
||||
@ -235,7 +235,7 @@ typedef volatile struct {
|
||||
} rmt_dev_t;
|
||||
extern rmt_dev_t RMT;
|
||||
|
||||
typedef struct {
|
||||
typedef struct rmt_item32_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t duration0 :15;
|
||||
@ -248,7 +248,7 @@ typedef struct {
|
||||
} rmt_item32_t;
|
||||
|
||||
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
|
||||
typedef volatile struct {
|
||||
typedef volatile struct rmt_mem_s {
|
||||
struct {
|
||||
union {
|
||||
rmt_item32_t data32[64];
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc_periph.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -88,7 +89,7 @@ typedef enum {
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
typedef struct {
|
||||
typedef struct rtc_cpu_freq_config_s {
|
||||
rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived
|
||||
uint32_t source_freq_mhz; //!< Source clock frequency
|
||||
uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div
|
||||
@ -127,7 +128,7 @@ typedef enum {
|
||||
/**
|
||||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
typedef struct rtc_clk_config_s {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
rtc_cpu_freq_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
|
||||
@ -304,82 +305,7 @@ void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
|
||||
rtc_fast_freq_t rtc_clk_fast_freq_get();
|
||||
|
||||
/**
|
||||
* @brief Switch CPU frequency
|
||||
*
|
||||
* @note This function is deprecated and will be removed.
|
||||
* See rtc_clk_cpu_freq_config_set instead.
|
||||
*
|
||||
* If a PLL-derived frequency is requested (80, 160, 240 MHz), this function
|
||||
* will enable the PLL. Otherwise, PLL will be disabled.
|
||||
* Note: this function is not optimized for switching speed. It may take several
|
||||
* hundred microseconds to perform frequency switch.
|
||||
*
|
||||
* @param cpu_freq new CPU frequency
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated));
|
||||
|
||||
/**
|
||||
* @brief Switch CPU frequency
|
||||
*
|
||||
* @note This function is deprecated and will be removed.
|
||||
* See rtc_clk_cpu_freq_set_config_fast instead.
|
||||
*
|
||||
* This is a faster version of rtc_clk_cpu_freq_set, which can handle some of
|
||||
* the frequency switch paths (XTAL -> PLL, PLL -> XTAL).
|
||||
* When switching from PLL to XTAL, PLL is not disabled (unlike rtc_clk_cpu_freq_set).
|
||||
* When switching back from XTAL to PLL, only the same PLL can be used.
|
||||
* Therefore it is not possible to switch 240 -> XTAL -> (80 or 160) using this
|
||||
* function.
|
||||
*
|
||||
* For unsupported cases, this function falls back to rtc_clk_cpu_freq_set.
|
||||
*
|
||||
* Unlike rtc_clk_cpu_freq_set, this function relies on static data, so it is
|
||||
* less safe to use it e.g. from a panic handler (when memory might be corrupted).
|
||||
*
|
||||
* @param cpu_freq new CPU frequency
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated));
|
||||
|
||||
/**
|
||||
* @brief Get the currently selected CPU frequency
|
||||
*
|
||||
* @note This function is deprecated and will be removed.
|
||||
* See rtc_clk_cpu_freq_get_config instead.
|
||||
*
|
||||
* Although CPU can be clocked by APLL and RTC 8M sources, such support is not
|
||||
* exposed through this library. As such, this function will not return
|
||||
* meaningful values when these clock sources are configured (e.g. using direct
|
||||
* access to clock selection registers). In debug builds, it will assert; in
|
||||
* release builds, it will return RTC_CPU_FREQ_XTAL.
|
||||
*
|
||||
* @return CPU frequency (one of rtc_cpu_freq_t values)
|
||||
*/
|
||||
rtc_cpu_freq_t rtc_clk_cpu_freq_get() __attribute__((deprecated));
|
||||
|
||||
/**
|
||||
* @brief Get corresponding frequency value for rtc_cpu_freq_t enum value
|
||||
*
|
||||
* @note This function is deprecated and will be removed.
|
||||
* See rtc_clk_cpu_freq_get/set_config instead.
|
||||
*
|
||||
* @param cpu_freq CPU frequency, on of rtc_cpu_freq_t values
|
||||
* @return CPU frequency, in HZ
|
||||
*/
|
||||
uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated));
|
||||
|
||||
/**
|
||||
* @brief Get rtc_cpu_freq_t enum value for given CPU frequency
|
||||
*
|
||||
* @note This function is deprecated and will be removed.
|
||||
* See rtc_clk_cpu_freq_mhz_to_config instead.
|
||||
*
|
||||
* @param cpu_freq_mhz CPU frequency, one of 80, 160, 240, 2, and XTAL frequency
|
||||
* @param[out] out_val output, rtc_cpu_freq_t value corresponding to the frequency
|
||||
* @return true if the given frequency value matches one of enum values
|
||||
*/
|
||||
bool rtc_clk_cpu_freq_from_mhz(int cpu_freq_mhz, rtc_cpu_freq_t* out_val) __attribute__((deprecated));
|
||||
|
||||
/**
|
||||
* @brief Get CPU frequency config corresponding to a rtc_cpu_freq_t value
|
||||
* @param cpu_freq CPU frequency enumeration value
|
||||
* @param[out] out_config Output, CPU frequency configuration structure
|
||||
@ -535,7 +461,7 @@ void rtc_clk_wait_for_slow_cycle();
|
||||
/**
|
||||
* @brief sleep configuration for rtc_sleep_init function
|
||||
*/
|
||||
typedef struct {
|
||||
typedef struct rtc_sleep_config_s {
|
||||
uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
|
||||
uint32_t rtc_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (RTC memory)
|
||||
uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
|
||||
@ -657,7 +583,7 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
|
||||
/**
|
||||
* RTC power and clock control initialization settings
|
||||
*/
|
||||
typedef struct {
|
||||
typedef struct rtc_config_s {
|
||||
uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
|
||||
uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
|
||||
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
|
||||
@ -693,7 +619,7 @@ void rtc_init(rtc_config_t cfg);
|
||||
/**
|
||||
* Structure describing vddsdio configuration
|
||||
*/
|
||||
typedef struct {
|
||||
typedef struct rtc_vddsdio_config_s {
|
||||
uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
|
||||
uint32_t enable : 1; //!< Enable VDDSDIO regulator
|
||||
uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct rtc_cntl_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
|
||||
|
||||
@ -35,13 +35,13 @@
|
||||
|
||||
#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x004)
|
||||
/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: Send LSB first */
|
||||
/*description: Receive LSB first */
|
||||
#define RTC_I2C_RX_LSB_FIRST BIT(7)
|
||||
#define RTC_I2C_RX_LSB_FIRST_M BIT(7)
|
||||
#define RTC_I2C_RX_LSB_FIRST_V (1)
|
||||
#define RTC_I2C_RX_LSB_FIRST_S (7)
|
||||
/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: Receive LSB first */
|
||||
/*description: Send LSB first */
|
||||
#define RTC_I2C_TX_LSB_FIRST BIT(6)
|
||||
#define RTC_I2C_TX_LSB_FIRST_M BIT(6)
|
||||
#define RTC_I2C_TX_LSB_FIRST_V (1)
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct rtc_io_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 14;
|
||||
|
||||
@ -12,13 +12,15 @@
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_RTC_PERIPH_H
|
||||
#define _SOC_RTC_PERIPH_H
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "soc/rtc_io_struct.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/rtc_cntl_struct.h"
|
||||
#include "soc/rtc_gpio_channel.h"
|
||||
#include "soc/gpio_pins.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
@ -58,5 +60,3 @@ extern const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT];
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _SOC_RTC_PERIPH_H
|
||||
|
||||
@ -47,12 +47,10 @@ without description where were CPUs when it happened.
|
||||
@endcode
|
||||
*/
|
||||
|
||||
#ifndef _SOC_RTC_WDT_H
|
||||
#define _SOC_RTC_WDT_H
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/rtc_periph.h"
|
||||
#include "esp_err.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
@ -198,5 +196,3 @@ bool rtc_wdt_is_on();
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _SOC_RTC_WDT_H
|
||||
|
||||
@ -12,9 +12,7 @@
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SDIO_SLAVE_PERIPH_H_
|
||||
#define _SOC_SDIO_SLAVE_PERIPH_H_
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
//include soc related (generated) definitions
|
||||
#include "soc/sdio_slave_pins.h"
|
||||
@ -45,5 +43,3 @@ extern const sdio_slave_slot_info_t sdio_slave_slot_info[];
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SDIO_SLAVE_PERIPH_H_ */
|
||||
@ -12,9 +12,7 @@
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SDMMC_PERIPH_H_
|
||||
#define _SOC_SDMMC_PERIPH_H_
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
//include soc related (generated) definitions
|
||||
#include "soc/sdmmc_pins.h"
|
||||
@ -49,5 +47,3 @@ extern const sdmmc_slot_info_t sdmmc_slot_info[];
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SDMMC_PERIPH_H_ */
|
||||
@ -22,7 +22,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
typedef struct sdmmc_desc_s {
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t disable_int_on_completion: 1;
|
||||
uint32_t last_descriptor: 1;
|
||||
@ -47,7 +47,7 @@ typedef struct {
|
||||
_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
|
||||
|
||||
|
||||
typedef struct {
|
||||
typedef struct sdmmc_hw_cmd_s {
|
||||
uint32_t cmd_index: 6; ///< Command index
|
||||
uint32_t response_expect: 1; ///< set if response is expected
|
||||
uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected
|
||||
@ -76,7 +76,7 @@ typedef struct {
|
||||
_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
|
||||
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct sdmmc_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t controller_reset: 1;
|
||||
|
||||
17
tools/sdk/include/soc/soc/sens_periph.h
Normal file
17
tools/sdk/include/soc/soc/sens_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/sens_reg.h"
|
||||
#include "soc/sens_struct.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct sens_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_clk_div: 8;
|
||||
|
||||
17
tools/sdk/include/soc/soc/sigmadelta_periph.h
Normal file
17
tools/sdk/include/soc/soc/sigmadelta_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/gpio_sd_struct.h"
|
||||
#include "soc/gpio_sd_reg.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct slc_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_tx_rst: 1;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
@ -20,40 +20,7 @@
|
||||
#include "esp_assert.h"
|
||||
#endif
|
||||
|
||||
//Register Bits{{
|
||||
#define BIT31 0x80000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT15 0x00008000
|
||||
#define BIT14 0x00004000
|
||||
#define BIT13 0x00002000
|
||||
#define BIT12 0x00001000
|
||||
#define BIT11 0x00000800
|
||||
#define BIT10 0x00000400
|
||||
#define BIT9 0x00000200
|
||||
#define BIT8 0x00000100
|
||||
#define BIT7 0x00000080
|
||||
#define BIT6 0x00000040
|
||||
#define BIT5 0x00000020
|
||||
#define BIT4 0x00000010
|
||||
#define BIT3 0x00000008
|
||||
#define BIT2 0x00000004
|
||||
#define BIT1 0x00000002
|
||||
#define BIT0 0x00000001
|
||||
//}}
|
||||
#include <esp_bit_defs.h>
|
||||
|
||||
#define PRO_CPU_NUM (0)
|
||||
#define APP_CPU_NUM (1)
|
||||
@ -63,7 +30,7 @@
|
||||
#define SOC_IROM_HIGH 0x40400000
|
||||
#define SOC_DROM_LOW 0x3F400000
|
||||
#define SOC_DROM_HIGH 0x3F800000
|
||||
#define SOC_DRAM_LOW 0x3FAE0000
|
||||
#define SOC_DRAM_LOW 0x3FFAE000
|
||||
#define SOC_DRAM_HIGH 0x40000000
|
||||
#define SOC_RTC_IRAM_LOW 0x400C0000
|
||||
#define SOC_RTC_IRAM_HIGH 0x400C2000
|
||||
@ -136,12 +103,6 @@
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
#define ETS_CACHED_ADDR(addr) (addr)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
#define BIT64(nr) (1ULL << (nr))
|
||||
#else
|
||||
#define BIT(nr) (1 << (nr))
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
@ -281,6 +242,7 @@
|
||||
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
|
||||
#define SPI_CLK_DIV 4
|
||||
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
|
||||
#define GPIO_MATRIX_DELAY_NS 25
|
||||
//}}
|
||||
|
||||
/* Overall memory map */
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
@ -48,7 +49,7 @@
|
||||
|
||||
#define SOC_MEM_BT_EM_PER_SYNC_SIZE 0x870
|
||||
|
||||
#define SOC_MEM_BT_EM_BREDR_REAL_END (SOC_MEM_BT_EM_BREDR_NO_SYNC_END + CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF * SOC_MEM_BT_EM_PER_SYNC_SIZE)
|
||||
#define SOC_MEM_BT_EM_BREDR_REAL_END (SOC_MEM_BT_EM_BREDR_NO_SYNC_END + CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF * SOC_MEM_BT_EM_PER_SYNC_SIZE)
|
||||
|
||||
#endif //CONFIG_BT_ENABLED
|
||||
|
||||
@ -161,7 +162,7 @@ inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
|
||||
{
|
||||
bool r;
|
||||
r = ((intptr_t)p >= SOC_BYTE_ACCESSIBLE_LOW && (intptr_t)p < SOC_BYTE_ACCESSIBLE_HIGH);
|
||||
#if CONFIG_SPIRAM_SUPPORT
|
||||
#if CONFIG_ESP32_SPIRAM_SUPPORT
|
||||
r |= ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
|
||||
#endif
|
||||
return r;
|
||||
@ -202,3 +203,10 @@ inline static bool IRAM_ATTR esp_ptr_in_diram_dram(const void *p) {
|
||||
inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) {
|
||||
return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH);
|
||||
}
|
||||
|
||||
|
||||
inline static bool IRAM_ATTR esp_stack_ptr_is_sane(uint32_t sp)
|
||||
{
|
||||
//Check if stack ptr is in between SOC_DRAM_LOW and SOC_DRAM_HIGH, and 16 byte aligned.
|
||||
return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0));
|
||||
}
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
@ -12,8 +12,11 @@
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SPI_PINS_H_
|
||||
#define _SOC_SPI_PINS_H_
|
||||
#ifndef _SOC_SPI_CAPS_H_
|
||||
#define _SOC_SPI_CAPS_H_
|
||||
|
||||
#define SOC_SPI_PERIPH_NUM 3
|
||||
#define SOC_SPI_DMA_CHAN_NUM 2
|
||||
|
||||
#define SPI_IOMUX_PIN_NUM_MISO 7
|
||||
#define SPI_IOMUX_PIN_NUM_MOSI 8
|
||||
@ -22,6 +25,14 @@
|
||||
#define SPI_IOMUX_PIN_NUM_WP 10
|
||||
#define SPI_IOMUX_PIN_NUM_HD 9
|
||||
|
||||
//For D2WD and PICO-D4 chip
|
||||
#define SPI_D2WD_PIN_NUM_MISO 17
|
||||
#define SPI_D2WD_PIN_NUM_MOSI 8
|
||||
#define SPI_D2WD_PIN_NUM_CLK 6
|
||||
#define SPI_D2WD_PIN_NUM_CS 16
|
||||
#define SPI_D2WD_PIN_NUM_WP 7
|
||||
#define SPI_D2WD_PIN_NUM_HD 11
|
||||
|
||||
#define HSPI_IOMUX_PIN_NUM_MISO 12
|
||||
#define HSPI_IOMUX_PIN_NUM_MOSI 13
|
||||
#define HSPI_IOMUX_PIN_NUM_CLK 14
|
||||
@ -36,4 +47,8 @@
|
||||
#define VSPI_IOMUX_PIN_NUM_WP 22
|
||||
#define VSPI_IOMUX_PIN_NUM_HD 21
|
||||
|
||||
#endif /* _SOC_SPI_PINS_H_ */
|
||||
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
|
||||
|
||||
#define SOC_SPI_SUPPORT_AS_CS 1 //Support to toggle the CS while the clock toggles
|
||||
|
||||
#endif /* _SOC_SPI_CAPS_H_ */
|
||||
@ -12,14 +12,12 @@
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SPI_PERIPH_H_
|
||||
#define _SOC_SPI_PERIPH_H_
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/periph_defs.h"
|
||||
//include soc related (generated) definitions
|
||||
#include "soc/spi_pins.h"
|
||||
#include "soc/spi_caps.h"
|
||||
#include "soc/spi_reg.h"
|
||||
#include "soc/spi_struct.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
@ -54,13 +52,12 @@ typedef struct {
|
||||
const uint8_t irq; //irq source for interrupt mux
|
||||
const uint8_t irq_dma; //dma irq source for interrupt mux
|
||||
const periph_module_t module; //peripheral module, for enabling clock etc
|
||||
const int func; //function number for IOMUX
|
||||
spi_dev_t *hw; //Pointer to the hardware registers
|
||||
} spi_signal_conn_t;
|
||||
|
||||
extern const spi_signal_conn_t spi_periph_signal[3];
|
||||
extern const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SPI_PERIPH_H_ */
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct spi_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 16; /*reserved*/
|
||||
|
||||
17
tools/sdk/include/soc/soc/syscon_periph.h
Normal file
17
tools/sdk/include/soc/soc/syscon_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "soc/syscon_struct.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct syscon_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t pre_div: 10;
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct timg_dev_s {
|
||||
struct{
|
||||
union {
|
||||
struct {
|
||||
|
||||
17
tools/sdk/include/soc/soc/timer_periph.h
Normal file
17
tools/sdk/include/soc/soc/timer_periph.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/timer_group_reg.h"
|
||||
#include "soc/timer_group_struct.h"
|
||||
16
tools/sdk/include/soc/soc/touch_periph.h
Normal file
16
tools/sdk/include/soc/soc/touch_periph.h
Normal file
@ -0,0 +1,16 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/touch_channel.h"
|
||||
26
tools/sdk/include/soc/soc/uart_caps.h
Normal file
26
tools/sdk/include/soc/soc/uart_caps.h
Normal file
@ -0,0 +1,26 @@
|
||||
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SOC_UART_NUM 3
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
20
tools/sdk/include/soc/soc/uart_periph.h
Normal file
20
tools/sdk/include/soc/soc/uart_periph.h
Normal file
@ -0,0 +1,20 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/uart_caps.h"
|
||||
#include "soc/uart_reg.h"
|
||||
#include "soc/uart_struct.h"
|
||||
#include "soc/uart_channel.h"
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct uart_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct uhci_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/
|
||||
|
||||
Reference in New Issue
Block a user