mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
synced 2025-07-31 03:07:16 +02:00
IDF release/v4.0 08219f3cf
This commit is contained in:
me-no-dev
399
tools/sdk/include/soc/hal/emac.h
Normal file
399
tools/sdk/include/soc/hal/emac.h
Normal file
@ -0,0 +1,399 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp_err.h"
|
||||
#include "soc/emac_dma_struct.h"
|
||||
#include "soc/emac_mac_struct.h"
|
||||
#include "soc/emac_ext_struct.h"
|
||||
|
||||
#define EMAC_MEDIA_INTERFACE_MII (0)
|
||||
#define EMAC_MEDIA_INTERFACE_RMII (1)
|
||||
|
||||
#define EMAC_WATCHDOG_ENABLE (0)
|
||||
#define EMAC_WATCHDOG_DISABLE (1)
|
||||
|
||||
#define EMAC_JABBER_ENABLE (0)
|
||||
#define EMAC_JABBER_DISABLE (1)
|
||||
|
||||
#define EMAC_INTERFRAME_GAP_96BIT (0)
|
||||
#define EMAC_INTERFRAME_GAP_88BIT (1)
|
||||
#define EMAC_INTERFRAME_GAP_80BIT (2)
|
||||
#define EMAC_INTERFRAME_GAP_72BIT (3)
|
||||
#define EMAC_INTERFRAME_GAP_64BIT (4)
|
||||
#define EMAC_INTERFRAME_GAP_56BIT (5)
|
||||
#define EMAC_INTERFRAME_GAP_48BIT (6)
|
||||
#define EMAC_INTERFRAME_GAP_40BIT (7)
|
||||
|
||||
#define EMAC_CARRIERSENSE_ENABLE (0)
|
||||
#define EMAC_CARRIERSENSE_DISABLE (1)
|
||||
|
||||
#define EMAC_PORT_1000MBPS (0)
|
||||
#define EMAC_PORT_10_100MBPS (1)
|
||||
|
||||
#define EMAC_SPEED_10M (0)
|
||||
#define EMAC_SPEED_100M (1)
|
||||
|
||||
#define EMAC_RECEIVE_OWN_ENABLE (0)
|
||||
#define EMAC_RECEIVE_OWN_DISABLE (1)
|
||||
|
||||
#define EMAC_LOOPBACK_DISABLE (0)
|
||||
#define EMAC_LOOPBACK_ENABLE (1)
|
||||
|
||||
#define EMAC_DUPLEX_HALF (0)
|
||||
#define EMAC_DUPLEX_FULL (1)
|
||||
|
||||
#define EMAC_CHECKSUM_SW (0)
|
||||
#define EMAC_CHECKSUM_HW (1)
|
||||
|
||||
#define EMAC_RETRY_TRANSMISSION_ENABLE (0)
|
||||
#define EMAC_RETRY_TRANSMISSION_DISABLE (1)
|
||||
|
||||
#define EMAC_AUTO_PAD_CRC_STRIP_DISABLE (0)
|
||||
#define EMAC_AUTO_PAD_CRC_STRIP_ENABLE (1)
|
||||
|
||||
#define EMAC_BACKOFF_LIMIT_10 (0)
|
||||
#define EMAC_BACKOFF_LIMIT_8 (1)
|
||||
#define EMAC_BACKOFF_LIMIT_4 (2)
|
||||
#define EMAC_BACKOFF_LIMIT_1 (3)
|
||||
|
||||
#define EMAC_DEFERRAL_CHECK_DISABLE (0)
|
||||
#define EMAC_DEFERRAL_CHECK_ENABLE (1)
|
||||
|
||||
#define EMAC_PREAMBLE_LENGTH_7 (0)
|
||||
#define EMAC_PREAMBLE_LENGTH_5 (1)
|
||||
#define EMAC_PREAMBLE_LENGTH_3 (2)
|
||||
|
||||
#define EMAC_RECEIVE_ALL_DISABLE (0)
|
||||
#define EMAC_RECEIVE_ALL_ENABLE (1)
|
||||
|
||||
#define EMAC_SOURCE_ADDR_FILTER_DISABLE (0)
|
||||
#define EMAC_SOURCE_ADDR_FILTER_NORMAL (2)
|
||||
#define EMAC_SOURCE_ADDR_FILTER_INVERSE (3)
|
||||
|
||||
#define EMAC_CONTROL_FRAME_BLOCKALL (0)
|
||||
#define EMAC_CONTROL_FRAME_FORWARDALL_PAUSE (1)
|
||||
#define EMAC_CONTROL_FRAME_FORWARDALL (2)
|
||||
#define EMAC_CONTROL_FRAME_FORWARDFILT (3)
|
||||
|
||||
#define EMAC_RECEPT_BROADCAST_ENABLE (0)
|
||||
#define EMAC_RECEPT_BROADCAST_DISABLE (1)
|
||||
|
||||
#define EMAC_DEST_ADDR_FILTER_NORMAL (0)
|
||||
#define EMAC_DEST_ADDR_FILTER_INVERSE (1)
|
||||
|
||||
#define EMAC_PROMISCUOUS_DISABLE (0)
|
||||
#define EMAC_PROMISCUOUS_ENABLE (1)
|
||||
|
||||
#define EMAC_PAUSE_TIME 0x1648
|
||||
|
||||
#define EMAC_ZERO_QUANTA_PAUSE_ENABLE (0)
|
||||
#define EMAC_ZERO_QUANTA_PAUSE_DISABLE (1)
|
||||
|
||||
#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_4 (0)
|
||||
#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_28 (1)
|
||||
#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_144 (2)
|
||||
#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_256
|
||||
|
||||
#define EMAC_UNICAST_PAUSE_DETECT_DISABLE (0)
|
||||
#define EMAC_UNICAST_PAUSE_DETECT_ENABLE (1)
|
||||
|
||||
#define EMAC_RECEIVE_FLOW_CONTROL_DISABLE (0)
|
||||
#define EMAC_RECEIVE_FLOW_CONTROL_ENABLE (1)
|
||||
|
||||
#define EMAC_TRANSMIT_FLOW_CONTROL_DISABLE (0)
|
||||
#define EMAC_TRANSMIT_FLOW_CONTROL_ENABLE (1)
|
||||
|
||||
#define EMAC_DROP_TCPIP_CHECKSUM_ERROR_ENABLE (0)
|
||||
#define EMAC_DROP_TCPIP_CHECKSUM_ERROR_DISABLE (1)
|
||||
|
||||
#define EMAC_RECEIVE_STORE_FORWARD_DISABLE (0)
|
||||
#define EMAC_RECEIVE_STORE_FORWARD_ENABLE (1)
|
||||
|
||||
#define EMAC_FLUSH_RECEIVED_FRAME_ENABLE (0)
|
||||
#define EMAC_FLUSH_RECEIVED_FRAME_DISABLE (1)
|
||||
|
||||
#define EMAC_TRANSMIT_STORE_FORWARD_DISABLE (0)
|
||||
#define EMAC_TRANSMIT_STORE_FORWARD_ENABLE (1)
|
||||
|
||||
#define EMAC_TRANSMIT_THRESHOLD_CONTROL_64 (0)
|
||||
#define EMAC_TRANSMIT_THRESHOLD_CONTROL_128 (1)
|
||||
#define EMAC_TRANSMIT_THRESHOLD_CONTROL_192 (2)
|
||||
#define EMAC_TRANSMIT_THRESHOLD_CONTROL_256 (3)
|
||||
#define EMAC_TRANSMIT_THRESHOLD_CONTROL_40 (4)
|
||||
#define EMAC_TRANSMIT_THRESHOLD_CONTROL_32 (5)
|
||||
#define EMAC_TRANSMIT_THRESHOLD_CONTROL_24 (6)
|
||||
#define EMAC_TRANSMIT_THRESHOLD_CONTROL_16 (7)
|
||||
|
||||
#define EMAC_FORWARD_ERROR_FRAME_DISABLE (0)
|
||||
#define EMAC_FORWARD_ERROR_FRAME_ENABLE (1)
|
||||
|
||||
#define EMAC_FORWARD_UNDERSIZED_GOOD_FRAME_DISABLE (0)
|
||||
#define EMAC_FORWARD_UNDERSIZED_GOOD_FRAME_ENABLE (1)
|
||||
|
||||
#define EMAC_RECEIVE_THRESHOLD_CONTROL_64 (0)
|
||||
#define EMAC_RECEIVE_THRESHOLD_CONTROL_32 (1)
|
||||
#define EMAC_RECEIVE_THRESHOLD_CONTROL_96 (2)
|
||||
#define EMAC_RECEIVE_THRESHOLD_CONTROL_128 (3)
|
||||
|
||||
#define EMAC_OPERATE_SECOND_FRAME_DISABLE (0)
|
||||
#define EMAC_OPERATE_SECOND_FRAME_ENABLE (1)
|
||||
|
||||
#define EMAC_MIXED_BURST_DISABLE (0)
|
||||
#define EMAC_MIXED_BURST_ENABLE (1)
|
||||
|
||||
#define EMAC_ADDR_ALIGN_BEATS_DISABLE (0)
|
||||
#define EMAC_ADDR_ALIGN_BEATS_ENABLE (1)
|
||||
|
||||
#define EMAC_UNUSE_SEPARATE_PBL (0)
|
||||
#define EMAC_USE_SEPARATE_PBL (1)
|
||||
|
||||
#define EMAC_DMA_BURST_LENGTH_1BEAT (1)
|
||||
#define EMAC_DMA_BURST_LENGTH_2BEAT (2)
|
||||
#define EMAC_DMA_BURST_LENGTH_4BEAT (4)
|
||||
#define EMAC_DMA_BURST_LENGTH_8BEAT (8)
|
||||
#define EMAC_DMA_BURST_LENGTH_16BEAT (16)
|
||||
#define EMAC_DMA_BURST_LENGTH_32BEAT (32)
|
||||
|
||||
#define EMAC_ENHANCED_DESCRIPTOR_DISABLE (0)
|
||||
#define EMAC_ENHANCED_DESCRIPTOR_ENABLE (1)
|
||||
|
||||
#define EMAC_DMA_ARBITRATION_SCHEME_ROUNDROBIN (0)
|
||||
#define EMAC_DMA_ARBITRATION_SCHEME_FIXEDPRIO (1)
|
||||
|
||||
#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_1_1 (0)
|
||||
#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_2_1 (1)
|
||||
#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_3_1 (2)
|
||||
#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_4_1 (3)
|
||||
|
||||
/**
|
||||
* @brief Ethernet DMA TX Descriptor
|
||||
*
|
||||
*/
|
||||
typedef struct {
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t Deferred : 1; /*!< MAC defers before transmission */
|
||||
uint32_t UnderflowErr : 1; /*!< DMA encountered an empty transmit buffer */
|
||||
uint32_t ExcessiveDeferral : 1; /*!< Excessive deferral of over 24,288 bit times */
|
||||
uint32_t CollisionCount : 4; /*!< Number of collisions occurred before transmitted */
|
||||
uint32_t VLanFrame : 1; /*!< Transmitted frame is a VLAN-type frame */
|
||||
uint32_t ExcessiveCollision : 1; /*!< Transmission aborted after 16 successive collisions */
|
||||
uint32_t LateCollision : 1; /*!< Collision occurred after the collision window */
|
||||
uint32_t NoCarrier : 1; /*!< Carrier Sense signal from the PHY was not asserted */
|
||||
uint32_t LossCarrier : 1; /*!< Loss of carrier occurred during transmission */
|
||||
uint32_t PayloadChecksumErr : 1; /*!< Checksum error in TCP/UDP/ICMP datagram payload */
|
||||
uint32_t FrameFlushed : 1; /*!< DMA or MTL flushed the frame */
|
||||
uint32_t JabberTimeout : 1; /*!< MAC transmitter has experienced a jabber timeout */
|
||||
uint32_t ErrSummary : 1; /*!< Error Summary */
|
||||
uint32_t IPHeadErr : 1; /*!< IP Header Error */
|
||||
uint32_t TxTimestampStatus : 1; /*!< Timestamp captured for the transmit frame */
|
||||
uint32_t VLANInsertControl : 2; /*!< VLAN tagging or untagging before transmitting */
|
||||
uint32_t SecondAddressChained : 1; /*!< Second address in the descriptor is Next Descriptor address */
|
||||
uint32_t TransmitEndRing : 1; /*!< Descriptor list reached its final descriptor */
|
||||
uint32_t ChecksumInsertControl : 2; /*!< Control checksum calculation and insertion */
|
||||
uint32_t CRCReplacementControl : 1; /*!< Control CRC replace */
|
||||
uint32_t TransmitTimestampEnable : 1; /*!< Enable IEEE1588 harware timestamping */
|
||||
uint32_t DisablePad : 1; /*!< Control add padding when frame short than 64 bytes */
|
||||
uint32_t DisableCRC : 1; /*!< Control append CRC to the end of frame */
|
||||
uint32_t FirstSegment : 1; /*!< Buffer contains the first segment of a frame */
|
||||
uint32_t LastSegment : 1; /*!< Buffer contains the last segment of a frame */
|
||||
uint32_t InterruptOnComplete : 1; /*!< Interrupt after frame transmitted */
|
||||
uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */
|
||||
};
|
||||
uint32_t Value;
|
||||
} TDES0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t TransmitBuffer1Size : 13; /*!< First data buffer byte size */
|
||||
uint32_t Reserved : 3; /*!< Reserved */
|
||||
uint32_t TransmitBuffer2Size : 13; /*!< Second data buffer byte size */
|
||||
uint32_t SAInsertControl : 3; /*!< Control MAC add or replace Source Address field */
|
||||
};
|
||||
uint32_t Value;
|
||||
} TDES1;
|
||||
uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
|
||||
uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
|
||||
uint32_t Reserved1; /*!< Reserved */
|
||||
uint32_t Reserved2; /*!< Reserved */
|
||||
uint32_t TimeStampLow; /*!< Transmit Frame Timestamp Low */
|
||||
uint32_t TimeStampHigh; /*!< Transmit Frame Timestamp High */
|
||||
} eth_dma_tx_descriptor_t;
|
||||
#define EMAC_DMATXDESC_CHECKSUM_BYPASS 0 /*!< Checksum engine bypass */
|
||||
#define EMAC_DMATXDESC_CHECKSUM_IPV4HEADER 1 /*!< IPv4 header checksum insertion */
|
||||
#define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPSEGMENT 2 /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
|
||||
#define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPFULL 3 /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
|
||||
|
||||
/**
|
||||
* @brief Ethernet DMA RX Descriptor
|
||||
*
|
||||
*/
|
||||
typedef struct {
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t ExtendStatusAvailable : 1; /*!< Extended statsu is available in RDES4 */
|
||||
uint32_t CRCErr : 1; /*!< CRC error occurred on frame */
|
||||
uint32_t DribbleBitErr : 1; /*!< frame contains non int multiple of 8 bits */
|
||||
uint32_t ReceiveErr : 1; /*!< Receive error */
|
||||
uint32_t ReceiveWatchdogTimeout : 1; /*!< Receive Watchdog timeout */
|
||||
uint32_t FrameType : 1; /*!< Ethernet type or IEEE802.3 */
|
||||
uint32_t LateCollision : 1; /*!< Late collision occurred during reception */
|
||||
uint32_t TSAvailIPChecksumErrGiantFrame : 1; /*!< Timestamp available or IP Checksum error or Giant frame */
|
||||
uint32_t LastDescriptor : 1; /*!< Last buffer of the frame */
|
||||
uint32_t FirstDescriptor : 1; /*!< First buffer of the frame */
|
||||
uint32_t VLANTag : 1; /*!< VLAN Tag: received frame is a VLAN frame */
|
||||
uint32_t OverflowErr : 1; /*!< Frame was damaged due to buffer overflow */
|
||||
uint32_t LengthErr : 1; /*!< Frame size not matching with length field */
|
||||
uint32_t SourceAddrFilterFail : 1; /*!< SA field of frame failed the SA filter */
|
||||
uint32_t DescriptorErr : 1; /*!< Frame truncated and DMA doesn't own next descriptor */
|
||||
uint32_t ErrSummary : 1; /*!< Error Summary, OR of all errors in RDES */
|
||||
uint32_t FrameLength : 14; /*!< Byte length of received frame */
|
||||
uint32_t DestinationAddrFilterFail : 1; /*!< Frame failed in the DA Filter in the MAC */
|
||||
uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */
|
||||
};
|
||||
uint32_t Value;
|
||||
} RDES0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ReceiveBuffer1Size : 13; /*!< First data buffer size in bytes */
|
||||
uint32_t Reserved1 : 1; /*!< Reserved */
|
||||
uint32_t SecondAddressChained : 1; /*!< Seconde address is the Next Descriptor address */
|
||||
uint32_t ReceiveEndOfRing : 1; /*!< Descriptor reached its final descriptor */
|
||||
uint32_t ReceiveBuffer2Size : 13; /*!< Second data buffer size in bytes */
|
||||
uint32_t Reserved : 2; /*!< Reserved */
|
||||
uint32_t DisableInterruptOnComplete : 1; /*!< Disable the assertion of interrupt to host */
|
||||
};
|
||||
uint32_t Value;
|
||||
} RDES1;
|
||||
uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
|
||||
uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t IPPayloadType : 3; /*!< Type of payload in the IP datagram */
|
||||
uint32_t IPHeadErr : 1; /*!< IP header error */
|
||||
uint32_t IPPayloadErr : 1; /*!< IP payload error */
|
||||
uint32_t IPChecksumBypass : 1; /*!< Checksum offload engine is bypassed */
|
||||
uint32_t IPv4PacketReceived : 1; /*!< Received packet is an IPv4 packet */
|
||||
uint32_t IPv6PacketReceived : 1; /*!< Received packet is an IPv6 packet */
|
||||
uint32_t MessageType : 4; /*!< PTP Message Type */
|
||||
uint32_t PTPFrameType : 1; /*!< PTP message is over Ethernet or IPv4/IPv6 */
|
||||
uint32_t PTPVersion : 1; /*!< Version of PTP protocol */
|
||||
uint32_t TimestampDropped : 1; /*!< Timestamp dropped because of overflow */
|
||||
uint32_t Reserved1 : 1; /*!< Reserved */
|
||||
uint32_t AVPacketReceived : 1; /*!< AV packet is received */
|
||||
uint32_t AVTaggedPacketReceived : 1; /*!< AV tagged packet is received */
|
||||
uint32_t VLANTagPrioVal : 3; /*!< VLAN tag's user value in the received packekt */
|
||||
uint32_t Reserved2 : 3; /*!< Reserved */
|
||||
uint32_t Layer3FilterMatch : 1; /*!< Received frame matches one of the enabled Layer3 IP */
|
||||
uint32_t Layer4FilterMatch : 1; /*!< Received frame matches one of the enabled Layer4 IP */
|
||||
uint32_t Layer3Layer4FilterNumberMatch : 2; /*!< Number of Layer3 and Layer4 Filter that matches the received frame */
|
||||
uint32_t Reserved3 : 4; /*!< Reserved */
|
||||
};
|
||||
uint32_t Value;
|
||||
} ExtendedStatus;
|
||||
uint32_t Reserved; /*!< Reserved */
|
||||
uint32_t TimeStampLow; /*!< Receive frame timestamp low */
|
||||
uint32_t TimeStampHigh; /*!< Receive frame timestamp high */
|
||||
} eth_dma_rx_descriptor_t;
|
||||
#define EMAC_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
|
||||
#define EMAC_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
|
||||
#define EMAC_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
|
||||
#define EMAC_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
|
||||
#define EMAC_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
|
||||
#define EMAC_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
|
||||
#define EMAC_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
|
||||
|
||||
#define EMAC_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
|
||||
#define EMAC_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
|
||||
#define EMAC_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
|
||||
|
||||
#define EMAC_DMADESC_OWNER_CPU (0)
|
||||
#define EMAC_DMADESC_OWNER_DMA (1)
|
||||
|
||||
typedef struct {
|
||||
emac_mac_dev_t *mac_regs;
|
||||
emac_dma_dev_t *dma_regs;
|
||||
emac_ext_dev_t *ext_regs;
|
||||
uint8_t **rx_buf;
|
||||
uint8_t **tx_buf;
|
||||
void *descriptors;
|
||||
eth_dma_rx_descriptor_t *rx_desc;
|
||||
eth_dma_tx_descriptor_t *tx_desc;
|
||||
} emac_hal_context_t;
|
||||
|
||||
void emac_hal_init(emac_hal_context_t *hal, void *descriptors,
|
||||
uint8_t **rx_buf, uint8_t **tx_buf);
|
||||
|
||||
void emac_hal_reset_desc_chain(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_lowlevel_init(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_reset(emac_hal_context_t *hal);
|
||||
|
||||
bool emac_hal_is_reset_done(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_csr_clock_range(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_init_mac_default(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_init_dma_default(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_speed(emac_hal_context_t *hal, uint32_t speed);
|
||||
|
||||
void emac_hal_set_duplex(emac_hal_context_t *hal, uint32_t duplex);
|
||||
|
||||
void emac_hal_set_promiscuous(emac_hal_context_t *hal, bool enable);
|
||||
|
||||
bool emac_hal_is_mii_busy(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write);
|
||||
|
||||
void emac_hal_set_phy_data(emac_hal_context_t *hal, uint32_t reg_value);
|
||||
|
||||
uint32_t emac_hal_get_phy_data(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr);
|
||||
|
||||
void emac_hal_start(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_stop(emac_hal_context_t *hal);
|
||||
|
||||
uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length);
|
||||
|
||||
uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *frames_remain);
|
||||
|
||||
void emac_hal_isr(void *arg);
|
||||
|
||||
void emac_hal_tx_complete_cb(void *arg);
|
||||
|
||||
void emac_hal_tx_unavail_cb (void *arg);
|
||||
|
||||
void emac_hal_rx_complete_cb (void *arg);
|
||||
|
||||
void emac_hal_rx_early_cb(void *arg);
|
||||
|
||||
void emac_hal_rx_unavail_cb(void *arg);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
48
tools/sdk/include/soc/hal/esp_flash_err.h
Normal file
48
tools/sdk/include/soc/hal/esp_flash_err.h
Normal file
@ -0,0 +1,48 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_err.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Possible errors returned from esp flash internal functions, these error codes
|
||||
* should be consistent with esp_err_t codes. But in order to make the source
|
||||
* files less dependent to esp_err_t, they use the error codes defined in this
|
||||
* replacable header. This header should ensure the consistency to esp_err_t.
|
||||
*/
|
||||
|
||||
enum {
|
||||
/* These codes should be consistent with esp_err_t errors. However, error codes with the same values are not
|
||||
* allowed in ESP-IDF. This is a workaround in order to not introduce a dependency between the "soc" and
|
||||
* "esp_common" components. The disadvantage is that the output of esp_err_to_name(ESP_ERR_FLASH_SIZE_NOT_MATCH)
|
||||
* will be ESP_ERR_INVALID_SIZE. */
|
||||
ESP_ERR_FLASH_SIZE_NOT_MATCH = ESP_ERR_INVALID_SIZE, ///< The chip doesn't have enough space for the current partition table
|
||||
ESP_ERR_FLASH_NO_RESPONSE = ESP_ERR_INVALID_RESPONSE, ///< Chip did not respond to the command, or timed out.
|
||||
};
|
||||
|
||||
//The ROM code has already taken 1 and 2, to avoid possible conflicts, start from 3.
|
||||
#define ESP_ERR_FLASH_NOT_INITIALISED (ESP_ERR_FLASH_BASE+3) ///< esp_flash_chip_t structure not correctly initialised by esp_flash_init().
|
||||
#define ESP_ERR_FLASH_UNSUPPORTED_HOST (ESP_ERR_FLASH_BASE+4) ///< Requested operation isn't supported via this host SPI bus (chip->spi field).
|
||||
#define ESP_ERR_FLASH_UNSUPPORTED_CHIP (ESP_ERR_FLASH_BASE+5) ///< Requested operation isn't supported by this model of SPI flash chip.
|
||||
#define ESP_ERR_FLASH_PROTECTED (ESP_ERR_FLASH_BASE+6) ///< Write operation failed due to chip's write protection being enabled.
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
28
tools/sdk/include/soc/hal/hal_defs.h
Normal file
28
tools/sdk/include/soc/hal/hal_defs.h
Normal file
@ -0,0 +1,28 @@
|
||||
// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_log.h"
|
||||
|
||||
// platform related stuff
|
||||
|
||||
#define HAL_SWAP32(word) __builtin_bswap32(word)
|
||||
#define HAL_SWAP64(word) __builtin_bswap64(word)
|
||||
|
||||
#define HAL_LOGE(...) ESP_LOGE(__VA_ARGS__)
|
||||
#define HAL_LOGW(...) ESP_LOGW(__VA_ARGS__)
|
||||
#define HAL_LOGI(...) ESP_LOGI(__VA_ARGS__)
|
||||
#define HAL_LOGD(...) ESP_LOGD(__VA_ARGS__)
|
||||
#define HAL_LOGV(...) ESP_LOGV(__VA_ARGS__)
|
||||
239
tools/sdk/include/soc/hal/spi_flash_hal.h
Normal file
239
tools/sdk/include/soc/hal/spi_flash_hal.h
Normal file
@ -0,0 +1,239 @@
|
||||
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The HAL is not public api, don't use in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The HAL layer for SPI Flash (common part)
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/spi_flash_ll.h"
|
||||
#include "hal/spi_types.h"
|
||||
#include "hal/spi_flash_types.h"
|
||||
#include "soc/soc_memory_layout.h"
|
||||
|
||||
/* Hardware host-specific constants */
|
||||
#define SPI_FLASH_HAL_MAX_WRITE_BYTES 64
|
||||
#define SPI_FLASH_HAL_MAX_READ_BYTES 64
|
||||
|
||||
/**
|
||||
* Generic driver context structure for all chips using the SPI peripheral.
|
||||
* Include this into the HEAD of the driver data for other driver
|
||||
* implementations that also use the SPI peripheral.
|
||||
*/
|
||||
typedef struct {
|
||||
spi_dev_t *spi; ///< Pointer to SPI peripheral registers (SP1, SPI2 or SPI3). Set before initialisation.
|
||||
int cs_num; ///< Which cs pin is used, 0-2.
|
||||
int extra_dummy;
|
||||
spi_flash_ll_clock_reg_t clock_conf;
|
||||
} spi_flash_memspi_data_t;
|
||||
|
||||
/// Configuration structure for the SPI driver.
|
||||
typedef struct {
|
||||
spi_host_device_t host_id; ///< SPI peripheral ID.
|
||||
int cs_num; ///< Which cs pin is used, 0-2.
|
||||
bool iomux; ///< Whether the IOMUX is used, used for timing compensation.
|
||||
int input_delay_ns; ///< Input delay on the MISO pin after the launch clock， used for timing compensation.
|
||||
esp_flash_speed_t speed;///< SPI flash clock speed to work at.
|
||||
} spi_flash_memspi_config_t;
|
||||
|
||||
/**
|
||||
* Configure SPI flash hal settings.
|
||||
*
|
||||
* @param data Buffer to hold configured data, the buffer should be in DRAM to be available when cache disabled
|
||||
* @param cfg Configurations to set
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: success
|
||||
* - ESP_ERR_INVALID_ARG: the data buffer is not in the DRAM.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_init(spi_flash_memspi_data_t *data_out, const spi_flash_memspi_config_t *cfg);
|
||||
|
||||
/**
|
||||
* Configure the device-related register before transactions.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
*
|
||||
* @return always return ESP_OK.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver);
|
||||
|
||||
/**
|
||||
* Send an user-defined spi transaction to the device.
|
||||
*
|
||||
* @note This is usually used when the memspi interface doesn't support some
|
||||
* particular commands. Since this function supports timing compensation, it is
|
||||
* also used to receive some data when the frequency is high.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param trans The transaction to send, also holds the received data.
|
||||
*
|
||||
* @return always return ESP_OK.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *driver, spi_flash_trans_t *trans);
|
||||
|
||||
/**
|
||||
* Erase whole flash chip by using the erase chip (C7h) command.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
*/
|
||||
void spi_flash_hal_erase_chip(spi_flash_host_driver_t *driver);
|
||||
|
||||
/**
|
||||
* Erase a specific sector by its start address through the sector erase (20h)
|
||||
* command.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param start_address Start address of the sector to erase.
|
||||
*/
|
||||
void spi_flash_hal_erase_sector(spi_flash_host_driver_t *driver, uint32_t start_address);
|
||||
|
||||
/**
|
||||
* Erase a specific 64KB block by its start address through the 64KB block
|
||||
* erase (D8h) command.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param start_address Start address of the block to erase.
|
||||
*/
|
||||
void spi_flash_hal_erase_block(spi_flash_host_driver_t *driver, uint32_t start_address);
|
||||
|
||||
/**
|
||||
* Program a page of the flash using the page program (02h) command.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param address Address of the page to program
|
||||
* @param buffer Data to program
|
||||
* @param length Size of the buffer in bytes, no larger than ``SPI_FLASH_HAL_MAX_WRITE_BYTES`` (64) bytes.
|
||||
*/
|
||||
void spi_flash_hal_program_page(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length);
|
||||
|
||||
/**
|
||||
* Read from the flash. Call ``spi_flash_hal_configure_host_read_mode`` to
|
||||
* configure the read command before calling this function.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param buffer Buffer to store the read data
|
||||
* @param address Address to read
|
||||
* @param length Length to read, no larger than ``SPI_FLASH_HAL_MAX_READ_BYTES`` (64) bytes.
|
||||
*
|
||||
* @return always return ESP_OK.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len);
|
||||
|
||||
/**
|
||||
* @brief Send the write enable (06h) or write disable (04h) command to the flash chip.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
* @param wp true to enable the write protection, otherwise false.
|
||||
*
|
||||
* @return always return ESP_OK.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *chip_drv, bool wp);
|
||||
|
||||
/**
|
||||
* Check whether the SPI host is idle and can perform other operations.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
*
|
||||
* @return ture if idle, otherwise false.
|
||||
*/
|
||||
bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver);
|
||||
|
||||
/**
|
||||
* @brief Configure the SPI host hardware registers for the specified io mode.
|
||||
*
|
||||
* Note that calling this configures SPI host registers, so if running any
|
||||
* other commands as part of set_io_mode() then these must be run before
|
||||
* calling this function.
|
||||
*
|
||||
* The command value, address length and dummy cycles are configured according
|
||||
* to the format of read commands:
|
||||
*
|
||||
* - command: 8 bits, value set.
|
||||
* - address: 24 bits
|
||||
* - dummy: cycles to compensate the input delay
|
||||
* - out & in data: 0 bits.
|
||||
*
|
||||
* The following commands still need to:
|
||||
*
|
||||
* - Read data: set address value and data (length and contents), no need
|
||||
* to touch command and dummy phases.
|
||||
* - Common read: set command value, address value (or length to 0 if not used)
|
||||
* - Common write: set command value, address value (or length to 0 if not
|
||||
* used), disable dummy phase, and set output data.
|
||||
*
|
||||
* @param driver The driver context
|
||||
* @param io_mode The HW read mode to use
|
||||
* @param addr_bitlen Length of the address phase, in bits
|
||||
* @param dummy_cyclelen_base Base cycles of the dummy phase, some extra dummy cycles may be appended to compensate the timing.
|
||||
* @param command Actual reading command to send to flash chip on the bus.
|
||||
*
|
||||
* @return always return ESP_OK.
|
||||
*/
|
||||
esp_err_t spi_flash_hal_configure_host_io_mode(spi_flash_host_driver_t *driver, uint32_t command, uint32_t addr_bitlen,
|
||||
int dummy_cyclelen_base, esp_flash_io_mode_t io_mode);
|
||||
|
||||
/**
|
||||
* Poll until the last operation is done.
|
||||
*
|
||||
* @param driver The driver context.
|
||||
*/
|
||||
void spi_flash_hal_poll_cmd_done(spi_flash_host_driver_t *driver);
|
||||
|
||||
/**
|
||||
* Check whether the given buffer can be used as the write buffer directly. If 'chip' is connected to the main SPI bus, we can only write directly from
|
||||
* regions that are accessible ith cache disabled. *
|
||||
*
|
||||
* @param driver The driver context
|
||||
* @param p The buffer holding data to send.
|
||||
*
|
||||
* @return True if the buffer can be used to send data, otherwise false.
|
||||
*/
|
||||
static inline bool spi_flash_hal_supports_direct_write(spi_flash_host_driver_t *driver, const void *p)
|
||||
{
|
||||
#ifdef ESP_PLATFORM
|
||||
bool direct_write = ( ((spi_flash_memspi_data_t *)driver->driver_data)->spi != &SPI1
|
||||
|| esp_ptr_in_dram(p) );
|
||||
#else
|
||||
//If it is not on real chips, there is no limitation that the data has to be in DRAM.
|
||||
bool direct_write = true;
|
||||
#endif
|
||||
return direct_write;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether the given buffer can be used as the read buffer directly. If 'chip' is connected to the main SPI bus, we can only read directly from
|
||||
* regions that are accessible ith cache disabled. *
|
||||
*
|
||||
* @param driver The driver context
|
||||
* @param p The buffer to hold the received data.
|
||||
*
|
||||
* @return True if the buffer can be used to receive data, otherwise false.
|
||||
*/
|
||||
static inline bool spi_flash_hal_supports_direct_read(spi_flash_host_driver_t *driver, const void *p)
|
||||
{
|
||||
#ifdef ESP_PLATFORM
|
||||
//currently the driver doesn't support to read through DMA, no word-aligned requirements
|
||||
bool direct_read = ( ((spi_flash_memspi_data_t *)driver->driver_data)->spi != &SPI1
|
||||
|| esp_ptr_in_dram(p) );
|
||||
#else
|
||||
//If it is not on real chips, there is no limitation that the data has to be in DRAM.
|
||||
bool direct_read = true;
|
||||
#endif
|
||||
return direct_read;
|
||||
}
|
||||
342
tools/sdk/include/soc/hal/spi_flash_ll.h
Normal file
342
tools/sdk/include/soc/hal/spi_flash_ll.h
Normal file
@ -0,0 +1,342 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The ll is not public api, don't use in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The Lowlevel layer for SPI Flash
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "soc/spi_periph.h"
|
||||
#include "hal/spi_types.h"
|
||||
#include "hal/spi_flash_types.h"
|
||||
#include <sys/param.h> // For MIN/MAX
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
//Supported clock register values
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_5MHZ ((spi_flash_ll_clock_reg_t){.val=0x0000F1CF}) ///< Clock set to 5 MHz
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_10MHZ ((spi_flash_ll_clock_reg_t){.val=0x000070C7}) ///< Clock set to 10 MHz
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_20MHZ ((spi_flash_ll_clock_reg_t){.val=0x00003043}) ///< Clock set to 20 MHz
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_26MHZ ((spi_flash_ll_clock_reg_t){.val=0x00002002}) ///< Clock set to 26 MHz
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_40MHZ ((spi_flash_ll_clock_reg_t){.val=0x00001001}) ///< Clock set to 40 MHz
|
||||
#define SPI_FLASH_LL_CLKREG_VAL_80MHZ ((spi_flash_ll_clock_reg_t){.val=0x80000000}) ///< Clock set to 80 MHz
|
||||
|
||||
/// Get the start address of SPI peripheral registers by the host ID
|
||||
#define spi_flash_ll_get_hw(host_id) ((host_id)==SPI1_HOST? &SPI1:((host_id)==SPI2_HOST?&SPI2:((host_id)==SPI3_HOST?&SPI3:({abort();(spi_dev_t*)0;}))))
|
||||
|
||||
/// type to store pre-calculated register value in above layers
|
||||
typedef typeof(SPI1.clock) spi_flash_ll_clock_reg_t;
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Control
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Reset peripheral registers before configuration and starting control
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_reset(spi_dev_t *dev)
|
||||
{
|
||||
dev->user.val = 0;
|
||||
dev->ctrl.val = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether the previous operation is done.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return true if last command is done, otherwise false.
|
||||
*/
|
||||
static inline bool spi_flash_ll_cmd_is_done(const spi_dev_t *dev)
|
||||
{
|
||||
return (dev->cmd.val == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* Erase the flash chip.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_erase_chip(spi_dev_t *dev)
|
||||
{
|
||||
dev->cmd.flash_ce = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Erase the sector, the address should be set by spi_flash_ll_set_address.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_erase_sector(spi_dev_t *dev)
|
||||
{
|
||||
dev->ctrl.val = 0;
|
||||
dev->cmd.flash_se = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Erase the block, the address should be set by spi_flash_ll_set_address.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_erase_block(spi_dev_t *dev)
|
||||
{
|
||||
dev->cmd.flash_be = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable write protection for the flash chip.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param wp true to enable the protection, false to disable (write enable).
|
||||
*/
|
||||
static inline void spi_flash_ll_set_write_protect(spi_dev_t *dev, bool wp)
|
||||
{
|
||||
if (wp) {
|
||||
dev->cmd.flash_wrdi = 1;
|
||||
} else {
|
||||
dev->cmd.flash_wren = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the read data from the buffer after ``spi_flash_ll_read`` is done.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param buffer Buffer to hold the output data
|
||||
* @param read_len Length to get out of the buffer
|
||||
*/
|
||||
static inline void spi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
|
||||
{
|
||||
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
|
||||
// If everything is word-aligned, do a faster memcpy
|
||||
memcpy(buffer, (void *)dev->data_buf, read_len);
|
||||
} else {
|
||||
// Otherwise, slow(er) path copies word by word
|
||||
int copy_len = read_len;
|
||||
for (int i = 0; i < (read_len + 3) / 4; i++) {
|
||||
int word_len = MIN(sizeof(uint32_t), copy_len);
|
||||
uint32_t word = dev->data_buf[i];
|
||||
memcpy(buffer, &word, word_len);
|
||||
buffer = (void *)((intptr_t)buffer + word_len);
|
||||
copy_len -= word_len;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Write a word to the data buffer.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param word Data to write at address 0.
|
||||
*/
|
||||
static inline void spi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
|
||||
{
|
||||
dev->data_buf[0] = word;
|
||||
}
|
||||
|
||||
/**
|
||||
* Program a page of the flash chip. Call ``spi_flash_ll_set_address`` before
|
||||
* this to set the address to program.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param buffer Buffer holding the data to program
|
||||
* @param length Length to program.
|
||||
*/
|
||||
static inline void spi_flash_ll_program_page(spi_dev_t *dev, const void *buffer, uint32_t length)
|
||||
{
|
||||
dev->user.usr_dummy = 0;
|
||||
|
||||
// Load data registers, word at a time
|
||||
int num_words = (length + 3) / 4;
|
||||
for (int i = 0; i < num_words; i++) {
|
||||
uint32_t word = 0;
|
||||
uint32_t word_len = MIN(length, sizeof(word));
|
||||
memcpy(&word, buffer, word_len);
|
||||
dev->data_buf[i] = word;
|
||||
length -= word_len;
|
||||
buffer = (void *)((intptr_t)buffer + word_len);
|
||||
}
|
||||
|
||||
dev->cmd.flash_pp = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases,
|
||||
* should be configured before this is called.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_user_start(spi_dev_t *dev)
|
||||
{
|
||||
dev->cmd.usr = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether the host is idle to perform new commands.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return true if the host is idle, otherwise false
|
||||
*/
|
||||
static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev)
|
||||
{
|
||||
return dev->ext2.st != 0;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Configs
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Select which pin to use for the flash
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
|
||||
{
|
||||
dev->pin.cs0_dis = (pin == 0) ? 0 : 1;
|
||||
dev->pin.cs1_dis = (pin == 1) ? 0 : 1;
|
||||
dev->pin.cs2_dis = (pin == 2) ? 0 : 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the read io mode.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param read_mode I/O mode to use in the following transactions.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
|
||||
{
|
||||
typeof (dev->ctrl) ctrl = dev->ctrl;
|
||||
ctrl.val &= ~(SPI_FREAD_QIO_M | SPI_FREAD_QUAD_M | SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M);
|
||||
ctrl.val |= SPI_FASTRD_MODE_M;
|
||||
switch (read_mode) {
|
||||
case SPI_FLASH_FASTRD:
|
||||
//the default option
|
||||
break;
|
||||
case SPI_FLASH_QIO:
|
||||
ctrl.fread_qio = 1;
|
||||
break;
|
||||
case SPI_FLASH_QOUT:
|
||||
ctrl.fread_quad = 1;
|
||||
break;
|
||||
case SPI_FLASH_DIO:
|
||||
ctrl.fread_dio = 1;
|
||||
break;
|
||||
case SPI_FLASH_DOUT:
|
||||
ctrl.fread_dual = 1;
|
||||
break;
|
||||
case SPI_FLASH_SLOWRD:
|
||||
ctrl.fastrd_mode = 0;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
dev->ctrl = ctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set clock frequency to work at.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param clock_val pointer to the clock value to set
|
||||
*/
|
||||
static inline void spi_flash_ll_set_clock(spi_dev_t *dev, spi_flash_ll_clock_reg_t *clock_val)
|
||||
{
|
||||
dev->clock = *clock_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the input length, in bits.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of input, in bits.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user.usr_miso = bitlen > 0;
|
||||
dev->miso_dlen.usr_miso_dbitlen = bitlen ? (bitlen - 1) : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the output length, in bits (not including command, address and dummy
|
||||
* phases)
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of output, in bits.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user.usr_mosi = bitlen > 0;
|
||||
dev->mosi_dlen.usr_mosi_dbitlen = bitlen ? (bitlen - 1) : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the command with fixed length (8 bits).
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param command Command to send
|
||||
*/
|
||||
static inline void spi_flash_ll_set_command8(spi_dev_t *dev, uint8_t command)
|
||||
{
|
||||
dev->user.usr_command = 1;
|
||||
typeof(dev->user2) user2 = {
|
||||
.usr_command_value = command,
|
||||
.usr_command_bitlen = (8 - 1),
|
||||
};
|
||||
dev->user2 = user2;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write...
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of the address, in bits
|
||||
*/
|
||||
static inline void spi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user1.usr_addr_bitlen = (bitlen - 1);
|
||||
dev->user.usr_addr = bitlen ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param addr Address to send
|
||||
*/
|
||||
static inline void spi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
|
||||
{
|
||||
dev->addr = addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the length of dummy cycles.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param dummy_n Cycles of dummy phases
|
||||
*/
|
||||
static inline void spi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
|
||||
{
|
||||
dev->user.usr_dummy = dummy_n ? 1 : 0;
|
||||
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
|
||||
}
|
||||
151
tools/sdk/include/soc/hal/spi_flash_types.h
Normal file
151
tools/sdk/include/soc/hal/spi_flash_types.h
Normal file
@ -0,0 +1,151 @@
|
||||
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <esp_types.h>
|
||||
#include "hal/esp_flash_err.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Definition of a common transaction. Also holds the return value. */
|
||||
typedef struct {
|
||||
uint8_t command; ///< Command to send, always 8bits
|
||||
uint8_t mosi_len; ///< Output data length, in bits
|
||||
uint8_t miso_len; ///< Input data length, in bits
|
||||
uint32_t mosi_data; ///< Output data to slave
|
||||
uint32_t miso_data[2]; ///< [out] Input data from slave, little endian
|
||||
} spi_flash_trans_t;
|
||||
|
||||
/**
|
||||
* @brief SPI flash clock speed values, always refer to them by the enum rather
|
||||
* than the actual value (more speed may be appended into the list).
|
||||
*
|
||||
* A strategy to select the maximum allowed speed is to enumerate from the
|
||||
* ``ESP_FLSH_SPEED_MAX-1`` or highest frequency supported by your flash, and
|
||||
* decrease the speed until the probing success.
|
||||
*/
|
||||
typedef enum {
|
||||
ESP_FLASH_5MHZ = 0, ///< The flash runs under 5MHz
|
||||
ESP_FLASH_10MHZ, ///< The flash runs under 10MHz
|
||||
ESP_FLASH_20MHZ, ///< The flash runs under 20MHz
|
||||
ESP_FLASH_26MHZ, ///< The flash runs under 26MHz
|
||||
ESP_FLASH_40MHZ, ///< The flash runs under 40MHz
|
||||
ESP_FLASH_80MHZ, ///< The flash runs under 80MHz
|
||||
ESP_FLASH_SPEED_MAX, ///< The maximum frequency supported by the host is ``ESP_FLASH_SPEED_MAX-1``.
|
||||
} esp_flash_speed_t;
|
||||
|
||||
///Lowest speed supported by the driver, currently 5 MHz
|
||||
#define ESP_FLASH_SPEED_MIN ESP_FLASH_5MHZ
|
||||
|
||||
/** @brief Mode used for reading from SPI flash */
|
||||
typedef enum {
|
||||
SPI_FLASH_SLOWRD = 0, ///< Data read using single I/O, some limits on speed
|
||||
SPI_FLASH_FASTRD, ///< Data read using single I/O, no limit on speed
|
||||
SPI_FLASH_DOUT, ///< Data read using dual I/O
|
||||
SPI_FLASH_DIO, ///< Both address & data transferred using dual I/O
|
||||
SPI_FLASH_QOUT, ///< Data read using quad I/O
|
||||
SPI_FLASH_QIO, ///< Both address & data transferred using quad I/O
|
||||
|
||||
SPI_FLASH_READ_MODE_MAX, ///< The fastest io mode supported by the host is ``ESP_FLASH_READ_MODE_MAX-1``.
|
||||
} esp_flash_io_mode_t;
|
||||
|
||||
///Slowest io mode supported by ESP32, currently SlowRd
|
||||
#define SPI_FLASH_READ_MODE_MIN SPI_FLASH_SLOWRD
|
||||
|
||||
struct spi_flash_host_driver_t;
|
||||
typedef struct spi_flash_host_driver_t spi_flash_host_driver_t;
|
||||
|
||||
/** Host driver configuration and context structure. */
|
||||
struct spi_flash_host_driver_t {
|
||||
/**
|
||||
* Configuration and static data used by the specific host driver. The type
|
||||
* is determined by the host driver.
|
||||
*/
|
||||
void *driver_data;
|
||||
/**
|
||||
* Configure the device-related register before transactions. This saves
|
||||
* some time to re-configure those registers when we send continuously
|
||||
*/
|
||||
esp_err_t (*dev_config)(spi_flash_host_driver_t *driver);
|
||||
/**
|
||||
* Send an user-defined spi transaction to the device.
|
||||
*/
|
||||
esp_err_t (*common_command)(spi_flash_host_driver_t *driver, spi_flash_trans_t *t);
|
||||
/**
|
||||
* Read flash ID.
|
||||
*/
|
||||
esp_err_t (*read_id)(spi_flash_host_driver_t *driver, uint32_t *id);
|
||||
/**
|
||||
* Erase whole flash chip.
|
||||
*/
|
||||
void (*erase_chip)(spi_flash_host_driver_t *driver);
|
||||
/**
|
||||
* Erase a specific sector by its start address.
|
||||
*/
|
||||
void (*erase_sector)(spi_flash_host_driver_t *driver, uint32_t start_address);
|
||||
/**
|
||||
* Erase a specific block by its start address.
|
||||
*/
|
||||
void (*erase_block)(spi_flash_host_driver_t *driver, uint32_t start_address);
|
||||
/**
|
||||
* Read the status of the flash chip.
|
||||
*/
|
||||
esp_err_t (*read_status)(spi_flash_host_driver_t *driver, uint8_t *out_sr);
|
||||
/**
|
||||
* Disable write protection.
|
||||
*/
|
||||
esp_err_t (*set_write_protect)(spi_flash_host_driver_t *driver, bool wp);
|
||||
/**
|
||||
* Program a page of the flash. Check ``max_write_bytes`` for the maximum allowed writing length.
|
||||
*/
|
||||
void (*program_page)(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length);
|
||||
/** Check whether need to allocate new buffer to write */
|
||||
bool (*supports_direct_write)(spi_flash_host_driver_t *driver, const void *p);
|
||||
/** Check whether need to allocate new buffer to read */
|
||||
bool (*supports_direct_read)(spi_flash_host_driver_t *driver, const void *p);
|
||||
/** maximum length of program_page */
|
||||
int max_write_bytes;
|
||||
/**
|
||||
* Read data from the flash. Check ``max_read_bytes`` for the maximum allowed reading length.
|
||||
*/
|
||||
esp_err_t (*read)(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len);
|
||||
/** maximum length of read */
|
||||
int max_read_bytes;
|
||||
/**
|
||||
* Check whether the host is idle to perform new operations.
|
||||
*/
|
||||
bool (*host_idle)(spi_flash_host_driver_t *driver);
|
||||
/**
|
||||
* Configure the host to work at different read mode. Responsible to compensate the timing and set IO mode.
|
||||
*/
|
||||
esp_err_t (*configure_host_io_mode)(spi_flash_host_driver_t *driver, uint32_t command,
|
||||
uint32_t addr_bitlen, int dummy_bitlen_base,
|
||||
esp_flash_io_mode_t io_mode);
|
||||
/**
|
||||
* Internal use, poll the HW until the last operation is done.
|
||||
*/
|
||||
void (*poll_cmd_done)(spi_flash_host_driver_t *driver);
|
||||
/**
|
||||
* For some host (SPI1), they are shared with a cache. When the data is
|
||||
* modified, the cache needs to be flushed. Left NULL if not supported.
|
||||
*/
|
||||
esp_err_t (*flush_cache)(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size);
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
222
tools/sdk/include/soc/hal/spi_hal.h
Normal file
222
tools/sdk/include/soc/hal/spi_hal.h
Normal file
@ -0,0 +1,222 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The hal is not public api, don't use in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The HAL layer for SPI master (common part)
|
||||
|
||||
// SPI HAL usages:
|
||||
// 1. initialize the bus
|
||||
// 2. initialize the DMA descriptors if DMA used
|
||||
// 3. setup the clock speed (since this takes long time)
|
||||
// 4. call setup_device to update parameters for the specific device
|
||||
// 5. call setup_trans to update parameters for the specific transaction
|
||||
// 6. prepare data to send, and prepare the receiving buffer
|
||||
// 7. trigger user defined SPI transaction to start
|
||||
// 8. wait until the user transaction is done
|
||||
// 9. fetch the received data
|
||||
// Parameter to be updated only during ``setup_device`` will be highlighted in the
|
||||
// field comments.
|
||||
|
||||
#pragma once
|
||||
#include "hal/spi_ll.h"
|
||||
#include <esp_err.h>
|
||||
#include "soc/lldesc.h"
|
||||
|
||||
/**
|
||||
* Timing configuration structure that should be calculated by
|
||||
* ``spi_hal_setup_clock`` at initialization and hold. Filled into the
|
||||
* ``timing_conf`` member of the context of HAL before setup a device.
|
||||
*/
|
||||
typedef struct {
|
||||
spi_ll_clock_val_t clock_reg; ///< Register value used by the LL layer
|
||||
int timing_dummy; ///< Extra dummy needed to compensate the timing
|
||||
int timing_miso_delay; ///< Extra miso delay clocks to compensate the timing
|
||||
} spi_hal_timing_conf_t;
|
||||
|
||||
/**
|
||||
* Context that should be maintained by both the driver and the HAL.
|
||||
*/
|
||||
typedef struct {
|
||||
/* configured by driver at initialization, don't touch */
|
||||
spi_dev_t *hw; ///< Beginning address of the peripheral registers.
|
||||
/* should be configured by driver at initialization */
|
||||
lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use.
|
||||
/*
|
||||
* Device specific, all these parameters will be updated to the peripheral
|
||||
* only when ``spi_hal_setup_device``. They may not get updated when
|
||||
* ``spi_hal_setup_trans``.
|
||||
*/
|
||||
int mode; ///< SPI mode, device specific
|
||||
int cs_setup; ///< Setup time of CS active edge before the first SPI clock, device specific
|
||||
int cs_hold; ///< Hold time of CS inactive edge after the last SPI clock, device specific
|
||||
int cs_pin_id; ///< CS pin to use, 0-2, otherwise all the CS pins are not used. Device specific
|
||||
spi_hal_timing_conf_t *timing_conf; /**< Pointer to an structure holding
|
||||
* the pre-calculated timing configuration for the device at initialization,
|
||||
* device specific
|
||||
*/
|
||||
struct {
|
||||
uint32_t sio : 1; ///< Whether to use SIO mode, device specific
|
||||
uint32_t half_duplex : 1; ///< Whether half duplex mode is used, device specific
|
||||
uint32_t tx_lsbfirst : 1; ///< Whether LSB is sent first for TX data, device specific
|
||||
uint32_t rx_lsbfirst : 1; ///< Whether LSB is received first for RX data, device specific
|
||||
uint32_t dma_enabled : 1; ///< Whether the DMA is enabled, do not update after initialization
|
||||
uint32_t no_compensate : 1; ///< No need to add dummy to compensate the timing, device specific
|
||||
#ifdef SOC_SPI_SUPPORT_AS_CS
|
||||
uint32_t as_cs : 1; ///< Whether to toggle the CS while the clock toggles, device specific
|
||||
#endif
|
||||
uint32_t positive_cs : 1; ///< Whether the postive CS feature is abled, device specific
|
||||
};//boolean configurations
|
||||
|
||||
/*
|
||||
* Transaction specific (data), all these parameters will be updated to the
|
||||
* peripheral every transaction.
|
||||
*/
|
||||
uint16_t cmd; ///< Command value to be sent
|
||||
int cmd_bits; ///< Length (in bits) of the command phase
|
||||
int addr_bits; ///< Length (in bits) of the address phase
|
||||
int dummy_bits; ///< Base length (in bits) of the dummy phase. Note when the compensation is enabled, some extra dummy bits may be appended.
|
||||
int tx_bitlen; ///< TX length, in bits
|
||||
int rx_bitlen; ///< RX length, in bits
|
||||
uint64_t addr; ///< Address value to be sent
|
||||
uint8_t *send_buffer; ///< Data to be sent
|
||||
uint8_t *rcv_buffer; ///< Buffer to hold the receive data.
|
||||
spi_ll_io_mode_t io_mode; ///< IO mode of the master
|
||||
|
||||
} spi_hal_context_t;
|
||||
|
||||
/**
|
||||
* Init the peripheral and the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
|
||||
*/
|
||||
void spi_hal_init(spi_hal_context_t *hal, int host_id);
|
||||
|
||||
/**
|
||||
* Deinit the peripheral (and the context if needed).
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_deinit(spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Setup device-related configurations according to the settings in the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_setup_device(const spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Setup transaction related configurations according to the settings in the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_setup_trans(const spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Prepare the data for the current transaction.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_prepare_data(const spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Trigger start a user-defined transaction.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_user_start(const spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Check whether the transaction is done (trans_done is set).
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
bool spi_hal_usr_is_done(const spi_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Post transaction operations, mainly fetch data from the buffer.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_hal_fetch_result(const spi_hal_context_t *hal);
|
||||
|
||||
/*----------------------------------------------------------
|
||||
* Utils
|
||||
* ---------------------------------------------------------*/
|
||||
/**
|
||||
* Get the configuration of clock and timing. The configuration will be used when ``spi_hal_setup_device``.
|
||||
*
|
||||
* It is highly suggested to do this at initialization, since it takes long time.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
* @param speed_hz Desired frequency.
|
||||
* @param duty_cycle Desired duty cycle of SPI clock
|
||||
* @param use_gpio true if the GPIO matrix is used, otherwise false
|
||||
* @param input_delay_ns Maximum delay between SPI launch clock and the data to
|
||||
* be valid. This is used to compensate/calculate the maximum frequency
|
||||
* allowed. Left 0 if not known.
|
||||
* @param out_freq Output of the actual frequency, left NULL if not required.
|
||||
* @param timing_conf Output of the timing configuration.
|
||||
*
|
||||
* @return ESP_OK if desired is available, otherwise fail.
|
||||
*/
|
||||
esp_err_t spi_hal_get_clock_conf(const spi_hal_context_t *hal, int speed_hz, int duty_cycle, bool use_gpio, int input_delay_ns, int *out_freq, spi_hal_timing_conf_t *timing_conf);
|
||||
|
||||
/**
|
||||
* Get the frequency actual used.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
* @param fapb APB clock frequency.
|
||||
* @param hz Desired frequencyc.
|
||||
* @param duty_cycle Desired duty cycle.
|
||||
*/
|
||||
int spi_hal_master_cal_clock(int fapb, int hz, int duty_cycle);
|
||||
|
||||
/**
|
||||
* Get the timing configuration for given parameters.
|
||||
*
|
||||
* @param eff_clk Actual SPI clock frequency
|
||||
* @param gpio_is_used true if the GPIO matrix is used, otherwise false.
|
||||
* @param input_delay_ns Maximum delay between SPI launch clock and the data to
|
||||
* be valid. This is used to compensate/calculate the maximum frequency
|
||||
* allowed. Left 0 if not known.
|
||||
* @param dummy_n Dummy cycles required to correctly read the data.
|
||||
* @param miso_delay_n suggested delay on the MISO line, in APB clocks.
|
||||
*/
|
||||
void spi_hal_cal_timing(int eff_clk, bool gpio_is_used, int input_delay_ns, int *dummy_n, int *miso_delay_n);
|
||||
|
||||
/**
|
||||
* Get the maximum frequency allowed to read if no compensation is used.
|
||||
*
|
||||
* @param gpio_is_used true if the GPIO matrix is used, otherwise false.
|
||||
* @param input_delay_ns Maximum delay between SPI launch clock and the data to
|
||||
* be valid. This is used to compensate/calculate the maximum frequency
|
||||
* allowed. Left 0 if not known.
|
||||
*/
|
||||
int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns);
|
||||
|
||||
864
tools/sdk/include/soc/hal/spi_ll.h
Normal file
864
tools/sdk/include/soc/hal/spi_ll.h
Normal file
@ -0,0 +1,864 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The hal is not public api, don't use in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The LL layer for ESP32 SPI register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/hal_defs.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include "esp32/rom/lldesc.h"
|
||||
#include <string.h>
|
||||
#include <esp_types.h>
|
||||
#include <stdlib.h> //for abs()
|
||||
|
||||
/// Registers to reset during initialization. Don't use in app.
|
||||
#define SPI_LL_RST_MASK (SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST)
|
||||
/// Interrupt not used. Don't use in app.
|
||||
#define SPI_LL_UNUSED_INT_MASK (SPI_INT_EN | SPI_SLV_WR_STA_DONE | SPI_SLV_RD_STA_DONE | SPI_SLV_WR_BUF_DONE | SPI_SLV_RD_BUF_DONE)
|
||||
/// Swap the bit order to its correct place to send
|
||||
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
|
||||
|
||||
/**
|
||||
* The data structure holding calculated clock configuration. Since the
|
||||
* calculation needs long time, it should be calculated during initialization and
|
||||
* stored somewhere to be quickly used.
|
||||
*/
|
||||
typedef uint32_t spi_ll_clock_val_t;
|
||||
|
||||
/** IO modes supported by the master. */
|
||||
typedef enum {
|
||||
SPI_LL_IO_MODE_NORMAL = 0, ///< 1-bit mode for all phases
|
||||
SPI_LL_IO_MODE_DIO, ///< 2-bit mode for address and data phases, 1-bit mode for command phase
|
||||
SPI_LL_IO_MODE_DUAL, ///< 2-bit mode for data phases only, 1-bit mode for command and address phases
|
||||
SPI_LL_IO_MODE_QIO, ///< 4-bit mode for address and data phases, 1-bit mode for command phase
|
||||
SPI_LL_IO_MODE_QUAD, ///< 4-bit mode for data phases only, 1-bit mode for command and address phases
|
||||
} spi_ll_io_mode_t;
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Control
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Initialize SPI peripheral (master).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_master_init(spi_dev_t *hw)
|
||||
{
|
||||
//Reset DMA
|
||||
hw->dma_conf.val |= SPI_LL_RST_MASK;
|
||||
hw->dma_out_link.start = 0;
|
||||
hw->dma_in_link.start = 0;
|
||||
hw->dma_conf.val &= ~SPI_LL_RST_MASK;
|
||||
//Reset timing
|
||||
hw->ctrl2.val = 0;
|
||||
|
||||
//use all 64 bytes of the buffer
|
||||
hw->user.usr_miso_highpart = 0;
|
||||
hw->user.usr_mosi_highpart = 0;
|
||||
|
||||
//Disable unneeded ints
|
||||
hw->slave.val &= ~SPI_LL_UNUSED_INT_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize SPI peripheral (slave).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_slave_init(spi_dev_t *hw)
|
||||
{
|
||||
//Configure slave
|
||||
hw->clock.val = 0;
|
||||
hw->user.val = 0;
|
||||
hw->ctrl.val = 0;
|
||||
hw->slave.wr_rd_buf_en = 1; //no sure if needed
|
||||
hw->user.doutdin = 1; //we only support full duplex
|
||||
hw->user.sio = 0;
|
||||
hw->slave.slave_mode = 1;
|
||||
hw->dma_conf.val |= SPI_LL_RST_MASK;
|
||||
hw->dma_out_link.start = 0;
|
||||
hw->dma_in_link.start = 0;
|
||||
hw->dma_conf.val &= ~SPI_LL_RST_MASK;
|
||||
hw->slave.sync_reset = 1;
|
||||
hw->slave.sync_reset = 0;
|
||||
//use all 64 bytes of the buffer
|
||||
hw->user.usr_miso_highpart = 0;
|
||||
hw->user.usr_mosi_highpart = 0;
|
||||
|
||||
//Disable unneeded ints
|
||||
hw->slave.val &= ~SPI_LL_UNUSED_INT_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Reset TX and RX DMAs.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_reset_dma(spi_dev_t *hw)
|
||||
{
|
||||
//Reset DMA peripheral
|
||||
hw->dma_conf.val |= SPI_LL_RST_MASK;
|
||||
hw->dma_out_link.start = 0;
|
||||
hw->dma_in_link.start = 0;
|
||||
hw->dma_conf.val &= ~SPI_LL_RST_MASK;
|
||||
hw->dma_conf.out_data_burst_en = 1;
|
||||
hw->dma_conf.indscr_burst_en = 1;
|
||||
hw->dma_conf.outdscr_burst_en = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Start RX DMA.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param addr Address of the beginning DMA descriptor.
|
||||
*/
|
||||
static inline void spi_ll_rxdma_start(spi_dev_t *hw, lldesc_t *addr)
|
||||
{
|
||||
hw->dma_in_link.addr = (int) addr & 0xFFFFF;
|
||||
hw->dma_in_link.start = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Start TX DMA.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param addr Address of the beginning DMA descriptor.
|
||||
*/
|
||||
static inline void spi_ll_txdma_start(spi_dev_t *hw, lldesc_t *addr)
|
||||
{
|
||||
hw->dma_out_link.addr = (int) addr & 0xFFFFF;
|
||||
hw->dma_out_link.start = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to SPI buffer.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param buffer_to_send Data address to copy to the buffer.
|
||||
* @param bitlen Length to copy, in bits.
|
||||
*/
|
||||
static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen)
|
||||
{
|
||||
for (int x = 0; x < bitlen; x += 32) {
|
||||
//Use memcpy to get around alignment issues for txdata
|
||||
uint32_t word;
|
||||
memcpy(&word, &buffer_to_send[x / 8], 4);
|
||||
hw->data_buf[(x / 32)] = word;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Read from SPI buffer.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param buffer_to_rcv Address to copy buffer data to.
|
||||
* @param bitlen Length to copy, in bits.
|
||||
*/
|
||||
static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen)
|
||||
{
|
||||
for (int x = 0; x < bitlen; x += 32) {
|
||||
//Do a memcpy to get around possible alignment issues in rx_buffer
|
||||
uint32_t word = hw->data_buf[x / 32];
|
||||
int len = bitlen - x;
|
||||
if (len > 32) {
|
||||
len = 32;
|
||||
}
|
||||
memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether user-defined transaction is done.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return true if transaction is done, otherwise false.
|
||||
*/
|
||||
static inline bool spi_ll_usr_is_done(spi_dev_t *hw)
|
||||
{
|
||||
return hw->slave.trans_done;
|
||||
}
|
||||
|
||||
/**
|
||||
* Trigger start of user-defined transaction.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_user_start(spi_dev_t *hw)
|
||||
{
|
||||
hw->cmd.usr = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get current running command bit-mask. (Preview)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command.
|
||||
*/
|
||||
static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw)
|
||||
{
|
||||
return hw->cmd.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the trans_done interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_disable_int(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.trans_inten = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Clear the trans_done interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.trans_done = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the trans_done interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_set_int_stat(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.trans_done = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the trans_done interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_enable_int(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.trans_inten = 1;
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Configs: mode
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Enable/disable the postive-cs feature.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param cs One of the CS (0-2) to enable/disable the feature.
|
||||
* @param pos_cs true to enable the feature, otherwise disable (default).
|
||||
*/
|
||||
static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_cs)
|
||||
{
|
||||
if (pos_cs) {
|
||||
hw->pin.master_cs_pol |= (1 << cs);
|
||||
} else {
|
||||
hw->pin.master_cs_pol &= (1 << cs);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable the LSBFIRST feature for TX data.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param lsbfirst true if LSB of TX data to be sent first, otherwise MSB is sent first (default).
|
||||
*/
|
||||
static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst)
|
||||
{
|
||||
hw->ctrl.wr_bit_order = lsbfirst;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable the LSBFIRST feature for RX data.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param lsbfirst true if first bit received as LSB, otherwise as MSB (default).
|
||||
*/
|
||||
static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst)
|
||||
{
|
||||
hw->ctrl.rd_bit_order = lsbfirst;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set SPI mode for the peripheral as master.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode SPI mode to work at, 0-3.
|
||||
*/
|
||||
static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode)
|
||||
{
|
||||
//Configure polarity
|
||||
if (mode == 0) {
|
||||
hw->pin.ck_idle_edge = 0;
|
||||
hw->user.ck_out_edge = 0;
|
||||
} else if (mode == 1) {
|
||||
hw->pin.ck_idle_edge = 0;
|
||||
hw->user.ck_out_edge = 1;
|
||||
} else if (mode == 2) {
|
||||
hw->pin.ck_idle_edge = 1;
|
||||
hw->user.ck_out_edge = 1;
|
||||
} else if (mode == 3) {
|
||||
hw->pin.ck_idle_edge = 1;
|
||||
hw->user.ck_out_edge = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set SPI mode for the peripheral as slave.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode SPI mode to work at, 0-3.
|
||||
*/
|
||||
static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma_used)
|
||||
{
|
||||
if (mode == 0) {
|
||||
//The timing needs to be fixed to meet the requirements of DMA
|
||||
hw->pin.ck_idle_edge = 1;
|
||||
hw->user.ck_i_edge = 0;
|
||||
hw->ctrl2.miso_delay_mode = 0;
|
||||
hw->ctrl2.miso_delay_num = 0;
|
||||
hw->ctrl2.mosi_delay_mode = 2;
|
||||
hw->ctrl2.mosi_delay_num = 2;
|
||||
} else if (mode == 1) {
|
||||
hw->pin.ck_idle_edge = 1;
|
||||
hw->user.ck_i_edge = 1;
|
||||
hw->ctrl2.miso_delay_mode = 2;
|
||||
hw->ctrl2.miso_delay_num = 0;
|
||||
hw->ctrl2.mosi_delay_mode = 0;
|
||||
hw->ctrl2.mosi_delay_num = 0;
|
||||
} else if (mode == 2) {
|
||||
//The timing needs to be fixed to meet the requirements of DMA
|
||||
hw->pin.ck_idle_edge = 0;
|
||||
hw->user.ck_i_edge = 1;
|
||||
hw->ctrl2.miso_delay_mode = 0;
|
||||
hw->ctrl2.miso_delay_num = 0;
|
||||
hw->ctrl2.mosi_delay_mode = 1;
|
||||
hw->ctrl2.mosi_delay_num = 2;
|
||||
} else if (mode == 3) {
|
||||
hw->pin.ck_idle_edge = 0;
|
||||
hw->user.ck_i_edge = 0;
|
||||
hw->ctrl2.miso_delay_mode = 1;
|
||||
hw->ctrl2.miso_delay_num = 0;
|
||||
hw->ctrl2.mosi_delay_mode = 0;
|
||||
hw->ctrl2.mosi_delay_num = 0;
|
||||
}
|
||||
|
||||
/* Silicon issues exists in mode 0 and 2 with DMA, change clock phase to
|
||||
* avoid dma issue. This will cause slave output to appear at most half a
|
||||
* spi clock before
|
||||
*/
|
||||
if (dma_used) {
|
||||
if (mode == 0) {
|
||||
hw->pin.ck_idle_edge = 0;
|
||||
hw->user.ck_i_edge = 1;
|
||||
hw->ctrl2.miso_delay_mode = 0;
|
||||
hw->ctrl2.miso_delay_num = 2;
|
||||
hw->ctrl2.mosi_delay_mode = 0;
|
||||
hw->ctrl2.mosi_delay_num = 3;
|
||||
} else if (mode == 2) {
|
||||
hw->pin.ck_idle_edge = 1;
|
||||
hw->user.ck_i_edge = 0;
|
||||
hw->ctrl2.miso_delay_mode = 0;
|
||||
hw->ctrl2.miso_delay_num = 2;
|
||||
hw->ctrl2.mosi_delay_mode = 0;
|
||||
hw->ctrl2.mosi_delay_num = 3;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set SPI to work in full duplex or half duplex mode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param half_duplex true to work in half duplex mode, otherwise in full duplex mode.
|
||||
*/
|
||||
static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex)
|
||||
{
|
||||
hw->user.doutdin = !half_duplex;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set SPI to work in SIO mode or not.
|
||||
*
|
||||
* SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param sio_mode true to work in SIO mode, otherwise false.
|
||||
*/
|
||||
static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode)
|
||||
{
|
||||
hw->user.sio = sio_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* Configure the io mode for the master to work at.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param io_mode IO mode to work at, see ``spi_ll_io_mode_t``.
|
||||
*/
|
||||
static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_mode)
|
||||
{
|
||||
hw->ctrl.val &= ~(SPI_FREAD_DUAL | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_QIO);
|
||||
hw->user.val &= ~(SPI_FWRITE_DUAL | SPI_FWRITE_QUAD | SPI_FWRITE_DIO | SPI_FWRITE_QIO);
|
||||
switch (io_mode) {
|
||||
case SPI_LL_IO_MODE_DIO:
|
||||
hw->ctrl.fread_dio = 1;
|
||||
hw->user.fwrite_dio = 1;
|
||||
break;
|
||||
case SPI_LL_IO_MODE_DUAL:
|
||||
hw->ctrl.fread_dual = 1;
|
||||
hw->user.fwrite_dual = 1;
|
||||
break;
|
||||
case SPI_LL_IO_MODE_QIO:
|
||||
hw->ctrl.fread_qio = 1;
|
||||
hw->user.fwrite_qio = 1;
|
||||
break;
|
||||
case SPI_LL_IO_MODE_QUAD:
|
||||
hw->ctrl.fread_quad = 1;
|
||||
hw->user.fwrite_quad = 1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
};
|
||||
if (io_mode != SPI_LL_IO_MODE_NORMAL) {
|
||||
hw->ctrl.fastrd_mode = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Select one of the CS to use in current transaction.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param cs_id The cs to use, 0-2, otherwise none of them is used.
|
||||
*/
|
||||
static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id)
|
||||
{
|
||||
hw->pin.cs0_dis = (cs_id == 0) ? 0 : 1;
|
||||
hw->pin.cs1_dis = (cs_id == 1) ? 0 : 1;
|
||||
hw->pin.cs2_dis = (cs_id == 2) ? 0 : 1;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Configs: parameters
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Set the clock for master by stored value.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param val stored clock configuration calculated before (by ``spi_ll_cal_clock``).
|
||||
*/
|
||||
static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, spi_ll_clock_val_t *val)
|
||||
{
|
||||
hw->clock.val = *(uint32_t *)val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the frequency of given dividers. Don't use in app.
|
||||
*
|
||||
* @param fapb APB clock of the system.
|
||||
* @param pre Pre devider.
|
||||
* @param n main divider.
|
||||
*
|
||||
* @return Frequency of given dividers.
|
||||
*/
|
||||
static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n)
|
||||
{
|
||||
return (fapb / (pre * n));
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate the nearest frequency avaliable for master.
|
||||
*
|
||||
* @param fapb APB clock of the system.
|
||||
* @param hz Frequncy desired.
|
||||
* @param duty_cycle Duty cycle desired.
|
||||
* @param out_reg Output address to store the calculated clock configurations for the return frequency.
|
||||
*
|
||||
* @return Actual (nearest) frequency.
|
||||
*/
|
||||
static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg)
|
||||
{
|
||||
typeof(SPI1.clock) reg;
|
||||
int eff_clk;
|
||||
|
||||
//In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value.
|
||||
if (hz > ((fapb / 4) * 3)) {
|
||||
//Using Fapb directly will give us the best result here.
|
||||
reg.clkcnt_l = 0;
|
||||
reg.clkcnt_h = 0;
|
||||
reg.clkcnt_n = 0;
|
||||
reg.clkdiv_pre = 0;
|
||||
reg.clk_equ_sysclk = 1;
|
||||
eff_clk = fapb;
|
||||
} else {
|
||||
//For best duty cycle resolution, we want n to be as close to 32 as possible, but
|
||||
//we also need a pre/n combo that gets us as close as possible to the intended freq.
|
||||
//To do this, we bruteforce n and calculate the best pre to go along with that.
|
||||
//If there's a choice between pre/n combos that give the same result, use the one
|
||||
//with the higher n.
|
||||
int pre, n, h, l;
|
||||
int bestn = -1;
|
||||
int bestpre = -1;
|
||||
int besterr = 0;
|
||||
int errval;
|
||||
for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse.
|
||||
//Effectively, this does pre=round((fapb/n)/hz).
|
||||
pre = ((fapb / n) + (hz / 2)) / hz;
|
||||
if (pre <= 0) {
|
||||
pre = 1;
|
||||
}
|
||||
if (pre > 8192) {
|
||||
pre = 8192;
|
||||
}
|
||||
errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz);
|
||||
if (bestn == -1 || errval <= besterr) {
|
||||
besterr = errval;
|
||||
bestn = n;
|
||||
bestpre = pre;
|
||||
}
|
||||
}
|
||||
|
||||
n = bestn;
|
||||
pre = bestpre;
|
||||
l = n;
|
||||
//This effectively does round((duty_cycle*n)/256)
|
||||
h = (duty_cycle * n + 127) / 256;
|
||||
if (h <= 0) {
|
||||
h = 1;
|
||||
}
|
||||
|
||||
reg.clk_equ_sysclk = 0;
|
||||
reg.clkcnt_n = n - 1;
|
||||
reg.clkdiv_pre = pre - 1;
|
||||
reg.clkcnt_h = h - 1;
|
||||
reg.clkcnt_l = l - 1;
|
||||
eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n);
|
||||
}
|
||||
if (out_reg != NULL) {
|
||||
*(uint32_t *)out_reg = reg.val;
|
||||
}
|
||||
return eff_clk;
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate and set clock for SPI master according to desired parameters.
|
||||
*
|
||||
* This takes long, suggest to calculate the configuration during
|
||||
* initialization by ``spi_ll_master_cal_clock`` and store the result, then
|
||||
* configure the clock by stored value when used by
|
||||
* ``spi_ll_msater_set_clock_by_reg``.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param fapb APB clock of the system.
|
||||
* @param hz Frequncy desired.
|
||||
* @param duty_cycle Duty cycle desired.
|
||||
*
|
||||
* @return Actual frequency that is used.
|
||||
*/
|
||||
static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle)
|
||||
{
|
||||
spi_ll_clock_val_t reg_val;
|
||||
int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val);
|
||||
spi_ll_master_set_clock_by_reg(hw, ®_val);
|
||||
return freq;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable the CK sel feature for a CS pin.
|
||||
*
|
||||
* CK sel is a feature to toggle the CS line along with the clock.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param cs CS pin to enable/disable the feature, 0-2.
|
||||
* @param cksel true to enable the feature, otherwise false.
|
||||
*/
|
||||
static inline void spi_ll_master_set_cksel(spi_dev_t *hw, int cs, uint32_t cksel)
|
||||
{
|
||||
if (cksel) {
|
||||
hw->pin.master_ck_sel |= (1 << cs);
|
||||
} else {
|
||||
hw->pin.master_ck_sel &= (1 << cs);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the mosi delay after the output edge to the signal. (Preview)
|
||||
*
|
||||
* The delay mode/num is a Espressif conception, may change in the new chips.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param delay_mode Delay mode, see TRM.
|
||||
* @param delay_num APB clocks to delay.
|
||||
*/
|
||||
static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int delay_num)
|
||||
{
|
||||
hw->ctrl2.mosi_delay_mode = delay_mode;
|
||||
hw->ctrl2.mosi_delay_num = delay_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the miso delay applied to the input signal before the internal peripheral. (Preview)
|
||||
*
|
||||
* The delay mode/num is a Espressif conception, may change in the new chips.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param delay_mode Delay mode, see TRM.
|
||||
* @param delay_num APB clocks to delay.
|
||||
*/
|
||||
static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int delay_num)
|
||||
{
|
||||
hw->ctrl2.miso_delay_mode = delay_mode;
|
||||
hw->ctrl2.miso_delay_num = delay_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set dummy clocks to output before RX phase (master), or clocks to skip
|
||||
* before the data phase and after the address phase (slave).
|
||||
*
|
||||
* Note this phase is also used to compensate RX timing in half duplex mode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param dummy_n Dummy cycles used. 0 to disable the dummy phase.
|
||||
*/
|
||||
static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
|
||||
{
|
||||
hw->user.usr_dummy = dummy_n ? 1 : 0;
|
||||
hw->user1.usr_dummy_cyclelen = dummy_n - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the delay of SPI clocks before the CS inactive edge after the last SPI clock.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param hold Delay of SPI clocks after the last clock, 0 to disable the hold phase.
|
||||
*/
|
||||
static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold)
|
||||
{
|
||||
hw->ctrl2.hold_time = hold;
|
||||
hw->user.cs_hold = hold ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the delay of SPI clocks before the first SPI clock after the CS active edge.
|
||||
*
|
||||
* Note ESP32 doesn't support to use this feature when command/address phases
|
||||
* are used in full duplex mode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param setup Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
|
||||
*/
|
||||
static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup)
|
||||
{
|
||||
hw->ctrl2.setup_time = setup - 1;
|
||||
hw->user.cs_setup = setup ? 1 : 0;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Configs: data
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Set the input length (master).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen input length, in bits.
|
||||
*/
|
||||
static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen)
|
||||
{
|
||||
hw->miso_dlen.usr_miso_dbitlen = bitlen - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the output length (master).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen output length, in bits.
|
||||
*/
|
||||
static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen)
|
||||
{
|
||||
hw->mosi_dlen.usr_mosi_dbitlen = bitlen - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the maximum input length (slave).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen input length, in bits.
|
||||
*/
|
||||
static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
|
||||
{
|
||||
hw->slv_wrbuf_dlen.bit_len = bitlen - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the maximum output length (slave).
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen output length, in bits.
|
||||
*/
|
||||
static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen)
|
||||
{
|
||||
hw->slv_rdbuf_dlen.bit_len = bitlen - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the length of command phase.
|
||||
*
|
||||
* When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit
|
||||
* command phases takes 4 cycles in 4-bit mode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of command phase, in bits. 0 to disable the command phase.
|
||||
*/
|
||||
static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen)
|
||||
{
|
||||
hw->user2.usr_command_bitlen = bitlen - 1;
|
||||
hw->user.usr_command = bitlen ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the length of address phase.
|
||||
*
|
||||
* When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit
|
||||
* address phases takes 4 cycles in 4-bit mode.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of address phase, in bits. 0 to disable the address phase.
|
||||
*/
|
||||
static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen)
|
||||
{
|
||||
hw->user1.usr_addr_bitlen = bitlen - 1;
|
||||
hw->user.usr_addr = bitlen ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the address value in an intuitive way.
|
||||
*
|
||||
* The length and lsbfirst is required to shift and swap the address to the right place.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param address Address to set
|
||||
* @param addrlen Length of the address phase
|
||||
* @param lsbfirst whether the LSB first feature is enabled.
|
||||
*/
|
||||
static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, uint32_t lsbfirst)
|
||||
{
|
||||
if (lsbfirst) {
|
||||
/* The output address start from the LSB of the highest byte, i.e.
|
||||
* addr[24] -> addr[31]
|
||||
* ...
|
||||
* addr[0] -> addr[7]
|
||||
* slv_wr_status[24] -> slv_wr_status[31]
|
||||
* ...
|
||||
* slv_wr_status[0] -> slv_wr_status[7]
|
||||
* So swap the byte order to let the LSB sent first.
|
||||
*/
|
||||
addr = HAL_SWAP64(addr);
|
||||
hw->addr = addr >> 32;
|
||||
hw->slv_wr_status = addr;
|
||||
} else {
|
||||
// shift the address to MSB of addr (and maybe slv_wr_status) register.
|
||||
// output address will be sent from MSB to LSB of addr register, then comes the MSB to LSB of slv_wr_status register.
|
||||
if (addrlen > 32) {
|
||||
hw->addr = addr >> (addrlen - 32);
|
||||
hw->slv_wr_status = addr << (64 - addrlen);
|
||||
} else {
|
||||
hw->addr = addr << (32 - addrlen);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the command value in an intuitive way.
|
||||
*
|
||||
* The length and lsbfirst is required to shift and swap the command to the right place.
|
||||
*
|
||||
* @param hw Beginning command of the peripheral registers.
|
||||
* @param command Command to set
|
||||
* @param addrlen Length of the command phase
|
||||
* @param lsbfirst whether the LSB first feature is enabled.
|
||||
*/
|
||||
static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst)
|
||||
{
|
||||
if (lsbfirst) {
|
||||
// The output command start from bit0 to bit 15, kept as is.
|
||||
hw->user2.usr_command_value = cmd;
|
||||
} else {
|
||||
/* Output command will be sent from bit 7 to 0 of command_value, and
|
||||
* then bit 15 to 8 of the same register field. Shift and swap to send
|
||||
* more straightly.
|
||||
*/
|
||||
hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable the RX data phase.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param enable true if RX phase exist, otherwise false.
|
||||
*/
|
||||
static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable)
|
||||
{
|
||||
hw->user.usr_miso = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable the TX data phase.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param enable true if TX phase exist, otherwise false.
|
||||
*/
|
||||
static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable)
|
||||
{
|
||||
hw->user.usr_mosi = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* Reset the slave peripheral before next transaction.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_slave_reset(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.sync_reset = 1;
|
||||
hw->slave.sync_reset = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the received bit length of the slave.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return Received bits of the slave.
|
||||
*/
|
||||
static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
|
||||
{
|
||||
return hw->slv_rd_bit.slv_rdata_bit;
|
||||
}
|
||||
|
||||
|
||||
#undef SPI_LL_RST_MASK
|
||||
#undef SPI_LL_UNUSED_INT_MASK
|
||||
152
tools/sdk/include/soc/hal/spi_slave_hal.h
Normal file
152
tools/sdk/include/soc/hal/spi_slave_hal.h
Normal file
@ -0,0 +1,152 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The hal is not public api, don't use in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The HAL layer for SPI slave (common part)
|
||||
|
||||
// SPI slave HAL usages:
|
||||
// 1. initialize the bus
|
||||
// 2. initialize the DMA descriptors if DMA used
|
||||
// 3. call setup_device to update parameters for the device
|
||||
// 4. prepare data to send, and prepare the receiving buffer
|
||||
// 5. trigger user defined SPI transaction to start
|
||||
// 6. wait until the user transaction is done
|
||||
// 7. store the received data and get the length
|
||||
// 8. check and reset the DMA (if needed) before the next transaction
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/lldesc.h"
|
||||
#include "soc/spi_struct.h"
|
||||
#include <esp_types.h>
|
||||
#include "soc/spi_caps.h"
|
||||
|
||||
/**
|
||||
* Context that should be maintained by both the driver and the HAL.
|
||||
*/
|
||||
typedef struct {
|
||||
/* configured by driver at initialization, don't touch */
|
||||
spi_dev_t *hw; ///< Beginning address of the peripheral registers.
|
||||
/* should be configured by driver at initialization */
|
||||
lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the TX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the RX DMA.
|
||||
* The amount should be larger than dmadesc_n. The driver should ensure that
|
||||
* the data to be sent is shorter than the descriptors can hold.
|
||||
*/
|
||||
int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use.
|
||||
|
||||
/*
|
||||
* configurations to be filled after ``spi_slave_hal_init``. Updated to
|
||||
* peripheral registers when ``spi_slave_hal_setup_device`` is called.
|
||||
*/
|
||||
struct {
|
||||
uint32_t rx_lsbfirst : 1;
|
||||
uint32_t tx_lsbfirst : 1;
|
||||
uint32_t use_dma : 1;
|
||||
};
|
||||
int mode;
|
||||
|
||||
/*
|
||||
* Transaction specific (data), all these parameters will be updated to the
|
||||
* peripheral every transaction.
|
||||
*/
|
||||
uint32_t bitlen; ///< Expected maximum length of the transaction, in bits.
|
||||
const void *tx_buffer; ///< Data to be sent
|
||||
void *rx_buffer; ///< Buffer to hold the received data.
|
||||
|
||||
/* Other transaction result after one transaction */
|
||||
uint32_t rcv_bitlen; ///< Length of the last transaction, in bits.
|
||||
} spi_slave_hal_context_t;
|
||||
|
||||
/**
|
||||
* Init the peripheral and the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
|
||||
*/
|
||||
void spi_slave_hal_init(spi_slave_hal_context_t *hal, int host_id);
|
||||
|
||||
/**
|
||||
* Deinit the peripheral (and the context if needed).
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_slave_hal_deinit(spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Setup device-related configurations according to the settings in the context.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_slave_hal_setup_device(const spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Prepare the data for the current transaction.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_slave_hal_prepare_data(const spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Trigger start a user-defined transaction.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_slave_hal_user_start(const spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Check whether the transaction is done (trans_done is set).
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
bool spi_slave_hal_usr_is_done(spi_slave_hal_context_t* hal);
|
||||
|
||||
/**
|
||||
* Post transaction operations, fetch data from the buffer and recored the length.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*/
|
||||
void spi_slave_hal_store_result(spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Get the length of last transaction, in bits. Should be called after ``spi_slave_hal_store_result``.
|
||||
*
|
||||
* Note that if last transaction is longer than configured before, the return
|
||||
* value will be truncated to the configured length.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*
|
||||
* @return Length of the last transaction, in bits.
|
||||
*/
|
||||
uint32_t spi_slave_hal_get_rcv_bitlen(spi_slave_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Check whether we need to reset the DMA according to the status of last transactions.
|
||||
*
|
||||
* In ESP32, sometimes we may need to reset the DMA for the slave before the
|
||||
* next transaction. Call this to check it.
|
||||
*
|
||||
* @param hal Context of the HAL layer.
|
||||
*
|
||||
* @return true if reset is needed, else false.
|
||||
*/
|
||||
bool spi_slave_hal_dma_need_reset(const spi_slave_hal_context_t *hal);
|
||||
18
tools/sdk/include/soc/hal/spi_types.h
Normal file
18
tools/sdk/include/soc/hal/spi_types.h
Normal file
@ -0,0 +1,18 @@
|
||||
#pragma once
|
||||
|
||||
#include "soc/spi_caps.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
/**
|
||||
* @brief Enum with the three SPI peripherals that are software-accessible in it
|
||||
*/
|
||||
typedef enum {
|
||||
SPI1_HOST=0, ///< SPI1
|
||||
SPI2_HOST=1, ///< SPI2
|
||||
SPI3_HOST=2, ///< SPI3
|
||||
} spi_host_device_t;
|
||||
|
||||
//alias for different chips
|
||||
#define SPI_HOST SPI1_HOST
|
||||
#define HSPI_HOST SPI2_HOST
|
||||
#define VSPI_HOST SPI3_HOST
|
||||
Reference in New Issue
Block a user