mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
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Update IDF to 1e0710f
This commit is contained in:
me-no-dev
126
tools/sdk/include/soc/soc/dport_access.h
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126
tools/sdk/include/soc/soc/dport_access.h
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@ -0,0 +1,126 @@
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// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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||||
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||||
// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _DPORT_ACCESS_H_
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#define _DPORT_ACCESS_H_
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#include <stdint.h>
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#include "esp_attr.h"
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void esp_dport_access_stall_other_cpu_start(void);
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void esp_dport_access_stall_other_cpu_end(void);
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#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
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#define DPORT_STALL_OTHER_CPU_START()
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#define DPORT_STALL_OTHER_CPU_END()
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#else
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#define DPORT_STALL_OTHER_CPU_START() esp_dport_access_stall_other_cpu_start()
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#define DPORT_STALL_OTHER_CPU_END() esp_dport_access_stall_other_cpu_end()
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#endif
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//Registers Operation {{
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//Origin access operation for the base and some special scene
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#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
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#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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//write value to register
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#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE(_r, _v)
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//read value from register
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static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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{
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uint32_t val;
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DPORT_STALL_OTHER_CPU_START();
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val = _DPORT_REG_READ(reg);
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DPORT_STALL_OTHER_CPU_END();
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return val;
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}
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//get bit or get bits from register
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#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
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//set bit or set bits to register
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#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
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//clear bit or clear bits of register
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#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
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//set bits of register controlled by mask
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#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
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//get field from register, uses field _S & _V to determine mask
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#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
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//set field to register, used when _f is not left shifted by _f##_S
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#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f) << (_f##_S))))|(((_v) & (_f))<<(_f##_S))))
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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//get field value from a variable, used when _f is left shifted by _f##_S
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#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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//set field value to a variable, used when _f is not left shifted by _f##_S
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#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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//set field value to a variable, used when _f is left shifted by _f##_S
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#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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//generate a value from a field value, used when _f is not left shifted by _f##_S
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#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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#define _READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
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#define _WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
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//read value from register
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static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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{
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uint32_t val;
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DPORT_STALL_OTHER_CPU_START();
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val = _READ_PERI_REG(addr);
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DPORT_STALL_OTHER_CPU_END();
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return val;
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}
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//write value to register
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#define DPORT_WRITE_PERI_REG(addr, val) _WRITE_PERI_REG(addr, val)
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//clear bits of register controlled by mask
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#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
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//set bits of register controlled by mask
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#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
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//get bits of register controlled by mask
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#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
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//get bits of register controlled by highest bit and lowest bit
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#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
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//set bits of register controlled by mask and shift
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#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg),(DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))
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//get field of register
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#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
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//}}
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#endif /* _DPORT_ACCESS_H_ */
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@ -16,6 +16,14 @@
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#include "soc.h"
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#ifndef __ASSEMBLER__
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#include "dport_access.h"
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#endif
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/* Registers defined in this header file must be accessed using special macros,
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* prefixed with DPORT_. See soc/dport_access.h file for details.
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||||
*/
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#define DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000)
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/* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: */
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@ -79,12 +79,27 @@
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#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0
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#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c)
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/* EFUSE_RD_CHIP_VER_RESERVE : RO ;bitpos:[16:9] ;default: 8'b0 ; */
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/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
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/*description: bit is set to 1 for rev1 silicon*/
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#define EFUSE_RD_CHIP_VER_REV1 (BIT(15))
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#define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S))
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#define EFUSE_RD_CHIP_VER_REV1_V 0x1
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#define EFUSE_RD_CHIP_VER_REV1_S 15
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/* EFUSE_RD_CHIP_VER_RESERVE : R/W ;bitpos:[15:12] ;default: 3'b0 ; */
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/*description: */
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#define EFUSE_RD_CHIP_VER_RESERVE 0x000000FF
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#define EFUSE_RD_CHIP_VER_RESERVE 0x00000007
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#define EFUSE_RD_CHIP_VER_RESERVE_M ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S))
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#define EFUSE_RD_CHIP_VER_RESERVE_V 0xFF
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#define EFUSE_RD_CHIP_VER_RESERVE_S 9
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#define EFUSE_RD_CHIP_VER_RESERVE_V 0x7
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#define EFUSE_RD_CHIP_VER_RESERVE_S 12
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/* EFUSE_RD_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
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/*description: chip package */
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#define EFUSE_RD_CHIP_VER 0x00000007
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#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S))
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#define EFUSE_RD_CHIP_VER_PKG_V 0x7
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#define EFUSE_RD_CHIP_VER_PKG_S 9
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#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0
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#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1
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#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2
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/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */
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/*description: read for SPI_pad_config_hd*/
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#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F
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@ -297,12 +312,24 @@
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#define EFUSE_WIFI_MAC_CRC_HIGH_S 0
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#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028)
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/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[16:9] ;default: 8'b0 ; */
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/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
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/*description: */
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#define EFUSE_CHIP_VER_RESERVE 0x000000FF
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#define EFUSE_CHIP_VER_REV1 (BIT(15))
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#define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S))
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#define EFUSE_CHIP_VER_REV1_V 0x1
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#define EFUSE_CHIP_VER_REV1_S 15
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/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[15:12] ;default: 3'b0 ; */
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/*description: */
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#define EFUSE_CHIP_VER_RESERVE 0x00000007
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#define EFUSE_CHIP_VER_RESERVE_M ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S))
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#define EFUSE_CHIP_VER_RESERVE_V 0xFF
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#define EFUSE_CHIP_VER_RESERVE_S 9
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#define EFUSE_CHIP_VER_RESERVE_V 0x7
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#define EFUSE_CHIP_VER_RESERVE_S 12
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/* EFUSE_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
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/*description: */
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#define EFUSE_CHIP_VER_PKG 0x00000007
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#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S))
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#define EFUSE_CHIP_VER_PKG_V 0x7
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#define EFUSE_CHIP_VER_PKG_S 9
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/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */
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/*description: program for SPI_pad_config_hd*/
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#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F
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3028
tools/sdk/include/soc/soc/mcpwm_reg.h
Normal file
3028
tools/sdk/include/soc/soc/mcpwm_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
452
tools/sdk/include/soc/soc/mcpwm_struct.h
Normal file
452
tools/sdk/include/soc/soc/mcpwm_struct.h
Normal file
@ -0,0 +1,452 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_MCPWM_STRUCT_H__
|
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#define _SOC_MCPWM_STRUCT_H__
|
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typedef volatile struct {
|
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union {
|
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struct {
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uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}clk_cfg;
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struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t prescale: 8; /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
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uint32_t period: 16; /*period shadow reg of PWM timer0*/
|
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uint32_t upmethod: 2; /*Update method for active reg of PWM timer0 period 0: immediate 1: TEZ 2: sync 3: TEZ | sync. TEZ here and below means timer equal zero event*/
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uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
}period;
|
||||
union {
|
||||
struct {
|
||||
uint32_t start: 3; /*PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/
|
||||
uint32_t mode: 2; /*PWM timer0 working mode 0: freeze 1: increase mod 2: decrease mod 3: up-down mod*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
}mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_en: 1; /*when set timer reload with phase on sync input event is enabled*/
|
||||
uint32_t sync_sw: 1; /*write the negate value will trigger a software sync*/
|
||||
uint32_t out_sel: 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/
|
||||
uint32_t timer_phase: 17; /*phase for timer reload on sync event*/
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
}sync;
|
||||
union {
|
||||
struct {
|
||||
uint32_t value: 16; /*current PWM timer0 counter value*/
|
||||
uint32_t direction: 1; /*current PWM timer0 counter direction 0: increment 1: decrement*/
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}status;
|
||||
}timer[3];
|
||||
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t t0_in_sel: 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
|
||||
uint32_t t1_in_sel: 3; /*select sync input for PWM timer1 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
|
||||
uint32_t t2_in_sel: 3; /*select sync input for PWM timer2 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
|
||||
uint32_t ext_in0_inv: 1; /*invert SYNC0 from GPIO matrix*/
|
||||
uint32_t ext_in1_inv: 1; /*invert SYNC1 from GPIO matrix*/
|
||||
uint32_t ext_in2_inv: 1; /*invert SYNC2 from GPIO matrix*/
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
}timer_synci_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t operator0_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator0 0: timer0 1: timer1 2: timer2*/
|
||||
uint32_t operator1_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator1 0: timer0 1: timer1 2: timer2*/
|
||||
uint32_t operator2_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator2 0: timer0 1: timer1 2: timer2*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
}timer_sel;
|
||||
|
||||
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t a_upmethod: 4; /*Update method for PWM compare0 A's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/
|
||||
uint32_t b_upmethod: 4; /*Update method for PWM compare0 B's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/
|
||||
uint32_t a_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/
|
||||
uint32_t b_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
}cmpr_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cmpr_val: 16; /*PWM compare0 A's shadow reg*/
|
||||
uint32_t reserved16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
}cmpr_value[2];
|
||||
union {
|
||||
struct {
|
||||
uint32_t upmethod: 4; /*Update method for PWM generate0's active reg of configuration. 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: freeze*/
|
||||
uint32_t t0_sel: 3; /*Source selection for PWM generate0 event_t0 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/
|
||||
uint32_t t1_sel: 3; /*Source selection for PWM generate0 event_t1 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
}gen_cfg0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cntu_force_upmethod: 6; /*Update method for continuous software force of PWM generate0. 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: freeze. (TEA/B here and below means timer equals A/B event)*/
|
||||
uint32_t a_cntuforce_mode: 2; /*Continuous software force mode for PWM0A. 0: disabled 1: low 2: high 3: disabled*/
|
||||
uint32_t b_cntuforce_mode: 2; /*Continuous software force mode for PWM0B. 0: disabled 1: low 2: high 3: disabled*/
|
||||
uint32_t a_nciforce: 1; /*non-continuous immediate software force trigger for PWM0A a toggle will trigger a force event*/
|
||||
uint32_t a_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0A 0: disabled 1: low 2: high 3: disabled*/
|
||||
uint32_t b_nciforce: 1; /*non-continuous immediate software force trigger for PWM0B a toggle will trigger a force event*/
|
||||
uint32_t b_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0B 0: disabled 1: low 2: high 3: disabled*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
}gen_force;
|
||||
union {
|
||||
struct {
|
||||
uint32_t utez: 2; /*Action on PWM0A triggered by event TEZ when timer increasing*/
|
||||
uint32_t utep: 2; /*Action on PWM0A triggered by event TEP when timer increasing*/
|
||||
uint32_t utea: 2; /*Action on PWM0A triggered by event TEA when timer increasing*/
|
||||
uint32_t uteb: 2; /*Action on PWM0A triggered by event TEB when timer increasing*/
|
||||
uint32_t ut0: 2; /*Action on PWM0A triggered by event_t0 when timer increasing*/
|
||||
uint32_t ut1: 2; /*Action on PWM0A triggered by event_t1 when timer increasing*/
|
||||
uint32_t dtez: 2; /*Action on PWM0A triggered by event TEZ when timer decreasing*/
|
||||
uint32_t dtep: 2; /*Action on PWM0A triggered by event TEP when timer decreasing*/
|
||||
uint32_t dtea: 2; /*Action on PWM0A triggered by event TEA when timer decreasing*/
|
||||
uint32_t dteb: 2; /*Action on PWM0A triggered by event TEB when timer decreasing*/
|
||||
uint32_t dt0: 2; /*Action on PWM0A triggered by event_t0 when timer decreasing*/
|
||||
uint32_t dt1: 2; /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change 1: low 2: high 3: toggle*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}generator[2];
|
||||
union {
|
||||
struct {
|
||||
uint32_t fed_upmethod: 4; /*Update method for FED (falling edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
|
||||
uint32_t red_upmethod: 4; /*Update method for RED (rising edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
|
||||
uint32_t deb_mode: 1; /*S8 in documentation dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/
|
||||
uint32_t a_outswap: 1; /*S6 in documentation*/
|
||||
uint32_t b_outswap: 1; /*S7 in documentation*/
|
||||
uint32_t red_insel: 1; /*S4 in documentation*/
|
||||
uint32_t fed_insel: 1; /*S5 in documentation*/
|
||||
uint32_t red_outinvert: 1; /*S2 in documentation*/
|
||||
uint32_t fed_outinvert: 1; /*S3 in documentation*/
|
||||
uint32_t a_outbypass: 1; /*S1 in documentation*/
|
||||
uint32_t b_outbypass: 1; /*S0 in documentation*/
|
||||
uint32_t clk_sel: 1; /*Dead band0 clock selection. 0: PWM_clk 1: PT_clk*/
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
}db_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t fed: 16; /*Shadow reg for FED*/
|
||||
uint32_t reserved16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
}db_fed_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t red: 16; /*Shadow reg for RED*/
|
||||
uint32_t reserved16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
}db_red_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t en: 1; /*When set carrier0 function is enabled. When reset carrier0 is bypassed*/
|
||||
uint32_t prescale: 4; /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
|
||||
uint32_t duty: 3; /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
|
||||
uint32_t oshtwth: 4; /*width of the fist pulse in number of periods of the carrier*/
|
||||
uint32_t out_invert: 1; /*when set invert the output of PWM0A and PWM0B for this submodule*/
|
||||
uint32_t in_invert: 1; /*when set invert the input of PWM0A and PWM0B for this submodule*/
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
}carrier_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_cbc: 1; /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
|
||||
uint32_t f2_cbc: 1; /*event_f2 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
|
||||
uint32_t f1_cbc: 1; /*event_f1 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
|
||||
uint32_t f0_cbc: 1; /*event_f0 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
|
||||
uint32_t sw_ost: 1; /*one-shot tripping software force event will trigger one-shot trip event. 0: disable 1: enable*/
|
||||
uint32_t f2_ost: 1; /*event_f2 will trigger one-shot trip event. 0: disable 1: enable*/
|
||||
uint32_t f1_ost: 1; /*event_f1 will trigger one-shot trip event. 0: disable 1: enable*/
|
||||
uint32_t f0_ost: 1; /*event_f0 will trigger one-shot trip event. 0: disable 1: enable*/
|
||||
uint32_t a_cbc_d: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t a_cbc_u: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t a_ost_d: 2; /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t a_ost_u: 2; /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t b_cbc_d: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t b_cbc_u: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t b_ost_d: 2; /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t b_ost_u: 2; /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}tz_cfg0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clr_ost: 1; /*a toggle will clear on going one-shot tripping*/
|
||||
uint32_t cbcpulse: 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/
|
||||
uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/
|
||||
uint32_t force_ost: 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
}tz_cfg1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cbc_on: 1; /*Set and reset by hardware. If set an cycle-by-cycle trip event is on going*/
|
||||
uint32_t ost_on: 1; /*Set and reset by hardware. If set an one-shot trip event is on going*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
}tz_status;
|
||||
}channel[3];
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t f0_en: 1; /*When set event_f0 generation is enabled*/
|
||||
uint32_t f1_en: 1; /*When set event_f1 generation is enabled*/
|
||||
uint32_t f2_en: 1; /*When set event_f2 generation is enabled*/
|
||||
uint32_t f0_pole: 1; /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
|
||||
uint32_t f1_pole: 1; /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
|
||||
uint32_t f2_pole: 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
|
||||
uint32_t event_f0: 1; /*Set and reset by hardware. If set event_f0 is on going*/
|
||||
uint32_t event_f1: 1; /*Set and reset by hardware. If set event_f1 is on going*/
|
||||
uint32_t event_f2: 1; /*Set and reset by hardware. If set event_f2 is on going*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
}fault_detect;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer_en: 1; /*When set capture timer incrementing under APB_clk is enabled.*/
|
||||
uint32_t synci_en: 1; /*When set capture timer sync is enabled.*/
|
||||
uint32_t synci_sel: 3; /*capture module sync input selection. 0: none 1: timer0 synco 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/
|
||||
uint32_t sync_sw: 1; /*Write 1 will force a capture timer sync capture timer is loaded with value in phase register.*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
}cap_timer_cfg;
|
||||
uint32_t cap_timer_phase; /*Phase value for capture timer sync operation.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t en: 1; /*When set capture on channel 0 is enabled*/
|
||||
uint32_t mode: 2; /*Edge of capture on channel 0 after prescale. bit0: negedge cap en bit1: posedge cap en*/
|
||||
uint32_t prescale: 8; /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/
|
||||
uint32_t in_invert: 1; /*when set CAP0 form GPIO matrix is inverted before prescale*/
|
||||
uint32_t sw: 1; /*Write 1 will trigger a software forced capture on channel 0*/
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
}cap_cfg_ch[3];
|
||||
uint32_t cap_val_ch[3]; /*Value of last capture on channel 0*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t cap0_edge: 1; /*Edge of last capture trigger on channel 0 0: posedge 1: negedge*/
|
||||
uint32_t cap1_edge: 1; /*Edge of last capture trigger on channel 1 0: posedge 1: negedge*/
|
||||
uint32_t cap2_edge: 1; /*Edge of last capture trigger on channel 2 0: posedge 1: negedge*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
}cap_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t global_up_en: 1; /*The global enable of update of all active registers in MCPWM module*/
|
||||
uint32_t global_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/
|
||||
uint32_t op0_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 0 are enabled*/
|
||||
uint32_t op0_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/
|
||||
uint32_t op1_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 1 are enabled*/
|
||||
uint32_t op1_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/
|
||||
uint32_t op2_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 2 are enabled*/
|
||||
uint32_t op2_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
}update_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer0_stop_int_ena: 1; /*Interrupt when timer 0 stops*/
|
||||
uint32_t timer1_stop_int_ena: 1; /*Interrupt when timer 1 stops*/
|
||||
uint32_t timer2_stop_int_ena: 1; /*Interrupt when timer 2 stops*/
|
||||
uint32_t timer0_tez_int_ena: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer1_tez_int_ena: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer2_tez_int_ena: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer0_tep_int_ena: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
|
||||
uint32_t timer1_tep_int_ena: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
|
||||
uint32_t timer2_tep_int_ena: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
|
||||
uint32_t fault0_int_ena: 1; /*Interrupt when event_f0 starts*/
|
||||
uint32_t fault1_int_ena: 1; /*Interrupt when event_f1 starts*/
|
||||
uint32_t fault2_int_ena: 1; /*Interrupt when event_f2 starts*/
|
||||
uint32_t fault0_clr_int_ena: 1; /*Interrupt when event_f0 ends*/
|
||||
uint32_t fault1_clr_int_ena: 1; /*Interrupt when event_f1 ends*/
|
||||
uint32_t fault2_clr_int_ena: 1; /*Interrupt when event_f2 ends*/
|
||||
uint32_t cmpr0_tea_int_ena: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr1_tea_int_ena: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr2_tea_int_ena: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr0_teb_int_ena: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
|
||||
uint32_t cmpr1_teb_int_ena: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
|
||||
uint32_t cmpr2_teb_int_ena: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
|
||||
uint32_t tz0_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
|
||||
uint32_t tz1_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
|
||||
uint32_t tz2_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
|
||||
uint32_t tz0_ost_int_ena: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
|
||||
uint32_t tz1_ost_int_ena: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
|
||||
uint32_t tz2_ost_int_ena: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
|
||||
uint32_t cap0_int_ena: 1; /*A capture on channel 0 will trigger this interrupt*/
|
||||
uint32_t cap1_int_ena: 1; /*A capture on channel 1 will trigger this interrupt*/
|
||||
uint32_t cap2_int_ena: 1; /*A capture on channel 2 will trigger this interrupt*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer0_stop_int_raw: 1; /*Interrupt when timer 0 stops*/
|
||||
uint32_t timer1_stop_int_raw: 1; /*Interrupt when timer 1 stops*/
|
||||
uint32_t timer2_stop_int_raw: 1; /*Interrupt when timer 2 stops*/
|
||||
uint32_t timer0_tez_int_raw: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer1_tez_int_raw: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer2_tez_int_raw: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer0_tep_int_raw: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
|
||||
uint32_t timer1_tep_int_raw: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
|
||||
uint32_t timer2_tep_int_raw: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
|
||||
uint32_t fault0_int_raw: 1; /*Interrupt when event_f0 starts*/
|
||||
uint32_t fault1_int_raw: 1; /*Interrupt when event_f1 starts*/
|
||||
uint32_t fault2_int_raw: 1; /*Interrupt when event_f2 starts*/
|
||||
uint32_t fault0_clr_int_raw: 1; /*Interrupt when event_f0 ends*/
|
||||
uint32_t fault1_clr_int_raw: 1; /*Interrupt when event_f1 ends*/
|
||||
uint32_t fault2_clr_int_raw: 1; /*Interrupt when event_f2 ends*/
|
||||
uint32_t cmpr0_tea_int_raw: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr1_tea_int_raw: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr2_tea_int_raw: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr0_teb_int_raw: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
|
||||
uint32_t cmpr1_teb_int_raw: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
|
||||
uint32_t cmpr2_teb_int_raw: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
|
||||
uint32_t tz0_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
|
||||
uint32_t tz1_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
|
||||
uint32_t tz2_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
|
||||
uint32_t tz0_ost_int_raw: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
|
||||
uint32_t tz1_ost_int_raw: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
|
||||
uint32_t tz2_ost_int_raw: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
|
||||
uint32_t cap0_int_raw: 1; /*A capture on channel 0 will trigger this interrupt*/
|
||||
uint32_t cap1_int_raw: 1; /*A capture on channel 1 will trigger this interrupt*/
|
||||
uint32_t cap2_int_raw: 1; /*A capture on channel 2 will trigger this interrupt*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer0_stop_int_st: 1; /*Interrupt when timer 0 stops*/
|
||||
uint32_t timer1_stop_int_st: 1; /*Interrupt when timer 1 stops*/
|
||||
uint32_t timer2_stop_int_st: 1; /*Interrupt when timer 2 stops*/
|
||||
uint32_t timer0_tez_int_st: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer1_tez_int_st: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer2_tez_int_st: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer0_tep_int_st: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
|
||||
uint32_t timer1_tep_int_st: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
|
||||
uint32_t timer2_tep_int_st: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
|
||||
uint32_t fault0_int_st: 1; /*Interrupt when event_f0 starts*/
|
||||
uint32_t fault1_int_st: 1; /*Interrupt when event_f1 starts*/
|
||||
uint32_t fault2_int_st: 1; /*Interrupt when event_f2 starts*/
|
||||
uint32_t fault0_clr_int_st: 1; /*Interrupt when event_f0 ends*/
|
||||
uint32_t fault1_clr_int_st: 1; /*Interrupt when event_f1 ends*/
|
||||
uint32_t fault2_clr_int_st: 1; /*Interrupt when event_f2 ends*/
|
||||
uint32_t cmpr0_tea_int_st: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr1_tea_int_st: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr2_tea_int_st: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr0_teb_int_st: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
|
||||
uint32_t cmpr1_teb_int_st: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
|
||||
uint32_t cmpr2_teb_int_st: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
|
||||
uint32_t tz0_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
|
||||
uint32_t tz1_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
|
||||
uint32_t tz2_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
|
||||
uint32_t tz0_ost_int_st: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
|
||||
uint32_t tz1_ost_int_st: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
|
||||
uint32_t tz2_ost_int_st: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
|
||||
uint32_t cap0_int_st: 1; /*A capture on channel 0 will trigger this interrupt*/
|
||||
uint32_t cap1_int_st: 1; /*A capture on channel 1 will trigger this interrupt*/
|
||||
uint32_t cap2_int_st: 1; /*A capture on channel 2 will trigger this interrupt*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer0_stop_int_clr: 1; /*Interrupt when timer 0 stops*/
|
||||
uint32_t timer1_stop_int_clr: 1; /*Interrupt when timer 1 stops*/
|
||||
uint32_t timer2_stop_int_clr: 1; /*Interrupt when timer 2 stops*/
|
||||
uint32_t timer0_tez_int_clr: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer1_tez_int_clr: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer2_tez_int_clr: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
|
||||
uint32_t timer0_tep_int_clr: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
|
||||
uint32_t timer1_tep_int_clr: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
|
||||
uint32_t timer2_tep_int_clr: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
|
||||
uint32_t fault0_int_clr: 1; /*Interrupt when event_f0 starts*/
|
||||
uint32_t fault1_int_clr: 1; /*Interrupt when event_f1 starts*/
|
||||
uint32_t fault2_int_clr: 1; /*Interrupt when event_f2 starts*/
|
||||
uint32_t fault0_clr_int_clr: 1; /*Interrupt when event_f0 ends*/
|
||||
uint32_t fault1_clr_int_clr: 1; /*Interrupt when event_f1 ends*/
|
||||
uint32_t fault2_clr_int_clr: 1; /*Interrupt when event_f2 ends*/
|
||||
uint32_t cmpr0_tea_int_clr: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr1_tea_int_clr: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr2_tea_int_clr: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
|
||||
uint32_t cmpr0_teb_int_clr: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
|
||||
uint32_t cmpr1_teb_int_clr: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
|
||||
uint32_t cmpr2_teb_int_clr: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
|
||||
uint32_t tz0_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
|
||||
uint32_t tz1_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
|
||||
uint32_t tz2_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
|
||||
uint32_t tz0_ost_int_clr: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
|
||||
uint32_t tz1_ost_int_clr: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
|
||||
uint32_t tz2_ost_int_clr: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
|
||||
uint32_t cap0_int_clr: 1; /*A capture on channel 0 will trigger this interrupt*/
|
||||
uint32_t cap1_int_clr: 1; /*A capture on channel 1 will trigger this interrupt*/
|
||||
uint32_t cap2_int_clr: 1; /*A capture on channel 2 will trigger this interrupt*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en: 1; /*Force clock on for this reg file*/
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
}reg_clk;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28; /*Version of this reg file*/
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
}version;
|
||||
} mcpwm_dev_t;
|
||||
extern mcpwm_dev_t MCPWM0;
|
||||
extern mcpwm_dev_t MCPWM1;
|
||||
#endif /* _SOC_MCPWM_STRUCT_H__ */
|
||||
@ -17,6 +17,7 @@
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
#include "esp_assert.h"
|
||||
#endif
|
||||
|
||||
//Register Bits{{
|
||||
@ -57,98 +58,6 @@
|
||||
#define PRO_CPU_NUM (0)
|
||||
#define APP_CPU_NUM (1)
|
||||
|
||||
//Registers Operation {{
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
#define ETS_CACHED_ADDR(addr) (addr)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
#else
|
||||
#define BIT(nr) (1 << (nr))
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
//write value to register
|
||||
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
|
||||
|
||||
//read value from register
|
||||
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
|
||||
|
||||
//get bit or get bits from register
|
||||
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
|
||||
|
||||
//set bit or set bits to register
|
||||
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
|
||||
|
||||
//set field of a register from variable, uses field _S & _V to determine mask
|
||||
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//read value from register
|
||||
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
|
||||
|
||||
//write value to register
|
||||
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
|
||||
|
||||
//get field of register
|
||||
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
|
||||
//}}
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
//Periheral Clock {{
|
||||
#define APB_CLK_FREQ_ROM ( 26*1000000 )
|
||||
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
|
||||
#define CPU_CLK_FREQ APB_CLK_FREQ
|
||||
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
|
||||
#define UART_CLK_FREQ APB_CLK_FREQ
|
||||
#define WDT_CLK_FREQ APB_CLK_FREQ
|
||||
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
|
||||
#define SPI_CLK_DIV 4
|
||||
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
|
||||
//}}
|
||||
|
||||
/* Overall memory map */
|
||||
#define SOC_IROM_LOW 0x400D0000
|
||||
#define SOC_IROM_HIGH 0x40400000
|
||||
@ -160,6 +69,7 @@
|
||||
#define SOC_RTC_DATA_HIGH 0x50002000
|
||||
|
||||
#define DR_REG_DPORT_BASE 0x3ff00000
|
||||
#define DR_REG_DPORT_END 0x3ff00FFC
|
||||
#define DR_REG_RSA_BASE 0x3ff02000
|
||||
#define DR_REG_SHA_BASE 0x3ff03000
|
||||
#define DR_REG_UART_BASE 0x3ff40000
|
||||
@ -210,6 +120,155 @@
|
||||
#define DR_REG_PWM3_BASE 0x3ff70000
|
||||
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
|
||||
|
||||
//Registers Operation {{
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
#define ETS_CACHED_ADDR(addr) (addr)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
#else
|
||||
#define BIT(nr) (1 << (nr))
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
|
||||
|
||||
#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
|
||||
#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
|
||||
#else
|
||||
#define ASSERT_IF_DPORT_REG(_r, OP)
|
||||
#endif
|
||||
|
||||
//write value to register
|
||||
#define REG_WRITE(_r, _v) ({ \
|
||||
ASSERT_IF_DPORT_REG(_r, REG_WRITE); \
|
||||
(*(volatile uint32_t *)(_r)) = (_v); \
|
||||
})
|
||||
|
||||
//read value from register
|
||||
#define REG_READ(_r) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_READ); \
|
||||
(*(volatile uint32_t *)_r); \
|
||||
})
|
||||
|
||||
//get bit or get bits from register
|
||||
#define REG_GET_BIT(_r, _b) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
|
||||
(*(volatile uint32_t*)(_r) & (_b)); \
|
||||
})
|
||||
|
||||
//set bit or set bits to register
|
||||
#define REG_SET_BIT(_r, _b) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
|
||||
(*(volatile uint32_t*)(_r) |= (_b)); \
|
||||
})
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define REG_CLR_BIT(_r, _b) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
|
||||
(*(volatile uint32_t*)(_r) &= ~(_b)); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define REG_SET_BITS(_r, _b, _m) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
|
||||
(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
|
||||
})
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define REG_GET_FIELD(_r, _f) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
|
||||
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
|
||||
})
|
||||
|
||||
//set field of a register from variable, uses field _S & _V to determine mask
|
||||
#define REG_SET_FIELD(_r, _f, _v) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
|
||||
(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
|
||||
})
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//read value from register
|
||||
#define READ_PERI_REG(addr) ({ \
|
||||
ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
|
||||
})
|
||||
|
||||
//write value to register
|
||||
#define WRITE_PERI_REG(addr, val) ({ \
|
||||
ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
|
||||
})
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define SET_PERI_REG_MASK(reg, mask) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
|
||||
})
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define GET_PERI_REG_MASK(reg, mask) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
|
||||
(READ_PERI_REG(reg) & (mask)); \
|
||||
})
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
|
||||
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
|
||||
(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
|
||||
})
|
||||
|
||||
//get field of register
|
||||
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
|
||||
((READ_PERI_REG(reg)>>(shift))&(mask)); \
|
||||
})
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
//}}
|
||||
|
||||
//Periheral Clock {{
|
||||
#define APB_CLK_FREQ_ROM ( 26*1000000 )
|
||||
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
|
||||
#define CPU_CLK_FREQ APB_CLK_FREQ
|
||||
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
|
||||
#define UART_CLK_FREQ APB_CLK_FREQ
|
||||
#define WDT_CLK_FREQ APB_CLK_FREQ
|
||||
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
|
||||
#define SPI_CLK_DIV 4
|
||||
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
|
||||
//}}
|
||||
|
||||
//Interrupt hardware source table
|
||||
//This table is decided by hardware, don't touch this.
|
||||
#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
|
||||
@ -238,8 +297,8 @@
|
||||
#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/
|
||||
#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
|
||||
#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
|
||||
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for VHCI */
|
||||
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Reserved */
|
||||
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
|
||||
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
|
||||
#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
|
||||
#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
|
||||
#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/
|
||||
@ -316,7 +375,7 @@
|
||||
* 28 4 extern edge
|
||||
* 29 3 software Reserved Reserved
|
||||
* 30 4 extern edge Reserved Reserved
|
||||
* 31 5 extern level Reserved Reserved
|
||||
* 31 5 extern level DPORT ACCESS DPORT ACCESS
|
||||
*************************************************************************************************************
|
||||
*/
|
||||
|
||||
@ -328,6 +387,7 @@
|
||||
#define ETS_FRC1_INUM 22
|
||||
#define ETS_T1_WDT_INUM 24
|
||||
#define ETS_CACHEERR_INUM 25
|
||||
#define ETS_DPORT_INUM 31
|
||||
|
||||
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
|
||||
#define ETS_SLC_INUM 1
|
||||
|
||||
Reference in New Issue
Block a user