mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
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IDF master 1d7068e4b (#5257)
esp-dsp: master 7cc5073 esp-face: master 420fc7e esp-rainmaker: f1b82c7 esp32-camera: master 7a06a7e esp_littlefs: master b58f00c
This commit is contained in:
Me No Dev
GitHub
@ -1,96 +0,0 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SDMMC_REG_H_
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#define _SOC_SDMMC_REG_H_
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#include "soc.h"
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#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00)
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#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04)
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#define SDMMC_CLKDIV_REG (DR_REG_SDMMC_BASE + 0x08)
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#define SDMMC_CLKSRC_REG (DR_REG_SDMMC_BASE + 0x0c)
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#define SDMMC_CLKENA_REG (DR_REG_SDMMC_BASE + 0x10)
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#define SDMMC_TMOUT_REG (DR_REG_SDMMC_BASE + 0x14)
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#define SDMMC_CTYPE_REG (DR_REG_SDMMC_BASE + 0x18)
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#define SDMMC_BLKSIZ_REG (DR_REG_SDMMC_BASE + 0x1c)
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#define SDMMC_BYTCNT_REG (DR_REG_SDMMC_BASE + 0x20)
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#define SDMMC_INTMASK_REG (DR_REG_SDMMC_BASE + 0x24)
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#define SDMMC_CMDARG_REG (DR_REG_SDMMC_BASE + 0x28)
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#define SDMMC_CMD_REG (DR_REG_SDMMC_BASE + 0x2c)
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#define SDMMC_RESP0_REG (DR_REG_SDMMC_BASE + 0x30)
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#define SDMMC_RESP1_REG (DR_REG_SDMMC_BASE + 0x34)
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#define SDMMC_RESP2_REG (DR_REG_SDMMC_BASE + 0x38)
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#define SDMMC_RESP3_REG (DR_REG_SDMMC_BASE + 0x3c)
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#define SDMMC_MINTSTS_REG (DR_REG_SDMMC_BASE + 0x40)
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#define SDMMC_RINTSTS_REG (DR_REG_SDMMC_BASE + 0x44)
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#define SDMMC_STATUS_REG (DR_REG_SDMMC_BASE + 0x48)
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#define SDMMC_FIFOTH_REG (DR_REG_SDMMC_BASE + 0x4c)
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#define SDMMC_CDETECT_REG (DR_REG_SDMMC_BASE + 0x50)
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#define SDMMC_WRTPRT_REG (DR_REG_SDMMC_BASE + 0x54)
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#define SDMMC_GPIO_REG (DR_REG_SDMMC_BASE + 0x58)
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#define SDMMC_TCBCNT_REG (DR_REG_SDMMC_BASE + 0x5c)
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#define SDMMC_TBBCNT_REG (DR_REG_SDMMC_BASE + 0x60)
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#define SDMMC_DEBNCE_REG (DR_REG_SDMMC_BASE + 0x64)
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#define SDMMC_USRID_REG (DR_REG_SDMMC_BASE + 0x68)
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#define SDMMC_VERID_REG (DR_REG_SDMMC_BASE + 0x6c)
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#define SDMMC_HCON_REG (DR_REG_SDMMC_BASE + 0x70)
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#define SDMMC_UHS_REG_REG (DR_REG_SDMMC_BASE + 0x74)
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#define SDMMC_RST_N_REG (DR_REG_SDMMC_BASE + 0x78)
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#define SDMMC_BMOD_REG (DR_REG_SDMMC_BASE + 0x80)
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#define SDMMC_PLDMND_REG (DR_REG_SDMMC_BASE + 0x84)
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#define SDMMC_DBADDR_REG (DR_REG_SDMMC_BASE + 0x88)
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#define SDMMC_DBADDRU_REG (DR_REG_SDMMC_BASE + 0x8c)
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#define SDMMC_IDSTS_REG (DR_REG_SDMMC_BASE + 0x8c)
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#define SDMMC_IDINTEN_REG (DR_REG_SDMMC_BASE + 0x90)
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#define SDMMC_DSCADDR_REG (DR_REG_SDMMC_BASE + 0x94)
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#define SDMMC_DSCADDRL_REG (DR_REG_SDMMC_BASE + 0x98)
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#define SDMMC_DSCADDRU_REG (DR_REG_SDMMC_BASE + 0x9c)
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#define SDMMC_BUFADDRL_REG (DR_REG_SDMMC_BASE + 0xa0)
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#define SDMMC_BUFADDRU_REG (DR_REG_SDMMC_BASE + 0xa4)
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#define SDMMC_CARDTHRCTL_REG (DR_REG_SDMMC_BASE + 0x100)
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#define SDMMC_BACK_END_POWER_REG (DR_REG_SDMMC_BASE + 0x104)
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#define SDMMC_UHS_REG_EXT_REG (DR_REG_SDMMC_BASE + 0x108)
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#define SDMMC_EMMC_DDR_REG_REG (DR_REG_SDMMC_BASE + 0x10c)
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#define SDMMC_ENABLE_SHIFT_REG (DR_REG_SDMMC_BASE + 0x110)
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#define SDMMC_CLOCK_REG (DR_REG_SDMMC_BASE + 0x800)
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#define SDMMC_INTMASK_IO_SLOT1 BIT(17)
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#define SDMMC_INTMASK_IO_SLOT0 BIT(16)
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#define SDMMC_INTMASK_EBE BIT(15)
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#define SDMMC_INTMASK_ACD BIT(14)
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#define SDMMC_INTMASK_SBE BIT(13)
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#define SDMMC_INTMASK_HLE BIT(12)
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#define SDMMC_INTMASK_FRUN BIT(11)
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#define SDMMC_INTMASK_HTO BIT(10)
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#define SDMMC_INTMASK_DTO BIT(9)
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#define SDMMC_INTMASK_RTO BIT(8)
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#define SDMMC_INTMASK_DCRC BIT(7)
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#define SDMMC_INTMASK_RCRC BIT(6)
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#define SDMMC_INTMASK_RXDR BIT(5)
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#define SDMMC_INTMASK_TXDR BIT(4)
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#define SDMMC_INTMASK_DATA_OVER BIT(3)
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#define SDMMC_INTMASK_CMD_DONE BIT(2)
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#define SDMMC_INTMASK_RESP_ERR BIT(1)
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#define SDMMC_INTMASK_CD BIT(0)
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#define SDMMC_IDMAC_INTMASK_AI BIT(9)
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#define SDMMC_IDMAC_INTMASK_NI BIT(8)
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#define SDMMC_IDMAC_INTMASK_CES BIT(5)
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#define SDMMC_IDMAC_INTMASK_DU BIT(4)
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#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
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#define SDMMC_IDMAC_INTMASK_RI BIT(1)
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#define SDMMC_IDMAC_INTMASK_TI BIT(0)
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#endif /* _SOC_SDMMC_REG_H_ */
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@ -1,377 +0,0 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SDMMC_STRUCT_H_
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#define _SOC_SDMMC_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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uint32_t reserved1: 1;
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uint32_t disable_int_on_completion: 1;
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uint32_t last_descriptor: 1;
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uint32_t first_descriptor: 1;
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uint32_t second_address_chained: 1;
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uint32_t end_of_ring: 1;
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uint32_t reserved2: 24;
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uint32_t card_error_summary: 1;
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uint32_t owned_by_idmac: 1;
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uint32_t buffer1_size: 13;
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uint32_t buffer2_size: 13;
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uint32_t reserved3: 6;
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void* buffer1_ptr;
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union {
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void* buffer2_ptr;
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void* next_desc_ptr;
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};
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} sdmmc_desc_t;
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#define SDMMC_DMA_MAX_BUF_LEN 4096
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_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
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typedef struct {
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uint32_t cmd_index: 6; ///< Command index
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uint32_t response_expect: 1; ///< set if response is expected
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uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected
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uint32_t check_response_crc: 1; ///< set if controller should check response CRC
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uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected
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uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected)
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uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected)
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uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer
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uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete
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uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer
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uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1)
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uint32_t card_num: 5; ///< card number
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uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers
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uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device
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uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device
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uint32_t enable_boot: 1; ///< set for mandatory boot mode
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uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern
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uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot)
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uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation
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uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only)
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uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register
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uint32_t reserved: 1;
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uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared.
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} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values
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_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
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typedef volatile struct {
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union {
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struct {
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uint32_t controller_reset: 1;
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uint32_t fifo_reset: 1;
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uint32_t dma_reset: 1;
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uint32_t reserved1: 1;
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uint32_t int_enable: 1;
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uint32_t dma_enable: 1;
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uint32_t read_wait: 1;
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uint32_t send_irq_response: 1;
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uint32_t abort_read_data: 1;
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uint32_t send_ccsd: 1;
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uint32_t send_auto_stop_ccsd: 1;
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uint32_t ceata_device_interrupt_status: 1;
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uint32_t reserved2: 4;
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uint32_t card_voltage_a: 4;
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uint32_t card_voltage_b: 4;
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uint32_t enable_od_pullup: 1;
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uint32_t use_internal_dma: 1;
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uint32_t reserved3: 6;
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};
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uint32_t val;
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} ctrl;
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uint32_t pwren; ///< 1: enable power to card, 0: disable power to card
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union {
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struct {
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uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
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uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
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uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
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uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
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};
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uint32_t val;
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} clkdiv;
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union {
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struct {
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uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3
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uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3
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uint32_t reserved: 28;
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};
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uint32_t val;
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} clksrc;
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union {
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struct {
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uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock
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uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating
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};
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uint32_t val;
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} clkena;
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union {
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struct {
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uint32_t response: 8; ///< response timeout, in card output clock cycles
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uint32_t data: 24; ///< data read timeout, in card output clock cycles
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};
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uint32_t val;
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} tmout;
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union {
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struct {
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uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode
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uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored)
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};
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uint32_t val;
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} ctype;
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uint32_t blksiz: 16; ///< block size, default 0x200
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uint32_t : 16;
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uint32_t bytcnt; ///< number of bytes to be transferred
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union {
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struct {
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uint32_t cd: 1; ///< Card detect interrupt enable
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uint32_t re: 1; ///< Response error interrupt enable
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uint32_t cmd_done: 1; ///< Command done interrupt enable
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uint32_t dto: 1; ///< Data transfer over interrupt enable
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uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable
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uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable
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uint32_t rcrc: 1; ///< Response CRC error interrupt enable
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uint32_t dcrc: 1; ///< Data CRC error interrupt enable
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uint32_t rto: 1; ///< Response timeout interrupt enable
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uint32_t drto: 1; ///< Data read timeout interrupt enable
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uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable
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uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable
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uint32_t hle: 1; ///< Hardware locked write error interrupt enable
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uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable
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uint32_t acd: 1; ///< Auto command done interrupt enable
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uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable
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uint32_t sdio: 16; ///< SDIO interrupt enable
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};
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uint32_t val;
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} intmask;
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uint32_t cmdarg; ///< Command argument to be passed to card
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sdmmc_hw_cmd_t cmd;
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uint32_t resp[4]; ///< Response from card
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union {
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struct {
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uint32_t cd: 1; ///< Card detect interrupt masked status
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uint32_t re: 1; ///< Response error interrupt masked status
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uint32_t cmd_done: 1; ///< Command done interrupt masked status
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uint32_t dto: 1; ///< Data transfer over interrupt masked status
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uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status
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uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status
|
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uint32_t rcrc: 1; ///< Response CRC error interrupt masked status
|
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uint32_t dcrc: 1; ///< Data CRC error interrupt masked status
|
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uint32_t rto: 1; ///< Response timeout interrupt masked status
|
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uint32_t drto: 1; ///< Data read timeout interrupt masked status
|
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uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status
|
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uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status
|
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uint32_t hle: 1; ///< Hardware locked write error interrupt masked status
|
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uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status
|
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uint32_t acd: 1; ///< Auto command done interrupt masked status
|
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uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status
|
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uint32_t sdio: 16; ///< SDIO interrupt masked status
|
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};
|
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uint32_t val;
|
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} mintsts;
|
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|
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union {
|
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struct {
|
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uint32_t cd: 1; ///< Card detect raw interrupt status
|
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uint32_t re: 1; ///< Response error raw interrupt status
|
||||
uint32_t cmd_done: 1; ///< Command done raw interrupt status
|
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uint32_t dto: 1; ///< Data transfer over raw interrupt status
|
||||
uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status
|
||||
uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status
|
||||
uint32_t rcrc: 1; ///< Response CRC error raw interrupt status
|
||||
uint32_t dcrc: 1; ///< Data CRC error raw interrupt status
|
||||
uint32_t rto: 1; ///< Response timeout raw interrupt status
|
||||
uint32_t drto: 1; ///< Data read timeout raw interrupt status
|
||||
uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status
|
||||
uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status
|
||||
uint32_t hle: 1; ///< Hardware locked write error raw interrupt status
|
||||
uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status
|
||||
uint32_t acd: 1; ///< Auto command done raw interrupt status
|
||||
uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status
|
||||
uint32_t sdio: 16; ///< SDIO raw interrupt status
|
||||
};
|
||||
uint32_t val;
|
||||
} rintsts; ///< interrupts can be cleared by writing this register
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level
|
||||
uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level
|
||||
uint32_t fifo_empty: 1; ///< FIFO is empty
|
||||
uint32_t fifo_full: 1; ///< FIFO is full
|
||||
uint32_t cmd_fsm_state: 4; ///< command FSM state
|
||||
uint32_t data3_status: 1; ///< this bit reads 1 if card is present
|
||||
uint32_t data_busy: 1; ///< this bit reads 1 if card is busy
|
||||
uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy
|
||||
uint32_t response_index: 6; ///< index of the previous response
|
||||
uint32_t fifo_count: 13; ///< number of filled locations in the FIFO
|
||||
uint32_t dma_ack: 1; ///< DMA acknowledge signal
|
||||
uint32_t dma_req: 1; ///< DMA request signal
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_watermark: 12; ///< FIFO TX watermark level
|
||||
uint32_t reserved1: 4;
|
||||
uint32_t rx_watermark: 12; ///< FIFO RX watermark level
|
||||
uint32_t dw_dma_mts: 3;
|
||||
uint32_t reserved2: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} fifoth;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t cards: 2; ///< bit N reads 0 if card N is present
|
||||
uint32_t reserved: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cdetect;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t cards: 2; ///< bit N reads 1 if card N is write protected
|
||||
uint32_t reserved: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} wrtprt;
|
||||
|
||||
uint32_t gpio; ///< unused
|
||||
uint32_t tcbcnt; ///< transferred (to card) byte count
|
||||
uint32_t tbbcnt; ///< transferred from host to FIFO byte count
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms
|
||||
uint32_t reserved: 8;
|
||||
};
|
||||
} debnce;
|
||||
|
||||
uint32_t usrid; ///< user ID
|
||||
uint32_t verid; ///< IP block version
|
||||
uint32_t hcon; ///< compile-time IP configuration
|
||||
uint32_t uhs; ///< TBD
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t cards: 2; ///< bit N resets card N, active low
|
||||
uint32_t reserved: 30;
|
||||
};
|
||||
} rst_n;
|
||||
|
||||
uint32_t reserved_7c;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_reset: 1; ///< set to reset DMA controller
|
||||
uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers
|
||||
uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors
|
||||
uint32_t enable: 1; ///< set to enable IDMAC
|
||||
uint32_t pbl: 3; ///< programmable burst length
|
||||
uint32_t reserved: 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} bmod;
|
||||
|
||||
uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state
|
||||
sdmmc_desc_t* dbaddr; ///< descriptor list base
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t ti: 1; ///< transmit interrupt status
|
||||
uint32_t ri: 1; ///< receive interrupt status
|
||||
uint32_t fbe: 1; ///< fatal bus error
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t du: 1; ///< descriptor unavailable
|
||||
uint32_t ces: 1; ///< card error summary
|
||||
uint32_t reserved2: 2;
|
||||
uint32_t nis: 1; ///< normal interrupt summary
|
||||
uint32_t fbe_code: 3; ///< code of fatal bus error
|
||||
uint32_t fsm: 4; ///< DMAC FSM state
|
||||
uint32_t reserved3: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} idsts;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t ti: 1; ///< transmit interrupt enable
|
||||
uint32_t ri: 1; ///< receive interrupt enable
|
||||
uint32_t fbe: 1; ///< fatal bus error interrupt enable
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t du: 1; ///< descriptor unavailable interrupt enable
|
||||
uint32_t ces: 1; ///< card error interrupt enable
|
||||
uint32_t reserved2: 2;
|
||||
uint32_t ni: 1; ///< normal interrupt interrupt enable
|
||||
uint32_t ai: 1; ///< abnormal interrupt enable
|
||||
uint32_t reserved3: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} idinten;
|
||||
|
||||
uint32_t dscaddr; ///< current host descriptor address
|
||||
uint32_t dscaddrl; ///< unused
|
||||
uint32_t dscaddru; ///< unused
|
||||
uint32_t bufaddrl; ///< unused
|
||||
uint32_t bufaddru; ///< unused
|
||||
uint32_t reserved_a8[22];
|
||||
uint32_t cardthrctl;
|
||||
uint32_t back_end_power;
|
||||
uint32_t uhs_reg_ext;
|
||||
uint32_t emmc_ddr_reg;
|
||||
uint32_t enable_shift;
|
||||
uint32_t reserved_114[443];
|
||||
union {
|
||||
struct {
|
||||
uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270)
|
||||
uint32_t phase_din: 3; ///< phase of data input clock
|
||||
uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral
|
||||
uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
|
||||
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
|
||||
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
|
||||
};
|
||||
uint32_t val;
|
||||
} clock;
|
||||
} sdmmc_dev_t;
|
||||
extern sdmmc_dev_t SDMMC;
|
||||
|
||||
_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure");
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //_SOC_SDMMC_STRUCT_H_
|
||||
@ -31,6 +31,24 @@
|
||||
/** Maximum size of data in the buffer that a DMA descriptor can hold. */
|
||||
#define LLDESC_MAX_NUM_PER_DESC (4096-4)
|
||||
|
||||
// Some DMA operations might impose certain alignment restrictions on the length
|
||||
#define LLDESC_MAX_NUM_PER_DESC_16B_ALIGNED (4096 - 16)
|
||||
#define LLDESC_MAX_NUM_PER_DESC_32B_ALIGNED (4096 - 32)
|
||||
|
||||
/**
|
||||
* Generate a linked list pointing to a (huge) buffer in an descriptor array.
|
||||
*
|
||||
* The caller should ensure there is enough size to hold the array, by calling
|
||||
* ``lldesc_get_required_num_constrained`` with the same max_desc_size argument.
|
||||
*
|
||||
* @param[out] out_desc_array Output of a descriptor array, the head should be fed to the DMA.
|
||||
* @param buffer Buffer for the descriptors to point to.
|
||||
* @param size Size (or length for TX) of the buffer
|
||||
* @param max_desc_size Maximum length of each descriptor
|
||||
* @param isrx The RX DMA may require the buffer to be word-aligned, set to true for a RX link, otherwise false.
|
||||
*/
|
||||
void lldesc_setup_link_constrained(lldesc_t *out_desc_array, const void *buffer, int size, int max_desc_size, bool isrx);
|
||||
|
||||
/**
|
||||
* Generate a linked list pointing to a (huge) buffer in an descriptor array.
|
||||
*
|
||||
@ -42,7 +60,7 @@
|
||||
* @param size Size (or length for TX) of the buffer
|
||||
* @param isrx The RX DMA may require the buffer to be word-aligned, set to true for a RX link, otherwise false.
|
||||
*/
|
||||
void lldesc_setup_link(lldesc_t *out_desc_array, const void *buffer, int size, bool isrx);
|
||||
#define lldesc_setup_link(out_desc_array, buffer, size, isrx) lldesc_setup_link_constrained(out_desc_array, buffer, size, LLDESC_MAX_NUM_PER_DESC, isrx)
|
||||
|
||||
/**
|
||||
* @brief Get the received length of a linked list, until end of the link or eof.
|
||||
@ -61,7 +79,16 @@ int lldesc_get_received_len(lldesc_t* head, lldesc_t** out_next);
|
||||
*
|
||||
* @return Numbers required.
|
||||
*/
|
||||
static inline int lldesc_get_required_num(int data_size)
|
||||
static inline int lldesc_get_required_num_constrained(int data_size, int max_desc_size)
|
||||
{
|
||||
return (data_size + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC;
|
||||
return (data_size + max_desc_size - 1) / max_desc_size;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the number of descriptors required for a given buffer size.
|
||||
*
|
||||
* @param data_size Size to check descriptor num.
|
||||
* @param max_desc_size Maximum length of each descriptor
|
||||
* @return Numbers required.
|
||||
*/
|
||||
#define lldesc_get_required_num(data_size) lldesc_get_required_num_constrained(data_size, LLDESC_MAX_NUM_PER_DESC)
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
//include soc related (generated) definitions
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/soc_pins.h"
|
||||
#include "soc/sdmmc_reg.h"
|
||||
#include "soc/sdmmc_struct.h"
|
||||
@ -24,25 +25,50 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Common SDMMC slot info, doesn't depend on SOC_SDMMC_USE_{IOMUX,GPIO_MATRIX}
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t clk_gpio;
|
||||
uint8_t cmd_gpio;
|
||||
uint8_t d0_gpio;
|
||||
uint8_t d1_gpio;
|
||||
uint8_t d2_gpio;
|
||||
uint8_t d3_gpio;
|
||||
uint8_t d4_gpio;
|
||||
uint8_t d5_gpio;
|
||||
uint8_t d6_gpio;
|
||||
uint8_t d7_gpio;
|
||||
uint8_t card_detect;
|
||||
uint8_t write_protect;
|
||||
uint8_t card_int;
|
||||
uint8_t width;
|
||||
uint8_t width; /*!< Maximum supported slot width (1, 4, 8) */
|
||||
uint8_t card_detect; /*!< Card detect signal in GPIO Matrix */
|
||||
uint8_t write_protect; /*!< Write protect signal in GPIO Matrix */
|
||||
uint8_t card_int; /*!< Card interrupt signal in GPIO Matrix */
|
||||
} sdmmc_slot_info_t;
|
||||
|
||||
/** pin and signal information of each slot */
|
||||
extern const sdmmc_slot_info_t sdmmc_slot_info[];
|
||||
/** Width and GPIO matrix signal numbers for auxillary SD host signals, one structure per slot */
|
||||
extern const sdmmc_slot_info_t sdmmc_slot_info[SOC_SDMMC_NUM_SLOTS];
|
||||
|
||||
/**
|
||||
* This structure lists pin numbers (if SOC_SDMMC_USE_IOMUX is set)
|
||||
* or GPIO Matrix signal numbers (if SOC_SDMMC_USE_GPIO_MATRIX is set)
|
||||
* for the SD bus signals. Field names match SD bus signal names.
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t clk;
|
||||
uint8_t cmd;
|
||||
uint8_t d0;
|
||||
uint8_t d1;
|
||||
uint8_t d2;
|
||||
uint8_t d3;
|
||||
uint8_t d4;
|
||||
uint8_t d5;
|
||||
uint8_t d6;
|
||||
uint8_t d7;
|
||||
} sdmmc_slot_io_info_t;
|
||||
|
||||
/* Note: it is in theory possible to have both IOMUX and GPIO Matrix supported
|
||||
* in the same SoC. However this is not used on any SoC at this point, and would
|
||||
* complicate the driver. Hence only one of these options is supported at a time.
|
||||
*/
|
||||
#if SOC_SDMMC_USE_IOMUX
|
||||
/** GPIO pin numbers of SD bus signals, one structure per slot */
|
||||
extern const sdmmc_slot_io_info_t sdmmc_slot_gpio_num[SOC_SDMMC_NUM_SLOTS];
|
||||
|
||||
#elif SOC_SDMMC_USE_GPIO_MATRIX
|
||||
/** GPIO matrix signal numbers of SD bus signals, one structure per slot */
|
||||
extern const sdmmc_slot_io_info_t sdmmc_slot_gpio_sig[SOC_SDMMC_NUM_SLOTS];
|
||||
|
||||
#endif // SOC_SDMMC_USE_{IOMUX,GPIO_MATRIX}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user