From 56ef31f899670ab6b6813bbe58afbc7f7395efc1 Mon Sep 17 00:00:00 2001 From: Me No Dev Date: Wed, 12 Apr 2017 21:49:58 +0300 Subject: [PATCH] Update IDF to version 3cad00f (#310) --- platform.txt | 4 +- tools/platformio-build.py | 3 +- tools/sdk/bin/bootloader.bin | Bin 10128 -> 11328 bytes tools/sdk/include/bluedroid/alarm.h | 3 + tools/sdk/include/bluedroid/bta_api.h | 2 + tools/sdk/include/bluedroid/btm_api.h | 2 + tools/sdk/include/bluedroid/esp_gap_ble_api.h | 2 + tools/sdk/include/bluedroid/thread.h | 10 +- tools/sdk/include/bt/bt.h | 38 +- tools/sdk/include/config/sdkconfig.h | 4 +- tools/sdk/include/driver/driver/rmt.h | 6 +- tools/sdk/include/esp32/esp_err.h | 5 +- tools/sdk/include/esp32/esp_panic.h | 5 + tools/sdk/include/esp32/esp_task.h | 2 +- tools/sdk/include/esp32/rom/rtc.h | 3 + tools/sdk/include/esp32/rom/spi_flash.h | 299 +- tools/sdk/include/esp32/soc/bb_reg.h | 102 - .../sdk/include/freertos/freertos/portmacro.h | 14 + tools/sdk/include/mdns/mdns.h | 4 + .../sdk/include/{esp32 => soc}/esp_brownout.h | 0 tools/sdk/include/soc/soc/apb_ctrl_reg.h | 294 + tools/sdk/include/soc/soc/apb_ctrl_struct.h | 120 + tools/sdk/include/soc/soc/bb_reg.h | 34 + .../include/{esp32 => soc}/soc/boot_mode.h | 0 tools/sdk/include/{esp32 => soc}/soc/cpu.h | 0 .../include/{esp32 => soc}/soc/dport_reg.h | 0 .../include/{esp32 => soc}/soc/efuse_reg.h | 0 .../include/{esp32 => soc}/soc/emac_ex_reg.h | 0 .../include/{esp32 => soc}/soc/emac_reg_v2.h | 0 tools/sdk/include/soc/soc/fe_reg.h | 33 + .../{esp32 => soc}/soc/frc_timer_reg.h | 0 .../sdk/include/{esp32 => soc}/soc/gpio_reg.h | 0 .../include/{esp32 => soc}/soc/gpio_sd_reg.h | 0 .../{esp32 => soc}/soc/gpio_sd_struct.h | 0 .../include/{esp32 => soc}/soc/gpio_sig_map.h | 0 .../include/{esp32 => soc}/soc/gpio_struct.h | 0 .../include/{esp32 => soc}/soc/hwcrypto_reg.h | 0 .../sdk/include/{esp32 => soc}/soc/i2c_reg.h | 1902 +++---- .../include/{esp32 => soc}/soc/i2c_struct.h | 0 .../sdk/include/{esp32 => soc}/soc/i2s_reg.h | 0 .../include/{esp32 => soc}/soc/i2s_struct.h | 0 .../include/{esp32 => soc}/soc/io_mux_reg.h | 0 .../sdk/include/{esp32 => soc}/soc/ledc_reg.h | 4846 ++++++++--------- .../include/{esp32 => soc}/soc/ledc_struct.h | 0 tools/sdk/include/soc/soc/nrx_reg.h | 39 + .../sdk/include/{esp32 => soc}/soc/pcnt_reg.h | 3052 +++++------ .../include/{esp32 => soc}/soc/pcnt_struct.h | 0 tools/sdk/include/{esp32 => soc}/soc/pid.h | 0 .../sdk/include/{esp32 => soc}/soc/rmt_reg.h | 4344 +++++++-------- .../include/{esp32 => soc}/soc/rmt_struct.h | 0 tools/sdk/include/soc/soc/rtc.h | 496 ++ .../include/{esp32 => soc}/soc/rtc_cntl_reg.h | 70 + tools/sdk/include/soc/soc/rtc_cntl_struct.h | 553 ++ .../include/{esp32 => soc}/soc/rtc_io_reg.h | 3904 ++++++------- tools/sdk/include/soc/soc/rtc_io_struct.h | 280 + .../include/{esp32 => soc}/soc/sdmmc_reg.h | 0 .../include/{esp32 => soc}/soc/sdmmc_struct.h | 0 .../sdk/include/{esp32 => soc}/soc/sens_reg.h | 0 tools/sdk/include/{esp32 => soc}/soc/soc.h | 3 + .../sdk/include/{esp32 => soc}/soc/soc_ulp.h | 0 .../sdk/include/{esp32 => soc}/soc/spi_reg.h | 3422 ++++++------ .../include/{esp32 => soc}/soc/spi_struct.h | 0 .../include/{esp32 => soc}/soc/syscon_reg.h | 0 .../{esp32 => soc}/soc/syscon_struct.h | 0 .../{esp32 => soc}/soc/timer_group_reg.h | 0 .../{esp32 => soc}/soc/timer_group_struct.h | 0 .../sdk/include/{esp32 => soc}/soc/uart_reg.h | 2334 ++++---- .../include/{esp32 => soc}/soc/uart_struct.h | 0 .../sdk/include/{esp32 => soc}/soc/uhci_reg.h | 0 .../include/{esp32 => soc}/soc/uhci_struct.h | 0 .../sdk/include/{esp32 => soc}/soc/wdev_reg.h | 0 .../sdk/include/tcpip_adapter/tcpip_adapter.h | 33 + tools/sdk/ld/esp32.common.ld | 4 +- tools/sdk/ld/esp32.rom.ld | 46 +- tools/sdk/ld/esp32.rom.spiflash.ld | 23 + tools/sdk/lib/libapp_update.a | Bin 45784 -> 45784 bytes tools/sdk/lib/libbootloader_support.a | Bin 111978 -> 111990 bytes tools/sdk/lib/libbt.a | Bin 8570180 -> 8591828 bytes tools/sdk/lib/libbtdm_app.a | Bin 71934 -> 87382 bytes tools/sdk/lib/libcoap.a | Bin 450954 -> 450954 bytes tools/sdk/lib/libcoexist.a | Bin 14930 -> 14930 bytes tools/sdk/lib/libcore.a | Bin 24578 -> 25624 bytes tools/sdk/lib/libcxx.a | Bin 50148 -> 50148 bytes tools/sdk/lib/libdriver.a | Bin 1134386 -> 1134442 bytes tools/sdk/lib/libesp32.a | Bin 507090 -> 505968 bytes tools/sdk/lib/libethernet.a | Bin 100188 -> 100188 bytes tools/sdk/lib/libexpat.a | Bin 1239676 -> 1239676 bytes tools/sdk/lib/libfatfs.a | Bin 344484 -> 344484 bytes tools/sdk/lib/libfreertos.a | Bin 543322 -> 545626 bytes tools/sdk/lib/libjsmn.a | Bin 21578 -> 21578 bytes tools/sdk/lib/libjson.a | Bin 208230 -> 208230 bytes tools/sdk/lib/liblog.a | Bin 20986 -> 20986 bytes tools/sdk/lib/liblwip.a | Bin 1881464 -> 1881672 bytes tools/sdk/lib/libmbedtls.a | Bin 3595712 -> 3595712 bytes tools/sdk/lib/libmdns.a | Bin 199480 -> 199480 bytes tools/sdk/lib/libmicro-ecc.a | Bin 154324 -> 154324 bytes tools/sdk/lib/libnet80211.a | Bin 705680 -> 706290 bytes tools/sdk/lib/libnewlib.a | Bin 80438 -> 80438 bytes tools/sdk/lib/libnghttp.a | Bin 1523258 -> 1523258 bytes tools/sdk/lib/libnvs_flash.a | Bin 626354 -> 626354 bytes tools/sdk/lib/libopenssl.a | Bin 269248 -> 269248 bytes tools/sdk/lib/libpp.a | Bin 410224 -> 463070 bytes tools/sdk/lib/librtc.a | Bin 92258 -> 162012 bytes tools/sdk/lib/librtc_clk.a | Bin 10956 -> 0 bytes tools/sdk/lib/librtc_pm.a | Bin 14202 -> 0 bytes tools/sdk/lib/libsdmmc.a | Bin 70902 -> 70902 bytes tools/sdk/lib/libsoc.a | Bin 0 -> 90482 bytes tools/sdk/lib/libspi_flash.a | Bin 127358 -> 176504 bytes tools/sdk/lib/libtcpip_adapter.a | Bin 77182 -> 95886 bytes tools/sdk/lib/libulp.a | Bin 32720 -> 32720 bytes tools/sdk/lib/libvfs.a | Bin 91266 -> 91270 bytes tools/sdk/lib/libwpa.a | Bin 150704 -> 150704 bytes tools/sdk/lib/libwpa2.a | Bin 427410 -> 427410 bytes tools/sdk/lib/libwpa_supplicant.a | Bin 462596 -> 462596 bytes tools/sdk/lib/libwps.a | Bin 337386 -> 337386 bytes tools/sdk/lib/libxtensa-debug-module.a | Bin 12082 -> 12082 bytes 116 files changed, 14132 insertions(+), 12208 deletions(-) delete mode 100755 tools/sdk/include/esp32/soc/bb_reg.h rename tools/sdk/include/{esp32 => soc}/esp_brownout.h (100%) create mode 100644 tools/sdk/include/soc/soc/apb_ctrl_reg.h create mode 100644 tools/sdk/include/soc/soc/apb_ctrl_struct.h create mode 100644 tools/sdk/include/soc/soc/bb_reg.h rename tools/sdk/include/{esp32 => soc}/soc/boot_mode.h (100%) mode change 100755 => 100644 rename tools/sdk/include/{esp32 => soc}/soc/cpu.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/dport_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/efuse_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/emac_ex_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/emac_reg_v2.h (100%) create mode 100644 tools/sdk/include/soc/soc/fe_reg.h rename tools/sdk/include/{esp32 => soc}/soc/frc_timer_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/gpio_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/gpio_sd_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/gpio_sd_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/gpio_sig_map.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/gpio_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/hwcrypto_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/i2c_reg.h (98%) rename tools/sdk/include/{esp32 => soc}/soc/i2c_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/i2s_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/i2s_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/io_mux_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/ledc_reg.h (98%) rename tools/sdk/include/{esp32 => soc}/soc/ledc_struct.h (100%) create mode 100644 tools/sdk/include/soc/soc/nrx_reg.h rename tools/sdk/include/{esp32 => soc}/soc/pcnt_reg.h (98%) rename tools/sdk/include/{esp32 => soc}/soc/pcnt_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/pid.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/rmt_reg.h (97%) rename tools/sdk/include/{esp32 => soc}/soc/rmt_struct.h (100%) create mode 100644 tools/sdk/include/soc/soc/rtc.h rename tools/sdk/include/{esp32 => soc}/soc/rtc_cntl_reg.h (96%) create mode 100644 tools/sdk/include/soc/soc/rtc_cntl_struct.h rename tools/sdk/include/{esp32 => soc}/soc/rtc_io_reg.h (98%) create mode 100644 tools/sdk/include/soc/soc/rtc_io_struct.h rename tools/sdk/include/{esp32 => soc}/soc/sdmmc_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/sdmmc_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/sens_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/soc.h (99%) mode change 100755 => 100644 rename tools/sdk/include/{esp32 => soc}/soc/soc_ulp.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/spi_reg.h (97%) rename tools/sdk/include/{esp32 => soc}/soc/spi_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/syscon_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/syscon_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/timer_group_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/timer_group_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/uart_reg.h (97%) rename tools/sdk/include/{esp32 => soc}/soc/uart_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/uhci_reg.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/uhci_struct.h (100%) rename tools/sdk/include/{esp32 => soc}/soc/wdev_reg.h (100%) create mode 100644 tools/sdk/ld/esp32.rom.spiflash.ld delete mode 100755 tools/sdk/lib/librtc_clk.a delete mode 100755 tools/sdk/lib/librtc_pm.a create mode 100644 tools/sdk/lib/libsoc.a diff --git a/platform.txt b/platform.txt index 4c8c56f1..d08160ab 100644 --- a/platform.txt +++ b/platform.txt @@ -21,7 +21,7 @@ compiler.warning_flags.all=-Wall -Werror=all -Wextra compiler.path={runtime.tools.xtensa-esp32-elf-gcc.path}/bin/ compiler.sdk.path={runtime.platform.path}/tools/sdk -compiler.cpreprocessor.flags=-DESP_PLATFORM -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DHAVE_CONFIG_H "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/bluedroid" "-I{compiler.sdk.path}/include/app_update" "-I{compiler.sdk.path}/include/bootloader_support" "-I{compiler.sdk.path}/include/bt" "-I{compiler.sdk.path}/include/driver" "-I{compiler.sdk.path}/include/esp32" "-I{compiler.sdk.path}/include/ethernet" "-I{compiler.sdk.path}/include/fatfs" "-I{compiler.sdk.path}/include/freertos" "-I{compiler.sdk.path}/include/jsmn" "-I{compiler.sdk.path}/include/log" "-I{compiler.sdk.path}/include/mdns" "-I{compiler.sdk.path}/include/mbedtls" "-I{compiler.sdk.path}/include/mbedtls_port" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/nvs_flash" "-I{compiler.sdk.path}/include/openssl" "-I{compiler.sdk.path}/include/spi_flash" "-I{compiler.sdk.path}/include/sdmmc" "-I{compiler.sdk.path}/include/tcpip_adapter" "-I{compiler.sdk.path}/include/ulp" "-I{compiler.sdk.path}/include/vfs" "-I{compiler.sdk.path}/include/xtensa-debug-module" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/coap" "-I{compiler.sdk.path}/include/wpa_supplicant" "-I{compiler.sdk.path}/include/expat" "-I{compiler.sdk.path}/include/json" "-I{compiler.sdk.path}/include/nghttp" "-I{compiler.sdk.path}/include/lwip" +compiler.cpreprocessor.flags=-DESP_PLATFORM -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DHAVE_CONFIG_H "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/bluedroid" "-I{compiler.sdk.path}/include/app_update" "-I{compiler.sdk.path}/include/bootloader_support" "-I{compiler.sdk.path}/include/bt" "-I{compiler.sdk.path}/include/driver" "-I{compiler.sdk.path}/include/esp32" "-I{compiler.sdk.path}/include/ethernet" "-I{compiler.sdk.path}/include/fatfs" "-I{compiler.sdk.path}/include/freertos" "-I{compiler.sdk.path}/include/jsmn" "-I{compiler.sdk.path}/include/log" "-I{compiler.sdk.path}/include/mdns" "-I{compiler.sdk.path}/include/mbedtls" "-I{compiler.sdk.path}/include/mbedtls_port" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/nvs_flash" "-I{compiler.sdk.path}/include/openssl" "-I{compiler.sdk.path}/include/soc" "-I{compiler.sdk.path}/include/spi_flash" "-I{compiler.sdk.path}/include/sdmmc" "-I{compiler.sdk.path}/include/tcpip_adapter" "-I{compiler.sdk.path}/include/ulp" "-I{compiler.sdk.path}/include/vfs" "-I{compiler.sdk.path}/include/xtensa-debug-module" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/coap" "-I{compiler.sdk.path}/include/wpa_supplicant" "-I{compiler.sdk.path}/include/expat" "-I{compiler.sdk.path}/include/json" "-I{compiler.sdk.path}/include/nghttp" "-I{compiler.sdk.path}/include/lwip" compiler.c.cmd=xtensa-esp32-elf-gcc compiler.c.flags=-std=gnu99 -Os -g3 -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -nostdlib -Wpointer-arith {compiler.warning_flags} -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -Wno-old-style-declaration -MMD -c @@ -34,7 +34,7 @@ compiler.S.flags=-c -g3 -x assembler-with-cpp -MMD -mlongcalls compiler.c.elf.cmd=xtensa-esp32-elf-gcc compiler.c.elf.flags=-nostdlib "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/ld" -T esp32_out.ld -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld -u call_user_start_cpu0 -Wl,--gc-sections -Wl,-static -Wl,--undefined=uxTopUsedPriority -compiler.c.elf.libs=-lgcc -lstdc++ -lapp_update -lbootloader_support -lbt -lbtdm_app -lc -lc_nano -lcoap -lcoexist -lcore -lcxx -ldriver -lesp32 -lethernet -lexpat -lfatfs -lfreertos -lhal -ljsmn -ljson -llog -llwip -lm -lmbedtls -lmdns -lmicro-ecc -lnet80211 -lnewlib -lnghttp -lnvs_flash -lopenssl -lphy -lpp -lrtc -lrtc_clk -lrtc_pm -lsdmmc -lsmartconfig -lspi_flash -ltcpip_adapter -lulp -lvfs -lwpa -lwpa2 -lwpa_supplicant -lwps -lxtensa-debug-module +compiler.c.elf.libs=-lgcc -lstdc++ -lapp_update -lbootloader_support -lbt -lbtdm_app -lc -lc_nano -lcoap -lcoexist -lcore -lcxx -ldriver -lesp32 -lethernet -lexpat -lfatfs -lfreertos -lhal -ljsmn -ljson -llog -llwip -lm -lmbedtls -lmdns -lmicro-ecc -lnet80211 -lnewlib -lnghttp -lnvs_flash -lopenssl -lphy -lpp -lrtc -lsdmmc -lsmartconfig -lsoc -lspi_flash -ltcpip_adapter -lulp -lvfs -lwpa -lwpa2 -lwpa_supplicant -lwps -lxtensa-debug-module compiler.as.cmd=xtensa-esp32-elf-as diff --git a/tools/platformio-build.py b/tools/platformio-build.py index 6bbe097b..34c15826 100644 --- a/tools/platformio-build.py +++ b/tools/platformio-build.py @@ -67,6 +67,7 @@ env.Prepend( join(FRAMEWORK_DIR, "tools", "sdk", "include", "newlib"), join(FRAMEWORK_DIR, "tools", "sdk", "include", "nvs_flash"), join(FRAMEWORK_DIR, "tools", "sdk", "include", "openssl"), + join(FRAMEWORK_DIR, "tools", "sdk", "include", "soc"), join(FRAMEWORK_DIR, "tools", "sdk", "include", "spi_flash"), join(FRAMEWORK_DIR, "tools", "sdk", "include", "sdmmc"), join(FRAMEWORK_DIR, "tools", "sdk", "include", "tcpip_adapter"), @@ -89,7 +90,7 @@ env.Prepend( ], LIBS=[ - "gcc", "stdc++", "app_update", "bootloader_support", "bt", "btdm_app", "c", "c_nano", "coap", "coexist", "core", "cxx", "driver", "esp32", "ethernet", "expat", "fatfs", "freertos", "hal", "jsmn", "json", "log", "lwip", "m", "mbedtls", "mdns", "micro-ecc", "net80211", "newlib", "nghttp", "nvs_flash", "openssl", "phy", "pp", "rtc", "rtc_clk", "rtc_pm", "sdmmc", "smartconfig", "spi_flash", "tcpip_adapter", "ulp", "vfs", "wpa", "wpa2", "wpa_supplicant", "wps", "xtensa-debug-module" + "gcc", "stdc++", "app_update", "bootloader_support", "bt", "btdm_app", "c", "c_nano", "coap", "coexist", "core", "cxx", "driver", "esp32", "ethernet", "expat", "fatfs", "freertos", "hal", "jsmn", "json", "log", "lwip", "m", "mbedtls", "mdns", "micro-ecc", "net80211", "newlib", "nghttp", "nvs_flash", "openssl", "phy", "pp", "rtc", "sdmmc", "smartconfig", "soc", "spi_flash", "tcpip_adapter", "ulp", "vfs", "wpa", "wpa2", "wpa_supplicant", "wps", "xtensa-debug-module" ], UPLOADERFLAGS=[ diff --git a/tools/sdk/bin/bootloader.bin b/tools/sdk/bin/bootloader.bin index 52aff86707dec5787f9c24b22ca65cc1079cb3da..bc20ab09663136319c12e4ed6708a9c80904b804 100644 GIT binary patch delta 7420 zcmbQ>e;{IliqI3*|Mmh5|LyOvGcYi4{$pIjuu(6L*&~Mezx^Qw1&037&kv)HeumWQD$I} zVfbQybn~K#lNC4|cy$>5+nX@_x6fesZ$D>pE{A&k8HWG%3XK2lLuwfut~4?@oH)eb zz`(=6z|g?J5Wx7~zJc+-J%_;;uv`D1|NsC0_y7NU8ot7~5!Sdh!#^gfI=K2q;|Ly;<{HQ21j1 z!{CcO3rLKCfl)`{i@gHJUy!>T7#J9s3LgEk=K#w&Fvx)9AfBveW?*25VNhUTWME*Z zQBn9}|C)iJfPsM_U^fFpK{f+Jfi(j|0XG9f0W$+b!Ip+E_RaUCoqJlo*fTJ&G5r5; z`TYO?^Zywb1Q)u)A>o_74MY70dxnND_6|<`3>FC-8211A{hwjW5te{f28aJ3lm0XQ```cn zzsm!L1cv|24FC84{m)>)z+mRc&}jSr0S7~)4Vbj}e?WnugQKCtG)&_E(>II>v>hM#G=~tcnT>zB;4{ID|s< zu%2bxw18p5YK6vs{~mBKfOWB+W#i#qw1BbkCrHTg>%RjE3`!O(IY|n}0tXZrELjXc zfrLDm6;wccP3A=l7#d&xn|zR4!s8W#E!Ui?r96ypnQt&1eEM%M*TSd&8b5&y0)@<> zg94itFfLMJP`%DD$4ixq@dneuJ0L}O|24jZD&pa4eEx5;B9ETIb%r@ssjQ55Sq`2A zsX6tp@ft*p#l{|E9w|2l1|F_7XGR{b#-snbnkOEaT+buMb^yfOKY2EfeEp7p=GKfn zoYOhjCvN{|Zpp~Q#Ur_KD_pQ~^FMP7MjkG)SFAe@?lNxN_|IHJzL(K_g;Xww>Tia> zY;T$GvK*WbvU>Hu#x)SD7b)^SZDd$rrEn+e=?{h%2X9oim3oumpcKg8=KmViA&M3$a)@y$)NfMcR5bp#-AFR^I>Vy{ z3O6Pm6acBy|JNuBQOCfb8pp6eOCc5{;r1rJs&Y~%&;*D^g#Vo*{vP-9|h(_>Ilv`}MWa?@eZs9)GK zNh#4mW1~`{&qlxV+} zsqyaL2OJD58W*f_T*}U<%LQghuX@VHxL}dO9Iez-3wka_R7Fs$cM6*TzMP9E)xVEae1ilzMuM;ot?3#`k|AR>*z;VSg^2R>B|3NznH*2e7fTQ8ZRY910zKX1?6IHB_l;W1EojWN&-q7EEZ{O zGD>s+dCmw_GePt|UHV__7o(D*fzqM+|5#PGse>(guwY?>>f--mTue%e7D|V3sFeYk ztfa^#_K8t-H^ae&e?h6?;NQk|ASY`q1cfLlc-w>+7*uyM9GnUA+wQ-O%Rtg0;IyuR z6bo#e3>pU^k#bQf(b0{S;ptX}gFPTk>;E>+1Ze{6S(?wV=ptk4vj1S7nIpr(m46Q? zFwB_MSUcHLP^Nz2UxjXg2^|Ut6c{?IdX{pBHqQOq&??Zzz`(%6p*RDicEzTNGyYDP zArLs@Z$KAJ?Is>h9tnre<^u{0D~bYUFa}OUk}T?(!tK)7{kNe-090CWD7JyjiC8qT z4P=gE+h2!PkU6m&2PR(;6p(EEYha?_%M2=HnHnoWN;^2ze|%9aoBUUBalP!{r;8aL zFfqh(@klU;I52oDbni0a;k|HH;lf^pMGM%LKKt*mRN(E{K8|6Ak}PSS0`=A)+&6de1T`Y*JXXV7}_z$??L9j4G2Gg>4x{Chr%v zV^)3je{znjBsarf*$*|JWIrhW`7?QftVH_WKMJY>h2Q>Eu$K!3^Kdn8`SXB-0Zz+< zs=0$7{_t>vs;sRbxmvC{x0cp3++{!b`p;gjg|GiK?gt6;a5b&~(IB%6AOF#0=izEx z0uoSAJrMZd&t!f%g?doEH5DWVXE+>D*vq_@Y3XqWT`nH3#)%-wwM|GICuhN;i*53b3n>K1-IjgKjvE`RZAHRE-M^7_y?4(kNjzz0+Lo* zz##j3OK*945V-dhYZ((nINq*IW`vknarY~7nkv8Vme5!lM_y-LHVgrIt4`U z;A~9()6fml+{rmH5h|2`5Q>8e#lnReqyJ2vpde}%{%68&fk}%PCd>xup2=}A7_5|M z(t3sovjup%H$a@kb3lRN2G2y_KNIc>O!WOT`L=?NnbV&GXF)mUB*#Mskfs}a2krkH zxGQjIDZ_!YAk$9rfpl>kwEhF-b2M81nQW_QuA>7|zk&l6BCyC^C;$@g;L7Zch=@lFkcl?G4L85x%@5!^2OjU0G-pjS{_V31)-w!w#6tDkw19cG? z6tDd5StQfL!@ZWJamw$>pOrKMPk_b-b7Ir)_MOUNR~esbFkDh&JhD#5noY|KOGu&l6mvtnRSXI*R$(vQQ1;fFjF~1ub zz@ovwC%;#bQ}F&R`$5qYWDbL($8XsWpfZ7hfx#@1!N8y-@Y=7*x~lTB&cE9w6~sQX zsd6wp5@krZrf|?6Y?%G;#s|M9XR4~{7=zqp^1JcMuLm3qN()(JKO`Mv3|bJMzO`3O znQ18#!$ED33Z37LXMRoIt*ThB3U-9jZw0MI3VM#RAIuUNcqBR*8x?*xaWL+Ya1&tQ z;cS!xMaHBIhKWCaHOhe4GdUWiKy(L3n8*J{F%WYGM@LXYr$8rT2P6B7Q*F!)Jke_z z8wEkegG4@PFlsU*JhhgoksG9|zDa|jp+O~#<9{P3h!5uqY*a}7{$EUrfkz5nfEqMx z3CmzsSfudu_y5LqzZ#4M8vpz{puk|1!O-~om*H0syOX)`Gl*`|Ur;?iv}iHcV1tY~RV$X3U_lNTELU`~PEl3=9l5Kf+gpOj`KA@fAq-OpbKoQVhsDq&+{ zUS}G@$#l#J z6jD#0{6D6{0Ai{B`X6?RyJ>-Z_zIgw-(L-r1sXGdHFPRWoCPw!DU$)>;F%ByuV6W# zz_5}N8Z_HFo&_C!V02i)O^AV^(e77$!(@SmRz{HSZjkOyPTV2Tip{`qi)TR#7$!FS zYAgropOnGSSOQ|e<3IK0|7D^~Z5I)#02E3f3~IvEGb}9rm3saErUj-3ixnEvLD{BB znW3RWu#*{*?m!jgS|-)2{~O~#<{D)%Omz9x7z1L1EQ@1U(7}KM=k}fc>!F2_LGYb^9HY{ZOwe;%$H@m7r zrPC4;N;(+Z&F%*ratyd~z~IaRt*s0H|9pBGcZ=h4nud ztOEt;N=^v>*3Sj&K<2LGEdRm8rp3^>A7tboaC4fou@V}`otz6#f()I()p!EzoRe_p zOg#Ow@i<6sCdaV^P(ig1#96`F*!UCHrdqfQ?Ee{DjXS}bcfmCy`(+`>Vs2!=EZhh( zY6e%M3P@Yig59tnIOfK{z~ElNJ8|vL#uXqnGdbMY8J=hGPh9o0aS23#4K$=Tarw{2 z1rUDy#2FyQ3eLu8gu|wQgl2FxP6k;3BC&*VHOO7n$nJ7eXPDRu(z$}OQ3oDEjfEhE zcPu~=%h{+67iZ%Gg-T^TNCPO}SVOG`<(m?a;3O>uXmlomOh5^OiP<0(D>xeqp}IOb z7p8-RW^gs8fgPO&56p?VKO0j)ax*y=M*Unm<9`nqq)Ib$WKc{8+pnYqDpr@qGl;EX zTFa!G$l$O_urcvx!>UCK7G0GIQnwP&5n8^9UFXvBO?<}~7-SYfng^f~U#AINt0^dy zh&8b_hJx&w!J!!P6INn?qLM=~@TY<%D0yju8d)=&QM0o4GQ%dpro$JY@^kv`ttz?1E>Y7r~s0;VDjN; zXa>o4GAYV{L}oBGN`vfZS_&GH0+nVU=YezeL}8GE6`YN2KN`9O6qFbhAm(x|TBy^= z4>cGR=$s&R8cYg$qTsM=tY-xY%m9VWOb#BaMi!`AP{FGB@5ccJ1`Q?!T~@GSHRB?g z#pXgbI?d)n>@v;flaxR$9V4D(9`;;z9hO*jH*N+VAs*&hCLTAZ1rK<(y0J4b@G#jj z!32)7F{3Cr>SJ5avxmof(So$bmp>kGFkD*D!ZQcLe+uHeDKjuII6eS5BZ9^7{tp9F zPW2^uIV1l(0Pw15e!VJAqzT^1f2h!3`cxlBAU z5bj10H-@Wm4TuIsGblRN)`R>8$pfjn3}RgjYnh(vF@S1cPzndf?OG;PJ%+}`AcZSo zy-y$w#l$vxgOen6BpWip68;!kt(Y%BrEOwwRbTEn1FuPI<)=xB8K zzk$IN10_)GDrGS6Xf+mtEMJ)aBlY9|#zc^M3l7EP9}30-irc>{D1+2#a>#y|m;#bo z!P%Gw_tajdwaiPe{!bHg+{%;ZH27BmKf6@sS3(v0LAJwax{)F~m`5Nj-r3{8e z3%D8$Kx!7+{aE_sKR72fDuR@+;7ApyXK>IGl>Gqe>u54s3M#6DBxW!*nu4OQgR!Bp zRG~unq)ip1&4Q^>jp5(hC$TPCz>vD^|Mp}arArTZq1 W4u2RJ7$hdQs(s~Jn)m}E7zP07QF~NU=3fBwP|Mmh5|Lq^JZ#0Wz4hdoYZ-0nEf#H8n7rR457rO&n4D)~cxeN|S zA}P%O?cak$47%7IWV+ZLI2jli82*C*OBcJthfa0}#)uF{9|hGEUoHj)hRt`FO;~tR z*VRblvVufy=)K7rxC{gla>9P0H)82;N!F#fj>sbz4u(#YU& z;t+!a0}lfOLjwbY2jhSH3daBT90p(Pdm6sjdwlq6|9}7g|0@{(+uvaPZ~tGOfq{YP zzkLAHfBPJ!|MqK`{@Z_G`fu-Zgu&sA4x2-OE}H{`!WaAh|Np=L|NlSC#orkiSQvPi z|JzG2|Btgjpv2~oqRr;;|NsB{|NsBr53>6I|Ns093=9Q1%>V5L85kLa7#JBi82;Nc zFcjGzVE%7^h55hz4Lvpo29OvFNZg1)2TVKIFPX~V5W(`_eh$lj`#X~}Ih*Uhu>QAa zVEb=x!uH=jgYCcl1h)V7JJ|l)KVbWBzbb%%L4y6iy$bt(`v~^`_8Zv$+Z!GZTo`bG z!QqF(7yBOuU+h6%U|?Wy;86Ht&%ofoQ1IxNy@v{$!v`fc2Qx>8#^V1EI2am>z+~S4 z0}2cs91R_&VG{p0X8-5mYGllv9KvmHn*@^o82kUxLWYYm{}0CeKd_0hG3NgYj>cG! z3=dah43v%r(Xt=R92t0g_A)J6|GzPO@&#^#dUudG4_70YZnXd3<>FBA)zR(0gRy{v zlE7bfAHKUxXPJ4p*K#+yfRrLcc%&K~Kq4B9hDQIbiV6z8I;06WghKSNo@Lv#fMLUG zg+_Cb8n73vt#KYC7@P9HRubx2`;~cBh8H{&X4l;q%F#m7lhp4gG*kjBi z<;K9k!Kn<#MR@G5%$H%Y2vR;EjKKxfVY8 z*ZB0`0}ck+4~rCepNcRpuu`}a^|YJu#lagF4_*MNxbv^^E=0v4MVa<09Id6rj0f}oE!d^7u;X8SV-3hO*$-=`JzEZg#z7G0qEezg zkC0NL9@xCpZT}Y~n({CyC7LZ-a6@WU>el~@5^dKqHEM#)U8KmiV2xvA5Qtr`%e5kL z!5YU!rx+XkKmrREDa_GYn#g!i1LR_te~qRfQP~d+Iy{>e?AWz&MPj2XNJN(lBya;H zu;`XRqXS3`q*v-`EaO2*kY3Y&jcOoK*$+HijeH>1F$V?)hD8f@ELhmEbnSn!UrdV@ z)ZbXO@adZWYrK>c^^6qF6qJj(m5da143r*eD+wrVuxQelWRz$J@~IK1#D!>ny7Ir+ zFGeLrJ*7kcu_`{M2Da$Nf`tvL%m0gUF)1mUVOLw9Xn#x^WU`VXhu9}Z)gZ=$ul|CP z2K&Fp?|&a~FlaP_f)^Cl#{?M|R09|fKKi?tYa!#m#`hp;a8gB%5jPG7jfId1+NhLh z-^Rl5)Q9olRgj*qe;Xe`^gLx_T(scFf`tvKBCGyS09kM5$guF^-vbH^GiEg&n;a=5 zQ~&a>Lbt$#4ut~>44qXyOSwZEpZ;xV6=-8%VBq0Ud;n6rV$;M2e<#ck2z>B2pbMsU z6AvekghOZZ0R@H?MFBGy18*Wp7WGWwc4@r)x1mJkjM28RQV44|fmf;B0&WuM6CSLAk2&KFGKg91|bG)q+w5$He<^vl`cdl+56O zgm6QBx2u|j@WiVi!4;g1yZ$tEfqdJP$spz=5b&XdhmR+gr)JXv=0yu~8!v!rZ?Wqv z24L}8o;gtQQy_5%h~S|G98l4tAW@#VJTW}hAkBwBTpu`hABf8)R1eDD{BQYr5TluLp52Ey#qKy&A+%06W0}jC{(<7xq!k=z6XT%)74)Z}OF%)15t?8)7cJCj z{0>qt`vH`nCx$}RWrNizuoxgIUBKM<2C9^yzNX=eJ%a_f5KuGDlUZyoWTw+>F2pX= zY(7b;jhTVRlqZFUt(HxP$(HRHCj*Zt4@)j9kGs->2RxgPu`)0~n1|VzQKSz0*dAKI zy=ei4V-D3R zibzh8IfUkv31Fu{UE;>ffaH`3JclnWILxyLVzU#-=1U7oU@o!yU;luEVZt@R1MPwh zcNGloDqOfwvLIB@!BxS*p@c^VqRSMd>n;lK6;};k z7?cDRG!z>DfZ{-t10=Vl;fsC!;ggJ@Mi;nz=-`<68zfyngR^15mxc{rx6fkd?%1^c zZ~JcJ2@PK+Ecm*7h7R}4np@MYR2@156+ixO-^8NRj8;2(lQQId^a{>=tbN{l8)Nq756qD%3A1 zX6ReM;@d(JM861v>|G|VnuI6xB>fqoB(b;$x#TDbiG zf+dRpIhyFNNOrGA%RDVpL!D#Vw z_03Fex(tqG5FJLV_8VA$LenUPVJ}m_QiY}a{-+7a8g_vkG|1C2YR8Ob|Vz}3|o3-Bl*6nXdF1q-wOKfUmuhb#3GxFzB8fFXh5 zKQqJs{eS=e2i4X88UOw72UpoWMr)at9{bP3_4N9GNLxaKW8&BU^%Ew6961wI$7yg( z{PcgqB#_5va!lL-CB|9Pa>azCy4Z===N2Xg<~bmpf^ z|F30LUHqR%oQFl1#X!9|>FB=%_sI?pCGJdYp#HdO)qn0{9wr{)0;9?9%xrs^c%+_I z{8tlY;o*9k3-b0B=Kr9A=hK2Uj~4s~H3oU4*D^i*@PFyf|DcxjkN-<2Fie&amE?Z= zOZG#}C)p2*FMmyT5S2(@^-Dojpz!gp3ifiLU>>fbeI&S-AzC}{Cl)>P#!ohXFKtA2{tFaLzt+aqa_Jd>2F9#<92c-jA z#*GQT>br~$48DQ}8WKS&c(@wDbl~z|f0=#w?y{U^1qF3u5>zr8Op6%K{^jJ%5Tyhv z!a>z)+#DK2#AYz2W-vHhQ8-uymTvyl=m(Q#FaT>$O#^$k z2rOUotI_S(WK(hdfP!D3W)^3o%`ZsvsgtuY2Q0)f(cl-TJs$E4)^-Cadm<`fBljEQxSSin>^$Zhc3-EMrfH;Zg zfC9q}o{84KCfpU6X#Hz)w}g(F!LI{nK{@p#$3s1krWdAcZ@)8jt*J=mrUOaxHuf721Okx(yQQ;DQ;p@Ck^&gRAi^Ldh+t z&?~sm#=9V)72J(?em1NUXngXsp-aIY)FtI^d<>G=0g9;AApfld6qj4Wd zdIiVCr9V-d?R7sVdr6t9ocy_$YvIYCjfFoSa4;wy{prRCYOpIF`q{HcriX`nElXqF z&&i9WGy=DQ6mI|77za|Qv=G$);gRL(*~_+;S#|&aKUE!K4HHDpcuvgw*}hX*>?-3^ z4Teio?BL0zz6 zx<4Dw{+KK&tEQs}a+lK2#)BZUl@_wden>jT7_=ZheQU3nGSgBfhJ%tI6;eMNcm9~1 zEvr~B4EBJ)PX(<-3VM#B>p$@AoC!pE0JO8-~R#&6&krgy2Ea< zG$}GDEn-m65Ku~Fc>4Q)BjZm+29UN+rpA9iK*^9J%;SIRum6pIK)e|oiobtA`l(u) z96J~n{`}GS3*=y3t{yMYcpeCYhI~P>#lXPf@P~ncL140@_E)jg;2&TofMOets{x*@ B*Hi!i diff --git a/tools/sdk/include/bluedroid/alarm.h b/tools/sdk/include/bluedroid/alarm.h index 2e226ed2..35c0f466 100644 --- a/tools/sdk/include/bluedroid/alarm.h +++ b/tools/sdk/include/bluedroid/alarm.h @@ -35,7 +35,10 @@ typedef struct alarm_t { void *cb_data; } osi_alarm_t; +int osi_alarm_create_mux(void); +int osi_alarm_delete_mux(void); void osi_alarm_init(void); +void osi_alarm_deinit(void); // Creates a new alarm object. The returned object must be freed by calling // |alarm_free|. Returns NULL on failure. diff --git a/tools/sdk/include/bluedroid/bta_api.h b/tools/sdk/include/bluedroid/bta_api.h index 8e4b927a..241b32ee 100644 --- a/tools/sdk/include/bluedroid/bta_api.h +++ b/tools/sdk/include/bluedroid/bta_api.h @@ -1003,6 +1003,8 @@ typedef struct { tBTM_BLE_EVT_TYPE ble_evt_type; tBT_DEVICE_TYPE device_type; UINT8 flag; + UINT8 adv_data_len; + UINT8 scan_rsp_len; #endif } tBTA_DM_INQ_RES; diff --git a/tools/sdk/include/bluedroid/btm_api.h b/tools/sdk/include/bluedroid/btm_api.h index 2d1edcb6..4406217c 100644 --- a/tools/sdk/include/bluedroid/btm_api.h +++ b/tools/sdk/include/bluedroid/btm_api.h @@ -611,6 +611,8 @@ typedef struct { UINT8 ble_addr_type; tBTM_BLE_EVT_TYPE ble_evt_type; UINT8 flag; + UINT8 adv_data_len; + UINT8 scan_rsp_len; #endif } tBTM_INQ_RESULTS; diff --git a/tools/sdk/include/bluedroid/esp_gap_ble_api.h b/tools/sdk/include/bluedroid/esp_gap_ble_api.h index 8b5882d2..3456008b 100644 --- a/tools/sdk/include/bluedroid/esp_gap_ble_api.h +++ b/tools/sdk/include/bluedroid/esp_gap_ble_api.h @@ -273,6 +273,8 @@ typedef union { uint8_t ble_adv[ESP_BLE_ADV_DATA_LEN_MAX + ESP_BLE_SCAN_RSP_DATA_LEN_MAX]; /*!< Received EIR */ int flag; /*!< Advertising data flag bit */ int num_resps; /*!< Scan result number */ + uint8_t adv_data_len; /*!< Adv data length */ + uint8_t scan_rsp_len; /*!< Scan response length */ } scan_rst; /*!< Event parameter of ESP_GAP_BLE_SCAN_RESULT_EVT */ /** * @brief ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT diff --git a/tools/sdk/include/bluedroid/thread.h b/tools/sdk/include/bluedroid/thread.h index 01df9538..c148cef7 100644 --- a/tools/sdk/include/bluedroid/thread.h +++ b/tools/sdk/include/bluedroid/thread.h @@ -44,24 +44,24 @@ enum { }; #define HCI_HOST_TASK_STACK_SIZE (2048 + BT_TASK_EXTRA_STACK_SIZE) -#define HCI_HOST_TASK_PRIO (configMAX_PRIORITIES - 2) +#define HCI_HOST_TASK_PRIO (configMAX_PRIORITIES - 3) #define HCI_HOST_TASK_NAME "hciHostT" #define HCI_HOST_QUEUE_NUM 40 #define HCI_H4_TASK_STACK_SIZE (2048 + BT_TASK_EXTRA_STACK_SIZE) -#define HCI_H4_TASK_PRIO (configMAX_PRIORITIES - 3) +#define HCI_H4_TASK_PRIO (configMAX_PRIORITIES - 4) #define HCI_H4_TASK_NAME "hciH4T" #define HCI_H4_QUEUE_NUM 60 #define BTU_TASK_STACK_SIZE (3584 + BT_TASK_EXTRA_STACK_SIZE) -#define BTU_TASK_PRIO (configMAX_PRIORITIES - 4) +#define BTU_TASK_PRIO (configMAX_PRIORITIES - 5) #define BTU_TASK_NAME "btuT" #define BTU_QUEUE_NUM 50 #define BTC_TASK_STACK_SIZE (CONFIG_BTC_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE) //by menuconfig #define BTC_TASK_NAME "btcT" -#define BTC_TASK_PRIO (configMAX_PRIORITIES - 5) -#define BTC_TASK_QUEUE_NUM 20 +#define BTC_TASK_PRIO (configMAX_PRIORITIES - 6) +#define BTC_TASK_QUEUE_NUM 60 void btu_task_post(uint32_t sig); void hci_host_task_post(void); diff --git a/tools/sdk/include/bt/bt.h b/tools/sdk/include/bt/bt.h index e3bd7f08..5a244e0c 100644 --- a/tools/sdk/include/bt/bt.h +++ b/tools/sdk/include/bt/bt.h @@ -18,11 +18,44 @@ #include #include #include "esp_err.h" +#include "sdkconfig.h" #ifdef __cplusplus extern "C" { #endif +/** + * @brief Controller config options, depend on config mask. + * Config mask indicate which functions enabled, this means + * some options or parameters of some functions enabled by config mask. + */ +typedef struct { + uint8_t hci_uart_no; /*!< If use UART1/2 as HCI IO interface, indicate UART number */ + uint32_t hci_uart_baudrate; /*!< If use UART1/2 as HCI IO interface, indicate UART baudrate */ +} esp_bt_controller_config_t; + +#ifdef CONFIG_BT_ENABLED + +#ifdef CONFIG_BT_HCI_UART_NO +#define BT_HCI_UART_NO_DEFAULT CONFIG_BT_HCI_UART_NO +#else +#define BT_HCI_UART_NO_DEFAULT 1 +#endif /* BT_HCI_UART_NO_DEFAULT */ + +#ifdef CONFIG_BT_HCI_UART_BAUDRATE +#define BT_HCI_UART_BAUDRATE_DEFAULT CONFIG_BT_HCI_UART_BAUDRATE +#else +#define BT_HCI_UART_BAUDRATE_DEFAULT 921600 +#endif /* BT_HCI_UART_BAUDRATE_DEFAULT */ + +#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() { \ + .hci_uart_no = BT_HCI_UART_NO_DEFAULT,\ + .hci_uart_baudrate = BT_HCI_UART_BAUDRATE_DEFAULT,\ +}; +#else +#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {0}; _Static_assert(0, "please enable bluetooth in menuconfig to use bt.h"); +#endif + /** * @brief Bluetooth mode for controller enable/disable */ @@ -45,10 +78,11 @@ typedef enum { /** * @brief Initialize BT controller to allocate task and other resource. - * + * @param cfg: Initial configuration of BT controller. * This function should be called only once, before any other BT functions are called. + * @return ESP_OK - success, other - failed */ -void esp_bt_controller_init(void); +esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg); /** * @brief De-initialize BT controller to free resource and delete task. diff --git a/tools/sdk/include/config/sdkconfig.h b/tools/sdk/include/config/sdkconfig.h index 1a7afb67..f58bf8bb 100644 --- a/tools/sdk/include/config/sdkconfig.h +++ b/tools/sdk/include/config/sdkconfig.h @@ -46,6 +46,7 @@ #define CONFIG_LOG_DEFAULT_LEVEL_ERROR 1 #define CONFIG_MBEDTLS_MPI_USE_INTERRUPT 1 #define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE 1 +#define CONFIG_BTDM_CONTROLLER_RUN_CPU 0 #define CONFIG_FATFS_CODEPAGE_850 1 #define CONFIG_TASK_WDT 1 #define CONFIG_MAIN_TASK_STACK_SIZE 4096 @@ -74,7 +75,7 @@ #define CONFIG_FLASHMODE_QIO 1 #define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1 #define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 2048 -#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 0 +#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 1000 #define CONFIG_PHY_DATA_OFFSET 0xf000 #define CONFIG_PARTITION_TABLE_CUSTOM_APP_BIN_OFFSET 0x10000 #define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32 @@ -110,6 +111,7 @@ #define CONFIG_ESPTOOLPY_BAUD_921600B 1 #define CONFIG_APP_OFFSET 0x10000 #define CONFIG_MEMMAP_SMP 1 +#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 #define CONFIG_LWIP_SO_RCVBUF 1 #define CONFIG_MBEDTLS_HARDWARE_MPI 1 #define CONFIG_MONITOR_BAUD_OTHER_VAL 115200 diff --git a/tools/sdk/include/driver/driver/rmt.h b/tools/sdk/include/driver/driver/rmt.h index f5e82b4a..0a958688 100644 --- a/tools/sdk/include/driver/driver/rmt.h +++ b/tools/sdk/include/driver/driver/rmt.h @@ -564,7 +564,7 @@ esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_nu * - ESP_ERR_INVALID_ARG Parameter error * - ESP_OK Success */ -esp_err_t rmt_config(rmt_config_t* rmt_param); +esp_err_t rmt_config(const rmt_config_t* rmt_param); /** * @brief register RMT interrupt handler, the handler is an ISR. @@ -612,7 +612,7 @@ esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle); * - ESP_ERR_INVALID_ARG Parameter error * - ESP_OK Success */ -esp_err_t rmt_fill_tx_items(rmt_channel_t channel, rmt_item32_t* item, uint16_t item_num, uint16_t mem_offset); +esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t* item, uint16_t item_num, uint16_t mem_offset); /** * @brief Initialize RMT driver @@ -670,7 +670,7 @@ esp_err_t rmt_driver_uninstall(rmt_channel_t channel); * - ESP_ERR_INVALID_ARG Parameter error * - ESP_OK Success */ -esp_err_t rmt_write_items(rmt_channel_t channel, rmt_item32_t* rmt_item, int item_num, bool wait_tx_done); +esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t* rmt_item, int item_num, bool wait_tx_done); /** * @brief Wait RMT TX finished. diff --git a/tools/sdk/include/esp32/esp_err.h b/tools/sdk/include/esp32/esp_err.h index c7beafd3..2990c893 100644 --- a/tools/sdk/include/esp32/esp_err.h +++ b/tools/sdk/include/esp32/esp_err.h @@ -61,7 +61,10 @@ void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const cha * Disabled if assertions are disabled. */ #ifdef NDEBUG -#define ESP_ERROR_CHECK(x) do { (x); } while (0) +#define ESP_ERROR_CHECK(x) do { \ + esp_err_t rc = (x); \ + (void) sizeof(rc); \ + } while(0); #else #define ESP_ERROR_CHECK(x) do { \ esp_err_t rc = (x); \ diff --git a/tools/sdk/include/esp32/esp_panic.h b/tools/sdk/include/esp32/esp_panic.h index e9668fac..c9ee1409 100644 --- a/tools/sdk/include/esp32/esp_panic.h +++ b/tools/sdk/include/esp32/esp_panic.h @@ -61,6 +61,11 @@ esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags); void esp_clear_watchpoint(int no); +/** + * @brief Stops panic WDT + */ +void esp_panic_wdt_stop(void); + #endif #ifdef __cplusplus diff --git a/tools/sdk/include/esp32/esp_task.h b/tools/sdk/include/esp32/esp_task.h index bd263626..522067ca 100644 --- a/tools/sdk/include/esp32/esp_task.h +++ b/tools/sdk/include/esp32/esp_task.h @@ -33,7 +33,7 @@ /* Bt contoller Task */ /* controller */ -#define ESP_TASK_BT_CONTROLLER_PRIO (ESP_TASK_PRIO_MAX - 1) +#define ESP_TASK_BT_CONTROLLER_PRIO (ESP_TASK_PRIO_MAX - 2) #ifdef CONFIG_NEWLIB_NANO_FORMAT #define BT_TASK_EXTRA_STACK_SIZE (0) #else diff --git a/tools/sdk/include/esp32/rom/rtc.h b/tools/sdk/include/esp32/rom/rtc.h index 9bcd9bd7..9ea3126a 100644 --- a/tools/sdk/include/esp32/rom/rtc.h +++ b/tools/sdk/include/esp32/rom/rtc.h @@ -61,8 +61,11 @@ extern "C" { * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC ************************************************************************************* */ + #define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG #define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG +#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG +#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG #define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG diff --git a/tools/sdk/include/esp32/rom/spi_flash.h b/tools/sdk/include/esp32/rom/spi_flash.h index a9d617e7..bb2da748 100644 --- a/tools/sdk/include/esp32/rom/spi_flash.h +++ b/tools/sdk/include/esp32/rom/spi_flash.h @@ -65,81 +65,81 @@ extern "C" { ************************************************************* */ -#define PERIPHS_SPI_FLASH_CMD SPI_CMD(1) -#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR(1) -#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL(1) -#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1(1) -#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS(1) -#define PERIPHS_SPI_FLASH_USRREG SPI_USER(1) -#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1(1) -#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2(1) -#define PERIPHS_SPI_FLASH_C0 SPI_W0(1) -#define PERIPHS_SPI_FLASH_C1 SPI_W1(1) -#define PERIPHS_SPI_FLASH_C2 SPI_W2(1) -#define PERIPHS_SPI_FLASH_C3 SPI_W3(1) -#define PERIPHS_SPI_FLASH_C4 SPI_W4(1) -#define PERIPHS_SPI_FLASH_C5 SPI_W5(1) -#define PERIPHS_SPI_FLASH_C6 SPI_W6(1) -#define PERIPHS_SPI_FLASH_C7 SPI_W7(1) -#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC(1) +#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1) -#define SPI0_R_QIO_DUMMY_CYCLELEN 3 -#define SPI0_R_QIO_ADDR_BITSLEN 31 -#define SPI0_R_FAST_DUMMY_CYCLELEN 7 -#define SPI0_R_DIO_DUMMY_CYCLELEN 3 -#define SPI0_R_FAST_ADDR_BITSLEN 23 -#define SPI0_R_SIO_ADDR_BITSLEN 23 +#define SPI0_R_QIO_DUMMY_CYCLELEN 3 +#define SPI0_R_QIO_ADDR_BITSLEN 31 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 3 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 -#define SPI1_R_QIO_DUMMY_CYCLELEN 3 -#define SPI1_R_QIO_ADDR_BITSLEN 31 -#define SPI1_R_FAST_DUMMY_CYCLELEN 7 -#define SPI1_R_DIO_DUMMY_CYCLELEN 3 -#define SPI1_R_DIO_ADDR_BITSLEN 31 -#define SPI1_R_FAST_ADDR_BITSLEN 23 -#define SPI1_R_SIO_ADDR_BITSLEN 23 +#define SPI1_R_QIO_DUMMY_CYCLELEN 3 +#define SPI1_R_QIO_ADDR_BITSLEN 31 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 31 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 -#define SPI_W_SIO_ADDR_BITSLEN 23 +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 -#define TWO_BYTE_STATUS_EN SPI_WRSR_2B +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B //SPI address register -#define SPI_FLASH_BYTES_LEN 24 -#define SPI_BUFF_BYTE_WRITE_NUM 32 -#define SPI_BUFF_BYTE_READ_NUM 64 -#define SPI_BUFF_BYTE_READ_BITS 0x3f +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f //SPI status register -#define SPI_FLASH_BUSY_FLAG BIT0 -#define SPI_FLASH_WRENABLE_FLAG BIT1 -#define SPI_FLASH_BP0 BIT2 -#define SPI_FLASH_BP1 BIT3 -#define SPI_FLASH_BP2 BIT4 -#define FLASH_WR_PROTECT (SPI_FLASH_BP0|SPI_FLASH_BP1|SPI_FLASH_BP2) -#define SPI_FLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 typedef enum { - SPI_FLASH_QIO_MODE = 0, - SPI_FLASH_QOUT_MODE, - SPI_FLASH_DIO_MODE, - SPI_FLASH_DOUT_MODE, - SPI_FLASH_FASTRD_MODE, - SPI_FLASH_SLOWRD_MODE -} SpiFlashRdMode; + ESP_ROM_SPIFLASH_QIO_MODE = 0, + ESP_ROM_SPIFLASH_QOUT_MODE, + ESP_ROM_SPIFLASH_DIO_MODE, + ESP_ROM_SPIFLASH_DOUT_MODE, + ESP_ROM_SPIFLASH_FASTRD_MODE, + ESP_ROM_SPIFLASH_SLOWRD_MODE +} esp_rom_spiflash_read_mode_t; typedef enum { - SPI_FLASH_RESULT_OK, - SPI_FLASH_RESULT_ERR, - SPI_FLASH_RESULT_TIMEOUT -} SpiFlashOpResult; + ESP_ROM_SPIFLASH_RESULT_OK, + ESP_ROM_SPIFLASH_RESULT_ERR, + ESP_ROM_SPIFLASH_RESULT_TIMEOUT +} esp_rom_spiflash_result_t; typedef struct { - uint32_t deviceId; + uint32_t device_id; uint32_t chip_size; // chip size in bytes uint32_t block_size; uint32_t sector_size; uint32_t page_size; uint32_t status_mask; -} SpiFlashChip; +} esp_rom_spiflash_chip_t; typedef struct { uint8_t data_length; @@ -148,7 +148,7 @@ typedef struct { uint8_t write_cmd; uint16_t data_mask; uint16_t data; -} SpiCommonCmd; +} esp_rom_spiflash_common_cmd_t; /** * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. @@ -160,7 +160,7 @@ typedef struct { * * @return None */ -void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv); +void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); /** * @brief Select SPI Flash to QIO mode when WP pad is read from Flash. @@ -173,7 +173,7 @@ void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv); * * @return None */ -void SelectSpiQIO(uint8_t wp_gpio_num, uint32_t ishspi); +void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi); /** * @brief Set SPI Flash pad drivers. @@ -191,7 +191,7 @@ void SelectSpiQIO(uint8_t wp_gpio_num, uint32_t ishspi); * * @return None */ -void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); +void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); /** * @brief Select SPI Flash function for pads. @@ -202,7 +202,7 @@ void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); * * @return None */ -void SelectSpiFunction(uint32_t ishspi); +void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); /** * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. @@ -215,89 +215,89 @@ void SelectSpiFunction(uint32_t ishspi); * * @return None */ -void spi_flash_attach(uint32_t ishspi, bool legacy); +void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); /** * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). * Please do not call this function in SDK. * - * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file. + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. * * @param uint32_t *status : The pointer to which to return the Flash status value. * - * @return SPI_FLASH_RESULT_OK : read OK. - * SPI_FLASH_RESULT_ERR : read error. - * SPI_FLASH_RESULT_TIMEOUT : read timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. */ -SpiFlashOpResult SPI_read_status(SpiFlashChip *spi, uint32_t *status); +esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); /** * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). * Please do not call this function in SDK. * - * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file. + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. * * @param uint32_t *status : The pointer to which to return the Flash status value. * - * @return SPI_FLASH_RESULT_OK : read OK. - * SPI_FLASH_RESULT_ERR : read error. - * SPI_FLASH_RESULT_TIMEOUT : read timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. */ -SpiFlashOpResult SPI_read_status_high(uint32_t *status); +esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); /** * @brief Write status to Falsh status register. * Please do not call this function in SDK. * - * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file. + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. * * @param uint32_t status_value : Value to . * - * @return SPI_FLASH_RESULT_OK : write OK. - * SPI_FLASH_RESULT_ERR : write error. - * SPI_FLASH_RESULT_TIMEOUT : write timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. */ -SpiFlashOpResult SPI_write_status(SpiFlashChip *spi, uint32_t status_value); +esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); /** * @brief Use a command to Read Flash status register. * Please do not call this function in SDK. * - * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file. + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. * * @param uint32_t*status : The pointer to which to return the Flash status value. * - * @return SPI_FLASH_RESULT_OK : read OK. - * SPI_FLASH_RESULT_ERR : read error. - * SPI_FLASH_RESULT_TIMEOUT : read timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. */ -SpiFlashOpResult SPI_user_command_read(uint32_t *status, uint8_t cmd); +esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); /** * @brief Config SPI Flash read mode when init. * Please do not call this function in SDK. * - * @param SpiFlashRdMode mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. * * @param uint8_t legacy: In legacy mode, more SPI command is used in line. * - * @return SPI_FLASH_RESULT_OK : config OK. - * SPI_FLASH_RESULT_ERR : config error. - * SPI_FLASH_RESULT_TIMEOUT : config timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. */ -SpiFlashOpResult SPIReadModeCnfig(SpiFlashRdMode mode, bool legacy); +esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode, bool legacy); /** * @brief Config SPI Flash read mode when Flash is running in some mode. * Please do not call this function in SDK. * - * @param SpiFlashRdMode mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. * - * @return SPI_FLASH_RESULT_OK : config OK. - * SPI_FLASH_RESULT_ERR : config error. - * SPI_FLASH_RESULT_TIMEOUT : config timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. */ -SpiFlashOpResult SPIMasterReadModeCnfig(SpiFlashRdMode mode); +esp_rom_spiflash_result_t esp_rom_spiflash_master_config_readmode(esp_rom_spiflash_read_mode_t mode); /** * @brief Config SPI Flash clock divisor. @@ -307,23 +307,23 @@ SpiFlashOpResult SPIMasterReadModeCnfig(SpiFlashRdMode mode); * * @param uint8_t spi: 0 for SPI0, 1 for SPI1. * - * @return SPI_FLASH_RESULT_OK : config OK. - * SPI_FLASH_RESULT_ERR : config error. - * SPI_FLASH_RESULT_TIMEOUT : config timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. */ -SpiFlashOpResult SPIClkConfig(uint8_t freqdiv, uint8_t spi); +esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); /** * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. * Please do not call this function in SDK. * - * @param SpiCommonCmd *cmd : A struct to show the action of a command. + * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. * * @return uint16_t 0 : do not send command any more. * 1 : go to the next command. * n > 1 : skip (n - 1) commands. */ -uint16_t SPI_Common_Command(SpiCommonCmd *cmd); +uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); /** * @brief Unlock SPI write protect. @@ -331,11 +331,11 @@ uint16_t SPI_Common_Command(SpiCommonCmd *cmd); * * @param None. * - * @return SPI_FLASH_RESULT_OK : Unlock OK. - * SPI_FLASH_RESULT_ERR : Unlock error. - * SPI_FLASH_RESULT_TIMEOUT : Unlock timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. */ -SpiFlashOpResult SPIUnlock(void); +esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); /** * @brief SPI write protect. @@ -343,11 +343,11 @@ SpiFlashOpResult SPIUnlock(void); * * @param None. * - * @return SPI_FLASH_RESULT_OK : Lock OK. - * SPI_FLASH_RESULT_ERR : Lock error. - * SPI_FLASH_RESULT_TIMEOUT : Lock timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. */ -SpiFlashOpResult SPILock(void); +esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); /** * @brief Update SPI Flash parameter. @@ -365,11 +365,12 @@ SpiFlashOpResult SPILock(void); * * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). * - * @return SPI_FLASH_RESULT_OK : Update OK. - * SPI_FLASH_RESULT_ERR : Update error. - * SPI_FLASH_RESULT_TIMEOUT : Update timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. */ -SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask); +esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, + uint32_t sector_size, uint32_t page_size, uint32_t status_mask); /** * @brief Erase whole flash chip. @@ -377,11 +378,11 @@ SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t blo * * @param None * - * @return SPI_FLASH_RESULT_OK : Erase OK. - * SPI_FLASH_RESULT_ERR : Erase error. - * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. */ -SpiFlashOpResult SPIEraseChip(void); +esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); /** * @brief Erase a 64KB block of flash @@ -390,11 +391,11 @@ SpiFlashOpResult SPIEraseChip(void); * * @param uint32_t block_num : Which block to erase. * - * @return SPI_FLASH_RESULT_OK : Erase OK. - * SPI_FLASH_RESULT_ERR : Erase error. - * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. */ -SpiFlashOpResult SPIEraseBlock(uint32_t block_num); +esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); /** * @brief Erase a sector of flash. @@ -403,11 +404,11 @@ SpiFlashOpResult SPIEraseBlock(uint32_t block_num); * * @param uint32_t sector_num : Which sector to erase. * - * @return SPI_FLASH_RESULT_OK : Erase OK. - * SPI_FLASH_RESULT_ERR : Erase error. - * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. */ -SpiFlashOpResult SPIEraseSector(uint32_t sector_num); +esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); /** * @brief Erase some sectors. @@ -417,11 +418,11 @@ SpiFlashOpResult SPIEraseSector(uint32_t sector_num); * * @param uint32_t area_len : Length to erase, should be sector aligned. * - * @return SPI_FLASH_RESULT_OK : Erase OK. - * SPI_FLASH_RESULT_ERR : Erase error. - * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. */ -SpiFlashOpResult SPIEraseArea(uint32_t start_addr, uint32_t area_len); +esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); /** * @brief Write Data to Flash, you should Erase it yourself if need. @@ -433,11 +434,11 @@ SpiFlashOpResult SPIEraseArea(uint32_t start_addr, uint32_t area_len); * * @param uint32_t len : Length to write, should be 4 bytes aligned. * - * @return SPI_FLASH_RESULT_OK : Write OK. - * SPI_FLASH_RESULT_ERR : Write error. - * SPI_FLASH_RESULT_TIMEOUT : Write timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. */ -SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t *src, int32_t len); +esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); /** * @brief Read Data from Flash, you should Erase it yourself if need. @@ -449,11 +450,11 @@ SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t *src, int32_t len); * * @param uint32_t len : Length to read, should be 4 bytes aligned. * - * @return SPI_FLASH_RESULT_OK : Read OK. - * SPI_FLASH_RESULT_ERR : Read error. - * SPI_FLASH_RESULT_TIMEOUT : Read timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. */ -SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t *dest, int32_t len); +esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); /** * @brief SPI1 go into encrypto mode. @@ -463,7 +464,7 @@ SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t *dest, int32_t len); * * @return None */ -void SPI_Write_Encrypt_Enable(void); +void esp_rom_spiflash_write_encrypted_enable(void); /** * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. @@ -473,11 +474,11 @@ void SPI_Write_Encrypt_Enable(void); * * @param uint32_t *data : The pointer to data which is to write. * - * @return SPI_FLASH_RESULT_OK : Prepare OK. - * SPI_FLASH_RESULT_ERR : Prepare error. - * SPI_FLASH_RESULT_TIMEOUT : Prepare timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. */ -SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t *data); +esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); /** * @brief SPI1 go out of encrypto mode. @@ -487,7 +488,7 @@ SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t *data); * * @return None */ -void SPI_Write_Encrypt_Disable(void); +void esp_rom_spiflash_write_encrypted_disable(void); /** * @brief Write data to flash with transparent encryption. @@ -503,11 +504,11 @@ void SPI_Write_Encrypt_Disable(void); * * @param uint32_t len : Length to write, should be 32 bytes aligned. * - * @return SPI_FLASH_RESULT_OK : Data written successfully. - * SPI_FLASH_RESULT_ERR : Encryption write error. - * SPI_FLASH_RESULT_TIMEOUT : Encrypto write timeout. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. */ -SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t *data, uint32_t len); +esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); /** @brief Wait until SPI flash write operation is complete @@ -517,16 +518,16 @@ SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t *data, uint32_t * Reads the Write In Progress bit of the SPI flash status register, * repeats until this bit is zero (indicating write complete). * - * @return SPI_FLASH_RESULT_OK : Write is complete - * SPI_FLASH_RESULT_ERR : Error while reading status. + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. */ -SpiFlashOpResult SPI_Wait_Idle(SpiFlashChip *spi); +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); -/** @brief Global SpiFlashChip structure used by ROM functions +/** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions * */ -extern SpiFlashChip g_rom_flashchip; +extern esp_rom_spiflash_chip_t g_rom_flashchip; /** * @} diff --git a/tools/sdk/include/esp32/soc/bb_reg.h b/tools/sdk/include/esp32/soc/bb_reg.h deleted file mode 100755 index 0b52f66a..00000000 --- a/tools/sdk/include/esp32/soc/bb_reg.h +++ /dev/null @@ -1,102 +0,0 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _SOC_BB_REG_H_ -#define _SOC_BB_REG_H_ - -#define apb_bb_offset 0x6001c000 - -#define BB_DLY apb_bb_offset + 0x00009b00 // reg 00 -#define BB_TEST apb_bb_offset + 0x00009b08 // reg 02 -#define BB_TM1 apb_bb_offset + 0x00009b0c // reg 03 -#define BB_TM_CNTL apb_bb_offset + 0x00009b14 // reg 05 -#define BB_DEL_CNTL apb_bb_offset + 0x00009b28 // reg 10 -#define BB_PARAL_CNTL apb_bb_offset + 0x00009b2c // reg 11 -#define BB_FSM1 apb_bb_offset + 0x00009b44 // reg 17 -#define BB_MXG apb_bb_offset + 0x00009b48 // reg 18 -#define BB_MNOF apb_bb_offset + 0x00009b4c // reg 19 -#define BB_SIZE apb_bb_offset + 0x00009b50 // reg 20 -#define BB_TM3a apb_bb_offset + 0x00009b54 // reg 21 -#define BB_TM4a apb_bb_offset + 0x00009b58 // reg 22 -#define BB_GAIN apb_bb_offset + 0x00009b5c // reg 23 -#define BB_CNTL apb_bb_offset + 0x00009b60 // reg 24 -#define BB_CAD apb_bb_offset + 0x00009b64 // reg 25 -#define BB_DET apb_bb_offset + 0x00009b68 // reg 26 -#define BB_DETL apb_bb_offset + 0x00009b6c // reg 27 - -#define BB_MASK_PCLL apb_bb_offset + 0x00009d08 // reg 66 -#define BB_MASK_PCLH apb_bb_offset + 0x00009d0c // reg 67 -#define BB_RX_CTRL4 apb_bb_offset + 0x00009d10 // reg 68 -#define BB_RX_CTRL apb_bb_offset + 0x00009d1c // reg 71 -#define BB_RX_CTRL2 apb_bb_offset + 0x00009d20 // reg 72 -#define BB_RX_CTRL3 apb_bb_offset + 0x00009d24 // reg 73 -#define BB_DEL4 apb_bb_offset + 0x00009d40 // reg 80 -#define BB_TM5 apb_bb_offset + 0x00009d44 // reg 81 -#define BB_TM6 apb_bb_offset + 0x00009d48 // reg 82 -#define BB_PMCTRL apb_bb_offset + 0x00009d4c // reg 83 -#define BB_PWR apb_bb_offset + 0x00009d68 // reg 90 -#define BB_BCTRL2 apb_bb_offset + 0x00009d70 // reg 92 - -#define BB_MASK_PL apb_bb_offset + 0x00009884 // reg 97 -#define BB_MASK_PCHL apb_bb_offset + 0x00009888 // reg 98 -#define BB_MASK_PCHH apb_bb_offset + 0x0000988c // reg 99 - -#define BB_MASK_CL apb_bb_offset + 0x0000989c // reg 103 -#define BB_TONE apb_bb_offset + 0x000098a0 // reg 104 -#define BB_MASK_CH apb_bb_offset + 0x000098d4 // reg 117 -#define BB_SER apb_bb_offset + 0x000098ec // reg 123 -#define BB_GN_TB apb_bb_offset + 0x00009e00 // reg 128 - -#define BB_MODE apb_bb_offset + 0x00009c00 // reg 640 -#define BB_TXCTRL apb_bb_offset + 0x00009c04 // reg 641 -#define BB_BCTRL3 apb_bb_offset + 0x00009c08 // reg 642 -#define BB_BCTRL apb_bb_offset + 0x00009c28 // reg 650 -#define BB_SMCTRL apb_bb_offset + 0x00009c48 // reg 658 -#define BB_SMCTRL2 apb_bb_offset + 0x00009c4C // reg 659 -#define BB_TXCNT apb_bb_offset + 0x00009c58 // reg 662 -#define BB_RXCTRL apb_bb_offset + 0x00009c68 // reg 666 - -#define BB_TXGAIN apb_bb_offset + 0x00009900 // reg 704 - -#define BB_RXS_CNTL apb_bb_offset + 0x00009988 // reg 738 -#define BB_MASK2_PCLL apb_bb_offset + 0x000099a8 // reg 746 -#define BB_MASK2_PCLH apb_bb_offset + 0x000099ac // reg 747 -#define BB_MASK_PH apb_bb_offset + 0x000099b0 // reg 748 -#define BB_MASK2_PCHL apb_bb_offset + 0x000099b8 // reg 750 -#define BB_MASK2_PCHH apb_bb_offset + 0x000099bc // reg 751 -// -#define BB_TX_TONE_CNTL apb_bb_offset + 0x000099f0 // reg 764 -#define BB_ADD_CNTL0 apb_bb_offset + 0x00009a28 // reg 778 -#define BB_ADD_CNTL2 apb_bb_offset + 0x00009a2c // reg 779 -#define BB_GAIN_CNTL0 apb_bb_offset + 0x00009a34 // reg 781 -#define BB_GAIN_CNTL1 apb_bb_offset + 0x00009a38 // reg 782 -#define BB_GAIN_CNTL2 apb_bb_offset + 0x00009a3c // reg 783 -#define BB_AGCMEM_CTRL apb_bb_offset + 0x00009a68 // reg 794 - -#define BB_11B_RECORD apb_bb_offset + 0x00009808 // reg 802 -#define BB_FILTER_CNTL apb_bb_offset + 0x0000980c // reg 803 -#define BB_ANALOG_CTRL1 apb_bb_offset + 0x00009838 -#define BB_ANALOG_CTRL2 apb_bb_offset + 0x0000983c //reg 815 -#define BB_ANALOG_CTRL3 apb_bb_offset + 0x00009840 //reg 816 -#define BB_RFCFG_CTRL0 apb_bb_offset + 0x00009844 //reg 817 -#define BB_RFCFG_CTRL1 apb_bb_offset + 0x00009848 //reg 818 - -#define BB_ADD_CNTL1 apb_bb_offset + 0x00009860 //reg824 -#define BB_PA_CNTL apb_bb_offset + 0x00009864 //reg825 -#define BB_RFCFG_CTRL2 apb_bb_offset + 0x0000986c //reg827 -#define BB_RXDEL_CTRL apb_bb_offset + 0x00009d18 -#define BB_RXLENGTH_CTRL apb_bb_offset + 0x00009d1c - -#endif /* _SOC_BB_REG_H_ */ - diff --git a/tools/sdk/include/freertos/freertos/portmacro.h b/tools/sdk/include/freertos/freertos/portmacro.h index 7cae4b05..157b9156 100644 --- a/tools/sdk/include/freertos/freertos/portmacro.h +++ b/tools/sdk/include/freertos/freertos/portmacro.h @@ -79,6 +79,8 @@ extern "C" { #include #include /* required for XSHAL_CLIB */ #include +#include "esp_crosscore_int.h" + //#include "xtensa_context.h" @@ -261,6 +263,18 @@ void vPortYield( void ); void _frxt_setup_switch( void ); #define portYIELD() vPortYield() #define portYIELD_FROM_ISR() _frxt_setup_switch() + +static inline uint32_t xPortGetCoreID(); + +/* Yielding within an API call (when interrupts are off), means the yield should be delayed + until interrupts are re-enabled. + + To do this, we use the "cross-core" interrupt as a trigger to yield on this core when interrupts are re-enabled.This + is the same interrupt & code path which is used to trigger a yield between CPUs, although in this case the yield is + happening on the same CPU. +*/ +#define portYIELD_WITHIN_API() esp_crosscore_int_send_yield(xPortGetCoreID()) + /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ diff --git a/tools/sdk/include/mdns/mdns.h b/tools/sdk/include/mdns/mdns.h index 58e588e3..c0855466 100644 --- a/tools/sdk/include/mdns/mdns.h +++ b/tools/sdk/include/mdns/mdns.h @@ -18,7 +18,11 @@ extern "C" { #endif +#ifndef MDNS_TEST_MODE #include +#else +#include "esp32_compat.h" +#endif struct mdns_server_s; typedef struct mdns_server_s mdns_server_t; diff --git a/tools/sdk/include/esp32/esp_brownout.h b/tools/sdk/include/soc/esp_brownout.h similarity index 100% rename from tools/sdk/include/esp32/esp_brownout.h rename to tools/sdk/include/soc/esp_brownout.h diff --git a/tools/sdk/include/soc/soc/apb_ctrl_reg.h b/tools/sdk/include/soc/soc/apb_ctrl_reg.h new file mode 100644 index 00000000..2e5ea54c --- /dev/null +++ b/tools/sdk/include/soc/soc/apb_ctrl_reg.h @@ -0,0 +1,294 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_CTRL_REG_H_ +#define _SOC_APB_CTRL_REG_H_ + +#include "soc.h" +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) +/* APB_CTRL_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_QUICK_CLK_CHNG (BIT(13)) +#define APB_CTRL_QUICK_CLK_CHNG_M (BIT(13)) +#define APB_CTRL_QUICK_CLK_CHNG_V 0x1 +#define APB_CTRL_QUICK_CLK_CHNG_S 13 +/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_RST_TICK_CNT (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_M (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_V 0x1 +#define APB_CTRL_RST_TICK_CNT_S 12 +/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_EN (BIT(11)) +#define APB_CTRL_CLK_EN_M (BIT(11)) +#define APB_CTRL_CLK_EN_V 0x1 +#define APB_CTRL_CLK_EN_S 11 +/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_320M_EN (BIT(10)) +#define APB_CTRL_CLK_320M_EN_M (BIT(10)) +#define APB_CTRL_CLK_320M_EN_V 0x1 +#define APB_CTRL_CLK_320M_EN_S 10 +/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define APB_CTRL_PRE_DIV_CNT 0x000003FF +#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S)) +#define APB_CTRL_PRE_DIV_CNT_V 0x3FF +#define APB_CTRL_PRE_DIV_CNT_S 0 + +#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) +/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ +/*description: */ +#define APB_CTRL_XTAL_TICK_NUM 0x000000FF +#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S)) +#define APB_CTRL_XTAL_TICK_NUM_V 0xFF +#define APB_CTRL_XTAL_TICK_NUM_S 0 + +#define APB_CTRL_PLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x8) +/* APB_CTRL_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */ +/*description: */ +#define APB_CTRL_PLL_TICK_NUM 0x000000FF +#define APB_CTRL_PLL_TICK_NUM_M ((APB_CTRL_PLL_TICK_NUM_V)<<(APB_CTRL_PLL_TICK_NUM_S)) +#define APB_CTRL_PLL_TICK_NUM_V 0xFF +#define APB_CTRL_PLL_TICK_NUM_S 0 + +#define APB_CTRL_CK8M_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0xC) +/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */ +/*description: */ +#define APB_CTRL_CK8M_TICK_NUM 0x000000FF +#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S)) +#define APB_CTRL_CK8M_TICK_NUM_V 0xFF +#define APB_CTRL_CK8M_TICK_NUM_S 0 + +#define APB_CTRL_APB_SARADC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x10) +/* APB_CTRL_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data + is from GPIO matrix*/ +#define APB_CTRL_SARADC_DATA_TO_I2S (BIT(26)) +#define APB_CTRL_SARADC_DATA_TO_I2S_M (BIT(26)) +#define APB_CTRL_SARADC_DATA_TO_I2S_V 0x1 +#define APB_CTRL_SARADC_DATA_TO_I2S_S 26 +/* APB_CTRL_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data + in this case the resolution should not be larger than 11 bits.*/ +#define APB_CTRL_SARADC_DATA_SAR_SEL (BIT(25)) +#define APB_CTRL_SARADC_DATA_SAR_SEL_M (BIT(25)) +#define APB_CTRL_SARADC_DATA_SAR_SEL_V 0x1 +#define APB_CTRL_SARADC_DATA_SAR_SEL_S 25 +/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V 0x1 +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S 24 +/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V 0x1 +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S 23 +/* APB_CTRL_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_CTRL_SARADC_SAR2_PATT_LEN 0x0000000F +#define APB_CTRL_SARADC_SAR2_PATT_LEN_M ((APB_CTRL_SARADC_SAR2_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR2_PATT_LEN_S)) +#define APB_CTRL_SARADC_SAR2_PATT_LEN_V 0xF +#define APB_CTRL_SARADC_SAR2_PATT_LEN_S 19 +/* APB_CTRL_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_CTRL_SARADC_SAR1_PATT_LEN 0x0000000F +#define APB_CTRL_SARADC_SAR1_PATT_LEN_M ((APB_CTRL_SARADC_SAR1_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR1_PATT_LEN_S)) +#define APB_CTRL_SARADC_SAR1_PATT_LEN_V 0xF +#define APB_CTRL_SARADC_SAR1_PATT_LEN_S 15 +/* APB_CTRL_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ +/*description: SAR clock divider*/ +#define APB_CTRL_SARADC_SAR_CLK_DIV 0x000000FF +#define APB_CTRL_SARADC_SAR_CLK_DIV_M ((APB_CTRL_SARADC_SAR_CLK_DIV_V)<<(APB_CTRL_SARADC_SAR_CLK_DIV_S)) +#define APB_CTRL_SARADC_SAR_CLK_DIV_V 0xFF +#define APB_CTRL_SARADC_SAR_CLK_DIV_S 7 +/* APB_CTRL_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_CTRL_SARADC_SAR_CLK_GATED_M (BIT(6)) +#define APB_CTRL_SARADC_SAR_CLK_GATED_V 0x1 +#define APB_CTRL_SARADC_SAR_CLK_GATED_S 6 +/* APB_CTRL_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ +#define APB_CTRL_SARADC_SAR_SEL (BIT(5)) +#define APB_CTRL_SARADC_SAR_SEL_M (BIT(5)) +#define APB_CTRL_SARADC_SAR_SEL_V 0x1 +#define APB_CTRL_SARADC_SAR_SEL_S 5 +/* APB_CTRL_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: single mode 1: double mode 2: alternate mode*/ +#define APB_CTRL_SARADC_WORK_MODE 0x00000003 +#define APB_CTRL_SARADC_WORK_MODE_M ((APB_CTRL_SARADC_WORK_MODE_V)<<(APB_CTRL_SARADC_WORK_MODE_S)) +#define APB_CTRL_SARADC_WORK_MODE_V 0x3 +#define APB_CTRL_SARADC_WORK_MODE_S 3 +/* APB_CTRL_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled + by PWDET CTRL*/ +#define APB_CTRL_SARADC_SAR2_MUX (BIT(2)) +#define APB_CTRL_SARADC_SAR2_MUX_M (BIT(2)) +#define APB_CTRL_SARADC_SAR2_MUX_V 0x1 +#define APB_CTRL_SARADC_SAR2_MUX_S 2 +/* APB_CTRL_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_START (BIT(1)) +#define APB_CTRL_SARADC_START_M (BIT(1)) +#define APB_CTRL_SARADC_START_V 0x1 +#define APB_CTRL_SARADC_START_S 1 +/* APB_CTRL_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_START_FORCE (BIT(0)) +#define APB_CTRL_SARADC_START_FORCE_M (BIT(0)) +#define APB_CTRL_SARADC_START_FORCE_V 0x1 +#define APB_CTRL_SARADC_START_FORCE_S 0 + +#define APB_CTRL_APB_SARADC_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0x14) +/* APB_CTRL_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ +#define APB_CTRL_SARADC_SAR2_INV (BIT(10)) +#define APB_CTRL_SARADC_SAR2_INV_M (BIT(10)) +#define APB_CTRL_SARADC_SAR2_INV_V 0x1 +#define APB_CTRL_SARADC_SAR2_INV_S 10 +/* APB_CTRL_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ +#define APB_CTRL_SARADC_SAR1_INV (BIT(9)) +#define APB_CTRL_SARADC_SAR1_INV_M (BIT(9)) +#define APB_CTRL_SARADC_SAR1_INV_V 0x1 +#define APB_CTRL_SARADC_SAR1_INV_S 9 +/* APB_CTRL_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ +/*description: max conversion number*/ +#define APB_CTRL_SARADC_MAX_MEAS_NUM 0x000000FF +#define APB_CTRL_SARADC_MAX_MEAS_NUM_M ((APB_CTRL_SARADC_MAX_MEAS_NUM_V)<<(APB_CTRL_SARADC_MAX_MEAS_NUM_S)) +#define APB_CTRL_SARADC_MAX_MEAS_NUM_V 0xFF +#define APB_CTRL_SARADC_MAX_MEAS_NUM_S 1 +/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V 0x1 +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S 0 + +#define APB_CTRL_APB_SARADC_FSM_REG (DR_REG_APB_CTRL_BASE + 0x18) +/* APB_CTRL_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */ +/*description: sample cycles*/ +#define APB_CTRL_SARADC_SAMPLE_CYCLE 0x000000FF +#define APB_CTRL_SARADC_SAMPLE_CYCLE_M ((APB_CTRL_SARADC_SAMPLE_CYCLE_V)<<(APB_CTRL_SARADC_SAMPLE_CYCLE_S)) +#define APB_CTRL_SARADC_SAMPLE_CYCLE_V 0xFF +#define APB_CTRL_SARADC_SAMPLE_CYCLE_S 24 +/* APB_CTRL_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */ +/*description: */ +#define APB_CTRL_SARADC_START_WAIT 0x000000FF +#define APB_CTRL_SARADC_START_WAIT_M ((APB_CTRL_SARADC_START_WAIT_V)<<(APB_CTRL_SARADC_START_WAIT_S)) +#define APB_CTRL_SARADC_START_WAIT_V 0xFF +#define APB_CTRL_SARADC_START_WAIT_S 16 +/* APB_CTRL_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */ +/*description: */ +#define APB_CTRL_SARADC_STANDBY_WAIT 0x000000FF +#define APB_CTRL_SARADC_STANDBY_WAIT_M ((APB_CTRL_SARADC_STANDBY_WAIT_V)<<(APB_CTRL_SARADC_STANDBY_WAIT_S)) +#define APB_CTRL_SARADC_STANDBY_WAIT_V 0xFF +#define APB_CTRL_SARADC_STANDBY_WAIT_S 8 +/* APB_CTRL_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ +/*description: */ +#define APB_CTRL_SARADC_RSTB_WAIT 0x000000FF +#define APB_CTRL_SARADC_RSTB_WAIT_M ((APB_CTRL_SARADC_RSTB_WAIT_V)<<(APB_CTRL_SARADC_RSTB_WAIT_S)) +#define APB_CTRL_SARADC_RSTB_WAIT_V 0xFF +#define APB_CTRL_SARADC_RSTB_WAIT_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x1C) +/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M ((APB_CTRL_SARADC_SAR1_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB1_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x20) +/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M ((APB_CTRL_SARADC_SAR1_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB2_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x24) +/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M ((APB_CTRL_SARADC_SAR1_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB3_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x28) +/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M ((APB_CTRL_SARADC_SAR1_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB4_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x2C) +/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M ((APB_CTRL_SARADC_SAR2_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB1_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x30) +/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M ((APB_CTRL_SARADC_SAR2_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB2_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x34) +/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M ((APB_CTRL_SARADC_SAR2_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB3_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x38) +/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M ((APB_CTRL_SARADC_SAR2_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB4_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S 0 + +#define APB_CTRL_APLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x3C) +/* APB_CTRL_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */ +/*description: */ +#define APB_CTRL_APLL_TICK_NUM 0x000000FF +#define APB_CTRL_APLL_TICK_NUM_M ((APB_CTRL_APLL_TICK_NUM_V)<<(APB_CTRL_APLL_TICK_NUM_S)) +#define APB_CTRL_APLL_TICK_NUM_V 0xFF +#define APB_CTRL_APLL_TICK_NUM_S 0 + +#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x7C) +/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ +/*description: */ +#define APB_CTRL_DATE 0xFFFFFFFF +#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S)) +#define APB_CTRL_DATE_V 0xFFFFFFFF +#define APB_CTRL_DATE_S 0 + + + + +#endif /*_SOC_APB_CTRL_REG_H_ */ + + diff --git a/tools/sdk/include/soc/soc/apb_ctrl_struct.h b/tools/sdk/include/soc/soc/apb_ctrl_struct.h new file mode 100644 index 00000000..d2596783 --- /dev/null +++ b/tools/sdk/include/soc/soc/apb_ctrl_struct.h @@ -0,0 +1,120 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_CTRL_STRUCT_H_ +#define _SOC_APB_CTRL_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t pre_div: 10; + volatile uint32_t clk_320m_en: 1; + volatile uint32_t clk_en: 1; + volatile uint32_t rst_tick: 1; + volatile uint32_t quick_clk_chng: 1; + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }clk_conf; + union { + struct { + volatile uint32_t xtal_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }xtal_tick_conf; + union { + struct { + volatile uint32_t pll_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }pll_tick_conf; + union { + struct { + volatile uint32_t ck8m_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }ck8m_tick_conf; + union { + struct { + volatile uint32_t start_force: 1; + volatile uint32_t start: 1; + volatile uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/ + volatile uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ + volatile uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ + volatile uint32_t sar_clk_gated: 1; + volatile uint32_t sar_clk_div: 8; /*SAR clock divider*/ + volatile uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + volatile uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + volatile uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ + volatile uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ + volatile uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ + volatile uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ + volatile uint32_t reserved27: 5; + }; + volatile uint32_t val; + }saradc_ctrl; + union { + struct { + volatile uint32_t meas_num_limit: 1; + volatile uint32_t max_meas_num: 8; /*max conversion number*/ + volatile uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ + volatile uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ + volatile uint32_t reserved11: 21; + }; + volatile uint32_t val; + }saradc_ctrl2; + union { + struct { + volatile uint32_t rstb_wait: 8; + volatile uint32_t standby_wait: 8; + volatile uint32_t start_wait: 8; + volatile uint32_t sample_cycle: 8; /*sample cycles*/ + }; + volatile uint32_t val; + }saradc_fsm; + volatile uint32_t saradc_sar1_patt_tab1; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/ + union { + struct { + volatile uint32_t apll_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }apll_tick_conf; + volatile uint32_t reserved_40; + volatile uint32_t reserved_44; + volatile uint32_t reserved_48; + volatile uint32_t reserved_4c; + volatile uint32_t reserved_50; + volatile uint32_t reserved_54; + volatile uint32_t reserved_58; + volatile uint32_t reserved_5c; + volatile uint32_t reserved_60; + volatile uint32_t reserved_64; + volatile uint32_t reserved_68; + volatile uint32_t reserved_6c; + volatile uint32_t reserved_70; + volatile uint32_t reserved_74; + volatile uint32_t reserved_78; + volatile uint32_t date; /**/ +} apb_ctrl_dev_t; + +#endif /* _SOC_APB_CTRL_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/soc/bb_reg.h b/tools/sdk/include/soc/soc/bb_reg.h new file mode 100644 index 00000000..fca84deb --- /dev/null +++ b/tools/sdk/include/soc/soc/bb_reg.h @@ -0,0 +1,34 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_BB_REG_H_ +#define _SOC_BB_REG_H_ + +/* Some of the baseband control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054) +#define BB_FFT_FORCE_PU (BIT(3)) +#define BB_FFT_FORCE_PU_S 3 +#define BB_FFT_FORCE_PD (BIT(2)) +#define BB_FFT_FORCE_PD_S 2 +#define BB_DC_EST_FORCE_PU (BIT(1)) +#define BB_DC_EST_FORCE_PU_S 1 +#define BB_DC_EST_FORCE_PD (BIT(0)) +#define BB_DC_EST_FORCE_PD_S 0 + + +#endif /* _SOC_BB_REG_H_ */ + diff --git a/tools/sdk/include/esp32/soc/boot_mode.h b/tools/sdk/include/soc/soc/boot_mode.h old mode 100755 new mode 100644 similarity index 100% rename from tools/sdk/include/esp32/soc/boot_mode.h rename to tools/sdk/include/soc/soc/boot_mode.h diff --git a/tools/sdk/include/esp32/soc/cpu.h b/tools/sdk/include/soc/soc/cpu.h similarity index 100% rename from tools/sdk/include/esp32/soc/cpu.h rename to tools/sdk/include/soc/soc/cpu.h diff --git a/tools/sdk/include/esp32/soc/dport_reg.h b/tools/sdk/include/soc/soc/dport_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/dport_reg.h rename to tools/sdk/include/soc/soc/dport_reg.h diff --git a/tools/sdk/include/esp32/soc/efuse_reg.h b/tools/sdk/include/soc/soc/efuse_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/efuse_reg.h rename to tools/sdk/include/soc/soc/efuse_reg.h diff --git a/tools/sdk/include/esp32/soc/emac_ex_reg.h b/tools/sdk/include/soc/soc/emac_ex_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/emac_ex_reg.h rename to tools/sdk/include/soc/soc/emac_ex_reg.h diff --git a/tools/sdk/include/esp32/soc/emac_reg_v2.h b/tools/sdk/include/soc/soc/emac_reg_v2.h similarity index 100% rename from tools/sdk/include/esp32/soc/emac_reg_v2.h rename to tools/sdk/include/soc/soc/emac_reg_v2.h diff --git a/tools/sdk/include/soc/soc/fe_reg.h b/tools/sdk/include/soc/soc/fe_reg.h new file mode 100644 index 00000000..f8c2ce58 --- /dev/null +++ b/tools/sdk/include/soc/soc/fe_reg.h @@ -0,0 +1,33 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" + +/* Some of the RF frontend control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090) +#define FE_IQ_EST_FORCE_PU (BIT(5)) +#define FE_IQ_EST_FORCE_PU_S 5 +#define FE_IQ_EST_FORCE_PD (BIT(4)) +#define FE_IQ_EST_FORCE_PD_S 4 + +#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0) +#define FE2_TX_INF_FORCE_PU (BIT(10)) +#define FE2_TX_INF_FORCE_PU_S 10 +#define FE2_TX_INF_FORCE_PD (BIT(9)) +#define FE2_TX_INF_FORCE_PD_S 9 diff --git a/tools/sdk/include/esp32/soc/frc_timer_reg.h b/tools/sdk/include/soc/soc/frc_timer_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/frc_timer_reg.h rename to tools/sdk/include/soc/soc/frc_timer_reg.h diff --git a/tools/sdk/include/esp32/soc/gpio_reg.h b/tools/sdk/include/soc/soc/gpio_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/gpio_reg.h rename to tools/sdk/include/soc/soc/gpio_reg.h diff --git a/tools/sdk/include/esp32/soc/gpio_sd_reg.h b/tools/sdk/include/soc/soc/gpio_sd_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/gpio_sd_reg.h rename to tools/sdk/include/soc/soc/gpio_sd_reg.h diff --git a/tools/sdk/include/esp32/soc/gpio_sd_struct.h b/tools/sdk/include/soc/soc/gpio_sd_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/gpio_sd_struct.h rename to tools/sdk/include/soc/soc/gpio_sd_struct.h diff --git a/tools/sdk/include/esp32/soc/gpio_sig_map.h b/tools/sdk/include/soc/soc/gpio_sig_map.h similarity index 100% rename from tools/sdk/include/esp32/soc/gpio_sig_map.h rename to tools/sdk/include/soc/soc/gpio_sig_map.h diff --git a/tools/sdk/include/esp32/soc/gpio_struct.h b/tools/sdk/include/soc/soc/gpio_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/gpio_struct.h rename to tools/sdk/include/soc/soc/gpio_struct.h diff --git a/tools/sdk/include/esp32/soc/hwcrypto_reg.h b/tools/sdk/include/soc/soc/hwcrypto_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/hwcrypto_reg.h rename to tools/sdk/include/soc/soc/hwcrypto_reg.h diff --git a/tools/sdk/include/esp32/soc/i2c_reg.h b/tools/sdk/include/soc/soc/i2c_reg.h similarity index 98% rename from tools/sdk/include/esp32/soc/i2c_reg.h rename to tools/sdk/include/soc/soc/i2c_reg.h index 9693ca5b..292695eb 100644 --- a/tools/sdk/include/esp32/soc/i2c_reg.h +++ b/tools/sdk/include/soc/soc/i2c_reg.h @@ -1,951 +1,951 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_I2C_REG_H_ -#define _SOC_I2C_REG_H_ - - -#include "soc.h" - -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) - -#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000) -/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This register is used to configure the low level width of SCL clock.*/ -#define I2C_SCL_LOW_PERIOD 0x00003FFF -#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) -#define I2C_SCL_LOW_PERIOD_V 0x3FFF -#define I2C_SCL_LOW_PERIOD_S 0 - -#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004) -/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This is the clock gating control bit for reading or writing registers.*/ -#define I2C_CLK_EN (BIT(8)) -#define I2C_CLK_EN_M (BIT(8)) -#define I2C_CLK_EN_V 0x1 -#define I2C_CLK_EN_S 8 -/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: This bit is used to control the storage mode for received datas. - 1: receive data from most significant bit 0: receive data from least significant bit*/ -#define I2C_RX_LSB_FIRST (BIT(7)) -#define I2C_RX_LSB_FIRST_M (BIT(7)) -#define I2C_RX_LSB_FIRST_V 0x1 -#define I2C_RX_LSB_FIRST_S 7 -/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This bit is used to control the sending mode for data need to - be send. 1: receive data from most significant bit 0: receive data from least significant bit*/ -#define I2C_TX_LSB_FIRST (BIT(6)) -#define I2C_TX_LSB_FIRST_M (BIT(6)) -#define I2C_TX_LSB_FIRST_V 0x1 -#define I2C_TX_LSB_FIRST_S 6 -/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to start sending data in txfifo.*/ -#define I2C_TRANS_START (BIT(5)) -#define I2C_TRANS_START_M (BIT(5)) -#define I2C_TRANS_START_V 0x1 -#define I2C_TRANS_START_S 5 -/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to configure the module as i2c master clear this - bit to configure the module as i2c slave.*/ -#define I2C_MS_MODE (BIT(4)) -#define I2C_MS_MODE_M (BIT(4)) -#define I2C_MS_MODE_V 0x1 -#define I2C_MS_MODE_S 4 -/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to sample data in SCL low level. clear this bit - to sample data in SCL high level.*/ -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_V 0x1 -#define I2C_SAMPLE_SCL_LEVEL_S 2 -/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: 1: normally ouput scl clock 0: exchange the function of scl_o - and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ -#define I2C_SCL_FORCE_OUT (BIT(1)) -#define I2C_SCL_FORCE_OUT_M (BIT(1)) -#define I2C_SCL_FORCE_OUT_V 0x1 -#define I2C_SCL_FORCE_OUT_S 1 -/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: 1: normally ouput sda data 0: exchange the function of sda_o - and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ -#define I2C_SDA_FORCE_OUT (BIT(0)) -#define I2C_SDA_FORCE_OUT_M (BIT(0)) -#define I2C_SDA_FORCE_OUT_V 0x1 -#define I2C_SDA_FORCE_OUT_S 0 - -#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008) -/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: This register stores the value of state machine to produce SCL. - 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ -#define I2C_SCL_STATE_LAST 0x00000007 -#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) -#define I2C_SCL_STATE_LAST_V 0x7 -#define I2C_SCL_STATE_LAST_S 28 -/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: This register stores the value of state machine for i2c module. - 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007 -#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) -#define I2C_SCL_MAIN_STATE_LAST_V 0x7 -#define I2C_SCL_MAIN_STATE_LAST_S 24 -/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ -/*description: This register stores the amount of received data in ram.*/ -#define I2C_TXFIFO_CNT 0x0000003F -#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) -#define I2C_TXFIFO_CNT_V 0x3F -#define I2C_TXFIFO_CNT_S 18 -/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ -/*description: This register represent the amount of data need to send.*/ -#define I2C_RXFIFO_CNT 0x0000003F -#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) -#define I2C_RXFIFO_CNT_V 0x3F -#define I2C_RXFIFO_CNT_S 8 -/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This register changes to high level when one byte is transferred.*/ -#define I2C_BYTE_TRANS (BIT(6)) -#define I2C_BYTE_TRANS_M (BIT(6)) -#define I2C_BYTE_TRANS_V 0x1 -#define I2C_BYTE_TRANS_S 6 -/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: when configured as i2c slave and the address send by master - is equal to slave's address then this bit will be high level.*/ -#define I2C_SLAVE_ADDRESSED (BIT(5)) -#define I2C_SLAVE_ADDRESSED_M (BIT(5)) -#define I2C_SLAVE_ADDRESSED_V 0x1 -#define I2C_SLAVE_ADDRESSED_S 5 -/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ -#define I2C_BUS_BUSY (BIT(4)) -#define I2C_BUS_BUSY_M (BIT(4)) -#define I2C_BUS_BUSY_V 0x1 -#define I2C_BUS_BUSY_S 4 -/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: when I2C lost control of SDA line this register changes to high level.*/ -#define I2C_ARB_LOST (BIT(3)) -#define I2C_ARB_LOST_M (BIT(3)) -#define I2C_ARB_LOST_V 0x1 -#define I2C_ARB_LOST_S 3 -/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: when I2C takes more than time_out_reg clocks to receive a data - then this register changes to high level.*/ -#define I2C_TIME_OUT (BIT(2)) -#define I2C_TIME_OUT_M (BIT(2)) -#define I2C_TIME_OUT_V 0x1 -#define I2C_TIME_OUT_S 2 -/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: when in slave mode 1: master read slave 0: master write slave.*/ -#define I2C_SLAVE_RW (BIT(1)) -#define I2C_SLAVE_RW_M (BIT(1)) -#define I2C_SLAVE_RW_V 0x1 -#define I2C_SLAVE_RW_S 1 -/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This register stores the value of ACK bit.*/ -#define I2C_ACK_REC (BIT(0)) -#define I2C_ACK_REC_M (BIT(0)) -#define I2C_ACK_REC_V 0x1 -#define I2C_ACK_REC_S 0 - -#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c) -/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: This register is used to configure the max clock number of receiving a data.*/ -#define I2C_TIME_OUT_REG 0x000FFFFF -#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S)) -#define I2C_TIME_OUT_REG_V 0xFFFFF -#define I2C_TIME_OUT_REG_S 0 - -#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010) -/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: This register is used to enable slave 10bit address mode.*/ -#define I2C_ADDR_10BIT_EN (BIT(31)) -#define I2C_ADDR_10BIT_EN_M (BIT(31)) -#define I2C_ADDR_10BIT_EN_V 0x1 -#define I2C_ADDR_10BIT_EN_S 31 -/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ -/*description: when configured as i2c slave this register is used to configure - slave's address.*/ -#define I2C_SLAVE_ADDR 0x00007FFF -#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) -#define I2C_SLAVE_ADDR_V 0x7FFF -#define I2C_SLAVE_ADDR_S 0 - -#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) -/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ -/*description: This is the offset address of the last sending data as described - in nonfifo_tx_thres register.*/ -#define I2C_TXFIFO_END_ADDR 0x0000001F -#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S)) -#define I2C_TXFIFO_END_ADDR_V 0x1F -#define I2C_TXFIFO_END_ADDR_S 15 -/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: This is the offset address of the first sending data as described - in nonfifo_tx_thres register.*/ -#define I2C_TXFIFO_START_ADDR 0x0000001F -#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S)) -#define I2C_TXFIFO_START_ADDR_V 0x1F -#define I2C_TXFIFO_START_ADDR_S 10 -/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: This is the offset address of the first receiving data as described - in nonfifo_rx_thres_register.*/ -#define I2C_RXFIFO_END_ADDR 0x0000001F -#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S)) -#define I2C_RXFIFO_END_ADDR_V 0x1F -#define I2C_RXFIFO_END_ADDR_S 5 -/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: This is the offset address of the last receiving data as described - in nonfifo_rx_thres_register.*/ -#define I2C_RXFIFO_START_ADDR 0x0000001F -#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S)) -#define I2C_RXFIFO_START_ADDR_V 0x1F -#define I2C_RXFIFO_START_ADDR_S 0 - -#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) -/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */ -/*description: when I2C sends more than nonfifo_tx_thres data it will produce - tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ -#define I2C_NONFIFO_TX_THRES 0x0000003F -#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S)) -#define I2C_NONFIFO_TX_THRES_V 0x3F -#define I2C_NONFIFO_TX_THRES_S 20 -/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */ -/*description: when I2C receives more than nonfifo_rx_thres data it will produce - rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ -#define I2C_NONFIFO_RX_THRES 0x0000003F -#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S)) -#define I2C_NONFIFO_RX_THRES_V 0x3F -#define I2C_NONFIFO_RX_THRES_S 14 -/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to reset tx fifo when using apb fifo access.*/ -#define I2C_TX_FIFO_RST (BIT(13)) -#define I2C_TX_FIFO_RST_M (BIT(13)) -#define I2C_TX_FIFO_RST_V 0x1 -#define I2C_TX_FIFO_RST_S 13 -/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to reset rx fifo when using apb fifo access.*/ -#define I2C_RX_FIFO_RST (BIT(12)) -#define I2C_RX_FIFO_RST_M (BIT(12)) -#define I2C_RX_FIFO_RST_V 0x1 -#define I2C_RX_FIFO_RST_S 12 -/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: When this bit is set to 1 then the byte after address represent - the offset address of I2C Slave's ram.*/ -#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_V 0x1 -#define I2C_FIFO_ADDR_CFG_EN_S 11 -/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to enble apb nonfifo access.*/ -#define I2C_NONFIFO_EN (BIT(10)) -#define I2C_NONFIFO_EN_M (BIT(10)) -#define I2C_NONFIFO_EN_V 0x1 -#define I2C_NONFIFO_EN_S 10 -/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ -/*description: Config txfifo empty threhd value when using apb fifo access*/ -#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F -#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S)) -#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F -#define I2C_TXFIFO_EMPTY_THRHD_S 5 -/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ -/*description: */ -#define I2C_RXFIFO_FULL_THRHD 0x0000001F -#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S)) -#define I2C_RXFIFO_FULL_THRHD_V 0x1F -#define I2C_RXFIFO_FULL_THRHD_S 0 - -#define I2C_DATA_APB_REG(i) (0x60013000 + (i) * 0x14000 + 0x001c) - -#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) -/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: The register represent the byte data read from rxfifo when use apb fifo access*/ -#define I2C_FIFO_RDATA 0x000000FF -#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) -#define I2C_FIFO_RDATA_V 0xFF -#define I2C_FIFO_RDATA_S 0 - -#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020) -/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when - I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ -#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_RAW_S 12 -/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when - I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ -#define I2C_RX_REC_FULL_INT_RAW (BIT(11)) -#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_RAW_V 0x1 -#define I2C_RX_REC_FULL_INT_RAW_S 11 -/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for ack_err_int interrupt. when - I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ -#define I2C_ACK_ERR_INT_RAW (BIT(10)) -#define I2C_ACK_ERR_INT_RAW_M (BIT(10)) -#define I2C_ACK_ERR_INT_RAW_V 0x1 -#define I2C_ACK_ERR_INT_RAW_S 10 -/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for trans_start_int interrupt. when - I2C sends the START bit it will produce trans_start_int interrupt.*/ -#define I2C_TRANS_START_INT_RAW (BIT(9)) -#define I2C_TRANS_START_INT_RAW_M (BIT(9)) -#define I2C_TRANS_START_INT_RAW_V 0x1 -#define I2C_TRANS_START_INT_RAW_S 9 -/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for time_out_int interrupt. when - I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ -#define I2C_TIME_OUT_INT_RAW (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_V 0x1 -#define I2C_TIME_OUT_INT_RAW_S 8 -/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for trans_complete_int interrupt. - when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 -#define I2C_TRANS_COMPLETE_INT_RAW_S 7 -/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for master_tra_comp_int interrupt. - when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ -#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6 -/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when - I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 -#define I2C_ARBITRATION_LOST_INT_RAW_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for slave_tran_comp_int interrupt. - when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/ -#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4 -/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for end_detect_int interrupt. when - I2C deals with the END command it will produce end_detect_int interrupt.*/ -#define I2C_END_DETECT_INT_RAW (BIT(3)) -#define I2C_END_DETECT_INT_RAW_M (BIT(3)) -#define I2C_END_DETECT_INT_RAW_V 0x1 -#define I2C_END_DETECT_INT_RAW_S 3 -/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for receiving data overflow when - use apb fifo access.*/ -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 -#define I2C_RXFIFO_OVF_INT_RAW_S 2 -/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/ -#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_RAW_S 1 -/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/ -#define I2C_RXFIFO_FULL_INT_RAW (BIT(0)) -#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_RAW_V 0x1 -#define I2C_RXFIFO_FULL_INT_RAW_S 0 - -#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024) -/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_send_empty_int interrupt.*/ -#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_CLR_S 12 -/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rx_rec_full_int interrupt.*/ -#define I2C_RX_REC_FULL_INT_CLR (BIT(11)) -#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_CLR_V 0x1 -#define I2C_RX_REC_FULL_INT_CLR_S 11 -/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the ack_err_int interrupt.*/ -#define I2C_ACK_ERR_INT_CLR (BIT(10)) -#define I2C_ACK_ERR_INT_CLR_M (BIT(10)) -#define I2C_ACK_ERR_INT_CLR_V 0x1 -#define I2C_ACK_ERR_INT_CLR_S 10 -/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the trans_start_int interrupt.*/ -#define I2C_TRANS_START_INT_CLR (BIT(9)) -#define I2C_TRANS_START_INT_CLR_M (BIT(9)) -#define I2C_TRANS_START_INT_CLR_V 0x1 -#define I2C_TRANS_START_INT_CLR_S 9 -/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the time_out_int interrupt.*/ -#define I2C_TIME_OUT_INT_CLR (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_V 0x1 -#define I2C_TIME_OUT_INT_CLR_S 8 -/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the trans_complete_int interrupt.*/ -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 -#define I2C_TRANS_COMPLETE_INT_CLR_S 7 -/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the master_tran_comp interrupt.*/ -#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6 -/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the arbitration_lost_int interrupt.*/ -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 -#define I2C_ARBITRATION_LOST_INT_CLR_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/ -#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4 -/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the end_detect_int interrupt.*/ -#define I2C_END_DETECT_INT_CLR (BIT(3)) -#define I2C_END_DETECT_INT_CLR_M (BIT(3)) -#define I2C_END_DETECT_INT_CLR_V 0x1 -#define I2C_END_DETECT_INT_CLR_S 3 -/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/ -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 -#define I2C_RXFIFO_OVF_INT_CLR_S 2 -/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the txfifo_empty_int interrupt.*/ -#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_CLR_S 1 -/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_full_int interrupt.*/ -#define I2C_RXFIFO_FULL_INT_CLR (BIT(0)) -#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_CLR_V 0x1 -#define I2C_RXFIFO_FULL_INT_CLR_S 0 - -#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028) -/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The enable bit for tx_send_empty_int interrupt.*/ -#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_ENA_S 12 -/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The enable bit for rx_rec_full_int interrupt.*/ -#define I2C_RX_REC_FULL_INT_ENA (BIT(11)) -#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_ENA_V 0x1 -#define I2C_RX_REC_FULL_INT_ENA_S 11 -/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The enable bit for ack_err_int interrupt.*/ -#define I2C_ACK_ERR_INT_ENA (BIT(10)) -#define I2C_ACK_ERR_INT_ENA_M (BIT(10)) -#define I2C_ACK_ERR_INT_ENA_V 0x1 -#define I2C_ACK_ERR_INT_ENA_S 10 -/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The enable bit for trans_start_int interrupt.*/ -#define I2C_TRANS_START_INT_ENA (BIT(9)) -#define I2C_TRANS_START_INT_ENA_M (BIT(9)) -#define I2C_TRANS_START_INT_ENA_V 0x1 -#define I2C_TRANS_START_INT_ENA_S 9 -/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The enable bit for time_out_int interrupt.*/ -#define I2C_TIME_OUT_INT_ENA (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_V 0x1 -#define I2C_TIME_OUT_INT_ENA_S 8 -/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The enable bit for trans_complete_int interrupt.*/ -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 -#define I2C_TRANS_COMPLETE_INT_ENA_S 7 -/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The enable bit for master_tran_comp_int interrupt.*/ -#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6 -/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The enable bit for arbitration_lost_int interrupt.*/ -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 -#define I2C_ARBITRATION_LOST_INT_ENA_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The enable bit for slave_tran_comp_int interrupt.*/ -#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4 -/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for end_detect_int interrupt.*/ -#define I2C_END_DETECT_INT_ENA (BIT(3)) -#define I2C_END_DETECT_INT_ENA_M (BIT(3)) -#define I2C_END_DETECT_INT_ENA_V 0x1 -#define I2C_END_DETECT_INT_ENA_S 3 -/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for rxfifo_ovf_int interrupt.*/ -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 -#define I2C_RXFIFO_OVF_INT_ENA_S 2 -/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for txfifo_empty_int interrupt.*/ -#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_ENA_S 1 -/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for rxfifo_full_int interrupt.*/ -#define I2C_RXFIFO_FULL_INT_ENA (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ENA_V 0x1 -#define I2C_RXFIFO_FULL_INT_ENA_S 0 - -#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) -/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The masked interrupt status for tx_send_empty_int interrupt.*/ -#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_ST_S 12 -/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The masked interrupt status for rx_rec_full_int interrupt.*/ -#define I2C_RX_REC_FULL_INT_ST (BIT(11)) -#define I2C_RX_REC_FULL_INT_ST_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_ST_V 0x1 -#define I2C_RX_REC_FULL_INT_ST_S 11 -/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The masked interrupt status for ack_err_int interrupt.*/ -#define I2C_ACK_ERR_INT_ST (BIT(10)) -#define I2C_ACK_ERR_INT_ST_M (BIT(10)) -#define I2C_ACK_ERR_INT_ST_V 0x1 -#define I2C_ACK_ERR_INT_ST_S 10 -/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The masked interrupt status for trans_start_int interrupt.*/ -#define I2C_TRANS_START_INT_ST (BIT(9)) -#define I2C_TRANS_START_INT_ST_M (BIT(9)) -#define I2C_TRANS_START_INT_ST_V 0x1 -#define I2C_TRANS_START_INT_ST_S 9 -/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The masked interrupt status for time_out_int interrupt.*/ -#define I2C_TIME_OUT_INT_ST (BIT(8)) -#define I2C_TIME_OUT_INT_ST_M (BIT(8)) -#define I2C_TIME_OUT_INT_ST_V 0x1 -#define I2C_TIME_OUT_INT_ST_S 8 -/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The masked interrupt status for trans_complete_int interrupt.*/ -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 -#define I2C_TRANS_COMPLETE_INT_ST_S 7 -/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The masked interrupt status for master_tran_comp_int interrupt.*/ -#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_ST_S 6 -/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The masked interrupt status for arbitration_lost_int interrupt.*/ -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 -#define I2C_ARBITRATION_LOST_INT_ST_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/ -#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4 -/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The masked interrupt status for end_detect_int interrupt.*/ -#define I2C_END_DETECT_INT_ST (BIT(3)) -#define I2C_END_DETECT_INT_ST_M (BIT(3)) -#define I2C_END_DETECT_INT_ST_V 0x1 -#define I2C_END_DETECT_INT_ST_S 3 -/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/ -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_V 0x1 -#define I2C_RXFIFO_OVF_INT_ST_S 2 -/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The masked interrupt status for txfifo_empty_int interrupt.*/ -#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_ST_S 1 -/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The masked interrupt status for rxfifo_full_int interrupt.*/ -#define I2C_RXFIFO_FULL_INT_ST (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ST_V 0x1 -#define I2C_RXFIFO_FULL_INT_ST_S 0 - -#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) -/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: This register is used to configure the clock num I2C used to - hold the data after the negedge of SCL.*/ -#define I2C_SDA_HOLD_TIME 0x000003FF -#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) -#define I2C_SDA_HOLD_TIME_V 0x3FF -#define I2C_SDA_HOLD_TIME_S 0 - -#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034) -/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: This register is used to configure the clock num I2C used to - sample data on SDA after the posedge of SCL*/ -#define I2C_SDA_SAMPLE_TIME 0x000003FF -#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) -#define I2C_SDA_SAMPLE_TIME_V 0x3FF -#define I2C_SDA_SAMPLE_TIME_S 0 - -#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038) -/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This register is used to configure the clock num during SCL is low level.*/ -#define I2C_SCL_HIGH_PERIOD 0x00003FFF -#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) -#define I2C_SCL_HIGH_PERIOD_V 0x3FFF -#define I2C_SCL_HIGH_PERIOD_S 0 - -#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040) -/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ -/*description: This register is used to configure the clock num between the - negedge of SDA and negedge of SCL for start mark.*/ -#define I2C_SCL_START_HOLD_TIME 0x000003FF -#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) -#define I2C_SCL_START_HOLD_TIME_V 0x3FF -#define I2C_SCL_START_HOLD_TIME_S 0 - -#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044) -/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ -/*description: This register is used to configure the clock num between the - posedge of SCL and the negedge of SDA for restart mark.*/ -#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF -#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF -#define I2C_SCL_RSTART_SETUP_TIME_S 0 - -#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048) -/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This register is used to configure the clock num after the STOP bit's posedge.*/ -#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF -#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) -#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF -#define I2C_SCL_STOP_HOLD_TIME_S 0 - -#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C) -/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: This register is used to configure the clock num between the - posedge of SCL and the posedge of SDA.*/ -#define I2C_SCL_STOP_SETUP_TIME 0x000003FF -#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) -#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF -#define I2C_SCL_STOP_SETUP_TIME_S 0 - -#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) -/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This is the filter enable bit for SCL.*/ -#define I2C_SCL_FILTER_EN (BIT(3)) -#define I2C_SCL_FILTER_EN_M (BIT(3)) -#define I2C_SCL_FILTER_EN_V 0x1 -#define I2C_SCL_FILTER_EN_S 3 -/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: When input SCL's pulse width is smaller than this register value - I2C ignores this pulse.*/ -#define I2C_SCL_FILTER_THRES 0x00000007 -#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) -#define I2C_SCL_FILTER_THRES_V 0x7 -#define I2C_SCL_FILTER_THRES_S 0 - -#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054) -/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This is the filter enable bit for SDA.*/ -#define I2C_SDA_FILTER_EN (BIT(3)) -#define I2C_SDA_FILTER_EN_M (BIT(3)) -#define I2C_SDA_FILTER_EN_V 0x1 -#define I2C_SDA_FILTER_EN_S 3 -/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: When input SCL's pulse width is smaller than this register value - I2C ignores this pulse.*/ -#define I2C_SDA_FILTER_THRES 0x00000007 -#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) -#define I2C_SDA_FILTER_THRES_V 0x7 -#define I2C_SDA_FILTER_THRES_S 0 - -#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) -/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command0 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND0_DONE (BIT(31)) -#define I2C_COMMAND0_DONE_M (BIT(31)) -#define I2C_COMMAND0_DONE_V 0x1 -#define I2C_COMMAND0_DONE_S 31 -/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command0. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND0 0x00003FFF -#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) -#define I2C_COMMAND0_V 0x3FFF -#define I2C_COMMAND0_S 0 - -#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C) -/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command1 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND1_DONE (BIT(31)) -#define I2C_COMMAND1_DONE_M (BIT(31)) -#define I2C_COMMAND1_DONE_V 0x1 -#define I2C_COMMAND1_DONE_S 31 -/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command1. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND1 0x00003FFF -#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) -#define I2C_COMMAND1_V 0x3FFF -#define I2C_COMMAND1_S 0 - -#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060) -/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command2 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND2_DONE (BIT(31)) -#define I2C_COMMAND2_DONE_M (BIT(31)) -#define I2C_COMMAND2_DONE_V 0x1 -#define I2C_COMMAND2_DONE_S 31 -/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command2. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND2 0x00003FFF -#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) -#define I2C_COMMAND2_V 0x3FFF -#define I2C_COMMAND2_S 0 - -#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064) -/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command3 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND3_DONE (BIT(31)) -#define I2C_COMMAND3_DONE_M (BIT(31)) -#define I2C_COMMAND3_DONE_V 0x1 -#define I2C_COMMAND3_DONE_S 31 -/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command3. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND3 0x00003FFF -#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) -#define I2C_COMMAND3_V 0x3FFF -#define I2C_COMMAND3_S 0 - -#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068) -/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command4 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND4_DONE (BIT(31)) -#define I2C_COMMAND4_DONE_M (BIT(31)) -#define I2C_COMMAND4_DONE_V 0x1 -#define I2C_COMMAND4_DONE_S 31 -/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command4. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND4 0x00003FFF -#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) -#define I2C_COMMAND4_V 0x3FFF -#define I2C_COMMAND4_S 0 - -#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C) -/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command5 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND5_DONE (BIT(31)) -#define I2C_COMMAND5_DONE_M (BIT(31)) -#define I2C_COMMAND5_DONE_V 0x1 -#define I2C_COMMAND5_DONE_S 31 -/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command5. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND5 0x00003FFF -#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) -#define I2C_COMMAND5_V 0x3FFF -#define I2C_COMMAND5_S 0 - -#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070) -/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command6 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND6_DONE (BIT(31)) -#define I2C_COMMAND6_DONE_M (BIT(31)) -#define I2C_COMMAND6_DONE_V 0x1 -#define I2C_COMMAND6_DONE_S 31 -/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command6. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND6 0x00003FFF -#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) -#define I2C_COMMAND6_V 0x3FFF -#define I2C_COMMAND6_S 0 - -#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074) -/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command7 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND7_DONE (BIT(31)) -#define I2C_COMMAND7_DONE_M (BIT(31)) -#define I2C_COMMAND7_DONE_V 0x1 -#define I2C_COMMAND7_DONE_S 31 -/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command7. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND7 0x00003FFF -#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) -#define I2C_COMMAND7_V 0x3FFF -#define I2C_COMMAND7_S 0 - -#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078) -/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command8 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND8_DONE (BIT(31)) -#define I2C_COMMAND8_DONE_M (BIT(31)) -#define I2C_COMMAND8_DONE_V 0x1 -#define I2C_COMMAND8_DONE_S 31 -/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command8. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND8 0x00003FFF -#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S)) -#define I2C_COMMAND8_V 0x3FFF -#define I2C_COMMAND8_S 0 - -#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C) -/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command9 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND9_DONE (BIT(31)) -#define I2C_COMMAND9_DONE_M (BIT(31)) -#define I2C_COMMAND9_DONE_V 0x1 -#define I2C_COMMAND9_DONE_S 31 -/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command9. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND9 0x00003FFF -#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S)) -#define I2C_COMMAND9_V 0x3FFF -#define I2C_COMMAND9_S 0 - -#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080) -/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command10 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND10_DONE (BIT(31)) -#define I2C_COMMAND10_DONE_M (BIT(31)) -#define I2C_COMMAND10_DONE_V 0x1 -#define I2C_COMMAND10_DONE_S 31 -/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command10. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND10 0x00003FFF -#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S)) -#define I2C_COMMAND10_V 0x3FFF -#define I2C_COMMAND10_S 0 - -#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084) -/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command11 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND11_DONE (BIT(31)) -#define I2C_COMMAND11_DONE_M (BIT(31)) -#define I2C_COMMAND11_DONE_V 0x1 -#define I2C_COMMAND11_DONE_S 31 -/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command11. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND11 0x00003FFF -#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S)) -#define I2C_COMMAND11_V 0x3FFF -#define I2C_COMMAND11_S 0 - -#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088) -/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command12 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND12_DONE (BIT(31)) -#define I2C_COMMAND12_DONE_M (BIT(31)) -#define I2C_COMMAND12_DONE_V 0x1 -#define I2C_COMMAND12_DONE_S 31 -/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command12. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND12 0x00003FFF -#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S)) -#define I2C_COMMAND12_V 0x3FFF -#define I2C_COMMAND12_S 0 - -#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C) -/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command13 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND13_DONE (BIT(31)) -#define I2C_COMMAND13_DONE_M (BIT(31)) -#define I2C_COMMAND13_DONE_V 0x1 -#define I2C_COMMAND13_DONE_S 31 -/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command13. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND13 0x00003FFF -#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S)) -#define I2C_COMMAND13_V 0x3FFF -#define I2C_COMMAND13_S 0 - -#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090) -/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command14 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND14_DONE (BIT(31)) -#define I2C_COMMAND14_DONE_M (BIT(31)) -#define I2C_COMMAND14_DONE_V 0x1 -#define I2C_COMMAND14_DONE_S 31 -/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command14. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND14 0x00003FFF -#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S)) -#define I2C_COMMAND14_V 0x3FFF -#define I2C_COMMAND14_S 0 - -#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094) -/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command15 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND15_DONE (BIT(31)) -#define I2C_COMMAND15_DONE_M (BIT(31)) -#define I2C_COMMAND15_DONE_V 0x1 -#define I2C_COMMAND15_DONE_S 31 -/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command15. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND15 0x00003FFF -#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S)) -#define I2C_COMMAND15_V 0x3FFF -#define I2C_COMMAND15_S 0 - -#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8) -/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ -/*description: */ -#define I2C_DATE 0xFFFFFFFF -#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) -#define I2C_DATE_V 0xFFFFFFFF -#define I2C_DATE_S 0 - -#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) - - - - -#endif /*_SOC_I2C_REG_H_ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2C_REG_H_ +#define _SOC_I2C_REG_H_ + + +#include "soc.h" + +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) + +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000) +/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the low level width of SCL clock.*/ +#define I2C_SCL_LOW_PERIOD 0x00003FFF +#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) +#define I2C_SCL_LOW_PERIOD_V 0x3FFF +#define I2C_SCL_LOW_PERIOD_S 0 + +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004) +/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the clock gating control bit for reading or writing registers.*/ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (BIT(8)) +#define I2C_CLK_EN_V 0x1 +#define I2C_CLK_EN_S 8 +/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: This bit is used to control the storage mode for received datas. + 1: receive data from most significant bit 0: receive data from least significant bit*/ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (BIT(7)) +#define I2C_RX_LSB_FIRST_V 0x1 +#define I2C_RX_LSB_FIRST_S 7 +/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This bit is used to control the sending mode for data need to + be send. 1: receive data from most significant bit 0: receive data from least significant bit*/ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (BIT(6)) +#define I2C_TX_LSB_FIRST_V 0x1 +#define I2C_TX_LSB_FIRST_S 6 +/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to start sending data in txfifo.*/ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (BIT(5)) +#define I2C_TRANS_START_V 0x1 +#define I2C_TRANS_START_S 5 +/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to configure the module as i2c master clear this + bit to configure the module as i2c slave.*/ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (BIT(4)) +#define I2C_MS_MODE_V 0x1 +#define I2C_MS_MODE_S 4 +/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to sample data in SCL low level. clear this bit + to sample data in SCL high level.*/ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_V 0x1 +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: 1: normally ouput scl clock 0: exchange the function of scl_o + and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (BIT(1)) +#define I2C_SCL_FORCE_OUT_V 0x1 +#define I2C_SCL_FORCE_OUT_S 1 +/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: 1: normally ouput sda data 0: exchange the function of sda_o + and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (BIT(0)) +#define I2C_SDA_FORCE_OUT_V 0x1 +#define I2C_SDA_FORCE_OUT_S 0 + +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008) +/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: This register stores the value of state machine to produce SCL. + 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ +#define I2C_SCL_STATE_LAST 0x00000007 +#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) +#define I2C_SCL_STATE_LAST_V 0x7 +#define I2C_SCL_STATE_LAST_S 28 +/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: This register stores the value of state machine for i2c module. + 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) +#define I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ +/*description: This register stores the amount of received data in ram.*/ +#define I2C_TXFIFO_CNT 0x0000003F +#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) +#define I2C_TXFIFO_CNT_V 0x3F +#define I2C_TXFIFO_CNT_S 18 +/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ +/*description: This register represent the amount of data need to send.*/ +#define I2C_RXFIFO_CNT 0x0000003F +#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) +#define I2C_RXFIFO_CNT_V 0x3F +#define I2C_RXFIFO_CNT_S 8 +/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This register changes to high level when one byte is transferred.*/ +#define I2C_BYTE_TRANS (BIT(6)) +#define I2C_BYTE_TRANS_M (BIT(6)) +#define I2C_BYTE_TRANS_V 0x1 +#define I2C_BYTE_TRANS_S 6 +/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: when configured as i2c slave and the address send by master + is equal to slave's address then this bit will be high level.*/ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (BIT(5)) +#define I2C_SLAVE_ADDRESSED_V 0x1 +#define I2C_SLAVE_ADDRESSED_S 5 +/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (BIT(4)) +#define I2C_BUS_BUSY_V 0x1 +#define I2C_BUS_BUSY_S 4 +/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: when I2C lost control of SDA line this register changes to high level.*/ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (BIT(3)) +#define I2C_ARB_LOST_V 0x1 +#define I2C_ARB_LOST_S 3 +/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: when I2C takes more than time_out_reg clocks to receive a data + then this register changes to high level.*/ +#define I2C_TIME_OUT (BIT(2)) +#define I2C_TIME_OUT_M (BIT(2)) +#define I2C_TIME_OUT_V 0x1 +#define I2C_TIME_OUT_S 2 +/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: when in slave mode 1: master read slave 0: master write slave.*/ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (BIT(1)) +#define I2C_SLAVE_RW_V 0x1 +#define I2C_SLAVE_RW_S 1 +/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This register stores the value of ACK bit.*/ +#define I2C_ACK_REC (BIT(0)) +#define I2C_ACK_REC_M (BIT(0)) +#define I2C_ACK_REC_V 0x1 +#define I2C_ACK_REC_S 0 + +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c) +/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: This register is used to configure the max clock number of receiving a data.*/ +#define I2C_TIME_OUT_REG 0x000FFFFF +#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S)) +#define I2C_TIME_OUT_REG_V 0xFFFFF +#define I2C_TIME_OUT_REG_S 0 + +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010) +/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: This register is used to enable slave 10bit address mode.*/ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (BIT(31)) +#define I2C_ADDR_10BIT_EN_V 0x1 +#define I2C_ADDR_10BIT_EN_S 31 +/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: when configured as i2c slave this register is used to configure + slave's address.*/ +#define I2C_SLAVE_ADDR 0x00007FFF +#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) +#define I2C_SLAVE_ADDR_V 0x7FFF +#define I2C_SLAVE_ADDR_S 0 + +#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) +/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: This is the offset address of the last sending data as described + in nonfifo_tx_thres register.*/ +#define I2C_TXFIFO_END_ADDR 0x0000001F +#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S)) +#define I2C_TXFIFO_END_ADDR_V 0x1F +#define I2C_TXFIFO_END_ADDR_S 15 +/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: This is the offset address of the first sending data as described + in nonfifo_tx_thres register.*/ +#define I2C_TXFIFO_START_ADDR 0x0000001F +#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S)) +#define I2C_TXFIFO_START_ADDR_V 0x1F +#define I2C_TXFIFO_START_ADDR_S 10 +/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: This is the offset address of the first receiving data as described + in nonfifo_rx_thres_register.*/ +#define I2C_RXFIFO_END_ADDR 0x0000001F +#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S)) +#define I2C_RXFIFO_END_ADDR_V 0x1F +#define I2C_RXFIFO_END_ADDR_S 5 +/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: This is the offset address of the last receiving data as described + in nonfifo_rx_thres_register.*/ +#define I2C_RXFIFO_START_ADDR 0x0000001F +#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S)) +#define I2C_RXFIFO_START_ADDR_V 0x1F +#define I2C_RXFIFO_START_ADDR_S 0 + +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) +/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */ +/*description: when I2C sends more than nonfifo_tx_thres data it will produce + tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ +#define I2C_NONFIFO_TX_THRES 0x0000003F +#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S)) +#define I2C_NONFIFO_TX_THRES_V 0x3F +#define I2C_NONFIFO_TX_THRES_S 20 +/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */ +/*description: when I2C receives more than nonfifo_rx_thres data it will produce + rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ +#define I2C_NONFIFO_RX_THRES 0x0000003F +#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S)) +#define I2C_NONFIFO_RX_THRES_V 0x3F +#define I2C_NONFIFO_RX_THRES_S 14 +/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to reset tx fifo when using apb fifo access.*/ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (BIT(13)) +#define I2C_TX_FIFO_RST_V 0x1 +#define I2C_TX_FIFO_RST_S 13 +/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to reset rx fifo when using apb fifo access.*/ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (BIT(12)) +#define I2C_RX_FIFO_RST_V 0x1 +#define I2C_RX_FIFO_RST_S 12 +/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: When this bit is set to 1 then the byte after address represent + the offset address of I2C Slave's ram.*/ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_V 0x1 +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to enble apb nonfifo access.*/ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (BIT(10)) +#define I2C_NONFIFO_EN_V 0x1 +#define I2C_NONFIFO_EN_S 10 +/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ +/*description: Config txfifo empty threhd value when using apb fifo access*/ +#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F +#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S)) +#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F +#define I2C_TXFIFO_EMPTY_THRHD_S 5 +/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ +/*description: */ +#define I2C_RXFIFO_FULL_THRHD 0x0000001F +#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S)) +#define I2C_RXFIFO_FULL_THRHD_V 0x1F +#define I2C_RXFIFO_FULL_THRHD_S 0 + +#define I2C_DATA_APB_REG(i) (0x60013000 + (i) * 0x14000 + 0x001c) + +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) +/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: The register represent the byte data read from rxfifo when use apb fifo access*/ +#define I2C_FIFO_RDATA 0x000000FF +#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) +#define I2C_FIFO_RDATA_V 0xFF +#define I2C_FIFO_RDATA_S 0 + +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020) +/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when + I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ +#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_RAW_S 12 +/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when + I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_RAW (BIT(11)) +#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_RAW_V 0x1 +#define I2C_RX_REC_FULL_INT_RAW_S 11 +/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for ack_err_int interrupt. when + I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ +#define I2C_ACK_ERR_INT_RAW (BIT(10)) +#define I2C_ACK_ERR_INT_RAW_M (BIT(10)) +#define I2C_ACK_ERR_INT_RAW_V 0x1 +#define I2C_ACK_ERR_INT_RAW_S 10 +/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for trans_start_int interrupt. when + I2C sends the START bit it will produce trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (BIT(9)) +#define I2C_TRANS_START_INT_RAW_V 0x1 +#define I2C_TRANS_START_INT_RAW_S 9 +/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for time_out_int interrupt. when + I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_V 0x1 +#define I2C_TIME_OUT_INT_RAW_S 8 +/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for trans_complete_int interrupt. + when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for master_tra_comp_int interrupt. + when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6 +/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when + I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for slave_tran_comp_int interrupt. + when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4 +/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for end_detect_int interrupt. when + I2C deals with the END command it will produce end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (BIT(3)) +#define I2C_END_DETECT_INT_RAW_V 0x1 +#define I2C_END_DETECT_INT_RAW_S 3 +/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for receiving data overflow when + use apb fifo access.*/ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/ +#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_RAW_S 1 +/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/ +#define I2C_RXFIFO_FULL_INT_RAW (BIT(0)) +#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_RAW_V 0x1 +#define I2C_RXFIFO_FULL_INT_RAW_S 0 + +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024) +/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_CLR_S 12 +/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_CLR (BIT(11)) +#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_CLR_V 0x1 +#define I2C_RX_REC_FULL_INT_CLR_S 11 +/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_CLR (BIT(10)) +#define I2C_ACK_ERR_INT_CLR_M (BIT(10)) +#define I2C_ACK_ERR_INT_CLR_V 0x1 +#define I2C_ACK_ERR_INT_CLR_S 10 +/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (BIT(9)) +#define I2C_TRANS_START_INT_CLR_V 0x1 +#define I2C_TRANS_START_INT_CLR_S 9 +/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_V 0x1 +#define I2C_TIME_OUT_INT_CLR_S 8 +/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the master_tran_comp interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6 +/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4 +/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (BIT(3)) +#define I2C_END_DETECT_INT_CLR_V 0x1 +#define I2C_END_DETECT_INT_CLR_S 3 +/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_CLR_S 1 +/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_CLR (BIT(0)) +#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_CLR_V 0x1 +#define I2C_RXFIFO_FULL_INT_CLR_S 0 + +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028) +/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The enable bit for tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_ENA_S 12 +/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The enable bit for rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_ENA (BIT(11)) +#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_ENA_V 0x1 +#define I2C_RX_REC_FULL_INT_ENA_S 11 +/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The enable bit for ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_ENA (BIT(10)) +#define I2C_ACK_ERR_INT_ENA_M (BIT(10)) +#define I2C_ACK_ERR_INT_ENA_V 0x1 +#define I2C_ACK_ERR_INT_ENA_S 10 +/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (BIT(9)) +#define I2C_TRANS_START_INT_ENA_V 0x1 +#define I2C_TRANS_START_INT_ENA_S 9 +/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_V 0x1 +#define I2C_TIME_OUT_INT_ENA_S 8 +/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6 +/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4 +/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (BIT(3)) +#define I2C_END_DETECT_INT_ENA_V 0x1 +#define I2C_END_DETECT_INT_ENA_S 3 +/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_ENA_S 1 +/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_ENA (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ENA_V 0x1 +#define I2C_RXFIFO_FULL_INT_ENA_S 0 + +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) +/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The masked interrupt status for tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_ST_S 12 +/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_ST (BIT(11)) +#define I2C_RX_REC_FULL_INT_ST_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_ST_V 0x1 +#define I2C_RX_REC_FULL_INT_ST_S 11 +/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The masked interrupt status for ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_ST (BIT(10)) +#define I2C_ACK_ERR_INT_ST_M (BIT(10)) +#define I2C_ACK_ERR_INT_ST_V 0x1 +#define I2C_ACK_ERR_INT_ST_S 10 +/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The masked interrupt status for trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (BIT(9)) +#define I2C_TRANS_START_INT_ST_V 0x1 +#define I2C_TRANS_START_INT_ST_S 9 +/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The masked interrupt status for time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (BIT(8)) +#define I2C_TIME_OUT_INT_ST_V 0x1 +#define I2C_TIME_OUT_INT_ST_S 8 +/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The masked interrupt status for trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The masked interrupt status for master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_ST_S 6 +/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The masked interrupt status for arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4 +/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The masked interrupt status for end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (BIT(3)) +#define I2C_END_DETECT_INT_ST_V 0x1 +#define I2C_END_DETECT_INT_ST_S 3 +/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_V 0x1 +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The masked interrupt status for txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_ST_S 1 +/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_ST (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ST_V 0x1 +#define I2C_RXFIFO_FULL_INT_ST_S 0 + +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) +/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num I2C used to + hold the data after the negedge of SCL.*/ +#define I2C_SDA_HOLD_TIME 0x000003FF +#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) +#define I2C_SDA_HOLD_TIME_V 0x3FF +#define I2C_SDA_HOLD_TIME_S 0 + +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034) +/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num I2C used to + sample data on SDA after the posedge of SCL*/ +#define I2C_SDA_SAMPLE_TIME 0x000003FF +#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) +#define I2C_SDA_SAMPLE_TIME_V 0x3FF +#define I2C_SDA_SAMPLE_TIME_S 0 + +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038) +/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the clock num during SCL is low level.*/ +#define I2C_SCL_HIGH_PERIOD 0x00003FFF +#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) +#define I2C_SCL_HIGH_PERIOD_V 0x3FFF +#define I2C_SCL_HIGH_PERIOD_S 0 + +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040) +/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ +/*description: This register is used to configure the clock num between the + negedge of SDA and negedge of SCL for start mark.*/ +#define I2C_SCL_START_HOLD_TIME 0x000003FF +#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) +#define I2C_SCL_START_HOLD_TIME_V 0x3FF +#define I2C_SCL_START_HOLD_TIME_S 0 + +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044) +/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ +/*description: This register is used to configure the clock num between the + posedge of SCL and the negedge of SDA for restart mark.*/ +#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF +#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048) +/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the clock num after the STOP bit's posedge.*/ +#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF +#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) +#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C) +/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num between the + posedge of SCL and the posedge of SDA.*/ +#define I2C_SCL_STOP_SETUP_TIME 0x000003FF +#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) +#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) +/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: This is the filter enable bit for SCL.*/ +#define I2C_SCL_FILTER_EN (BIT(3)) +#define I2C_SCL_FILTER_EN_M (BIT(3)) +#define I2C_SCL_FILTER_EN_V 0x1 +#define I2C_SCL_FILTER_EN_S 3 +/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: When input SCL's pulse width is smaller than this register value + I2C ignores this pulse.*/ +#define I2C_SCL_FILTER_THRES 0x00000007 +#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) +#define I2C_SCL_FILTER_THRES_V 0x7 +#define I2C_SCL_FILTER_THRES_S 0 + +#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054) +/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: This is the filter enable bit for SDA.*/ +#define I2C_SDA_FILTER_EN (BIT(3)) +#define I2C_SDA_FILTER_EN_M (BIT(3)) +#define I2C_SDA_FILTER_EN_V 0x1 +#define I2C_SDA_FILTER_EN_S 3 +/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: When input SCL's pulse width is smaller than this register value + I2C ignores this pulse.*/ +#define I2C_SDA_FILTER_THRES 0x00000007 +#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) +#define I2C_SDA_FILTER_THRES_V 0x7 +#define I2C_SDA_FILTER_THRES_S 0 + +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) +/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command0 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (BIT(31)) +#define I2C_COMMAND0_DONE_V 0x1 +#define I2C_COMMAND0_DONE_S 31 +/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command0. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND0 0x00003FFF +#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) +#define I2C_COMMAND0_V 0x3FFF +#define I2C_COMMAND0_S 0 + +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C) +/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command1 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (BIT(31)) +#define I2C_COMMAND1_DONE_V 0x1 +#define I2C_COMMAND1_DONE_S 31 +/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command1. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND1 0x00003FFF +#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) +#define I2C_COMMAND1_V 0x3FFF +#define I2C_COMMAND1_S 0 + +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060) +/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command2 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (BIT(31)) +#define I2C_COMMAND2_DONE_V 0x1 +#define I2C_COMMAND2_DONE_S 31 +/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command2. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND2 0x00003FFF +#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) +#define I2C_COMMAND2_V 0x3FFF +#define I2C_COMMAND2_S 0 + +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064) +/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command3 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (BIT(31)) +#define I2C_COMMAND3_DONE_V 0x1 +#define I2C_COMMAND3_DONE_S 31 +/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command3. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND3 0x00003FFF +#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) +#define I2C_COMMAND3_V 0x3FFF +#define I2C_COMMAND3_S 0 + +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068) +/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command4 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (BIT(31)) +#define I2C_COMMAND4_DONE_V 0x1 +#define I2C_COMMAND4_DONE_S 31 +/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command4. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND4 0x00003FFF +#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) +#define I2C_COMMAND4_V 0x3FFF +#define I2C_COMMAND4_S 0 + +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C) +/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command5 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (BIT(31)) +#define I2C_COMMAND5_DONE_V 0x1 +#define I2C_COMMAND5_DONE_S 31 +/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command5. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND5 0x00003FFF +#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) +#define I2C_COMMAND5_V 0x3FFF +#define I2C_COMMAND5_S 0 + +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070) +/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command6 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (BIT(31)) +#define I2C_COMMAND6_DONE_V 0x1 +#define I2C_COMMAND6_DONE_S 31 +/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command6. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND6 0x00003FFF +#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) +#define I2C_COMMAND6_V 0x3FFF +#define I2C_COMMAND6_S 0 + +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074) +/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command7 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (BIT(31)) +#define I2C_COMMAND7_DONE_V 0x1 +#define I2C_COMMAND7_DONE_S 31 +/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command7. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND7 0x00003FFF +#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) +#define I2C_COMMAND7_V 0x3FFF +#define I2C_COMMAND7_S 0 + +#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078) +/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command8 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND8_DONE (BIT(31)) +#define I2C_COMMAND8_DONE_M (BIT(31)) +#define I2C_COMMAND8_DONE_V 0x1 +#define I2C_COMMAND8_DONE_S 31 +/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command8. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND8 0x00003FFF +#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S)) +#define I2C_COMMAND8_V 0x3FFF +#define I2C_COMMAND8_S 0 + +#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C) +/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command9 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND9_DONE (BIT(31)) +#define I2C_COMMAND9_DONE_M (BIT(31)) +#define I2C_COMMAND9_DONE_V 0x1 +#define I2C_COMMAND9_DONE_S 31 +/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command9. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND9 0x00003FFF +#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S)) +#define I2C_COMMAND9_V 0x3FFF +#define I2C_COMMAND9_S 0 + +#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080) +/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command10 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND10_DONE (BIT(31)) +#define I2C_COMMAND10_DONE_M (BIT(31)) +#define I2C_COMMAND10_DONE_V 0x1 +#define I2C_COMMAND10_DONE_S 31 +/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command10. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND10 0x00003FFF +#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S)) +#define I2C_COMMAND10_V 0x3FFF +#define I2C_COMMAND10_S 0 + +#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084) +/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command11 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND11_DONE (BIT(31)) +#define I2C_COMMAND11_DONE_M (BIT(31)) +#define I2C_COMMAND11_DONE_V 0x1 +#define I2C_COMMAND11_DONE_S 31 +/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command11. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND11 0x00003FFF +#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S)) +#define I2C_COMMAND11_V 0x3FFF +#define I2C_COMMAND11_S 0 + +#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088) +/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command12 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND12_DONE (BIT(31)) +#define I2C_COMMAND12_DONE_M (BIT(31)) +#define I2C_COMMAND12_DONE_V 0x1 +#define I2C_COMMAND12_DONE_S 31 +/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command12. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND12 0x00003FFF +#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S)) +#define I2C_COMMAND12_V 0x3FFF +#define I2C_COMMAND12_S 0 + +#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C) +/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command13 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND13_DONE (BIT(31)) +#define I2C_COMMAND13_DONE_M (BIT(31)) +#define I2C_COMMAND13_DONE_V 0x1 +#define I2C_COMMAND13_DONE_S 31 +/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command13. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND13 0x00003FFF +#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S)) +#define I2C_COMMAND13_V 0x3FFF +#define I2C_COMMAND13_S 0 + +#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090) +/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command14 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND14_DONE (BIT(31)) +#define I2C_COMMAND14_DONE_M (BIT(31)) +#define I2C_COMMAND14_DONE_V 0x1 +#define I2C_COMMAND14_DONE_S 31 +/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command14. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND14 0x00003FFF +#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S)) +#define I2C_COMMAND14_V 0x3FFF +#define I2C_COMMAND14_S 0 + +#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094) +/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command15 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND15_DONE (BIT(31)) +#define I2C_COMMAND15_DONE_M (BIT(31)) +#define I2C_COMMAND15_DONE_V 0x1 +#define I2C_COMMAND15_DONE_S 31 +/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command15. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND15 0x00003FFF +#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S)) +#define I2C_COMMAND15_V 0x3FFF +#define I2C_COMMAND15_S 0 + +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8) +/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ +/*description: */ +#define I2C_DATE 0xFFFFFFFF +#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) +#define I2C_DATE_V 0xFFFFFFFF +#define I2C_DATE_S 0 + +#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) + + + + +#endif /*_SOC_I2C_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/i2c_struct.h b/tools/sdk/include/soc/soc/i2c_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/i2c_struct.h rename to tools/sdk/include/soc/soc/i2c_struct.h diff --git a/tools/sdk/include/esp32/soc/i2s_reg.h b/tools/sdk/include/soc/soc/i2s_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/i2s_reg.h rename to tools/sdk/include/soc/soc/i2s_reg.h diff --git a/tools/sdk/include/esp32/soc/i2s_struct.h b/tools/sdk/include/soc/soc/i2s_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/i2s_struct.h rename to tools/sdk/include/soc/soc/i2s_struct.h diff --git a/tools/sdk/include/esp32/soc/io_mux_reg.h b/tools/sdk/include/soc/soc/io_mux_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/io_mux_reg.h rename to tools/sdk/include/soc/soc/io_mux_reg.h diff --git a/tools/sdk/include/esp32/soc/ledc_reg.h b/tools/sdk/include/soc/soc/ledc_reg.h similarity index 98% rename from tools/sdk/include/esp32/soc/ledc_reg.h rename to tools/sdk/include/soc/soc/ledc_reg.h index 1137e3da..6d6abf8b 100644 --- a/tools/sdk/include/esp32/soc/ledc_reg.h +++ b/tools/sdk/include/soc/soc/ledc_reg.h @@ -1,2423 +1,2423 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_LEDC_REG_H_ -#define _SOC_LEDC_REG_H_ - - -#include "soc.h" -#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) -/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: This bit is clock gating control signal. when software config - LED_PWM internal registers it controls the register clock.*/ -#define LEDC_CLK_EN (BIT(31)) -#define LEDC_CLK_EN_M (BIT(31)) -#define LEDC_CLK_EN_V 0x1 -#define LEDC_CLK_EN_S 31 -/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel0 is off.*/ -#define LEDC_IDLE_LV_HSCH0 (BIT(3)) -#define LEDC_IDLE_LV_HSCH0_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH0_V 0x1 -#define LEDC_IDLE_LV_HSCH0_S 3 -/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel0*/ -#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH0_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH0_S 2 -/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH0 0x00000003 -#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S)) -#define LEDC_TIMER_SEL_HSCH0_V 0x3 -#define LEDC_TIMER_SEL_HSCH0_S 0 - -#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) -/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/ -#define LEDC_HPOINT_HSCH0 0x000FFFFF -#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S)) -#define LEDC_HPOINT_HSCH0_V 0xFFFFF -#define LEDC_HPOINT_HSCH0_S 0 - -#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) -/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH0 0x01FFFFFF -#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) -#define LEDC_DUTY_HSCH0_V 0x1FFFFFF -#define LEDC_DUTY_HSCH0_S 0 - -#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) -/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 - has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH0 (BIT(31)) -#define LEDC_DUTY_START_HSCH0_M (BIT(31)) -#define LEDC_DUTY_START_HSCH0_V 0x1 -#define LEDC_DUTY_START_HSCH0_S 31 -/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel0.*/ -#define LEDC_DUTY_INC_HSCH0 (BIT(30)) -#define LEDC_DUTY_INC_HSCH0_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH0_V 0x1 -#define LEDC_DUTY_INC_HSCH0_S 30 -/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel0.*/ -#define LEDC_DUTY_NUM_HSCH0 0x000003FF -#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S)) -#define LEDC_DUTY_NUM_HSCH0_V 0x3FF -#define LEDC_DUTY_NUM_HSCH0_S 20 -/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch0 cycles for high speed channel0.*/ -#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S)) -#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH0_S 10 -/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel0.*/ -#define LEDC_DUTY_SCALE_HSCH0 0x000003FF -#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S)) -#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH0_S 0 - -#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) -/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel0.*/ -#define LEDC_DUTY_HSCH0 0x01FFFFFF -#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) -#define LEDC_DUTY_HSCH0_V 0x1FFFFFF -#define LEDC_DUTY_HSCH0_S 0 - -#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) -/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel1 is off.*/ -#define LEDC_IDLE_LV_HSCH1 (BIT(3)) -#define LEDC_IDLE_LV_HSCH1_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH1_V 0x1 -#define LEDC_IDLE_LV_HSCH1_S 3 -/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel1*/ -#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH1_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH1_S 2 -/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH1 0x00000003 -#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S)) -#define LEDC_TIMER_SEL_HSCH1_V 0x3 -#define LEDC_TIMER_SEL_HSCH1_S 0 - -#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) -/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/ -#define LEDC_HPOINT_HSCH1 0x000FFFFF -#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S)) -#define LEDC_HPOINT_HSCH1_V 0xFFFFF -#define LEDC_HPOINT_HSCH1_S 0 - -#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) -/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH1 0x01FFFFFF -#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) -#define LEDC_DUTY_HSCH1_V 0x1FFFFFF -#define LEDC_DUTY_HSCH1_S 0 - -#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) -/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH1 (BIT(31)) -#define LEDC_DUTY_START_HSCH1_M (BIT(31)) -#define LEDC_DUTY_START_HSCH1_V 0x1 -#define LEDC_DUTY_START_HSCH1_S 31 -/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel1.*/ -#define LEDC_DUTY_INC_HSCH1 (BIT(30)) -#define LEDC_DUTY_INC_HSCH1_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH1_V 0x1 -#define LEDC_DUTY_INC_HSCH1_S 30 -/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel1.*/ -#define LEDC_DUTY_NUM_HSCH1 0x000003FF -#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S)) -#define LEDC_DUTY_NUM_HSCH1_V 0x3FF -#define LEDC_DUTY_NUM_HSCH1_S 20 -/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch1 cycles for high speed channel1.*/ -#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S)) -#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH1_S 10 -/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel1.*/ -#define LEDC_DUTY_SCALE_HSCH1 0x000003FF -#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S)) -#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH1_S 0 - -#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) -/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel1.*/ -#define LEDC_DUTY_HSCH1 0x01FFFFFF -#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) -#define LEDC_DUTY_HSCH1_V 0x1FFFFFF -#define LEDC_DUTY_HSCH1_S 0 - -#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) -/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel2 is off.*/ -#define LEDC_IDLE_LV_HSCH2 (BIT(3)) -#define LEDC_IDLE_LV_HSCH2_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH2_V 0x1 -#define LEDC_IDLE_LV_HSCH2_S 3 -/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel2*/ -#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH2_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH2_S 2 -/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH2 0x00000003 -#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S)) -#define LEDC_TIMER_SEL_HSCH2_V 0x3 -#define LEDC_TIMER_SEL_HSCH2_S 0 - -#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) -/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/ -#define LEDC_HPOINT_HSCH2 0x000FFFFF -#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S)) -#define LEDC_HPOINT_HSCH2_V 0xFFFFF -#define LEDC_HPOINT_HSCH2_S 0 - -#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) -/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH2 0x01FFFFFF -#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) -#define LEDC_DUTY_HSCH2_V 0x1FFFFFF -#define LEDC_DUTY_HSCH2_S 0 - -#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) -/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 - has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH2 (BIT(31)) -#define LEDC_DUTY_START_HSCH2_M (BIT(31)) -#define LEDC_DUTY_START_HSCH2_V 0x1 -#define LEDC_DUTY_START_HSCH2_S 31 -/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel2.*/ -#define LEDC_DUTY_INC_HSCH2 (BIT(30)) -#define LEDC_DUTY_INC_HSCH2_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH2_V 0x1 -#define LEDC_DUTY_INC_HSCH2_S 30 -/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel2.*/ -#define LEDC_DUTY_NUM_HSCH2 0x000003FF -#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S)) -#define LEDC_DUTY_NUM_HSCH2_V 0x3FF -#define LEDC_DUTY_NUM_HSCH2_S 20 -/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch2 cycles for high speed channel2.*/ -#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S)) -#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH2_S 10 -/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel2.*/ -#define LEDC_DUTY_SCALE_HSCH2 0x000003FF -#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S)) -#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH2_S 0 - -#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) -/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel2.*/ -#define LEDC_DUTY_HSCH2 0x01FFFFFF -#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) -#define LEDC_DUTY_HSCH2_V 0x1FFFFFF -#define LEDC_DUTY_HSCH2_S 0 - -#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) -/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel3 is off.*/ -#define LEDC_IDLE_LV_HSCH3 (BIT(3)) -#define LEDC_IDLE_LV_HSCH3_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH3_V 0x1 -#define LEDC_IDLE_LV_HSCH3_S 3 -/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel3*/ -#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH3_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH3_S 2 -/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH3 0x00000003 -#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S)) -#define LEDC_TIMER_SEL_HSCH3_V 0x3 -#define LEDC_TIMER_SEL_HSCH3_S 0 - -#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) -/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/ -#define LEDC_HPOINT_HSCH3 0x000FFFFF -#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S)) -#define LEDC_HPOINT_HSCH3_V 0xFFFFF -#define LEDC_HPOINT_HSCH3_S 0 - -#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) -/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH3 0x01FFFFFF -#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) -#define LEDC_DUTY_HSCH3_V 0x1FFFFFF -#define LEDC_DUTY_HSCH3_S 0 - -#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) -/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 - has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH3 (BIT(31)) -#define LEDC_DUTY_START_HSCH3_M (BIT(31)) -#define LEDC_DUTY_START_HSCH3_V 0x1 -#define LEDC_DUTY_START_HSCH3_S 31 -/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel3.*/ -#define LEDC_DUTY_INC_HSCH3 (BIT(30)) -#define LEDC_DUTY_INC_HSCH3_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH3_V 0x1 -#define LEDC_DUTY_INC_HSCH3_S 30 -/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel3.*/ -#define LEDC_DUTY_NUM_HSCH3 0x000003FF -#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S)) -#define LEDC_DUTY_NUM_HSCH3_V 0x3FF -#define LEDC_DUTY_NUM_HSCH3_S 20 -/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch3 cycles for high speed channel3.*/ -#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S)) -#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH3_S 10 -/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel3.*/ -#define LEDC_DUTY_SCALE_HSCH3 0x000003FF -#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S)) -#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH3_S 0 - -#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) -/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel3.*/ -#define LEDC_DUTY_HSCH3 0x01FFFFFF -#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) -#define LEDC_DUTY_HSCH3_V 0x1FFFFFF -#define LEDC_DUTY_HSCH3_S 0 - -#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) -/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel4 is off.*/ -#define LEDC_IDLE_LV_HSCH4 (BIT(3)) -#define LEDC_IDLE_LV_HSCH4_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH4_V 0x1 -#define LEDC_IDLE_LV_HSCH4_S 3 -/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel4*/ -#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH4_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH4_S 2 -/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH4 0x00000003 -#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S)) -#define LEDC_TIMER_SEL_HSCH4_V 0x3 -#define LEDC_TIMER_SEL_HSCH4_S 0 - -#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) -/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/ -#define LEDC_HPOINT_HSCH4 0x000FFFFF -#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S)) -#define LEDC_HPOINT_HSCH4_V 0xFFFFF -#define LEDC_HPOINT_HSCH4_S 0 - -#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) -/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH4 0x01FFFFFF -#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) -#define LEDC_DUTY_HSCH4_V 0x1FFFFFF -#define LEDC_DUTY_HSCH4_S 0 - -#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) -/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH4 (BIT(31)) -#define LEDC_DUTY_START_HSCH4_M (BIT(31)) -#define LEDC_DUTY_START_HSCH4_V 0x1 -#define LEDC_DUTY_START_HSCH4_S 31 -/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel4.*/ -#define LEDC_DUTY_INC_HSCH4 (BIT(30)) -#define LEDC_DUTY_INC_HSCH4_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH4_V 0x1 -#define LEDC_DUTY_INC_HSCH4_S 30 -/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel1.*/ -#define LEDC_DUTY_NUM_HSCH4 0x000003FF -#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S)) -#define LEDC_DUTY_NUM_HSCH4_V 0x3FF -#define LEDC_DUTY_NUM_HSCH4_S 20 -/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch4 cycles for high speed channel4.*/ -#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S)) -#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH4_S 10 -/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel4.*/ -#define LEDC_DUTY_SCALE_HSCH4 0x000003FF -#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S)) -#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH4_S 0 - -#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) -/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel4.*/ -#define LEDC_DUTY_HSCH4 0x01FFFFFF -#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) -#define LEDC_DUTY_HSCH4_V 0x1FFFFFF -#define LEDC_DUTY_HSCH4_S 0 - -#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) -/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel5 is off.*/ -#define LEDC_IDLE_LV_HSCH5 (BIT(3)) -#define LEDC_IDLE_LV_HSCH5_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH5_V 0x1 -#define LEDC_IDLE_LV_HSCH5_S 3 -/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel5.*/ -#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH5_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH5_S 2 -/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH5 0x00000003 -#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S)) -#define LEDC_TIMER_SEL_HSCH5_V 0x3 -#define LEDC_TIMER_SEL_HSCH5_S 0 - -#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) -/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/ -#define LEDC_HPOINT_HSCH5 0x000FFFFF -#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S)) -#define LEDC_HPOINT_HSCH5_V 0xFFFFF -#define LEDC_HPOINT_HSCH5_S 0 - -#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) -/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH5 0x01FFFFFF -#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) -#define LEDC_DUTY_HSCH5_V 0x1FFFFFF -#define LEDC_DUTY_HSCH5_S 0 - -#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) -/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5 - has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH5 (BIT(31)) -#define LEDC_DUTY_START_HSCH5_M (BIT(31)) -#define LEDC_DUTY_START_HSCH5_V 0x1 -#define LEDC_DUTY_START_HSCH5_S 31 -/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel5.*/ -#define LEDC_DUTY_INC_HSCH5 (BIT(30)) -#define LEDC_DUTY_INC_HSCH5_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH5_V 0x1 -#define LEDC_DUTY_INC_HSCH5_S 30 -/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel5.*/ -#define LEDC_DUTY_NUM_HSCH5 0x000003FF -#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S)) -#define LEDC_DUTY_NUM_HSCH5_V 0x3FF -#define LEDC_DUTY_NUM_HSCH5_S 20 -/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch5 cycles for high speed channel5.*/ -#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S)) -#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH5_S 10 -/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel5.*/ -#define LEDC_DUTY_SCALE_HSCH5 0x000003FF -#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S)) -#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH5_S 0 - -#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) -/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel5.*/ -#define LEDC_DUTY_HSCH5 0x01FFFFFF -#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) -#define LEDC_DUTY_HSCH5_V 0x1FFFFFF -#define LEDC_DUTY_HSCH5_S 0 - -#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078) -/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel6 is off.*/ -#define LEDC_IDLE_LV_HSCH6 (BIT(3)) -#define LEDC_IDLE_LV_HSCH6_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH6_V 0x1 -#define LEDC_IDLE_LV_HSCH6_S 3 -/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel6*/ -#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH6_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH6_S 2 -/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH6 0x00000003 -#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S)) -#define LEDC_TIMER_SEL_HSCH6_V 0x3 -#define LEDC_TIMER_SEL_HSCH6_S 0 - -#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C) -/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/ -#define LEDC_HPOINT_HSCH6 0x000FFFFF -#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S)) -#define LEDC_HPOINT_HSCH6_V 0xFFFFF -#define LEDC_HPOINT_HSCH6_S 0 - -#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080) -/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH6 0x01FFFFFF -#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) -#define LEDC_DUTY_HSCH6_V 0x1FFFFFF -#define LEDC_DUTY_HSCH6_S 0 - -#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084) -/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH6 (BIT(31)) -#define LEDC_DUTY_START_HSCH6_M (BIT(31)) -#define LEDC_DUTY_START_HSCH6_V 0x1 -#define LEDC_DUTY_START_HSCH6_S 31 -/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel6.*/ -#define LEDC_DUTY_INC_HSCH6 (BIT(30)) -#define LEDC_DUTY_INC_HSCH6_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH6_V 0x1 -#define LEDC_DUTY_INC_HSCH6_S 30 -/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel6.*/ -#define LEDC_DUTY_NUM_HSCH6 0x000003FF -#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S)) -#define LEDC_DUTY_NUM_HSCH6_V 0x3FF -#define LEDC_DUTY_NUM_HSCH6_S 20 -/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch6 cycles for high speed channel6.*/ -#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S)) -#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH6_S 10 -/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel6.*/ -#define LEDC_DUTY_SCALE_HSCH6 0x000003FF -#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S)) -#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH6_S 0 - -#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088) -/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel6.*/ -#define LEDC_DUTY_HSCH6 0x01FFFFFF -#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) -#define LEDC_DUTY_HSCH6_V 0x1FFFFFF -#define LEDC_DUTY_HSCH6_S 0 - -#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C) -/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel7 is off.*/ -#define LEDC_IDLE_LV_HSCH7 (BIT(3)) -#define LEDC_IDLE_LV_HSCH7_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH7_V 0x1 -#define LEDC_IDLE_LV_HSCH7_S 3 -/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel7.*/ -#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH7_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH7_S 2 -/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH7 0x00000003 -#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S)) -#define LEDC_TIMER_SEL_HSCH7_V 0x3 -#define LEDC_TIMER_SEL_HSCH7_S 0 - -#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090) -/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/ -#define LEDC_HPOINT_HSCH7 0x000FFFFF -#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S)) -#define LEDC_HPOINT_HSCH7_V 0xFFFFF -#define LEDC_HPOINT_HSCH7_S 0 - -#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094) -/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH7 0x01FFFFFF -#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) -#define LEDC_DUTY_HSCH7_V 0x1FFFFFF -#define LEDC_DUTY_HSCH7_S 0 - -#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098) -/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH7 (BIT(31)) -#define LEDC_DUTY_START_HSCH7_M (BIT(31)) -#define LEDC_DUTY_START_HSCH7_V 0x1 -#define LEDC_DUTY_START_HSCH7_S 31 -/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel6.*/ -#define LEDC_DUTY_INC_HSCH7 (BIT(30)) -#define LEDC_DUTY_INC_HSCH7_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH7_V 0x1 -#define LEDC_DUTY_INC_HSCH7_S 30 -/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel6.*/ -#define LEDC_DUTY_NUM_HSCH7 0x000003FF -#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S)) -#define LEDC_DUTY_NUM_HSCH7_V 0x3FF -#define LEDC_DUTY_NUM_HSCH7_S 20 -/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch7 cycles for high speed channel7.*/ -#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S)) -#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH7_S 10 -/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel7.*/ -#define LEDC_DUTY_SCALE_HSCH7 0x000003FF -#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S)) -#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH7_S 0 - -#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C) -/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel7.*/ -#define LEDC_DUTY_HSCH7 0x01FFFFFF -#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) -#define LEDC_DUTY_HSCH7_V 0x1FFFFFF -#define LEDC_DUTY_HSCH7_S 0 - -#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0) -/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY - for low speed channel0.*/ -#define LEDC_PARA_UP_LSCH0 (BIT(4)) -#define LEDC_PARA_UP_LSCH0_M (BIT(4)) -#define LEDC_PARA_UP_LSCH0_V 0x1 -#define LEDC_PARA_UP_LSCH0_S 4 -/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel0 is off.*/ -#define LEDC_IDLE_LV_LSCH0 (BIT(3)) -#define LEDC_IDLE_LV_LSCH0_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH0_V 0x1 -#define LEDC_IDLE_LV_LSCH0_S 3 -/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel0.*/ -#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH0_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH0_S 2 -/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH0 0x00000003 -#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S)) -#define LEDC_TIMER_SEL_LSCH0_V 0x3 -#define LEDC_TIMER_SEL_LSCH0_S 0 - -#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4) -/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/ -#define LEDC_HPOINT_LSCH0 0x000FFFFF -#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S)) -#define LEDC_HPOINT_LSCH0_V 0xFFFFF -#define LEDC_HPOINT_LSCH0_S 0 - -#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8) -/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH0 0x01FFFFFF -#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) -#define LEDC_DUTY_LSCH0_V 0x1FFFFFF -#define LEDC_DUTY_LSCH0_S 0 - -#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC) -/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH0 (BIT(31)) -#define LEDC_DUTY_START_LSCH0_M (BIT(31)) -#define LEDC_DUTY_START_LSCH0_V 0x1 -#define LEDC_DUTY_START_LSCH0_S 31 -/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel6.*/ -#define LEDC_DUTY_INC_LSCH0 (BIT(30)) -#define LEDC_DUTY_INC_LSCH0_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH0_V 0x1 -#define LEDC_DUTY_INC_LSCH0_S 30 -/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel6.*/ -#define LEDC_DUTY_NUM_LSCH0 0x000003FF -#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S)) -#define LEDC_DUTY_NUM_LSCH0_V 0x3FF -#define LEDC_DUTY_NUM_LSCH0_S 20 -/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch0 cycles for low speed channel0.*/ -#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S)) -#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH0_S 10 -/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel0.*/ -#define LEDC_DUTY_SCALE_LSCH0 0x000003FF -#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S)) -#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH0_S 0 - -#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0) -/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel0.*/ -#define LEDC_DUTY_LSCH0 0x01FFFFFF -#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) -#define LEDC_DUTY_LSCH0_V 0x1FFFFFF -#define LEDC_DUTY_LSCH0_S 0 - -#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4) -/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY - for low speed channel1.*/ -#define LEDC_PARA_UP_LSCH1 (BIT(4)) -#define LEDC_PARA_UP_LSCH1_M (BIT(4)) -#define LEDC_PARA_UP_LSCH1_V 0x1 -#define LEDC_PARA_UP_LSCH1_S 4 -/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel1 is off.*/ -#define LEDC_IDLE_LV_LSCH1 (BIT(3)) -#define LEDC_IDLE_LV_LSCH1_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH1_V 0x1 -#define LEDC_IDLE_LV_LSCH1_S 3 -/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel1.*/ -#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH1_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH1_S 2 -/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH1 0x00000003 -#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S)) -#define LEDC_TIMER_SEL_LSCH1_V 0x3 -#define LEDC_TIMER_SEL_LSCH1_S 0 - -#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8) -/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/ -#define LEDC_HPOINT_LSCH1 0x000FFFFF -#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S)) -#define LEDC_HPOINT_LSCH1_V 0xFFFFF -#define LEDC_HPOINT_LSCH1_S 0 - -#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC) -/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH1 0x01FFFFFF -#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) -#define LEDC_DUTY_LSCH1_V 0x1FFFFFF -#define LEDC_DUTY_LSCH1_S 0 - -#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0) -/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH1 (BIT(31)) -#define LEDC_DUTY_START_LSCH1_M (BIT(31)) -#define LEDC_DUTY_START_LSCH1_V 0x1 -#define LEDC_DUTY_START_LSCH1_S 31 -/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel1.*/ -#define LEDC_DUTY_INC_LSCH1 (BIT(30)) -#define LEDC_DUTY_INC_LSCH1_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH1_V 0x1 -#define LEDC_DUTY_INC_LSCH1_S 30 -/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel1.*/ -#define LEDC_DUTY_NUM_LSCH1 0x000003FF -#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S)) -#define LEDC_DUTY_NUM_LSCH1_V 0x3FF -#define LEDC_DUTY_NUM_LSCH1_S 20 -/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch1 cycles for low speed channel1.*/ -#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S)) -#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH1_S 10 -/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel1.*/ -#define LEDC_DUTY_SCALE_LSCH1 0x000003FF -#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S)) -#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH1_S 0 - -#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4) -/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel1.*/ -#define LEDC_DUTY_LSCH1 0x01FFFFFF -#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) -#define LEDC_DUTY_LSCH1_V 0x1FFFFFF -#define LEDC_DUTY_LSCH1_S 0 - -#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8) -/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY - for low speed channel2.*/ -#define LEDC_PARA_UP_LSCH2 (BIT(4)) -#define LEDC_PARA_UP_LSCH2_M (BIT(4)) -#define LEDC_PARA_UP_LSCH2_V 0x1 -#define LEDC_PARA_UP_LSCH2_S 4 -/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel2 is off.*/ -#define LEDC_IDLE_LV_LSCH2 (BIT(3)) -#define LEDC_IDLE_LV_LSCH2_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH2_V 0x1 -#define LEDC_IDLE_LV_LSCH2_S 3 -/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel2.*/ -#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH2_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH2_S 2 -/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH2 0x00000003 -#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S)) -#define LEDC_TIMER_SEL_LSCH2_V 0x3 -#define LEDC_TIMER_SEL_LSCH2_S 0 - -#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC) -/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/ -#define LEDC_HPOINT_LSCH2 0x000FFFFF -#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S)) -#define LEDC_HPOINT_LSCH2_V 0xFFFFF -#define LEDC_HPOINT_LSCH2_S 0 - -#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0) -/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH2 0x01FFFFFF -#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) -#define LEDC_DUTY_LSCH2_V 0x1FFFFFF -#define LEDC_DUTY_LSCH2_S 0 - -#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4) -/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 - has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH2 (BIT(31)) -#define LEDC_DUTY_START_LSCH2_M (BIT(31)) -#define LEDC_DUTY_START_LSCH2_V 0x1 -#define LEDC_DUTY_START_LSCH2_S 31 -/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel2.*/ -#define LEDC_DUTY_INC_LSCH2 (BIT(30)) -#define LEDC_DUTY_INC_LSCH2_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH2_V 0x1 -#define LEDC_DUTY_INC_LSCH2_S 30 -/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel2.*/ -#define LEDC_DUTY_NUM_LSCH2 0x000003FF -#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S)) -#define LEDC_DUTY_NUM_LSCH2_V 0x3FF -#define LEDC_DUTY_NUM_LSCH2_S 20 -/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch2 cycles for low speed channel2.*/ -#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S)) -#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH2_S 10 -/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel2.*/ -#define LEDC_DUTY_SCALE_LSCH2 0x000003FF -#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S)) -#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH2_S 0 - -#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8) -/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel2.*/ -#define LEDC_DUTY_LSCH2 0x01FFFFFF -#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) -#define LEDC_DUTY_LSCH2_V 0x1FFFFFF -#define LEDC_DUTY_LSCH2_S 0 - -#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC) -/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY - for low speed channel3.*/ -#define LEDC_PARA_UP_LSCH3 (BIT(4)) -#define LEDC_PARA_UP_LSCH3_M (BIT(4)) -#define LEDC_PARA_UP_LSCH3_V 0x1 -#define LEDC_PARA_UP_LSCH3_S 4 -/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel3 is off.*/ -#define LEDC_IDLE_LV_LSCH3 (BIT(3)) -#define LEDC_IDLE_LV_LSCH3_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH3_V 0x1 -#define LEDC_IDLE_LV_LSCH3_S 3 -/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel3.*/ -#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH3_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH3_S 2 -/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH3 0x00000003 -#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S)) -#define LEDC_TIMER_SEL_LSCH3_V 0x3 -#define LEDC_TIMER_SEL_LSCH3_S 0 - -#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0) -/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/ -#define LEDC_HPOINT_LSCH3 0x000FFFFF -#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S)) -#define LEDC_HPOINT_LSCH3_V 0xFFFFF -#define LEDC_HPOINT_LSCH3_S 0 - -#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4) -/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH3 0x01FFFFFF -#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) -#define LEDC_DUTY_LSCH3_V 0x1FFFFFF -#define LEDC_DUTY_LSCH3_S 0 - -#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8) -/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 - has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH3 (BIT(31)) -#define LEDC_DUTY_START_LSCH3_M (BIT(31)) -#define LEDC_DUTY_START_LSCH3_V 0x1 -#define LEDC_DUTY_START_LSCH3_S 31 -/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel3.*/ -#define LEDC_DUTY_INC_LSCH3 (BIT(30)) -#define LEDC_DUTY_INC_LSCH3_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH3_V 0x1 -#define LEDC_DUTY_INC_LSCH3_S 30 -/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel3.*/ -#define LEDC_DUTY_NUM_LSCH3 0x000003FF -#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S)) -#define LEDC_DUTY_NUM_LSCH3_V 0x3FF -#define LEDC_DUTY_NUM_LSCH3_S 20 -/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch3 cycles for low speed channel3.*/ -#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S)) -#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH3_S 10 -/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel3.*/ -#define LEDC_DUTY_SCALE_LSCH3 0x000003FF -#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S)) -#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH3_S 0 - -#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC) -/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel3.*/ -#define LEDC_DUTY_LSCH3 0x01FFFFFF -#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) -#define LEDC_DUTY_LSCH3_V 0x1FFFFFF -#define LEDC_DUTY_LSCH3_S 0 - -#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0) -/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY - for low speed channel4.*/ -#define LEDC_PARA_UP_LSCH4 (BIT(4)) -#define LEDC_PARA_UP_LSCH4_M (BIT(4)) -#define LEDC_PARA_UP_LSCH4_V 0x1 -#define LEDC_PARA_UP_LSCH4_S 4 -/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel4 is off.*/ -#define LEDC_IDLE_LV_LSCH4 (BIT(3)) -#define LEDC_IDLE_LV_LSCH4_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH4_V 0x1 -#define LEDC_IDLE_LV_LSCH4_S 3 -/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel4.*/ -#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH4_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH4_S 2 -/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH4 0x00000003 -#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S)) -#define LEDC_TIMER_SEL_LSCH4_V 0x3 -#define LEDC_TIMER_SEL_LSCH4_S 0 - -#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4) -/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/ -#define LEDC_HPOINT_LSCH4 0x000FFFFF -#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S)) -#define LEDC_HPOINT_LSCH4_V 0xFFFFF -#define LEDC_HPOINT_LSCH4_S 0 - -#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8) -/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH4 0x01FFFFFF -#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) -#define LEDC_DUTY_LSCH4_V 0x1FFFFFF -#define LEDC_DUTY_LSCH4_S 0 - -#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC) -/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 - has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH4 (BIT(31)) -#define LEDC_DUTY_START_LSCH4_M (BIT(31)) -#define LEDC_DUTY_START_LSCH4_V 0x1 -#define LEDC_DUTY_START_LSCH4_S 31 -/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel4.*/ -#define LEDC_DUTY_INC_LSCH4 (BIT(30)) -#define LEDC_DUTY_INC_LSCH4_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH4_V 0x1 -#define LEDC_DUTY_INC_LSCH4_S 30 -/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel4.*/ -#define LEDC_DUTY_NUM_LSCH4 0x000003FF -#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S)) -#define LEDC_DUTY_NUM_LSCH4_V 0x3FF -#define LEDC_DUTY_NUM_LSCH4_S 20 -/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch4 cycles for low speed channel4.*/ -#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S)) -#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH4_S 10 -/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel4.*/ -#define LEDC_DUTY_SCALE_LSCH4 0x000003FF -#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S)) -#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH4_S 0 - -#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100) -/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel4.*/ -#define LEDC_DUTY_LSCH4 0x01FFFFFF -#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) -#define LEDC_DUTY_LSCH4_V 0x1FFFFFF -#define LEDC_DUTY_LSCH4_S 0 - -#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104) -/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY - for low speed channel5.*/ -#define LEDC_PARA_UP_LSCH5 (BIT(4)) -#define LEDC_PARA_UP_LSCH5_M (BIT(4)) -#define LEDC_PARA_UP_LSCH5_V 0x1 -#define LEDC_PARA_UP_LSCH5_S 4 -/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel5 is off.*/ -#define LEDC_IDLE_LV_LSCH5 (BIT(3)) -#define LEDC_IDLE_LV_LSCH5_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH5_V 0x1 -#define LEDC_IDLE_LV_LSCH5_S 3 -/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel5.*/ -#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH5_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH5_S 2 -/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH5 0x00000003 -#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S)) -#define LEDC_TIMER_SEL_LSCH5_V 0x3 -#define LEDC_TIMER_SEL_LSCH5_S 0 - -#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108) -/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/ -#define LEDC_HPOINT_LSCH5 0x000FFFFF -#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S)) -#define LEDC_HPOINT_LSCH5_V 0xFFFFF -#define LEDC_HPOINT_LSCH5_S 0 - -#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C) -/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH5 0x01FFFFFF -#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) -#define LEDC_DUTY_LSCH5_V 0x1FFFFFF -#define LEDC_DUTY_LSCH5_S 0 - -#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110) -/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 - has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH5 (BIT(31)) -#define LEDC_DUTY_START_LSCH5_M (BIT(31)) -#define LEDC_DUTY_START_LSCH5_V 0x1 -#define LEDC_DUTY_START_LSCH5_S 31 -/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel5.*/ -#define LEDC_DUTY_INC_LSCH5 (BIT(30)) -#define LEDC_DUTY_INC_LSCH5_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH5_V 0x1 -#define LEDC_DUTY_INC_LSCH5_S 30 -/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel5.*/ -#define LEDC_DUTY_NUM_LSCH5 0x000003FF -#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S)) -#define LEDC_DUTY_NUM_LSCH5_V 0x3FF -#define LEDC_DUTY_NUM_LSCH5_S 20 -/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch5 cycles for low speed channel4.*/ -#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S)) -#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH5_S 10 -/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel5.*/ -#define LEDC_DUTY_SCALE_LSCH5 0x000003FF -#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S)) -#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH5_S 0 - -#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114) -/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel5.*/ -#define LEDC_DUTY_LSCH5 0x01FFFFFF -#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) -#define LEDC_DUTY_LSCH5_V 0x1FFFFFF -#define LEDC_DUTY_LSCH5_S 0 - -#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118) -/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY - for low speed channel6.*/ -#define LEDC_PARA_UP_LSCH6 (BIT(4)) -#define LEDC_PARA_UP_LSCH6_M (BIT(4)) -#define LEDC_PARA_UP_LSCH6_V 0x1 -#define LEDC_PARA_UP_LSCH6_S 4 -/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel6 is off.*/ -#define LEDC_IDLE_LV_LSCH6 (BIT(3)) -#define LEDC_IDLE_LV_LSCH6_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH6_V 0x1 -#define LEDC_IDLE_LV_LSCH6_S 3 -/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel6.*/ -#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH6_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH6_S 2 -/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH6 0x00000003 -#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S)) -#define LEDC_TIMER_SEL_LSCH6_V 0x3 -#define LEDC_TIMER_SEL_LSCH6_S 0 - -#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C) -/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/ -#define LEDC_HPOINT_LSCH6 0x000FFFFF -#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S)) -#define LEDC_HPOINT_LSCH6_V 0xFFFFF -#define LEDC_HPOINT_LSCH6_S 0 - -#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120) -/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH6 0x01FFFFFF -#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) -#define LEDC_DUTY_LSCH6_V 0x1FFFFFF -#define LEDC_DUTY_LSCH6_S 0 - -#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124) -/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6 - has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH6 (BIT(31)) -#define LEDC_DUTY_START_LSCH6_M (BIT(31)) -#define LEDC_DUTY_START_LSCH6_V 0x1 -#define LEDC_DUTY_START_LSCH6_S 31 -/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel6.*/ -#define LEDC_DUTY_INC_LSCH6 (BIT(30)) -#define LEDC_DUTY_INC_LSCH6_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH6_V 0x1 -#define LEDC_DUTY_INC_LSCH6_S 30 -/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel6.*/ -#define LEDC_DUTY_NUM_LSCH6 0x000003FF -#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S)) -#define LEDC_DUTY_NUM_LSCH6_V 0x3FF -#define LEDC_DUTY_NUM_LSCH6_S 20 -/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch6 cycles for low speed channel6.*/ -#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S)) -#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH6_S 10 -/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel6.*/ -#define LEDC_DUTY_SCALE_LSCH6 0x000003FF -#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S)) -#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH6_S 0 - -#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128) -/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel6.*/ -#define LEDC_DUTY_LSCH6 0x01FFFFFF -#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) -#define LEDC_DUTY_LSCH6_V 0x1FFFFFF -#define LEDC_DUTY_LSCH6_S 0 - -#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C) -/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY - for low speed channel7.*/ -#define LEDC_PARA_UP_LSCH7 (BIT(4)) -#define LEDC_PARA_UP_LSCH7_M (BIT(4)) -#define LEDC_PARA_UP_LSCH7_V 0x1 -#define LEDC_PARA_UP_LSCH7_S 4 -/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel7 is off.*/ -#define LEDC_IDLE_LV_LSCH7 (BIT(3)) -#define LEDC_IDLE_LV_LSCH7_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH7_V 0x1 -#define LEDC_IDLE_LV_LSCH7_S 3 -/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel7.*/ -#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH7_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH7_S 2 -/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH7 0x00000003 -#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S)) -#define LEDC_TIMER_SEL_LSCH7_V 0x3 -#define LEDC_TIMER_SEL_LSCH7_S 0 - -#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130) -/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/ -#define LEDC_HPOINT_LSCH7 0x000FFFFF -#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S)) -#define LEDC_HPOINT_LSCH7_V 0xFFFFF -#define LEDC_HPOINT_LSCH7_S 0 - -#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134) -/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH7 0x01FFFFFF -#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) -#define LEDC_DUTY_LSCH7_V 0x1FFFFFF -#define LEDC_DUTY_LSCH7_S 0 - -#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138) -/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 - has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH7 (BIT(31)) -#define LEDC_DUTY_START_LSCH7_M (BIT(31)) -#define LEDC_DUTY_START_LSCH7_V 0x1 -#define LEDC_DUTY_START_LSCH7_S 31 -/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel4.*/ -#define LEDC_DUTY_INC_LSCH7 (BIT(30)) -#define LEDC_DUTY_INC_LSCH7_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH7_V 0x1 -#define LEDC_DUTY_INC_LSCH7_S 30 -/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel4.*/ -#define LEDC_DUTY_NUM_LSCH7 0x000003FF -#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S)) -#define LEDC_DUTY_NUM_LSCH7_V 0x3FF -#define LEDC_DUTY_NUM_LSCH7_S 20 -/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch7 cycles for low speed channel7.*/ -#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S)) -#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH7_S 10 -/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel7.*/ -#define LEDC_DUTY_SCALE_LSCH7 0x000003FF -#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S)) -#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH7_S 0 - -#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C) -/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel7.*/ -#define LEDC_DUTY_LSCH7 0x01FFFFFF -#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) -#define LEDC_DUTY_LSCH7_V 0x1FFFFFF -#define LEDC_DUTY_LSCH7_S 0 - -#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140) -/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer0. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER0 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER0_V 0x1 -#define LEDC_TICK_SEL_HSTIMER0_S 25 -/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER0_RST (BIT(24)) -#define LEDC_HSTIMER0_RST_M (BIT(24)) -#define LEDC_HSTIMER0_RST_V 0x1 -#define LEDC_HSTIMER0_RST_S 24 -/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer0*/ -#define LEDC_HSTIMER0_PAUSE (BIT(23)) -#define LEDC_HSTIMER0_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER0_PAUSE_V 0x1 -#define LEDC_HSTIMER0_PAUSE_S 23 -/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in high - speed timer0 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF -#define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S)) -#define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF -#define LEDC_DIV_NUM_HSTIMER0_S 5 -/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in high speed - timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ -#define LEDC_HSTIMER0_LIM 0x0000001F -#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S)) -#define LEDC_HSTIMER0_LIM_V 0x1F -#define LEDC_HSTIMER0_LIM_S 0 - -#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144) -/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer0*/ -#define LEDC_HSTIMER0_CNT 0x000FFFFF -#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S)) -#define LEDC_HSTIMER0_CNT_V 0xFFFFF -#define LEDC_HSTIMER0_CNT_S 0 - -#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148) -/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer1. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER1 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER1_V 0x1 -#define LEDC_TICK_SEL_HSTIMER1_S 25 -/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER1_RST (BIT(24)) -#define LEDC_HSTIMER1_RST_M (BIT(24)) -#define LEDC_HSTIMER1_RST_V 0x1 -#define LEDC_HSTIMER1_RST_S 24 -/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer1*/ -#define LEDC_HSTIMER1_PAUSE (BIT(23)) -#define LEDC_HSTIMER1_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER1_PAUSE_V 0x1 -#define LEDC_HSTIMER1_PAUSE_S 23 -/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in high - speed timer1 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF -#define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S)) -#define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF -#define LEDC_DIV_NUM_HSTIMER1_S 5 -/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in high speed - timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/ -#define LEDC_HSTIMER1_LIM 0x0000001F -#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S)) -#define LEDC_HSTIMER1_LIM_V 0x1F -#define LEDC_HSTIMER1_LIM_S 0 - -#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C) -/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer1.*/ -#define LEDC_HSTIMER1_CNT 0x000FFFFF -#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S)) -#define LEDC_HSTIMER1_CNT_V 0xFFFFF -#define LEDC_HSTIMER1_CNT_S 0 - -#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150) -/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer2. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER2 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER2_V 0x1 -#define LEDC_TICK_SEL_HSTIMER2_S 25 -/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER2_RST (BIT(24)) -#define LEDC_HSTIMER2_RST_M (BIT(24)) -#define LEDC_HSTIMER2_RST_V 0x1 -#define LEDC_HSTIMER2_RST_S 24 -/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer2*/ -#define LEDC_HSTIMER2_PAUSE (BIT(23)) -#define LEDC_HSTIMER2_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER2_PAUSE_V 0x1 -#define LEDC_HSTIMER2_PAUSE_S 23 -/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in high - speed timer2 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF -#define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S)) -#define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF -#define LEDC_DIV_NUM_HSTIMER2_S 5 -/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in high speed - timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/ -#define LEDC_HSTIMER2_LIM 0x0000001F -#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S)) -#define LEDC_HSTIMER2_LIM_V 0x1F -#define LEDC_HSTIMER2_LIM_S 0 - -#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154) -/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer2*/ -#define LEDC_HSTIMER2_CNT 0x000FFFFF -#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S)) -#define LEDC_HSTIMER2_CNT_V 0xFFFFF -#define LEDC_HSTIMER2_CNT_S 0 - -#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158) -/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer3. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER3 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER3_V 0x1 -#define LEDC_TICK_SEL_HSTIMER3_S 25 -/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER3_RST (BIT(24)) -#define LEDC_HSTIMER3_RST_M (BIT(24)) -#define LEDC_HSTIMER3_RST_V 0x1 -#define LEDC_HSTIMER3_RST_S 24 -/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer3*/ -#define LEDC_HSTIMER3_PAUSE (BIT(23)) -#define LEDC_HSTIMER3_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER3_PAUSE_V 0x1 -#define LEDC_HSTIMER3_PAUSE_S 23 -/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in high - speed timer3 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF -#define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S)) -#define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF -#define LEDC_DIV_NUM_HSTIMER3_S 5 -/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in high speed - timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/ -#define LEDC_HSTIMER3_LIM 0x0000001F -#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S)) -#define LEDC_HSTIMER3_LIM_V 0x1F -#define LEDC_HSTIMER3_LIM_S 0 - -#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C) -/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer3*/ -#define LEDC_HSTIMER3_CNT 0x000FFFFF -#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S)) -#define LEDC_HSTIMER3_CNT_V 0xFFFFF -#define LEDC_HSTIMER3_CNT_S 0 - -#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160) -/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ -#define LEDC_LSTIMER0_PARA_UP (BIT(26)) -#define LEDC_LSTIMER0_PARA_UP_M (BIT(26)) -#define LEDC_LSTIMER0_PARA_UP_V 0x1 -#define LEDC_LSTIMER0_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer0. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER0 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER0_V 0x1 -#define LEDC_TICK_SEL_LSTIMER0_S 25 -/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER0_RST (BIT(24)) -#define LEDC_LSTIMER0_RST_M (BIT(24)) -#define LEDC_LSTIMER0_RST_V 0x1 -#define LEDC_LSTIMER0_RST_S 24 -/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer0.*/ -#define LEDC_LSTIMER0_PAUSE (BIT(23)) -#define LEDC_LSTIMER0_PAUSE_M (BIT(23)) -#define LEDC_LSTIMER0_PAUSE_V 0x1 -#define LEDC_LSTIMER0_PAUSE_S 23 -/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in low - speed timer0 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF -#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S)) -#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF -#define LEDC_DIV_NUM_LSTIMER0_S 5 -/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in low speed - timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ -#define LEDC_LSTIMER0_LIM 0x0000001F -#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S)) -#define LEDC_LSTIMER0_LIM_V 0x1F -#define LEDC_LSTIMER0_LIM_S 0 - -#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164) -/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer0.*/ -#define LEDC_LSTIMER0_CNT 0x000FFFFF -#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S)) -#define LEDC_LSTIMER0_CNT_V 0xFFFFF -#define LEDC_LSTIMER0_CNT_S 0 - -#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168) -/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/ -#define LEDC_LSTIMER1_PARA_UP (BIT(26)) -#define LEDC_LSTIMER1_PARA_UP_M (BIT(26)) -#define LEDC_LSTIMER1_PARA_UP_V 0x1 -#define LEDC_LSTIMER1_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer1. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER1 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER1_V 0x1 -#define LEDC_TICK_SEL_LSTIMER1_S 25 -/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER1_RST (BIT(24)) -#define LEDC_LSTIMER1_RST_M (BIT(24)) -#define LEDC_LSTIMER1_RST_V 0x1 -#define LEDC_LSTIMER1_RST_S 24 -/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer1.*/ -#define LEDC_LSTIMER1_PAUSE (BIT(23)) -#define LEDC_LSTIMER1_PAUSE_M (BIT(23)) -#define LEDC_LSTIMER1_PAUSE_V 0x1 -#define LEDC_LSTIMER1_PAUSE_S 23 -/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in low - speed timer1 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF -#define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S)) -#define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF -#define LEDC_DIV_NUM_LSTIMER1_S 5 -/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in low speed - timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/ -#define LEDC_LSTIMER1_LIM 0x0000001F -#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S)) -#define LEDC_LSTIMER1_LIM_V 0x1F -#define LEDC_LSTIMER1_LIM_S 0 - -#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C) -/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer1.*/ -#define LEDC_LSTIMER1_CNT 0x000FFFFF -#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S)) -#define LEDC_LSTIMER1_CNT_V 0xFFFFF -#define LEDC_LSTIMER1_CNT_S 0 - -#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170) -/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/ -#define LEDC_LSTIMER2_PARA_UP (BIT(26)) -#define LEDC_LSTIMER2_PARA_UP_M (BIT(26)) -#define LEDC_LSTIMER2_PARA_UP_V 0x1 -#define LEDC_LSTIMER2_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer2. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER2 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER2_V 0x1 -#define LEDC_TICK_SEL_LSTIMER2_S 25 -/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER2_RST (BIT(24)) -#define LEDC_LSTIMER2_RST_M (BIT(24)) -#define LEDC_LSTIMER2_RST_V 0x1 -#define LEDC_LSTIMER2_RST_S 24 -/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer2.*/ -#define LEDC_LSTIMER2_PAUSE (BIT(23)) -#define LEDC_LSTIMER2_PAUSE_M (BIT(23)) -#define LEDC_LSTIMER2_PAUSE_V 0x1 -#define LEDC_LSTIMER2_PAUSE_S 23 -/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in low - speed timer2 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF -#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S)) -#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF -#define LEDC_DIV_NUM_LSTIMER2_S 5 -/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in low speed - timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/ -#define LEDC_LSTIMER2_LIM 0x0000001F -#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S)) -#define LEDC_LSTIMER2_LIM_V 0x1F -#define LEDC_LSTIMER2_LIM_S 0 - -#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174) -/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer2.*/ -#define LEDC_LSTIMER2_CNT 0x000FFFFF -#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S)) -#define LEDC_LSTIMER2_CNT_V 0xFFFFF -#define LEDC_LSTIMER2_CNT_S 0 - -#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178) -/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/ -#define LEDC_LSTIMER3_PARA_UP (BIT(26)) -#define LEDC_LSTIMER3_PARA_UP_M (BIT(26)) -#define LEDC_LSTIMER3_PARA_UP_V 0x1 -#define LEDC_LSTIMER3_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer3. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER3 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER3_V 0x1 -#define LEDC_TICK_SEL_LSTIMER3_S 25 -/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER3_RST (BIT(24)) -#define LEDC_LSTIMER3_RST_M (BIT(24)) -#define LEDC_LSTIMER3_RST_V 0x1 -#define LEDC_LSTIMER3_RST_S 24 -/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer3.*/ -#define LEDC_LSTIMER3_PAUSE (BIT(23)) -#define LEDC_LSTIMER3_PAUSE_M (BIT(23)) -#define LEDC_LSTIMER3_PAUSE_V 0x1 -#define LEDC_LSTIMER3_PAUSE_S 23 -/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in low - speed timer3 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF -#define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S)) -#define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF -#define LEDC_DIV_NUM_LSTIMER3_S 5 -/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in low speed - timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/ -#define LEDC_LSTIMER3_LIM 0x0000001F -#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S)) -#define LEDC_LSTIMER3_LIM_V 0x1F -#define LEDC_LSTIMER3_LIM_S 0 - -#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C) -/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer3.*/ -#define LEDC_LSTIMER3_CNT 0x000FFFFF -#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S)) -#define LEDC_LSTIMER3_CNT_V 0xFFFFF -#define LEDC_LSTIMER3_CNT_S 0 - -#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 7 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 6 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 5 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 4 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 3 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 2 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 1 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 0 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 7 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 6 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 5 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 4 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 3 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 2 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 1 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 0 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8 -/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel3 counter overflow.*/ -#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_RAW_S 7 -/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel2 counter overflow.*/ -#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_RAW_S 6 -/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel1 counter overflow.*/ -#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_RAW_S 5 -/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel0 counter overflow.*/ -#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_RAW_S 4 -/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel3 counter overflow.*/ -#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_RAW_S 3 -/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel2 counter overflow.*/ -#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_RAW_S 2 -/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel1 counter overflow.*/ -#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_RAW_S 1 -/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel0 counter overflow.*/ -#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_RAW_S 0 - -#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: The interrupt status bit for low speed channel 7 duty change done event*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 6 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 5 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 4 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 3 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 2 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 1 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 0 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 7 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 6 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 5 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 4 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 3 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 2 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 1 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 0 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8 -/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel3 counter overflow event.*/ -#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_ST_S 7 -/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel2 counter overflow event.*/ -#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_ST_S 6 -/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel1 counter overflow event.*/ -#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_ST_S 5 -/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel0 counter overflow event.*/ -#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_ST_S 4 -/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel3 counter overflow event.*/ -#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_ST_S 3 -/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel2 counter overflow event.*/ -#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_ST_S 2 -/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel1 counter overflow event.*/ -#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_ST_S 1 -/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel0 counter overflow event.*/ -#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_ST_S 0 - -#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8 -/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ -#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_ENA_S 7 -/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ -#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_ENA_S 6 -/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ -#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_ENA_S 5 -/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ -#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_ENA_S 4 -/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ -#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_ENA_S 3 -/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ -#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_ENA_S 2 -/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ -#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_ENA_S 1 -/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ -#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_ENA_S 0 - -#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8 -/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/ -#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_CLR_S 7 -/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/ -#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_CLR_S 6 -/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/ -#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_CLR_S 5 -/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/ -#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_CLR_S 4 -/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/ -#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_CLR_S 3 -/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/ -#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_CLR_S 2 -/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/ -#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_CLR_S 1 -/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/ -#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_CLR_S 0 - -#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190) -/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ -#define LEDC_APB_CLK_SEL (BIT(0)) -#define LEDC_APB_CLK_SEL_M (BIT(0)) -#define LEDC_APB_CLK_SEL_V 0x1 -#define LEDC_APB_CLK_SEL_S 0 - -#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC) -/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */ -/*description: This register represents the version .*/ -#define LEDC_DATE 0xFFFFFFFF -#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) -#define LEDC_DATE_V 0xFFFFFFFF -#define LEDC_DATE_S 0 - - - - -#endif /*_SOC_LEDC_REG_H_ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_LEDC_REG_H_ +#define _SOC_LEDC_REG_H_ + + +#include "soc.h" +#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) +/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: This bit is clock gating control signal. when software config + LED_PWM internal registers it controls the register clock.*/ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (BIT(31)) +#define LEDC_CLK_EN_V 0x1 +#define LEDC_CLK_EN_S 31 +/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel0 is off.*/ +#define LEDC_IDLE_LV_HSCH0 (BIT(3)) +#define LEDC_IDLE_LV_HSCH0_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH0_V 0x1 +#define LEDC_IDLE_LV_HSCH0_S 3 +/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel0*/ +#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH0_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH0_S 2 +/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH0 0x00000003 +#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S)) +#define LEDC_TIMER_SEL_HSCH0_V 0x3 +#define LEDC_TIMER_SEL_HSCH0_S 0 + +#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) +/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/ +#define LEDC_HPOINT_HSCH0 0x000FFFFF +#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S)) +#define LEDC_HPOINT_HSCH0_V 0xFFFFF +#define LEDC_HPOINT_HSCH0_S 0 + +#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) +/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH0 0x01FFFFFF +#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) +#define LEDC_DUTY_HSCH0_V 0x1FFFFFF +#define LEDC_DUTY_HSCH0_S 0 + +#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) +/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 + has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH0 (BIT(31)) +#define LEDC_DUTY_START_HSCH0_M (BIT(31)) +#define LEDC_DUTY_START_HSCH0_V 0x1 +#define LEDC_DUTY_START_HSCH0_S 31 +/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel0.*/ +#define LEDC_DUTY_INC_HSCH0 (BIT(30)) +#define LEDC_DUTY_INC_HSCH0_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH0_V 0x1 +#define LEDC_DUTY_INC_HSCH0_S 30 +/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel0.*/ +#define LEDC_DUTY_NUM_HSCH0 0x000003FF +#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S)) +#define LEDC_DUTY_NUM_HSCH0_V 0x3FF +#define LEDC_DUTY_NUM_HSCH0_S 20 +/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch0 cycles for high speed channel0.*/ +#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S)) +#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH0_S 10 +/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel0.*/ +#define LEDC_DUTY_SCALE_HSCH0 0x000003FF +#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S)) +#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH0_S 0 + +#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) +/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel0.*/ +#define LEDC_DUTY_HSCH0 0x01FFFFFF +#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) +#define LEDC_DUTY_HSCH0_V 0x1FFFFFF +#define LEDC_DUTY_HSCH0_S 0 + +#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) +/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel1 is off.*/ +#define LEDC_IDLE_LV_HSCH1 (BIT(3)) +#define LEDC_IDLE_LV_HSCH1_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH1_V 0x1 +#define LEDC_IDLE_LV_HSCH1_S 3 +/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel1*/ +#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH1_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH1_S 2 +/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH1 0x00000003 +#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S)) +#define LEDC_TIMER_SEL_HSCH1_V 0x3 +#define LEDC_TIMER_SEL_HSCH1_S 0 + +#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) +/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/ +#define LEDC_HPOINT_HSCH1 0x000FFFFF +#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S)) +#define LEDC_HPOINT_HSCH1_V 0xFFFFF +#define LEDC_HPOINT_HSCH1_S 0 + +#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) +/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH1 0x01FFFFFF +#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) +#define LEDC_DUTY_HSCH1_V 0x1FFFFFF +#define LEDC_DUTY_HSCH1_S 0 + +#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) +/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH1 (BIT(31)) +#define LEDC_DUTY_START_HSCH1_M (BIT(31)) +#define LEDC_DUTY_START_HSCH1_V 0x1 +#define LEDC_DUTY_START_HSCH1_S 31 +/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel1.*/ +#define LEDC_DUTY_INC_HSCH1 (BIT(30)) +#define LEDC_DUTY_INC_HSCH1_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH1_V 0x1 +#define LEDC_DUTY_INC_HSCH1_S 30 +/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel1.*/ +#define LEDC_DUTY_NUM_HSCH1 0x000003FF +#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S)) +#define LEDC_DUTY_NUM_HSCH1_V 0x3FF +#define LEDC_DUTY_NUM_HSCH1_S 20 +/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch1 cycles for high speed channel1.*/ +#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S)) +#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH1_S 10 +/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel1.*/ +#define LEDC_DUTY_SCALE_HSCH1 0x000003FF +#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S)) +#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH1_S 0 + +#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) +/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel1.*/ +#define LEDC_DUTY_HSCH1 0x01FFFFFF +#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) +#define LEDC_DUTY_HSCH1_V 0x1FFFFFF +#define LEDC_DUTY_HSCH1_S 0 + +#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) +/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel2 is off.*/ +#define LEDC_IDLE_LV_HSCH2 (BIT(3)) +#define LEDC_IDLE_LV_HSCH2_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH2_V 0x1 +#define LEDC_IDLE_LV_HSCH2_S 3 +/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel2*/ +#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH2_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH2_S 2 +/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH2 0x00000003 +#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S)) +#define LEDC_TIMER_SEL_HSCH2_V 0x3 +#define LEDC_TIMER_SEL_HSCH2_S 0 + +#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) +/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/ +#define LEDC_HPOINT_HSCH2 0x000FFFFF +#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S)) +#define LEDC_HPOINT_HSCH2_V 0xFFFFF +#define LEDC_HPOINT_HSCH2_S 0 + +#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) +/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH2 0x01FFFFFF +#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) +#define LEDC_DUTY_HSCH2_V 0x1FFFFFF +#define LEDC_DUTY_HSCH2_S 0 + +#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) +/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 + has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH2 (BIT(31)) +#define LEDC_DUTY_START_HSCH2_M (BIT(31)) +#define LEDC_DUTY_START_HSCH2_V 0x1 +#define LEDC_DUTY_START_HSCH2_S 31 +/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel2.*/ +#define LEDC_DUTY_INC_HSCH2 (BIT(30)) +#define LEDC_DUTY_INC_HSCH2_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH2_V 0x1 +#define LEDC_DUTY_INC_HSCH2_S 30 +/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel2.*/ +#define LEDC_DUTY_NUM_HSCH2 0x000003FF +#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S)) +#define LEDC_DUTY_NUM_HSCH2_V 0x3FF +#define LEDC_DUTY_NUM_HSCH2_S 20 +/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch2 cycles for high speed channel2.*/ +#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S)) +#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH2_S 10 +/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel2.*/ +#define LEDC_DUTY_SCALE_HSCH2 0x000003FF +#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S)) +#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH2_S 0 + +#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) +/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel2.*/ +#define LEDC_DUTY_HSCH2 0x01FFFFFF +#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) +#define LEDC_DUTY_HSCH2_V 0x1FFFFFF +#define LEDC_DUTY_HSCH2_S 0 + +#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) +/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel3 is off.*/ +#define LEDC_IDLE_LV_HSCH3 (BIT(3)) +#define LEDC_IDLE_LV_HSCH3_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH3_V 0x1 +#define LEDC_IDLE_LV_HSCH3_S 3 +/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel3*/ +#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH3_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH3_S 2 +/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH3 0x00000003 +#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S)) +#define LEDC_TIMER_SEL_HSCH3_V 0x3 +#define LEDC_TIMER_SEL_HSCH3_S 0 + +#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) +/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/ +#define LEDC_HPOINT_HSCH3 0x000FFFFF +#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S)) +#define LEDC_HPOINT_HSCH3_V 0xFFFFF +#define LEDC_HPOINT_HSCH3_S 0 + +#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) +/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH3 0x01FFFFFF +#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) +#define LEDC_DUTY_HSCH3_V 0x1FFFFFF +#define LEDC_DUTY_HSCH3_S 0 + +#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) +/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 + has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH3 (BIT(31)) +#define LEDC_DUTY_START_HSCH3_M (BIT(31)) +#define LEDC_DUTY_START_HSCH3_V 0x1 +#define LEDC_DUTY_START_HSCH3_S 31 +/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel3.*/ +#define LEDC_DUTY_INC_HSCH3 (BIT(30)) +#define LEDC_DUTY_INC_HSCH3_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH3_V 0x1 +#define LEDC_DUTY_INC_HSCH3_S 30 +/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel3.*/ +#define LEDC_DUTY_NUM_HSCH3 0x000003FF +#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S)) +#define LEDC_DUTY_NUM_HSCH3_V 0x3FF +#define LEDC_DUTY_NUM_HSCH3_S 20 +/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch3 cycles for high speed channel3.*/ +#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S)) +#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH3_S 10 +/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel3.*/ +#define LEDC_DUTY_SCALE_HSCH3 0x000003FF +#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S)) +#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH3_S 0 + +#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) +/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel3.*/ +#define LEDC_DUTY_HSCH3 0x01FFFFFF +#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) +#define LEDC_DUTY_HSCH3_V 0x1FFFFFF +#define LEDC_DUTY_HSCH3_S 0 + +#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) +/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel4 is off.*/ +#define LEDC_IDLE_LV_HSCH4 (BIT(3)) +#define LEDC_IDLE_LV_HSCH4_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH4_V 0x1 +#define LEDC_IDLE_LV_HSCH4_S 3 +/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel4*/ +#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH4_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH4_S 2 +/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH4 0x00000003 +#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S)) +#define LEDC_TIMER_SEL_HSCH4_V 0x3 +#define LEDC_TIMER_SEL_HSCH4_S 0 + +#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) +/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/ +#define LEDC_HPOINT_HSCH4 0x000FFFFF +#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S)) +#define LEDC_HPOINT_HSCH4_V 0xFFFFF +#define LEDC_HPOINT_HSCH4_S 0 + +#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) +/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH4 0x01FFFFFF +#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) +#define LEDC_DUTY_HSCH4_V 0x1FFFFFF +#define LEDC_DUTY_HSCH4_S 0 + +#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) +/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH4 (BIT(31)) +#define LEDC_DUTY_START_HSCH4_M (BIT(31)) +#define LEDC_DUTY_START_HSCH4_V 0x1 +#define LEDC_DUTY_START_HSCH4_S 31 +/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel4.*/ +#define LEDC_DUTY_INC_HSCH4 (BIT(30)) +#define LEDC_DUTY_INC_HSCH4_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH4_V 0x1 +#define LEDC_DUTY_INC_HSCH4_S 30 +/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel1.*/ +#define LEDC_DUTY_NUM_HSCH4 0x000003FF +#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S)) +#define LEDC_DUTY_NUM_HSCH4_V 0x3FF +#define LEDC_DUTY_NUM_HSCH4_S 20 +/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch4 cycles for high speed channel4.*/ +#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S)) +#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH4_S 10 +/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel4.*/ +#define LEDC_DUTY_SCALE_HSCH4 0x000003FF +#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S)) +#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH4_S 0 + +#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) +/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel4.*/ +#define LEDC_DUTY_HSCH4 0x01FFFFFF +#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) +#define LEDC_DUTY_HSCH4_V 0x1FFFFFF +#define LEDC_DUTY_HSCH4_S 0 + +#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) +/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel5 is off.*/ +#define LEDC_IDLE_LV_HSCH5 (BIT(3)) +#define LEDC_IDLE_LV_HSCH5_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH5_V 0x1 +#define LEDC_IDLE_LV_HSCH5_S 3 +/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel5.*/ +#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH5_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH5_S 2 +/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH5 0x00000003 +#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S)) +#define LEDC_TIMER_SEL_HSCH5_V 0x3 +#define LEDC_TIMER_SEL_HSCH5_S 0 + +#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) +/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/ +#define LEDC_HPOINT_HSCH5 0x000FFFFF +#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S)) +#define LEDC_HPOINT_HSCH5_V 0xFFFFF +#define LEDC_HPOINT_HSCH5_S 0 + +#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) +/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH5 0x01FFFFFF +#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) +#define LEDC_DUTY_HSCH5_V 0x1FFFFFF +#define LEDC_DUTY_HSCH5_S 0 + +#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) +/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5 + has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH5 (BIT(31)) +#define LEDC_DUTY_START_HSCH5_M (BIT(31)) +#define LEDC_DUTY_START_HSCH5_V 0x1 +#define LEDC_DUTY_START_HSCH5_S 31 +/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel5.*/ +#define LEDC_DUTY_INC_HSCH5 (BIT(30)) +#define LEDC_DUTY_INC_HSCH5_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH5_V 0x1 +#define LEDC_DUTY_INC_HSCH5_S 30 +/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel5.*/ +#define LEDC_DUTY_NUM_HSCH5 0x000003FF +#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S)) +#define LEDC_DUTY_NUM_HSCH5_V 0x3FF +#define LEDC_DUTY_NUM_HSCH5_S 20 +/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch5 cycles for high speed channel5.*/ +#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S)) +#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH5_S 10 +/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel5.*/ +#define LEDC_DUTY_SCALE_HSCH5 0x000003FF +#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S)) +#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH5_S 0 + +#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) +/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel5.*/ +#define LEDC_DUTY_HSCH5 0x01FFFFFF +#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) +#define LEDC_DUTY_HSCH5_V 0x1FFFFFF +#define LEDC_DUTY_HSCH5_S 0 + +#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078) +/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel6 is off.*/ +#define LEDC_IDLE_LV_HSCH6 (BIT(3)) +#define LEDC_IDLE_LV_HSCH6_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH6_V 0x1 +#define LEDC_IDLE_LV_HSCH6_S 3 +/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel6*/ +#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH6_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH6_S 2 +/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH6 0x00000003 +#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S)) +#define LEDC_TIMER_SEL_HSCH6_V 0x3 +#define LEDC_TIMER_SEL_HSCH6_S 0 + +#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C) +/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/ +#define LEDC_HPOINT_HSCH6 0x000FFFFF +#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S)) +#define LEDC_HPOINT_HSCH6_V 0xFFFFF +#define LEDC_HPOINT_HSCH6_S 0 + +#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080) +/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH6 0x01FFFFFF +#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) +#define LEDC_DUTY_HSCH6_V 0x1FFFFFF +#define LEDC_DUTY_HSCH6_S 0 + +#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084) +/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH6 (BIT(31)) +#define LEDC_DUTY_START_HSCH6_M (BIT(31)) +#define LEDC_DUTY_START_HSCH6_V 0x1 +#define LEDC_DUTY_START_HSCH6_S 31 +/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel6.*/ +#define LEDC_DUTY_INC_HSCH6 (BIT(30)) +#define LEDC_DUTY_INC_HSCH6_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH6_V 0x1 +#define LEDC_DUTY_INC_HSCH6_S 30 +/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel6.*/ +#define LEDC_DUTY_NUM_HSCH6 0x000003FF +#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S)) +#define LEDC_DUTY_NUM_HSCH6_V 0x3FF +#define LEDC_DUTY_NUM_HSCH6_S 20 +/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch6 cycles for high speed channel6.*/ +#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S)) +#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH6_S 10 +/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel6.*/ +#define LEDC_DUTY_SCALE_HSCH6 0x000003FF +#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S)) +#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH6_S 0 + +#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088) +/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel6.*/ +#define LEDC_DUTY_HSCH6 0x01FFFFFF +#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) +#define LEDC_DUTY_HSCH6_V 0x1FFFFFF +#define LEDC_DUTY_HSCH6_S 0 + +#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C) +/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel7 is off.*/ +#define LEDC_IDLE_LV_HSCH7 (BIT(3)) +#define LEDC_IDLE_LV_HSCH7_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH7_V 0x1 +#define LEDC_IDLE_LV_HSCH7_S 3 +/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel7.*/ +#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH7_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH7_S 2 +/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH7 0x00000003 +#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S)) +#define LEDC_TIMER_SEL_HSCH7_V 0x3 +#define LEDC_TIMER_SEL_HSCH7_S 0 + +#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090) +/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/ +#define LEDC_HPOINT_HSCH7 0x000FFFFF +#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S)) +#define LEDC_HPOINT_HSCH7_V 0xFFFFF +#define LEDC_HPOINT_HSCH7_S 0 + +#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094) +/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH7 0x01FFFFFF +#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) +#define LEDC_DUTY_HSCH7_V 0x1FFFFFF +#define LEDC_DUTY_HSCH7_S 0 + +#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098) +/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH7 (BIT(31)) +#define LEDC_DUTY_START_HSCH7_M (BIT(31)) +#define LEDC_DUTY_START_HSCH7_V 0x1 +#define LEDC_DUTY_START_HSCH7_S 31 +/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel6.*/ +#define LEDC_DUTY_INC_HSCH7 (BIT(30)) +#define LEDC_DUTY_INC_HSCH7_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH7_V 0x1 +#define LEDC_DUTY_INC_HSCH7_S 30 +/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel6.*/ +#define LEDC_DUTY_NUM_HSCH7 0x000003FF +#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S)) +#define LEDC_DUTY_NUM_HSCH7_V 0x3FF +#define LEDC_DUTY_NUM_HSCH7_S 20 +/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch7 cycles for high speed channel7.*/ +#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S)) +#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH7_S 10 +/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel7.*/ +#define LEDC_DUTY_SCALE_HSCH7 0x000003FF +#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S)) +#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH7_S 0 + +#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C) +/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel7.*/ +#define LEDC_DUTY_HSCH7 0x01FFFFFF +#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) +#define LEDC_DUTY_HSCH7_V 0x1FFFFFF +#define LEDC_DUTY_HSCH7_S 0 + +#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0) +/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY + for low speed channel0.*/ +#define LEDC_PARA_UP_LSCH0 (BIT(4)) +#define LEDC_PARA_UP_LSCH0_M (BIT(4)) +#define LEDC_PARA_UP_LSCH0_V 0x1 +#define LEDC_PARA_UP_LSCH0_S 4 +/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel0 is off.*/ +#define LEDC_IDLE_LV_LSCH0 (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_V 0x1 +#define LEDC_IDLE_LV_LSCH0_S 3 +/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel0.*/ +#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH0_S 2 +/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH0 0x00000003 +#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S)) +#define LEDC_TIMER_SEL_LSCH0_V 0x3 +#define LEDC_TIMER_SEL_LSCH0_S 0 + +#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4) +/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/ +#define LEDC_HPOINT_LSCH0 0x000FFFFF +#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S)) +#define LEDC_HPOINT_LSCH0_V 0xFFFFF +#define LEDC_HPOINT_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8) +/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH0 0x01FFFFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x1FFFFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC) +/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH0 (BIT(31)) +#define LEDC_DUTY_START_LSCH0_M (BIT(31)) +#define LEDC_DUTY_START_LSCH0_V 0x1 +#define LEDC_DUTY_START_LSCH0_S 31 +/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel6.*/ +#define LEDC_DUTY_INC_LSCH0 (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_V 0x1 +#define LEDC_DUTY_INC_LSCH0_S 30 +/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel6.*/ +#define LEDC_DUTY_NUM_LSCH0 0x000003FF +#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S)) +#define LEDC_DUTY_NUM_LSCH0_V 0x3FF +#define LEDC_DUTY_NUM_LSCH0_S 20 +/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch0 cycles for low speed channel0.*/ +#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S)) +#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH0_S 10 +/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel0.*/ +#define LEDC_DUTY_SCALE_LSCH0 0x000003FF +#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S)) +#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0) +/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel0.*/ +#define LEDC_DUTY_LSCH0 0x01FFFFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x1FFFFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4) +/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY + for low speed channel1.*/ +#define LEDC_PARA_UP_LSCH1 (BIT(4)) +#define LEDC_PARA_UP_LSCH1_M (BIT(4)) +#define LEDC_PARA_UP_LSCH1_V 0x1 +#define LEDC_PARA_UP_LSCH1_S 4 +/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel1 is off.*/ +#define LEDC_IDLE_LV_LSCH1 (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_V 0x1 +#define LEDC_IDLE_LV_LSCH1_S 3 +/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel1.*/ +#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH1_S 2 +/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH1 0x00000003 +#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S)) +#define LEDC_TIMER_SEL_LSCH1_V 0x3 +#define LEDC_TIMER_SEL_LSCH1_S 0 + +#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8) +/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/ +#define LEDC_HPOINT_LSCH1 0x000FFFFF +#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S)) +#define LEDC_HPOINT_LSCH1_V 0xFFFFF +#define LEDC_HPOINT_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC) +/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH1 0x01FFFFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x1FFFFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0) +/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH1 (BIT(31)) +#define LEDC_DUTY_START_LSCH1_M (BIT(31)) +#define LEDC_DUTY_START_LSCH1_V 0x1 +#define LEDC_DUTY_START_LSCH1_S 31 +/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel1.*/ +#define LEDC_DUTY_INC_LSCH1 (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_V 0x1 +#define LEDC_DUTY_INC_LSCH1_S 30 +/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel1.*/ +#define LEDC_DUTY_NUM_LSCH1 0x000003FF +#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S)) +#define LEDC_DUTY_NUM_LSCH1_V 0x3FF +#define LEDC_DUTY_NUM_LSCH1_S 20 +/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch1 cycles for low speed channel1.*/ +#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S)) +#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH1_S 10 +/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel1.*/ +#define LEDC_DUTY_SCALE_LSCH1 0x000003FF +#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S)) +#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4) +/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel1.*/ +#define LEDC_DUTY_LSCH1 0x01FFFFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x1FFFFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8) +/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY + for low speed channel2.*/ +#define LEDC_PARA_UP_LSCH2 (BIT(4)) +#define LEDC_PARA_UP_LSCH2_M (BIT(4)) +#define LEDC_PARA_UP_LSCH2_V 0x1 +#define LEDC_PARA_UP_LSCH2_S 4 +/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel2 is off.*/ +#define LEDC_IDLE_LV_LSCH2 (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_V 0x1 +#define LEDC_IDLE_LV_LSCH2_S 3 +/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel2.*/ +#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH2_S 2 +/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH2 0x00000003 +#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S)) +#define LEDC_TIMER_SEL_LSCH2_V 0x3 +#define LEDC_TIMER_SEL_LSCH2_S 0 + +#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC) +/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/ +#define LEDC_HPOINT_LSCH2 0x000FFFFF +#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S)) +#define LEDC_HPOINT_LSCH2_V 0xFFFFF +#define LEDC_HPOINT_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0) +/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH2 0x01FFFFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x1FFFFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4) +/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 + has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH2 (BIT(31)) +#define LEDC_DUTY_START_LSCH2_M (BIT(31)) +#define LEDC_DUTY_START_LSCH2_V 0x1 +#define LEDC_DUTY_START_LSCH2_S 31 +/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel2.*/ +#define LEDC_DUTY_INC_LSCH2 (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_V 0x1 +#define LEDC_DUTY_INC_LSCH2_S 30 +/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel2.*/ +#define LEDC_DUTY_NUM_LSCH2 0x000003FF +#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S)) +#define LEDC_DUTY_NUM_LSCH2_V 0x3FF +#define LEDC_DUTY_NUM_LSCH2_S 20 +/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch2 cycles for low speed channel2.*/ +#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S)) +#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH2_S 10 +/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel2.*/ +#define LEDC_DUTY_SCALE_LSCH2 0x000003FF +#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S)) +#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8) +/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel2.*/ +#define LEDC_DUTY_LSCH2 0x01FFFFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x1FFFFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC) +/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY + for low speed channel3.*/ +#define LEDC_PARA_UP_LSCH3 (BIT(4)) +#define LEDC_PARA_UP_LSCH3_M (BIT(4)) +#define LEDC_PARA_UP_LSCH3_V 0x1 +#define LEDC_PARA_UP_LSCH3_S 4 +/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel3 is off.*/ +#define LEDC_IDLE_LV_LSCH3 (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_V 0x1 +#define LEDC_IDLE_LV_LSCH3_S 3 +/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel3.*/ +#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH3_S 2 +/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH3 0x00000003 +#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S)) +#define LEDC_TIMER_SEL_LSCH3_V 0x3 +#define LEDC_TIMER_SEL_LSCH3_S 0 + +#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0) +/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/ +#define LEDC_HPOINT_LSCH3 0x000FFFFF +#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S)) +#define LEDC_HPOINT_LSCH3_V 0xFFFFF +#define LEDC_HPOINT_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4) +/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH3 0x01FFFFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x1FFFFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8) +/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 + has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH3 (BIT(31)) +#define LEDC_DUTY_START_LSCH3_M (BIT(31)) +#define LEDC_DUTY_START_LSCH3_V 0x1 +#define LEDC_DUTY_START_LSCH3_S 31 +/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel3.*/ +#define LEDC_DUTY_INC_LSCH3 (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_V 0x1 +#define LEDC_DUTY_INC_LSCH3_S 30 +/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel3.*/ +#define LEDC_DUTY_NUM_LSCH3 0x000003FF +#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S)) +#define LEDC_DUTY_NUM_LSCH3_V 0x3FF +#define LEDC_DUTY_NUM_LSCH3_S 20 +/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch3 cycles for low speed channel3.*/ +#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S)) +#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH3_S 10 +/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel3.*/ +#define LEDC_DUTY_SCALE_LSCH3 0x000003FF +#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S)) +#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC) +/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel3.*/ +#define LEDC_DUTY_LSCH3 0x01FFFFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x1FFFFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0) +/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY + for low speed channel4.*/ +#define LEDC_PARA_UP_LSCH4 (BIT(4)) +#define LEDC_PARA_UP_LSCH4_M (BIT(4)) +#define LEDC_PARA_UP_LSCH4_V 0x1 +#define LEDC_PARA_UP_LSCH4_S 4 +/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel4 is off.*/ +#define LEDC_IDLE_LV_LSCH4 (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_V 0x1 +#define LEDC_IDLE_LV_LSCH4_S 3 +/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel4.*/ +#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH4_S 2 +/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH4 0x00000003 +#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S)) +#define LEDC_TIMER_SEL_LSCH4_V 0x3 +#define LEDC_TIMER_SEL_LSCH4_S 0 + +#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4) +/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/ +#define LEDC_HPOINT_LSCH4 0x000FFFFF +#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S)) +#define LEDC_HPOINT_LSCH4_V 0xFFFFF +#define LEDC_HPOINT_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8) +/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH4 0x01FFFFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x1FFFFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC) +/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH4 (BIT(31)) +#define LEDC_DUTY_START_LSCH4_M (BIT(31)) +#define LEDC_DUTY_START_LSCH4_V 0x1 +#define LEDC_DUTY_START_LSCH4_S 31 +/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel4.*/ +#define LEDC_DUTY_INC_LSCH4 (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_V 0x1 +#define LEDC_DUTY_INC_LSCH4_S 30 +/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel4.*/ +#define LEDC_DUTY_NUM_LSCH4 0x000003FF +#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S)) +#define LEDC_DUTY_NUM_LSCH4_V 0x3FF +#define LEDC_DUTY_NUM_LSCH4_S 20 +/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch4 cycles for low speed channel4.*/ +#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S)) +#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH4_S 10 +/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel4.*/ +#define LEDC_DUTY_SCALE_LSCH4 0x000003FF +#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S)) +#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100) +/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel4.*/ +#define LEDC_DUTY_LSCH4 0x01FFFFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x1FFFFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104) +/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY + for low speed channel5.*/ +#define LEDC_PARA_UP_LSCH5 (BIT(4)) +#define LEDC_PARA_UP_LSCH5_M (BIT(4)) +#define LEDC_PARA_UP_LSCH5_V 0x1 +#define LEDC_PARA_UP_LSCH5_S 4 +/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel5 is off.*/ +#define LEDC_IDLE_LV_LSCH5 (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_V 0x1 +#define LEDC_IDLE_LV_LSCH5_S 3 +/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel5.*/ +#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH5_S 2 +/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH5 0x00000003 +#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S)) +#define LEDC_TIMER_SEL_LSCH5_V 0x3 +#define LEDC_TIMER_SEL_LSCH5_S 0 + +#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108) +/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/ +#define LEDC_HPOINT_LSCH5 0x000FFFFF +#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S)) +#define LEDC_HPOINT_LSCH5_V 0xFFFFF +#define LEDC_HPOINT_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C) +/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH5 0x01FFFFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x1FFFFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110) +/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH5 (BIT(31)) +#define LEDC_DUTY_START_LSCH5_M (BIT(31)) +#define LEDC_DUTY_START_LSCH5_V 0x1 +#define LEDC_DUTY_START_LSCH5_S 31 +/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel5.*/ +#define LEDC_DUTY_INC_LSCH5 (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_V 0x1 +#define LEDC_DUTY_INC_LSCH5_S 30 +/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel5.*/ +#define LEDC_DUTY_NUM_LSCH5 0x000003FF +#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S)) +#define LEDC_DUTY_NUM_LSCH5_V 0x3FF +#define LEDC_DUTY_NUM_LSCH5_S 20 +/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch5 cycles for low speed channel4.*/ +#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S)) +#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH5_S 10 +/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel5.*/ +#define LEDC_DUTY_SCALE_LSCH5 0x000003FF +#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S)) +#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114) +/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel5.*/ +#define LEDC_DUTY_LSCH5 0x01FFFFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x1FFFFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118) +/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY + for low speed channel6.*/ +#define LEDC_PARA_UP_LSCH6 (BIT(4)) +#define LEDC_PARA_UP_LSCH6_M (BIT(4)) +#define LEDC_PARA_UP_LSCH6_V 0x1 +#define LEDC_PARA_UP_LSCH6_S 4 +/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel6 is off.*/ +#define LEDC_IDLE_LV_LSCH6 (BIT(3)) +#define LEDC_IDLE_LV_LSCH6_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH6_V 0x1 +#define LEDC_IDLE_LV_LSCH6_S 3 +/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel6.*/ +#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH6_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH6_S 2 +/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH6 0x00000003 +#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S)) +#define LEDC_TIMER_SEL_LSCH6_V 0x3 +#define LEDC_TIMER_SEL_LSCH6_S 0 + +#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C) +/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/ +#define LEDC_HPOINT_LSCH6 0x000FFFFF +#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S)) +#define LEDC_HPOINT_LSCH6_V 0xFFFFF +#define LEDC_HPOINT_LSCH6_S 0 + +#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120) +/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH6 0x01FFFFFF +#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) +#define LEDC_DUTY_LSCH6_V 0x1FFFFFF +#define LEDC_DUTY_LSCH6_S 0 + +#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124) +/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6 + has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH6 (BIT(31)) +#define LEDC_DUTY_START_LSCH6_M (BIT(31)) +#define LEDC_DUTY_START_LSCH6_V 0x1 +#define LEDC_DUTY_START_LSCH6_S 31 +/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel6.*/ +#define LEDC_DUTY_INC_LSCH6 (BIT(30)) +#define LEDC_DUTY_INC_LSCH6_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH6_V 0x1 +#define LEDC_DUTY_INC_LSCH6_S 30 +/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel6.*/ +#define LEDC_DUTY_NUM_LSCH6 0x000003FF +#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S)) +#define LEDC_DUTY_NUM_LSCH6_V 0x3FF +#define LEDC_DUTY_NUM_LSCH6_S 20 +/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch6 cycles for low speed channel6.*/ +#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S)) +#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH6_S 10 +/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel6.*/ +#define LEDC_DUTY_SCALE_LSCH6 0x000003FF +#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S)) +#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH6_S 0 + +#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128) +/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel6.*/ +#define LEDC_DUTY_LSCH6 0x01FFFFFF +#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) +#define LEDC_DUTY_LSCH6_V 0x1FFFFFF +#define LEDC_DUTY_LSCH6_S 0 + +#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C) +/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY + for low speed channel7.*/ +#define LEDC_PARA_UP_LSCH7 (BIT(4)) +#define LEDC_PARA_UP_LSCH7_M (BIT(4)) +#define LEDC_PARA_UP_LSCH7_V 0x1 +#define LEDC_PARA_UP_LSCH7_S 4 +/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel7 is off.*/ +#define LEDC_IDLE_LV_LSCH7 (BIT(3)) +#define LEDC_IDLE_LV_LSCH7_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH7_V 0x1 +#define LEDC_IDLE_LV_LSCH7_S 3 +/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel7.*/ +#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH7_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH7_S 2 +/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH7 0x00000003 +#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S)) +#define LEDC_TIMER_SEL_LSCH7_V 0x3 +#define LEDC_TIMER_SEL_LSCH7_S 0 + +#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130) +/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/ +#define LEDC_HPOINT_LSCH7 0x000FFFFF +#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S)) +#define LEDC_HPOINT_LSCH7_V 0xFFFFF +#define LEDC_HPOINT_LSCH7_S 0 + +#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134) +/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH7 0x01FFFFFF +#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) +#define LEDC_DUTY_LSCH7_V 0x1FFFFFF +#define LEDC_DUTY_LSCH7_S 0 + +#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138) +/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH7 (BIT(31)) +#define LEDC_DUTY_START_LSCH7_M (BIT(31)) +#define LEDC_DUTY_START_LSCH7_V 0x1 +#define LEDC_DUTY_START_LSCH7_S 31 +/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel4.*/ +#define LEDC_DUTY_INC_LSCH7 (BIT(30)) +#define LEDC_DUTY_INC_LSCH7_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH7_V 0x1 +#define LEDC_DUTY_INC_LSCH7_S 30 +/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel4.*/ +#define LEDC_DUTY_NUM_LSCH7 0x000003FF +#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S)) +#define LEDC_DUTY_NUM_LSCH7_V 0x3FF +#define LEDC_DUTY_NUM_LSCH7_S 20 +/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch7 cycles for low speed channel7.*/ +#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S)) +#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH7_S 10 +/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel7.*/ +#define LEDC_DUTY_SCALE_LSCH7 0x000003FF +#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S)) +#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH7_S 0 + +#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C) +/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel7.*/ +#define LEDC_DUTY_LSCH7 0x01FFFFFF +#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) +#define LEDC_DUTY_LSCH7_V 0x1FFFFFF +#define LEDC_DUTY_LSCH7_S 0 + +#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140) +/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer0. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER0 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER0_V 0x1 +#define LEDC_TICK_SEL_HSTIMER0_S 25 +/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER0_RST (BIT(24)) +#define LEDC_HSTIMER0_RST_M (BIT(24)) +#define LEDC_HSTIMER0_RST_V 0x1 +#define LEDC_HSTIMER0_RST_S 24 +/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer0*/ +#define LEDC_HSTIMER0_PAUSE (BIT(23)) +#define LEDC_HSTIMER0_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER0_PAUSE_V 0x1 +#define LEDC_HSTIMER0_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer0 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S)) +#define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER0_S 5 +/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER0_LIM 0x0000001F +#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S)) +#define LEDC_HSTIMER0_LIM_V 0x1F +#define LEDC_HSTIMER0_LIM_S 0 + +#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144) +/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer0*/ +#define LEDC_HSTIMER0_CNT 0x000FFFFF +#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S)) +#define LEDC_HSTIMER0_CNT_V 0xFFFFF +#define LEDC_HSTIMER0_CNT_S 0 + +#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148) +/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer1. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER1 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER1_V 0x1 +#define LEDC_TICK_SEL_HSTIMER1_S 25 +/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER1_RST (BIT(24)) +#define LEDC_HSTIMER1_RST_M (BIT(24)) +#define LEDC_HSTIMER1_RST_V 0x1 +#define LEDC_HSTIMER1_RST_S 24 +/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer1*/ +#define LEDC_HSTIMER1_PAUSE (BIT(23)) +#define LEDC_HSTIMER1_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER1_PAUSE_V 0x1 +#define LEDC_HSTIMER1_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer1 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S)) +#define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER1_S 5 +/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER1_LIM 0x0000001F +#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S)) +#define LEDC_HSTIMER1_LIM_V 0x1F +#define LEDC_HSTIMER1_LIM_S 0 + +#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C) +/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer1.*/ +#define LEDC_HSTIMER1_CNT 0x000FFFFF +#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S)) +#define LEDC_HSTIMER1_CNT_V 0xFFFFF +#define LEDC_HSTIMER1_CNT_S 0 + +#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150) +/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer2. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER2 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER2_V 0x1 +#define LEDC_TICK_SEL_HSTIMER2_S 25 +/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER2_RST (BIT(24)) +#define LEDC_HSTIMER2_RST_M (BIT(24)) +#define LEDC_HSTIMER2_RST_V 0x1 +#define LEDC_HSTIMER2_RST_S 24 +/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer2*/ +#define LEDC_HSTIMER2_PAUSE (BIT(23)) +#define LEDC_HSTIMER2_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER2_PAUSE_V 0x1 +#define LEDC_HSTIMER2_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer2 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S)) +#define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER2_S 5 +/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER2_LIM 0x0000001F +#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S)) +#define LEDC_HSTIMER2_LIM_V 0x1F +#define LEDC_HSTIMER2_LIM_S 0 + +#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154) +/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer2*/ +#define LEDC_HSTIMER2_CNT 0x000FFFFF +#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S)) +#define LEDC_HSTIMER2_CNT_V 0xFFFFF +#define LEDC_HSTIMER2_CNT_S 0 + +#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158) +/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer3. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER3 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER3_V 0x1 +#define LEDC_TICK_SEL_HSTIMER3_S 25 +/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER3_RST (BIT(24)) +#define LEDC_HSTIMER3_RST_M (BIT(24)) +#define LEDC_HSTIMER3_RST_V 0x1 +#define LEDC_HSTIMER3_RST_S 24 +/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer3*/ +#define LEDC_HSTIMER3_PAUSE (BIT(23)) +#define LEDC_HSTIMER3_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER3_PAUSE_V 0x1 +#define LEDC_HSTIMER3_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer3 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S)) +#define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER3_S 5 +/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER3_LIM 0x0000001F +#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S)) +#define LEDC_HSTIMER3_LIM_V 0x1F +#define LEDC_HSTIMER3_LIM_S 0 + +#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C) +/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer3*/ +#define LEDC_HSTIMER3_CNT 0x000FFFFF +#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S)) +#define LEDC_HSTIMER3_CNT_V 0xFFFFF +#define LEDC_HSTIMER3_CNT_S 0 + +#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160) +/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ +#define LEDC_LSTIMER0_PARA_UP (BIT(26)) +#define LEDC_LSTIMER0_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER0_PARA_UP_V 0x1 +#define LEDC_LSTIMER0_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer0. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER0 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER0_V 0x1 +#define LEDC_TICK_SEL_LSTIMER0_S 25 +/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER0_RST (BIT(24)) +#define LEDC_LSTIMER0_RST_M (BIT(24)) +#define LEDC_LSTIMER0_RST_V 0x1 +#define LEDC_LSTIMER0_RST_S 24 +/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer0.*/ +#define LEDC_LSTIMER0_PAUSE (BIT(23)) +#define LEDC_LSTIMER0_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER0_PAUSE_V 0x1 +#define LEDC_LSTIMER0_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer0 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S)) +#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER0_S 5 +/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER0_LIM 0x0000001F +#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S)) +#define LEDC_LSTIMER0_LIM_V 0x1F +#define LEDC_LSTIMER0_LIM_S 0 + +#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164) +/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer0.*/ +#define LEDC_LSTIMER0_CNT 0x000FFFFF +#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S)) +#define LEDC_LSTIMER0_CNT_V 0xFFFFF +#define LEDC_LSTIMER0_CNT_S 0 + +#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168) +/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/ +#define LEDC_LSTIMER1_PARA_UP (BIT(26)) +#define LEDC_LSTIMER1_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER1_PARA_UP_V 0x1 +#define LEDC_LSTIMER1_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer1. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER1 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER1_V 0x1 +#define LEDC_TICK_SEL_LSTIMER1_S 25 +/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER1_RST (BIT(24)) +#define LEDC_LSTIMER1_RST_M (BIT(24)) +#define LEDC_LSTIMER1_RST_V 0x1 +#define LEDC_LSTIMER1_RST_S 24 +/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer1.*/ +#define LEDC_LSTIMER1_PAUSE (BIT(23)) +#define LEDC_LSTIMER1_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER1_PAUSE_V 0x1 +#define LEDC_LSTIMER1_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer1 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S)) +#define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER1_S 5 +/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER1_LIM 0x0000001F +#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S)) +#define LEDC_LSTIMER1_LIM_V 0x1F +#define LEDC_LSTIMER1_LIM_S 0 + +#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C) +/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer1.*/ +#define LEDC_LSTIMER1_CNT 0x000FFFFF +#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S)) +#define LEDC_LSTIMER1_CNT_V 0xFFFFF +#define LEDC_LSTIMER1_CNT_S 0 + +#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170) +/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/ +#define LEDC_LSTIMER2_PARA_UP (BIT(26)) +#define LEDC_LSTIMER2_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER2_PARA_UP_V 0x1 +#define LEDC_LSTIMER2_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer2. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER2 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER2_V 0x1 +#define LEDC_TICK_SEL_LSTIMER2_S 25 +/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER2_RST (BIT(24)) +#define LEDC_LSTIMER2_RST_M (BIT(24)) +#define LEDC_LSTIMER2_RST_V 0x1 +#define LEDC_LSTIMER2_RST_S 24 +/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer2.*/ +#define LEDC_LSTIMER2_PAUSE (BIT(23)) +#define LEDC_LSTIMER2_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER2_PAUSE_V 0x1 +#define LEDC_LSTIMER2_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer2 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S)) +#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER2_S 5 +/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER2_LIM 0x0000001F +#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S)) +#define LEDC_LSTIMER2_LIM_V 0x1F +#define LEDC_LSTIMER2_LIM_S 0 + +#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174) +/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer2.*/ +#define LEDC_LSTIMER2_CNT 0x000FFFFF +#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S)) +#define LEDC_LSTIMER2_CNT_V 0xFFFFF +#define LEDC_LSTIMER2_CNT_S 0 + +#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178) +/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/ +#define LEDC_LSTIMER3_PARA_UP (BIT(26)) +#define LEDC_LSTIMER3_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER3_PARA_UP_V 0x1 +#define LEDC_LSTIMER3_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer3. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER3 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER3_V 0x1 +#define LEDC_TICK_SEL_LSTIMER3_S 25 +/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER3_RST (BIT(24)) +#define LEDC_LSTIMER3_RST_M (BIT(24)) +#define LEDC_LSTIMER3_RST_V 0x1 +#define LEDC_LSTIMER3_RST_S 24 +/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer3.*/ +#define LEDC_LSTIMER3_PAUSE (BIT(23)) +#define LEDC_LSTIMER3_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER3_PAUSE_V 0x1 +#define LEDC_LSTIMER3_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer3 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S)) +#define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER3_S 5 +/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER3_LIM 0x0000001F +#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S)) +#define LEDC_LSTIMER3_LIM_V 0x1F +#define LEDC_LSTIMER3_LIM_S 0 + +#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C) +/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer3.*/ +#define LEDC_LSTIMER3_CNT 0x000FFFFF +#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S)) +#define LEDC_LSTIMER3_CNT_V 0xFFFFF +#define LEDC_LSTIMER3_CNT_S 0 + +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 7 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 6 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 5 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 4 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 3 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 2 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 1 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 0 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 7 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 6 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 5 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 4 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 3 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 2 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 1 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 0 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8 +/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel3 counter overflow.*/ +#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_RAW_S 7 +/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel2 counter overflow.*/ +#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_RAW_S 6 +/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel1 counter overflow.*/ +#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_RAW_S 5 +/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel0 counter overflow.*/ +#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_RAW_S 4 +/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel3 counter overflow.*/ +#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_RAW_S 3 +/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel2 counter overflow.*/ +#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_RAW_S 2 +/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel1 counter overflow.*/ +#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_RAW_S 1 +/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel0 counter overflow.*/ +#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_RAW_S 0 + +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: The interrupt status bit for low speed channel 7 duty change done event*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 6 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 5 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 4 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 3 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 2 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 1 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 0 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 7 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 6 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 5 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 4 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 3 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 2 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 1 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 0 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8 +/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel3 counter overflow event.*/ +#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ST_S 7 +/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel2 counter overflow event.*/ +#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ST_S 6 +/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel1 counter overflow event.*/ +#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ST_S 5 +/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel0 counter overflow event.*/ +#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ST_S 4 +/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel3 counter overflow event.*/ +#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_ST_S 3 +/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel2 counter overflow event.*/ +#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_ST_S 2 +/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel1 counter overflow event.*/ +#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_ST_S 1 +/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel0 counter overflow event.*/ +#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_ST_S 0 + +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8 +/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ +#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ENA_S 7 +/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ +#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ENA_S 6 +/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ +#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ENA_S 5 +/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ +#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ENA_S 4 +/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ +#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_ENA_S 3 +/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ +#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_ENA_S 2 +/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ +#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_ENA_S 1 +/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ +#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_ENA_S 0 + +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8 +/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/ +#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_CLR_S 7 +/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/ +#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_CLR_S 6 +/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/ +#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_CLR_S 5 +/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/ +#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_CLR_S 4 +/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/ +#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_CLR_S 3 +/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/ +#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_CLR_S 2 +/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/ +#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_CLR_S 1 +/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/ +#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_CLR_S 0 + +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190) +/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ +#define LEDC_APB_CLK_SEL (BIT(0)) +#define LEDC_APB_CLK_SEL_M (BIT(0)) +#define LEDC_APB_CLK_SEL_V 0x1 +#define LEDC_APB_CLK_SEL_S 0 + +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC) +/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */ +/*description: This register represents the version .*/ +#define LEDC_DATE 0xFFFFFFFF +#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) +#define LEDC_DATE_V 0xFFFFFFFF +#define LEDC_DATE_S 0 + + + + +#endif /*_SOC_LEDC_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/ledc_struct.h b/tools/sdk/include/soc/soc/ledc_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/ledc_struct.h rename to tools/sdk/include/soc/soc/ledc_struct.h diff --git a/tools/sdk/include/soc/soc/nrx_reg.h b/tools/sdk/include/soc/soc/nrx_reg.h new file mode 100644 index 00000000..cd13319c --- /dev/null +++ b/tools/sdk/include/soc/soc/nrx_reg.h @@ -0,0 +1,39 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" + +/* Some of the WiFi RX control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4) +#define NRX_CHAN_EST_FORCE_PU (BIT(7)) +#define NRX_CHAN_EST_FORCE_PU_S 7 +#define NRX_CHAN_EST_FORCE_PD (BIT(6)) +#define NRX_CHAN_EST_FORCE_PD_S 6 +#define NRX_RX_ROT_FORCE_PU (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_S 5 +#define NRX_RX_ROT_FORCE_PD (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_S 4 +#define NRX_VIT_FORCE_PU (BIT(3)) +#define NRX_VIT_FORCE_PU_S 3 +#define NRX_VIT_FORCE_PD (BIT(2)) +#define NRX_VIT_FORCE_PD_S 2 +#define NRX_DEMAP_FORCE_PU (BIT(1)) +#define NRX_DEMAP_FORCE_PU_S 1 +#define NRX_DEMAP_FORCE_PD (BIT(0)) +#define NRX_DEMAP_FORCE_PD_S 0 diff --git a/tools/sdk/include/esp32/soc/pcnt_reg.h b/tools/sdk/include/soc/soc/pcnt_reg.h similarity index 98% rename from tools/sdk/include/esp32/soc/pcnt_reg.h rename to tools/sdk/include/soc/soc/pcnt_reg.h index 9809faf7..fa7dedc2 100644 --- a/tools/sdk/include/esp32/soc/pcnt_reg.h +++ b/tools/sdk/include/soc/soc/pcnt_reg.h @@ -1,1526 +1,1526 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_PCNT_REG_H_ -#define _SOC_PCNT_REG_H_ - - -#include "soc.h" -#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000) -/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U0 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S)) -#define PCNT_CH1_LCTRL_MODE_U0_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U0_S 30 -/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U0 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S)) -#define PCNT_CH1_HCTRL_MODE_U0_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U0_S 28 -/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U0 0x00000003 -#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S)) -#define PCNT_CH1_POS_MODE_U0_V 0x3 -#define PCNT_CH1_POS_MODE_U0_S 26 -/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U0 0x00000003 -#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S)) -#define PCNT_CH1_NEG_MODE_U0_V 0x3 -#define PCNT_CH1_NEG_MODE_U0_S 24 -/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U0 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S)) -#define PCNT_CH0_LCTRL_MODE_U0_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U0_S 22 -/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U0 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S)) -#define PCNT_CH0_HCTRL_MODE_U0_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U0_S 20 -/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U0 0x00000003 -#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S)) -#define PCNT_CH0_POS_MODE_U0_V 0x3 -#define PCNT_CH0_POS_MODE_U0_S 18 -/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U0 0x00000003 -#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S)) -#define PCNT_CH0_NEG_MODE_U0_V 0x3 -#define PCNT_CH0_NEG_MODE_U0_S 16 -/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit0's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U0 (BIT(15)) -#define PCNT_THR_THRES1_EN_U0_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U0_V 0x1 -#define PCNT_THR_THRES1_EN_U0_S 15 -/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit0's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U0 (BIT(14)) -#define PCNT_THR_THRES0_EN_U0_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U0_V 0x1 -#define PCNT_THR_THRES0_EN_U0_S 14 -/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit0's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U0_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U0_V 0x1 -#define PCNT_THR_L_LIM_EN_U0_S 13 -/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit0's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U0_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U0_V 0x1 -#define PCNT_THR_H_LIM_EN_U0_S 12 -/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit0's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U0 (BIT(11)) -#define PCNT_THR_ZERO_EN_U0_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U0_V 0x1 -#define PCNT_THR_ZERO_EN_U0_S 11 -/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit0.*/ -#define PCNT_FILTER_EN_U0 (BIT(10)) -#define PCNT_FILTER_EN_U0_M (BIT(10)) -#define PCNT_FILTER_EN_U0_V 0x1 -#define PCNT_FILTER_EN_U0_S 10 -/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit0.*/ -#define PCNT_FILTER_THRES_U0 0x000003FF -#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S)) -#define PCNT_FILTER_THRES_U0_V 0x3FF -#define PCNT_FILTER_THRES_U0_S 0 - -#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004) -/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit0.*/ -#define PCNT_CNT_THRES1_U0 0x0000FFFF -#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S)) -#define PCNT_CNT_THRES1_U0_V 0xFFFF -#define PCNT_CNT_THRES1_U0_S 16 -/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit0.*/ -#define PCNT_CNT_THRES0_U0 0x0000FFFF -#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S)) -#define PCNT_CNT_THRES0_U0_V 0xFFFF -#define PCNT_CNT_THRES0_U0_S 0 - -#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008) -/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit0.*/ -#define PCNT_CNT_L_LIM_U0 0x0000FFFF -#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S)) -#define PCNT_CNT_L_LIM_U0_V 0xFFFF -#define PCNT_CNT_L_LIM_U0_S 16 -/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit0.*/ -#define PCNT_CNT_H_LIM_U0 0x0000FFFF -#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S)) -#define PCNT_CNT_H_LIM_U0_V 0xFFFF -#define PCNT_CNT_H_LIM_U0_S 0 - -#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c) -/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U1 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S)) -#define PCNT_CH1_LCTRL_MODE_U1_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U1_S 30 -/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U1 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S)) -#define PCNT_CH1_HCTRL_MODE_U1_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U1_S 28 -/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U1 0x00000003 -#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S)) -#define PCNT_CH1_POS_MODE_U1_V 0x3 -#define PCNT_CH1_POS_MODE_U1_S 26 -/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U1 0x00000003 -#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S)) -#define PCNT_CH1_NEG_MODE_U1_V 0x3 -#define PCNT_CH1_NEG_MODE_U1_S 24 -/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U1 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S)) -#define PCNT_CH0_LCTRL_MODE_U1_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U1_S 22 -/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U1 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S)) -#define PCNT_CH0_HCTRL_MODE_U1_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U1_S 20 -/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U1 0x00000003 -#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S)) -#define PCNT_CH0_POS_MODE_U1_V 0x3 -#define PCNT_CH0_POS_MODE_U1_S 18 -/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U1 0x00000003 -#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S)) -#define PCNT_CH0_NEG_MODE_U1_V 0x3 -#define PCNT_CH0_NEG_MODE_U1_S 16 -/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit1's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U1 (BIT(15)) -#define PCNT_THR_THRES1_EN_U1_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U1_V 0x1 -#define PCNT_THR_THRES1_EN_U1_S 15 -/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit1's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U1 (BIT(14)) -#define PCNT_THR_THRES0_EN_U1_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U1_V 0x1 -#define PCNT_THR_THRES0_EN_U1_S 14 -/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit1's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U1_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U1_V 0x1 -#define PCNT_THR_L_LIM_EN_U1_S 13 -/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit1's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U1_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U1_V 0x1 -#define PCNT_THR_H_LIM_EN_U1_S 12 -/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit1's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U1 (BIT(11)) -#define PCNT_THR_ZERO_EN_U1_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U1_V 0x1 -#define PCNT_THR_ZERO_EN_U1_S 11 -/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit1.*/ -#define PCNT_FILTER_EN_U1 (BIT(10)) -#define PCNT_FILTER_EN_U1_M (BIT(10)) -#define PCNT_FILTER_EN_U1_V 0x1 -#define PCNT_FILTER_EN_U1_S 10 -/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit1.*/ -#define PCNT_FILTER_THRES_U1 0x000003FF -#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S)) -#define PCNT_FILTER_THRES_U1_V 0x3FF -#define PCNT_FILTER_THRES_U1_S 0 - -#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010) -/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit1.*/ -#define PCNT_CNT_THRES1_U1 0x0000FFFF -#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S)) -#define PCNT_CNT_THRES1_U1_V 0xFFFF -#define PCNT_CNT_THRES1_U1_S 16 -/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit1.*/ -#define PCNT_CNT_THRES0_U1 0x0000FFFF -#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S)) -#define PCNT_CNT_THRES0_U1_V 0xFFFF -#define PCNT_CNT_THRES0_U1_S 0 - -#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014) -/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit1.*/ -#define PCNT_CNT_L_LIM_U1 0x0000FFFF -#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S)) -#define PCNT_CNT_L_LIM_U1_V 0xFFFF -#define PCNT_CNT_L_LIM_U1_S 16 -/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit1.*/ -#define PCNT_CNT_H_LIM_U1 0x0000FFFF -#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S)) -#define PCNT_CNT_H_LIM_U1_V 0xFFFF -#define PCNT_CNT_H_LIM_U1_S 0 - -#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018) -/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U2 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S)) -#define PCNT_CH1_LCTRL_MODE_U2_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U2_S 30 -/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U2 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S)) -#define PCNT_CH1_HCTRL_MODE_U2_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U2_S 28 -/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U2 0x00000003 -#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S)) -#define PCNT_CH1_POS_MODE_U2_V 0x3 -#define PCNT_CH1_POS_MODE_U2_S 26 -/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U2 0x00000003 -#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S)) -#define PCNT_CH1_NEG_MODE_U2_V 0x3 -#define PCNT_CH1_NEG_MODE_U2_S 24 -/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U2 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S)) -#define PCNT_CH0_LCTRL_MODE_U2_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U2_S 22 -/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U2 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S)) -#define PCNT_CH0_HCTRL_MODE_U2_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U2_S 20 -/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U2 0x00000003 -#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S)) -#define PCNT_CH0_POS_MODE_U2_V 0x3 -#define PCNT_CH0_POS_MODE_U2_S 18 -/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U2 0x00000003 -#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S)) -#define PCNT_CH0_NEG_MODE_U2_V 0x3 -#define PCNT_CH0_NEG_MODE_U2_S 16 -/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit2's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U2 (BIT(15)) -#define PCNT_THR_THRES1_EN_U2_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U2_V 0x1 -#define PCNT_THR_THRES1_EN_U2_S 15 -/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit2's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U2 (BIT(14)) -#define PCNT_THR_THRES0_EN_U2_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U2_V 0x1 -#define PCNT_THR_THRES0_EN_U2_S 14 -/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit2's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U2_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U2_V 0x1 -#define PCNT_THR_L_LIM_EN_U2_S 13 -/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit2's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U2_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U2_V 0x1 -#define PCNT_THR_H_LIM_EN_U2_S 12 -/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit2's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U2 (BIT(11)) -#define PCNT_THR_ZERO_EN_U2_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U2_V 0x1 -#define PCNT_THR_ZERO_EN_U2_S 11 -/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit2.*/ -#define PCNT_FILTER_EN_U2 (BIT(10)) -#define PCNT_FILTER_EN_U2_M (BIT(10)) -#define PCNT_FILTER_EN_U2_V 0x1 -#define PCNT_FILTER_EN_U2_S 10 -/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit2.*/ -#define PCNT_FILTER_THRES_U2 0x000003FF -#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S)) -#define PCNT_FILTER_THRES_U2_V 0x3FF -#define PCNT_FILTER_THRES_U2_S 0 - -#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c) -/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit2.*/ -#define PCNT_CNT_THRES1_U2 0x0000FFFF -#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S)) -#define PCNT_CNT_THRES1_U2_V 0xFFFF -#define PCNT_CNT_THRES1_U2_S 16 -/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit2.*/ -#define PCNT_CNT_THRES0_U2 0x0000FFFF -#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S)) -#define PCNT_CNT_THRES0_U2_V 0xFFFF -#define PCNT_CNT_THRES0_U2_S 0 - -#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020) -/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit2.*/ -#define PCNT_CNT_L_LIM_U2 0x0000FFFF -#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S)) -#define PCNT_CNT_L_LIM_U2_V 0xFFFF -#define PCNT_CNT_L_LIM_U2_S 16 -/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit2.*/ -#define PCNT_CNT_H_LIM_U2 0x0000FFFF -#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S)) -#define PCNT_CNT_H_LIM_U2_V 0xFFFF -#define PCNT_CNT_H_LIM_U2_S 0 - -#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024) -/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U3 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S)) -#define PCNT_CH1_LCTRL_MODE_U3_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U3_S 30 -/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U3 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S)) -#define PCNT_CH1_HCTRL_MODE_U3_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U3_S 28 -/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U3 0x00000003 -#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S)) -#define PCNT_CH1_POS_MODE_U3_V 0x3 -#define PCNT_CH1_POS_MODE_U3_S 26 -/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U3 0x00000003 -#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S)) -#define PCNT_CH1_NEG_MODE_U3_V 0x3 -#define PCNT_CH1_NEG_MODE_U3_S 24 -/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U3 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S)) -#define PCNT_CH0_LCTRL_MODE_U3_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U3_S 22 -/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U3 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S)) -#define PCNT_CH0_HCTRL_MODE_U3_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U3_S 20 -/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U3 0x00000003 -#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S)) -#define PCNT_CH0_POS_MODE_U3_V 0x3 -#define PCNT_CH0_POS_MODE_U3_S 18 -/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U3 0x00000003 -#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S)) -#define PCNT_CH0_NEG_MODE_U3_V 0x3 -#define PCNT_CH0_NEG_MODE_U3_S 16 -/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit3's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U3 (BIT(15)) -#define PCNT_THR_THRES1_EN_U3_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U3_V 0x1 -#define PCNT_THR_THRES1_EN_U3_S 15 -/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit3's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U3 (BIT(14)) -#define PCNT_THR_THRES0_EN_U3_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U3_V 0x1 -#define PCNT_THR_THRES0_EN_U3_S 14 -/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit3's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U3_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U3_V 0x1 -#define PCNT_THR_L_LIM_EN_U3_S 13 -/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit3's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U3_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U3_V 0x1 -#define PCNT_THR_H_LIM_EN_U3_S 12 -/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit3's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U3 (BIT(11)) -#define PCNT_THR_ZERO_EN_U3_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U3_V 0x1 -#define PCNT_THR_ZERO_EN_U3_S 11 -/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit3.*/ -#define PCNT_FILTER_EN_U3 (BIT(10)) -#define PCNT_FILTER_EN_U3_M (BIT(10)) -#define PCNT_FILTER_EN_U3_V 0x1 -#define PCNT_FILTER_EN_U3_S 10 -/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit3.*/ -#define PCNT_FILTER_THRES_U3 0x000003FF -#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S)) -#define PCNT_FILTER_THRES_U3_V 0x3FF -#define PCNT_FILTER_THRES_U3_S 0 - -#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028) -/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit3.*/ -#define PCNT_CNT_THRES1_U3 0x0000FFFF -#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S)) -#define PCNT_CNT_THRES1_U3_V 0xFFFF -#define PCNT_CNT_THRES1_U3_S 16 -/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit3.*/ -#define PCNT_CNT_THRES0_U3 0x0000FFFF -#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S)) -#define PCNT_CNT_THRES0_U3_V 0xFFFF -#define PCNT_CNT_THRES0_U3_S 0 - -#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c) -/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit3.*/ -#define PCNT_CNT_L_LIM_U3 0x0000FFFF -#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S)) -#define PCNT_CNT_L_LIM_U3_V 0xFFFF -#define PCNT_CNT_L_LIM_U3_S 16 -/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit3.*/ -#define PCNT_CNT_H_LIM_U3 0x0000FFFF -#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S)) -#define PCNT_CNT_H_LIM_U3_V 0xFFFF -#define PCNT_CNT_H_LIM_U3_S 0 - -#define PCNT_U4_CONF0_REG (DR_REG_PCNT_BASE + 0x0030) -/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U4 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U4_M ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S)) -#define PCNT_CH1_LCTRL_MODE_U4_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U4_S 30 -/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U4 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U4_M ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S)) -#define PCNT_CH1_HCTRL_MODE_U4_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U4_S 28 -/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U4 0x00000003 -#define PCNT_CH1_POS_MODE_U4_M ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S)) -#define PCNT_CH1_POS_MODE_U4_V 0x3 -#define PCNT_CH1_POS_MODE_U4_S 26 -/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U4 0x00000003 -#define PCNT_CH1_NEG_MODE_U4_M ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S)) -#define PCNT_CH1_NEG_MODE_U4_V 0x3 -#define PCNT_CH1_NEG_MODE_U4_S 24 -/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U4 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U4_M ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S)) -#define PCNT_CH0_LCTRL_MODE_U4_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U4_S 22 -/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U4 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U4_M ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S)) -#define PCNT_CH0_HCTRL_MODE_U4_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U4_S 20 -/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U4 0x00000003 -#define PCNT_CH0_POS_MODE_U4_M ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S)) -#define PCNT_CH0_POS_MODE_U4_V 0x3 -#define PCNT_CH0_POS_MODE_U4_S 18 -/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U4 0x00000003 -#define PCNT_CH0_NEG_MODE_U4_M ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S)) -#define PCNT_CH0_NEG_MODE_U4_V 0x3 -#define PCNT_CH0_NEG_MODE_U4_S 16 -/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit4's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U4 (BIT(15)) -#define PCNT_THR_THRES1_EN_U4_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U4_V 0x1 -#define PCNT_THR_THRES1_EN_U4_S 15 -/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit4's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U4 (BIT(14)) -#define PCNT_THR_THRES0_EN_U4_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U4_V 0x1 -#define PCNT_THR_THRES0_EN_U4_S 14 -/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit4's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U4 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U4_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U4_V 0x1 -#define PCNT_THR_L_LIM_EN_U4_S 13 -/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit4's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U4 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U4_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U4_V 0x1 -#define PCNT_THR_H_LIM_EN_U4_S 12 -/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit4's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U4 (BIT(11)) -#define PCNT_THR_ZERO_EN_U4_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U4_V 0x1 -#define PCNT_THR_ZERO_EN_U4_S 11 -/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit4.*/ -#define PCNT_FILTER_EN_U4 (BIT(10)) -#define PCNT_FILTER_EN_U4_M (BIT(10)) -#define PCNT_FILTER_EN_U4_V 0x1 -#define PCNT_FILTER_EN_U4_S 10 -/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit4.*/ -#define PCNT_FILTER_THRES_U4 0x000003FF -#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S)) -#define PCNT_FILTER_THRES_U4_V 0x3FF -#define PCNT_FILTER_THRES_U4_S 0 - -#define PCNT_U4_CONF1_REG (DR_REG_PCNT_BASE + 0x0034) -/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit4.*/ -#define PCNT_CNT_THRES1_U4 0x0000FFFF -#define PCNT_CNT_THRES1_U4_M ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S)) -#define PCNT_CNT_THRES1_U4_V 0xFFFF -#define PCNT_CNT_THRES1_U4_S 16 -/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit4.*/ -#define PCNT_CNT_THRES0_U4 0x0000FFFF -#define PCNT_CNT_THRES0_U4_M ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S)) -#define PCNT_CNT_THRES0_U4_V 0xFFFF -#define PCNT_CNT_THRES0_U4_S 0 - -#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038) -/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit4.*/ -#define PCNT_CNT_L_LIM_U4 0x0000FFFF -#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S)) -#define PCNT_CNT_L_LIM_U4_V 0xFFFF -#define PCNT_CNT_L_LIM_U4_S 16 -/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit4.*/ -#define PCNT_CNT_H_LIM_U4 0x0000FFFF -#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S)) -#define PCNT_CNT_H_LIM_U4_V 0xFFFF -#define PCNT_CNT_H_LIM_U4_S 0 - -#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c) -/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U5 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U5_M ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S)) -#define PCNT_CH1_LCTRL_MODE_U5_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U5_S 30 -/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U5 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U5_M ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S)) -#define PCNT_CH1_HCTRL_MODE_U5_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U5_S 28 -/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U5 0x00000003 -#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S)) -#define PCNT_CH1_POS_MODE_U5_V 0x3 -#define PCNT_CH1_POS_MODE_U5_S 26 -/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U5 0x00000003 -#define PCNT_CH1_NEG_MODE_U5_M ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S)) -#define PCNT_CH1_NEG_MODE_U5_V 0x3 -#define PCNT_CH1_NEG_MODE_U5_S 24 -/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U5 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U5_M ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S)) -#define PCNT_CH0_LCTRL_MODE_U5_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U5_S 22 -/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U5 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S)) -#define PCNT_CH0_HCTRL_MODE_U5_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U5_S 20 -/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U5 0x00000003 -#define PCNT_CH0_POS_MODE_U5_M ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S)) -#define PCNT_CH0_POS_MODE_U5_V 0x3 -#define PCNT_CH0_POS_MODE_U5_S 18 -/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U5 0x00000003 -#define PCNT_CH0_NEG_MODE_U5_M ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S)) -#define PCNT_CH0_NEG_MODE_U5_V 0x3 -#define PCNT_CH0_NEG_MODE_U5_S 16 -/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit5's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U5 (BIT(15)) -#define PCNT_THR_THRES1_EN_U5_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U5_V 0x1 -#define PCNT_THR_THRES1_EN_U5_S 15 -/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit5's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U5 (BIT(14)) -#define PCNT_THR_THRES0_EN_U5_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U5_V 0x1 -#define PCNT_THR_THRES0_EN_U5_S 14 -/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit5's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U5 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U5_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U5_V 0x1 -#define PCNT_THR_L_LIM_EN_U5_S 13 -/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit5's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U5 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U5_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U5_V 0x1 -#define PCNT_THR_H_LIM_EN_U5_S 12 -/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit5's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U5 (BIT(11)) -#define PCNT_THR_ZERO_EN_U5_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U5_V 0x1 -#define PCNT_THR_ZERO_EN_U5_S 11 -/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit5.*/ -#define PCNT_FILTER_EN_U5 (BIT(10)) -#define PCNT_FILTER_EN_U5_M (BIT(10)) -#define PCNT_FILTER_EN_U5_V 0x1 -#define PCNT_FILTER_EN_U5_S 10 -/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit5.*/ -#define PCNT_FILTER_THRES_U5 0x000003FF -#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S)) -#define PCNT_FILTER_THRES_U5_V 0x3FF -#define PCNT_FILTER_THRES_U5_S 0 - -#define PCNT_U5_CONF1_REG (DR_REG_PCNT_BASE + 0x0040) -/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit5.*/ -#define PCNT_CNT_THRES1_U5 0x0000FFFF -#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S)) -#define PCNT_CNT_THRES1_U5_V 0xFFFF -#define PCNT_CNT_THRES1_U5_S 16 -/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit5.*/ -#define PCNT_CNT_THRES0_U5 0x0000FFFF -#define PCNT_CNT_THRES0_U5_M ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S)) -#define PCNT_CNT_THRES0_U5_V 0xFFFF -#define PCNT_CNT_THRES0_U5_S 0 - -#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044) -/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit5.*/ -#define PCNT_CNT_L_LIM_U5 0x0000FFFF -#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S)) -#define PCNT_CNT_L_LIM_U5_V 0xFFFF -#define PCNT_CNT_L_LIM_U5_S 16 -/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit5.*/ -#define PCNT_CNT_H_LIM_U5 0x0000FFFF -#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S)) -#define PCNT_CNT_H_LIM_U5_V 0xFFFF -#define PCNT_CNT_H_LIM_U5_S 0 - -#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048) -/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U6 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U6_M ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S)) -#define PCNT_CH1_LCTRL_MODE_U6_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U6_S 30 -/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U6 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U6_M ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S)) -#define PCNT_CH1_HCTRL_MODE_U6_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U6_S 28 -/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U6 0x00000003 -#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S)) -#define PCNT_CH1_POS_MODE_U6_V 0x3 -#define PCNT_CH1_POS_MODE_U6_S 26 -/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U6 0x00000003 -#define PCNT_CH1_NEG_MODE_U6_M ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S)) -#define PCNT_CH1_NEG_MODE_U6_V 0x3 -#define PCNT_CH1_NEG_MODE_U6_S 24 -/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U6 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U6_M ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S)) -#define PCNT_CH0_LCTRL_MODE_U6_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U6_S 22 -/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U6 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S)) -#define PCNT_CH0_HCTRL_MODE_U6_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U6_S 20 -/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U6 0x00000003 -#define PCNT_CH0_POS_MODE_U6_M ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S)) -#define PCNT_CH0_POS_MODE_U6_V 0x3 -#define PCNT_CH0_POS_MODE_U6_S 18 -/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U6 0x00000003 -#define PCNT_CH0_NEG_MODE_U6_M ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S)) -#define PCNT_CH0_NEG_MODE_U6_V 0x3 -#define PCNT_CH0_NEG_MODE_U6_S 16 -/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit6's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U6 (BIT(15)) -#define PCNT_THR_THRES1_EN_U6_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U6_V 0x1 -#define PCNT_THR_THRES1_EN_U6_S 15 -/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit6's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U6 (BIT(14)) -#define PCNT_THR_THRES0_EN_U6_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U6_V 0x1 -#define PCNT_THR_THRES0_EN_U6_S 14 -/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit6's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U6 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U6_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U6_V 0x1 -#define PCNT_THR_L_LIM_EN_U6_S 13 -/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit6's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U6 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U6_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U6_V 0x1 -#define PCNT_THR_H_LIM_EN_U6_S 12 -/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit6's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U6 (BIT(11)) -#define PCNT_THR_ZERO_EN_U6_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U6_V 0x1 -#define PCNT_THR_ZERO_EN_U6_S 11 -/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit6.*/ -#define PCNT_FILTER_EN_U6 (BIT(10)) -#define PCNT_FILTER_EN_U6_M (BIT(10)) -#define PCNT_FILTER_EN_U6_V 0x1 -#define PCNT_FILTER_EN_U6_S 10 -/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit6.*/ -#define PCNT_FILTER_THRES_U6 0x000003FF -#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S)) -#define PCNT_FILTER_THRES_U6_V 0x3FF -#define PCNT_FILTER_THRES_U6_S 0 - -#define PCNT_U6_CONF1_REG (DR_REG_PCNT_BASE + 0x004c) -/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit6.*/ -#define PCNT_CNT_THRES1_U6 0x0000FFFF -#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S)) -#define PCNT_CNT_THRES1_U6_V 0xFFFF -#define PCNT_CNT_THRES1_U6_S 16 -/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit6.*/ -#define PCNT_CNT_THRES0_U6 0x0000FFFF -#define PCNT_CNT_THRES0_U6_M ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S)) -#define PCNT_CNT_THRES0_U6_V 0xFFFF -#define PCNT_CNT_THRES0_U6_S 0 - -#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050) -/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit6.*/ -#define PCNT_CNT_L_LIM_U6 0x0000FFFF -#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S)) -#define PCNT_CNT_L_LIM_U6_V 0xFFFF -#define PCNT_CNT_L_LIM_U6_S 16 -/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit6.*/ -#define PCNT_CNT_H_LIM_U6 0x0000FFFF -#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S)) -#define PCNT_CNT_H_LIM_U6_V 0xFFFF -#define PCNT_CNT_H_LIM_U6_S 0 - -#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054) -/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U7 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U7_M ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S)) -#define PCNT_CH1_LCTRL_MODE_U7_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U7_S 30 -/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U7 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U7_M ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S)) -#define PCNT_CH1_HCTRL_MODE_U7_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U7_S 28 -/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U7 0x00000003 -#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S)) -#define PCNT_CH1_POS_MODE_U7_V 0x3 -#define PCNT_CH1_POS_MODE_U7_S 26 -/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U7 0x00000003 -#define PCNT_CH1_NEG_MODE_U7_M ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S)) -#define PCNT_CH1_NEG_MODE_U7_V 0x3 -#define PCNT_CH1_NEG_MODE_U7_S 24 -/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U7 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U7_M ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S)) -#define PCNT_CH0_LCTRL_MODE_U7_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U7_S 22 -/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U7 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S)) -#define PCNT_CH0_HCTRL_MODE_U7_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U7_S 20 -/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U7 0x00000003 -#define PCNT_CH0_POS_MODE_U7_M ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S)) -#define PCNT_CH0_POS_MODE_U7_V 0x3 -#define PCNT_CH0_POS_MODE_U7_S 18 -/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U7 0x00000003 -#define PCNT_CH0_NEG_MODE_U7_M ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S)) -#define PCNT_CH0_NEG_MODE_U7_V 0x3 -#define PCNT_CH0_NEG_MODE_U7_S 16 -/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit7's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U7 (BIT(15)) -#define PCNT_THR_THRES1_EN_U7_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U7_V 0x1 -#define PCNT_THR_THRES1_EN_U7_S 15 -/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit7's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U7 (BIT(14)) -#define PCNT_THR_THRES0_EN_U7_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U7_V 0x1 -#define PCNT_THR_THRES0_EN_U7_S 14 -/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit7's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U7 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U7_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U7_V 0x1 -#define PCNT_THR_L_LIM_EN_U7_S 13 -/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit7's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U7 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U7_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U7_V 0x1 -#define PCNT_THR_H_LIM_EN_U7_S 12 -/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit7's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U7 (BIT(11)) -#define PCNT_THR_ZERO_EN_U7_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U7_V 0x1 -#define PCNT_THR_ZERO_EN_U7_S 11 -/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit7.*/ -#define PCNT_FILTER_EN_U7 (BIT(10)) -#define PCNT_FILTER_EN_U7_M (BIT(10)) -#define PCNT_FILTER_EN_U7_V 0x1 -#define PCNT_FILTER_EN_U7_S 10 -/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit7.*/ -#define PCNT_FILTER_THRES_U7 0x000003FF -#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S)) -#define PCNT_FILTER_THRES_U7_V 0x3FF -#define PCNT_FILTER_THRES_U7_S 0 - -#define PCNT_U7_CONF1_REG (DR_REG_PCNT_BASE + 0x0058) -/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit7.*/ -#define PCNT_CNT_THRES1_U7 0x0000FFFF -#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S)) -#define PCNT_CNT_THRES1_U7_V 0xFFFF -#define PCNT_CNT_THRES1_U7_S 16 -/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit7.*/ -#define PCNT_CNT_THRES0_U7 0x0000FFFF -#define PCNT_CNT_THRES0_U7_M ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S)) -#define PCNT_CNT_THRES0_U7_V 0xFFFF -#define PCNT_CNT_THRES0_U7_S 0 - -#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c) -/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit7.*/ -#define PCNT_CNT_L_LIM_U7 0x0000FFFF -#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S)) -#define PCNT_CNT_L_LIM_U7_V 0xFFFF -#define PCNT_CNT_L_LIM_U7_S 16 -/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit7.*/ -#define PCNT_CNT_H_LIM_U7 0x0000FFFF -#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S)) -#define PCNT_CNT_H_LIM_U7_V 0xFFFF -#define PCNT_CNT_H_LIM_U7_S 0 - -#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060) -/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit0.*/ -#define PCNT_PLUS_CNT_U0 0x0000FFFF -#define PCNT_PLUS_CNT_U0_M ((PCNT_PLUS_CNT_U0_V)<<(PCNT_PLUS_CNT_U0_S)) -#define PCNT_PLUS_CNT_U0_V 0xFFFF -#define PCNT_PLUS_CNT_U0_S 0 - -#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0064) -/* PCNT_PLUS_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit1.*/ -#define PCNT_PLUS_CNT_U1 0x0000FFFF -#define PCNT_PLUS_CNT_U1_M ((PCNT_PLUS_CNT_U1_V)<<(PCNT_PLUS_CNT_U1_S)) -#define PCNT_PLUS_CNT_U1_V 0xFFFF -#define PCNT_PLUS_CNT_U1_S 0 - -#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0068) -/* PCNT_PLUS_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit2.*/ -#define PCNT_PLUS_CNT_U2 0x0000FFFF -#define PCNT_PLUS_CNT_U2_M ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S)) -#define PCNT_PLUS_CNT_U2_V 0xFFFF -#define PCNT_PLUS_CNT_U2_S 0 - -#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c) -/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit3.*/ -#define PCNT_PLUS_CNT_U3 0x0000FFFF -#define PCNT_PLUS_CNT_U3_M ((PCNT_PLUS_CNT_U3_V)<<(PCNT_PLUS_CNT_U3_S)) -#define PCNT_PLUS_CNT_U3_V 0xFFFF -#define PCNT_PLUS_CNT_U3_S 0 - -#define PCNT_U4_CNT_REG (DR_REG_PCNT_BASE + 0x0070) -/* PCNT_PLUS_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit4.*/ -#define PCNT_PLUS_CNT_U4 0x0000FFFF -#define PCNT_PLUS_CNT_U4_M ((PCNT_PLUS_CNT_U4_V)<<(PCNT_PLUS_CNT_U4_S)) -#define PCNT_PLUS_CNT_U4_V 0xFFFF -#define PCNT_PLUS_CNT_U4_S 0 - -#define PCNT_U5_CNT_REG (DR_REG_PCNT_BASE + 0x0074) -/* PCNT_PLUS_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit5.*/ -#define PCNT_PLUS_CNT_U5 0x0000FFFF -#define PCNT_PLUS_CNT_U5_M ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S)) -#define PCNT_PLUS_CNT_U5_V 0xFFFF -#define PCNT_PLUS_CNT_U5_S 0 - -#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078) -/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit6.*/ -#define PCNT_PLUS_CNT_U6 0x0000FFFF -#define PCNT_PLUS_CNT_U6_M ((PCNT_PLUS_CNT_U6_V)<<(PCNT_PLUS_CNT_U6_S)) -#define PCNT_PLUS_CNT_U6_V 0xFFFF -#define PCNT_PLUS_CNT_U6_S 0 - -#define PCNT_U7_CNT_REG (DR_REG_PCNT_BASE + 0x007c) -/* PCNT_PLUS_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit7.*/ -#define PCNT_PLUS_CNT_U7 0x0000FFFF -#define PCNT_PLUS_CNT_U7_M ((PCNT_PLUS_CNT_U7_V)<<(PCNT_PLUS_CNT_U7_S)) -#define PCNT_PLUS_CNT_U7_V 0xFFFF -#define PCNT_PLUS_CNT_U7_S 0 - -#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0080) -/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel7 event.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel6 event.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_RAW (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel5 event.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_RAW (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel4 event.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_RAW (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S 4 -/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel3 event.*/ -#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 -/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel2 event.*/ -#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 -/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel1 event.*/ -#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 -/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel0 event.*/ -#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 - -#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0084) -/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel7 event.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel6 event.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_ST (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ST_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_ST_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel5 event.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_ST (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ST_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_ST_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel4 event.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_ST (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ST_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_ST_S 4 -/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel3 event.*/ -#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 -/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel2 event.*/ -#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 -/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel1 event.*/ -#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 -/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel0 event.*/ -#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 - -#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0088) -/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel7 event.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel6 event.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_ENA (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel5 event.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_ENA (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel4 event.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_ENA (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S 4 -/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel3 event.*/ -#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 -/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel2 event.*/ -#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 -/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel1 event.*/ -#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 -/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel0 event.*/ -#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 - -#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x008c) -/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel7 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel6 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_CLR (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel5 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_CLR (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel4 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_CLR (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S 4 -/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel3 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 -/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel2 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 -/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel1 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 -/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel0 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 - -#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0090) -/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U0 0xFFFFFFFF -#define PCNT_CORE_STATUS_U0_M ((PCNT_CORE_STATUS_U0_V)<<(PCNT_CORE_STATUS_U0_S)) -#define PCNT_CORE_STATUS_U0_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U0_S 0 -/*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/ -#define PCNT_STATUS_CNT_MODE 0x3 -#define PCNT_STATUS_CNT_MODE_M ((PCNT_STATUS_CNT_MODE_V)<<(PCNT_STATUS_CNT_MODE_S)) -#define PCNT_STATUS_CNT_MODE_V 0x3 -#define PCNT_STATUS_CNT_MODE_S 0 -/* counter value equals to thresh1*/ -#define PCNT_STATUS_THRES1 BIT(2) -#define PCNT_STATUS_THRES1_M BIT(2) -#define PCNT_STATUS_THRES1_V 0x1 -#define PCNT_STATUS_THRES1_S 2 -/* counter value equals to thresh0*/ -#define PCNT_STATUS_THRES0 BIT(3) -#define PCNT_STATUS_THRES0_M BIT(3) -#define PCNT_STATUS_THRES0_V 0x1 -#define PCNT_STATUS_THRES0_S 3 -/* counter value reaches h_lim*/ -#define PCNT_STATUS_L_LIM BIT(4) -#define PCNT_STATUS_L_LIM_M BIT(4) -#define PCNT_STATUS_L_LIM_V 0x1 -#define PCNT_STATUS_L_LIM_S 4 -/* counter value reaches l_lim*/ -#define PCNT_STATUS_H_LIM BIT(5) -#define PCNT_STATUS_H_LIM_M BIT(5) -#define PCNT_STATUS_H_LIM_V 0x1 -#define PCNT_STATUS_H_LIM_S 5 -/* counter value equals to zero*/ -#define PCNT_STATUS_ZERO BIT(6) -#define PCNT_STATUS_ZERO_M BIT(6) -#define PCNT_STATUS_ZERO_V 0x1 -#define PCNT_STATUS_ZERO_S 6 - -#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0094) -/* PCNT_CORE_STATUS_U1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U1 0xFFFFFFFF -#define PCNT_CORE_STATUS_U1_M ((PCNT_CORE_STATUS_U1_V)<<(PCNT_CORE_STATUS_U1_S)) -#define PCNT_CORE_STATUS_U1_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U1_S 0 - -#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0098) -/* PCNT_CORE_STATUS_U2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U2 0xFFFFFFFF -#define PCNT_CORE_STATUS_U2_M ((PCNT_CORE_STATUS_U2_V)<<(PCNT_CORE_STATUS_U2_S)) -#define PCNT_CORE_STATUS_U2_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U2_S 0 - -#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x009c) -/* PCNT_CORE_STATUS_U3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U3 0xFFFFFFFF -#define PCNT_CORE_STATUS_U3_M ((PCNT_CORE_STATUS_U3_V)<<(PCNT_CORE_STATUS_U3_S)) -#define PCNT_CORE_STATUS_U3_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U3_S 0 - -#define PCNT_U4_STATUS_REG (DR_REG_PCNT_BASE + 0x00a0) -/* PCNT_CORE_STATUS_U4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U4 0xFFFFFFFF -#define PCNT_CORE_STATUS_U4_M ((PCNT_CORE_STATUS_U4_V)<<(PCNT_CORE_STATUS_U4_S)) -#define PCNT_CORE_STATUS_U4_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U4_S 0 - -#define PCNT_U5_STATUS_REG (DR_REG_PCNT_BASE + 0x00a4) -/* PCNT_CORE_STATUS_U5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U5 0xFFFFFFFF -#define PCNT_CORE_STATUS_U5_M ((PCNT_CORE_STATUS_U5_V)<<(PCNT_CORE_STATUS_U5_S)) -#define PCNT_CORE_STATUS_U5_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U5_S 0 - -#define PCNT_U6_STATUS_REG (DR_REG_PCNT_BASE + 0x00a8) -/* PCNT_CORE_STATUS_U6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U6 0xFFFFFFFF -#define PCNT_CORE_STATUS_U6_M ((PCNT_CORE_STATUS_U6_V)<<(PCNT_CORE_STATUS_U6_S)) -#define PCNT_CORE_STATUS_U6_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U6_S 0 - -#define PCNT_U7_STATUS_REG (DR_REG_PCNT_BASE + 0x00ac) -/* PCNT_CORE_STATUS_U7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U7 0xFFFFFFFF -#define PCNT_CORE_STATUS_U7_M ((PCNT_CORE_STATUS_U7_V)<<(PCNT_CORE_STATUS_U7_S)) -#define PCNT_CORE_STATUS_U7_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U7_S 0 - -#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x00b0) -/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CLK_EN (BIT(16)) -#define PCNT_CLK_EN_M (BIT(16)) -#define PCNT_CLK_EN_V 0x1 -#define PCNT_CLK_EN_S 16 -/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit7's counter.*/ -#define PCNT_CNT_PAUSE_U7 (BIT(15)) -#define PCNT_CNT_PAUSE_U7_M (BIT(15)) -#define PCNT_CNT_PAUSE_U7_V 0x1 -#define PCNT_CNT_PAUSE_U7_S 15 -/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit7's counter.*/ -#define PCNT_PLUS_CNT_RST_U7 (BIT(14)) -#define PCNT_PLUS_CNT_RST_U7_M (BIT(14)) -#define PCNT_PLUS_CNT_RST_U7_V 0x1 -#define PCNT_PLUS_CNT_RST_U7_S 14 -/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit6's counter.*/ -#define PCNT_CNT_PAUSE_U6 (BIT(13)) -#define PCNT_CNT_PAUSE_U6_M (BIT(13)) -#define PCNT_CNT_PAUSE_U6_V 0x1 -#define PCNT_CNT_PAUSE_U6_S 13 -/* PCNT_PLUS_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit6's counter.*/ -#define PCNT_PLUS_CNT_RST_U6 (BIT(12)) -#define PCNT_PLUS_CNT_RST_U6_M (BIT(12)) -#define PCNT_PLUS_CNT_RST_U6_V 0x1 -#define PCNT_PLUS_CNT_RST_U6_S 12 -/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit5's counter.*/ -#define PCNT_CNT_PAUSE_U5 (BIT(11)) -#define PCNT_CNT_PAUSE_U5_M (BIT(11)) -#define PCNT_CNT_PAUSE_U5_V 0x1 -#define PCNT_CNT_PAUSE_U5_S 11 -/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit5's counter.*/ -#define PCNT_PLUS_CNT_RST_U5 (BIT(10)) -#define PCNT_PLUS_CNT_RST_U5_M (BIT(10)) -#define PCNT_PLUS_CNT_RST_U5_V 0x1 -#define PCNT_PLUS_CNT_RST_U5_S 10 -/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit4's counter.*/ -#define PCNT_CNT_PAUSE_U4 (BIT(9)) -#define PCNT_CNT_PAUSE_U4_M (BIT(9)) -#define PCNT_CNT_PAUSE_U4_V 0x1 -#define PCNT_CNT_PAUSE_U4_S 9 -/* PCNT_PLUS_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit4's counter.*/ -#define PCNT_PLUS_CNT_RST_U4 (BIT(8)) -#define PCNT_PLUS_CNT_RST_U4_M (BIT(8)) -#define PCNT_PLUS_CNT_RST_U4_V 0x1 -#define PCNT_PLUS_CNT_RST_U4_S 8 -/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit3's counter.*/ -#define PCNT_CNT_PAUSE_U3 (BIT(7)) -#define PCNT_CNT_PAUSE_U3_M (BIT(7)) -#define PCNT_CNT_PAUSE_U3_V 0x1 -#define PCNT_CNT_PAUSE_U3_S 7 -/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit3's counter.*/ -#define PCNT_PLUS_CNT_RST_U3 (BIT(6)) -#define PCNT_PLUS_CNT_RST_U3_M (BIT(6)) -#define PCNT_PLUS_CNT_RST_U3_V 0x1 -#define PCNT_PLUS_CNT_RST_U3_S 6 -/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit2's counter.*/ -#define PCNT_CNT_PAUSE_U2 (BIT(5)) -#define PCNT_CNT_PAUSE_U2_M (BIT(5)) -#define PCNT_CNT_PAUSE_U2_V 0x1 -#define PCNT_CNT_PAUSE_U2_S 5 -/* PCNT_PLUS_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit2's counter.*/ -#define PCNT_PLUS_CNT_RST_U2 (BIT(4)) -#define PCNT_PLUS_CNT_RST_U2_M (BIT(4)) -#define PCNT_PLUS_CNT_RST_U2_V 0x1 -#define PCNT_PLUS_CNT_RST_U2_S 4 -/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit1's counter.*/ -#define PCNT_CNT_PAUSE_U1 (BIT(3)) -#define PCNT_CNT_PAUSE_U1_M (BIT(3)) -#define PCNT_CNT_PAUSE_U1_V 0x1 -#define PCNT_CNT_PAUSE_U1_S 3 -/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit1's counter.*/ -#define PCNT_PLUS_CNT_RST_U1 (BIT(2)) -#define PCNT_PLUS_CNT_RST_U1_M (BIT(2)) -#define PCNT_PLUS_CNT_RST_U1_V 0x1 -#define PCNT_PLUS_CNT_RST_U1_S 2 -/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit0's counter.*/ -#define PCNT_CNT_PAUSE_U0 (BIT(1)) -#define PCNT_CNT_PAUSE_U0_M (BIT(1)) -#define PCNT_CNT_PAUSE_U0_V 0x1 -#define PCNT_CNT_PAUSE_U0_S 1 -/* PCNT_PLUS_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit0's counter.*/ -#define PCNT_PLUS_CNT_RST_U0 (BIT(0)) -#define PCNT_PLUS_CNT_RST_U0_M (BIT(0)) -#define PCNT_PLUS_CNT_RST_U0_V 0x1 -#define PCNT_PLUS_CNT_RST_U0_S 0 - -#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc) -/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */ -/*description: */ -#define PCNT_DATE 0xFFFFFFFF -#define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S)) -#define PCNT_DATE_V 0xFFFFFFFF -#define PCNT_DATE_S 0 - - - - -#endif /*_SOC_PCNT_REG_H_ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PCNT_REG_H_ +#define _SOC_PCNT_REG_H_ + + +#include "soc.h" +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000) +/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S)) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U0_S 30 +/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S)) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U0 0x00000003 +#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S)) +#define PCNT_CH1_POS_MODE_U0_V 0x3 +#define PCNT_CH1_POS_MODE_U0_S 26 +/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U0 0x00000003 +#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S)) +#define PCNT_CH1_NEG_MODE_U0_V 0x3 +#define PCNT_CH1_NEG_MODE_U0_S 24 +/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S)) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S)) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U0 0x00000003 +#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S)) +#define PCNT_CH0_POS_MODE_U0_V 0x3 +#define PCNT_CH0_POS_MODE_U0_S 18 +/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U0 0x00000003 +#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S)) +#define PCNT_CH0_NEG_MODE_U0_V 0x3 +#define PCNT_CH0_NEG_MODE_U0_S 16 +/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit0's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_V 0x1 +#define PCNT_THR_THRES1_EN_U0_S 15 +/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit0's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_V 0x1 +#define PCNT_THR_THRES0_EN_U0_S 14 +/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_V 0x1 +#define PCNT_THR_L_LIM_EN_U0_S 13 +/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_V 0x1 +#define PCNT_THR_H_LIM_EN_U0_S 12 +/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_V 0x1 +#define PCNT_THR_ZERO_EN_U0_S 11 +/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit0.*/ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (BIT(10)) +#define PCNT_FILTER_EN_U0_V 0x1 +#define PCNT_FILTER_EN_U0_S 10 +/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit0.*/ +#define PCNT_FILTER_THRES_U0 0x000003FF +#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S)) +#define PCNT_FILTER_THRES_U0_V 0x3FF +#define PCNT_FILTER_THRES_U0_S 0 + +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004) +/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit0.*/ +#define PCNT_CNT_THRES1_U0 0x0000FFFF +#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S)) +#define PCNT_CNT_THRES1_U0_V 0xFFFF +#define PCNT_CNT_THRES1_U0_S 16 +/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit0.*/ +#define PCNT_CNT_THRES0_U0 0x0000FFFF +#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S)) +#define PCNT_CNT_THRES0_U0_V 0xFFFF +#define PCNT_CNT_THRES0_U0_S 0 + +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008) +/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit0.*/ +#define PCNT_CNT_L_LIM_U0 0x0000FFFF +#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S)) +#define PCNT_CNT_L_LIM_U0_V 0xFFFF +#define PCNT_CNT_L_LIM_U0_S 16 +/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit0.*/ +#define PCNT_CNT_H_LIM_U0 0x0000FFFF +#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S)) +#define PCNT_CNT_H_LIM_U0_V 0xFFFF +#define PCNT_CNT_H_LIM_U0_S 0 + +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c) +/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S)) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U1_S 30 +/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S)) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U1 0x00000003 +#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S)) +#define PCNT_CH1_POS_MODE_U1_V 0x3 +#define PCNT_CH1_POS_MODE_U1_S 26 +/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U1 0x00000003 +#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S)) +#define PCNT_CH1_NEG_MODE_U1_V 0x3 +#define PCNT_CH1_NEG_MODE_U1_S 24 +/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S)) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S)) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U1 0x00000003 +#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S)) +#define PCNT_CH0_POS_MODE_U1_V 0x3 +#define PCNT_CH0_POS_MODE_U1_S 18 +/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U1 0x00000003 +#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S)) +#define PCNT_CH0_NEG_MODE_U1_V 0x3 +#define PCNT_CH0_NEG_MODE_U1_S 16 +/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit1's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_V 0x1 +#define PCNT_THR_THRES1_EN_U1_S 15 +/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit1's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_V 0x1 +#define PCNT_THR_THRES0_EN_U1_S 14 +/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_V 0x1 +#define PCNT_THR_L_LIM_EN_U1_S 13 +/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_V 0x1 +#define PCNT_THR_H_LIM_EN_U1_S 12 +/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_V 0x1 +#define PCNT_THR_ZERO_EN_U1_S 11 +/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit1.*/ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (BIT(10)) +#define PCNT_FILTER_EN_U1_V 0x1 +#define PCNT_FILTER_EN_U1_S 10 +/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit1.*/ +#define PCNT_FILTER_THRES_U1 0x000003FF +#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S)) +#define PCNT_FILTER_THRES_U1_V 0x3FF +#define PCNT_FILTER_THRES_U1_S 0 + +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010) +/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit1.*/ +#define PCNT_CNT_THRES1_U1 0x0000FFFF +#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S)) +#define PCNT_CNT_THRES1_U1_V 0xFFFF +#define PCNT_CNT_THRES1_U1_S 16 +/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit1.*/ +#define PCNT_CNT_THRES0_U1 0x0000FFFF +#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S)) +#define PCNT_CNT_THRES0_U1_V 0xFFFF +#define PCNT_CNT_THRES0_U1_S 0 + +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014) +/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit1.*/ +#define PCNT_CNT_L_LIM_U1 0x0000FFFF +#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S)) +#define PCNT_CNT_L_LIM_U1_V 0xFFFF +#define PCNT_CNT_L_LIM_U1_S 16 +/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit1.*/ +#define PCNT_CNT_H_LIM_U1 0x0000FFFF +#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S)) +#define PCNT_CNT_H_LIM_U1_V 0xFFFF +#define PCNT_CNT_H_LIM_U1_S 0 + +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018) +/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S)) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U2_S 30 +/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S)) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U2 0x00000003 +#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S)) +#define PCNT_CH1_POS_MODE_U2_V 0x3 +#define PCNT_CH1_POS_MODE_U2_S 26 +/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U2 0x00000003 +#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S)) +#define PCNT_CH1_NEG_MODE_U2_V 0x3 +#define PCNT_CH1_NEG_MODE_U2_S 24 +/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S)) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S)) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U2 0x00000003 +#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S)) +#define PCNT_CH0_POS_MODE_U2_V 0x3 +#define PCNT_CH0_POS_MODE_U2_S 18 +/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U2 0x00000003 +#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S)) +#define PCNT_CH0_NEG_MODE_U2_V 0x3 +#define PCNT_CH0_NEG_MODE_U2_S 16 +/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit2's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_V 0x1 +#define PCNT_THR_THRES1_EN_U2_S 15 +/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit2's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_V 0x1 +#define PCNT_THR_THRES0_EN_U2_S 14 +/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_V 0x1 +#define PCNT_THR_L_LIM_EN_U2_S 13 +/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_V 0x1 +#define PCNT_THR_H_LIM_EN_U2_S 12 +/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_V 0x1 +#define PCNT_THR_ZERO_EN_U2_S 11 +/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit2.*/ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (BIT(10)) +#define PCNT_FILTER_EN_U2_V 0x1 +#define PCNT_FILTER_EN_U2_S 10 +/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit2.*/ +#define PCNT_FILTER_THRES_U2 0x000003FF +#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S)) +#define PCNT_FILTER_THRES_U2_V 0x3FF +#define PCNT_FILTER_THRES_U2_S 0 + +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c) +/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit2.*/ +#define PCNT_CNT_THRES1_U2 0x0000FFFF +#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S)) +#define PCNT_CNT_THRES1_U2_V 0xFFFF +#define PCNT_CNT_THRES1_U2_S 16 +/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit2.*/ +#define PCNT_CNT_THRES0_U2 0x0000FFFF +#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S)) +#define PCNT_CNT_THRES0_U2_V 0xFFFF +#define PCNT_CNT_THRES0_U2_S 0 + +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020) +/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit2.*/ +#define PCNT_CNT_L_LIM_U2 0x0000FFFF +#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S)) +#define PCNT_CNT_L_LIM_U2_V 0xFFFF +#define PCNT_CNT_L_LIM_U2_S 16 +/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit2.*/ +#define PCNT_CNT_H_LIM_U2 0x0000FFFF +#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S)) +#define PCNT_CNT_H_LIM_U2_V 0xFFFF +#define PCNT_CNT_H_LIM_U2_S 0 + +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024) +/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S)) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U3_S 30 +/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S)) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U3 0x00000003 +#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S)) +#define PCNT_CH1_POS_MODE_U3_V 0x3 +#define PCNT_CH1_POS_MODE_U3_S 26 +/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U3 0x00000003 +#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S)) +#define PCNT_CH1_NEG_MODE_U3_V 0x3 +#define PCNT_CH1_NEG_MODE_U3_S 24 +/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S)) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S)) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U3 0x00000003 +#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S)) +#define PCNT_CH0_POS_MODE_U3_V 0x3 +#define PCNT_CH0_POS_MODE_U3_S 18 +/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U3 0x00000003 +#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S)) +#define PCNT_CH0_NEG_MODE_U3_V 0x3 +#define PCNT_CH0_NEG_MODE_U3_S 16 +/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit3's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_V 0x1 +#define PCNT_THR_THRES1_EN_U3_S 15 +/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit3's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_V 0x1 +#define PCNT_THR_THRES0_EN_U3_S 14 +/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_V 0x1 +#define PCNT_THR_L_LIM_EN_U3_S 13 +/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_V 0x1 +#define PCNT_THR_H_LIM_EN_U3_S 12 +/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_V 0x1 +#define PCNT_THR_ZERO_EN_U3_S 11 +/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit3.*/ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (BIT(10)) +#define PCNT_FILTER_EN_U3_V 0x1 +#define PCNT_FILTER_EN_U3_S 10 +/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit3.*/ +#define PCNT_FILTER_THRES_U3 0x000003FF +#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S)) +#define PCNT_FILTER_THRES_U3_V 0x3FF +#define PCNT_FILTER_THRES_U3_S 0 + +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028) +/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit3.*/ +#define PCNT_CNT_THRES1_U3 0x0000FFFF +#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S)) +#define PCNT_CNT_THRES1_U3_V 0xFFFF +#define PCNT_CNT_THRES1_U3_S 16 +/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit3.*/ +#define PCNT_CNT_THRES0_U3 0x0000FFFF +#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S)) +#define PCNT_CNT_THRES0_U3_V 0xFFFF +#define PCNT_CNT_THRES0_U3_S 0 + +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c) +/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit3.*/ +#define PCNT_CNT_L_LIM_U3 0x0000FFFF +#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S)) +#define PCNT_CNT_L_LIM_U3_V 0xFFFF +#define PCNT_CNT_L_LIM_U3_S 16 +/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit3.*/ +#define PCNT_CNT_H_LIM_U3 0x0000FFFF +#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S)) +#define PCNT_CNT_H_LIM_U3_V 0xFFFF +#define PCNT_CNT_H_LIM_U3_S 0 + +#define PCNT_U4_CONF0_REG (DR_REG_PCNT_BASE + 0x0030) +/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U4 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U4_M ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S)) +#define PCNT_CH1_LCTRL_MODE_U4_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U4_S 30 +/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U4 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U4_M ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S)) +#define PCNT_CH1_HCTRL_MODE_U4_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U4_S 28 +/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U4 0x00000003 +#define PCNT_CH1_POS_MODE_U4_M ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S)) +#define PCNT_CH1_POS_MODE_U4_V 0x3 +#define PCNT_CH1_POS_MODE_U4_S 26 +/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U4 0x00000003 +#define PCNT_CH1_NEG_MODE_U4_M ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S)) +#define PCNT_CH1_NEG_MODE_U4_V 0x3 +#define PCNT_CH1_NEG_MODE_U4_S 24 +/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U4 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U4_M ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S)) +#define PCNT_CH0_LCTRL_MODE_U4_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U4_S 22 +/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U4 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U4_M ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S)) +#define PCNT_CH0_HCTRL_MODE_U4_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U4_S 20 +/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U4 0x00000003 +#define PCNT_CH0_POS_MODE_U4_M ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S)) +#define PCNT_CH0_POS_MODE_U4_V 0x3 +#define PCNT_CH0_POS_MODE_U4_S 18 +/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U4 0x00000003 +#define PCNT_CH0_NEG_MODE_U4_M ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S)) +#define PCNT_CH0_NEG_MODE_U4_V 0x3 +#define PCNT_CH0_NEG_MODE_U4_S 16 +/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit4's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U4 (BIT(15)) +#define PCNT_THR_THRES1_EN_U4_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U4_V 0x1 +#define PCNT_THR_THRES1_EN_U4_S 15 +/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit4's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U4 (BIT(14)) +#define PCNT_THR_THRES0_EN_U4_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U4_V 0x1 +#define PCNT_THR_THRES0_EN_U4_S 14 +/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U4 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U4_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U4_V 0x1 +#define PCNT_THR_L_LIM_EN_U4_S 13 +/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U4 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U4_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U4_V 0x1 +#define PCNT_THR_H_LIM_EN_U4_S 12 +/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U4 (BIT(11)) +#define PCNT_THR_ZERO_EN_U4_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U4_V 0x1 +#define PCNT_THR_ZERO_EN_U4_S 11 +/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit4.*/ +#define PCNT_FILTER_EN_U4 (BIT(10)) +#define PCNT_FILTER_EN_U4_M (BIT(10)) +#define PCNT_FILTER_EN_U4_V 0x1 +#define PCNT_FILTER_EN_U4_S 10 +/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit4.*/ +#define PCNT_FILTER_THRES_U4 0x000003FF +#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S)) +#define PCNT_FILTER_THRES_U4_V 0x3FF +#define PCNT_FILTER_THRES_U4_S 0 + +#define PCNT_U4_CONF1_REG (DR_REG_PCNT_BASE + 0x0034) +/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit4.*/ +#define PCNT_CNT_THRES1_U4 0x0000FFFF +#define PCNT_CNT_THRES1_U4_M ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S)) +#define PCNT_CNT_THRES1_U4_V 0xFFFF +#define PCNT_CNT_THRES1_U4_S 16 +/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit4.*/ +#define PCNT_CNT_THRES0_U4 0x0000FFFF +#define PCNT_CNT_THRES0_U4_M ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S)) +#define PCNT_CNT_THRES0_U4_V 0xFFFF +#define PCNT_CNT_THRES0_U4_S 0 + +#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038) +/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit4.*/ +#define PCNT_CNT_L_LIM_U4 0x0000FFFF +#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S)) +#define PCNT_CNT_L_LIM_U4_V 0xFFFF +#define PCNT_CNT_L_LIM_U4_S 16 +/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit4.*/ +#define PCNT_CNT_H_LIM_U4 0x0000FFFF +#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S)) +#define PCNT_CNT_H_LIM_U4_V 0xFFFF +#define PCNT_CNT_H_LIM_U4_S 0 + +#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c) +/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U5 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U5_M ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S)) +#define PCNT_CH1_LCTRL_MODE_U5_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U5_S 30 +/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U5 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U5_M ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S)) +#define PCNT_CH1_HCTRL_MODE_U5_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U5_S 28 +/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U5 0x00000003 +#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S)) +#define PCNT_CH1_POS_MODE_U5_V 0x3 +#define PCNT_CH1_POS_MODE_U5_S 26 +/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U5 0x00000003 +#define PCNT_CH1_NEG_MODE_U5_M ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S)) +#define PCNT_CH1_NEG_MODE_U5_V 0x3 +#define PCNT_CH1_NEG_MODE_U5_S 24 +/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U5 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U5_M ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S)) +#define PCNT_CH0_LCTRL_MODE_U5_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U5_S 22 +/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U5 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S)) +#define PCNT_CH0_HCTRL_MODE_U5_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U5_S 20 +/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U5 0x00000003 +#define PCNT_CH0_POS_MODE_U5_M ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S)) +#define PCNT_CH0_POS_MODE_U5_V 0x3 +#define PCNT_CH0_POS_MODE_U5_S 18 +/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U5 0x00000003 +#define PCNT_CH0_NEG_MODE_U5_M ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S)) +#define PCNT_CH0_NEG_MODE_U5_V 0x3 +#define PCNT_CH0_NEG_MODE_U5_S 16 +/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit5's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U5 (BIT(15)) +#define PCNT_THR_THRES1_EN_U5_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U5_V 0x1 +#define PCNT_THR_THRES1_EN_U5_S 15 +/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit5's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U5 (BIT(14)) +#define PCNT_THR_THRES0_EN_U5_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U5_V 0x1 +#define PCNT_THR_THRES0_EN_U5_S 14 +/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U5 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U5_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U5_V 0x1 +#define PCNT_THR_L_LIM_EN_U5_S 13 +/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U5 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U5_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U5_V 0x1 +#define PCNT_THR_H_LIM_EN_U5_S 12 +/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U5 (BIT(11)) +#define PCNT_THR_ZERO_EN_U5_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U5_V 0x1 +#define PCNT_THR_ZERO_EN_U5_S 11 +/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit5.*/ +#define PCNT_FILTER_EN_U5 (BIT(10)) +#define PCNT_FILTER_EN_U5_M (BIT(10)) +#define PCNT_FILTER_EN_U5_V 0x1 +#define PCNT_FILTER_EN_U5_S 10 +/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit5.*/ +#define PCNT_FILTER_THRES_U5 0x000003FF +#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S)) +#define PCNT_FILTER_THRES_U5_V 0x3FF +#define PCNT_FILTER_THRES_U5_S 0 + +#define PCNT_U5_CONF1_REG (DR_REG_PCNT_BASE + 0x0040) +/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit5.*/ +#define PCNT_CNT_THRES1_U5 0x0000FFFF +#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S)) +#define PCNT_CNT_THRES1_U5_V 0xFFFF +#define PCNT_CNT_THRES1_U5_S 16 +/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit5.*/ +#define PCNT_CNT_THRES0_U5 0x0000FFFF +#define PCNT_CNT_THRES0_U5_M ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S)) +#define PCNT_CNT_THRES0_U5_V 0xFFFF +#define PCNT_CNT_THRES0_U5_S 0 + +#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044) +/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit5.*/ +#define PCNT_CNT_L_LIM_U5 0x0000FFFF +#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S)) +#define PCNT_CNT_L_LIM_U5_V 0xFFFF +#define PCNT_CNT_L_LIM_U5_S 16 +/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit5.*/ +#define PCNT_CNT_H_LIM_U5 0x0000FFFF +#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S)) +#define PCNT_CNT_H_LIM_U5_V 0xFFFF +#define PCNT_CNT_H_LIM_U5_S 0 + +#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048) +/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U6 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U6_M ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S)) +#define PCNT_CH1_LCTRL_MODE_U6_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U6_S 30 +/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U6 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U6_M ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S)) +#define PCNT_CH1_HCTRL_MODE_U6_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U6_S 28 +/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U6 0x00000003 +#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S)) +#define PCNT_CH1_POS_MODE_U6_V 0x3 +#define PCNT_CH1_POS_MODE_U6_S 26 +/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U6 0x00000003 +#define PCNT_CH1_NEG_MODE_U6_M ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S)) +#define PCNT_CH1_NEG_MODE_U6_V 0x3 +#define PCNT_CH1_NEG_MODE_U6_S 24 +/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U6 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U6_M ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S)) +#define PCNT_CH0_LCTRL_MODE_U6_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U6_S 22 +/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U6 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S)) +#define PCNT_CH0_HCTRL_MODE_U6_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U6_S 20 +/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U6 0x00000003 +#define PCNT_CH0_POS_MODE_U6_M ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S)) +#define PCNT_CH0_POS_MODE_U6_V 0x3 +#define PCNT_CH0_POS_MODE_U6_S 18 +/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U6 0x00000003 +#define PCNT_CH0_NEG_MODE_U6_M ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S)) +#define PCNT_CH0_NEG_MODE_U6_V 0x3 +#define PCNT_CH0_NEG_MODE_U6_S 16 +/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit6's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U6 (BIT(15)) +#define PCNT_THR_THRES1_EN_U6_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U6_V 0x1 +#define PCNT_THR_THRES1_EN_U6_S 15 +/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit6's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U6 (BIT(14)) +#define PCNT_THR_THRES0_EN_U6_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U6_V 0x1 +#define PCNT_THR_THRES0_EN_U6_S 14 +/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U6 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U6_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U6_V 0x1 +#define PCNT_THR_L_LIM_EN_U6_S 13 +/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U6 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U6_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U6_V 0x1 +#define PCNT_THR_H_LIM_EN_U6_S 12 +/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U6 (BIT(11)) +#define PCNT_THR_ZERO_EN_U6_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U6_V 0x1 +#define PCNT_THR_ZERO_EN_U6_S 11 +/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit6.*/ +#define PCNT_FILTER_EN_U6 (BIT(10)) +#define PCNT_FILTER_EN_U6_M (BIT(10)) +#define PCNT_FILTER_EN_U6_V 0x1 +#define PCNT_FILTER_EN_U6_S 10 +/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit6.*/ +#define PCNT_FILTER_THRES_U6 0x000003FF +#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S)) +#define PCNT_FILTER_THRES_U6_V 0x3FF +#define PCNT_FILTER_THRES_U6_S 0 + +#define PCNT_U6_CONF1_REG (DR_REG_PCNT_BASE + 0x004c) +/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit6.*/ +#define PCNT_CNT_THRES1_U6 0x0000FFFF +#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S)) +#define PCNT_CNT_THRES1_U6_V 0xFFFF +#define PCNT_CNT_THRES1_U6_S 16 +/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit6.*/ +#define PCNT_CNT_THRES0_U6 0x0000FFFF +#define PCNT_CNT_THRES0_U6_M ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S)) +#define PCNT_CNT_THRES0_U6_V 0xFFFF +#define PCNT_CNT_THRES0_U6_S 0 + +#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050) +/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit6.*/ +#define PCNT_CNT_L_LIM_U6 0x0000FFFF +#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S)) +#define PCNT_CNT_L_LIM_U6_V 0xFFFF +#define PCNT_CNT_L_LIM_U6_S 16 +/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit6.*/ +#define PCNT_CNT_H_LIM_U6 0x0000FFFF +#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S)) +#define PCNT_CNT_H_LIM_U6_V 0xFFFF +#define PCNT_CNT_H_LIM_U6_S 0 + +#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054) +/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U7 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U7_M ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S)) +#define PCNT_CH1_LCTRL_MODE_U7_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U7_S 30 +/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U7 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U7_M ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S)) +#define PCNT_CH1_HCTRL_MODE_U7_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U7_S 28 +/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U7 0x00000003 +#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S)) +#define PCNT_CH1_POS_MODE_U7_V 0x3 +#define PCNT_CH1_POS_MODE_U7_S 26 +/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U7 0x00000003 +#define PCNT_CH1_NEG_MODE_U7_M ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S)) +#define PCNT_CH1_NEG_MODE_U7_V 0x3 +#define PCNT_CH1_NEG_MODE_U7_S 24 +/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U7 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U7_M ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S)) +#define PCNT_CH0_LCTRL_MODE_U7_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U7_S 22 +/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U7 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S)) +#define PCNT_CH0_HCTRL_MODE_U7_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U7_S 20 +/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U7 0x00000003 +#define PCNT_CH0_POS_MODE_U7_M ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S)) +#define PCNT_CH0_POS_MODE_U7_V 0x3 +#define PCNT_CH0_POS_MODE_U7_S 18 +/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U7 0x00000003 +#define PCNT_CH0_NEG_MODE_U7_M ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S)) +#define PCNT_CH0_NEG_MODE_U7_V 0x3 +#define PCNT_CH0_NEG_MODE_U7_S 16 +/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit7's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U7 (BIT(15)) +#define PCNT_THR_THRES1_EN_U7_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U7_V 0x1 +#define PCNT_THR_THRES1_EN_U7_S 15 +/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit7's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U7 (BIT(14)) +#define PCNT_THR_THRES0_EN_U7_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U7_V 0x1 +#define PCNT_THR_THRES0_EN_U7_S 14 +/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U7 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U7_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U7_V 0x1 +#define PCNT_THR_L_LIM_EN_U7_S 13 +/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U7 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U7_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U7_V 0x1 +#define PCNT_THR_H_LIM_EN_U7_S 12 +/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U7 (BIT(11)) +#define PCNT_THR_ZERO_EN_U7_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U7_V 0x1 +#define PCNT_THR_ZERO_EN_U7_S 11 +/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit7.*/ +#define PCNT_FILTER_EN_U7 (BIT(10)) +#define PCNT_FILTER_EN_U7_M (BIT(10)) +#define PCNT_FILTER_EN_U7_V 0x1 +#define PCNT_FILTER_EN_U7_S 10 +/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit7.*/ +#define PCNT_FILTER_THRES_U7 0x000003FF +#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S)) +#define PCNT_FILTER_THRES_U7_V 0x3FF +#define PCNT_FILTER_THRES_U7_S 0 + +#define PCNT_U7_CONF1_REG (DR_REG_PCNT_BASE + 0x0058) +/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit7.*/ +#define PCNT_CNT_THRES1_U7 0x0000FFFF +#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S)) +#define PCNT_CNT_THRES1_U7_V 0xFFFF +#define PCNT_CNT_THRES1_U7_S 16 +/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit7.*/ +#define PCNT_CNT_THRES0_U7 0x0000FFFF +#define PCNT_CNT_THRES0_U7_M ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S)) +#define PCNT_CNT_THRES0_U7_V 0xFFFF +#define PCNT_CNT_THRES0_U7_S 0 + +#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c) +/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit7.*/ +#define PCNT_CNT_L_LIM_U7 0x0000FFFF +#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S)) +#define PCNT_CNT_L_LIM_U7_V 0xFFFF +#define PCNT_CNT_L_LIM_U7_S 16 +/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit7.*/ +#define PCNT_CNT_H_LIM_U7 0x0000FFFF +#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S)) +#define PCNT_CNT_H_LIM_U7_V 0xFFFF +#define PCNT_CNT_H_LIM_U7_S 0 + +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060) +/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit0.*/ +#define PCNT_PLUS_CNT_U0 0x0000FFFF +#define PCNT_PLUS_CNT_U0_M ((PCNT_PLUS_CNT_U0_V)<<(PCNT_PLUS_CNT_U0_S)) +#define PCNT_PLUS_CNT_U0_V 0xFFFF +#define PCNT_PLUS_CNT_U0_S 0 + +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0064) +/* PCNT_PLUS_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit1.*/ +#define PCNT_PLUS_CNT_U1 0x0000FFFF +#define PCNT_PLUS_CNT_U1_M ((PCNT_PLUS_CNT_U1_V)<<(PCNT_PLUS_CNT_U1_S)) +#define PCNT_PLUS_CNT_U1_V 0xFFFF +#define PCNT_PLUS_CNT_U1_S 0 + +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0068) +/* PCNT_PLUS_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit2.*/ +#define PCNT_PLUS_CNT_U2 0x0000FFFF +#define PCNT_PLUS_CNT_U2_M ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S)) +#define PCNT_PLUS_CNT_U2_V 0xFFFF +#define PCNT_PLUS_CNT_U2_S 0 + +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c) +/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit3.*/ +#define PCNT_PLUS_CNT_U3 0x0000FFFF +#define PCNT_PLUS_CNT_U3_M ((PCNT_PLUS_CNT_U3_V)<<(PCNT_PLUS_CNT_U3_S)) +#define PCNT_PLUS_CNT_U3_V 0xFFFF +#define PCNT_PLUS_CNT_U3_S 0 + +#define PCNT_U4_CNT_REG (DR_REG_PCNT_BASE + 0x0070) +/* PCNT_PLUS_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit4.*/ +#define PCNT_PLUS_CNT_U4 0x0000FFFF +#define PCNT_PLUS_CNT_U4_M ((PCNT_PLUS_CNT_U4_V)<<(PCNT_PLUS_CNT_U4_S)) +#define PCNT_PLUS_CNT_U4_V 0xFFFF +#define PCNT_PLUS_CNT_U4_S 0 + +#define PCNT_U5_CNT_REG (DR_REG_PCNT_BASE + 0x0074) +/* PCNT_PLUS_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit5.*/ +#define PCNT_PLUS_CNT_U5 0x0000FFFF +#define PCNT_PLUS_CNT_U5_M ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S)) +#define PCNT_PLUS_CNT_U5_V 0xFFFF +#define PCNT_PLUS_CNT_U5_S 0 + +#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078) +/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit6.*/ +#define PCNT_PLUS_CNT_U6 0x0000FFFF +#define PCNT_PLUS_CNT_U6_M ((PCNT_PLUS_CNT_U6_V)<<(PCNT_PLUS_CNT_U6_S)) +#define PCNT_PLUS_CNT_U6_V 0xFFFF +#define PCNT_PLUS_CNT_U6_S 0 + +#define PCNT_U7_CNT_REG (DR_REG_PCNT_BASE + 0x007c) +/* PCNT_PLUS_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit7.*/ +#define PCNT_PLUS_CNT_U7 0x0000FFFF +#define PCNT_PLUS_CNT_U7_M ((PCNT_PLUS_CNT_U7_V)<<(PCNT_PLUS_CNT_U7_S)) +#define PCNT_PLUS_CNT_U7_V 0xFFFF +#define PCNT_PLUS_CNT_U7_S 0 + +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0080) +/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_RAW (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_RAW (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_RAW (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 + +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0084) +/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_ST (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ST_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_ST_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_ST (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ST_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_ST_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_ST (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ST_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_ST_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 + +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0088) +/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_ENA (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_ENA (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_ENA (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 + +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x008c) +/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel7 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel6 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_CLR (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel5 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_CLR (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel4 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_CLR (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel3 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel2 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel1 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel0 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 + +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0090) +/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U0 0xFFFFFFFF +#define PCNT_CORE_STATUS_U0_M ((PCNT_CORE_STATUS_U0_V)<<(PCNT_CORE_STATUS_U0_S)) +#define PCNT_CORE_STATUS_U0_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U0_S 0 +/*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/ +#define PCNT_STATUS_CNT_MODE 0x3 +#define PCNT_STATUS_CNT_MODE_M ((PCNT_STATUS_CNT_MODE_V)<<(PCNT_STATUS_CNT_MODE_S)) +#define PCNT_STATUS_CNT_MODE_V 0x3 +#define PCNT_STATUS_CNT_MODE_S 0 +/* counter value equals to thresh1*/ +#define PCNT_STATUS_THRES1 BIT(2) +#define PCNT_STATUS_THRES1_M BIT(2) +#define PCNT_STATUS_THRES1_V 0x1 +#define PCNT_STATUS_THRES1_S 2 +/* counter value equals to thresh0*/ +#define PCNT_STATUS_THRES0 BIT(3) +#define PCNT_STATUS_THRES0_M BIT(3) +#define PCNT_STATUS_THRES0_V 0x1 +#define PCNT_STATUS_THRES0_S 3 +/* counter value reaches h_lim*/ +#define PCNT_STATUS_L_LIM BIT(4) +#define PCNT_STATUS_L_LIM_M BIT(4) +#define PCNT_STATUS_L_LIM_V 0x1 +#define PCNT_STATUS_L_LIM_S 4 +/* counter value reaches l_lim*/ +#define PCNT_STATUS_H_LIM BIT(5) +#define PCNT_STATUS_H_LIM_M BIT(5) +#define PCNT_STATUS_H_LIM_V 0x1 +#define PCNT_STATUS_H_LIM_S 5 +/* counter value equals to zero*/ +#define PCNT_STATUS_ZERO BIT(6) +#define PCNT_STATUS_ZERO_M BIT(6) +#define PCNT_STATUS_ZERO_V 0x1 +#define PCNT_STATUS_ZERO_S 6 + +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0094) +/* PCNT_CORE_STATUS_U1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U1 0xFFFFFFFF +#define PCNT_CORE_STATUS_U1_M ((PCNT_CORE_STATUS_U1_V)<<(PCNT_CORE_STATUS_U1_S)) +#define PCNT_CORE_STATUS_U1_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U1_S 0 + +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0098) +/* PCNT_CORE_STATUS_U2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U2 0xFFFFFFFF +#define PCNT_CORE_STATUS_U2_M ((PCNT_CORE_STATUS_U2_V)<<(PCNT_CORE_STATUS_U2_S)) +#define PCNT_CORE_STATUS_U2_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U2_S 0 + +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x009c) +/* PCNT_CORE_STATUS_U3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U3 0xFFFFFFFF +#define PCNT_CORE_STATUS_U3_M ((PCNT_CORE_STATUS_U3_V)<<(PCNT_CORE_STATUS_U3_S)) +#define PCNT_CORE_STATUS_U3_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U3_S 0 + +#define PCNT_U4_STATUS_REG (DR_REG_PCNT_BASE + 0x00a0) +/* PCNT_CORE_STATUS_U4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U4 0xFFFFFFFF +#define PCNT_CORE_STATUS_U4_M ((PCNT_CORE_STATUS_U4_V)<<(PCNT_CORE_STATUS_U4_S)) +#define PCNT_CORE_STATUS_U4_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U4_S 0 + +#define PCNT_U5_STATUS_REG (DR_REG_PCNT_BASE + 0x00a4) +/* PCNT_CORE_STATUS_U5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U5 0xFFFFFFFF +#define PCNT_CORE_STATUS_U5_M ((PCNT_CORE_STATUS_U5_V)<<(PCNT_CORE_STATUS_U5_S)) +#define PCNT_CORE_STATUS_U5_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U5_S 0 + +#define PCNT_U6_STATUS_REG (DR_REG_PCNT_BASE + 0x00a8) +/* PCNT_CORE_STATUS_U6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U6 0xFFFFFFFF +#define PCNT_CORE_STATUS_U6_M ((PCNT_CORE_STATUS_U6_V)<<(PCNT_CORE_STATUS_U6_S)) +#define PCNT_CORE_STATUS_U6_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U6_S 0 + +#define PCNT_U7_STATUS_REG (DR_REG_PCNT_BASE + 0x00ac) +/* PCNT_CORE_STATUS_U7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U7 0xFFFFFFFF +#define PCNT_CORE_STATUS_U7_M ((PCNT_CORE_STATUS_U7_V)<<(PCNT_CORE_STATUS_U7_S)) +#define PCNT_CORE_STATUS_U7_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U7_S 0 + +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x00b0) +/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (BIT(16)) +#define PCNT_CLK_EN_V 0x1 +#define PCNT_CLK_EN_S 16 +/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit7's counter.*/ +#define PCNT_CNT_PAUSE_U7 (BIT(15)) +#define PCNT_CNT_PAUSE_U7_M (BIT(15)) +#define PCNT_CNT_PAUSE_U7_V 0x1 +#define PCNT_CNT_PAUSE_U7_S 15 +/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit7's counter.*/ +#define PCNT_PLUS_CNT_RST_U7 (BIT(14)) +#define PCNT_PLUS_CNT_RST_U7_M (BIT(14)) +#define PCNT_PLUS_CNT_RST_U7_V 0x1 +#define PCNT_PLUS_CNT_RST_U7_S 14 +/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit6's counter.*/ +#define PCNT_CNT_PAUSE_U6 (BIT(13)) +#define PCNT_CNT_PAUSE_U6_M (BIT(13)) +#define PCNT_CNT_PAUSE_U6_V 0x1 +#define PCNT_CNT_PAUSE_U6_S 13 +/* PCNT_PLUS_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit6's counter.*/ +#define PCNT_PLUS_CNT_RST_U6 (BIT(12)) +#define PCNT_PLUS_CNT_RST_U6_M (BIT(12)) +#define PCNT_PLUS_CNT_RST_U6_V 0x1 +#define PCNT_PLUS_CNT_RST_U6_S 12 +/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit5's counter.*/ +#define PCNT_CNT_PAUSE_U5 (BIT(11)) +#define PCNT_CNT_PAUSE_U5_M (BIT(11)) +#define PCNT_CNT_PAUSE_U5_V 0x1 +#define PCNT_CNT_PAUSE_U5_S 11 +/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit5's counter.*/ +#define PCNT_PLUS_CNT_RST_U5 (BIT(10)) +#define PCNT_PLUS_CNT_RST_U5_M (BIT(10)) +#define PCNT_PLUS_CNT_RST_U5_V 0x1 +#define PCNT_PLUS_CNT_RST_U5_S 10 +/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit4's counter.*/ +#define PCNT_CNT_PAUSE_U4 (BIT(9)) +#define PCNT_CNT_PAUSE_U4_M (BIT(9)) +#define PCNT_CNT_PAUSE_U4_V 0x1 +#define PCNT_CNT_PAUSE_U4_S 9 +/* PCNT_PLUS_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit4's counter.*/ +#define PCNT_PLUS_CNT_RST_U4 (BIT(8)) +#define PCNT_PLUS_CNT_RST_U4_M (BIT(8)) +#define PCNT_PLUS_CNT_RST_U4_V 0x1 +#define PCNT_PLUS_CNT_RST_U4_S 8 +/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit3's counter.*/ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (BIT(7)) +#define PCNT_CNT_PAUSE_U3_V 0x1 +#define PCNT_CNT_PAUSE_U3_S 7 +/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit3's counter.*/ +#define PCNT_PLUS_CNT_RST_U3 (BIT(6)) +#define PCNT_PLUS_CNT_RST_U3_M (BIT(6)) +#define PCNT_PLUS_CNT_RST_U3_V 0x1 +#define PCNT_PLUS_CNT_RST_U3_S 6 +/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit2's counter.*/ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (BIT(5)) +#define PCNT_CNT_PAUSE_U2_V 0x1 +#define PCNT_CNT_PAUSE_U2_S 5 +/* PCNT_PLUS_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit2's counter.*/ +#define PCNT_PLUS_CNT_RST_U2 (BIT(4)) +#define PCNT_PLUS_CNT_RST_U2_M (BIT(4)) +#define PCNT_PLUS_CNT_RST_U2_V 0x1 +#define PCNT_PLUS_CNT_RST_U2_S 4 +/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit1's counter.*/ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (BIT(3)) +#define PCNT_CNT_PAUSE_U1_V 0x1 +#define PCNT_CNT_PAUSE_U1_S 3 +/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit1's counter.*/ +#define PCNT_PLUS_CNT_RST_U1 (BIT(2)) +#define PCNT_PLUS_CNT_RST_U1_M (BIT(2)) +#define PCNT_PLUS_CNT_RST_U1_V 0x1 +#define PCNT_PLUS_CNT_RST_U1_S 2 +/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit0's counter.*/ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (BIT(1)) +#define PCNT_CNT_PAUSE_U0_V 0x1 +#define PCNT_CNT_PAUSE_U0_S 1 +/* PCNT_PLUS_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit0's counter.*/ +#define PCNT_PLUS_CNT_RST_U0 (BIT(0)) +#define PCNT_PLUS_CNT_RST_U0_M (BIT(0)) +#define PCNT_PLUS_CNT_RST_U0_V 0x1 +#define PCNT_PLUS_CNT_RST_U0_S 0 + +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc) +/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */ +/*description: */ +#define PCNT_DATE 0xFFFFFFFF +#define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S)) +#define PCNT_DATE_V 0xFFFFFFFF +#define PCNT_DATE_S 0 + + + + +#endif /*_SOC_PCNT_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/pcnt_struct.h b/tools/sdk/include/soc/soc/pcnt_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/pcnt_struct.h rename to tools/sdk/include/soc/soc/pcnt_struct.h diff --git a/tools/sdk/include/esp32/soc/pid.h b/tools/sdk/include/soc/soc/pid.h similarity index 100% rename from tools/sdk/include/esp32/soc/pid.h rename to tools/sdk/include/soc/soc/pid.h diff --git a/tools/sdk/include/esp32/soc/rmt_reg.h b/tools/sdk/include/soc/soc/rmt_reg.h similarity index 97% rename from tools/sdk/include/esp32/soc/rmt_reg.h rename to tools/sdk/include/soc/soc/rmt_reg.h index 07ba24ac..59756fa2 100644 --- a/tools/sdk/include/esp32/soc/rmt_reg.h +++ b/tools/sdk/include/soc/soc/rmt_reg.h @@ -1,2172 +1,2172 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RMT_REG_H_ -#define _SOC_RMT_REG_H_ - -#include "soc.h" -#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) - -#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) - -#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) - -#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) - -#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010) - -#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014) - -#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018) - -#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c) - -#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020) -/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: This bit is used to control clock.when software config RMT - internal registers it controls the register clock.*/ -#define RMT_CLK_EN (BIT(31)) -#define RMT_CLK_EN_M (BIT(31)) -#define RMT_CLK_EN_V 0x1 -#define RMT_CLK_EN_S 31 -/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/ -#define RMT_MEM_PD (BIT(30)) -#define RMT_MEM_PD_M (BIT(30)) -#define RMT_MEM_PD_V 0x1 -#define RMT_MEM_PD_S 30 -/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure the way carrier wave is modulated - for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ -#define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH0_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH0_V 0x1 -#define RMT_CARRIER_OUT_LV_CH0_S 29 -/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel0.*/ -#define RMT_CARRIER_EN_CH0 (BIT(28)) -#define RMT_CARRIER_EN_CH0_M (BIT(28)) -#define RMT_CARRIER_EN_CH0_V 0x1 -#define RMT_CARRIER_EN_CH0_S 28 -/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel0.*/ -#define RMT_MEM_SIZE_CH0 0x0000000F -#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) -#define RMT_MEM_SIZE_CH0_V 0xF -#define RMT_MEM_SIZE_CH0_S 24 -/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when no edge is detected on the input signal - for longer than reg_idle_thres_ch0 then the receive process is done.*/ -#define RMT_IDLE_THRES_CH0 0x0000FFFF -#define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S)) -#define RMT_IDLE_THRES_CH0_V 0xFFFF -#define RMT_IDLE_THRES_CH0_S 8 -/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel0.*/ -#define RMT_DIV_CNT_CH0 0x000000FF -#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) -#define RMT_DIV_CNT_CH0_V 0xFF -#define RMT_DIV_CNT_CH0_S 0 - -#define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x0024) -/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel0 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH0 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH0_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH0_V 0x1 -#define RMT_IDLE_OUT_EN_CH0_S 19 -/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel0 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH0 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH0_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH0_V 0x1 -#define RMT_IDLE_OUT_LV_CH0_S 18 -/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH0_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH0_V 0x1 -#define RMT_REF_ALWAYS_ON_CH0_S 17 -/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel0.*/ -#define RMT_REF_CNT_RST_CH0 (BIT(16)) -#define RMT_REF_CNT_RST_CH0_M (BIT(16)) -#define RMT_REF_CNT_RST_CH0_V 0x1 -#define RMT_REF_CNT_RST_CH0_S 16 -/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel0 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH0 0x000000FF -#define RMT_RX_FILTER_THRES_CH0_M ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S)) -#define RMT_RX_FILTER_THRES_CH0_V 0xFF -#define RMT_RX_FILTER_THRES_CH0_S 8 -/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel0.*/ -#define RMT_RX_FILTER_EN_CH0 (BIT(7)) -#define RMT_RX_FILTER_EN_CH0_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH0_V 0x1 -#define RMT_RX_FILTER_EN_CH0_S 7 -/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel0 again and again.*/ -#define RMT_TX_CONTI_MODE_CH0 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH0_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH0_V 0x1 -#define RMT_TX_CONTI_MODE_CH0_S 6 -/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel0's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH0 (BIT(5)) -#define RMT_MEM_OWNER_CH0_M (BIT(5)) -#define RMT_MEM_OWNER_CH0_V 0x1 -#define RMT_MEM_OWNER_CH0_S 5 -/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH0 (BIT(4)) -#define RMT_APB_MEM_RST_CH0_M (BIT(4)) -#define RMT_APB_MEM_RST_CH0_V 0x1 -#define RMT_APB_MEM_RST_CH0_S 4 -/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH0 (BIT(3)) -#define RMT_MEM_RD_RST_CH0_M (BIT(3)) -#define RMT_MEM_RD_RST_CH0_V 0x1 -#define RMT_MEM_RD_RST_CH0_S 3 -/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel0 by receiver access.*/ -#define RMT_MEM_WR_RST_CH0 (BIT(2)) -#define RMT_MEM_WR_RST_CH0_M (BIT(2)) -#define RMT_MEM_WR_RST_CH0_V 0x1 -#define RMT_MEM_WR_RST_CH0_S 2 -/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel0.*/ -#define RMT_RX_EN_CH0 (BIT(1)) -#define RMT_RX_EN_CH0_M (BIT(1)) -#define RMT_RX_EN_CH0_V 0x1 -#define RMT_RX_EN_CH0_S 1 -/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel0.*/ -#define RMT_TX_START_CH0 (BIT(0)) -#define RMT_TX_START_CH0_M (BIT(0)) -#define RMT_TX_START_CH0_V 0x1 -#define RMT_TX_START_CH0_S 0 - -#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0028) -/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure the way carrier wave is modulated - for channel1.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ -#define RMT_CARRIER_OUT_LV_CH1 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH1_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH1_V 0x1 -#define RMT_CARRIER_OUT_LV_CH1_S 29 -/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel1.*/ -#define RMT_CARRIER_EN_CH1 (BIT(28)) -#define RMT_CARRIER_EN_CH1_M (BIT(28)) -#define RMT_CARRIER_EN_CH1_V 0x1 -#define RMT_CARRIER_EN_CH1_S 28 -/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel1.*/ -#define RMT_MEM_SIZE_CH1 0x0000000F -#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) -#define RMT_MEM_SIZE_CH1_V 0xF -#define RMT_MEM_SIZE_CH1_S 24 -/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel1.*/ -#define RMT_IDLE_THRES_CH1 0x0000FFFF -#define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S)) -#define RMT_IDLE_THRES_CH1_V 0xFFFF -#define RMT_IDLE_THRES_CH1_S 8 -/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel1.*/ -#define RMT_DIV_CNT_CH1 0x000000FF -#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) -#define RMT_DIV_CNT_CH1_V 0xFF -#define RMT_DIV_CNT_CH1_S 0 - -#define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x002c) -/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel1 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH1 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH1_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH1_V 0x1 -#define RMT_IDLE_OUT_EN_CH1_S 19 -/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel1 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH1 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH1_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH1_V 0x1 -#define RMT_IDLE_OUT_LV_CH1_S 18 -/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH1 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH1_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH1_V 0x1 -#define RMT_REF_ALWAYS_ON_CH1_S 17 -/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel1.*/ -#define RMT_REF_CNT_RST_CH1 (BIT(16)) -#define RMT_REF_CNT_RST_CH1_M (BIT(16)) -#define RMT_REF_CNT_RST_CH1_V 0x1 -#define RMT_REF_CNT_RST_CH1_S 16 -/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel1 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH1 0x000000FF -#define RMT_RX_FILTER_THRES_CH1_M ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S)) -#define RMT_RX_FILTER_THRES_CH1_V 0xFF -#define RMT_RX_FILTER_THRES_CH1_S 8 -/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel1.*/ -#define RMT_RX_FILTER_EN_CH1 (BIT(7)) -#define RMT_RX_FILTER_EN_CH1_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH1_V 0x1 -#define RMT_RX_FILTER_EN_CH1_S 7 -/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel1 again and again.*/ -#define RMT_TX_CONTI_MODE_CH1 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH1_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH1_V 0x1 -#define RMT_TX_CONTI_MODE_CH1_S 6 -/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel1's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH1 (BIT(5)) -#define RMT_MEM_OWNER_CH1_M (BIT(5)) -#define RMT_MEM_OWNER_CH1_V 0x1 -#define RMT_MEM_OWNER_CH1_S 5 -/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH1 (BIT(4)) -#define RMT_APB_MEM_RST_CH1_M (BIT(4)) -#define RMT_APB_MEM_RST_CH1_V 0x1 -#define RMT_APB_MEM_RST_CH1_S 4 -/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH1 (BIT(3)) -#define RMT_MEM_RD_RST_CH1_M (BIT(3)) -#define RMT_MEM_RD_RST_CH1_V 0x1 -#define RMT_MEM_RD_RST_CH1_S 3 -/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel1 by receiver access.*/ -#define RMT_MEM_WR_RST_CH1 (BIT(2)) -#define RMT_MEM_WR_RST_CH1_M (BIT(2)) -#define RMT_MEM_WR_RST_CH1_V 0x1 -#define RMT_MEM_WR_RST_CH1_S 2 -/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel1.*/ -#define RMT_RX_EN_CH1 (BIT(1)) -#define RMT_RX_EN_CH1_M (BIT(1)) -#define RMT_RX_EN_CH1_V 0x1 -#define RMT_RX_EN_CH1_S 1 -/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel1.*/ -#define RMT_TX_START_CH1 (BIT(0)) -#define RMT_TX_START_CH1_M (BIT(0)) -#define RMT_TX_START_CH1_V 0x1 -#define RMT_TX_START_CH1_S 0 - -#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0030) -/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH2_V 0x1 -#define RMT_CARRIER_OUT_LV_CH2_S 29 -/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel2.*/ -#define RMT_CARRIER_EN_CH2 (BIT(28)) -#define RMT_CARRIER_EN_CH2_M (BIT(28)) -#define RMT_CARRIER_EN_CH2_V 0x1 -#define RMT_CARRIER_EN_CH2_S 28 -/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel2.*/ -#define RMT_MEM_SIZE_CH2 0x0000000F -#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) -#define RMT_MEM_SIZE_CH2_V 0xF -#define RMT_MEM_SIZE_CH2_S 24 -/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH2 0x0000FFFF -#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S)) -#define RMT_IDLE_THRES_CH2_V 0xFFFF -#define RMT_IDLE_THRES_CH2_S 8 -/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel2.*/ -#define RMT_DIV_CNT_CH2 0x000000FF -#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) -#define RMT_DIV_CNT_CH2_V 0xFF -#define RMT_DIV_CNT_CH2_S 0 - -#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x0034) -/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel2 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH2 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH2_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH2_V 0x1 -#define RMT_IDLE_OUT_EN_CH2_S 19 -/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel2 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH2 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH2_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH2_V 0x1 -#define RMT_IDLE_OUT_LV_CH2_S 18 -/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH2 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH2_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH2_V 0x1 -#define RMT_REF_ALWAYS_ON_CH2_S 17 -/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel2.*/ -#define RMT_REF_CNT_RST_CH2 (BIT(16)) -#define RMT_REF_CNT_RST_CH2_M (BIT(16)) -#define RMT_REF_CNT_RST_CH2_V 0x1 -#define RMT_REF_CNT_RST_CH2_S 16 -/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel2 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH2 0x000000FF -#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S)) -#define RMT_RX_FILTER_THRES_CH2_V 0xFF -#define RMT_RX_FILTER_THRES_CH2_S 8 -/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel2.*/ -#define RMT_RX_FILTER_EN_CH2 (BIT(7)) -#define RMT_RX_FILTER_EN_CH2_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH2_V 0x1 -#define RMT_RX_FILTER_EN_CH2_S 7 -/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel2.*/ -#define RMT_TX_CONTI_MODE_CH2 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH2_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH2_V 0x1 -#define RMT_TX_CONTI_MODE_CH2_S 6 -/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel2's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH2 (BIT(5)) -#define RMT_MEM_OWNER_CH2_M (BIT(5)) -#define RMT_MEM_OWNER_CH2_V 0x1 -#define RMT_MEM_OWNER_CH2_S 5 -/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH2 (BIT(4)) -#define RMT_APB_MEM_RST_CH2_M (BIT(4)) -#define RMT_APB_MEM_RST_CH2_V 0x1 -#define RMT_APB_MEM_RST_CH2_S 4 -/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH2 (BIT(3)) -#define RMT_MEM_RD_RST_CH2_M (BIT(3)) -#define RMT_MEM_RD_RST_CH2_V 0x1 -#define RMT_MEM_RD_RST_CH2_S 3 -/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel2 by receiver access.*/ -#define RMT_MEM_WR_RST_CH2 (BIT(2)) -#define RMT_MEM_WR_RST_CH2_M (BIT(2)) -#define RMT_MEM_WR_RST_CH2_V 0x1 -#define RMT_MEM_WR_RST_CH2_S 2 -/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel2.*/ -#define RMT_RX_EN_CH2 (BIT(1)) -#define RMT_RX_EN_CH2_M (BIT(1)) -#define RMT_RX_EN_CH2_V 0x1 -#define RMT_RX_EN_CH2_S 1 -/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel2.*/ -#define RMT_TX_START_CH2 (BIT(0)) -#define RMT_TX_START_CH2_M (BIT(0)) -#define RMT_TX_START_CH2_V 0x1 -#define RMT_TX_START_CH2_S 0 - -#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0038) -/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH3_V 0x1 -#define RMT_CARRIER_OUT_LV_CH3_S 29 -/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel3.*/ -#define RMT_CARRIER_EN_CH3 (BIT(28)) -#define RMT_CARRIER_EN_CH3_M (BIT(28)) -#define RMT_CARRIER_EN_CH3_V 0x1 -#define RMT_CARRIER_EN_CH3_S 28 -/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel3.*/ -#define RMT_MEM_SIZE_CH3 0x0000000F -#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) -#define RMT_MEM_SIZE_CH3_V 0xF -#define RMT_MEM_SIZE_CH3_S 24 -/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH3 0x0000FFFF -#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S)) -#define RMT_IDLE_THRES_CH3_V 0xFFFF -#define RMT_IDLE_THRES_CH3_S 8 -/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel3.*/ -#define RMT_DIV_CNT_CH3 0x000000FF -#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) -#define RMT_DIV_CNT_CH3_V 0xFF -#define RMT_DIV_CNT_CH3_S 0 - -#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x003c) -/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel3 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH3 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH3_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH3_V 0x1 -#define RMT_IDLE_OUT_EN_CH3_S 19 -/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel3 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH3 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH3_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH3_V 0x1 -#define RMT_IDLE_OUT_LV_CH3_S 18 -/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH3 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH3_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH3_V 0x1 -#define RMT_REF_ALWAYS_ON_CH3_S 17 -/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel3.*/ -#define RMT_REF_CNT_RST_CH3 (BIT(16)) -#define RMT_REF_CNT_RST_CH3_M (BIT(16)) -#define RMT_REF_CNT_RST_CH3_V 0x1 -#define RMT_REF_CNT_RST_CH3_S 16 -/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel3 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH3 0x000000FF -#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S)) -#define RMT_RX_FILTER_THRES_CH3_V 0xFF -#define RMT_RX_FILTER_THRES_CH3_S 8 -/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel3.*/ -#define RMT_RX_FILTER_EN_CH3 (BIT(7)) -#define RMT_RX_FILTER_EN_CH3_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH3_V 0x1 -#define RMT_RX_FILTER_EN_CH3_S 7 -/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel3.*/ -#define RMT_TX_CONTI_MODE_CH3 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH3_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH3_V 0x1 -#define RMT_TX_CONTI_MODE_CH3_S 6 -/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel3's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH3 (BIT(5)) -#define RMT_MEM_OWNER_CH3_M (BIT(5)) -#define RMT_MEM_OWNER_CH3_V 0x1 -#define RMT_MEM_OWNER_CH3_S 5 -/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH3 (BIT(4)) -#define RMT_APB_MEM_RST_CH3_M (BIT(4)) -#define RMT_APB_MEM_RST_CH3_V 0x1 -#define RMT_APB_MEM_RST_CH3_S 4 -/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH3 (BIT(3)) -#define RMT_MEM_RD_RST_CH3_M (BIT(3)) -#define RMT_MEM_RD_RST_CH3_V 0x1 -#define RMT_MEM_RD_RST_CH3_S 3 -/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel3 by receiver access.*/ -#define RMT_MEM_WR_RST_CH3 (BIT(2)) -#define RMT_MEM_WR_RST_CH3_M (BIT(2)) -#define RMT_MEM_WR_RST_CH3_V 0x1 -#define RMT_MEM_WR_RST_CH3_S 2 -/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel3.*/ -#define RMT_RX_EN_CH3 (BIT(1)) -#define RMT_RX_EN_CH3_M (BIT(1)) -#define RMT_RX_EN_CH3_V 0x1 -#define RMT_RX_EN_CH3_S 1 -/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel3.*/ -#define RMT_TX_START_CH3 (BIT(0)) -#define RMT_TX_START_CH3_M (BIT(0)) -#define RMT_TX_START_CH3_V 0x1 -#define RMT_TX_START_CH3_S 0 - -#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0040) -/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH4_V 0x1 -#define RMT_CARRIER_OUT_LV_CH4_S 29 -/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel4.*/ -#define RMT_CARRIER_EN_CH4 (BIT(28)) -#define RMT_CARRIER_EN_CH4_M (BIT(28)) -#define RMT_CARRIER_EN_CH4_V 0x1 -#define RMT_CARRIER_EN_CH4_S 28 -/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel4.*/ -#define RMT_MEM_SIZE_CH4 0x0000000F -#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S)) -#define RMT_MEM_SIZE_CH4_V 0xF -#define RMT_MEM_SIZE_CH4_S 24 -/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH4 0x0000FFFF -#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S)) -#define RMT_IDLE_THRES_CH4_V 0xFFFF -#define RMT_IDLE_THRES_CH4_S 8 -/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel4.*/ -#define RMT_DIV_CNT_CH4 0x000000FF -#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S)) -#define RMT_DIV_CNT_CH4_V 0xFF -#define RMT_DIV_CNT_CH4_S 0 - -#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0044) -/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel4 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH4 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH4_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH4_V 0x1 -#define RMT_IDLE_OUT_EN_CH4_S 19 -/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel4 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH4 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH4_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH4_V 0x1 -#define RMT_IDLE_OUT_LV_CH4_S 18 -/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH4 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH4_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH4_V 0x1 -#define RMT_REF_ALWAYS_ON_CH4_S 17 -/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel4.*/ -#define RMT_REF_CNT_RST_CH4 (BIT(16)) -#define RMT_REF_CNT_RST_CH4_M (BIT(16)) -#define RMT_REF_CNT_RST_CH4_V 0x1 -#define RMT_REF_CNT_RST_CH4_S 16 -/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel4 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH4 0x000000FF -#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S)) -#define RMT_RX_FILTER_THRES_CH4_V 0xFF -#define RMT_RX_FILTER_THRES_CH4_S 8 -/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel4.*/ -#define RMT_RX_FILTER_EN_CH4 (BIT(7)) -#define RMT_RX_FILTER_EN_CH4_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH4_V 0x1 -#define RMT_RX_FILTER_EN_CH4_S 7 -/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel4.*/ -#define RMT_TX_CONTI_MODE_CH4 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH4_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH4_V 0x1 -#define RMT_TX_CONTI_MODE_CH4_S 6 -/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel4's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH4 (BIT(5)) -#define RMT_MEM_OWNER_CH4_M (BIT(5)) -#define RMT_MEM_OWNER_CH4_V 0x1 -#define RMT_MEM_OWNER_CH4_S 5 -/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH4 (BIT(4)) -#define RMT_APB_MEM_RST_CH4_M (BIT(4)) -#define RMT_APB_MEM_RST_CH4_V 0x1 -#define RMT_APB_MEM_RST_CH4_S 4 -/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH4 (BIT(3)) -#define RMT_MEM_RD_RST_CH4_M (BIT(3)) -#define RMT_MEM_RD_RST_CH4_V 0x1 -#define RMT_MEM_RD_RST_CH4_S 3 -/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel4 by receiver access.*/ -#define RMT_MEM_WR_RST_CH4 (BIT(2)) -#define RMT_MEM_WR_RST_CH4_M (BIT(2)) -#define RMT_MEM_WR_RST_CH4_V 0x1 -#define RMT_MEM_WR_RST_CH4_S 2 -/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel4.*/ -#define RMT_RX_EN_CH4 (BIT(1)) -#define RMT_RX_EN_CH4_M (BIT(1)) -#define RMT_RX_EN_CH4_V 0x1 -#define RMT_RX_EN_CH4_S 1 -/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel4.*/ -#define RMT_TX_START_CH4 (BIT(0)) -#define RMT_TX_START_CH4_M (BIT(0)) -#define RMT_TX_START_CH4_V 0x1 -#define RMT_TX_START_CH4_S 0 - -#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0048) -/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH5_V 0x1 -#define RMT_CARRIER_OUT_LV_CH5_S 29 -/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel5.*/ -#define RMT_CARRIER_EN_CH5 (BIT(28)) -#define RMT_CARRIER_EN_CH5_M (BIT(28)) -#define RMT_CARRIER_EN_CH5_V 0x1 -#define RMT_CARRIER_EN_CH5_S 28 -/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel5.*/ -#define RMT_MEM_SIZE_CH5 0x0000000F -#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S)) -#define RMT_MEM_SIZE_CH5_V 0xF -#define RMT_MEM_SIZE_CH5_S 24 -/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH5 0x0000FFFF -#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S)) -#define RMT_IDLE_THRES_CH5_V 0xFFFF -#define RMT_IDLE_THRES_CH5_S 8 -/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel5.*/ -#define RMT_DIV_CNT_CH5 0x000000FF -#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S)) -#define RMT_DIV_CNT_CH5_V 0xFF -#define RMT_DIV_CNT_CH5_S 0 - -#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x004c) -/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel5 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH5 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH5_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH5_V 0x1 -#define RMT_IDLE_OUT_EN_CH5_S 19 -/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel5 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH5 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH5_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH5_V 0x1 -#define RMT_IDLE_OUT_LV_CH5_S 18 -/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH5 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH5_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH5_V 0x1 -#define RMT_REF_ALWAYS_ON_CH5_S 17 -/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel5.*/ -#define RMT_REF_CNT_RST_CH5 (BIT(16)) -#define RMT_REF_CNT_RST_CH5_M (BIT(16)) -#define RMT_REF_CNT_RST_CH5_V 0x1 -#define RMT_REF_CNT_RST_CH5_S 16 -/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel5 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH5 0x000000FF -#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S)) -#define RMT_RX_FILTER_THRES_CH5_V 0xFF -#define RMT_RX_FILTER_THRES_CH5_S 8 -/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel5.*/ -#define RMT_RX_FILTER_EN_CH5 (BIT(7)) -#define RMT_RX_FILTER_EN_CH5_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH5_V 0x1 -#define RMT_RX_FILTER_EN_CH5_S 7 -/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel5.*/ -#define RMT_TX_CONTI_MODE_CH5 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH5_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH5_V 0x1 -#define RMT_TX_CONTI_MODE_CH5_S 6 -/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel5's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH5 (BIT(5)) -#define RMT_MEM_OWNER_CH5_M (BIT(5)) -#define RMT_MEM_OWNER_CH5_V 0x1 -#define RMT_MEM_OWNER_CH5_S 5 -/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH5 (BIT(4)) -#define RMT_APB_MEM_RST_CH5_M (BIT(4)) -#define RMT_APB_MEM_RST_CH5_V 0x1 -#define RMT_APB_MEM_RST_CH5_S 4 -/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH5 (BIT(3)) -#define RMT_MEM_RD_RST_CH5_M (BIT(3)) -#define RMT_MEM_RD_RST_CH5_V 0x1 -#define RMT_MEM_RD_RST_CH5_S 3 -/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel5 by receiver access.*/ -#define RMT_MEM_WR_RST_CH5 (BIT(2)) -#define RMT_MEM_WR_RST_CH5_M (BIT(2)) -#define RMT_MEM_WR_RST_CH5_V 0x1 -#define RMT_MEM_WR_RST_CH5_S 2 -/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel5.*/ -#define RMT_RX_EN_CH5 (BIT(1)) -#define RMT_RX_EN_CH5_M (BIT(1)) -#define RMT_RX_EN_CH5_V 0x1 -#define RMT_RX_EN_CH5_S 1 -/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel5.*/ -#define RMT_TX_START_CH5 (BIT(0)) -#define RMT_TX_START_CH5_M (BIT(0)) -#define RMT_TX_START_CH5_V 0x1 -#define RMT_TX_START_CH5_S 0 - -#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0050) -/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH6_V 0x1 -#define RMT_CARRIER_OUT_LV_CH6_S 29 -/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel6.*/ -#define RMT_CARRIER_EN_CH6 (BIT(28)) -#define RMT_CARRIER_EN_CH6_M (BIT(28)) -#define RMT_CARRIER_EN_CH6_V 0x1 -#define RMT_CARRIER_EN_CH6_S 28 -/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel6.*/ -#define RMT_MEM_SIZE_CH6 0x0000000F -#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S)) -#define RMT_MEM_SIZE_CH6_V 0xF -#define RMT_MEM_SIZE_CH6_S 24 -/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH6 0x0000FFFF -#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S)) -#define RMT_IDLE_THRES_CH6_V 0xFFFF -#define RMT_IDLE_THRES_CH6_S 8 -/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel6.*/ -#define RMT_DIV_CNT_CH6 0x000000FF -#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S)) -#define RMT_DIV_CNT_CH6_V 0xFF -#define RMT_DIV_CNT_CH6_S 0 - -#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0054) -/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel6 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH6 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH6_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH6_V 0x1 -#define RMT_IDLE_OUT_EN_CH6_S 19 -/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel6 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH6 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH6_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH6_V 0x1 -#define RMT_IDLE_OUT_LV_CH6_S 18 -/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH6 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH6_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH6_V 0x1 -#define RMT_REF_ALWAYS_ON_CH6_S 17 -/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel6.*/ -#define RMT_REF_CNT_RST_CH6 (BIT(16)) -#define RMT_REF_CNT_RST_CH6_M (BIT(16)) -#define RMT_REF_CNT_RST_CH6_V 0x1 -#define RMT_REF_CNT_RST_CH6_S 16 -/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel6 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH6 0x000000FF -#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S)) -#define RMT_RX_FILTER_THRES_CH6_V 0xFF -#define RMT_RX_FILTER_THRES_CH6_S 8 -/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel6.*/ -#define RMT_RX_FILTER_EN_CH6 (BIT(7)) -#define RMT_RX_FILTER_EN_CH6_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH6_V 0x1 -#define RMT_RX_FILTER_EN_CH6_S 7 -/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel6.*/ -#define RMT_TX_CONTI_MODE_CH6 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH6_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH6_V 0x1 -#define RMT_TX_CONTI_MODE_CH6_S 6 -/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel6's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH6 (BIT(5)) -#define RMT_MEM_OWNER_CH6_M (BIT(5)) -#define RMT_MEM_OWNER_CH6_V 0x1 -#define RMT_MEM_OWNER_CH6_S 5 -/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH6 (BIT(4)) -#define RMT_APB_MEM_RST_CH6_M (BIT(4)) -#define RMT_APB_MEM_RST_CH6_V 0x1 -#define RMT_APB_MEM_RST_CH6_S 4 -/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH6 (BIT(3)) -#define RMT_MEM_RD_RST_CH6_M (BIT(3)) -#define RMT_MEM_RD_RST_CH6_V 0x1 -#define RMT_MEM_RD_RST_CH6_S 3 -/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel6 by receiver access.*/ -#define RMT_MEM_WR_RST_CH6 (BIT(2)) -#define RMT_MEM_WR_RST_CH6_M (BIT(2)) -#define RMT_MEM_WR_RST_CH6_V 0x1 -#define RMT_MEM_WR_RST_CH6_S 2 -/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel6.*/ -#define RMT_RX_EN_CH6 (BIT(1)) -#define RMT_RX_EN_CH6_M (BIT(1)) -#define RMT_RX_EN_CH6_V 0x1 -#define RMT_RX_EN_CH6_S 1 -/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel6.*/ -#define RMT_TX_START_CH6 (BIT(0)) -#define RMT_TX_START_CH6_M (BIT(0)) -#define RMT_TX_START_CH6_V 0x1 -#define RMT_TX_START_CH6_S 0 - -#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0058) -/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH7_V 0x1 -#define RMT_CARRIER_OUT_LV_CH7_S 29 -/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel7.*/ -#define RMT_CARRIER_EN_CH7 (BIT(28)) -#define RMT_CARRIER_EN_CH7_M (BIT(28)) -#define RMT_CARRIER_EN_CH7_V 0x1 -#define RMT_CARRIER_EN_CH7_S 28 -/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel7.*/ -#define RMT_MEM_SIZE_CH7 0x0000000F -#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S)) -#define RMT_MEM_SIZE_CH7_V 0xF -#define RMT_MEM_SIZE_CH7_S 24 -/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH7 0x0000FFFF -#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S)) -#define RMT_IDLE_THRES_CH7_V 0xFFFF -#define RMT_IDLE_THRES_CH7_S 8 -/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel7.*/ -#define RMT_DIV_CNT_CH7 0x000000FF -#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S)) -#define RMT_DIV_CNT_CH7_V 0xFF -#define RMT_DIV_CNT_CH7_S 0 - -#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x005c) -/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel6 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH7 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH7_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH7_V 0x1 -#define RMT_IDLE_OUT_EN_CH7_S 19 -/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel7 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH7 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH7_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH7_V 0x1 -#define RMT_IDLE_OUT_LV_CH7_S 18 -/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH7 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH7_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH7_V 0x1 -#define RMT_REF_ALWAYS_ON_CH7_S 17 -/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel7.*/ -#define RMT_REF_CNT_RST_CH7 (BIT(16)) -#define RMT_REF_CNT_RST_CH7_M (BIT(16)) -#define RMT_REF_CNT_RST_CH7_V 0x1 -#define RMT_REF_CNT_RST_CH7_S 16 -/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel7 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH7 0x000000FF -#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S)) -#define RMT_RX_FILTER_THRES_CH7_V 0xFF -#define RMT_RX_FILTER_THRES_CH7_S 8 -/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel7.*/ -#define RMT_RX_FILTER_EN_CH7 (BIT(7)) -#define RMT_RX_FILTER_EN_CH7_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH7_V 0x1 -#define RMT_RX_FILTER_EN_CH7_S 7 -/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel7.*/ -#define RMT_TX_CONTI_MODE_CH7 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH7_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH7_V 0x1 -#define RMT_TX_CONTI_MODE_CH7_S 6 -/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel7's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH7 (BIT(5)) -#define RMT_MEM_OWNER_CH7_M (BIT(5)) -#define RMT_MEM_OWNER_CH7_V 0x1 -#define RMT_MEM_OWNER_CH7_S 5 -/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH7 (BIT(4)) -#define RMT_APB_MEM_RST_CH7_M (BIT(4)) -#define RMT_APB_MEM_RST_CH7_V 0x1 -#define RMT_APB_MEM_RST_CH7_S 4 -/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH7 (BIT(3)) -#define RMT_MEM_RD_RST_CH7_M (BIT(3)) -#define RMT_MEM_RD_RST_CH7_V 0x1 -#define RMT_MEM_RD_RST_CH7_S 3 -/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel7 by receiver access.*/ -#define RMT_MEM_WR_RST_CH7 (BIT(2)) -#define RMT_MEM_WR_RST_CH7_M (BIT(2)) -#define RMT_MEM_WR_RST_CH7_V 0x1 -#define RMT_MEM_WR_RST_CH7_S 2 -/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel7.*/ -#define RMT_RX_EN_CH7 (BIT(1)) -#define RMT_RX_EN_CH7_M (BIT(1)) -#define RMT_RX_EN_CH7_V 0x1 -#define RMT_RX_EN_CH7_S 1 -/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel7.*/ -#define RMT_TX_START_CH7 (BIT(0)) -#define RMT_TX_START_CH7_M (BIT(0)) -#define RMT_TX_START_CH7_V 0x1 -#define RMT_TX_START_CH7_S 0 - -#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0060) -/* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel0*/ -#define RMT_STATUS_CH0 0xFFFFFFFF -#define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S)) -#define RMT_STATUS_CH0_V 0xFFFFFFFF -#define RMT_STATUS_CH0_S 0 - -#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064) -/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel1*/ -#define RMT_STATUS_CH1 0xFFFFFFFF -#define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S)) -#define RMT_STATUS_CH1_V 0xFFFFFFFF -#define RMT_STATUS_CH1_S 0 - -#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068) -/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel2*/ -#define RMT_STATUS_CH2 0xFFFFFFFF -#define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S)) -#define RMT_STATUS_CH2_V 0xFFFFFFFF -#define RMT_STATUS_CH2_S 0 - -#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c) -/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel3*/ -#define RMT_STATUS_CH3 0xFFFFFFFF -#define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S)) -#define RMT_STATUS_CH3_V 0xFFFFFFFF -#define RMT_STATUS_CH3_S 0 - -#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070) -/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel4*/ -#define RMT_STATUS_CH4 0xFFFFFFFF -#define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S)) -#define RMT_STATUS_CH4_V 0xFFFFFFFF -#define RMT_STATUS_CH4_S 0 - -#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074) -/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel5*/ -#define RMT_STATUS_CH5 0xFFFFFFFF -#define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S)) -#define RMT_STATUS_CH5_V 0xFFFFFFFF -#define RMT_STATUS_CH5_S 0 - -#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078) -/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel6*/ -#define RMT_STATUS_CH6 0xFFFFFFFF -#define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S)) -#define RMT_STATUS_CH6_V 0xFFFFFFFF -#define RMT_STATUS_CH6_S 0 - -#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c) -/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel7*/ -#define RMT_STATUS_CH7 0xFFFFFFFF -#define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S)) -#define RMT_STATUS_CH7_V 0xFFFFFFFF -#define RMT_STATUS_CH7_S 0 - -#define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080) -/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel0 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH0 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH0_M ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S)) -#define RMT_APB_MEM_ADDR_CH0_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH0_S 0 - -#define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x0084) -/* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel1 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH1 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH1_M ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S)) -#define RMT_APB_MEM_ADDR_CH1_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH1_S 0 - -#define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x0088) -/* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel2 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH2 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH2_M ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S)) -#define RMT_APB_MEM_ADDR_CH2_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH2_S 0 - -#define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x008c) -/* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel3 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH3 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH3_M ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S)) -#define RMT_APB_MEM_ADDR_CH3_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH3_S 0 - -#define RMT_CH4ADDR_REG (DR_REG_RMT_BASE + 0x0090) -/* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel4 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH4 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH4_M ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S)) -#define RMT_APB_MEM_ADDR_CH4_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH4_S 0 - -#define RMT_CH5ADDR_REG (DR_REG_RMT_BASE + 0x0094) -/* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel5 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH5 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH5_M ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S)) -#define RMT_APB_MEM_ADDR_CH5_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH5_S 0 - -#define RMT_CH6ADDR_REG (DR_REG_RMT_BASE + 0x0098) -/* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel6 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH6 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH6_M ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S)) -#define RMT_APB_MEM_ADDR_CH6_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH6_S 0 - -#define RMT_CH7ADDR_REG (DR_REG_RMT_BASE + 0x009c) -/* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel7 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH7 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH7_M ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S)) -#define RMT_APB_MEM_ADDR_CH7_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH7_S 0 - -#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0) -/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 7 turns to high level when - transmitter in channle7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31 -/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 6 turns to high level when - transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30 -/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 5 turns to high level when - transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29 -/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 4 turns to high level when - transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28 -/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 3 turns to high level when - transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27 -/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 2 turns to high level when - transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26 -/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 1 turns to high level when - transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25 -/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 0 turns to high level when - transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24 -/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 7 turns to high level when - channle 7 detects some errors.*/ -#define RMT_CH7_ERR_INT_RAW (BIT(23)) -#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) -#define RMT_CH7_ERR_INT_RAW_V 0x1 -#define RMT_CH7_ERR_INT_RAW_S 23 -/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 7 turns to high level when - the receive process is done.*/ -#define RMT_CH7_RX_END_INT_RAW (BIT(22)) -#define RMT_CH7_RX_END_INT_RAW_M (BIT(22)) -#define RMT_CH7_RX_END_INT_RAW_V 0x1 -#define RMT_CH7_RX_END_INT_RAW_S 22 -/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 7 turns to high level when - the transmit process is done.*/ -#define RMT_CH7_TX_END_INT_RAW (BIT(21)) -#define RMT_CH7_TX_END_INT_RAW_M (BIT(21)) -#define RMT_CH7_TX_END_INT_RAW_V 0x1 -#define RMT_CH7_TX_END_INT_RAW_S 21 -/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 6 turns to high level when - channle 6 detects some errors.*/ -#define RMT_CH6_ERR_INT_RAW (BIT(20)) -#define RMT_CH6_ERR_INT_RAW_M (BIT(20)) -#define RMT_CH6_ERR_INT_RAW_V 0x1 -#define RMT_CH6_ERR_INT_RAW_S 20 -/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 6 turns to high level when - the receive process is done.*/ -#define RMT_CH6_RX_END_INT_RAW (BIT(19)) -#define RMT_CH6_RX_END_INT_RAW_M (BIT(19)) -#define RMT_CH6_RX_END_INT_RAW_V 0x1 -#define RMT_CH6_RX_END_INT_RAW_S 19 -/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 6 turns to high level when - the transmit process is done.*/ -#define RMT_CH6_TX_END_INT_RAW (BIT(18)) -#define RMT_CH6_TX_END_INT_RAW_M (BIT(18)) -#define RMT_CH6_TX_END_INT_RAW_V 0x1 -#define RMT_CH6_TX_END_INT_RAW_S 18 -/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 5 turns to high level when - channle 5 detects some errors.*/ -#define RMT_CH5_ERR_INT_RAW (BIT(17)) -#define RMT_CH5_ERR_INT_RAW_M (BIT(17)) -#define RMT_CH5_ERR_INT_RAW_V 0x1 -#define RMT_CH5_ERR_INT_RAW_S 17 -/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 5 turns to high level when - the receive process is done.*/ -#define RMT_CH5_RX_END_INT_RAW (BIT(16)) -#define RMT_CH5_RX_END_INT_RAW_M (BIT(16)) -#define RMT_CH5_RX_END_INT_RAW_V 0x1 -#define RMT_CH5_RX_END_INT_RAW_S 16 -/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 5 turns to high level when - the transmit process is done.*/ -#define RMT_CH5_TX_END_INT_RAW (BIT(15)) -#define RMT_CH5_TX_END_INT_RAW_M (BIT(15)) -#define RMT_CH5_TX_END_INT_RAW_V 0x1 -#define RMT_CH5_TX_END_INT_RAW_S 15 -/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 4 turns to high level when - channle 4 detects some errors.*/ -#define RMT_CH4_ERR_INT_RAW (BIT(14)) -#define RMT_CH4_ERR_INT_RAW_M (BIT(14)) -#define RMT_CH4_ERR_INT_RAW_V 0x1 -#define RMT_CH4_ERR_INT_RAW_S 14 -/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 4 turns to high level when - the receive process is done.*/ -#define RMT_CH4_RX_END_INT_RAW (BIT(13)) -#define RMT_CH4_RX_END_INT_RAW_M (BIT(13)) -#define RMT_CH4_RX_END_INT_RAW_V 0x1 -#define RMT_CH4_RX_END_INT_RAW_S 13 -/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 4 turns to high level when - the transmit process is done.*/ -#define RMT_CH4_TX_END_INT_RAW (BIT(12)) -#define RMT_CH4_TX_END_INT_RAW_M (BIT(12)) -#define RMT_CH4_TX_END_INT_RAW_V 0x1 -#define RMT_CH4_TX_END_INT_RAW_S 12 -/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 3 turns to high level when - channle 3 detects some errors.*/ -#define RMT_CH3_ERR_INT_RAW (BIT(11)) -#define RMT_CH3_ERR_INT_RAW_M (BIT(11)) -#define RMT_CH3_ERR_INT_RAW_V 0x1 -#define RMT_CH3_ERR_INT_RAW_S 11 -/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 3 turns to high level when - the receive process is done.*/ -#define RMT_CH3_RX_END_INT_RAW (BIT(10)) -#define RMT_CH3_RX_END_INT_RAW_M (BIT(10)) -#define RMT_CH3_RX_END_INT_RAW_V 0x1 -#define RMT_CH3_RX_END_INT_RAW_S 10 -/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 3 turns to high level when - the transmit process is done.*/ -#define RMT_CH3_TX_END_INT_RAW (BIT(9)) -#define RMT_CH3_TX_END_INT_RAW_M (BIT(9)) -#define RMT_CH3_TX_END_INT_RAW_V 0x1 -#define RMT_CH3_TX_END_INT_RAW_S 9 -/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 2 turns to high level when - channle 2 detects some errors.*/ -#define RMT_CH2_ERR_INT_RAW (BIT(8)) -#define RMT_CH2_ERR_INT_RAW_M (BIT(8)) -#define RMT_CH2_ERR_INT_RAW_V 0x1 -#define RMT_CH2_ERR_INT_RAW_S 8 -/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 2 turns to high level when - the receive process is done.*/ -#define RMT_CH2_RX_END_INT_RAW (BIT(7)) -#define RMT_CH2_RX_END_INT_RAW_M (BIT(7)) -#define RMT_CH2_RX_END_INT_RAW_V 0x1 -#define RMT_CH2_RX_END_INT_RAW_S 7 -/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 2 turns to high level when - the transmit process is done.*/ -#define RMT_CH2_TX_END_INT_RAW (BIT(6)) -#define RMT_CH2_TX_END_INT_RAW_M (BIT(6)) -#define RMT_CH2_TX_END_INT_RAW_V 0x1 -#define RMT_CH2_TX_END_INT_RAW_S 6 -/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 1 turns to high level when - channle 1 detects some errors.*/ -#define RMT_CH1_ERR_INT_RAW (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_V 0x1 -#define RMT_CH1_ERR_INT_RAW_S 5 -/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 1 turns to high level when - the receive process is done.*/ -#define RMT_CH1_RX_END_INT_RAW (BIT(4)) -#define RMT_CH1_RX_END_INT_RAW_M (BIT(4)) -#define RMT_CH1_RX_END_INT_RAW_V 0x1 -#define RMT_CH1_RX_END_INT_RAW_S 4 -/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 1 turns to high level when - the transmit process is done.*/ -#define RMT_CH1_TX_END_INT_RAW (BIT(3)) -#define RMT_CH1_TX_END_INT_RAW_M (BIT(3)) -#define RMT_CH1_TX_END_INT_RAW_V 0x1 -#define RMT_CH1_TX_END_INT_RAW_S 3 -/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 0 turns to high level when - channle 0 detects some errors.*/ -#define RMT_CH0_ERR_INT_RAW (BIT(2)) -#define RMT_CH0_ERR_INT_RAW_M (BIT(2)) -#define RMT_CH0_ERR_INT_RAW_V 0x1 -#define RMT_CH0_ERR_INT_RAW_S 2 -/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 0 turns to high level when - the receive process is done.*/ -#define RMT_CH0_RX_END_INT_RAW (BIT(1)) -#define RMT_CH0_RX_END_INT_RAW_M (BIT(1)) -#define RMT_CH0_RX_END_INT_RAW_V 0x1 -#define RMT_CH0_RX_END_INT_RAW_S 1 -/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 0 turns to high level when - the transmit process is done.*/ -#define RMT_CH0_TX_END_INT_RAW (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_V 0x1 -#define RMT_CH0_TX_END_INT_RAW_S 0 - -#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x00a4) -/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw - when mt_ch7_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH7_TX_THR_EVENT_INT_ST (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_ST_M (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH7_TX_THR_EVENT_INT_ST_S 31 -/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw - when mt_ch6_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH6_TX_THR_EVENT_INT_ST (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_ST_M (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH6_TX_THR_EVENT_INT_ST_S 30 -/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw - when mt_ch5_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH5_TX_THR_EVENT_INT_ST (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_ST_M (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH5_TX_THR_EVENT_INT_ST_S 29 -/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw - when mt_ch4_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH4_TX_THR_EVENT_INT_ST (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_ST_M (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH4_TX_THR_EVENT_INT_ST_S 28 -/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw - when mt_ch3_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_ST_S 27 -/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw - when mt_ch2_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_ST_S 26 -/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw - when mt_ch1_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ST_S 25 -/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw - when mt_ch0_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ST_S 24 -/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 7's rmt_ch7_err_int_raw - when rmt_ch7_err_int_ena is set to 1.*/ -#define RMT_CH7_ERR_INT_ST (BIT(23)) -#define RMT_CH7_ERR_INT_ST_M (BIT(23)) -#define RMT_CH7_ERR_INT_ST_V 0x1 -#define RMT_CH7_ERR_INT_ST_S 23 -/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw - when rmt_ch7_rx_end_int_ena is set to 1.*/ -#define RMT_CH7_RX_END_INT_ST (BIT(22)) -#define RMT_CH7_RX_END_INT_ST_M (BIT(22)) -#define RMT_CH7_RX_END_INT_ST_V 0x1 -#define RMT_CH7_RX_END_INT_ST_S 22 -/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw - when mt_ch7_tx_end_int_ena is set to 1.*/ -#define RMT_CH7_TX_END_INT_ST (BIT(21)) -#define RMT_CH7_TX_END_INT_ST_M (BIT(21)) -#define RMT_CH7_TX_END_INT_ST_V 0x1 -#define RMT_CH7_TX_END_INT_ST_S 21 -/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 6's rmt_ch6_err_int_raw - when rmt_ch6_err_int_ena is set to 1.*/ -#define RMT_CH6_ERR_INT_ST (BIT(20)) -#define RMT_CH6_ERR_INT_ST_M (BIT(20)) -#define RMT_CH6_ERR_INT_ST_V 0x1 -#define RMT_CH6_ERR_INT_ST_S 20 -/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw - when rmt_ch6_rx_end_int_ena is set to 1.*/ -#define RMT_CH6_RX_END_INT_ST (BIT(19)) -#define RMT_CH6_RX_END_INT_ST_M (BIT(19)) -#define RMT_CH6_RX_END_INT_ST_V 0x1 -#define RMT_CH6_RX_END_INT_ST_S 19 -/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw - when mt_ch6_tx_end_int_ena is set to 1.*/ -#define RMT_CH6_TX_END_INT_ST (BIT(18)) -#define RMT_CH6_TX_END_INT_ST_M (BIT(18)) -#define RMT_CH6_TX_END_INT_ST_V 0x1 -#define RMT_CH6_TX_END_INT_ST_S 18 -/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 5's rmt_ch5_err_int_raw - when rmt_ch5_err_int_ena is set to 1.*/ -#define RMT_CH5_ERR_INT_ST (BIT(17)) -#define RMT_CH5_ERR_INT_ST_M (BIT(17)) -#define RMT_CH5_ERR_INT_ST_V 0x1 -#define RMT_CH5_ERR_INT_ST_S 17 -/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw - when rmt_ch5_rx_end_int_ena is set to 1.*/ -#define RMT_CH5_RX_END_INT_ST (BIT(16)) -#define RMT_CH5_RX_END_INT_ST_M (BIT(16)) -#define RMT_CH5_RX_END_INT_ST_V 0x1 -#define RMT_CH5_RX_END_INT_ST_S 16 -/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw - when mt_ch5_tx_end_int_ena is set to 1.*/ -#define RMT_CH5_TX_END_INT_ST (BIT(15)) -#define RMT_CH5_TX_END_INT_ST_M (BIT(15)) -#define RMT_CH5_TX_END_INT_ST_V 0x1 -#define RMT_CH5_TX_END_INT_ST_S 15 -/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 4's rmt_ch4_err_int_raw - when rmt_ch4_err_int_ena is set to 1.*/ -#define RMT_CH4_ERR_INT_ST (BIT(14)) -#define RMT_CH4_ERR_INT_ST_M (BIT(14)) -#define RMT_CH4_ERR_INT_ST_V 0x1 -#define RMT_CH4_ERR_INT_ST_S 14 -/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw - when rmt_ch4_rx_end_int_ena is set to 1.*/ -#define RMT_CH4_RX_END_INT_ST (BIT(13)) -#define RMT_CH4_RX_END_INT_ST_M (BIT(13)) -#define RMT_CH4_RX_END_INT_ST_V 0x1 -#define RMT_CH4_RX_END_INT_ST_S 13 -/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw - when mt_ch4_tx_end_int_ena is set to 1.*/ -#define RMT_CH4_TX_END_INT_ST (BIT(12)) -#define RMT_CH4_TX_END_INT_ST_M (BIT(12)) -#define RMT_CH4_TX_END_INT_ST_V 0x1 -#define RMT_CH4_TX_END_INT_ST_S 12 -/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 3's rmt_ch3_err_int_raw - when rmt_ch3_err_int_ena is set to 1.*/ -#define RMT_CH3_ERR_INT_ST (BIT(11)) -#define RMT_CH3_ERR_INT_ST_M (BIT(11)) -#define RMT_CH3_ERR_INT_ST_V 0x1 -#define RMT_CH3_ERR_INT_ST_S 11 -/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw - when rmt_ch3_rx_end_int_ena is set to 1.*/ -#define RMT_CH3_RX_END_INT_ST (BIT(10)) -#define RMT_CH3_RX_END_INT_ST_M (BIT(10)) -#define RMT_CH3_RX_END_INT_ST_V 0x1 -#define RMT_CH3_RX_END_INT_ST_S 10 -/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw - when mt_ch3_tx_end_int_ena is set to 1.*/ -#define RMT_CH3_TX_END_INT_ST (BIT(9)) -#define RMT_CH3_TX_END_INT_ST_M (BIT(9)) -#define RMT_CH3_TX_END_INT_ST_V 0x1 -#define RMT_CH3_TX_END_INT_ST_S 9 -/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 2's rmt_ch2_err_int_raw - when rmt_ch2_err_int_ena is set to 1.*/ -#define RMT_CH2_ERR_INT_ST (BIT(8)) -#define RMT_CH2_ERR_INT_ST_M (BIT(8)) -#define RMT_CH2_ERR_INT_ST_V 0x1 -#define RMT_CH2_ERR_INT_ST_S 8 -/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw - when rmt_ch2_rx_end_int_ena is set to 1.*/ -#define RMT_CH2_RX_END_INT_ST (BIT(7)) -#define RMT_CH2_RX_END_INT_ST_M (BIT(7)) -#define RMT_CH2_RX_END_INT_ST_V 0x1 -#define RMT_CH2_RX_END_INT_ST_S 7 -/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw - when mt_ch2_tx_end_int_ena is set to 1.*/ -#define RMT_CH2_TX_END_INT_ST (BIT(6)) -#define RMT_CH2_TX_END_INT_ST_M (BIT(6)) -#define RMT_CH2_TX_END_INT_ST_V 0x1 -#define RMT_CH2_TX_END_INT_ST_S 6 -/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 1's rmt_ch1_err_int_raw - when rmt_ch1_err_int_ena is set to 1.*/ -#define RMT_CH1_ERR_INT_ST (BIT(5)) -#define RMT_CH1_ERR_INT_ST_M (BIT(5)) -#define RMT_CH1_ERR_INT_ST_V 0x1 -#define RMT_CH1_ERR_INT_ST_S 5 -/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw - when rmt_ch1_rx_end_int_ena is set to 1.*/ -#define RMT_CH1_RX_END_INT_ST (BIT(4)) -#define RMT_CH1_RX_END_INT_ST_M (BIT(4)) -#define RMT_CH1_RX_END_INT_ST_V 0x1 -#define RMT_CH1_RX_END_INT_ST_S 4 -/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw - when mt_ch1_tx_end_int_ena is set to 1.*/ -#define RMT_CH1_TX_END_INT_ST (BIT(3)) -#define RMT_CH1_TX_END_INT_ST_M (BIT(3)) -#define RMT_CH1_TX_END_INT_ST_V 0x1 -#define RMT_CH1_TX_END_INT_ST_S 3 -/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 0's rmt_ch0_err_int_raw - when rmt_ch0_err_int_ena is set to 0.*/ -#define RMT_CH0_ERR_INT_ST (BIT(2)) -#define RMT_CH0_ERR_INT_ST_M (BIT(2)) -#define RMT_CH0_ERR_INT_ST_V 0x1 -#define RMT_CH0_ERR_INT_ST_S 2 -/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw - when rmt_ch0_rx_end_int_ena is set to 0.*/ -#define RMT_CH0_RX_END_INT_ST (BIT(1)) -#define RMT_CH0_RX_END_INT_ST_M (BIT(1)) -#define RMT_CH0_RX_END_INT_ST_V 0x1 -#define RMT_CH0_RX_END_INT_ST_S 1 -/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw - when mt_ch0_tx_end_int_ena is set to 0.*/ -#define RMT_CH0_TX_END_INT_ST (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_V 0x1 -#define RMT_CH0_TX_END_INT_ST_S 0 - -#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x00a8) -/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ -#define RMT_CH7_TX_THR_EVENT_INT_ENA (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_ENA_M (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH7_TX_THR_EVENT_INT_ENA_S 31 -/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ -#define RMT_CH6_TX_THR_EVENT_INT_ENA (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_ENA_M (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH6_TX_THR_EVENT_INT_ENA_S 30 -/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ -#define RMT_CH5_TX_THR_EVENT_INT_ENA (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_ENA_M (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH5_TX_THR_EVENT_INT_ENA_S 29 -/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ -#define RMT_CH4_TX_THR_EVENT_INT_ENA (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_ENA_M (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH4_TX_THR_EVENT_INT_ENA_S 28 -/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ -#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 27 -/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ -#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 26 -/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ -#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 25 -/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ -#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 24 -/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch7_err_int_st.*/ -#define RMT_CH7_ERR_INT_ENA (BIT(23)) -#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) -#define RMT_CH7_ERR_INT_ENA_V 0x1 -#define RMT_CH7_ERR_INT_ENA_S 23 -/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/ -#define RMT_CH7_RX_END_INT_ENA (BIT(22)) -#define RMT_CH7_RX_END_INT_ENA_M (BIT(22)) -#define RMT_CH7_RX_END_INT_ENA_V 0x1 -#define RMT_CH7_RX_END_INT_ENA_S 22 -/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/ -#define RMT_CH7_TX_END_INT_ENA (BIT(21)) -#define RMT_CH7_TX_END_INT_ENA_M (BIT(21)) -#define RMT_CH7_TX_END_INT_ENA_V 0x1 -#define RMT_CH7_TX_END_INT_ENA_S 21 -/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch6_err_int_st.*/ -#define RMT_CH6_ERR_INT_ENA (BIT(20)) -#define RMT_CH6_ERR_INT_ENA_M (BIT(20)) -#define RMT_CH6_ERR_INT_ENA_V 0x1 -#define RMT_CH6_ERR_INT_ENA_S 20 -/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/ -#define RMT_CH6_RX_END_INT_ENA (BIT(19)) -#define RMT_CH6_RX_END_INT_ENA_M (BIT(19)) -#define RMT_CH6_RX_END_INT_ENA_V 0x1 -#define RMT_CH6_RX_END_INT_ENA_S 19 -/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/ -#define RMT_CH6_TX_END_INT_ENA (BIT(18)) -#define RMT_CH6_TX_END_INT_ENA_M (BIT(18)) -#define RMT_CH6_TX_END_INT_ENA_V 0x1 -#define RMT_CH6_TX_END_INT_ENA_S 18 -/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch5_err_int_st.*/ -#define RMT_CH5_ERR_INT_ENA (BIT(17)) -#define RMT_CH5_ERR_INT_ENA_M (BIT(17)) -#define RMT_CH5_ERR_INT_ENA_V 0x1 -#define RMT_CH5_ERR_INT_ENA_S 17 -/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/ -#define RMT_CH5_RX_END_INT_ENA (BIT(16)) -#define RMT_CH5_RX_END_INT_ENA_M (BIT(16)) -#define RMT_CH5_RX_END_INT_ENA_V 0x1 -#define RMT_CH5_RX_END_INT_ENA_S 16 -/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/ -#define RMT_CH5_TX_END_INT_ENA (BIT(15)) -#define RMT_CH5_TX_END_INT_ENA_M (BIT(15)) -#define RMT_CH5_TX_END_INT_ENA_V 0x1 -#define RMT_CH5_TX_END_INT_ENA_S 15 -/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch4_err_int_st.*/ -#define RMT_CH4_ERR_INT_ENA (BIT(14)) -#define RMT_CH4_ERR_INT_ENA_M (BIT(14)) -#define RMT_CH4_ERR_INT_ENA_V 0x1 -#define RMT_CH4_ERR_INT_ENA_S 14 -/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/ -#define RMT_CH4_RX_END_INT_ENA (BIT(13)) -#define RMT_CH4_RX_END_INT_ENA_M (BIT(13)) -#define RMT_CH4_RX_END_INT_ENA_V 0x1 -#define RMT_CH4_RX_END_INT_ENA_S 13 -/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/ -#define RMT_CH4_TX_END_INT_ENA (BIT(12)) -#define RMT_CH4_TX_END_INT_ENA_M (BIT(12)) -#define RMT_CH4_TX_END_INT_ENA_V 0x1 -#define RMT_CH4_TX_END_INT_ENA_S 12 -/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch3_err_int_st.*/ -#define RMT_CH3_ERR_INT_ENA (BIT(11)) -#define RMT_CH3_ERR_INT_ENA_M (BIT(11)) -#define RMT_CH3_ERR_INT_ENA_V 0x1 -#define RMT_CH3_ERR_INT_ENA_S 11 -/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/ -#define RMT_CH3_RX_END_INT_ENA (BIT(10)) -#define RMT_CH3_RX_END_INT_ENA_M (BIT(10)) -#define RMT_CH3_RX_END_INT_ENA_V 0x1 -#define RMT_CH3_RX_END_INT_ENA_S 10 -/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/ -#define RMT_CH3_TX_END_INT_ENA (BIT(9)) -#define RMT_CH3_TX_END_INT_ENA_M (BIT(9)) -#define RMT_CH3_TX_END_INT_ENA_V 0x1 -#define RMT_CH3_TX_END_INT_ENA_S 9 -/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch2_err_int_st.*/ -#define RMT_CH2_ERR_INT_ENA (BIT(8)) -#define RMT_CH2_ERR_INT_ENA_M (BIT(8)) -#define RMT_CH2_ERR_INT_ENA_V 0x1 -#define RMT_CH2_ERR_INT_ENA_S 8 -/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/ -#define RMT_CH2_RX_END_INT_ENA (BIT(7)) -#define RMT_CH2_RX_END_INT_ENA_M (BIT(7)) -#define RMT_CH2_RX_END_INT_ENA_V 0x1 -#define RMT_CH2_RX_END_INT_ENA_S 7 -/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/ -#define RMT_CH2_TX_END_INT_ENA (BIT(6)) -#define RMT_CH2_TX_END_INT_ENA_M (BIT(6)) -#define RMT_CH2_TX_END_INT_ENA_V 0x1 -#define RMT_CH2_TX_END_INT_ENA_S 6 -/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch1_err_int_st.*/ -#define RMT_CH1_ERR_INT_ENA (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_V 0x1 -#define RMT_CH1_ERR_INT_ENA_S 5 -/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/ -#define RMT_CH1_RX_END_INT_ENA (BIT(4)) -#define RMT_CH1_RX_END_INT_ENA_M (BIT(4)) -#define RMT_CH1_RX_END_INT_ENA_V 0x1 -#define RMT_CH1_RX_END_INT_ENA_S 4 -/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/ -#define RMT_CH1_TX_END_INT_ENA (BIT(3)) -#define RMT_CH1_TX_END_INT_ENA_M (BIT(3)) -#define RMT_CH1_TX_END_INT_ENA_V 0x1 -#define RMT_CH1_TX_END_INT_ENA_S 3 -/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch0_err_int_st.*/ -#define RMT_CH0_ERR_INT_ENA (BIT(2)) -#define RMT_CH0_ERR_INT_ENA_M (BIT(2)) -#define RMT_CH0_ERR_INT_ENA_V 0x1 -#define RMT_CH0_ERR_INT_ENA_S 2 -/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/ -#define RMT_CH0_RX_END_INT_ENA (BIT(1)) -#define RMT_CH0_RX_END_INT_ENA_M (BIT(1)) -#define RMT_CH0_RX_END_INT_ENA_V 0x1 -#define RMT_CH0_RX_END_INT_ENA_S 1 -/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/ -#define RMT_CH0_TX_END_INT_ENA (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_V 0x1 -#define RMT_CH0_TX_END_INT_ENA_S 0 - -#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x00ac) -/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH7_TX_THR_EVENT_INT_CLR (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_CLR_M (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH7_TX_THR_EVENT_INT_CLR_S 31 -/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH6_TX_THR_EVENT_INT_CLR (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_CLR_M (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH6_TX_THR_EVENT_INT_CLR_S 30 -/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH5_TX_THR_EVENT_INT_CLR (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_CLR_M (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH5_TX_THR_EVENT_INT_CLR_S 29 -/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH4_TX_THR_EVENT_INT_CLR (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_CLR_M (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH4_TX_THR_EVENT_INT_CLR_S 28 -/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 27 -/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 26 -/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 25 -/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 24 -/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch7_err_int_raw.*/ -#define RMT_CH7_ERR_INT_CLR (BIT(23)) -#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) -#define RMT_CH7_ERR_INT_CLR_V 0x1 -#define RMT_CH7_ERR_INT_CLR_S 23 -/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ -#define RMT_CH7_RX_END_INT_CLR (BIT(22)) -#define RMT_CH7_RX_END_INT_CLR_M (BIT(22)) -#define RMT_CH7_RX_END_INT_CLR_V 0x1 -#define RMT_CH7_RX_END_INT_CLR_S 22 -/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ -#define RMT_CH7_TX_END_INT_CLR (BIT(21)) -#define RMT_CH7_TX_END_INT_CLR_M (BIT(21)) -#define RMT_CH7_TX_END_INT_CLR_V 0x1 -#define RMT_CH7_TX_END_INT_CLR_S 21 -/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch6_err_int_raw.*/ -#define RMT_CH6_ERR_INT_CLR (BIT(20)) -#define RMT_CH6_ERR_INT_CLR_M (BIT(20)) -#define RMT_CH6_ERR_INT_CLR_V 0x1 -#define RMT_CH6_ERR_INT_CLR_S 20 -/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ -#define RMT_CH6_RX_END_INT_CLR (BIT(19)) -#define RMT_CH6_RX_END_INT_CLR_M (BIT(19)) -#define RMT_CH6_RX_END_INT_CLR_V 0x1 -#define RMT_CH6_RX_END_INT_CLR_S 19 -/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ -#define RMT_CH6_TX_END_INT_CLR (BIT(18)) -#define RMT_CH6_TX_END_INT_CLR_M (BIT(18)) -#define RMT_CH6_TX_END_INT_CLR_V 0x1 -#define RMT_CH6_TX_END_INT_CLR_S 18 -/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch5_err_int_raw.*/ -#define RMT_CH5_ERR_INT_CLR (BIT(17)) -#define RMT_CH5_ERR_INT_CLR_M (BIT(17)) -#define RMT_CH5_ERR_INT_CLR_V 0x1 -#define RMT_CH5_ERR_INT_CLR_S 17 -/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ -#define RMT_CH5_RX_END_INT_CLR (BIT(16)) -#define RMT_CH5_RX_END_INT_CLR_M (BIT(16)) -#define RMT_CH5_RX_END_INT_CLR_V 0x1 -#define RMT_CH5_RX_END_INT_CLR_S 16 -/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ -#define RMT_CH5_TX_END_INT_CLR (BIT(15)) -#define RMT_CH5_TX_END_INT_CLR_M (BIT(15)) -#define RMT_CH5_TX_END_INT_CLR_V 0x1 -#define RMT_CH5_TX_END_INT_CLR_S 15 -/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch4_err_int_raw.*/ -#define RMT_CH4_ERR_INT_CLR (BIT(14)) -#define RMT_CH4_ERR_INT_CLR_M (BIT(14)) -#define RMT_CH4_ERR_INT_CLR_V 0x1 -#define RMT_CH4_ERR_INT_CLR_S 14 -/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ -#define RMT_CH4_RX_END_INT_CLR (BIT(13)) -#define RMT_CH4_RX_END_INT_CLR_M (BIT(13)) -#define RMT_CH4_RX_END_INT_CLR_V 0x1 -#define RMT_CH4_RX_END_INT_CLR_S 13 -/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ -#define RMT_CH4_TX_END_INT_CLR (BIT(12)) -#define RMT_CH4_TX_END_INT_CLR_M (BIT(12)) -#define RMT_CH4_TX_END_INT_CLR_V 0x1 -#define RMT_CH4_TX_END_INT_CLR_S 12 -/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch3_err_int_raw.*/ -#define RMT_CH3_ERR_INT_CLR (BIT(11)) -#define RMT_CH3_ERR_INT_CLR_M (BIT(11)) -#define RMT_CH3_ERR_INT_CLR_V 0x1 -#define RMT_CH3_ERR_INT_CLR_S 11 -/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ -#define RMT_CH3_RX_END_INT_CLR (BIT(10)) -#define RMT_CH3_RX_END_INT_CLR_M (BIT(10)) -#define RMT_CH3_RX_END_INT_CLR_V 0x1 -#define RMT_CH3_RX_END_INT_CLR_S 10 -/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ -#define RMT_CH3_TX_END_INT_CLR (BIT(9)) -#define RMT_CH3_TX_END_INT_CLR_M (BIT(9)) -#define RMT_CH3_TX_END_INT_CLR_V 0x1 -#define RMT_CH3_TX_END_INT_CLR_S 9 -/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch2_err_int_raw.*/ -#define RMT_CH2_ERR_INT_CLR (BIT(8)) -#define RMT_CH2_ERR_INT_CLR_M (BIT(8)) -#define RMT_CH2_ERR_INT_CLR_V 0x1 -#define RMT_CH2_ERR_INT_CLR_S 8 -/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ -#define RMT_CH2_RX_END_INT_CLR (BIT(7)) -#define RMT_CH2_RX_END_INT_CLR_M (BIT(7)) -#define RMT_CH2_RX_END_INT_CLR_V 0x1 -#define RMT_CH2_RX_END_INT_CLR_S 7 -/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ -#define RMT_CH2_TX_END_INT_CLR (BIT(6)) -#define RMT_CH2_TX_END_INT_CLR_M (BIT(6)) -#define RMT_CH2_TX_END_INT_CLR_V 0x1 -#define RMT_CH2_TX_END_INT_CLR_S 6 -/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch1_err_int_raw.*/ -#define RMT_CH1_ERR_INT_CLR (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_V 0x1 -#define RMT_CH1_ERR_INT_CLR_S 5 -/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ -#define RMT_CH1_RX_END_INT_CLR (BIT(4)) -#define RMT_CH1_RX_END_INT_CLR_M (BIT(4)) -#define RMT_CH1_RX_END_INT_CLR_V 0x1 -#define RMT_CH1_RX_END_INT_CLR_S 4 -/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ -#define RMT_CH1_TX_END_INT_CLR (BIT(3)) -#define RMT_CH1_TX_END_INT_CLR_M (BIT(3)) -#define RMT_CH1_TX_END_INT_CLR_V 0x1 -#define RMT_CH1_TX_END_INT_CLR_S 3 -/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch0_err_int_raw.*/ -#define RMT_CH0_ERR_INT_CLR (BIT(2)) -#define RMT_CH0_ERR_INT_CLR_M (BIT(2)) -#define RMT_CH0_ERR_INT_CLR_V 0x1 -#define RMT_CH0_ERR_INT_CLR_S 2 -/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ -#define RMT_CH0_RX_END_INT_CLR (BIT(1)) -#define RMT_CH0_RX_END_INT_CLR_M (BIT(1)) -#define RMT_CH0_RX_END_INT_CLR_V 0x1 -#define RMT_CH0_RX_END_INT_CLR_S 1 -/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ -#define RMT_CH0_TX_END_INT_CLR (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_V 0x1 -#define RMT_CH0_TX_END_INT_CLR_S 0 - -#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b0) -/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel0.*/ -#define RMT_CARRIER_HIGH_CH0 0x0000FFFF -#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) -#define RMT_CARRIER_HIGH_CH0_V 0xFFFF -#define RMT_CARRIER_HIGH_CH0_S 16 -/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel0.*/ -#define RMT_CARRIER_LOW_CH0 0x0000FFFF -#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) -#define RMT_CARRIER_LOW_CH0_V 0xFFFF -#define RMT_CARRIER_LOW_CH0_S 0 - -#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b4) -/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel1.*/ -#define RMT_CARRIER_HIGH_CH1 0x0000FFFF -#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) -#define RMT_CARRIER_HIGH_CH1_V 0xFFFF -#define RMT_CARRIER_HIGH_CH1_S 16 -/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel1.*/ -#define RMT_CARRIER_LOW_CH1 0x0000FFFF -#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) -#define RMT_CARRIER_LOW_CH1_V 0xFFFF -#define RMT_CARRIER_LOW_CH1_S 0 - -#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b8) -/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel2.*/ -#define RMT_CARRIER_HIGH_CH2 0x0000FFFF -#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S)) -#define RMT_CARRIER_HIGH_CH2_V 0xFFFF -#define RMT_CARRIER_HIGH_CH2_S 16 -/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel2.*/ -#define RMT_CARRIER_LOW_CH2 0x0000FFFF -#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S)) -#define RMT_CARRIER_LOW_CH2_V 0xFFFF -#define RMT_CARRIER_LOW_CH2_S 0 - -#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00bc) -/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel3.*/ -#define RMT_CARRIER_HIGH_CH3 0x0000FFFF -#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S)) -#define RMT_CARRIER_HIGH_CH3_V 0xFFFF -#define RMT_CARRIER_HIGH_CH3_S 16 -/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel3.*/ -#define RMT_CARRIER_LOW_CH3 0x0000FFFF -#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S)) -#define RMT_CARRIER_LOW_CH3_V 0xFFFF -#define RMT_CARRIER_LOW_CH3_S 0 - -#define RMT_CH4CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c0) -/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel4.*/ -#define RMT_CARRIER_HIGH_CH4 0x0000FFFF -#define RMT_CARRIER_HIGH_CH4_M ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S)) -#define RMT_CARRIER_HIGH_CH4_V 0xFFFF -#define RMT_CARRIER_HIGH_CH4_S 16 -/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel4.*/ -#define RMT_CARRIER_LOW_CH4 0x0000FFFF -#define RMT_CARRIER_LOW_CH4_M ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S)) -#define RMT_CARRIER_LOW_CH4_V 0xFFFF -#define RMT_CARRIER_LOW_CH4_S 0 - -#define RMT_CH5CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c4) -/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel5.*/ -#define RMT_CARRIER_HIGH_CH5 0x0000FFFF -#define RMT_CARRIER_HIGH_CH5_M ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S)) -#define RMT_CARRIER_HIGH_CH5_V 0xFFFF -#define RMT_CARRIER_HIGH_CH5_S 16 -/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel5.*/ -#define RMT_CARRIER_LOW_CH5 0x0000FFFF -#define RMT_CARRIER_LOW_CH5_M ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S)) -#define RMT_CARRIER_LOW_CH5_V 0xFFFF -#define RMT_CARRIER_LOW_CH5_S 0 - -#define RMT_CH6CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c8) -/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel6.*/ -#define RMT_CARRIER_HIGH_CH6 0x0000FFFF -#define RMT_CARRIER_HIGH_CH6_M ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S)) -#define RMT_CARRIER_HIGH_CH6_V 0xFFFF -#define RMT_CARRIER_HIGH_CH6_S 16 -/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel6.*/ -#define RMT_CARRIER_LOW_CH6 0x0000FFFF -#define RMT_CARRIER_LOW_CH6_M ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S)) -#define RMT_CARRIER_LOW_CH6_V 0xFFFF -#define RMT_CARRIER_LOW_CH6_S 0 - -#define RMT_CH7CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00cc) -/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel7.*/ -#define RMT_CARRIER_HIGH_CH7 0x0000FFFF -#define RMT_CARRIER_HIGH_CH7_M ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S)) -#define RMT_CARRIER_HIGH_CH7_V 0xFFFF -#define RMT_CARRIER_HIGH_CH7_S 16 -/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel7.*/ -#define RMT_CARRIER_LOW_CH7 0x0000FFFF -#define RMT_CARRIER_LOW_CH7_M ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S)) -#define RMT_CARRIER_LOW_CH7_V 0xFFFF -#define RMT_CARRIER_LOW_CH7_S 0 - -#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0) -/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH0 0x000001FF -#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) -#define RMT_TX_LIM_CH0_V 0x1FF -#define RMT_TX_LIM_CH0_S 0 - -#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4) -/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH1 0x000001FF -#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) -#define RMT_TX_LIM_CH1_V 0x1FF -#define RMT_TX_LIM_CH1_S 0 - -#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8) -/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH2 0x000001FF -#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S)) -#define RMT_TX_LIM_CH2_V 0x1FF -#define RMT_TX_LIM_CH2_S 0 - -#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc) -/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH3 0x000001FF -#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S)) -#define RMT_TX_LIM_CH3_V 0x1FF -#define RMT_TX_LIM_CH3_S 0 - -#define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0) -/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH4 0x000001FF -#define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S)) -#define RMT_TX_LIM_CH4_V 0x1FF -#define RMT_TX_LIM_CH4_S 0 - -#define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4) -/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH5 0x000001FF -#define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S)) -#define RMT_TX_LIM_CH5_V 0x1FF -#define RMT_TX_LIM_CH5_S 0 - -#define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8) -/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH6 0x000001FF -#define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S)) -#define RMT_TX_LIM_CH6_V 0x1FF -#define RMT_TX_LIM_CH6_S 0 - -#define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec) -/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH7 0x000001FF -#define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S)) -#define RMT_TX_LIM_CH7_V 0x1FF -#define RMT_TX_LIM_CH7_S 0 - -#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0) -/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: when datas need to be send is more than channel's mem can store - then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/ -#define RMT_MEM_TX_WRAP_EN (BIT(1)) -#define RMT_MEM_TX_WRAP_EN_M (BIT(1)) -#define RMT_MEM_TX_WRAP_EN_V 0x1 -#define RMT_MEM_TX_WRAP_EN_S 1 -/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to disable apb fifo access*/ -#define RMT_APB_FIFO_MASK (BIT(0)) -#define RMT_APB_FIFO_MASK_M (BIT(0)) -#define RMT_APB_FIFO_MASK_V 0x1 -#define RMT_APB_FIFO_MASK_S 0 - -#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00fc) -/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */ -/*description: This is the version register.*/ -#define RMT_DATE 0xFFFFFFFF -#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) -#define RMT_DATE_V 0xFFFFFFFF -#define RMT_DATE_S 0 - -/* RMT memory block address */ -#define RMT_CHANNEL_MEM(i) (DR_REG_RMT_BASE + 0x800 + 64 * 4 * (i)) - - -#endif /*_SOC_RMT_REG_H_ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RMT_REG_H_ +#define _SOC_RMT_REG_H_ + +#include "soc.h" +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) + +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) + +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) + +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) + +#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010) + +#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014) + +#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018) + +#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c) + +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020) +/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: This bit is used to control clock.when software config RMT + internal registers it controls the register clock.*/ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (BIT(31)) +#define RMT_CLK_EN_V 0x1 +#define RMT_CLK_EN_S 31 +/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/ +#define RMT_MEM_PD (BIT(30)) +#define RMT_MEM_PD_M (BIT(30)) +#define RMT_MEM_PD_V 0x1 +#define RMT_MEM_PD_S 30 +/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure the way carrier wave is modulated + for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH0_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH0_V 0x1 +#define RMT_CARRIER_OUT_LV_CH0_S 29 +/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel0.*/ +#define RMT_CARRIER_EN_CH0 (BIT(28)) +#define RMT_CARRIER_EN_CH0_M (BIT(28)) +#define RMT_CARRIER_EN_CH0_V 0x1 +#define RMT_CARRIER_EN_CH0_S 28 +/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel0.*/ +#define RMT_MEM_SIZE_CH0 0x0000000F +#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) +#define RMT_MEM_SIZE_CH0_V 0xF +#define RMT_MEM_SIZE_CH0_S 24 +/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when no edge is detected on the input signal + for longer than reg_idle_thres_ch0 then the receive process is done.*/ +#define RMT_IDLE_THRES_CH0 0x0000FFFF +#define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S)) +#define RMT_IDLE_THRES_CH0_V 0xFFFF +#define RMT_IDLE_THRES_CH0_S 8 +/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel0.*/ +#define RMT_DIV_CNT_CH0 0x000000FF +#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) +#define RMT_DIV_CNT_CH0_V 0xFF +#define RMT_DIV_CNT_CH0_S 0 + +#define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x0024) +/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel0 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH0 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH0_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH0_V 0x1 +#define RMT_IDLE_OUT_EN_CH0_S 19 +/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel0 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH0 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH0_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH0_V 0x1 +#define RMT_IDLE_OUT_LV_CH0_S 18 +/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH0_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH0_V 0x1 +#define RMT_REF_ALWAYS_ON_CH0_S 17 +/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel0.*/ +#define RMT_REF_CNT_RST_CH0 (BIT(16)) +#define RMT_REF_CNT_RST_CH0_M (BIT(16)) +#define RMT_REF_CNT_RST_CH0_V 0x1 +#define RMT_REF_CNT_RST_CH0_S 16 +/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel0 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH0 0x000000FF +#define RMT_RX_FILTER_THRES_CH0_M ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S)) +#define RMT_RX_FILTER_THRES_CH0_V 0xFF +#define RMT_RX_FILTER_THRES_CH0_S 8 +/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel0.*/ +#define RMT_RX_FILTER_EN_CH0 (BIT(7)) +#define RMT_RX_FILTER_EN_CH0_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH0_V 0x1 +#define RMT_RX_FILTER_EN_CH0_S 7 +/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel0 again and again.*/ +#define RMT_TX_CONTI_MODE_CH0 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH0_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH0_V 0x1 +#define RMT_TX_CONTI_MODE_CH0_S 6 +/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel0's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH0 (BIT(5)) +#define RMT_MEM_OWNER_CH0_M (BIT(5)) +#define RMT_MEM_OWNER_CH0_V 0x1 +#define RMT_MEM_OWNER_CH0_S 5 +/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH0 (BIT(4)) +#define RMT_APB_MEM_RST_CH0_M (BIT(4)) +#define RMT_APB_MEM_RST_CH0_V 0x1 +#define RMT_APB_MEM_RST_CH0_S 4 +/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH0 (BIT(3)) +#define RMT_MEM_RD_RST_CH0_M (BIT(3)) +#define RMT_MEM_RD_RST_CH0_V 0x1 +#define RMT_MEM_RD_RST_CH0_S 3 +/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel0 by receiver access.*/ +#define RMT_MEM_WR_RST_CH0 (BIT(2)) +#define RMT_MEM_WR_RST_CH0_M (BIT(2)) +#define RMT_MEM_WR_RST_CH0_V 0x1 +#define RMT_MEM_WR_RST_CH0_S 2 +/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel0.*/ +#define RMT_RX_EN_CH0 (BIT(1)) +#define RMT_RX_EN_CH0_M (BIT(1)) +#define RMT_RX_EN_CH0_V 0x1 +#define RMT_RX_EN_CH0_S 1 +/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel0.*/ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (BIT(0)) +#define RMT_TX_START_CH0_V 0x1 +#define RMT_TX_START_CH0_S 0 + +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0028) +/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure the way carrier wave is modulated + for channel1.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH1_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH1_V 0x1 +#define RMT_CARRIER_OUT_LV_CH1_S 29 +/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel1.*/ +#define RMT_CARRIER_EN_CH1 (BIT(28)) +#define RMT_CARRIER_EN_CH1_M (BIT(28)) +#define RMT_CARRIER_EN_CH1_V 0x1 +#define RMT_CARRIER_EN_CH1_S 28 +/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel1.*/ +#define RMT_MEM_SIZE_CH1 0x0000000F +#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) +#define RMT_MEM_SIZE_CH1_V 0xF +#define RMT_MEM_SIZE_CH1_S 24 +/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel1.*/ +#define RMT_IDLE_THRES_CH1 0x0000FFFF +#define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S)) +#define RMT_IDLE_THRES_CH1_V 0xFFFF +#define RMT_IDLE_THRES_CH1_S 8 +/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel1.*/ +#define RMT_DIV_CNT_CH1 0x000000FF +#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) +#define RMT_DIV_CNT_CH1_V 0xFF +#define RMT_DIV_CNT_CH1_S 0 + +#define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x002c) +/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel1 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH1 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH1_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH1_V 0x1 +#define RMT_IDLE_OUT_EN_CH1_S 19 +/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel1 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH1 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH1_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH1_V 0x1 +#define RMT_IDLE_OUT_LV_CH1_S 18 +/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH1 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH1_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH1_V 0x1 +#define RMT_REF_ALWAYS_ON_CH1_S 17 +/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel1.*/ +#define RMT_REF_CNT_RST_CH1 (BIT(16)) +#define RMT_REF_CNT_RST_CH1_M (BIT(16)) +#define RMT_REF_CNT_RST_CH1_V 0x1 +#define RMT_REF_CNT_RST_CH1_S 16 +/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel1 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH1 0x000000FF +#define RMT_RX_FILTER_THRES_CH1_M ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S)) +#define RMT_RX_FILTER_THRES_CH1_V 0xFF +#define RMT_RX_FILTER_THRES_CH1_S 8 +/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel1.*/ +#define RMT_RX_FILTER_EN_CH1 (BIT(7)) +#define RMT_RX_FILTER_EN_CH1_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH1_V 0x1 +#define RMT_RX_FILTER_EN_CH1_S 7 +/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel1 again and again.*/ +#define RMT_TX_CONTI_MODE_CH1 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH1_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH1_V 0x1 +#define RMT_TX_CONTI_MODE_CH1_S 6 +/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel1's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH1 (BIT(5)) +#define RMT_MEM_OWNER_CH1_M (BIT(5)) +#define RMT_MEM_OWNER_CH1_V 0x1 +#define RMT_MEM_OWNER_CH1_S 5 +/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH1 (BIT(4)) +#define RMT_APB_MEM_RST_CH1_M (BIT(4)) +#define RMT_APB_MEM_RST_CH1_V 0x1 +#define RMT_APB_MEM_RST_CH1_S 4 +/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH1 (BIT(3)) +#define RMT_MEM_RD_RST_CH1_M (BIT(3)) +#define RMT_MEM_RD_RST_CH1_V 0x1 +#define RMT_MEM_RD_RST_CH1_S 3 +/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel1 by receiver access.*/ +#define RMT_MEM_WR_RST_CH1 (BIT(2)) +#define RMT_MEM_WR_RST_CH1_M (BIT(2)) +#define RMT_MEM_WR_RST_CH1_V 0x1 +#define RMT_MEM_WR_RST_CH1_S 2 +/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel1.*/ +#define RMT_RX_EN_CH1 (BIT(1)) +#define RMT_RX_EN_CH1_M (BIT(1)) +#define RMT_RX_EN_CH1_V 0x1 +#define RMT_RX_EN_CH1_S 1 +/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel1.*/ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (BIT(0)) +#define RMT_TX_START_CH1_V 0x1 +#define RMT_TX_START_CH1_S 0 + +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0030) +/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_V 0x1 +#define RMT_CARRIER_OUT_LV_CH2_S 29 +/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel2.*/ +#define RMT_CARRIER_EN_CH2 (BIT(28)) +#define RMT_CARRIER_EN_CH2_M (BIT(28)) +#define RMT_CARRIER_EN_CH2_V 0x1 +#define RMT_CARRIER_EN_CH2_S 28 +/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel2.*/ +#define RMT_MEM_SIZE_CH2 0x0000000F +#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) +#define RMT_MEM_SIZE_CH2_V 0xF +#define RMT_MEM_SIZE_CH2_S 24 +/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH2 0x0000FFFF +#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S)) +#define RMT_IDLE_THRES_CH2_V 0xFFFF +#define RMT_IDLE_THRES_CH2_S 8 +/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel2.*/ +#define RMT_DIV_CNT_CH2 0x000000FF +#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) +#define RMT_DIV_CNT_CH2_V 0xFF +#define RMT_DIV_CNT_CH2_S 0 + +#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x0034) +/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel2 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH2 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH2_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH2_V 0x1 +#define RMT_IDLE_OUT_EN_CH2_S 19 +/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel2 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH2 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH2_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH2_V 0x1 +#define RMT_IDLE_OUT_LV_CH2_S 18 +/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH2 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH2_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH2_V 0x1 +#define RMT_REF_ALWAYS_ON_CH2_S 17 +/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel2.*/ +#define RMT_REF_CNT_RST_CH2 (BIT(16)) +#define RMT_REF_CNT_RST_CH2_M (BIT(16)) +#define RMT_REF_CNT_RST_CH2_V 0x1 +#define RMT_REF_CNT_RST_CH2_S 16 +/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel2 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH2 0x000000FF +#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S)) +#define RMT_RX_FILTER_THRES_CH2_V 0xFF +#define RMT_RX_FILTER_THRES_CH2_S 8 +/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel2.*/ +#define RMT_RX_FILTER_EN_CH2 (BIT(7)) +#define RMT_RX_FILTER_EN_CH2_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH2_V 0x1 +#define RMT_RX_FILTER_EN_CH2_S 7 +/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel2.*/ +#define RMT_TX_CONTI_MODE_CH2 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH2_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH2_V 0x1 +#define RMT_TX_CONTI_MODE_CH2_S 6 +/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel2's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH2 (BIT(5)) +#define RMT_MEM_OWNER_CH2_M (BIT(5)) +#define RMT_MEM_OWNER_CH2_V 0x1 +#define RMT_MEM_OWNER_CH2_S 5 +/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH2 (BIT(4)) +#define RMT_APB_MEM_RST_CH2_M (BIT(4)) +#define RMT_APB_MEM_RST_CH2_V 0x1 +#define RMT_APB_MEM_RST_CH2_S 4 +/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH2 (BIT(3)) +#define RMT_MEM_RD_RST_CH2_M (BIT(3)) +#define RMT_MEM_RD_RST_CH2_V 0x1 +#define RMT_MEM_RD_RST_CH2_S 3 +/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel2 by receiver access.*/ +#define RMT_MEM_WR_RST_CH2 (BIT(2)) +#define RMT_MEM_WR_RST_CH2_M (BIT(2)) +#define RMT_MEM_WR_RST_CH2_V 0x1 +#define RMT_MEM_WR_RST_CH2_S 2 +/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel2.*/ +#define RMT_RX_EN_CH2 (BIT(1)) +#define RMT_RX_EN_CH2_M (BIT(1)) +#define RMT_RX_EN_CH2_V 0x1 +#define RMT_RX_EN_CH2_S 1 +/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel2.*/ +#define RMT_TX_START_CH2 (BIT(0)) +#define RMT_TX_START_CH2_M (BIT(0)) +#define RMT_TX_START_CH2_V 0x1 +#define RMT_TX_START_CH2_S 0 + +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0038) +/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_V 0x1 +#define RMT_CARRIER_OUT_LV_CH3_S 29 +/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel3.*/ +#define RMT_CARRIER_EN_CH3 (BIT(28)) +#define RMT_CARRIER_EN_CH3_M (BIT(28)) +#define RMT_CARRIER_EN_CH3_V 0x1 +#define RMT_CARRIER_EN_CH3_S 28 +/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel3.*/ +#define RMT_MEM_SIZE_CH3 0x0000000F +#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) +#define RMT_MEM_SIZE_CH3_V 0xF +#define RMT_MEM_SIZE_CH3_S 24 +/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH3 0x0000FFFF +#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S)) +#define RMT_IDLE_THRES_CH3_V 0xFFFF +#define RMT_IDLE_THRES_CH3_S 8 +/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel3.*/ +#define RMT_DIV_CNT_CH3 0x000000FF +#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) +#define RMT_DIV_CNT_CH3_V 0xFF +#define RMT_DIV_CNT_CH3_S 0 + +#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x003c) +/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel3 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH3 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH3_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH3_V 0x1 +#define RMT_IDLE_OUT_EN_CH3_S 19 +/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel3 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH3 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH3_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH3_V 0x1 +#define RMT_IDLE_OUT_LV_CH3_S 18 +/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH3 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH3_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH3_V 0x1 +#define RMT_REF_ALWAYS_ON_CH3_S 17 +/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel3.*/ +#define RMT_REF_CNT_RST_CH3 (BIT(16)) +#define RMT_REF_CNT_RST_CH3_M (BIT(16)) +#define RMT_REF_CNT_RST_CH3_V 0x1 +#define RMT_REF_CNT_RST_CH3_S 16 +/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel3 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH3 0x000000FF +#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S)) +#define RMT_RX_FILTER_THRES_CH3_V 0xFF +#define RMT_RX_FILTER_THRES_CH3_S 8 +/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel3.*/ +#define RMT_RX_FILTER_EN_CH3 (BIT(7)) +#define RMT_RX_FILTER_EN_CH3_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH3_V 0x1 +#define RMT_RX_FILTER_EN_CH3_S 7 +/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel3.*/ +#define RMT_TX_CONTI_MODE_CH3 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH3_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH3_V 0x1 +#define RMT_TX_CONTI_MODE_CH3_S 6 +/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel3's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH3 (BIT(5)) +#define RMT_MEM_OWNER_CH3_M (BIT(5)) +#define RMT_MEM_OWNER_CH3_V 0x1 +#define RMT_MEM_OWNER_CH3_S 5 +/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH3 (BIT(4)) +#define RMT_APB_MEM_RST_CH3_M (BIT(4)) +#define RMT_APB_MEM_RST_CH3_V 0x1 +#define RMT_APB_MEM_RST_CH3_S 4 +/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH3 (BIT(3)) +#define RMT_MEM_RD_RST_CH3_M (BIT(3)) +#define RMT_MEM_RD_RST_CH3_V 0x1 +#define RMT_MEM_RD_RST_CH3_S 3 +/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel3 by receiver access.*/ +#define RMT_MEM_WR_RST_CH3 (BIT(2)) +#define RMT_MEM_WR_RST_CH3_M (BIT(2)) +#define RMT_MEM_WR_RST_CH3_V 0x1 +#define RMT_MEM_WR_RST_CH3_S 2 +/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel3.*/ +#define RMT_RX_EN_CH3 (BIT(1)) +#define RMT_RX_EN_CH3_M (BIT(1)) +#define RMT_RX_EN_CH3_V 0x1 +#define RMT_RX_EN_CH3_S 1 +/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel3.*/ +#define RMT_TX_START_CH3 (BIT(0)) +#define RMT_TX_START_CH3_M (BIT(0)) +#define RMT_TX_START_CH3_V 0x1 +#define RMT_TX_START_CH3_S 0 + +#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0040) +/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_V 0x1 +#define RMT_CARRIER_OUT_LV_CH4_S 29 +/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel4.*/ +#define RMT_CARRIER_EN_CH4 (BIT(28)) +#define RMT_CARRIER_EN_CH4_M (BIT(28)) +#define RMT_CARRIER_EN_CH4_V 0x1 +#define RMT_CARRIER_EN_CH4_S 28 +/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel4.*/ +#define RMT_MEM_SIZE_CH4 0x0000000F +#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S)) +#define RMT_MEM_SIZE_CH4_V 0xF +#define RMT_MEM_SIZE_CH4_S 24 +/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH4 0x0000FFFF +#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S)) +#define RMT_IDLE_THRES_CH4_V 0xFFFF +#define RMT_IDLE_THRES_CH4_S 8 +/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel4.*/ +#define RMT_DIV_CNT_CH4 0x000000FF +#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S)) +#define RMT_DIV_CNT_CH4_V 0xFF +#define RMT_DIV_CNT_CH4_S 0 + +#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0044) +/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel4 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH4 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH4_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH4_V 0x1 +#define RMT_IDLE_OUT_EN_CH4_S 19 +/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel4 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH4 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH4_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH4_V 0x1 +#define RMT_IDLE_OUT_LV_CH4_S 18 +/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH4 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH4_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH4_V 0x1 +#define RMT_REF_ALWAYS_ON_CH4_S 17 +/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel4.*/ +#define RMT_REF_CNT_RST_CH4 (BIT(16)) +#define RMT_REF_CNT_RST_CH4_M (BIT(16)) +#define RMT_REF_CNT_RST_CH4_V 0x1 +#define RMT_REF_CNT_RST_CH4_S 16 +/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel4 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH4 0x000000FF +#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S)) +#define RMT_RX_FILTER_THRES_CH4_V 0xFF +#define RMT_RX_FILTER_THRES_CH4_S 8 +/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel4.*/ +#define RMT_RX_FILTER_EN_CH4 (BIT(7)) +#define RMT_RX_FILTER_EN_CH4_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH4_V 0x1 +#define RMT_RX_FILTER_EN_CH4_S 7 +/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel4.*/ +#define RMT_TX_CONTI_MODE_CH4 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH4_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH4_V 0x1 +#define RMT_TX_CONTI_MODE_CH4_S 6 +/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel4's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH4 (BIT(5)) +#define RMT_MEM_OWNER_CH4_M (BIT(5)) +#define RMT_MEM_OWNER_CH4_V 0x1 +#define RMT_MEM_OWNER_CH4_S 5 +/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH4 (BIT(4)) +#define RMT_APB_MEM_RST_CH4_M (BIT(4)) +#define RMT_APB_MEM_RST_CH4_V 0x1 +#define RMT_APB_MEM_RST_CH4_S 4 +/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH4 (BIT(3)) +#define RMT_MEM_RD_RST_CH4_M (BIT(3)) +#define RMT_MEM_RD_RST_CH4_V 0x1 +#define RMT_MEM_RD_RST_CH4_S 3 +/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel4 by receiver access.*/ +#define RMT_MEM_WR_RST_CH4 (BIT(2)) +#define RMT_MEM_WR_RST_CH4_M (BIT(2)) +#define RMT_MEM_WR_RST_CH4_V 0x1 +#define RMT_MEM_WR_RST_CH4_S 2 +/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel4.*/ +#define RMT_RX_EN_CH4 (BIT(1)) +#define RMT_RX_EN_CH4_M (BIT(1)) +#define RMT_RX_EN_CH4_V 0x1 +#define RMT_RX_EN_CH4_S 1 +/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel4.*/ +#define RMT_TX_START_CH4 (BIT(0)) +#define RMT_TX_START_CH4_M (BIT(0)) +#define RMT_TX_START_CH4_V 0x1 +#define RMT_TX_START_CH4_S 0 + +#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0048) +/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_V 0x1 +#define RMT_CARRIER_OUT_LV_CH5_S 29 +/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel5.*/ +#define RMT_CARRIER_EN_CH5 (BIT(28)) +#define RMT_CARRIER_EN_CH5_M (BIT(28)) +#define RMT_CARRIER_EN_CH5_V 0x1 +#define RMT_CARRIER_EN_CH5_S 28 +/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel5.*/ +#define RMT_MEM_SIZE_CH5 0x0000000F +#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S)) +#define RMT_MEM_SIZE_CH5_V 0xF +#define RMT_MEM_SIZE_CH5_S 24 +/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH5 0x0000FFFF +#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S)) +#define RMT_IDLE_THRES_CH5_V 0xFFFF +#define RMT_IDLE_THRES_CH5_S 8 +/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel5.*/ +#define RMT_DIV_CNT_CH5 0x000000FF +#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S)) +#define RMT_DIV_CNT_CH5_V 0xFF +#define RMT_DIV_CNT_CH5_S 0 + +#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x004c) +/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel5 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH5 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH5_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH5_V 0x1 +#define RMT_IDLE_OUT_EN_CH5_S 19 +/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel5 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH5 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH5_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH5_V 0x1 +#define RMT_IDLE_OUT_LV_CH5_S 18 +/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH5 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH5_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH5_V 0x1 +#define RMT_REF_ALWAYS_ON_CH5_S 17 +/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel5.*/ +#define RMT_REF_CNT_RST_CH5 (BIT(16)) +#define RMT_REF_CNT_RST_CH5_M (BIT(16)) +#define RMT_REF_CNT_RST_CH5_V 0x1 +#define RMT_REF_CNT_RST_CH5_S 16 +/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel5 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH5 0x000000FF +#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S)) +#define RMT_RX_FILTER_THRES_CH5_V 0xFF +#define RMT_RX_FILTER_THRES_CH5_S 8 +/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel5.*/ +#define RMT_RX_FILTER_EN_CH5 (BIT(7)) +#define RMT_RX_FILTER_EN_CH5_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH5_V 0x1 +#define RMT_RX_FILTER_EN_CH5_S 7 +/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel5.*/ +#define RMT_TX_CONTI_MODE_CH5 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH5_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH5_V 0x1 +#define RMT_TX_CONTI_MODE_CH5_S 6 +/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel5's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH5 (BIT(5)) +#define RMT_MEM_OWNER_CH5_M (BIT(5)) +#define RMT_MEM_OWNER_CH5_V 0x1 +#define RMT_MEM_OWNER_CH5_S 5 +/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH5 (BIT(4)) +#define RMT_APB_MEM_RST_CH5_M (BIT(4)) +#define RMT_APB_MEM_RST_CH5_V 0x1 +#define RMT_APB_MEM_RST_CH5_S 4 +/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH5 (BIT(3)) +#define RMT_MEM_RD_RST_CH5_M (BIT(3)) +#define RMT_MEM_RD_RST_CH5_V 0x1 +#define RMT_MEM_RD_RST_CH5_S 3 +/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel5 by receiver access.*/ +#define RMT_MEM_WR_RST_CH5 (BIT(2)) +#define RMT_MEM_WR_RST_CH5_M (BIT(2)) +#define RMT_MEM_WR_RST_CH5_V 0x1 +#define RMT_MEM_WR_RST_CH5_S 2 +/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel5.*/ +#define RMT_RX_EN_CH5 (BIT(1)) +#define RMT_RX_EN_CH5_M (BIT(1)) +#define RMT_RX_EN_CH5_V 0x1 +#define RMT_RX_EN_CH5_S 1 +/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel5.*/ +#define RMT_TX_START_CH5 (BIT(0)) +#define RMT_TX_START_CH5_M (BIT(0)) +#define RMT_TX_START_CH5_V 0x1 +#define RMT_TX_START_CH5_S 0 + +#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0050) +/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_V 0x1 +#define RMT_CARRIER_OUT_LV_CH6_S 29 +/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel6.*/ +#define RMT_CARRIER_EN_CH6 (BIT(28)) +#define RMT_CARRIER_EN_CH6_M (BIT(28)) +#define RMT_CARRIER_EN_CH6_V 0x1 +#define RMT_CARRIER_EN_CH6_S 28 +/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel6.*/ +#define RMT_MEM_SIZE_CH6 0x0000000F +#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S)) +#define RMT_MEM_SIZE_CH6_V 0xF +#define RMT_MEM_SIZE_CH6_S 24 +/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH6 0x0000FFFF +#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S)) +#define RMT_IDLE_THRES_CH6_V 0xFFFF +#define RMT_IDLE_THRES_CH6_S 8 +/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel6.*/ +#define RMT_DIV_CNT_CH6 0x000000FF +#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S)) +#define RMT_DIV_CNT_CH6_V 0xFF +#define RMT_DIV_CNT_CH6_S 0 + +#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0054) +/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH6 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH6_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH6_V 0x1 +#define RMT_IDLE_OUT_EN_CH6_S 19 +/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH6 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH6_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH6_V 0x1 +#define RMT_IDLE_OUT_LV_CH6_S 18 +/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH6 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH6_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH6_V 0x1 +#define RMT_REF_ALWAYS_ON_CH6_S 17 +/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel6.*/ +#define RMT_REF_CNT_RST_CH6 (BIT(16)) +#define RMT_REF_CNT_RST_CH6_M (BIT(16)) +#define RMT_REF_CNT_RST_CH6_V 0x1 +#define RMT_REF_CNT_RST_CH6_S 16 +/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel6 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH6 0x000000FF +#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S)) +#define RMT_RX_FILTER_THRES_CH6_V 0xFF +#define RMT_RX_FILTER_THRES_CH6_S 8 +/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel6.*/ +#define RMT_RX_FILTER_EN_CH6 (BIT(7)) +#define RMT_RX_FILTER_EN_CH6_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH6_V 0x1 +#define RMT_RX_FILTER_EN_CH6_S 7 +/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel6.*/ +#define RMT_TX_CONTI_MODE_CH6 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH6_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH6_V 0x1 +#define RMT_TX_CONTI_MODE_CH6_S 6 +/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel6's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH6 (BIT(5)) +#define RMT_MEM_OWNER_CH6_M (BIT(5)) +#define RMT_MEM_OWNER_CH6_V 0x1 +#define RMT_MEM_OWNER_CH6_S 5 +/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH6 (BIT(4)) +#define RMT_APB_MEM_RST_CH6_M (BIT(4)) +#define RMT_APB_MEM_RST_CH6_V 0x1 +#define RMT_APB_MEM_RST_CH6_S 4 +/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH6 (BIT(3)) +#define RMT_MEM_RD_RST_CH6_M (BIT(3)) +#define RMT_MEM_RD_RST_CH6_V 0x1 +#define RMT_MEM_RD_RST_CH6_S 3 +/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel6 by receiver access.*/ +#define RMT_MEM_WR_RST_CH6 (BIT(2)) +#define RMT_MEM_WR_RST_CH6_M (BIT(2)) +#define RMT_MEM_WR_RST_CH6_V 0x1 +#define RMT_MEM_WR_RST_CH6_S 2 +/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel6.*/ +#define RMT_RX_EN_CH6 (BIT(1)) +#define RMT_RX_EN_CH6_M (BIT(1)) +#define RMT_RX_EN_CH6_V 0x1 +#define RMT_RX_EN_CH6_S 1 +/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel6.*/ +#define RMT_TX_START_CH6 (BIT(0)) +#define RMT_TX_START_CH6_M (BIT(0)) +#define RMT_TX_START_CH6_V 0x1 +#define RMT_TX_START_CH6_S 0 + +#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0058) +/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_V 0x1 +#define RMT_CARRIER_OUT_LV_CH7_S 29 +/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel7.*/ +#define RMT_CARRIER_EN_CH7 (BIT(28)) +#define RMT_CARRIER_EN_CH7_M (BIT(28)) +#define RMT_CARRIER_EN_CH7_V 0x1 +#define RMT_CARRIER_EN_CH7_S 28 +/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel7.*/ +#define RMT_MEM_SIZE_CH7 0x0000000F +#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S)) +#define RMT_MEM_SIZE_CH7_V 0xF +#define RMT_MEM_SIZE_CH7_S 24 +/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH7 0x0000FFFF +#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S)) +#define RMT_IDLE_THRES_CH7_V 0xFFFF +#define RMT_IDLE_THRES_CH7_S 8 +/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel7.*/ +#define RMT_DIV_CNT_CH7 0x000000FF +#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S)) +#define RMT_DIV_CNT_CH7_V 0xFF +#define RMT_DIV_CNT_CH7_S 0 + +#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x005c) +/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH7 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH7_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH7_V 0x1 +#define RMT_IDLE_OUT_EN_CH7_S 19 +/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel7 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH7 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH7_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH7_V 0x1 +#define RMT_IDLE_OUT_LV_CH7_S 18 +/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH7 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH7_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH7_V 0x1 +#define RMT_REF_ALWAYS_ON_CH7_S 17 +/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel7.*/ +#define RMT_REF_CNT_RST_CH7 (BIT(16)) +#define RMT_REF_CNT_RST_CH7_M (BIT(16)) +#define RMT_REF_CNT_RST_CH7_V 0x1 +#define RMT_REF_CNT_RST_CH7_S 16 +/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel7 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH7 0x000000FF +#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S)) +#define RMT_RX_FILTER_THRES_CH7_V 0xFF +#define RMT_RX_FILTER_THRES_CH7_S 8 +/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel7.*/ +#define RMT_RX_FILTER_EN_CH7 (BIT(7)) +#define RMT_RX_FILTER_EN_CH7_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH7_V 0x1 +#define RMT_RX_FILTER_EN_CH7_S 7 +/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel7.*/ +#define RMT_TX_CONTI_MODE_CH7 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH7_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH7_V 0x1 +#define RMT_TX_CONTI_MODE_CH7_S 6 +/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel7's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH7 (BIT(5)) +#define RMT_MEM_OWNER_CH7_M (BIT(5)) +#define RMT_MEM_OWNER_CH7_V 0x1 +#define RMT_MEM_OWNER_CH7_S 5 +/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH7 (BIT(4)) +#define RMT_APB_MEM_RST_CH7_M (BIT(4)) +#define RMT_APB_MEM_RST_CH7_V 0x1 +#define RMT_APB_MEM_RST_CH7_S 4 +/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH7 (BIT(3)) +#define RMT_MEM_RD_RST_CH7_M (BIT(3)) +#define RMT_MEM_RD_RST_CH7_V 0x1 +#define RMT_MEM_RD_RST_CH7_S 3 +/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel7 by receiver access.*/ +#define RMT_MEM_WR_RST_CH7 (BIT(2)) +#define RMT_MEM_WR_RST_CH7_M (BIT(2)) +#define RMT_MEM_WR_RST_CH7_V 0x1 +#define RMT_MEM_WR_RST_CH7_S 2 +/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel7.*/ +#define RMT_RX_EN_CH7 (BIT(1)) +#define RMT_RX_EN_CH7_M (BIT(1)) +#define RMT_RX_EN_CH7_V 0x1 +#define RMT_RX_EN_CH7_S 1 +/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel7.*/ +#define RMT_TX_START_CH7 (BIT(0)) +#define RMT_TX_START_CH7_M (BIT(0)) +#define RMT_TX_START_CH7_V 0x1 +#define RMT_TX_START_CH7_S 0 + +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0060) +/* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel0*/ +#define RMT_STATUS_CH0 0xFFFFFFFF +#define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S)) +#define RMT_STATUS_CH0_V 0xFFFFFFFF +#define RMT_STATUS_CH0_S 0 + +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064) +/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel1*/ +#define RMT_STATUS_CH1 0xFFFFFFFF +#define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S)) +#define RMT_STATUS_CH1_V 0xFFFFFFFF +#define RMT_STATUS_CH1_S 0 + +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068) +/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel2*/ +#define RMT_STATUS_CH2 0xFFFFFFFF +#define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S)) +#define RMT_STATUS_CH2_V 0xFFFFFFFF +#define RMT_STATUS_CH2_S 0 + +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c) +/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel3*/ +#define RMT_STATUS_CH3 0xFFFFFFFF +#define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S)) +#define RMT_STATUS_CH3_V 0xFFFFFFFF +#define RMT_STATUS_CH3_S 0 + +#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070) +/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel4*/ +#define RMT_STATUS_CH4 0xFFFFFFFF +#define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S)) +#define RMT_STATUS_CH4_V 0xFFFFFFFF +#define RMT_STATUS_CH4_S 0 + +#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074) +/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel5*/ +#define RMT_STATUS_CH5 0xFFFFFFFF +#define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S)) +#define RMT_STATUS_CH5_V 0xFFFFFFFF +#define RMT_STATUS_CH5_S 0 + +#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078) +/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel6*/ +#define RMT_STATUS_CH6 0xFFFFFFFF +#define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S)) +#define RMT_STATUS_CH6_V 0xFFFFFFFF +#define RMT_STATUS_CH6_S 0 + +#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c) +/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel7*/ +#define RMT_STATUS_CH7 0xFFFFFFFF +#define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S)) +#define RMT_STATUS_CH7_V 0xFFFFFFFF +#define RMT_STATUS_CH7_S 0 + +#define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080) +/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel0 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH0 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH0_M ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S)) +#define RMT_APB_MEM_ADDR_CH0_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH0_S 0 + +#define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x0084) +/* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel1 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH1 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH1_M ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S)) +#define RMT_APB_MEM_ADDR_CH1_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH1_S 0 + +#define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x0088) +/* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel2 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH2 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH2_M ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S)) +#define RMT_APB_MEM_ADDR_CH2_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH2_S 0 + +#define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x008c) +/* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel3 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH3 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH3_M ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S)) +#define RMT_APB_MEM_ADDR_CH3_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH3_S 0 + +#define RMT_CH4ADDR_REG (DR_REG_RMT_BASE + 0x0090) +/* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel4 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH4 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH4_M ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S)) +#define RMT_APB_MEM_ADDR_CH4_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH4_S 0 + +#define RMT_CH5ADDR_REG (DR_REG_RMT_BASE + 0x0094) +/* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel5 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH5 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH5_M ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S)) +#define RMT_APB_MEM_ADDR_CH5_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH5_S 0 + +#define RMT_CH6ADDR_REG (DR_REG_RMT_BASE + 0x0098) +/* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel6 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH6 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH6_M ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S)) +#define RMT_APB_MEM_ADDR_CH6_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH6_S 0 + +#define RMT_CH7ADDR_REG (DR_REG_RMT_BASE + 0x009c) +/* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel7 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH7 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH7_M ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S)) +#define RMT_APB_MEM_ADDR_CH7_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH7_S 0 + +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0) +/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + transmitter in channle7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24 +/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + channle 7 detects some errors.*/ +#define RMT_CH7_ERR_INT_RAW (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_V 0x1 +#define RMT_CH7_ERR_INT_RAW_S 23 +/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + the receive process is done.*/ +#define RMT_CH7_RX_END_INT_RAW (BIT(22)) +#define RMT_CH7_RX_END_INT_RAW_M (BIT(22)) +#define RMT_CH7_RX_END_INT_RAW_V 0x1 +#define RMT_CH7_RX_END_INT_RAW_S 22 +/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + the transmit process is done.*/ +#define RMT_CH7_TX_END_INT_RAW (BIT(21)) +#define RMT_CH7_TX_END_INT_RAW_M (BIT(21)) +#define RMT_CH7_TX_END_INT_RAW_V 0x1 +#define RMT_CH7_TX_END_INT_RAW_S 21 +/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + channle 6 detects some errors.*/ +#define RMT_CH6_ERR_INT_RAW (BIT(20)) +#define RMT_CH6_ERR_INT_RAW_M (BIT(20)) +#define RMT_CH6_ERR_INT_RAW_V 0x1 +#define RMT_CH6_ERR_INT_RAW_S 20 +/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + the receive process is done.*/ +#define RMT_CH6_RX_END_INT_RAW (BIT(19)) +#define RMT_CH6_RX_END_INT_RAW_M (BIT(19)) +#define RMT_CH6_RX_END_INT_RAW_V 0x1 +#define RMT_CH6_RX_END_INT_RAW_S 19 +/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + the transmit process is done.*/ +#define RMT_CH6_TX_END_INT_RAW (BIT(18)) +#define RMT_CH6_TX_END_INT_RAW_M (BIT(18)) +#define RMT_CH6_TX_END_INT_RAW_V 0x1 +#define RMT_CH6_TX_END_INT_RAW_S 18 +/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + channle 5 detects some errors.*/ +#define RMT_CH5_ERR_INT_RAW (BIT(17)) +#define RMT_CH5_ERR_INT_RAW_M (BIT(17)) +#define RMT_CH5_ERR_INT_RAW_V 0x1 +#define RMT_CH5_ERR_INT_RAW_S 17 +/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + the receive process is done.*/ +#define RMT_CH5_RX_END_INT_RAW (BIT(16)) +#define RMT_CH5_RX_END_INT_RAW_M (BIT(16)) +#define RMT_CH5_RX_END_INT_RAW_V 0x1 +#define RMT_CH5_RX_END_INT_RAW_S 16 +/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + the transmit process is done.*/ +#define RMT_CH5_TX_END_INT_RAW (BIT(15)) +#define RMT_CH5_TX_END_INT_RAW_M (BIT(15)) +#define RMT_CH5_TX_END_INT_RAW_V 0x1 +#define RMT_CH5_TX_END_INT_RAW_S 15 +/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + channle 4 detects some errors.*/ +#define RMT_CH4_ERR_INT_RAW (BIT(14)) +#define RMT_CH4_ERR_INT_RAW_M (BIT(14)) +#define RMT_CH4_ERR_INT_RAW_V 0x1 +#define RMT_CH4_ERR_INT_RAW_S 14 +/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + the receive process is done.*/ +#define RMT_CH4_RX_END_INT_RAW (BIT(13)) +#define RMT_CH4_RX_END_INT_RAW_M (BIT(13)) +#define RMT_CH4_RX_END_INT_RAW_V 0x1 +#define RMT_CH4_RX_END_INT_RAW_S 13 +/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + the transmit process is done.*/ +#define RMT_CH4_TX_END_INT_RAW (BIT(12)) +#define RMT_CH4_TX_END_INT_RAW_M (BIT(12)) +#define RMT_CH4_TX_END_INT_RAW_V 0x1 +#define RMT_CH4_TX_END_INT_RAW_S 12 +/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + channle 3 detects some errors.*/ +#define RMT_CH3_ERR_INT_RAW (BIT(11)) +#define RMT_CH3_ERR_INT_RAW_M (BIT(11)) +#define RMT_CH3_ERR_INT_RAW_V 0x1 +#define RMT_CH3_ERR_INT_RAW_S 11 +/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + the receive process is done.*/ +#define RMT_CH3_RX_END_INT_RAW (BIT(10)) +#define RMT_CH3_RX_END_INT_RAW_M (BIT(10)) +#define RMT_CH3_RX_END_INT_RAW_V 0x1 +#define RMT_CH3_RX_END_INT_RAW_S 10 +/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + the transmit process is done.*/ +#define RMT_CH3_TX_END_INT_RAW (BIT(9)) +#define RMT_CH3_TX_END_INT_RAW_M (BIT(9)) +#define RMT_CH3_TX_END_INT_RAW_V 0x1 +#define RMT_CH3_TX_END_INT_RAW_S 9 +/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + channle 2 detects some errors.*/ +#define RMT_CH2_ERR_INT_RAW (BIT(8)) +#define RMT_CH2_ERR_INT_RAW_M (BIT(8)) +#define RMT_CH2_ERR_INT_RAW_V 0x1 +#define RMT_CH2_ERR_INT_RAW_S 8 +/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + the receive process is done.*/ +#define RMT_CH2_RX_END_INT_RAW (BIT(7)) +#define RMT_CH2_RX_END_INT_RAW_M (BIT(7)) +#define RMT_CH2_RX_END_INT_RAW_V 0x1 +#define RMT_CH2_RX_END_INT_RAW_S 7 +/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + the transmit process is done.*/ +#define RMT_CH2_TX_END_INT_RAW (BIT(6)) +#define RMT_CH2_TX_END_INT_RAW_M (BIT(6)) +#define RMT_CH2_TX_END_INT_RAW_V 0x1 +#define RMT_CH2_TX_END_INT_RAW_S 6 +/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + channle 1 detects some errors.*/ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_V 0x1 +#define RMT_CH1_ERR_INT_RAW_S 5 +/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + the receive process is done.*/ +#define RMT_CH1_RX_END_INT_RAW (BIT(4)) +#define RMT_CH1_RX_END_INT_RAW_M (BIT(4)) +#define RMT_CH1_RX_END_INT_RAW_V 0x1 +#define RMT_CH1_RX_END_INT_RAW_S 4 +/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + the transmit process is done.*/ +#define RMT_CH1_TX_END_INT_RAW (BIT(3)) +#define RMT_CH1_TX_END_INT_RAW_M (BIT(3)) +#define RMT_CH1_TX_END_INT_RAW_V 0x1 +#define RMT_CH1_TX_END_INT_RAW_S 3 +/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + channle 0 detects some errors.*/ +#define RMT_CH0_ERR_INT_RAW (BIT(2)) +#define RMT_CH0_ERR_INT_RAW_M (BIT(2)) +#define RMT_CH0_ERR_INT_RAW_V 0x1 +#define RMT_CH0_ERR_INT_RAW_S 2 +/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + the receive process is done.*/ +#define RMT_CH0_RX_END_INT_RAW (BIT(1)) +#define RMT_CH0_RX_END_INT_RAW_M (BIT(1)) +#define RMT_CH0_RX_END_INT_RAW_V 0x1 +#define RMT_CH0_RX_END_INT_RAW_S 1 +/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + the transmit process is done.*/ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_V 0x1 +#define RMT_CH0_TX_END_INT_RAW_S 0 + +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x00a4) +/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw + when mt_ch7_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH7_TX_THR_EVENT_INT_ST (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ST_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_ST_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw + when mt_ch6_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH6_TX_THR_EVENT_INT_ST (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ST_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_ST_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw + when mt_ch5_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH5_TX_THR_EVENT_INT_ST (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ST_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_ST_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw + when mt_ch4_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH4_TX_THR_EVENT_INT_ST (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ST_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_ST_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw + when mt_ch3_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ST_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw + when mt_ch2_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ST_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw + when mt_ch1_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw + when mt_ch0_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 24 +/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_err_int_raw + when rmt_ch7_err_int_ena is set to 1.*/ +#define RMT_CH7_ERR_INT_ST (BIT(23)) +#define RMT_CH7_ERR_INT_ST_M (BIT(23)) +#define RMT_CH7_ERR_INT_ST_V 0x1 +#define RMT_CH7_ERR_INT_ST_S 23 +/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw + when rmt_ch7_rx_end_int_ena is set to 1.*/ +#define RMT_CH7_RX_END_INT_ST (BIT(22)) +#define RMT_CH7_RX_END_INT_ST_M (BIT(22)) +#define RMT_CH7_RX_END_INT_ST_V 0x1 +#define RMT_CH7_RX_END_INT_ST_S 22 +/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw + when mt_ch7_tx_end_int_ena is set to 1.*/ +#define RMT_CH7_TX_END_INT_ST (BIT(21)) +#define RMT_CH7_TX_END_INT_ST_M (BIT(21)) +#define RMT_CH7_TX_END_INT_ST_V 0x1 +#define RMT_CH7_TX_END_INT_ST_S 21 +/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_err_int_raw + when rmt_ch6_err_int_ena is set to 1.*/ +#define RMT_CH6_ERR_INT_ST (BIT(20)) +#define RMT_CH6_ERR_INT_ST_M (BIT(20)) +#define RMT_CH6_ERR_INT_ST_V 0x1 +#define RMT_CH6_ERR_INT_ST_S 20 +/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw + when rmt_ch6_rx_end_int_ena is set to 1.*/ +#define RMT_CH6_RX_END_INT_ST (BIT(19)) +#define RMT_CH6_RX_END_INT_ST_M (BIT(19)) +#define RMT_CH6_RX_END_INT_ST_V 0x1 +#define RMT_CH6_RX_END_INT_ST_S 19 +/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw + when mt_ch6_tx_end_int_ena is set to 1.*/ +#define RMT_CH6_TX_END_INT_ST (BIT(18)) +#define RMT_CH6_TX_END_INT_ST_M (BIT(18)) +#define RMT_CH6_TX_END_INT_ST_V 0x1 +#define RMT_CH6_TX_END_INT_ST_S 18 +/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_err_int_raw + when rmt_ch5_err_int_ena is set to 1.*/ +#define RMT_CH5_ERR_INT_ST (BIT(17)) +#define RMT_CH5_ERR_INT_ST_M (BIT(17)) +#define RMT_CH5_ERR_INT_ST_V 0x1 +#define RMT_CH5_ERR_INT_ST_S 17 +/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw + when rmt_ch5_rx_end_int_ena is set to 1.*/ +#define RMT_CH5_RX_END_INT_ST (BIT(16)) +#define RMT_CH5_RX_END_INT_ST_M (BIT(16)) +#define RMT_CH5_RX_END_INT_ST_V 0x1 +#define RMT_CH5_RX_END_INT_ST_S 16 +/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw + when mt_ch5_tx_end_int_ena is set to 1.*/ +#define RMT_CH5_TX_END_INT_ST (BIT(15)) +#define RMT_CH5_TX_END_INT_ST_M (BIT(15)) +#define RMT_CH5_TX_END_INT_ST_V 0x1 +#define RMT_CH5_TX_END_INT_ST_S 15 +/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_err_int_raw + when rmt_ch4_err_int_ena is set to 1.*/ +#define RMT_CH4_ERR_INT_ST (BIT(14)) +#define RMT_CH4_ERR_INT_ST_M (BIT(14)) +#define RMT_CH4_ERR_INT_ST_V 0x1 +#define RMT_CH4_ERR_INT_ST_S 14 +/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw + when rmt_ch4_rx_end_int_ena is set to 1.*/ +#define RMT_CH4_RX_END_INT_ST (BIT(13)) +#define RMT_CH4_RX_END_INT_ST_M (BIT(13)) +#define RMT_CH4_RX_END_INT_ST_V 0x1 +#define RMT_CH4_RX_END_INT_ST_S 13 +/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw + when mt_ch4_tx_end_int_ena is set to 1.*/ +#define RMT_CH4_TX_END_INT_ST (BIT(12)) +#define RMT_CH4_TX_END_INT_ST_M (BIT(12)) +#define RMT_CH4_TX_END_INT_ST_V 0x1 +#define RMT_CH4_TX_END_INT_ST_S 12 +/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_err_int_raw + when rmt_ch3_err_int_ena is set to 1.*/ +#define RMT_CH3_ERR_INT_ST (BIT(11)) +#define RMT_CH3_ERR_INT_ST_M (BIT(11)) +#define RMT_CH3_ERR_INT_ST_V 0x1 +#define RMT_CH3_ERR_INT_ST_S 11 +/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw + when rmt_ch3_rx_end_int_ena is set to 1.*/ +#define RMT_CH3_RX_END_INT_ST (BIT(10)) +#define RMT_CH3_RX_END_INT_ST_M (BIT(10)) +#define RMT_CH3_RX_END_INT_ST_V 0x1 +#define RMT_CH3_RX_END_INT_ST_S 10 +/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw + when mt_ch3_tx_end_int_ena is set to 1.*/ +#define RMT_CH3_TX_END_INT_ST (BIT(9)) +#define RMT_CH3_TX_END_INT_ST_M (BIT(9)) +#define RMT_CH3_TX_END_INT_ST_V 0x1 +#define RMT_CH3_TX_END_INT_ST_S 9 +/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_err_int_raw + when rmt_ch2_err_int_ena is set to 1.*/ +#define RMT_CH2_ERR_INT_ST (BIT(8)) +#define RMT_CH2_ERR_INT_ST_M (BIT(8)) +#define RMT_CH2_ERR_INT_ST_V 0x1 +#define RMT_CH2_ERR_INT_ST_S 8 +/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw + when rmt_ch2_rx_end_int_ena is set to 1.*/ +#define RMT_CH2_RX_END_INT_ST (BIT(7)) +#define RMT_CH2_RX_END_INT_ST_M (BIT(7)) +#define RMT_CH2_RX_END_INT_ST_V 0x1 +#define RMT_CH2_RX_END_INT_ST_S 7 +/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw + when mt_ch2_tx_end_int_ena is set to 1.*/ +#define RMT_CH2_TX_END_INT_ST (BIT(6)) +#define RMT_CH2_TX_END_INT_ST_M (BIT(6)) +#define RMT_CH2_TX_END_INT_ST_V 0x1 +#define RMT_CH2_TX_END_INT_ST_S 6 +/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_err_int_raw + when rmt_ch1_err_int_ena is set to 1.*/ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (BIT(5)) +#define RMT_CH1_ERR_INT_ST_V 0x1 +#define RMT_CH1_ERR_INT_ST_S 5 +/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw + when rmt_ch1_rx_end_int_ena is set to 1.*/ +#define RMT_CH1_RX_END_INT_ST (BIT(4)) +#define RMT_CH1_RX_END_INT_ST_M (BIT(4)) +#define RMT_CH1_RX_END_INT_ST_V 0x1 +#define RMT_CH1_RX_END_INT_ST_S 4 +/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw + when mt_ch1_tx_end_int_ena is set to 1.*/ +#define RMT_CH1_TX_END_INT_ST (BIT(3)) +#define RMT_CH1_TX_END_INT_ST_M (BIT(3)) +#define RMT_CH1_TX_END_INT_ST_V 0x1 +#define RMT_CH1_TX_END_INT_ST_S 3 +/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_err_int_raw + when rmt_ch0_err_int_ena is set to 0.*/ +#define RMT_CH0_ERR_INT_ST (BIT(2)) +#define RMT_CH0_ERR_INT_ST_M (BIT(2)) +#define RMT_CH0_ERR_INT_ST_V 0x1 +#define RMT_CH0_ERR_INT_ST_S 2 +/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw + when rmt_ch0_rx_end_int_ena is set to 0.*/ +#define RMT_CH0_RX_END_INT_ST (BIT(1)) +#define RMT_CH0_RX_END_INT_ST_M (BIT(1)) +#define RMT_CH0_RX_END_INT_ST_V 0x1 +#define RMT_CH0_RX_END_INT_ST_S 1 +/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw + when mt_ch0_tx_end_int_ena is set to 0.*/ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_V 0x1 +#define RMT_CH0_TX_END_INT_ST_S 0 + +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x00a8) +/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ +#define RMT_CH7_TX_THR_EVENT_INT_ENA (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ENA_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_ENA_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ +#define RMT_CH6_TX_THR_EVENT_INT_ENA (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ENA_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_ENA_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ +#define RMT_CH5_TX_THR_EVENT_INT_ENA (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ENA_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_ENA_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ +#define RMT_CH4_TX_THR_EVENT_INT_ENA (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ENA_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_ENA_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ +#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ +#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 24 +/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_err_int_st.*/ +#define RMT_CH7_ERR_INT_ENA (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_V 0x1 +#define RMT_CH7_ERR_INT_ENA_S 23 +/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/ +#define RMT_CH7_RX_END_INT_ENA (BIT(22)) +#define RMT_CH7_RX_END_INT_ENA_M (BIT(22)) +#define RMT_CH7_RX_END_INT_ENA_V 0x1 +#define RMT_CH7_RX_END_INT_ENA_S 22 +/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/ +#define RMT_CH7_TX_END_INT_ENA (BIT(21)) +#define RMT_CH7_TX_END_INT_ENA_M (BIT(21)) +#define RMT_CH7_TX_END_INT_ENA_V 0x1 +#define RMT_CH7_TX_END_INT_ENA_S 21 +/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_err_int_st.*/ +#define RMT_CH6_ERR_INT_ENA (BIT(20)) +#define RMT_CH6_ERR_INT_ENA_M (BIT(20)) +#define RMT_CH6_ERR_INT_ENA_V 0x1 +#define RMT_CH6_ERR_INT_ENA_S 20 +/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/ +#define RMT_CH6_RX_END_INT_ENA (BIT(19)) +#define RMT_CH6_RX_END_INT_ENA_M (BIT(19)) +#define RMT_CH6_RX_END_INT_ENA_V 0x1 +#define RMT_CH6_RX_END_INT_ENA_S 19 +/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/ +#define RMT_CH6_TX_END_INT_ENA (BIT(18)) +#define RMT_CH6_TX_END_INT_ENA_M (BIT(18)) +#define RMT_CH6_TX_END_INT_ENA_V 0x1 +#define RMT_CH6_TX_END_INT_ENA_S 18 +/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_err_int_st.*/ +#define RMT_CH5_ERR_INT_ENA (BIT(17)) +#define RMT_CH5_ERR_INT_ENA_M (BIT(17)) +#define RMT_CH5_ERR_INT_ENA_V 0x1 +#define RMT_CH5_ERR_INT_ENA_S 17 +/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/ +#define RMT_CH5_RX_END_INT_ENA (BIT(16)) +#define RMT_CH5_RX_END_INT_ENA_M (BIT(16)) +#define RMT_CH5_RX_END_INT_ENA_V 0x1 +#define RMT_CH5_RX_END_INT_ENA_S 16 +/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/ +#define RMT_CH5_TX_END_INT_ENA (BIT(15)) +#define RMT_CH5_TX_END_INT_ENA_M (BIT(15)) +#define RMT_CH5_TX_END_INT_ENA_V 0x1 +#define RMT_CH5_TX_END_INT_ENA_S 15 +/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_err_int_st.*/ +#define RMT_CH4_ERR_INT_ENA (BIT(14)) +#define RMT_CH4_ERR_INT_ENA_M (BIT(14)) +#define RMT_CH4_ERR_INT_ENA_V 0x1 +#define RMT_CH4_ERR_INT_ENA_S 14 +/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/ +#define RMT_CH4_RX_END_INT_ENA (BIT(13)) +#define RMT_CH4_RX_END_INT_ENA_M (BIT(13)) +#define RMT_CH4_RX_END_INT_ENA_V 0x1 +#define RMT_CH4_RX_END_INT_ENA_S 13 +/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/ +#define RMT_CH4_TX_END_INT_ENA (BIT(12)) +#define RMT_CH4_TX_END_INT_ENA_M (BIT(12)) +#define RMT_CH4_TX_END_INT_ENA_V 0x1 +#define RMT_CH4_TX_END_INT_ENA_S 12 +/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_err_int_st.*/ +#define RMT_CH3_ERR_INT_ENA (BIT(11)) +#define RMT_CH3_ERR_INT_ENA_M (BIT(11)) +#define RMT_CH3_ERR_INT_ENA_V 0x1 +#define RMT_CH3_ERR_INT_ENA_S 11 +/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/ +#define RMT_CH3_RX_END_INT_ENA (BIT(10)) +#define RMT_CH3_RX_END_INT_ENA_M (BIT(10)) +#define RMT_CH3_RX_END_INT_ENA_V 0x1 +#define RMT_CH3_RX_END_INT_ENA_S 10 +/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/ +#define RMT_CH3_TX_END_INT_ENA (BIT(9)) +#define RMT_CH3_TX_END_INT_ENA_M (BIT(9)) +#define RMT_CH3_TX_END_INT_ENA_V 0x1 +#define RMT_CH3_TX_END_INT_ENA_S 9 +/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_err_int_st.*/ +#define RMT_CH2_ERR_INT_ENA (BIT(8)) +#define RMT_CH2_ERR_INT_ENA_M (BIT(8)) +#define RMT_CH2_ERR_INT_ENA_V 0x1 +#define RMT_CH2_ERR_INT_ENA_S 8 +/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/ +#define RMT_CH2_RX_END_INT_ENA (BIT(7)) +#define RMT_CH2_RX_END_INT_ENA_M (BIT(7)) +#define RMT_CH2_RX_END_INT_ENA_V 0x1 +#define RMT_CH2_RX_END_INT_ENA_S 7 +/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/ +#define RMT_CH2_TX_END_INT_ENA (BIT(6)) +#define RMT_CH2_TX_END_INT_ENA_M (BIT(6)) +#define RMT_CH2_TX_END_INT_ENA_V 0x1 +#define RMT_CH2_TX_END_INT_ENA_S 6 +/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_err_int_st.*/ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_V 0x1 +#define RMT_CH1_ERR_INT_ENA_S 5 +/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/ +#define RMT_CH1_RX_END_INT_ENA (BIT(4)) +#define RMT_CH1_RX_END_INT_ENA_M (BIT(4)) +#define RMT_CH1_RX_END_INT_ENA_V 0x1 +#define RMT_CH1_RX_END_INT_ENA_S 4 +/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/ +#define RMT_CH1_TX_END_INT_ENA (BIT(3)) +#define RMT_CH1_TX_END_INT_ENA_M (BIT(3)) +#define RMT_CH1_TX_END_INT_ENA_V 0x1 +#define RMT_CH1_TX_END_INT_ENA_S 3 +/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_err_int_st.*/ +#define RMT_CH0_ERR_INT_ENA (BIT(2)) +#define RMT_CH0_ERR_INT_ENA_M (BIT(2)) +#define RMT_CH0_ERR_INT_ENA_V 0x1 +#define RMT_CH0_ERR_INT_ENA_S 2 +/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/ +#define RMT_CH0_RX_END_INT_ENA (BIT(1)) +#define RMT_CH0_RX_END_INT_ENA_M (BIT(1)) +#define RMT_CH0_RX_END_INT_ENA_V 0x1 +#define RMT_CH0_RX_END_INT_ENA_S 1 +/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_V 0x1 +#define RMT_CH0_TX_END_INT_ENA_S 0 + +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x00ac) +/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH7_TX_THR_EVENT_INT_CLR (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_CLR_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_CLR_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH6_TX_THR_EVENT_INT_CLR (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_CLR_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_CLR_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH5_TX_THR_EVENT_INT_CLR (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_CLR_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_CLR_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH4_TX_THR_EVENT_INT_CLR (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_CLR_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_CLR_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 24 +/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_err_int_raw.*/ +#define RMT_CH7_ERR_INT_CLR (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_V 0x1 +#define RMT_CH7_ERR_INT_CLR_S 23 +/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ +#define RMT_CH7_RX_END_INT_CLR (BIT(22)) +#define RMT_CH7_RX_END_INT_CLR_M (BIT(22)) +#define RMT_CH7_RX_END_INT_CLR_V 0x1 +#define RMT_CH7_RX_END_INT_CLR_S 22 +/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ +#define RMT_CH7_TX_END_INT_CLR (BIT(21)) +#define RMT_CH7_TX_END_INT_CLR_M (BIT(21)) +#define RMT_CH7_TX_END_INT_CLR_V 0x1 +#define RMT_CH7_TX_END_INT_CLR_S 21 +/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_err_int_raw.*/ +#define RMT_CH6_ERR_INT_CLR (BIT(20)) +#define RMT_CH6_ERR_INT_CLR_M (BIT(20)) +#define RMT_CH6_ERR_INT_CLR_V 0x1 +#define RMT_CH6_ERR_INT_CLR_S 20 +/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ +#define RMT_CH6_RX_END_INT_CLR (BIT(19)) +#define RMT_CH6_RX_END_INT_CLR_M (BIT(19)) +#define RMT_CH6_RX_END_INT_CLR_V 0x1 +#define RMT_CH6_RX_END_INT_CLR_S 19 +/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ +#define RMT_CH6_TX_END_INT_CLR (BIT(18)) +#define RMT_CH6_TX_END_INT_CLR_M (BIT(18)) +#define RMT_CH6_TX_END_INT_CLR_V 0x1 +#define RMT_CH6_TX_END_INT_CLR_S 18 +/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_err_int_raw.*/ +#define RMT_CH5_ERR_INT_CLR (BIT(17)) +#define RMT_CH5_ERR_INT_CLR_M (BIT(17)) +#define RMT_CH5_ERR_INT_CLR_V 0x1 +#define RMT_CH5_ERR_INT_CLR_S 17 +/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ +#define RMT_CH5_RX_END_INT_CLR (BIT(16)) +#define RMT_CH5_RX_END_INT_CLR_M (BIT(16)) +#define RMT_CH5_RX_END_INT_CLR_V 0x1 +#define RMT_CH5_RX_END_INT_CLR_S 16 +/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ +#define RMT_CH5_TX_END_INT_CLR (BIT(15)) +#define RMT_CH5_TX_END_INT_CLR_M (BIT(15)) +#define RMT_CH5_TX_END_INT_CLR_V 0x1 +#define RMT_CH5_TX_END_INT_CLR_S 15 +/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_err_int_raw.*/ +#define RMT_CH4_ERR_INT_CLR (BIT(14)) +#define RMT_CH4_ERR_INT_CLR_M (BIT(14)) +#define RMT_CH4_ERR_INT_CLR_V 0x1 +#define RMT_CH4_ERR_INT_CLR_S 14 +/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ +#define RMT_CH4_RX_END_INT_CLR (BIT(13)) +#define RMT_CH4_RX_END_INT_CLR_M (BIT(13)) +#define RMT_CH4_RX_END_INT_CLR_V 0x1 +#define RMT_CH4_RX_END_INT_CLR_S 13 +/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ +#define RMT_CH4_TX_END_INT_CLR (BIT(12)) +#define RMT_CH4_TX_END_INT_CLR_M (BIT(12)) +#define RMT_CH4_TX_END_INT_CLR_V 0x1 +#define RMT_CH4_TX_END_INT_CLR_S 12 +/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_err_int_raw.*/ +#define RMT_CH3_ERR_INT_CLR (BIT(11)) +#define RMT_CH3_ERR_INT_CLR_M (BIT(11)) +#define RMT_CH3_ERR_INT_CLR_V 0x1 +#define RMT_CH3_ERR_INT_CLR_S 11 +/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ +#define RMT_CH3_RX_END_INT_CLR (BIT(10)) +#define RMT_CH3_RX_END_INT_CLR_M (BIT(10)) +#define RMT_CH3_RX_END_INT_CLR_V 0x1 +#define RMT_CH3_RX_END_INT_CLR_S 10 +/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ +#define RMT_CH3_TX_END_INT_CLR (BIT(9)) +#define RMT_CH3_TX_END_INT_CLR_M (BIT(9)) +#define RMT_CH3_TX_END_INT_CLR_V 0x1 +#define RMT_CH3_TX_END_INT_CLR_S 9 +/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_err_int_raw.*/ +#define RMT_CH2_ERR_INT_CLR (BIT(8)) +#define RMT_CH2_ERR_INT_CLR_M (BIT(8)) +#define RMT_CH2_ERR_INT_CLR_V 0x1 +#define RMT_CH2_ERR_INT_CLR_S 8 +/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ +#define RMT_CH2_RX_END_INT_CLR (BIT(7)) +#define RMT_CH2_RX_END_INT_CLR_M (BIT(7)) +#define RMT_CH2_RX_END_INT_CLR_V 0x1 +#define RMT_CH2_RX_END_INT_CLR_S 7 +/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ +#define RMT_CH2_TX_END_INT_CLR (BIT(6)) +#define RMT_CH2_TX_END_INT_CLR_M (BIT(6)) +#define RMT_CH2_TX_END_INT_CLR_V 0x1 +#define RMT_CH2_TX_END_INT_CLR_S 6 +/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_err_int_raw.*/ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_V 0x1 +#define RMT_CH1_ERR_INT_CLR_S 5 +/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ +#define RMT_CH1_RX_END_INT_CLR (BIT(4)) +#define RMT_CH1_RX_END_INT_CLR_M (BIT(4)) +#define RMT_CH1_RX_END_INT_CLR_V 0x1 +#define RMT_CH1_RX_END_INT_CLR_S 4 +/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ +#define RMT_CH1_TX_END_INT_CLR (BIT(3)) +#define RMT_CH1_TX_END_INT_CLR_M (BIT(3)) +#define RMT_CH1_TX_END_INT_CLR_V 0x1 +#define RMT_CH1_TX_END_INT_CLR_S 3 +/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_err_int_raw.*/ +#define RMT_CH0_ERR_INT_CLR (BIT(2)) +#define RMT_CH0_ERR_INT_CLR_M (BIT(2)) +#define RMT_CH0_ERR_INT_CLR_V 0x1 +#define RMT_CH0_ERR_INT_CLR_S 2 +/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ +#define RMT_CH0_RX_END_INT_CLR (BIT(1)) +#define RMT_CH0_RX_END_INT_CLR_M (BIT(1)) +#define RMT_CH0_RX_END_INT_CLR_V 0x1 +#define RMT_CH0_RX_END_INT_CLR_S 1 +/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_V 0x1 +#define RMT_CH0_TX_END_INT_CLR_S 0 + +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b0) +/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel0.*/ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFF +#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) +#define RMT_CARRIER_HIGH_CH0_V 0xFFFF +#define RMT_CARRIER_HIGH_CH0_S 16 +/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel0.*/ +#define RMT_CARRIER_LOW_CH0 0x0000FFFF +#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) +#define RMT_CARRIER_LOW_CH0_V 0xFFFF +#define RMT_CARRIER_LOW_CH0_S 0 + +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b4) +/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel1.*/ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFF +#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) +#define RMT_CARRIER_HIGH_CH1_V 0xFFFF +#define RMT_CARRIER_HIGH_CH1_S 16 +/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel1.*/ +#define RMT_CARRIER_LOW_CH1 0x0000FFFF +#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) +#define RMT_CARRIER_LOW_CH1_V 0xFFFF +#define RMT_CARRIER_LOW_CH1_S 0 + +#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b8) +/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel2.*/ +#define RMT_CARRIER_HIGH_CH2 0x0000FFFF +#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S)) +#define RMT_CARRIER_HIGH_CH2_V 0xFFFF +#define RMT_CARRIER_HIGH_CH2_S 16 +/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel2.*/ +#define RMT_CARRIER_LOW_CH2 0x0000FFFF +#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S)) +#define RMT_CARRIER_LOW_CH2_V 0xFFFF +#define RMT_CARRIER_LOW_CH2_S 0 + +#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00bc) +/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel3.*/ +#define RMT_CARRIER_HIGH_CH3 0x0000FFFF +#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S)) +#define RMT_CARRIER_HIGH_CH3_V 0xFFFF +#define RMT_CARRIER_HIGH_CH3_S 16 +/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel3.*/ +#define RMT_CARRIER_LOW_CH3 0x0000FFFF +#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S)) +#define RMT_CARRIER_LOW_CH3_V 0xFFFF +#define RMT_CARRIER_LOW_CH3_S 0 + +#define RMT_CH4CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c0) +/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel4.*/ +#define RMT_CARRIER_HIGH_CH4 0x0000FFFF +#define RMT_CARRIER_HIGH_CH4_M ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S)) +#define RMT_CARRIER_HIGH_CH4_V 0xFFFF +#define RMT_CARRIER_HIGH_CH4_S 16 +/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel4.*/ +#define RMT_CARRIER_LOW_CH4 0x0000FFFF +#define RMT_CARRIER_LOW_CH4_M ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S)) +#define RMT_CARRIER_LOW_CH4_V 0xFFFF +#define RMT_CARRIER_LOW_CH4_S 0 + +#define RMT_CH5CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c4) +/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel5.*/ +#define RMT_CARRIER_HIGH_CH5 0x0000FFFF +#define RMT_CARRIER_HIGH_CH5_M ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S)) +#define RMT_CARRIER_HIGH_CH5_V 0xFFFF +#define RMT_CARRIER_HIGH_CH5_S 16 +/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel5.*/ +#define RMT_CARRIER_LOW_CH5 0x0000FFFF +#define RMT_CARRIER_LOW_CH5_M ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S)) +#define RMT_CARRIER_LOW_CH5_V 0xFFFF +#define RMT_CARRIER_LOW_CH5_S 0 + +#define RMT_CH6CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c8) +/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel6.*/ +#define RMT_CARRIER_HIGH_CH6 0x0000FFFF +#define RMT_CARRIER_HIGH_CH6_M ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S)) +#define RMT_CARRIER_HIGH_CH6_V 0xFFFF +#define RMT_CARRIER_HIGH_CH6_S 16 +/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel6.*/ +#define RMT_CARRIER_LOW_CH6 0x0000FFFF +#define RMT_CARRIER_LOW_CH6_M ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S)) +#define RMT_CARRIER_LOW_CH6_V 0xFFFF +#define RMT_CARRIER_LOW_CH6_S 0 + +#define RMT_CH7CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00cc) +/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel7.*/ +#define RMT_CARRIER_HIGH_CH7 0x0000FFFF +#define RMT_CARRIER_HIGH_CH7_M ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S)) +#define RMT_CARRIER_HIGH_CH7_V 0xFFFF +#define RMT_CARRIER_HIGH_CH7_S 16 +/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel7.*/ +#define RMT_CARRIER_LOW_CH7 0x0000FFFF +#define RMT_CARRIER_LOW_CH7_M ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S)) +#define RMT_CARRIER_LOW_CH7_V 0xFFFF +#define RMT_CARRIER_LOW_CH7_S 0 + +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0) +/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH0 0x000001FF +#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) +#define RMT_TX_LIM_CH0_V 0x1FF +#define RMT_TX_LIM_CH0_S 0 + +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4) +/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH1 0x000001FF +#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) +#define RMT_TX_LIM_CH1_V 0x1FF +#define RMT_TX_LIM_CH1_S 0 + +#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8) +/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH2 0x000001FF +#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S)) +#define RMT_TX_LIM_CH2_V 0x1FF +#define RMT_TX_LIM_CH2_S 0 + +#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc) +/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH3 0x000001FF +#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S)) +#define RMT_TX_LIM_CH3_V 0x1FF +#define RMT_TX_LIM_CH3_S 0 + +#define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0) +/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH4 0x000001FF +#define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S)) +#define RMT_TX_LIM_CH4_V 0x1FF +#define RMT_TX_LIM_CH4_S 0 + +#define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4) +/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH5 0x000001FF +#define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S)) +#define RMT_TX_LIM_CH5_V 0x1FF +#define RMT_TX_LIM_CH5_S 0 + +#define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8) +/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH6 0x000001FF +#define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S)) +#define RMT_TX_LIM_CH6_V 0x1FF +#define RMT_TX_LIM_CH6_S 0 + +#define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec) +/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH7 0x000001FF +#define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S)) +#define RMT_TX_LIM_CH7_V 0x1FF +#define RMT_TX_LIM_CH7_S 0 + +#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0) +/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: when datas need to be send is more than channel's mem can store + then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/ +#define RMT_MEM_TX_WRAP_EN (BIT(1)) +#define RMT_MEM_TX_WRAP_EN_M (BIT(1)) +#define RMT_MEM_TX_WRAP_EN_V 0x1 +#define RMT_MEM_TX_WRAP_EN_S 1 +/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to disable apb fifo access*/ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (BIT(0)) +#define RMT_APB_FIFO_MASK_V 0x1 +#define RMT_APB_FIFO_MASK_S 0 + +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00fc) +/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */ +/*description: This is the version register.*/ +#define RMT_DATE 0xFFFFFFFF +#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) +#define RMT_DATE_V 0xFFFFFFFF +#define RMT_DATE_S 0 + +/* RMT memory block address */ +#define RMT_CHANNEL_MEM(i) (DR_REG_RMT_BASE + 0x800 + 64 * 4 * (i)) + + +#endif /*_SOC_RMT_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/rmt_struct.h b/tools/sdk/include/soc/soc/rmt_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/rmt_struct.h rename to tools/sdk/include/soc/soc/rmt_struct.h diff --git a/tools/sdk/include/soc/soc/rtc.h b/tools/sdk/include/soc/soc/rtc.h new file mode 100644 index 00000000..aecf76be --- /dev/null +++ b/tools/sdk/include/soc/soc/rtc.h @@ -0,0 +1,496 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file rtc.h + * @brief Low-level RTC power, clock, and sleep functions. + * + * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. + * RTC_CNTL peripheral handles many functions: + * - enables/disables clocks and power to various parts of the chip; this is + * done using direct register access (forcing power up or power down) or by + * allowing state machines to control power and clocks automatically + * - handles sleep and wakeup functions + * - maintains a 48-bit counter which can be used for timekeeping + * + * These functions are not thread safe, and should not be viewed as high level + * APIs. For example, while this file provides a function which can switch + * CPU frequency, this function is on its own is not sufficient to implement + * frequency switching in ESP-IDF context: some coordination with RTOS, + * peripheral drivers, and WiFi/BT stacks is also required. + * + * These functions will normally not be used in applications directly. + * ESP-IDF provides, or will provide, drivers and other facilities to use + * RTC subsystem functionality. + * + * The functions are loosely split into the following groups: + * - rtc_clk: clock switching, calibration + * - rtc_time: reading RTC counter, conversion between counter values and time + * - rtc_sleep: entry into sleep modes + * - rtc_init: initialization + */ + + +/** + * @brief Possible main XTAL frequency values. + * + * Enum values should be equal to frequency in MHz. + */ +typedef enum { + RTC_XTAL_FREQ_AUTO = 0, //!< Automatic XTAL frequency detection + RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL + RTC_XTAL_FREQ_26M = 26, //!< 26 MHz XTAL + RTC_XTAL_FREQ_24M = 24, //!< 24 MHz XTAL +} rtc_xtal_freq_t; + +/** + * @brief CPU frequency values + */ +typedef enum { + RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency + RTC_CPU_FREQ_80M = 1, //!< 80 MHz + RTC_CPU_FREQ_160M = 2, //!< 160 MHz + RTC_CPU_FREQ_240M = 3, //!< 240 MHz + RTC_CPU_FREQ_2M = 4, //!< 2 MHz +} rtc_cpu_freq_t; + +/** + * @brief RTC SLOW_CLK frequency values + */ +typedef enum { + RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator + RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL + RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 +} rtc_slow_freq_t; + +/** + * @brief RTC FAST_CLK frequency values + */ +typedef enum { + RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 + RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator +} rtc_fast_freq_t; + +/** + * @brief Clock source to be calibrated using rtc_clk_cal function + */ +typedef enum { + RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK + RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256 + RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL +} rtc_cal_sel_t; + +/** + * Initialization parameters for rtc_clk_init + */ +typedef struct { + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + rtc_cpu_freq_t cpu_freq : 3; //!< CPU frequency to set + rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set + rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set + uint32_t clk_8m_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) +} rtc_clk_config_t; + +/** + * Default initializer for rtc_clk_config_t + */ +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = RTC_XTAL_FREQ_AUTO, \ + .cpu_freq = RTC_CPU_FREQ_80M, \ + .fast_freq = RTC_FAST_FREQ_8M, \ + .slow_freq = RTC_SLOW_FREQ_RTC, \ + .clk_8m_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ +} + +/** + * Initialize clocks and set CPU frequency + * + * If cfg.xtal_freq is set to RTC_XTAL_FREQ_AUTO, this function will attempt + * to auto detect XTAL frequency. Auto detection is performed by comparing + * XTAL frequency with the frequency of internal 8MHz oscillator. Note that at + * high temperatures the frequency of the internal 8MHz oscillator may drift + * enough for auto detection to be unreliable. + * Auto detection code will attempt to distinguish between 26MHz and 40MHz + * crystals. 24 MHz crystals are not supported by auto detection code. + * If XTAL frequency can not be auto detected, this 26MHz frequency will be used. + * + * @param cfg clock configuration as rtc_clk_config_t + */ +void rtc_clk_init(rtc_clk_config_t cfg); + +/** + * @brief Get main XTAL frequency + * + * This is the value passed to rtc_clk_init function, or if the value was + * RTC_XTAL_FREQ_AUTO, the detected XTAL frequency. + * + * @return XTAL frequency, one of rtc_xtal_freq_t + */ +rtc_xtal_freq_t rtc_clk_xtal_freq_get(); + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_32k_enable(bool en); + +/** + * @brief Get the state of 32k XTAL oscillator + * @return true if 32k XTAL oscillator has been enabled + */ +bool rtc_clk_32k_enabled(); + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * Output from 8 MHz internal oscillator is passed into a configurable + * divider, which by default divides the input clock frequency by 256. + * Output of the divider may be used as RTC_SLOW_CLK source. + * Output of the divider is referred to in register descriptions and code as + * 8md256 or simply d256. Divider values other than 256 may be configured, but + * this facility is not currently needed, so is not exposed in the code. + * + * When 8MHz/256 divided output is not needed, the divider should be disabled + * to reduce power consumption. + * + * @param clk_8m_en true to enable 8MHz generator + * @param d256_en true to enable /256 divider + */ +void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +bool rtc_clk_8m_enabled(); + +/** + * @brief Get the state of /256 divider which is applied to 8MHz clock + * @return true if the divided output is enabled + */ +bool rtc_clk_8md256_enabled(); + +/** + * @brief Enable or disable APLL + * + * Output frequency is given by the formula: + * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) + * + * The dividend in this expression should be in the range of 240 - 600 MHz. + * + * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0. + * + * @param enable true to enable, false to disable + * @param sdm0 frequency adjustment parameter, 0..255 + * @param sdm1 frequency adjustment parameter, 0..255 + * @param sdm2 frequency adjustment parameter, 0..63 + * @param o_div frequency divider, 0..31 + */ +void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, + uint32_t sdm2, uint32_t o_div); + +/** + * @brief Select source for RTC_SLOW_CLK + * @param slow_freq clock source (one of rtc_slow_freq_t values) + */ +void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of rtc_slow_freq_t values) + */ +rtc_slow_freq_t rtc_clk_slow_freq_get(); + +/** + * @brief Select source for RTC_FAST_CLK + * @param fast_freq clock source (one of rtc_fast_freq_t values) + */ +void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of rtc_fast_freq_t values) + */ +rtc_fast_freq_t rtc_clk_fast_freq_get(); + +/** + * @brief Switch CPU frequency + * + * If a PLL-derived frequency is requested (80, 160, 240 MHz), this function + * will enable the PLL. Otherwise, PLL will be disabled. + * Note: this function is not optimized for switching speed. It may take several + * hundred microseconds to perform frequency switch. + * + * @param cpu_freq new CPU frequency + */ +void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq); + +/** + * @brief Get the currently selected CPU frequency + * + * Although CPU can be clocked by APLL and RTC 8M sources, such support is not + * exposed through this library. As such, this function will not return + * meaningful values when these clock sources are configured (e.g. using direct + * access to clock selection registers). In debug builds, it will assert; in + * release builds, it will return RTC_CPU_FREQ_XTAL. + * + * @return CPU frequency (one of rtc_cpu_freq_t values) + */ +rtc_cpu_freq_t rtc_clk_cpu_freq_get(); + +/** + * @brief Get corresponding frequency value for rtc_cpu_freq_t enum value + * @param cpu_freq CPU frequency, on of rtc_cpu_freq_t values + * @return CPU frequency, in HZ + */ +uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq); + +/** + * @brief Store new APB frequency value into RTC_APB_FREQ_REG + * + * This function doesn't change any hardware clocks. + * + * Functions which perform frequency switching and change APB frequency call + * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG + * (one of RTC general purpose retention registers). This should not normally + * be called from application code. + * + * @param apb_freq new APB frequency, in Hz + */ +void rtc_clk_apb_freq_update(uint32_t apb_freq); + +/** + * @brief Get the current stored APB frequency. + * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. + */ +uint32_t rtc_clk_apb_freq_get(); + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +uint64_t rtc_time_get(); + +/** + * @brief sleep configuration for rtc_sleep_init function + */ +typedef struct { + uint32_t soc_clk_sel : 2; //!< SoC clock select, see RTC_CNTL_SOC_CLK_SEL + uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) + uint32_t rtc_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (RTC memory) + uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) + uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory + uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory + uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals + uint32_t wifi_pd_en : 1; //!< power down WiFi + uint32_t rom_mem_pd_en : 1; //!< power down main RAM and ROM + uint32_t deep_slp : 1; //!< power down digital domain + uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode + uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode + uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode + uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode + uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode + uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags +} rtc_sleep_config_t; + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ + .soc_clk_sel = RTC_CNTL_SOC_CLK_SEL_XTL, \ + .lslp_mem_inf_fpu = 0, \ + .rtc_mem_inf_fpu = 0, \ + .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ + .wifi_pd_en = 0, \ + .rom_mem_pd_en = 0, \ + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ + .wdt_flashboot_mod_en = 0, \ + .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \ + .rtc_dbias_wak = RTC_CNTL_DBIAS_0V90, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \ + .lslp_meminf_pd = 1 \ +}; + +#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) +#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals +#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory +#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory +#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU + +/** + * @brief Prepare the chip to enter sleep mode + * + * This function configures various power control state machines to handle + * entry into light sleep or deep sleep mode, switches APB and CPU clock source + * (usually to XTAL), and sets bias voltages for digital and RTC power domains. + * + * This function does not actually enter sleep mode; this is done using + * rtc_sleep_start function. Software may do some other actions between + * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure + * wakeup sources. + * @param cfg sleep mode configuration + */ +void rtc_sleep_init(rtc_sleep_config_t cfg); + + +/** + * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source + * @param t value of RTC counter at which wakeup from sleep will happen; + * only the lower 48 bits are used + */ +void rtc_sleep_set_wakeup_time(uint64_t t); + + +#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup +#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup +#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only) +#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup +#define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only) +#define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only) +#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only) +#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only) +#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup +#define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup +#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) + +/** + * @brief Enter deep or light sleep mode + * + * This function enters the sleep mode previously configured using rtc_sleep_init + * function. Before entering sleep, software should configure wake up sources + * appropriately (set up GPIO wakeup registers, timer wakeup registers, + * and so on). + * + * If deep sleep mode was configured using rtc_sleep_init, and sleep is not + * rejected by hardware (based on reject_opt flags), this function never returns. + * When the chip wakes up from deep sleep, CPU is reset and execution starts + * from ROM bootloader. + * + * If light sleep mode was configured using rtc_sleep_init, this function + * returns on wakeup, or if sleep is rejected by hardware. + * + * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags + * combined with OR) + * @param reject_opt bit mask of sleep reject reasons: + * - RTC_CNTL_GPIO_REJECT_EN + * - RTC_CNTL_SDIO_REJECT_EN + * These flags are used to prevent entering sleep when e.g. + * an external host is communicating via SDIO slave + * @return non-zero if sleep was rejected by hardware + */ +uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); + +/** + * RTC power and clock control initialization settings + */ +typedef struct { + uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready + uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready + uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready + uint32_t clkctl_init : 1; //!< Perform clock control related initialization + uint32_t pwrctl_init : 1; //!< Perform power control related initialization + uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST +} rtc_config_t; + +/** + * Default initializer of rtc_config_t. + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use). + */ +#define RTC_CONFIG_DEFAULT() {\ + .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ + .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ + .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ + .clkctl_init = 1, \ + .pwrctl_init = 1, \ + .rtc_dboost_fpd = 1 \ +} + +/** + * Initialize RTC clock and power control related functions + * @param cfg configuration options as rtc_config_t + */ +void rtc_init(rtc_config_t cfg); + + +#ifdef __cplusplus +} +#endif + diff --git a/tools/sdk/include/esp32/soc/rtc_cntl_reg.h b/tools/sdk/include/soc/soc/rtc_cntl_reg.h similarity index 96% rename from tools/sdk/include/esp32/soc/rtc_cntl_reg.h rename to tools/sdk/include/soc/soc/rtc_cntl_reg.h index 40d65f21..067f2296 100644 --- a/tools/sdk/include/esp32/soc/rtc_cntl_reg.h +++ b/tools/sdk/include/soc/soc/rtc_cntl_reg.h @@ -321,18 +321,21 @@ #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF #define RTC_CNTL_PLL_BUF_WAIT_S 24 +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ /*description: XTAL wait cycles in slow_clk_rtc*/ #define RTC_CNTL_XTL_BUF_WAIT 0x000003FF #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF #define RTC_CNTL_XTL_BUF_WAIT_S 14 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ /*description: CK8M wait cycles in slow_clk_rtc*/ #define RTC_CNTL_CK8M_WAIT 0x000000FF #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) #define RTC_CNTL_CK8M_WAIT_V 0xFF #define RTC_CNTL_CK8M_WAIT_S 6 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ /*description: CPU stall wait cycles in fast_clk_rtc*/ #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F @@ -892,6 +895,10 @@ #define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S)) #define RTC_CNTL_SOC_CLK_SEL_V 0x3 #define RTC_CNTL_SOC_CLK_SEL_S 27 +#define RTC_CNTL_SOC_CLK_SEL_XTL 0 +#define RTC_CNTL_SOC_CLK_SEL_PLL 1 +#define RTC_CNTL_SOC_CLK_SEL_8M 2 +#define RTC_CNTL_SOC_CLK_SEL_APLL 3 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ /*description: CK8M force power up*/ #define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) @@ -910,6 +917,7 @@ #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) #define RTC_CNTL_CK8M_DFREQ_V 0xFF #define RTC_CNTL_CK8M_DFREQ_S 17 +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ /*description: CK8M force no gating during sleep*/ #define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) @@ -1109,6 +1117,7 @@ #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) #define RTC_CNTL_SCK_DCAP_V 0xFF #define RTC_CNTL_SCK_DCAP_S 14 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ /*description: DIG_REG_DBIAS during wakeup*/ #define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 @@ -1128,6 +1137,19 @@ #define RTC_CNTL_SCK_DCAP_FORCE_V 0x1 #define RTC_CNTL_SCK_DCAP_FORCE_S 7 +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DBIAS_0V90 0 +#define RTC_CNTL_DBIAS_0V95 1 +#define RTC_CNTL_DBIAS_1V00 2 +#define RTC_CNTL_DBIAS_1V05 3 +#define RTC_CNTL_DBIAS_1V10 4 +#define RTC_CNTL_DBIAS_1V15 5 +#define RTC_CNTL_DBIAS_1V20 6 +#define RTC_CNTL_DBIAS_1V25 7 + #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ /*description: enable power down rtc_peri in sleep*/ @@ -1257,6 +1279,24 @@ #define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 #define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 +/* Useful groups of RTC_CNTL_PWC_REG bits */ +#define RTC_CNTL_MEM_FORCE_ISO \ + (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO) +#define RTC_CNTL_MEM_FORCE_NOISO \ + (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) +#define RTC_CNTL_MEM_PD_EN \ + (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN) +#define RTC_CNTL_MEM_FORCE_PU \ + (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU) +#define RTC_CNTL_MEM_FORCE_PD \ + (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD) +#define RTC_CNTL_MEM_FOLW_CPU \ + (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU) +#define RTC_CNTL_MEM_FORCE_LPU \ + (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU) +#define RTC_CNTL_MEM_FORCE_LPD \ + (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD) + #define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ /*description: enable power down digital core in sleep*/ @@ -1415,6 +1455,20 @@ #define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 +/* Useful groups of RTC_CNTL_DIG_PWC_REG bits */ +#define RTC_CNTL_CPU_ROM_RAM_PD_EN \ + (RTC_CNTL_INTER_RAM4_PD_EN | RTC_CNTL_INTER_RAM3_PD_EN |\ + RTC_CNTL_INTER_RAM2_PD_EN | RTC_CNTL_INTER_RAM1_PD_EN |\ + RTC_CNTL_INTER_RAM0_PD_EN | RTC_CNTL_ROM0_PD_EN) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_PU \ + (RTC_CNTL_INTER_RAM4_FORCE_PU | RTC_CNTL_INTER_RAM3_FORCE_PU |\ + RTC_CNTL_INTER_RAM2_FORCE_PU | RTC_CNTL_INTER_RAM1_FORCE_PU |\ + RTC_CNTL_INTER_RAM0_FORCE_PU | RTC_CNTL_ROM0_FORCE_PU) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_PD \ + (RTC_CNTL_INTER_RAM4_FORCE_PD | RTC_CNTL_INTER_RAM3_FORCE_PD |\ + RTC_CNTL_INTER_RAM2_FORCE_PD | RTC_CNTL_INTER_RAM1_FORCE_PD |\ + RTC_CNTL_INTER_RAM0_FORCE_PD | RTC_CNTL_ROM0_FORCE_PD + #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ /*description: digital core force no ISO*/ @@ -1567,6 +1621,16 @@ #define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 +/* Useful groups of RTC_CNTL_DIG_ISO_REG bits */ +#define RTC_CNTL_CPU_ROM_RAM_FORCE_ISO \ + (RTC_CNTL_INTER_RAM4_FORCE_ISO | RTC_CNTL_INTER_RAM3_FORCE_ISO |\ + RTC_CNTL_INTER_RAM2_FORCE_ISO | RTC_CNTL_INTER_RAM1_FORCE_ISO |\ + RTC_CNTL_INTER_RAM0_FORCE_ISO | RTC_CNTL_ROM0_FORCE_ISO) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO \ + (RTC_CNTL_INTER_RAM4_FORCE_NOISO | RTC_CNTL_INTER_RAM3_FORCE_NOISO |\ + RTC_CNTL_INTER_RAM2_FORCE_NOISO | RTC_CNTL_INTER_RAM1_FORCE_NOISO |\ + RTC_CNTL_INTER_RAM0_FORCE_NOISO | RTC_CNTL_ROM0_FORCE_NOISO) + #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ /*description: enable RTC WDT*/ @@ -1650,6 +1714,12 @@ #define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(7)) #define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7 +/* RTC_CNTL_WDT_STGX : */ +/*description: stage action selection values */ +#define RTC_WDT_STG_SEL_OFF 0 +#define RTC_WDT_STG_SEL_INT 1 +#define RTC_WDT_STG_SEL_RESET_CPU 2 +#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 #define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */ diff --git a/tools/sdk/include/soc/soc/rtc_cntl_struct.h b/tools/sdk/include/soc/soc/rtc_cntl_struct.h new file mode 100644 index 00000000..acb12432 --- /dev/null +++ b/tools/sdk/include/soc/soc/rtc_cntl_struct.h @@ -0,0 +1,553 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_CNTL_STRUCT_H_ +#define _SOC_RTC_CNTL_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ + uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ + uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ + uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ + uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ + uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ + uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ + uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ + uint32_t xtl_force_pd: 1; /*crystall force power down*/ + uint32_t xtl_force_pu: 1; /*crystall force power up*/ + uint32_t bias_sleep_folw_8m: 1; /*BIAS_SLEEP follow CK8M*/ + uint32_t bias_force_sleep: 1; /*BIAS_SLEEP force sleep*/ + uint32_t bias_force_nosleep: 1; /*BIAS_SLEEP force no sleep*/ + uint32_t bias_i2c_folw_8m: 1; /*BIAS_I2C follow CK8M*/ + uint32_t bias_i2c_force_pd: 1; /*BIAS_I2C force power down*/ + uint32_t bias_i2c_force_pu: 1; /*BIAS_I2C force power up*/ + uint32_t bias_core_folw_8m: 1; /*BIAS_CORE follow CK8M*/ + uint32_t bias_core_force_pd: 1; /*BIAS_CORE force power down*/ + uint32_t bias_core_force_pu: 1; /*BIAS_CORE force power up*/ + uint32_t xtl_force_iso: 1; + uint32_t pll_force_iso: 1; + uint32_t analog_force_iso: 1; + uint32_t xtl_force_noiso: 1; + uint32_t pll_force_noiso: 1; + uint32_t analog_force_noiso: 1; + uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ + uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ + uint32_t sw_sys_rst: 1; /*SW system reset*/ + }; + uint32_t val; + } options0; + uint32_t slp_timer0; /*RTC sleep timer low 32 bits*/ + union { + struct { + uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ + uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } slp_timer1; + union { + struct { + uint32_t reserved0: 30; + uint32_t valid: 1; /*To indicate the register is updated*/ + uint32_t update: 1; /*Set 1: to update register with RTC timer*/ + }; + uint32_t val; + } time_update; + uint32_t time0; /*RTC timer low 32 bits*/ + union { + struct { + uint32_t time_hi:16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } time1; + union { + struct { + uint32_t reserved0: 20; + uint32_t touch_wakeup_force_en: 1; /*touch controller force wake up*/ + uint32_t ulp_cp_wakeup_force_en: 1; /*ULP-coprocessor force wake up*/ + uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge 0: APB to RTC using sync*/ + uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/ + uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/ + uint32_t reserved25: 3; + uint32_t sdio_active_ind: 1; /*SDIO active indication*/ + uint32_t slp_wakeup: 1; /*sleep wakeup bit*/ + uint32_t slp_reject: 1; /*sleep reject bit*/ + uint32_t sleep_en: 1; /*sleep enable bit*/ + }; + uint32_t val; + } state0; + union { + struct { + uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ + uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ + uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ + uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ + uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ + }; + uint32_t val; + } timer1; + union { + struct { + uint32_t reserved0: 15; + uint32_t ulpcp_touch_start_wait: 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/ + uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ + }; + uint32_t val; + } timer2; + union { + struct { + uint32_t wifi_wait_timer: 9; + uint32_t wifi_powerup_timer: 7; + uint32_t rom_ram_wait_timer: 9; + uint32_t rom_ram_powerup_timer: 7; + }; + uint32_t val; + } timer3; + union { + struct { + uint32_t rtc_wait_timer: 9; + uint32_t rtc_powerup_timer: 7; + uint32_t dg_wrap_wait_timer: 9; + uint32_t dg_wrap_powerup_timer: 7; + }; + uint32_t val; + } timer4; + union { + struct { + uint32_t ulp_cp_subtimer_prediv: 8; + uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t rtcmem_wait_timer: 9; + uint32_t rtcmem_powerup_timer: 7; + }; + uint32_t val; + } timer5; + union { + struct { + uint32_t reserved0: 23; + uint32_t plla_force_pd: 1; /*PLLA force power down*/ + uint32_t plla_force_pu: 1; /*PLLA force power up*/ + uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ + uint32_t pvtmon_pu: 1; /*1: PVTMON power up otherwise power down*/ + uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up otherwise power down*/ + uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up otherwise power down*/ + uint32_t reserved29: 1; + uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up otherwise power down*/ + uint32_t pll_i2c_pu: 1; /*1: PLL_I2C power up otherwise power down*/ + }; + uint32_t val; + } ana_conf; + union { + struct { + uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ + uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ + uint32_t appcpu_stat_vector_sel: 1; /*APP CPU state vector sel*/ + uint32_t procpu_stat_vector_sel: 1; /*PRO CPU state vector sel*/ + uint32_t reserved14: 18; + }; + uint32_t val; + } reset_state; + union { + struct { + uint32_t wakeup_cause: 11; /*wakeup cause*/ + uint32_t rtc_wakeup_ena: 11; /*wakeup enable bitmap*/ + uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ + uint32_t reserved23: 9; + }; + uint32_t val; + } wakeup_state; + union { + struct { + uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/ + uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch: 1; /*enable touch interrupt*/ + uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ + uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/ + uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ + uint32_t rtc_touch: 1; /*touch interrupt raw*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ + uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/ + uint32_t rtc_sar: 1; /*ULP-coprocessor interrupt state*/ + uint32_t rtc_touch: 1; /*touch interrupt state*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/ + uint32_t rtc_sar: 1; /*Clear ULP-coprocessor interrupt state*/ + uint32_t rtc_touch: 1; /*Clear touch interrupt state*/ + uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_clr; + uint32_t rtc_store0; /*32-bit general purpose retention register*/ + uint32_t rtc_store1; /*32-bit general purpose retention register*/ + uint32_t rtc_store2; /*32-bit general purpose retention register*/ + uint32_t rtc_store3; /*32-bit general purpose retention register*/ + union { + struct { + uint32_t reserved0: 30; + uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/ + uint32_t ctr_en: 1; /*enable control XTAL by external pads*/ + }; + uint32_t val; + } ext_xtl_conf; + union { + struct { + uint32_t reserved0: 30; + uint32_t wakeup0_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/ + uint32_t wakeup1_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/ + }; + uint32_t val; + } ext_wakeup_conf; + union { + struct { + uint32_t reserved0: 24; + uint32_t gpio_reject_en: 1; /*enable GPIO reject*/ + uint32_t sdio_reject_en: 1; /*enable SDIO reject*/ + uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ + uint32_t reject_cause: 4; /*sleep reject cause*/ + }; + uint32_t val; + } slp_reject_conf; + union { + struct { + uint32_t reserved0: 29; + uint32_t cpusel_conf: 1; /*CPU sel option*/ + uint32_t cpuperiod_sel: 2; /*CPU period sel*/ + }; + uint32_t val; + } cpu_period_conf; + union { + struct { + uint32_t reserved0: 22; + uint32_t sdio_act_dnum:10; + }; + uint32_t val; + } sdio_act_conf; + union { + struct { + uint32_t reserved0: 4; + uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ + uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ + uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ + uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t ck8m_dfreq_force: 1; + uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ + uint32_t soc_clk_sel: 2; /*SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ + uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ + uint32_t ana_clk_rtc_sel: 2; /*slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t reserved0: 21; + uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG 0: use state machine*/ + uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t xpd_sdio: 1; /*SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ + }; + uint32_t val; + } sdio_conf; + union { + struct { + uint32_t reserved0: 24; + uint32_t dbg_atten: 2; /*DBG_ATTEN*/ + uint32_t enb_sck_xtal: 1; /*ENB_SCK_XTAL*/ + uint32_t inc_heartbeat_refresh: 1; /*INC_HEARTBEAT_REFRESH*/ + uint32_t dec_heartbeat_period: 1; /*DEC_HEARTBEAT_PERIOD*/ + uint32_t inc_heartbeat_period: 1; /*INC_HEARTBEAT_PERIOD*/ + uint32_t dec_heartbeat_width: 1; /*DEC_HEARTBEAT_WIDTH*/ + uint32_t rst_bias_i2c: 1; /*RST_BIAS_I2C*/ + }; + uint32_t val; + } bias_conf; + union { + struct { + uint32_t reserved0: 7; + uint32_t sck_dcap_force: 1; /*N/A*/ + uint32_t dig_dbias_slp: 3; /*DIG_REG_DBIAS during sleep*/ + uint32_t dig_dbias_wak: 3; /*DIG_REG_DBIAS during wakeup*/ + uint32_t sck_dcap: 8; /*SCK_DCAP*/ + uint32_t rtc_dbias_slp: 3; /*RTC_DBIAS during sleep*/ + uint32_t rtc_dbias_wak: 3; /*RTC_DBIAS during wakeup*/ + uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ + uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ + uint32_t rtc_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ + uint32_t rtc_force_pu: 1; /*RTC_REG force power up*/ + }; + uint32_t val; + } rtc; + union { + struct { + uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/ + uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/ + uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/ + uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/ + uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/ + uint32_t force_noiso: 1; /*rtc_peri force no ISO*/ + uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine*/ + uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/ + uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/ + uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ + uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/ + uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/ + uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/ + uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/ + uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/ + uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/ + uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/ + uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/ + uint32_t pwc_force_pd: 1; /*rtc_peri force power down*/ + uint32_t pwc_force_pu: 1; /*rtc_peri force power up*/ + uint32_t pd_en: 1; /*enable power down rtc_peri in sleep*/ + uint32_t reserved21: 11; + }; + uint32_t val; + } rtc_pwc; + union { + struct { + uint32_t reserved0: 3; + uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ + uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ + uint32_t rom0_force_pd: 1; /*ROM force power down*/ + uint32_t rom0_force_pu: 1; /*ROM force power up*/ + uint32_t inter_ram0_force_pd: 1; /*internal SRAM 0 force power down*/ + uint32_t inter_ram0_force_pu: 1; /*internal SRAM 0 force power up*/ + uint32_t inter_ram1_force_pd: 1; /*internal SRAM 1 force power down*/ + uint32_t inter_ram1_force_pu: 1; /*internal SRAM 1 force power up*/ + uint32_t inter_ram2_force_pd: 1; /*internal SRAM 2 force power down*/ + uint32_t inter_ram2_force_pu: 1; /*internal SRAM 2 force power up*/ + uint32_t inter_ram3_force_pd: 1; /*internal SRAM 3 force power down*/ + uint32_t inter_ram3_force_pu: 1; /*internal SRAM 3 force power up*/ + uint32_t inter_ram4_force_pd: 1; /*internal SRAM 4 force power down*/ + uint32_t inter_ram4_force_pu: 1; /*internal SRAM 4 force power up*/ + uint32_t wifi_force_pd: 1; /*wifi force power down*/ + uint32_t wifi_force_pu: 1; /*wifi force power up*/ + uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/ + uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/ + uint32_t reserved21: 3; + uint32_t rom0_pd_en: 1; /*enable power down ROM in sleep*/ + uint32_t inter_ram0_pd_en: 1; /*enable power down internal SRAM 0 in sleep*/ + uint32_t inter_ram1_pd_en: 1; /*enable power down internal SRAM 1 in sleep*/ + uint32_t inter_ram2_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/ + uint32_t inter_ram3_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/ + uint32_t inter_ram4_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/ + uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ + uint32_t dg_wrap_pd_en: 1; /*enable power down digital core in sleep*/ + }; + uint32_t val; + } dig_pwc; + union { + struct { + uint32_t reserved0: 7; + uint32_t dig_iso_force_off: 1; + uint32_t dig_iso_force_on: 1; + uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ + uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ + uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ + uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ + uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ + uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ + uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ + uint32_t rom0_force_iso: 1; /*ROM force ISO*/ + uint32_t rom0_force_noiso: 1; /*ROM force no ISO*/ + uint32_t inter_ram0_force_iso: 1; /*internal SRAM 0 force ISO*/ + uint32_t inter_ram0_force_noiso: 1; /*internal SRAM 0 force no ISO*/ + uint32_t inter_ram1_force_iso: 1; /*internal SRAM 1 force ISO*/ + uint32_t inter_ram1_force_noiso: 1; /*internal SRAM 1 force no ISO*/ + uint32_t inter_ram2_force_iso: 1; /*internal SRAM 2 force ISO*/ + uint32_t inter_ram2_force_noiso: 1; /*internal SRAM 2 force no ISO*/ + uint32_t inter_ram3_force_iso: 1; /*internal SRAM 3 force ISO*/ + uint32_t inter_ram3_force_noiso: 1; /*internal SRAM 3 force no ISO*/ + uint32_t inter_ram4_force_iso: 1; /*internal SRAM 4 force ISO*/ + uint32_t inter_ram4_force_noiso: 1; /*internal SRAM 4 force no ISO*/ + uint32_t wifi_force_iso: 1; /*wifi force ISO*/ + uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ + uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ + uint32_t dg_wrap_force_noiso: 1; /*digital core force no ISO*/ + }; + uint32_t val; + } dig_iso; + union { + struct { + uint32_t reserved0: 7; + uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ + uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ + uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ + uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ + uint32_t sys_reset_length: 3; /*system reset counter length*/ + uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ + uint32_t level_int_en: 1; /*N/A*/ + uint32_t edge_int_en: 1; /*N/A*/ + uint32_t stg3: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg2: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg1: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg0: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t en: 1; /*enable RTC WDT*/ + }; + uint32_t val; + } wdt_config0; + uint32_t wdt_config1; /**/ + uint32_t wdt_config2; /**/ + uint32_t wdt_config3; /**/ + uint32_t wdt_config4; /**/ + union { + struct { + uint32_t reserved0: 31; + uint32_t feed: 1; + }; + uint32_t val; + } wdt_feed; + uint32_t wdt_wprotect; /**/ + union { + struct { + uint32_t reserved0: 29; + uint32_t ent_rtc: 1; /*ENT_RTC*/ + uint32_t dtest_rtc: 2; /*DTEST_RTC*/ + }; + uint32_t val; + } test_mux; + union { + struct { + uint32_t reserved0: 20; + uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t procpu_c1: 6; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + }; + uint32_t val; + } sw_cpu_stall; + uint32_t store4; /*32-bit general purpose retention register*/ + uint32_t store5; /*32-bit general purpose retention register*/ + uint32_t store6; /*32-bit general purpose retention register*/ + uint32_t store7; /*32-bit general purpose retention register*/ + uint32_t diag0; /**/ + uint32_t diag1; /**/ + union { + struct { + uint32_t adc1_hold_force: 1; + uint32_t adc2_hold_force: 1; + uint32_t pdac1_hold_force: 1; + uint32_t pdac2_hold_force: 1; + uint32_t sense1_hold_force: 1; + uint32_t sense2_hold_force: 1; + uint32_t sense3_hold_force: 1; + uint32_t sense4_hold_force: 1; + uint32_t touch_pad0_hold_force: 1; + uint32_t touch_pad1_hold_force: 1; + uint32_t touch_pad2_hold_force: 1; + uint32_t touch_pad3_hold_force: 1; + uint32_t touch_pad4_hold_force: 1; + uint32_t touch_pad5_hold_force: 1; + uint32_t touch_pad6_hold_force: 1; + uint32_t touch_pad7_hold_force: 1; + uint32_t x32p_hold_force: 1; + uint32_t x32n_hold_force: 1; + uint32_t reserved18: 14; + }; + uint32_t val; + } hold_force; + union { + struct { + uint32_t ext_wakeup1_sel: 18; /*Bitmap to select RTC pads for ext wakeup1*/ + uint32_t ext_wakeup1_status_clr: 1; /*clear ext wakeup1 status*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } ext_wakeup1; + union { + struct { + uint32_t ext_wakeup1_status:18; /*ext wakeup1 status*/ + uint32_t reserved18: 14; + }; + uint32_t val; + } ext_wakeup1_status; + union { + struct { + uint32_t reserved0: 14; + uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ + uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ + uint32_t rst_wait: 10; /*brown out reset wait cycles*/ + uint32_t rst_ena: 1; /*enable brown out reset*/ + uint32_t thres: 3; /*brown out threshold*/ + uint32_t ena: 1; /*enable brown out*/ + uint32_t det: 1; /*brown out detect*/ + }; + uint32_t val; + } brown_out; + uint32_t reserved_39; + uint32_t reserved_3d; + uint32_t reserved_41; + uint32_t reserved_45; + uint32_t reserved_49; + uint32_t reserved_4d; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_cntl_dev_t; +#endif /* _SOC_RTC_CNTL_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/rtc_io_reg.h b/tools/sdk/include/soc/soc/rtc_io_reg.h similarity index 98% rename from tools/sdk/include/esp32/soc/rtc_io_reg.h rename to tools/sdk/include/soc/soc/rtc_io_reg.h index 345bb804..f6d0dac7 100644 --- a/tools/sdk/include/esp32/soc/rtc_io_reg.h +++ b/tools/sdk/include/soc/soc/rtc_io_reg.h @@ -1,1951 +1,1953 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RTC_IO_REG_H_ -#define _SOC_RTC_IO_REG_H_ - - -#include "soc.h" -#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) -/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output value*/ -#define RTC_GPIO_OUT_DATA 0x0003FFFF -#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S)) -#define RTC_GPIO_OUT_DATA_V 0x3FFFF -#define RTC_GPIO_OUT_DATA_S 14 - -#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) -/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output value write 1 to set*/ -#define RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF -#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S)) -#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFF -#define RTC_GPIO_OUT_DATA_W1TS_S 14 - -#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) -/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output value write 1 to clear*/ -#define RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF -#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S)) -#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFF -#define RTC_GPIO_OUT_DATA_W1TC_S 14 - -#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) -/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output enable*/ -#define RTC_GPIO_ENABLE 0x0003FFFF -#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S)) -#define RTC_GPIO_ENABLE_V 0x3FFFF -#define RTC_GPIO_ENABLE_S 14 - -#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) -/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output enable write 1 to set*/ -#define RTC_GPIO_ENABLE_W1TS 0x0003FFFF -#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S)) -#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFF -#define RTC_GPIO_ENABLE_W1TS_S 14 - -#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) -/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output enable write 1 to clear*/ -#define RTC_GPIO_ENABLE_W1TC 0x0003FFFF -#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S)) -#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFF -#define RTC_GPIO_ENABLE_W1TC_S 14 - -#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) -/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 interrupt status*/ -#define RTC_GPIO_STATUS_INT 0x0003FFFF -#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S)) -#define RTC_GPIO_STATUS_INT_V 0x3FFFF -#define RTC_GPIO_STATUS_INT_S 14 - -#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) -/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 interrupt status write 1 to set*/ -#define RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF -#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S)) -#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFF -#define RTC_GPIO_STATUS_INT_W1TS_S 14 - -#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) -/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 interrupt status write 1 to clear*/ -#define RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF -#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S)) -#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFF -#define RTC_GPIO_STATUS_INT_W1TC_S 14 - -#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) -/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default: ; */ -/*description: GPIO0~17 input value*/ -#define RTC_GPIO_IN_NEXT 0x0003FFFF -#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S)) -#define RTC_GPIO_IN_NEXT_V 0x3FFFF -#define RTC_GPIO_IN_NEXT_S 14 - -#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) -/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN0_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S)) -#define RTC_GPIO_PIN0_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN0_INT_TYPE_S 7 -/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN0_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) -/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN1_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S)) -#define RTC_GPIO_PIN1_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN1_INT_TYPE_S 7 -/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN1_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) -/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN2_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S)) -#define RTC_GPIO_PIN2_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN2_INT_TYPE_S 7 -/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN2_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) -/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN3_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S)) -#define RTC_GPIO_PIN3_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN3_INT_TYPE_S 7 -/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN3_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) -/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN4_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S)) -#define RTC_GPIO_PIN4_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN4_INT_TYPE_S 7 -/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN4_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) -/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN5_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S)) -#define RTC_GPIO_PIN5_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN5_INT_TYPE_S 7 -/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN5_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) -/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN6_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S)) -#define RTC_GPIO_PIN6_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN6_INT_TYPE_S 7 -/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN6_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) -/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN7_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S)) -#define RTC_GPIO_PIN7_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN7_INT_TYPE_S 7 -/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN7_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) -/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN8_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S)) -#define RTC_GPIO_PIN8_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN8_INT_TYPE_S 7 -/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN8_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) -/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN9_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S)) -#define RTC_GPIO_PIN9_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN9_INT_TYPE_S 7 -/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN9_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) -/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN10_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S)) -#define RTC_GPIO_PIN10_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN10_INT_TYPE_S 7 -/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN10_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) -/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN11_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S)) -#define RTC_GPIO_PIN11_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN11_INT_TYPE_S 7 -/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN11_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) -/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN12_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S)) -#define RTC_GPIO_PIN12_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN12_INT_TYPE_S 7 -/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN12_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) -/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN13_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S)) -#define RTC_GPIO_PIN13_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN13_INT_TYPE_S 7 -/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN13_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) -/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN14_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S)) -#define RTC_GPIO_PIN14_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN14_INT_TYPE_S 7 -/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN14_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) -/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN15_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S)) -#define RTC_GPIO_PIN15_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN15_INT_TYPE_S 7 -/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN15_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) -/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN16_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S)) -#define RTC_GPIO_PIN16_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN16_INT_TYPE_S 7 -/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN16_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) -/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN17_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S)) -#define RTC_GPIO_PIN17_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN17_INT_TYPE_S 7 -/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN17_PAD_DRIVER_S 2 - -#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70) -/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25)) -#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25)) -#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1 -#define RTC_IO_DEBUG_12M_NO_GATING_S 25 -/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL4 0x0000001F -#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S)) -#define RTC_IO_DEBUG_SEL4_V 0x1F -#define RTC_IO_DEBUG_SEL4_S 20 -/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL3 0x0000001F -#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S)) -#define RTC_IO_DEBUG_SEL3_V 0x1F -#define RTC_IO_DEBUG_SEL3_S 15 -/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL2 0x0000001F -#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S)) -#define RTC_IO_DEBUG_SEL2_V 0x1F -#define RTC_IO_DEBUG_SEL2_S 10 -/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL1 0x0000001F -#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S)) -#define RTC_IO_DEBUG_SEL1_V 0x1F -#define RTC_IO_DEBUG_SEL1_S 5 -/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL0 0x0000001F -#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S)) -#define RTC_IO_DEBUG_SEL0_V 0x1F -#define RTC_IO_DEBUG_SEL0_S 0 - -#define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74) -/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */ -/*description: select the digital pad hold value.*/ -#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF -#define RTC_IO_DIG_PAD_HOLD_M ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S)) -#define RTC_IO_DIG_PAD_HOLD_V 0xFFFFFFFF -#define RTC_IO_DIG_PAD_HOLD_S 0 - -#define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78) -/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: Power on hall sensor and connect to VP and VN*/ -#define RTC_IO_XPD_HALL (BIT(31)) -#define RTC_IO_XPD_HALL_M (BIT(31)) -#define RTC_IO_XPD_HALL_V 0x1 -#define RTC_IO_XPD_HALL_S 31 -/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: Reverse phase of hall sensor*/ -#define RTC_IO_HALL_PHASE (BIT(30)) -#define RTC_IO_HALL_PHASE_M (BIT(30)) -#define RTC_IO_HALL_PHASE_V 0x1 -#define RTC_IO_HALL_PHASE_S 30 - -#define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c) -/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_SENSE1_HOLD (BIT(31)) -#define RTC_IO_SENSE1_HOLD_M (BIT(31)) -#define RTC_IO_SENSE1_HOLD_V 0x1 -#define RTC_IO_SENSE1_HOLD_S 31 -/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_SENSE2_HOLD (BIT(30)) -#define RTC_IO_SENSE2_HOLD_M (BIT(30)) -#define RTC_IO_SENSE2_HOLD_V 0x1 -#define RTC_IO_SENSE2_HOLD_S 30 -/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_SENSE3_HOLD (BIT(29)) -#define RTC_IO_SENSE3_HOLD_M (BIT(29)) -#define RTC_IO_SENSE3_HOLD_V 0x1 -#define RTC_IO_SENSE3_HOLD_S 29 -/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_SENSE4_HOLD (BIT(28)) -#define RTC_IO_SENSE4_HOLD_M (BIT(28)) -#define RTC_IO_SENSE4_HOLD_V 0x1 -#define RTC_IO_SENSE4_HOLD_S 28 -/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_SENSE1_MUX_SEL (BIT(27)) -#define RTC_IO_SENSE1_MUX_SEL_M (BIT(27)) -#define RTC_IO_SENSE1_MUX_SEL_V 0x1 -#define RTC_IO_SENSE1_MUX_SEL_S 27 -/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_SENSE2_MUX_SEL (BIT(26)) -#define RTC_IO_SENSE2_MUX_SEL_M (BIT(26)) -#define RTC_IO_SENSE2_MUX_SEL_V 0x1 -#define RTC_IO_SENSE2_MUX_SEL_S 26 -/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_SENSE3_MUX_SEL (BIT(25)) -#define RTC_IO_SENSE3_MUX_SEL_M (BIT(25)) -#define RTC_IO_SENSE3_MUX_SEL_V 0x1 -#define RTC_IO_SENSE3_MUX_SEL_S 25 -/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_SENSE4_MUX_SEL (BIT(24)) -#define RTC_IO_SENSE4_MUX_SEL_M (BIT(24)) -#define RTC_IO_SENSE4_MUX_SEL_V 0x1 -#define RTC_IO_SENSE4_MUX_SEL_S 24 -/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_SENSE1_FUN_SEL 0x00000003 -#define RTC_IO_SENSE1_FUN_SEL_M ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S)) -#define RTC_IO_SENSE1_FUN_SEL_V 0x3 -#define RTC_IO_SENSE1_FUN_SEL_S 22 -/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_SENSE1_SLP_SEL (BIT(21)) -#define RTC_IO_SENSE1_SLP_SEL_M (BIT(21)) -#define RTC_IO_SENSE1_SLP_SEL_V 0x1 -#define RTC_IO_SENSE1_SLP_SEL_S 21 -/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_SENSE1_SLP_IE (BIT(20)) -#define RTC_IO_SENSE1_SLP_IE_M (BIT(20)) -#define RTC_IO_SENSE1_SLP_IE_V 0x1 -#define RTC_IO_SENSE1_SLP_IE_S 20 -/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_SENSE1_FUN_IE (BIT(19)) -#define RTC_IO_SENSE1_FUN_IE_M (BIT(19)) -#define RTC_IO_SENSE1_FUN_IE_V 0x1 -#define RTC_IO_SENSE1_FUN_IE_S 19 -/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_SENSE2_FUN_SEL 0x00000003 -#define RTC_IO_SENSE2_FUN_SEL_M ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S)) -#define RTC_IO_SENSE2_FUN_SEL_V 0x3 -#define RTC_IO_SENSE2_FUN_SEL_S 17 -/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_SENSE2_SLP_SEL (BIT(16)) -#define RTC_IO_SENSE2_SLP_SEL_M (BIT(16)) -#define RTC_IO_SENSE2_SLP_SEL_V 0x1 -#define RTC_IO_SENSE2_SLP_SEL_S 16 -/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_SENSE2_SLP_IE (BIT(15)) -#define RTC_IO_SENSE2_SLP_IE_M (BIT(15)) -#define RTC_IO_SENSE2_SLP_IE_V 0x1 -#define RTC_IO_SENSE2_SLP_IE_S 15 -/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_SENSE2_FUN_IE (BIT(14)) -#define RTC_IO_SENSE2_FUN_IE_M (BIT(14)) -#define RTC_IO_SENSE2_FUN_IE_V 0x1 -#define RTC_IO_SENSE2_FUN_IE_S 14 -/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_SENSE3_FUN_SEL 0x00000003 -#define RTC_IO_SENSE3_FUN_SEL_M ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S)) -#define RTC_IO_SENSE3_FUN_SEL_V 0x3 -#define RTC_IO_SENSE3_FUN_SEL_S 12 -/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_SENSE3_SLP_SEL (BIT(11)) -#define RTC_IO_SENSE3_SLP_SEL_M (BIT(11)) -#define RTC_IO_SENSE3_SLP_SEL_V 0x1 -#define RTC_IO_SENSE3_SLP_SEL_S 11 -/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_SENSE3_SLP_IE (BIT(10)) -#define RTC_IO_SENSE3_SLP_IE_M (BIT(10)) -#define RTC_IO_SENSE3_SLP_IE_V 0x1 -#define RTC_IO_SENSE3_SLP_IE_S 10 -/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_SENSE3_FUN_IE (BIT(9)) -#define RTC_IO_SENSE3_FUN_IE_M (BIT(9)) -#define RTC_IO_SENSE3_FUN_IE_V 0x1 -#define RTC_IO_SENSE3_FUN_IE_S 9 -/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_SENSE4_FUN_SEL 0x00000003 -#define RTC_IO_SENSE4_FUN_SEL_M ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S)) -#define RTC_IO_SENSE4_FUN_SEL_V 0x3 -#define RTC_IO_SENSE4_FUN_SEL_S 7 -/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_SENSE4_SLP_SEL (BIT(6)) -#define RTC_IO_SENSE4_SLP_SEL_M (BIT(6)) -#define RTC_IO_SENSE4_SLP_SEL_V 0x1 -#define RTC_IO_SENSE4_SLP_SEL_S 6 -/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_SENSE4_SLP_IE (BIT(5)) -#define RTC_IO_SENSE4_SLP_IE_M (BIT(5)) -#define RTC_IO_SENSE4_SLP_IE_V 0x1 -#define RTC_IO_SENSE4_SLP_IE_S 5 -/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_SENSE4_FUN_IE (BIT(4)) -#define RTC_IO_SENSE4_FUN_IE_M (BIT(4)) -#define RTC_IO_SENSE4_FUN_IE_V 0x1 -#define RTC_IO_SENSE4_FUN_IE_S 4 - -#define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80) -/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_ADC1_HOLD (BIT(31)) -#define RTC_IO_ADC1_HOLD_M (BIT(31)) -#define RTC_IO_ADC1_HOLD_V 0x1 -#define RTC_IO_ADC1_HOLD_S 31 -/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_ADC2_HOLD (BIT(30)) -#define RTC_IO_ADC2_HOLD_M (BIT(30)) -#define RTC_IO_ADC2_HOLD_V 0x1 -#define RTC_IO_ADC2_HOLD_S 30 -/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_ADC1_MUX_SEL (BIT(29)) -#define RTC_IO_ADC1_MUX_SEL_M (BIT(29)) -#define RTC_IO_ADC1_MUX_SEL_V 0x1 -#define RTC_IO_ADC1_MUX_SEL_S 29 -/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_ADC2_MUX_SEL (BIT(28)) -#define RTC_IO_ADC2_MUX_SEL_M (BIT(28)) -#define RTC_IO_ADC2_MUX_SEL_V 0x1 -#define RTC_IO_ADC2_MUX_SEL_S 28 -/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_ADC1_FUN_SEL 0x00000003 -#define RTC_IO_ADC1_FUN_SEL_M ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S)) -#define RTC_IO_ADC1_FUN_SEL_V 0x3 -#define RTC_IO_ADC1_FUN_SEL_S 26 -/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_ADC1_SLP_SEL (BIT(25)) -#define RTC_IO_ADC1_SLP_SEL_M (BIT(25)) -#define RTC_IO_ADC1_SLP_SEL_V 0x1 -#define RTC_IO_ADC1_SLP_SEL_S 25 -/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_ADC1_SLP_IE (BIT(24)) -#define RTC_IO_ADC1_SLP_IE_M (BIT(24)) -#define RTC_IO_ADC1_SLP_IE_V 0x1 -#define RTC_IO_ADC1_SLP_IE_S 24 -/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_ADC1_FUN_IE (BIT(23)) -#define RTC_IO_ADC1_FUN_IE_M (BIT(23)) -#define RTC_IO_ADC1_FUN_IE_V 0x1 -#define RTC_IO_ADC1_FUN_IE_S 23 -/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_ADC2_FUN_SEL 0x00000003 -#define RTC_IO_ADC2_FUN_SEL_M ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S)) -#define RTC_IO_ADC2_FUN_SEL_V 0x3 -#define RTC_IO_ADC2_FUN_SEL_S 21 -/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_ADC2_SLP_SEL (BIT(20)) -#define RTC_IO_ADC2_SLP_SEL_M (BIT(20)) -#define RTC_IO_ADC2_SLP_SEL_V 0x1 -#define RTC_IO_ADC2_SLP_SEL_S 20 -/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_ADC2_SLP_IE (BIT(19)) -#define RTC_IO_ADC2_SLP_IE_M (BIT(19)) -#define RTC_IO_ADC2_SLP_IE_V 0x1 -#define RTC_IO_ADC2_SLP_IE_S 19 -/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_ADC2_FUN_IE (BIT(18)) -#define RTC_IO_ADC2_FUN_IE_M (BIT(18)) -#define RTC_IO_ADC2_FUN_IE_V 0x1 -#define RTC_IO_ADC2_FUN_IE_S 18 - -#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84) -/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_PDAC1_DRV 0x00000003 -#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S)) -#define RTC_IO_PDAC1_DRV_V 0x3 -#define RTC_IO_PDAC1_DRV_S 30 -/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_PDAC1_HOLD (BIT(29)) -#define RTC_IO_PDAC1_HOLD_M (BIT(29)) -#define RTC_IO_PDAC1_HOLD_V 0x1 -#define RTC_IO_PDAC1_HOLD_S 29 -/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_PDAC1_RDE (BIT(28)) -#define RTC_IO_PDAC1_RDE_M (BIT(28)) -#define RTC_IO_PDAC1_RDE_V 0x1 -#define RTC_IO_PDAC1_RDE_S 28 -/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_PDAC1_RUE (BIT(27)) -#define RTC_IO_PDAC1_RUE_M (BIT(27)) -#define RTC_IO_PDAC1_RUE_V 0x1 -#define RTC_IO_PDAC1_RUE_S 27 -/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ -/*description: PAD DAC1 control code.*/ -#define RTC_IO_PDAC1_DAC 0x000000FF -#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S)) -#define RTC_IO_PDAC1_DAC_V 0xFF -#define RTC_IO_PDAC1_DAC_S 19 -/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power - on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ -#define RTC_IO_PDAC1_XPD_DAC (BIT(18)) -#define RTC_IO_PDAC1_XPD_DAC_M (BIT(18)) -#define RTC_IO_PDAC1_XPD_DAC_V 0x1 -#define RTC_IO_PDAC1_XPD_DAC_S 18 -/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_PDAC1_MUX_SEL (BIT(17)) -#define RTC_IO_PDAC1_MUX_SEL_M (BIT(17)) -#define RTC_IO_PDAC1_MUX_SEL_V 0x1 -#define RTC_IO_PDAC1_MUX_SEL_S 17 -/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_PDAC1_FUN_SEL 0x00000003 -#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S)) -#define RTC_IO_PDAC1_FUN_SEL_V 0x3 -#define RTC_IO_PDAC1_FUN_SEL_S 15 -/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_PDAC1_SLP_SEL (BIT(14)) -#define RTC_IO_PDAC1_SLP_SEL_M (BIT(14)) -#define RTC_IO_PDAC1_SLP_SEL_V 0x1 -#define RTC_IO_PDAC1_SLP_SEL_S 14 -/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_PDAC1_SLP_IE (BIT(13)) -#define RTC_IO_PDAC1_SLP_IE_M (BIT(13)) -#define RTC_IO_PDAC1_SLP_IE_V 0x1 -#define RTC_IO_PDAC1_SLP_IE_S 13 -/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_PDAC1_SLP_OE (BIT(12)) -#define RTC_IO_PDAC1_SLP_OE_M (BIT(12)) -#define RTC_IO_PDAC1_SLP_OE_V 0x1 -#define RTC_IO_PDAC1_SLP_OE_S 12 -/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_PDAC1_FUN_IE (BIT(11)) -#define RTC_IO_PDAC1_FUN_IE_M (BIT(11)) -#define RTC_IO_PDAC1_FUN_IE_V 0x1 -#define RTC_IO_PDAC1_FUN_IE_S 11 -/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power - on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ -#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10)) -#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(10)) -#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1 -#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10 - -#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88) -/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_PDAC2_DRV 0x00000003 -#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S)) -#define RTC_IO_PDAC2_DRV_V 0x3 -#define RTC_IO_PDAC2_DRV_S 30 -/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_PDAC2_HOLD (BIT(29)) -#define RTC_IO_PDAC2_HOLD_M (BIT(29)) -#define RTC_IO_PDAC2_HOLD_V 0x1 -#define RTC_IO_PDAC2_HOLD_S 29 -/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_PDAC2_RDE (BIT(28)) -#define RTC_IO_PDAC2_RDE_M (BIT(28)) -#define RTC_IO_PDAC2_RDE_V 0x1 -#define RTC_IO_PDAC2_RDE_S 28 -/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_PDAC2_RUE (BIT(27)) -#define RTC_IO_PDAC2_RUE_M (BIT(27)) -#define RTC_IO_PDAC2_RUE_V 0x1 -#define RTC_IO_PDAC2_RUE_S 27 -/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ -/*description: PAD DAC2 control code.*/ -#define RTC_IO_PDAC2_DAC 0x000000FF -#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S)) -#define RTC_IO_PDAC2_DAC_V 0xFF -#define RTC_IO_PDAC2_DAC_S 19 -/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: Power on DAC2. Usually we need to tristate PDAC1 if we power - on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ -#define RTC_IO_PDAC2_XPD_DAC (BIT(18)) -#define RTC_IO_PDAC2_XPD_DAC_M (BIT(18)) -#define RTC_IO_PDAC2_XPD_DAC_V 0x1 -#define RTC_IO_PDAC2_XPD_DAC_S 18 -/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_PDAC2_MUX_SEL (BIT(17)) -#define RTC_IO_PDAC2_MUX_SEL_M (BIT(17)) -#define RTC_IO_PDAC2_MUX_SEL_V 0x1 -#define RTC_IO_PDAC2_MUX_SEL_S 17 -/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_PDAC2_FUN_SEL 0x00000003 -#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S)) -#define RTC_IO_PDAC2_FUN_SEL_V 0x3 -#define RTC_IO_PDAC2_FUN_SEL_S 15 -/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_PDAC2_SLP_SEL (BIT(14)) -#define RTC_IO_PDAC2_SLP_SEL_M (BIT(14)) -#define RTC_IO_PDAC2_SLP_SEL_V 0x1 -#define RTC_IO_PDAC2_SLP_SEL_S 14 -/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_PDAC2_SLP_IE (BIT(13)) -#define RTC_IO_PDAC2_SLP_IE_M (BIT(13)) -#define RTC_IO_PDAC2_SLP_IE_V 0x1 -#define RTC_IO_PDAC2_SLP_IE_S 13 -/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_PDAC2_SLP_OE (BIT(12)) -#define RTC_IO_PDAC2_SLP_OE_M (BIT(12)) -#define RTC_IO_PDAC2_SLP_OE_V 0x1 -#define RTC_IO_PDAC2_SLP_OE_S 12 -/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_PDAC2_FUN_IE (BIT(11)) -#define RTC_IO_PDAC2_FUN_IE_M (BIT(11)) -#define RTC_IO_PDAC2_FUN_IE_V 0x1 -#define RTC_IO_PDAC2_FUN_IE_S 11 -/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Power on DAC2. Usually we need to tristate PDAC2 if we power - on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ -#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10)) -#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(10)) -#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1 -#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10 - -#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) -/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_X32N_DRV 0x00000003 -#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S)) -#define RTC_IO_X32N_DRV_V 0x3 -#define RTC_IO_X32N_DRV_S 30 -/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_X32N_HOLD (BIT(29)) -#define RTC_IO_X32N_HOLD_M (BIT(29)) -#define RTC_IO_X32N_HOLD_V 0x1 -#define RTC_IO_X32N_HOLD_S 29 -/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_X32N_RDE (BIT(28)) -#define RTC_IO_X32N_RDE_M (BIT(28)) -#define RTC_IO_X32N_RDE_V 0x1 -#define RTC_IO_X32N_RDE_S 28 -/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_X32N_RUE (BIT(27)) -#define RTC_IO_X32N_RUE_M (BIT(27)) -#define RTC_IO_X32N_RUE_V 0x1 -#define RTC_IO_X32N_RUE_S 27 -/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_X32P_DRV 0x00000003 -#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S)) -#define RTC_IO_X32P_DRV_V 0x3 -#define RTC_IO_X32P_DRV_S 25 -/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_X32P_HOLD (BIT(24)) -#define RTC_IO_X32P_HOLD_M (BIT(24)) -#define RTC_IO_X32P_HOLD_V 0x1 -#define RTC_IO_X32P_HOLD_S 24 -/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_X32P_RDE (BIT(23)) -#define RTC_IO_X32P_RDE_M (BIT(23)) -#define RTC_IO_X32P_RDE_V 0x1 -#define RTC_IO_X32P_RDE_S 23 -/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_X32P_RUE (BIT(22)) -#define RTC_IO_X32P_RUE_M (BIT(22)) -#define RTC_IO_X32P_RUE_V 0x1 -#define RTC_IO_X32P_RUE_S 22 -/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */ -/*description: 32K XTAL bias current DAC.*/ -#define RTC_IO_DAC_XTAL_32K 0x00000003 -#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S)) -#define RTC_IO_DAC_XTAL_32K_V 0x3 -#define RTC_IO_DAC_XTAL_32K_S 20 -/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Power up 32kHz crystal oscillator*/ -#define RTC_IO_XPD_XTAL_32K (BIT(19)) -#define RTC_IO_XPD_XTAL_32K_M (BIT(19)) -#define RTC_IO_XPD_XTAL_32K_V 0x1 -#define RTC_IO_XPD_XTAL_32K_S 19 -/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_X32N_MUX_SEL (BIT(18)) -#define RTC_IO_X32N_MUX_SEL_M (BIT(18)) -#define RTC_IO_X32N_MUX_SEL_V 0x1 -#define RTC_IO_X32N_MUX_SEL_S 18 -/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_X32P_MUX_SEL (BIT(17)) -#define RTC_IO_X32P_MUX_SEL_M (BIT(17)) -#define RTC_IO_X32P_MUX_SEL_V 0x1 -#define RTC_IO_X32P_MUX_SEL_S 17 -/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_X32N_FUN_SEL 0x00000003 -#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S)) -#define RTC_IO_X32N_FUN_SEL_V 0x3 -#define RTC_IO_X32N_FUN_SEL_S 15 -/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_X32N_SLP_SEL (BIT(14)) -#define RTC_IO_X32N_SLP_SEL_M (BIT(14)) -#define RTC_IO_X32N_SLP_SEL_V 0x1 -#define RTC_IO_X32N_SLP_SEL_S 14 -/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_X32N_SLP_IE (BIT(13)) -#define RTC_IO_X32N_SLP_IE_M (BIT(13)) -#define RTC_IO_X32N_SLP_IE_V 0x1 -#define RTC_IO_X32N_SLP_IE_S 13 -/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_X32N_SLP_OE (BIT(12)) -#define RTC_IO_X32N_SLP_OE_M (BIT(12)) -#define RTC_IO_X32N_SLP_OE_V 0x1 -#define RTC_IO_X32N_SLP_OE_S 12 -/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_X32N_FUN_IE (BIT(11)) -#define RTC_IO_X32N_FUN_IE_M (BIT(11)) -#define RTC_IO_X32N_FUN_IE_V 0x1 -#define RTC_IO_X32N_FUN_IE_S 11 -/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_X32P_FUN_SEL 0x00000003 -#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S)) -#define RTC_IO_X32P_FUN_SEL_V 0x3 -#define RTC_IO_X32P_FUN_SEL_S 9 -/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_X32P_SLP_SEL (BIT(8)) -#define RTC_IO_X32P_SLP_SEL_M (BIT(8)) -#define RTC_IO_X32P_SLP_SEL_V 0x1 -#define RTC_IO_X32P_SLP_SEL_S 8 -/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_X32P_SLP_IE (BIT(7)) -#define RTC_IO_X32P_SLP_IE_M (BIT(7)) -#define RTC_IO_X32P_SLP_IE_V 0x1 -#define RTC_IO_X32P_SLP_IE_S 7 -/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_X32P_SLP_OE (BIT(6)) -#define RTC_IO_X32P_SLP_OE_M (BIT(6)) -#define RTC_IO_X32P_SLP_OE_V 0x1 -#define RTC_IO_X32P_SLP_OE_S 6 -/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_X32P_FUN_IE (BIT(5)) -#define RTC_IO_X32P_FUN_IE_M (BIT(5)) -#define RTC_IO_X32P_FUN_IE_V 0x1 -#define RTC_IO_X32P_FUN_IE_S 5 -/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */ -/*description: 32K XTAL resistor bias control.*/ -#define RTC_IO_DRES_XTAL_32K 0x00000003 -#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S)) -#define RTC_IO_DRES_XTAL_32K_V 0x3 -#define RTC_IO_DRES_XTAL_32K_S 3 -/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */ -/*description: 32K XTAL self-bias reference control.*/ -#define RTC_IO_DBIAS_XTAL_32K 0x00000003 -#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S)) -#define RTC_IO_DBIAS_XTAL_32K_V 0x3 -#define RTC_IO_DBIAS_XTAL_32K_S 1 - -#define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90) -/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: touch sensor bias power on.*/ -#define RTC_IO_TOUCH_XPD_BIAS (BIT(31)) -#define RTC_IO_TOUCH_XPD_BIAS_M (BIT(31)) -#define RTC_IO_TOUCH_XPD_BIAS_V 0x1 -#define RTC_IO_TOUCH_XPD_BIAS_S 31 -/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */ -/*description: touch sensor saw wave top voltage.*/ -#define RTC_IO_TOUCH_DREFH 0x00000003 -#define RTC_IO_TOUCH_DREFH_M ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S)) -#define RTC_IO_TOUCH_DREFH_V 0x3 -#define RTC_IO_TOUCH_DREFH_S 29 -/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ -/*description: touch sensor saw wave bottom voltage.*/ -#define RTC_IO_TOUCH_DREFL 0x00000003 -#define RTC_IO_TOUCH_DREFL_M ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S)) -#define RTC_IO_TOUCH_DREFL_V 0x3 -#define RTC_IO_TOUCH_DREFL_S 27 -/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */ -/*description: touch sensor saw wave voltage range.*/ -#define RTC_IO_TOUCH_DRANGE 0x00000003 -#define RTC_IO_TOUCH_DRANGE_M ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S)) -#define RTC_IO_TOUCH_DRANGE_V 0x3 -#define RTC_IO_TOUCH_DRANGE_S 25 -/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */ -/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When - BIAS_SLEEP this setting is available*/ -#define RTC_IO_TOUCH_DCUR 0x00000003 -#define RTC_IO_TOUCH_DCUR_M ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S)) -#define RTC_IO_TOUCH_DCUR_V 0x3 -#define RTC_IO_TOUCH_DCUR_S 23 - -#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94) -/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD0_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD0_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD0_HOLD_S 31 -/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD0_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S)) -#define RTC_IO_TOUCH_PAD0_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD0_DRV_S 29 -/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD0_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD0_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD0_RDE_S 28 -/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD0_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD0_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD0_RUE_S 27 -/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD0_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S)) -#define RTC_IO_TOUCH_PAD0_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD0_DAC_S 23 -/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD0_START (BIT(22)) -#define RTC_IO_TOUCH_PAD0_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD0_START_V 0x1 -#define RTC_IO_TOUCH_PAD0_START_S 22 -/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD0_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD0_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD0_XPD_S 20 -/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/ -#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD0_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD0_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98) -/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD1_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD1_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD1_HOLD_S 31 -/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD1_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S)) -#define RTC_IO_TOUCH_PAD1_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD1_DRV_S 29 -/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD1_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD1_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD1_RDE_S 28 -/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD1_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD1_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD1_RUE_S 27 -/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD1_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S)) -#define RTC_IO_TOUCH_PAD1_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD1_DAC_S 23 -/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD1_START (BIT(22)) -#define RTC_IO_TOUCH_PAD1_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD1_START_V 0x1 -#define RTC_IO_TOUCH_PAD1_START_S 22 -/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD1_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD1_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD1_XPD_S 20 -/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/ -#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c) -/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD2_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD2_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD2_HOLD_S 31 -/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD2_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S)) -#define RTC_IO_TOUCH_PAD2_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD2_DRV_S 29 -/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD2_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD2_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD2_RDE_S 28 -/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD2_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD2_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD2_RUE_S 27 -/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD2_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S)) -#define RTC_IO_TOUCH_PAD2_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD2_DAC_S 23 -/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD2_START (BIT(22)) -#define RTC_IO_TOUCH_PAD2_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD2_START_V 0x1 -#define RTC_IO_TOUCH_PAD2_START_S 22 -/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD2_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD2_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD2_XPD_S 20 -/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/ -#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0) -/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD3_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD3_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD3_HOLD_S 31 -/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD3_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S)) -#define RTC_IO_TOUCH_PAD3_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD3_DRV_S 29 -/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD3_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD3_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD3_RDE_S 28 -/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD3_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD3_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD3_RUE_S 27 -/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD3_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S)) -#define RTC_IO_TOUCH_PAD3_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD3_DAC_S 23 -/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD3_START (BIT(22)) -#define RTC_IO_TOUCH_PAD3_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD3_START_V 0x1 -#define RTC_IO_TOUCH_PAD3_START_S 22 -/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD3_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD3_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD3_XPD_S 20 -/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/ -#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4) -/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD4_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD4_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD4_HOLD_S 31 -/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD4_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S)) -#define RTC_IO_TOUCH_PAD4_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD4_DRV_S 29 -/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD4_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD4_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD4_RDE_S 28 -/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD4_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD4_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD4_RUE_S 27 -/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD4_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S)) -#define RTC_IO_TOUCH_PAD4_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD4_DAC_S 23 -/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD4_START (BIT(22)) -#define RTC_IO_TOUCH_PAD4_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD4_START_V 0x1 -#define RTC_IO_TOUCH_PAD4_START_S 22 -/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD4_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD4_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD4_XPD_S 20 -/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/ -#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8) -/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD5_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD5_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD5_HOLD_S 31 -/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD5_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S)) -#define RTC_IO_TOUCH_PAD5_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD5_DRV_S 29 -/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD5_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD5_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD5_RDE_S 28 -/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD5_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD5_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD5_RUE_S 27 -/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD5_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S)) -#define RTC_IO_TOUCH_PAD5_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD5_DAC_S 23 -/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD5_START (BIT(22)) -#define RTC_IO_TOUCH_PAD5_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD5_START_V 0x1 -#define RTC_IO_TOUCH_PAD5_START_S 22 -/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD5_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD5_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD5_XPD_S 20 -/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/ -#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac) -/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD6_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD6_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD6_HOLD_S 31 -/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD6_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S)) -#define RTC_IO_TOUCH_PAD6_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD6_DRV_S 29 -/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD6_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD6_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD6_RDE_S 28 -/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD6_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD6_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD6_RUE_S 27 -/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD6_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S)) -#define RTC_IO_TOUCH_PAD6_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD6_DAC_S 23 -/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD6_START (BIT(22)) -#define RTC_IO_TOUCH_PAD6_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD6_START_V 0x1 -#define RTC_IO_TOUCH_PAD6_START_S 22 -/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD6_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD6_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD6_XPD_S 20 -/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/ -#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0) -/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD7_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD7_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD7_HOLD_S 31 -/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD7_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S)) -#define RTC_IO_TOUCH_PAD7_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD7_DRV_S 29 -/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD7_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD7_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD7_RDE_S 28 -/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD7_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD7_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD7_RUE_S 27 -/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD7_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S)) -#define RTC_IO_TOUCH_PAD7_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD7_DAC_S 23 -/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD7_START (BIT(22)) -#define RTC_IO_TOUCH_PAD7_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD7_START_V 0x1 -#define RTC_IO_TOUCH_PAD7_START_S 22 -/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD7_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD7_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD7_XPD_S 20 -/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/ -#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4) -/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD8_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S)) -#define RTC_IO_TOUCH_PAD8_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD8_DAC_S 23 -/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD8_START (BIT(22)) -#define RTC_IO_TOUCH_PAD8_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD8_START_V 0x1 -#define RTC_IO_TOUCH_PAD8_START_S 22 -/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD8_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD8_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD8_XPD_S 20 -/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ -#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19)) -#define RTC_IO_TOUCH_PAD8_TO_GPIO_M (BIT(19)) -#define RTC_IO_TOUCH_PAD8_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19 - -#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8) -/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD9_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S)) -#define RTC_IO_TOUCH_PAD9_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD9_DAC_S 23 -/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD9_START (BIT(22)) -#define RTC_IO_TOUCH_PAD9_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD9_START_V 0x1 -#define RTC_IO_TOUCH_PAD9_START_S 22 -/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD9_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD9_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD9_XPD_S 20 -/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ -#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19)) -#define RTC_IO_TOUCH_PAD9_TO_GPIO_M (BIT(19)) -#define RTC_IO_TOUCH_PAD9_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19 - -#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) -/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ -/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/ -#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F -#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S)) -#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F -#define RTC_IO_EXT_WAKEUP0_SEL_S 27 - -#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) -/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ -/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select - GPIO2 ...Ò17Ó select GPIO17*/ -#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F -#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S)) -#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F -#define RTC_IO_XTL_EXT_CTR_SEL_S 27 - -#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4) -/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/ -#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003 -#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S)) -#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3 -#define RTC_IO_SAR_I2C_SDA_SEL_S 30 -/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/ -#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003 -#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S)) -#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3 -#define RTC_IO_SAR_I2C_SCL_SEL_S 28 -/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */ -/*description: */ -#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F -#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S)) -#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F -#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23 - -#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8) -/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */ -/*description: date*/ -#define RTC_IO_IO_DATE 0x0FFFFFFF -#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S)) -#define RTC_IO_IO_DATE_V 0xFFFFFFF -#define RTC_IO_IO_DATE_S 0 -#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160 - - - - -#endif /*_SOC_RTC_IO_REG_H_ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_IO_REG_H_ +#define _SOC_RTC_IO_REG_H_ + + +#include "soc.h" +#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) +/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value*/ +#define RTC_GPIO_OUT_DATA 0x0003FFFF +#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S)) +#define RTC_GPIO_OUT_DATA_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_S 14 + +#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) +/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value write 1 to set*/ +#define RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF +#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S)) +#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_W1TS_S 14 + +#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) +/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value write 1 to clear*/ +#define RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF +#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S)) +#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_W1TC_S 14 + +#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) +/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable*/ +#define RTC_GPIO_ENABLE 0x0003FFFF +#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S)) +#define RTC_GPIO_ENABLE_V 0x3FFFF +#define RTC_GPIO_ENABLE_S 14 + +#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) +/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable write 1 to set*/ +#define RTC_GPIO_ENABLE_W1TS 0x0003FFFF +#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S)) +#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFF +#define RTC_GPIO_ENABLE_W1TS_S 14 + +#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) +/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable write 1 to clear*/ +#define RTC_GPIO_ENABLE_W1TC 0x0003FFFF +#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S)) +#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFF +#define RTC_GPIO_ENABLE_W1TC_S 14 + +#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) +/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status*/ +#define RTC_GPIO_STATUS_INT 0x0003FFFF +#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S)) +#define RTC_GPIO_STATUS_INT_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_S 14 + +#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) +/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status write 1 to set*/ +#define RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF +#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S)) +#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_W1TS_S 14 + +#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) +/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status write 1 to clear*/ +#define RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF +#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S)) +#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_W1TC_S 14 + +#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) +/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default: ; */ +/*description: GPIO0~17 input value*/ +#define RTC_GPIO_IN_NEXT 0x0003FFFF +#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S)) +#define RTC_GPIO_IN_NEXT_V 0x3FFFF +#define RTC_GPIO_IN_NEXT_S 14 + +#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) +/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S)) +#define RTC_GPIO_PIN0_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN0_INT_TYPE_S 7 +/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN0_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) +/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S)) +#define RTC_GPIO_PIN1_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN1_INT_TYPE_S 7 +/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN1_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) +/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S)) +#define RTC_GPIO_PIN2_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN2_INT_TYPE_S 7 +/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN2_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) +/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S)) +#define RTC_GPIO_PIN3_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN3_INT_TYPE_S 7 +/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN3_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) +/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S)) +#define RTC_GPIO_PIN4_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN4_INT_TYPE_S 7 +/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN4_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) +/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S)) +#define RTC_GPIO_PIN5_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN5_INT_TYPE_S 7 +/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN5_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) +/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN6_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S)) +#define RTC_GPIO_PIN6_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN6_INT_TYPE_S 7 +/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN6_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) +/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN7_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S)) +#define RTC_GPIO_PIN7_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN7_INT_TYPE_S 7 +/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN7_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) +/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN8_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S)) +#define RTC_GPIO_PIN8_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN8_INT_TYPE_S 7 +/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN8_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) +/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN9_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S)) +#define RTC_GPIO_PIN9_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN9_INT_TYPE_S 7 +/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN9_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) +/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN10_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S)) +#define RTC_GPIO_PIN10_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN10_INT_TYPE_S 7 +/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN10_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) +/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN11_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S)) +#define RTC_GPIO_PIN11_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN11_INT_TYPE_S 7 +/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN11_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) +/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN12_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S)) +#define RTC_GPIO_PIN12_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN12_INT_TYPE_S 7 +/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN12_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) +/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN13_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S)) +#define RTC_GPIO_PIN13_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN13_INT_TYPE_S 7 +/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN13_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) +/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN14_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S)) +#define RTC_GPIO_PIN14_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN14_INT_TYPE_S 7 +/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN14_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) +/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN15_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S)) +#define RTC_GPIO_PIN15_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN15_INT_TYPE_S 7 +/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN15_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) +/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN16_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S)) +#define RTC_GPIO_PIN16_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN16_INT_TYPE_S 7 +/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN16_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) +/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN17_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S)) +#define RTC_GPIO_PIN17_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN17_INT_TYPE_S 7 +/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN17_PAD_DRIVER_S 2 + +#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70) +/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1 +#define RTC_IO_DEBUG_12M_NO_GATING_S 25 +/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL4 0x0000001F +#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S)) +#define RTC_IO_DEBUG_SEL4_V 0x1F +#define RTC_IO_DEBUG_SEL4_S 20 +/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL3 0x0000001F +#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S)) +#define RTC_IO_DEBUG_SEL3_V 0x1F +#define RTC_IO_DEBUG_SEL3_S 15 +/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL2 0x0000001F +#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S)) +#define RTC_IO_DEBUG_SEL2_V 0x1F +#define RTC_IO_DEBUG_SEL2_S 10 +/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL1 0x0000001F +#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S)) +#define RTC_IO_DEBUG_SEL1_V 0x1F +#define RTC_IO_DEBUG_SEL1_S 5 +/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL0 0x0000001F +#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S)) +#define RTC_IO_DEBUG_SEL0_V 0x1F +#define RTC_IO_DEBUG_SEL0_S 0 +#define RTC_IO_DEBUG_SEL0_32K_XTAL 4 +#define RTC_IO_DEBUG_SEL0_150K_OSC 5 + +#define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74) +/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */ +/*description: select the digital pad hold value.*/ +#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_IO_DIG_PAD_HOLD_M ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S)) +#define RTC_IO_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_IO_DIG_PAD_HOLD_S 0 + +#define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78) +/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: Power on hall sensor and connect to VP and VN*/ +#define RTC_IO_XPD_HALL (BIT(31)) +#define RTC_IO_XPD_HALL_M (BIT(31)) +#define RTC_IO_XPD_HALL_V 0x1 +#define RTC_IO_XPD_HALL_S 31 +/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: Reverse phase of hall sensor*/ +#define RTC_IO_HALL_PHASE (BIT(30)) +#define RTC_IO_HALL_PHASE_M (BIT(30)) +#define RTC_IO_HALL_PHASE_V 0x1 +#define RTC_IO_HALL_PHASE_S 30 + +#define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c) +/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE1_HOLD (BIT(31)) +#define RTC_IO_SENSE1_HOLD_M (BIT(31)) +#define RTC_IO_SENSE1_HOLD_V 0x1 +#define RTC_IO_SENSE1_HOLD_S 31 +/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE2_HOLD (BIT(30)) +#define RTC_IO_SENSE2_HOLD_M (BIT(30)) +#define RTC_IO_SENSE2_HOLD_V 0x1 +#define RTC_IO_SENSE2_HOLD_S 30 +/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE3_HOLD (BIT(29)) +#define RTC_IO_SENSE3_HOLD_M (BIT(29)) +#define RTC_IO_SENSE3_HOLD_V 0x1 +#define RTC_IO_SENSE3_HOLD_S 29 +/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE4_HOLD (BIT(28)) +#define RTC_IO_SENSE4_HOLD_M (BIT(28)) +#define RTC_IO_SENSE4_HOLD_V 0x1 +#define RTC_IO_SENSE4_HOLD_S 28 +/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE1_MUX_SEL (BIT(27)) +#define RTC_IO_SENSE1_MUX_SEL_M (BIT(27)) +#define RTC_IO_SENSE1_MUX_SEL_V 0x1 +#define RTC_IO_SENSE1_MUX_SEL_S 27 +/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE2_MUX_SEL (BIT(26)) +#define RTC_IO_SENSE2_MUX_SEL_M (BIT(26)) +#define RTC_IO_SENSE2_MUX_SEL_V 0x1 +#define RTC_IO_SENSE2_MUX_SEL_S 26 +/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE3_MUX_SEL (BIT(25)) +#define RTC_IO_SENSE3_MUX_SEL_M (BIT(25)) +#define RTC_IO_SENSE3_MUX_SEL_V 0x1 +#define RTC_IO_SENSE3_MUX_SEL_S 25 +/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE4_MUX_SEL (BIT(24)) +#define RTC_IO_SENSE4_MUX_SEL_M (BIT(24)) +#define RTC_IO_SENSE4_MUX_SEL_V 0x1 +#define RTC_IO_SENSE4_MUX_SEL_S 24 +/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE1_FUN_SEL 0x00000003 +#define RTC_IO_SENSE1_FUN_SEL_M ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S)) +#define RTC_IO_SENSE1_FUN_SEL_V 0x3 +#define RTC_IO_SENSE1_FUN_SEL_S 22 +/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE1_SLP_SEL (BIT(21)) +#define RTC_IO_SENSE1_SLP_SEL_M (BIT(21)) +#define RTC_IO_SENSE1_SLP_SEL_V 0x1 +#define RTC_IO_SENSE1_SLP_SEL_S 21 +/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE1_SLP_IE (BIT(20)) +#define RTC_IO_SENSE1_SLP_IE_M (BIT(20)) +#define RTC_IO_SENSE1_SLP_IE_V 0x1 +#define RTC_IO_SENSE1_SLP_IE_S 20 +/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE1_FUN_IE (BIT(19)) +#define RTC_IO_SENSE1_FUN_IE_M (BIT(19)) +#define RTC_IO_SENSE1_FUN_IE_V 0x1 +#define RTC_IO_SENSE1_FUN_IE_S 19 +/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE2_FUN_SEL 0x00000003 +#define RTC_IO_SENSE2_FUN_SEL_M ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S)) +#define RTC_IO_SENSE2_FUN_SEL_V 0x3 +#define RTC_IO_SENSE2_FUN_SEL_S 17 +/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE2_SLP_SEL (BIT(16)) +#define RTC_IO_SENSE2_SLP_SEL_M (BIT(16)) +#define RTC_IO_SENSE2_SLP_SEL_V 0x1 +#define RTC_IO_SENSE2_SLP_SEL_S 16 +/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE2_SLP_IE (BIT(15)) +#define RTC_IO_SENSE2_SLP_IE_M (BIT(15)) +#define RTC_IO_SENSE2_SLP_IE_V 0x1 +#define RTC_IO_SENSE2_SLP_IE_S 15 +/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE2_FUN_IE (BIT(14)) +#define RTC_IO_SENSE2_FUN_IE_M (BIT(14)) +#define RTC_IO_SENSE2_FUN_IE_V 0x1 +#define RTC_IO_SENSE2_FUN_IE_S 14 +/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE3_FUN_SEL 0x00000003 +#define RTC_IO_SENSE3_FUN_SEL_M ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S)) +#define RTC_IO_SENSE3_FUN_SEL_V 0x3 +#define RTC_IO_SENSE3_FUN_SEL_S 12 +/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE3_SLP_SEL (BIT(11)) +#define RTC_IO_SENSE3_SLP_SEL_M (BIT(11)) +#define RTC_IO_SENSE3_SLP_SEL_V 0x1 +#define RTC_IO_SENSE3_SLP_SEL_S 11 +/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE3_SLP_IE (BIT(10)) +#define RTC_IO_SENSE3_SLP_IE_M (BIT(10)) +#define RTC_IO_SENSE3_SLP_IE_V 0x1 +#define RTC_IO_SENSE3_SLP_IE_S 10 +/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE3_FUN_IE (BIT(9)) +#define RTC_IO_SENSE3_FUN_IE_M (BIT(9)) +#define RTC_IO_SENSE3_FUN_IE_V 0x1 +#define RTC_IO_SENSE3_FUN_IE_S 9 +/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE4_FUN_SEL 0x00000003 +#define RTC_IO_SENSE4_FUN_SEL_M ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S)) +#define RTC_IO_SENSE4_FUN_SEL_V 0x3 +#define RTC_IO_SENSE4_FUN_SEL_S 7 +/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE4_SLP_SEL (BIT(6)) +#define RTC_IO_SENSE4_SLP_SEL_M (BIT(6)) +#define RTC_IO_SENSE4_SLP_SEL_V 0x1 +#define RTC_IO_SENSE4_SLP_SEL_S 6 +/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE4_SLP_IE (BIT(5)) +#define RTC_IO_SENSE4_SLP_IE_M (BIT(5)) +#define RTC_IO_SENSE4_SLP_IE_V 0x1 +#define RTC_IO_SENSE4_SLP_IE_S 5 +/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE4_FUN_IE (BIT(4)) +#define RTC_IO_SENSE4_FUN_IE_M (BIT(4)) +#define RTC_IO_SENSE4_FUN_IE_V 0x1 +#define RTC_IO_SENSE4_FUN_IE_S 4 + +#define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80) +/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_ADC1_HOLD (BIT(31)) +#define RTC_IO_ADC1_HOLD_M (BIT(31)) +#define RTC_IO_ADC1_HOLD_V 0x1 +#define RTC_IO_ADC1_HOLD_S 31 +/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_ADC2_HOLD (BIT(30)) +#define RTC_IO_ADC2_HOLD_M (BIT(30)) +#define RTC_IO_ADC2_HOLD_V 0x1 +#define RTC_IO_ADC2_HOLD_S 30 +/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_ADC1_MUX_SEL (BIT(29)) +#define RTC_IO_ADC1_MUX_SEL_M (BIT(29)) +#define RTC_IO_ADC1_MUX_SEL_V 0x1 +#define RTC_IO_ADC1_MUX_SEL_S 29 +/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_ADC2_MUX_SEL (BIT(28)) +#define RTC_IO_ADC2_MUX_SEL_M (BIT(28)) +#define RTC_IO_ADC2_MUX_SEL_V 0x1 +#define RTC_IO_ADC2_MUX_SEL_S 28 +/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_ADC1_FUN_SEL 0x00000003 +#define RTC_IO_ADC1_FUN_SEL_M ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S)) +#define RTC_IO_ADC1_FUN_SEL_V 0x3 +#define RTC_IO_ADC1_FUN_SEL_S 26 +/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_ADC1_SLP_SEL (BIT(25)) +#define RTC_IO_ADC1_SLP_SEL_M (BIT(25)) +#define RTC_IO_ADC1_SLP_SEL_V 0x1 +#define RTC_IO_ADC1_SLP_SEL_S 25 +/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_ADC1_SLP_IE (BIT(24)) +#define RTC_IO_ADC1_SLP_IE_M (BIT(24)) +#define RTC_IO_ADC1_SLP_IE_V 0x1 +#define RTC_IO_ADC1_SLP_IE_S 24 +/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_ADC1_FUN_IE (BIT(23)) +#define RTC_IO_ADC1_FUN_IE_M (BIT(23)) +#define RTC_IO_ADC1_FUN_IE_V 0x1 +#define RTC_IO_ADC1_FUN_IE_S 23 +/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_ADC2_FUN_SEL 0x00000003 +#define RTC_IO_ADC2_FUN_SEL_M ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S)) +#define RTC_IO_ADC2_FUN_SEL_V 0x3 +#define RTC_IO_ADC2_FUN_SEL_S 21 +/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_ADC2_SLP_SEL (BIT(20)) +#define RTC_IO_ADC2_SLP_SEL_M (BIT(20)) +#define RTC_IO_ADC2_SLP_SEL_V 0x1 +#define RTC_IO_ADC2_SLP_SEL_S 20 +/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_ADC2_SLP_IE (BIT(19)) +#define RTC_IO_ADC2_SLP_IE_M (BIT(19)) +#define RTC_IO_ADC2_SLP_IE_V 0x1 +#define RTC_IO_ADC2_SLP_IE_S 19 +/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_ADC2_FUN_IE (BIT(18)) +#define RTC_IO_ADC2_FUN_IE_M (BIT(18)) +#define RTC_IO_ADC2_FUN_IE_V 0x1 +#define RTC_IO_ADC2_FUN_IE_S 18 + +#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84) +/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_PDAC1_DRV 0x00000003 +#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S)) +#define RTC_IO_PDAC1_DRV_V 0x3 +#define RTC_IO_PDAC1_DRV_S 30 +/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_PDAC1_HOLD (BIT(29)) +#define RTC_IO_PDAC1_HOLD_M (BIT(29)) +#define RTC_IO_PDAC1_HOLD_V 0x1 +#define RTC_IO_PDAC1_HOLD_S 29 +/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_PDAC1_RDE (BIT(28)) +#define RTC_IO_PDAC1_RDE_M (BIT(28)) +#define RTC_IO_PDAC1_RDE_V 0x1 +#define RTC_IO_PDAC1_RDE_S 28 +/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_PDAC1_RUE (BIT(27)) +#define RTC_IO_PDAC1_RUE_M (BIT(27)) +#define RTC_IO_PDAC1_RUE_V 0x1 +#define RTC_IO_PDAC1_RUE_S 27 +/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: PAD DAC1 control code.*/ +#define RTC_IO_PDAC1_DAC 0x000000FF +#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S)) +#define RTC_IO_PDAC1_DAC_V 0xFF +#define RTC_IO_PDAC1_DAC_S 19 +/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC1_XPD_DAC (BIT(18)) +#define RTC_IO_PDAC1_XPD_DAC_M (BIT(18)) +#define RTC_IO_PDAC1_XPD_DAC_V 0x1 +#define RTC_IO_PDAC1_XPD_DAC_S 18 +/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_PDAC1_MUX_SEL (BIT(17)) +#define RTC_IO_PDAC1_MUX_SEL_M (BIT(17)) +#define RTC_IO_PDAC1_MUX_SEL_V 0x1 +#define RTC_IO_PDAC1_MUX_SEL_S 17 +/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_PDAC1_FUN_SEL 0x00000003 +#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S)) +#define RTC_IO_PDAC1_FUN_SEL_V 0x3 +#define RTC_IO_PDAC1_FUN_SEL_S 15 +/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_PDAC1_SLP_SEL (BIT(14)) +#define RTC_IO_PDAC1_SLP_SEL_M (BIT(14)) +#define RTC_IO_PDAC1_SLP_SEL_V 0x1 +#define RTC_IO_PDAC1_SLP_SEL_S 14 +/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_PDAC1_SLP_IE (BIT(13)) +#define RTC_IO_PDAC1_SLP_IE_M (BIT(13)) +#define RTC_IO_PDAC1_SLP_IE_V 0x1 +#define RTC_IO_PDAC1_SLP_IE_S 13 +/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_PDAC1_SLP_OE (BIT(12)) +#define RTC_IO_PDAC1_SLP_OE_M (BIT(12)) +#define RTC_IO_PDAC1_SLP_OE_V 0x1 +#define RTC_IO_PDAC1_SLP_OE_S 12 +/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_PDAC1_FUN_IE (BIT(11)) +#define RTC_IO_PDAC1_FUN_IE_M (BIT(11)) +#define RTC_IO_PDAC1_FUN_IE_V 0x1 +#define RTC_IO_PDAC1_FUN_IE_S 11 +/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(10)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10 + +#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88) +/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_PDAC2_DRV 0x00000003 +#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S)) +#define RTC_IO_PDAC2_DRV_V 0x3 +#define RTC_IO_PDAC2_DRV_S 30 +/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_PDAC2_HOLD (BIT(29)) +#define RTC_IO_PDAC2_HOLD_M (BIT(29)) +#define RTC_IO_PDAC2_HOLD_V 0x1 +#define RTC_IO_PDAC2_HOLD_S 29 +/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_PDAC2_RDE (BIT(28)) +#define RTC_IO_PDAC2_RDE_M (BIT(28)) +#define RTC_IO_PDAC2_RDE_V 0x1 +#define RTC_IO_PDAC2_RDE_S 28 +/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_PDAC2_RUE (BIT(27)) +#define RTC_IO_PDAC2_RUE_M (BIT(27)) +#define RTC_IO_PDAC2_RUE_V 0x1 +#define RTC_IO_PDAC2_RUE_S 27 +/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: PAD DAC2 control code.*/ +#define RTC_IO_PDAC2_DAC 0x000000FF +#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S)) +#define RTC_IO_PDAC2_DAC_V 0xFF +#define RTC_IO_PDAC2_DAC_S 19 +/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Power on DAC2. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC2_XPD_DAC (BIT(18)) +#define RTC_IO_PDAC2_XPD_DAC_M (BIT(18)) +#define RTC_IO_PDAC2_XPD_DAC_V 0x1 +#define RTC_IO_PDAC2_XPD_DAC_S 18 +/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_PDAC2_MUX_SEL (BIT(17)) +#define RTC_IO_PDAC2_MUX_SEL_M (BIT(17)) +#define RTC_IO_PDAC2_MUX_SEL_V 0x1 +#define RTC_IO_PDAC2_MUX_SEL_S 17 +/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_PDAC2_FUN_SEL 0x00000003 +#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S)) +#define RTC_IO_PDAC2_FUN_SEL_V 0x3 +#define RTC_IO_PDAC2_FUN_SEL_S 15 +/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_PDAC2_SLP_SEL (BIT(14)) +#define RTC_IO_PDAC2_SLP_SEL_M (BIT(14)) +#define RTC_IO_PDAC2_SLP_SEL_V 0x1 +#define RTC_IO_PDAC2_SLP_SEL_S 14 +/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_PDAC2_SLP_IE (BIT(13)) +#define RTC_IO_PDAC2_SLP_IE_M (BIT(13)) +#define RTC_IO_PDAC2_SLP_IE_V 0x1 +#define RTC_IO_PDAC2_SLP_IE_S 13 +/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_PDAC2_SLP_OE (BIT(12)) +#define RTC_IO_PDAC2_SLP_OE_M (BIT(12)) +#define RTC_IO_PDAC2_SLP_OE_V 0x1 +#define RTC_IO_PDAC2_SLP_OE_S 12 +/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_PDAC2_FUN_IE (BIT(11)) +#define RTC_IO_PDAC2_FUN_IE_M (BIT(11)) +#define RTC_IO_PDAC2_FUN_IE_V 0x1 +#define RTC_IO_PDAC2_FUN_IE_S 11 +/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Power on DAC2. Usually we need to tristate PDAC2 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(10)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10 + +#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) +/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_X32N_DRV 0x00000003 +#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S)) +#define RTC_IO_X32N_DRV_V 0x3 +#define RTC_IO_X32N_DRV_S 30 +/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_X32N_HOLD (BIT(29)) +#define RTC_IO_X32N_HOLD_M (BIT(29)) +#define RTC_IO_X32N_HOLD_V 0x1 +#define RTC_IO_X32N_HOLD_S 29 +/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_X32N_RDE (BIT(28)) +#define RTC_IO_X32N_RDE_M (BIT(28)) +#define RTC_IO_X32N_RDE_V 0x1 +#define RTC_IO_X32N_RDE_S 28 +/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_X32N_RUE (BIT(27)) +#define RTC_IO_X32N_RUE_M (BIT(27)) +#define RTC_IO_X32N_RUE_V 0x1 +#define RTC_IO_X32N_RUE_S 27 +/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_X32P_DRV 0x00000003 +#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S)) +#define RTC_IO_X32P_DRV_V 0x3 +#define RTC_IO_X32P_DRV_S 25 +/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_X32P_HOLD (BIT(24)) +#define RTC_IO_X32P_HOLD_M (BIT(24)) +#define RTC_IO_X32P_HOLD_V 0x1 +#define RTC_IO_X32P_HOLD_S 24 +/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_X32P_RDE (BIT(23)) +#define RTC_IO_X32P_RDE_M (BIT(23)) +#define RTC_IO_X32P_RDE_V 0x1 +#define RTC_IO_X32P_RDE_S 23 +/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_X32P_RUE (BIT(22)) +#define RTC_IO_X32P_RUE_M (BIT(22)) +#define RTC_IO_X32P_RUE_V 0x1 +#define RTC_IO_X32P_RUE_S 22 +/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */ +/*description: 32K XTAL bias current DAC.*/ +#define RTC_IO_DAC_XTAL_32K 0x00000003 +#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S)) +#define RTC_IO_DAC_XTAL_32K_V 0x3 +#define RTC_IO_DAC_XTAL_32K_S 20 +/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Power up 32kHz crystal oscillator*/ +#define RTC_IO_XPD_XTAL_32K (BIT(19)) +#define RTC_IO_XPD_XTAL_32K_M (BIT(19)) +#define RTC_IO_XPD_XTAL_32K_V 0x1 +#define RTC_IO_XPD_XTAL_32K_S 19 +/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_X32N_MUX_SEL (BIT(18)) +#define RTC_IO_X32N_MUX_SEL_M (BIT(18)) +#define RTC_IO_X32N_MUX_SEL_V 0x1 +#define RTC_IO_X32N_MUX_SEL_S 18 +/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_X32P_MUX_SEL (BIT(17)) +#define RTC_IO_X32P_MUX_SEL_M (BIT(17)) +#define RTC_IO_X32P_MUX_SEL_V 0x1 +#define RTC_IO_X32P_MUX_SEL_S 17 +/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_X32N_FUN_SEL 0x00000003 +#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S)) +#define RTC_IO_X32N_FUN_SEL_V 0x3 +#define RTC_IO_X32N_FUN_SEL_S 15 +/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_X32N_SLP_SEL (BIT(14)) +#define RTC_IO_X32N_SLP_SEL_M (BIT(14)) +#define RTC_IO_X32N_SLP_SEL_V 0x1 +#define RTC_IO_X32N_SLP_SEL_S 14 +/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_X32N_SLP_IE (BIT(13)) +#define RTC_IO_X32N_SLP_IE_M (BIT(13)) +#define RTC_IO_X32N_SLP_IE_V 0x1 +#define RTC_IO_X32N_SLP_IE_S 13 +/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_X32N_SLP_OE (BIT(12)) +#define RTC_IO_X32N_SLP_OE_M (BIT(12)) +#define RTC_IO_X32N_SLP_OE_V 0x1 +#define RTC_IO_X32N_SLP_OE_S 12 +/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_X32N_FUN_IE (BIT(11)) +#define RTC_IO_X32N_FUN_IE_M (BIT(11)) +#define RTC_IO_X32N_FUN_IE_V 0x1 +#define RTC_IO_X32N_FUN_IE_S 11 +/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_X32P_FUN_SEL 0x00000003 +#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S)) +#define RTC_IO_X32P_FUN_SEL_V 0x3 +#define RTC_IO_X32P_FUN_SEL_S 9 +/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_X32P_SLP_SEL (BIT(8)) +#define RTC_IO_X32P_SLP_SEL_M (BIT(8)) +#define RTC_IO_X32P_SLP_SEL_V 0x1 +#define RTC_IO_X32P_SLP_SEL_S 8 +/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_X32P_SLP_IE (BIT(7)) +#define RTC_IO_X32P_SLP_IE_M (BIT(7)) +#define RTC_IO_X32P_SLP_IE_V 0x1 +#define RTC_IO_X32P_SLP_IE_S 7 +/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_X32P_SLP_OE (BIT(6)) +#define RTC_IO_X32P_SLP_OE_M (BIT(6)) +#define RTC_IO_X32P_SLP_OE_V 0x1 +#define RTC_IO_X32P_SLP_OE_S 6 +/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_X32P_FUN_IE (BIT(5)) +#define RTC_IO_X32P_FUN_IE_M (BIT(5)) +#define RTC_IO_X32P_FUN_IE_V 0x1 +#define RTC_IO_X32P_FUN_IE_S 5 +/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */ +/*description: 32K XTAL resistor bias control.*/ +#define RTC_IO_DRES_XTAL_32K 0x00000003 +#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S)) +#define RTC_IO_DRES_XTAL_32K_V 0x3 +#define RTC_IO_DRES_XTAL_32K_S 3 +/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */ +/*description: 32K XTAL self-bias reference control.*/ +#define RTC_IO_DBIAS_XTAL_32K 0x00000003 +#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S)) +#define RTC_IO_DBIAS_XTAL_32K_V 0x3 +#define RTC_IO_DBIAS_XTAL_32K_S 1 + +#define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90) +/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: touch sensor bias power on.*/ +#define RTC_IO_TOUCH_XPD_BIAS (BIT(31)) +#define RTC_IO_TOUCH_XPD_BIAS_M (BIT(31)) +#define RTC_IO_TOUCH_XPD_BIAS_V 0x1 +#define RTC_IO_TOUCH_XPD_BIAS_S 31 +/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */ +/*description: touch sensor saw wave top voltage.*/ +#define RTC_IO_TOUCH_DREFH 0x00000003 +#define RTC_IO_TOUCH_DREFH_M ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S)) +#define RTC_IO_TOUCH_DREFH_V 0x3 +#define RTC_IO_TOUCH_DREFH_S 29 +/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ +/*description: touch sensor saw wave bottom voltage.*/ +#define RTC_IO_TOUCH_DREFL 0x00000003 +#define RTC_IO_TOUCH_DREFL_M ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S)) +#define RTC_IO_TOUCH_DREFL_V 0x3 +#define RTC_IO_TOUCH_DREFL_S 27 +/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */ +/*description: touch sensor saw wave voltage range.*/ +#define RTC_IO_TOUCH_DRANGE 0x00000003 +#define RTC_IO_TOUCH_DRANGE_M ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S)) +#define RTC_IO_TOUCH_DRANGE_V 0x3 +#define RTC_IO_TOUCH_DRANGE_S 25 +/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */ +/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When + BIAS_SLEEP this setting is available*/ +#define RTC_IO_TOUCH_DCUR 0x00000003 +#define RTC_IO_TOUCH_DCUR_M ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S)) +#define RTC_IO_TOUCH_DCUR_V 0x3 +#define RTC_IO_TOUCH_DCUR_S 23 + +#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94) +/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD0_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD0_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD0_HOLD_S 31 +/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD0_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S)) +#define RTC_IO_TOUCH_PAD0_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD0_DRV_S 29 +/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RDE_S 28 +/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RUE_S 27 +/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD0_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S)) +#define RTC_IO_TOUCH_PAD0_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD0_DAC_S 23 +/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD0_START (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_V 0x1 +#define RTC_IO_TOUCH_PAD0_START_S 22 +/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD0_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD0_XPD_S 20 +/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/ +#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD0_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD0_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98) +/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD1_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD1_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD1_HOLD_S 31 +/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD1_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S)) +#define RTC_IO_TOUCH_PAD1_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD1_DRV_S 29 +/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RDE_S 28 +/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RUE_S 27 +/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD1_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S)) +#define RTC_IO_TOUCH_PAD1_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD1_DAC_S 23 +/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD1_START (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_V 0x1 +#define RTC_IO_TOUCH_PAD1_START_S 22 +/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD1_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD1_XPD_S 20 +/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/ +#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c) +/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD2_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD2_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD2_HOLD_S 31 +/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD2_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S)) +#define RTC_IO_TOUCH_PAD2_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD2_DRV_S 29 +/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RDE_S 28 +/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RUE_S 27 +/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD2_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S)) +#define RTC_IO_TOUCH_PAD2_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD2_DAC_S 23 +/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD2_START (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_V 0x1 +#define RTC_IO_TOUCH_PAD2_START_S 22 +/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD2_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD2_XPD_S 20 +/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/ +#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0) +/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD3_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD3_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD3_HOLD_S 31 +/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD3_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S)) +#define RTC_IO_TOUCH_PAD3_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD3_DRV_S 29 +/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RDE_S 28 +/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RUE_S 27 +/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD3_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S)) +#define RTC_IO_TOUCH_PAD3_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD3_DAC_S 23 +/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD3_START (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_V 0x1 +#define RTC_IO_TOUCH_PAD3_START_S 22 +/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD3_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD3_XPD_S 20 +/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/ +#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4) +/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD4_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD4_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD4_HOLD_S 31 +/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD4_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S)) +#define RTC_IO_TOUCH_PAD4_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD4_DRV_S 29 +/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RDE_S 28 +/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RUE_S 27 +/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD4_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S)) +#define RTC_IO_TOUCH_PAD4_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD4_DAC_S 23 +/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD4_START (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_V 0x1 +#define RTC_IO_TOUCH_PAD4_START_S 22 +/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD4_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD4_XPD_S 20 +/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/ +#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8) +/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD5_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD5_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD5_HOLD_S 31 +/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD5_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S)) +#define RTC_IO_TOUCH_PAD5_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD5_DRV_S 29 +/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RDE_S 28 +/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RUE_S 27 +/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD5_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S)) +#define RTC_IO_TOUCH_PAD5_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD5_DAC_S 23 +/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD5_START (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_V 0x1 +#define RTC_IO_TOUCH_PAD5_START_S 22 +/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD5_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD5_XPD_S 20 +/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/ +#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac) +/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD6_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD6_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD6_HOLD_S 31 +/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD6_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S)) +#define RTC_IO_TOUCH_PAD6_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD6_DRV_S 29 +/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RDE_S 28 +/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RUE_S 27 +/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD6_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S)) +#define RTC_IO_TOUCH_PAD6_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD6_DAC_S 23 +/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD6_START (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_V 0x1 +#define RTC_IO_TOUCH_PAD6_START_S 22 +/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD6_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD6_XPD_S 20 +/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/ +#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0) +/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD7_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD7_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD7_HOLD_S 31 +/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD7_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S)) +#define RTC_IO_TOUCH_PAD7_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD7_DRV_S 29 +/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RDE_S 28 +/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RUE_S 27 +/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD7_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S)) +#define RTC_IO_TOUCH_PAD7_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD7_DAC_S 23 +/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD7_START (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_V 0x1 +#define RTC_IO_TOUCH_PAD7_START_S 22 +/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD7_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD7_XPD_S 20 +/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/ +#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4) +/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD8_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S)) +#define RTC_IO_TOUCH_PAD8_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD8_DAC_S 23 +/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD8_START (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_V 0x1 +#define RTC_IO_TOUCH_PAD8_START_S 22 +/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD8_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD8_XPD_S 20 +/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ +#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19)) +#define RTC_IO_TOUCH_PAD8_TO_GPIO_M (BIT(19)) +#define RTC_IO_TOUCH_PAD8_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19 + +#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8) +/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD9_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S)) +#define RTC_IO_TOUCH_PAD9_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD9_DAC_S 23 +/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD9_START (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_V 0x1 +#define RTC_IO_TOUCH_PAD9_START_S 22 +/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD9_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD9_XPD_S 20 +/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ +#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19)) +#define RTC_IO_TOUCH_PAD9_TO_GPIO_M (BIT(19)) +#define RTC_IO_TOUCH_PAD9_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19 + +#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) +/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/ +#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F +#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S)) +#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F +#define RTC_IO_EXT_WAKEUP0_SEL_S 27 + +#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) +/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select + GPIO2 ...Ò17Ó select GPIO17*/ +#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F +#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S)) +#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F +#define RTC_IO_XTL_EXT_CTR_SEL_S 27 + +#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4) +/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/ +#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S)) +#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SDA_SEL_S 30 +/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/ +#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S)) +#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SCL_SEL_S 28 +/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */ +/*description: */ +#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F +#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S)) +#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F +#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23 + +#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8) +/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */ +/*description: date*/ +#define RTC_IO_IO_DATE 0x0FFFFFFF +#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S)) +#define RTC_IO_IO_DATE_V 0xFFFFFFF +#define RTC_IO_IO_DATE_S 0 +#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160 + + + + +#endif /*_SOC_RTC_IO_REG_H_ */ + + diff --git a/tools/sdk/include/soc/soc/rtc_io_struct.h b/tools/sdk/include/soc/soc/rtc_io_struct.h new file mode 100644 index 00000000..da27078c --- /dev/null +++ b/tools/sdk/include/soc/soc/rtc_io_struct.h @@ -0,0 +1,280 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_IO_STRUCT_H_ +#define _SOC_RTC_IO_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint32_t reserved0: 14; + uint32_t data:18; /*GPIO0~17 output value*/ + }; + uint32_t val; + } out; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 output value write 1 to set*/ + }; + uint32_t val; + } out_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 output value write 1 to clear*/ + }; + uint32_t val; + } out_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t enable:18; /*GPIO0~17 output enable*/ + }; + uint32_t val; + } enable; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 output enable write 1 to set*/ + }; + uint32_t val; + } enable_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 output enable write 1 to clear*/ + }; + uint32_t val; + } enable_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t status:18; /*GPIO0~17 interrupt status*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 interrupt status write 1 to set*/ + }; + uint32_t val; + } status_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 interrupt status write 1 to clear*/ + }; + uint32_t val; + } status_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t in:18; /*GPIO0~17 input value*/ + }; + uint32_t val; + } in_val; + union { + struct { + uint32_t reserved0: 2; + uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + uint32_t reserved3: 4; + uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ + uint32_t reserved11: 21; + }; + uint32_t val; + } pin[18]; + union { + struct { + uint32_t sel0: 5; + uint32_t sel1: 5; + uint32_t sel2: 5; + uint32_t sel3: 5; + uint32_t sel4: 5; + uint32_t no_gating_12m: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } debug_sel; + uint32_t dig_pad_hold; /*select the digital pad hold value.*/ + union { + struct { + uint32_t reserved0: 30; + uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/ + uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/ + }; + uint32_t val; + } hall_sens; + union { + struct { + uint32_t reserved0: 4; + uint32_t sense4_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense4_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense4_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense4_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense3_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense3_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense3_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense3_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense2_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense2_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense2_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense2_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense1_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense1_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense1_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense1_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense4_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense3_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense2_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense1_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense4_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense3_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense2_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense1_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } sensor_pads; + union { + struct { + uint32_t reserved0: 18; + uint32_t adc2_fun_ie: 1; /*the input enable of the pad*/ + uint32_t adc2_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t adc2_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t adc2_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t adc1_fun_ie: 1; /*the input enable of the pad*/ + uint32_t adc1_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t adc1_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t adc1_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t adc2_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t adc1_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t adc2_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t adc1_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } adc_pad; + union { + struct { + uint32_t reserved0: 10; + uint32_t dac_xpd_force: 1; /*Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ + uint32_t fun_ie: 1; /*the input enable of the pad*/ + uint32_t slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd_dac: 1; /*Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ + uint32_t dac: 8; /*PAD DAC1 control code.*/ + uint32_t rue: 1; /*the pull up enable of the pad*/ + uint32_t rde: 1; /*the pull down enable of the pad*/ + uint32_t hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t drv: 2; /*the driver strength of the pad*/ + }; + uint32_t val; + } pad_dac[2]; + union { + struct { + uint32_t reserved0: 1; + uint32_t dbias_xtal_32k: 2; /*32K XTAL self-bias reference control.*/ + uint32_t dres_xtal_32k: 2; /*32K XTAL resistor bias control.*/ + uint32_t x32p_fun_ie: 1; /*the input enable of the pad*/ + uint32_t x32p_slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t x32p_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t x32p_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t x32p_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t x32n_fun_ie: 1; /*the input enable of the pad*/ + uint32_t x32n_slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t x32n_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t x32n_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t x32n_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t x32p_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t x32n_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd_xtal_32k: 1; /*Power up 32kHz crystal oscillator*/ + uint32_t dac_xtal_32k: 2; /*32K XTAL bias current DAC.*/ + uint32_t x32p_rue: 1; /*the pull up enable of the pad*/ + uint32_t x32p_rde: 1; /*the pull down enable of the pad*/ + uint32_t x32p_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t x32p_drv: 2; /*the driver strength of the pad*/ + uint32_t x32n_rue: 1; /*the pull up enable of the pad*/ + uint32_t x32n_rde: 1; /*the pull down enable of the pad*/ + uint32_t x32n_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t x32n_drv: 2; /*the driver strength of the pad*/ + }; + uint32_t val; + } xtal_32k_pad; + union { + struct { + uint32_t reserved0: 23; + uint32_t dcur: 2; /*touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP this setting is available*/ + uint32_t drange: 2; /*touch sensor saw wave voltage range.*/ + uint32_t drefl: 2; /*touch sensor saw wave bottom voltage.*/ + uint32_t drefh: 2; /*touch sensor saw wave top voltage.*/ + uint32_t xpd_bias: 1; /*touch sensor bias power on.*/ + }; + uint32_t val; + } touch_cfg; + union { + struct { + uint32_t reserved0: 12; + uint32_t to_gpio: 1; /*connect the rtc pad input to digital pad input �0� is availbale GPIO4*/ + uint32_t fun_ie: 1; /*the input enable of the pad*/ + uint32_t slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd: 1; /*touch sensor power on.*/ + uint32_t tie_opt: 1; /*default touch sensor tie option. 0: tie low 1: tie high.*/ + uint32_t start: 1; /*start touch sensor.*/ + uint32_t dac: 3; /*touch sensor slope control. 3-bit for each touch panel default 100.*/ + uint32_t reserved26: 1; + uint32_t rue: 1; /*the pull up enable of the pad*/ + uint32_t rde: 1; /*the pull down enable of the pad*/ + uint32_t drv: 2; /*the driver strength of the pad*/ + uint32_t hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } touch_pad[10]; + union { + struct { + uint32_t reserved0: 27; + uint32_t sel: 5; /*select the wakeup source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/ + }; + uint32_t val; + } ext_wakeup0; + union { + struct { + uint32_t reserved0: 27; + uint32_t sel: 5; /*select the external xtl power source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/ + }; + uint32_t val; + } xtl_ext_ctr; + union { + struct { + uint32_t reserved0: 23; + uint32_t debug_bit_sel: 5; + uint32_t scl_sel: 2; /*�0� using TOUCH_PAD[0] as i2c clk �1� using TOUCH_PAD[2] as i2c clk*/ + uint32_t sda_sel: 2; /*�0� using TOUCH_PAD[1] as i2c sda �1� using TOUCH_PAD[3] as i2c sda*/ + }; + uint32_t val; + } sar_i2c_io; + union { + struct { + uint32_t date: 28; /*date*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_io_dev_t; +#endif /* _SOC_RTC_IO_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/sdmmc_reg.h b/tools/sdk/include/soc/soc/sdmmc_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/sdmmc_reg.h rename to tools/sdk/include/soc/soc/sdmmc_reg.h diff --git a/tools/sdk/include/esp32/soc/sdmmc_struct.h b/tools/sdk/include/soc/soc/sdmmc_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/sdmmc_struct.h rename to tools/sdk/include/soc/soc/sdmmc_struct.h diff --git a/tools/sdk/include/esp32/soc/sens_reg.h b/tools/sdk/include/soc/soc/sens_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/sens_reg.h rename to tools/sdk/include/soc/soc/sens_reg.h diff --git a/tools/sdk/include/esp32/soc/soc.h b/tools/sdk/include/soc/soc/soc.h old mode 100755 new mode 100644 similarity index 99% rename from tools/sdk/include/esp32/soc/soc.h rename to tools/sdk/include/soc/soc/soc.h index 9b0c82fc..bcb49a66 --- a/tools/sdk/include/esp32/soc/soc.h +++ b/tools/sdk/include/soc/soc/soc.h @@ -179,11 +179,14 @@ #define DR_REG_LEDC_BASE 0x3ff59000 #define DR_REG_EFUSE_BASE 0x3ff5A000 #define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 +#define DR_REG_NRX_BASE 0x3ff5CC00 +#define DR_REG_BB_BASE 0x3ff5D000 #define DR_REG_PWM_BASE 0x3ff5E000 #define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 #define DR_REG_TIMERGROUP1_BASE 0x3ff60000 #define DR_REG_SPI2_BASE 0x3ff64000 #define DR_REG_SPI3_BASE 0x3ff65000 +#define DR_REG_APB_CTRL_BASE 0x3ff66000 #define DR_REG_I2C1_EXT_BASE 0x3ff67000 #define DR_REG_SDMMC_BASE 0x3ff68000 #define DR_REG_EMAC_BASE 0x3ff69000 diff --git a/tools/sdk/include/esp32/soc/soc_ulp.h b/tools/sdk/include/soc/soc/soc_ulp.h similarity index 100% rename from tools/sdk/include/esp32/soc/soc_ulp.h rename to tools/sdk/include/soc/soc/soc_ulp.h diff --git a/tools/sdk/include/esp32/soc/spi_reg.h b/tools/sdk/include/soc/soc/spi_reg.h similarity index 97% rename from tools/sdk/include/esp32/soc/spi_reg.h rename to tools/sdk/include/soc/soc/spi_reg.h index 0cc27b89..fac2965c 100644 --- a/tools/sdk/include/esp32/soc/spi_reg.h +++ b/tools/sdk/include/soc/soc/spi_reg.h @@ -1,1713 +1,1713 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef __SPI_REG_H__ -#define __SPI_REG_H__ - - -#include "soc.h" -#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 ))) - -#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) -/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Read flash enable. Read flash operation will be triggered when - the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_FLASH_READ (BIT(31)) -#define SPI_FLASH_READ_M (BIT(31)) -#define SPI_FLASH_READ_V 0x1 -#define SPI_FLASH_READ_S 31 -/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Write flash enable. Write enable command will be sent when the - bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_FLASH_WREN (BIT(30)) -#define SPI_FLASH_WREN_M (BIT(30)) -#define SPI_FLASH_WREN_V 0x1 -#define SPI_FLASH_WREN_S 30 -/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Write flash disable. Write disable command will be sent when - the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_FLASH_WRDI (BIT(29)) -#define SPI_FLASH_WRDI_M (BIT(29)) -#define SPI_FLASH_WRDI_V 0x1 -#define SPI_FLASH_WRDI_S 29 -/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Read JEDEC ID . Read ID command will be sent when the bit is - set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_FLASH_RDID (BIT(28)) -#define SPI_FLASH_RDID_M (BIT(28)) -#define SPI_FLASH_RDID_V 0x1 -#define SPI_FLASH_RDID_S 28 -/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Read status register-1. Read status operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_RDSR (BIT(27)) -#define SPI_FLASH_RDSR_M (BIT(27)) -#define SPI_FLASH_RDSR_V 0x1 -#define SPI_FLASH_RDSR_S 27 -/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Write status register enable. Write status operation will - be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_WRSR (BIT(26)) -#define SPI_FLASH_WRSR_M (BIT(26)) -#define SPI_FLASH_WRSR_V 0x1 -#define SPI_FLASH_WRSR_S 26 -/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Page program enable(1 byte ~256 bytes data to be programmed). - Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ -#define SPI_FLASH_PP (BIT(25)) -#define SPI_FLASH_PP_M (BIT(25)) -#define SPI_FLASH_PP_V 0x1 -#define SPI_FLASH_PP_S 25 -/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_SE (BIT(24)) -#define SPI_FLASH_SE_M (BIT(24)) -#define SPI_FLASH_SE_V 0x1 -#define SPI_FLASH_SE_S 24 -/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_BE (BIT(23)) -#define SPI_FLASH_BE_M (BIT(23)) -#define SPI_FLASH_BE_V 0x1 -#define SPI_FLASH_BE_S 23 -/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Chip erase enable. Chip erase operation will be triggered when - the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_CE (BIT(22)) -#define SPI_FLASH_CE_M (BIT(22)) -#define SPI_FLASH_CE_V 0x1 -#define SPI_FLASH_CE_S 22 -/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Drive Flash into power down. An operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_DP (BIT(21)) -#define SPI_FLASH_DP_M (BIT(21)) -#define SPI_FLASH_DP_V 0x1 -#define SPI_FLASH_DP_S 21 -/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: This bit combined with reg_resandres bit releases Flash from - the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_RES (BIT(20)) -#define SPI_FLASH_RES_M (BIT(20)) -#define SPI_FLASH_RES_V 0x1 -#define SPI_FLASH_RES_S 20 -/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Drive Flash into high performance mode. The bit will be cleared - once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_HPM (BIT(19)) -#define SPI_FLASH_HPM_M (BIT(19)) -#define SPI_FLASH_HPM_V 0x1 -#define SPI_FLASH_HPM_S 19 -/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: User define command enable. An operation will be triggered when - the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_USR (BIT(18)) -#define SPI_USR_M (BIT(18)) -#define SPI_USR_V 0x1 -#define SPI_USR_S 18 -/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: program erase suspend bit program erase suspend operation will - be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_PES (BIT(17)) -#define SPI_FLASH_PES_M (BIT(17)) -#define SPI_FLASH_PES_V 0x1 -#define SPI_FLASH_PES_S 17 -/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: program erase resume bit program erase suspend operation will - be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_PER (BIT(16)) -#define SPI_FLASH_PER_M (BIT(16)) -#define SPI_FLASH_PER_V 0x1 -#define SPI_FLASH_PER_S 16 - -#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + + +#include "soc.h" +#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 ))) + +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) +/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Read flash enable. Read flash operation will be triggered when + the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_READ (BIT(31)) +#define SPI_FLASH_READ_M (BIT(31)) +#define SPI_FLASH_READ_V 0x1 +#define SPI_FLASH_READ_S 31 +/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Write flash enable. Write enable command will be sent when the + bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_WREN (BIT(30)) +#define SPI_FLASH_WREN_M (BIT(30)) +#define SPI_FLASH_WREN_V 0x1 +#define SPI_FLASH_WREN_S 30 +/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Write flash disable. Write disable command will be sent when + the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_WRDI (BIT(29)) +#define SPI_FLASH_WRDI_M (BIT(29)) +#define SPI_FLASH_WRDI_V 0x1 +#define SPI_FLASH_WRDI_S 29 +/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Read JEDEC ID . Read ID command will be sent when the bit is + set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_RDID (BIT(28)) +#define SPI_FLASH_RDID_M (BIT(28)) +#define SPI_FLASH_RDID_V 0x1 +#define SPI_FLASH_RDID_S 28 +/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Read status register-1. Read status operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_RDSR (BIT(27)) +#define SPI_FLASH_RDSR_M (BIT(27)) +#define SPI_FLASH_RDSR_V 0x1 +#define SPI_FLASH_RDSR_S 27 +/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write status register enable. Write status operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_WRSR (BIT(26)) +#define SPI_FLASH_WRSR_M (BIT(26)) +#define SPI_FLASH_WRSR_V 0x1 +#define SPI_FLASH_WRSR_S 26 +/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Page program enable(1 byte ~256 bytes data to be programmed). + Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ +#define SPI_FLASH_PP (BIT(25)) +#define SPI_FLASH_PP_M (BIT(25)) +#define SPI_FLASH_PP_V 0x1 +#define SPI_FLASH_PP_S 25 +/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_SE (BIT(24)) +#define SPI_FLASH_SE_M (BIT(24)) +#define SPI_FLASH_SE_V 0x1 +#define SPI_FLASH_SE_S 24 +/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_BE (BIT(23)) +#define SPI_FLASH_BE_M (BIT(23)) +#define SPI_FLASH_BE_V 0x1 +#define SPI_FLASH_BE_S 23 +/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Chip erase enable. Chip erase operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_CE (BIT(22)) +#define SPI_FLASH_CE_M (BIT(22)) +#define SPI_FLASH_CE_V 0x1 +#define SPI_FLASH_CE_S 22 +/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Drive Flash into power down. An operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_DP (BIT(21)) +#define SPI_FLASH_DP_M (BIT(21)) +#define SPI_FLASH_DP_V 0x1 +#define SPI_FLASH_DP_S 21 +/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This bit combined with reg_resandres bit releases Flash from + the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_RES (BIT(20)) +#define SPI_FLASH_RES_M (BIT(20)) +#define SPI_FLASH_RES_V 0x1 +#define SPI_FLASH_RES_S 20 +/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Drive Flash into high performance mode. The bit will be cleared + once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_HPM (BIT(19)) +#define SPI_FLASH_HPM_M (BIT(19)) +#define SPI_FLASH_HPM_V 0x1 +#define SPI_FLASH_HPM_S 19 +/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: User define command enable. An operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_USR (BIT(18)) +#define SPI_USR_M (BIT(18)) +#define SPI_USR_V 0x1 +#define SPI_USR_S 18 +/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: program erase suspend bit program erase suspend operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_PES (BIT(17)) +#define SPI_FLASH_PES_M (BIT(17)) +#define SPI_FLASH_PES_V 0x1 +#define SPI_FLASH_PES_S 17 +/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: program erase resume bit program erase suspend operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_PER (BIT(16)) +#define SPI_FLASH_PER_M (BIT(16)) +#define SPI_FLASH_PER_V 0x1 +#define SPI_FLASH_PER_S 16 + +#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) //The CSV actually is wrong here. It indicates that the lower 8 bits of this register are reserved. This is not true, //all 32 bits of SPI_ADDR_REG are usable/used. - -#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) -/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ -#define SPI_WR_BIT_ORDER (BIT(26)) -#define SPI_WR_BIT_ORDER_M (BIT(26)) -#define SPI_WR_BIT_ORDER_V 0x1 -#define SPI_WR_BIT_ORDER_S 26 -/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/ -#define SPI_RD_BIT_ORDER (BIT(25)) -#define SPI_RD_BIT_ORDER_M (BIT(25)) -#define SPI_RD_BIT_ORDER_V 0x1 -#define SPI_RD_BIT_ORDER_S 25 -/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: In the read operations address phase and read-data phase apply - 4 signals. 1: enable 0: disable.*/ -#define SPI_FREAD_QIO (BIT(24)) -#define SPI_FREAD_QIO_M (BIT(24)) -#define SPI_FREAD_QIO_V 0x1 -#define SPI_FREAD_QIO_S 24 -/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: In the read operations address phase and read-data phase apply - 2 signals. 1: enable 0: disable.*/ -#define SPI_FREAD_DIO (BIT(23)) -#define SPI_FREAD_DIO_M (BIT(23)) -#define SPI_FREAD_DIO_V 0x1 -#define SPI_FREAD_DIO_S 23 -/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: two bytes data will be written to status register when it is - set. 1: enable 0: disable.*/ -#define SPI_WRSR_2B (BIT(22)) -#define SPI_WRSR_2B_M (BIT(22)) -#define SPI_WRSR_2B_V 0x1 -#define SPI_WRSR_2B_S 22 -/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/ -#define SPI_WP_REG (BIT(21)) -#define SPI_WP_REG_M (BIT(21)) -#define SPI_WP_REG_V 0x1 -#define SPI_WP_REG_S 21 -/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ -#define SPI_FREAD_QUAD (BIT(20)) -#define SPI_FREAD_QUAD_M (BIT(20)) -#define SPI_FREAD_QUAD_V 0x1 -#define SPI_FREAD_QUAD_S 20 -/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: The Device ID is read out to SPI_RD_STATUS register, this bit - combine with spi_flash_res bit. 1: enable 0: disable.*/ -#define SPI_RESANDRES (BIT(15)) -#define SPI_RESANDRES_M (BIT(15)) -#define SPI_RESANDRES_V 0x1 -#define SPI_RESANDRES_S 15 -/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ -#define SPI_FREAD_DUAL (BIT(14)) -#define SPI_FREAD_DUAL_M (BIT(14)) -#define SPI_FREAD_DUAL_V 0x1 -#define SPI_FREAD_DUAL_S 14 -/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout - and spi_fread_dout. 1: enable 0: disable.*/ -#define SPI_FASTRD_MODE (BIT(13)) -#define SPI_FASTRD_MODE_M (BIT(13)) -#define SPI_FASTRD_MODE_V 0x1 -#define SPI_FASTRD_MODE_S 13 -/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ -#define SPI_WAIT_FLASH_IDLE_EN (BIT(12)) -#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12)) -#define SPI_WAIT_FLASH_IDLE_EN_V 0x1 -#define SPI_WAIT_FLASH_IDLE_EN_S 12 -/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: For SPI1 enable crc32 when writing encrypted data to flash. - 1: enable 0:disable*/ -#define SPI_TX_CRC_EN (BIT(11)) -#define SPI_TX_CRC_EN_M (BIT(11)) -#define SPI_TX_CRC_EN_V 0x1 -#define SPI_TX_CRC_EN_S 11 -/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: For SPI1 initialize crc32 module before writing encrypted data - to flash. Active low.*/ -#define SPI_FCS_CRC_EN (BIT(10)) -#define SPI_FCS_CRC_EN_M (BIT(10)) -#define SPI_FCS_CRC_EN_V 0x1 -#define SPI_FCS_CRC_EN_S 10 - -#define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC) -/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */ -/*description: SPI cs signal is delayed by spi clock cycles*/ -#define SPI_CS_HOLD_DELAY 0x0000000F -#define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S)) -#define SPI_CS_HOLD_DELAY_V 0xF -#define SPI_CS_HOLD_DELAY_S 28 -/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */ -/*description: Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ -#define SPI_CS_HOLD_DELAY_RES 0x00000FFF -#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S)) -#define SPI_CS_HOLD_DELAY_RES_V 0xFFF -#define SPI_CS_HOLD_DELAY_RES_S 16 - -#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10) -/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */ -/*description: In the slave mode,it is the status for master to read out.*/ -#define SPI_STATUS_EXT 0x000000FF -#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S)) -#define SPI_STATUS_EXT_V 0xFF -#define SPI_STATUS_EXT_S 24 -/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ -/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ -#define SPI_WB_MODE 0x000000FF -#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S)) -#define SPI_WB_MODE_V 0xFF -#define SPI_WB_MODE_S 16 -/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: In the slave mode, it is the status for master to read out.*/ -#define SPI_STATUS 0x0000FFFF -#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S)) -#define SPI_STATUS_V 0xFFFF -#define SPI_STATUS_S 0 - -#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14) -/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: spi_cs signal is delayed by system clock cycles*/ -#define SPI_CS_DELAY_NUM 0x0000000F -#define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S)) -#define SPI_CS_DELAY_NUM_V 0xF -#define SPI_CS_DELAY_NUM_S 28 -/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ -/*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge - or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ -#define SPI_CS_DELAY_MODE 0x00000003 -#define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S)) -#define SPI_CS_DELAY_MODE_V 0x3 -#define SPI_CS_DELAY_MODE_S 26 -/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */ -/*description: MOSI signals are delayed by system clock cycles*/ -#define SPI_MOSI_DELAY_NUM 0x00000007 -#define SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S)) -#define SPI_MOSI_DELAY_NUM_V 0x7 -#define SPI_MOSI_DELAY_NUM_S 23 -/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge - or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ -#define SPI_MOSI_DELAY_MODE 0x00000003 -#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S)) -#define SPI_MOSI_DELAY_MODE_V 0x3 -#define SPI_MOSI_DELAY_MODE_S 21 -/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: MISO signals are delayed by system clock cycles*/ -#define SPI_MISO_DELAY_NUM 0x00000007 -#define SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S)) -#define SPI_MISO_DELAY_NUM_V 0x7 -#define SPI_MISO_DELAY_NUM_S 18 -/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge - or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ -#define SPI_MISO_DELAY_MODE 0x00000003 -#define SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S)) -#define SPI_MISO_DELAY_MODE_V 0x3 -#define SPI_MISO_DELAY_MODE_S 16 -/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: modify spi clock duty ratio when the value is lager than 8, - the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ -#define SPI_CK_OUT_HIGH_MODE 0x0000000F -#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S)) -#define SPI_CK_OUT_HIGH_MODE_V 0xF -#define SPI_CK_OUT_HIGH_MODE_S 12 -/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: modify spi clock duty ratio when the value is lager than 8, - the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ -#define SPI_CK_OUT_LOW_MODE 0x0000000F -#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S)) -#define SPI_CK_OUT_LOW_MODE_V 0xF -#define SPI_CK_OUT_LOW_MODE_S 8 -/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */ -/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ -#define SPI_HOLD_TIME 0x0000000F -#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S)) -#define SPI_HOLD_TIME_V 0xF -#define SPI_HOLD_TIME_S 4 -/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */ -/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined - with spi_cs_setup bit.*/ -#define SPI_SETUP_TIME 0x0000000F -#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S)) -#define SPI_SETUP_TIME_V 0xF -#define SPI_SETUP_TIME_S 0 - -#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18) -/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is - divided from system clock.*/ -#define SPI_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_CLK_EQU_SYSCLK_V 0x1 -#define SPI_CLK_EQU_SYSCLK_S 31 -/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ -/*description: In the master mode it is pre-divider of spi_clk.*/ -#define SPI_CLKDIV_PRE 0x00001FFF -#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) -#define SPI_CLKDIV_PRE_V 0x1FFF -#define SPI_CLKDIV_PRE_S 18 -/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ -/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency - is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ -#define SPI_CLKCNT_N 0x0000003F -#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) -#define SPI_CLKCNT_N_V 0x3F -#define SPI_CLKCNT_N_S 12 -/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ -/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In - the slave mode it must be 0.*/ -#define SPI_CLKCNT_H 0x0000003F -#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) -#define SPI_CLKCNT_H_V 0x3F -#define SPI_CLKCNT_H_S 6 -/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ -/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave - mode it must be 0.*/ -#define SPI_CLKCNT_L 0x0000003F -#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) -#define SPI_CLKCNT_L_V 0x3F -#define SPI_CLKCNT_L_S 0 - -#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C) -/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit enable the command phase of an operation.*/ -#define SPI_USR_COMMAND (BIT(31)) -#define SPI_USR_COMMAND_M (BIT(31)) -#define SPI_USR_COMMAND_V 0x1 -#define SPI_USR_COMMAND_S 31 -/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit enable the address phase of an operation.*/ -#define SPI_USR_ADDR (BIT(30)) -#define SPI_USR_ADDR_M (BIT(30)) -#define SPI_USR_ADDR_V 0x1 -#define SPI_USR_ADDR_S 30 -/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: This bit enable the dummy phase of an operation.*/ -#define SPI_USR_DUMMY (BIT(29)) -#define SPI_USR_DUMMY_M (BIT(29)) -#define SPI_USR_DUMMY_V 0x1 -#define SPI_USR_DUMMY_S 29 -/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: This bit enable the read-data phase of an operation.*/ -#define SPI_USR_MISO (BIT(28)) -#define SPI_USR_MISO_M (BIT(28)) -#define SPI_USR_MISO_V 0x1 -#define SPI_USR_MISO_S 28 -/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This bit enable the write-data phase of an operation.*/ -#define SPI_USR_MOSI (BIT(27)) -#define SPI_USR_MOSI_M (BIT(27)) -#define SPI_USR_MOSI_V 0x1 -#define SPI_USR_MOSI_S 27 -/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: spi clock is disable in dummy phase when the bit is enable.*/ -#define SPI_USR_DUMMY_IDLE (BIT(26)) -#define SPI_USR_DUMMY_IDLE_M (BIT(26)) -#define SPI_USR_DUMMY_IDLE_V 0x1 -#define SPI_USR_DUMMY_IDLE_S 26 -/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable.*/ -#define SPI_USR_MOSI_HIGHPART (BIT(25)) -#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) -#define SPI_USR_MOSI_HIGHPART_V 0x1 -#define SPI_USR_MOSI_HIGHPART_S 25 -/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable.*/ -#define SPI_USR_MISO_HIGHPART (BIT(24)) -#define SPI_USR_MISO_HIGHPART_M (BIT(24)) -#define SPI_USR_MISO_HIGHPART_V 0x1 -#define SPI_USR_MISO_HIGHPART_S 24 -/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_PREP_HOLD (BIT(23)) -#define SPI_USR_PREP_HOLD_M (BIT(23)) -#define SPI_USR_PREP_HOLD_V 0x1 -#define SPI_USR_PREP_HOLD_S 23 -/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_CMD_HOLD (BIT(22)) -#define SPI_USR_CMD_HOLD_M (BIT(22)) -#define SPI_USR_CMD_HOLD_V 0x1 -#define SPI_USR_CMD_HOLD_S 22 -/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_ADDR_HOLD (BIT(21)) -#define SPI_USR_ADDR_HOLD_M (BIT(21)) -#define SPI_USR_ADDR_HOLD_V 0x1 -#define SPI_USR_ADDR_HOLD_S 21 -/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_DUMMY_HOLD (BIT(20)) -#define SPI_USR_DUMMY_HOLD_M (BIT(20)) -#define SPI_USR_DUMMY_HOLD_V 0x1 -#define SPI_USR_DUMMY_HOLD_S 20 -/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_DIN_HOLD (BIT(19)) -#define SPI_USR_DIN_HOLD_M (BIT(19)) -#define SPI_USR_DIN_HOLD_V 0x1 -#define SPI_USR_DIN_HOLD_S 19 -/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_DOUT_HOLD (BIT(18)) -#define SPI_USR_DOUT_HOLD_M (BIT(18)) -#define SPI_USR_DOUT_HOLD_V 0x1 -#define SPI_USR_DOUT_HOLD_S 18 -/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: It is combined with hold bits to set the polarity of spi hold - line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ -#define SPI_USR_HOLD_POL (BIT(17)) -#define SPI_USR_HOLD_POL_M (BIT(17)) -#define SPI_USR_HOLD_POL_V 0x1 -#define SPI_USR_HOLD_POL_S 17 -/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set the bit to enable 3-line half duplex communication mosi - and miso signals share the same pin. 1: enable 0: disable.*/ -#define SPI_SIO (BIT(16)) -#define SPI_SIO_M (BIT(16)) -#define SPI_SIO_V 0x1 -#define SPI_SIO_S 16 -/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: In the write operations address phase and read-data phase apply 4 signals.*/ -#define SPI_FWRITE_QIO (BIT(15)) -#define SPI_FWRITE_QIO_M (BIT(15)) -#define SPI_FWRITE_QIO_V 0x1 -#define SPI_FWRITE_QIO_S 15 -/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the write operations address phase and read-data phase apply 2 signals.*/ -#define SPI_FWRITE_DIO (BIT(14)) -#define SPI_FWRITE_DIO_M (BIT(14)) -#define SPI_FWRITE_DIO_V 0x1 -#define SPI_FWRITE_DIO_S 14 -/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 4 signals*/ -#define SPI_FWRITE_QUAD (BIT(13)) -#define SPI_FWRITE_QUAD_M (BIT(13)) -#define SPI_FWRITE_QUAD_V 0x1 -#define SPI_FWRITE_QUAD_S 13 -/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 2 signals*/ -#define SPI_FWRITE_DUAL (BIT(12)) -#define SPI_FWRITE_DUAL_M (BIT(12)) -#define SPI_FWRITE_DUAL_V 0x1 -#define SPI_FWRITE_DUAL_S 12 -/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ -#define SPI_WR_BYTE_ORDER (BIT(11)) -#define SPI_WR_BYTE_ORDER_M (BIT(11)) -#define SPI_WR_BYTE_ORDER_V 0x1 -#define SPI_WR_BYTE_ORDER_S 11 -/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/ -#define SPI_RD_BYTE_ORDER (BIT(10)) -#define SPI_RD_BYTE_ORDER_M (BIT(10)) -#define SPI_RD_BYTE_ORDER_V 0x1 -#define SPI_RD_BYTE_ORDER_S 10 -/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ -#define SPI_CK_OUT_EDGE (BIT(7)) -#define SPI_CK_OUT_EDGE_M (BIT(7)) -#define SPI_CK_OUT_EDGE_V 0x1 -#define SPI_CK_OUT_EDGE_S 7 -/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: In the slave mode the bit is same as spi_ck_out_edge in master - mode. It is combined with spi_miso_delay_mode bits.*/ -#define SPI_CK_I_EDGE (BIT(6)) -#define SPI_CK_I_EDGE_M (BIT(6)) -#define SPI_CK_I_EDGE_V 0x1 -#define SPI_CK_I_EDGE_S 6 -/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.*/ -#define SPI_CS_SETUP (BIT(5)) -#define SPI_CS_SETUP_M (BIT(5)) -#define SPI_CS_SETUP_V 0x1 -#define SPI_CS_SETUP_S 5 -/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.*/ -#define SPI_CS_HOLD (BIT(4)) -#define SPI_CS_HOLD_M (BIT(4)) -#define SPI_CS_HOLD_V 0x1 -#define SPI_CS_HOLD_S 4 -/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/ -#define SPI_DOUTDIN (BIT(0)) -#define SPI_DOUTDIN_M (BIT(0)) -#define SPI_DOUTDIN_V 0x1 -#define SPI_DOUTDIN_S 0 - -#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20) -/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */ -/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/ -#define SPI_USR_ADDR_BITLEN 0x0000003F -#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) -#define SPI_USR_ADDR_BITLEN_V 0x3F -#define SPI_USR_ADDR_BITLEN_S 26 -/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ -/*description: The length in spi_clk cycles of dummy phase. The register value - shall be (cycle_num-1).*/ -#define SPI_USR_DUMMY_CYCLELEN 0x000000FF -#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) -#define SPI_USR_DUMMY_CYCLELEN_V 0xFF -#define SPI_USR_DUMMY_CYCLELEN_S 0 - -#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x24) -/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ -/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/ -#define SPI_USR_COMMAND_BITLEN 0x0000000F -#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) -#define SPI_USR_COMMAND_BITLEN_V 0xF -#define SPI_USR_COMMAND_BITLEN_S 28 -/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: The value of command.*/ -#define SPI_USR_COMMAND_VALUE 0x0000FFFF -#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) -#define SPI_USR_COMMAND_VALUE_V 0xFFFF -#define SPI_USR_COMMAND_VALUE_S 0 - -#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28) -/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/ -#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF -#define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S)) -#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF -#define SPI_USR_MOSI_DBITLEN_S 0 - -#define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x2C) -/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/ -#define SPI_USR_MISO_DBITLEN 0x00FFFFFF -#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S)) -#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF -#define SPI_USR_MISO_DBITLEN_S 0 - -#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30) -/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: In the slave mode this register are the status register for the - master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ -#define SPI_SLV_WR_ST 0xFFFFFFFF -#define SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S)) -#define SPI_SLV_WR_ST_V 0xFFFFFFFF -#define SPI_SLV_WR_ST_S 0 - -#define SPI_PIN_REG(i) (REG_SPI_BASE(i) + 0x34) -/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: spi cs line keep low when the bit is set.*/ -#define SPI_CS_KEEP_ACTIVE (BIT(30)) -#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) -#define SPI_CS_KEEP_ACTIVE_V 0x1 -#define SPI_CS_KEEP_ACTIVE_S 30 -/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/ -#define SPI_CK_IDLE_EDGE (BIT(29)) -#define SPI_CK_IDLE_EDGE_M (BIT(29)) -#define SPI_CK_IDLE_EDGE_V 0x1 -#define SPI_CK_IDLE_EDGE_S 29 -/* SPI_MASTER_CK_SEL : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ -/*description: In the master mode spi cs line is enable as spi clk it is combined - with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ -#define SPI_MASTER_CK_SEL 0x00000007 -#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S)) -#define SPI_MASTER_CK_SEL_V 0x07 -#define SPI_MASTER_CK_SEL_S 11 -/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */ -/*description: In the master mode the bits are the polarity of spi cs line - the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ -#define SPI_MASTER_CS_POL 0x00000007 -#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) -#define SPI_MASTER_CS_POL_V 0x7 -#define SPI_MASTER_CS_POL_S 6 -/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: 1: spi clk out disable 0: spi clk out enable*/ -#define SPI_CK_DIS (BIT(5)) -#define SPI_CK_DIS_M (BIT(5)) -#define SPI_CK_DIS_V 0x1 -#define SPI_CK_DIS_S 5 -/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ -#define SPI_CS2_DIS (BIT(2)) -#define SPI_CS2_DIS_M (BIT(2)) -#define SPI_CS2_DIS_V 0x1 -#define SPI_CS2_DIS_S 2 -/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ -#define SPI_CS1_DIS (BIT(1)) -#define SPI_CS1_DIS_M (BIT(1)) -#define SPI_CS1_DIS_V 0x1 -#define SPI_CS1_DIS_S 1 -/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ -#define SPI_CS0_DIS (BIT(0)) -#define SPI_CS0_DIS_M (BIT(0)) -#define SPI_CS0_DIS_V 0x1 -#define SPI_CS0_DIS_S 0 - -#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38) -/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Software reset enable, reset the spi clock line cs line and data lines.*/ -#define SPI_SYNC_RESET (BIT(31)) -#define SPI_SYNC_RESET_M (BIT(31)) -#define SPI_SYNC_RESET_V 0x1 -#define SPI_SYNC_RESET_S 31 -/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 1: slave mode 0: master mode.*/ -#define SPI_SLAVE_MODE (BIT(30)) -#define SPI_SLAVE_MODE_M (BIT(30)) -#define SPI_SLAVE_MODE_V 0x1 -#define SPI_SLAVE_MODE_S 30 -/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: write and read buffer enable in the slave mode*/ -#define SPI_SLV_WR_RD_BUF_EN (BIT(29)) -#define SPI_SLV_WR_RD_BUF_EN_M (BIT(29)) -#define SPI_SLV_WR_RD_BUF_EN_V 0x1 -#define SPI_SLV_WR_RD_BUF_EN_S 29 -/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: write and read status enable in the slave mode*/ -#define SPI_SLV_WR_RD_STA_EN (BIT(28)) -#define SPI_SLV_WR_RD_STA_EN_M (BIT(28)) -#define SPI_SLV_WR_RD_STA_EN_V 0x1 -#define SPI_SLV_WR_RD_STA_EN_S 28 -/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode - commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ -#define SPI_SLV_CMD_DEFINE (BIT(27)) -#define SPI_SLV_CMD_DEFINE_M (BIT(27)) -#define SPI_SLV_CMD_DEFINE_V 0x1 -#define SPI_SLV_CMD_DEFINE_S 27 -/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */ -/*description: The operations counter in both the master mode and the slave - mode. 4: read-status*/ -#define SPI_TRANS_CNT 0x0000000F -#define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S)) -#define SPI_TRANS_CNT_V 0xF -#define SPI_TRANS_CNT_S 23 -/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: In the slave mode it is the state of spi state machine.*/ -#define SPI_SLV_LAST_STATE 0x00000007 -#define SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S)) -#define SPI_SLV_LAST_STATE_V 0x7 -#define SPI_SLV_LAST_STATE_S 20 -/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */ -/*description: In the slave mode it is the value of command.*/ -#define SPI_SLV_LAST_COMMAND 0x00000007 -#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) -#define SPI_SLV_LAST_COMMAND_V 0x7 -#define SPI_SLV_LAST_COMMAND_S 17 -/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: In the slave mode this bits used to synchronize the input spi - cs signal and eliminate spi cs jitter.*/ -#define SPI_CS_I_MODE 0x00000003 -#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S)) -#define SPI_CS_I_MODE_V 0x3 -#define SPI_CS_I_MODE_S 10 -/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */ -/*description: Interrupt enable bits for the below 5 sources*/ -#define SPI_INT_EN 0x0000001F -#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S)) -#define SPI_INT_EN_V 0x1F -#define SPI_INT_EN_S 5 -/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of any operation in - both the master mode and the slave mode.*/ -#define SPI_TRANS_DONE (BIT(4)) -#define SPI_TRANS_DONE_M (BIT(4)) -#define SPI_TRANS_DONE_V 0x1 -#define SPI_TRANS_DONE_S 4 -/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of write-status operation - in the slave mode.*/ -#define SPI_SLV_WR_STA_DONE (BIT(3)) -#define SPI_SLV_WR_STA_DONE_M (BIT(3)) -#define SPI_SLV_WR_STA_DONE_V 0x1 -#define SPI_SLV_WR_STA_DONE_S 3 -/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of read-status operation - in the slave mode.*/ -#define SPI_SLV_RD_STA_DONE (BIT(2)) -#define SPI_SLV_RD_STA_DONE_M (BIT(2)) -#define SPI_SLV_RD_STA_DONE_V 0x1 -#define SPI_SLV_RD_STA_DONE_S 2 -/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of write-buffer operation - in the slave mode.*/ -#define SPI_SLV_WR_BUF_DONE (BIT(1)) -#define SPI_SLV_WR_BUF_DONE_M (BIT(1)) -#define SPI_SLV_WR_BUF_DONE_V 0x1 -#define SPI_SLV_WR_BUF_DONE_S 1 -/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of read-buffer operation - in the slave mode.*/ -#define SPI_SLV_RD_BUF_DONE (BIT(0)) -#define SPI_SLV_RD_BUF_DONE_M (BIT(0)) -#define SPI_SLV_RD_BUF_DONE_V 0x1 -#define SPI_SLV_RD_BUF_DONE_S 0 - -#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x3C) -/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */ -/*description: In the slave mode it is the length of status bit.*/ -#define SPI_SLV_STATUS_BITLEN 0x0000001F -#define SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S)) -#define SPI_SLV_STATUS_BITLEN_V 0x1F -#define SPI_SLV_STATUS_BITLEN_S 27 -/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: In the slave mode enable fast read status.*/ -#define SPI_SLV_STATUS_FAST_EN (BIT(26)) -#define SPI_SLV_STATUS_FAST_EN_M (BIT(26)) -#define SPI_SLV_STATUS_FAST_EN_V 0x1 -#define SPI_SLV_STATUS_FAST_EN_S 26 -/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read - register of SPI_RD_STATUS.*/ -#define SPI_SLV_STATUS_READBACK (BIT(25)) -#define SPI_SLV_STATUS_READBACK_M (BIT(25)) -#define SPI_SLV_STATUS_READBACK_V 0x1 -#define SPI_SLV_STATUS_READBACK_S 25 -/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ -/*description: In the slave mode it is the address length in bits for read-buffer - operation. The register value shall be (bit_num-1).*/ -#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F -#define SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S)) -#define SPI_SLV_RD_ADDR_BITLEN_V 0x3F -#define SPI_SLV_RD_ADDR_BITLEN_S 10 -/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */ -/*description: In the slave mode it is the address length in bits for write-buffer - operation. The register value shall be (bit_num-1).*/ -#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F -#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S)) -#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F -#define SPI_SLV_WR_ADDR_BITLEN_S 4 -/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: In the slave mode it is the enable bit of dummy phase for write-status - operations.*/ -#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3)) -#define SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3)) -#define SPI_SLV_WRSTA_DUMMY_EN_V 0x1 -#define SPI_SLV_WRSTA_DUMMY_EN_S 3 -/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: In the slave mode it is the enable bit of dummy phase for read-status - operations.*/ -#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2)) -#define SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2)) -#define SPI_SLV_RDSTA_DUMMY_EN_V 0x1 -#define SPI_SLV_RDSTA_DUMMY_EN_S 2 -/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: In the slave mode it is the enable bit of dummy phase for write-buffer - operations.*/ -#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1)) -#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1)) -#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1 -#define SPI_SLV_WRBUF_DUMMY_EN_S 1 -/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: In the slave mode it is the enable bit of dummy phase for read-buffer - operations.*/ -#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0)) -#define SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0)) -#define SPI_SLV_RDBUF_DUMMY_EN_V 0x1 -#define SPI_SLV_RDBUF_DUMMY_EN_S 0 - -#define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x40) -/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ -/*description: In the slave mode it is the length in spi_clk cycles of dummy - phase for write-buffer operations. The register value shall be (cycle_num-1).*/ -#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF -#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S)) -#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF -#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24 -/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: In the slave mode it is the length in spi_clk cycles of dummy - phase for read-buffer operations. The register value shall be (cycle_num-1).*/ -#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF -#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S)) -#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF -#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16 -/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: In the slave mode it is the length in spi_clk cycles of dummy - phase for write-status operations. The register value shall be (cycle_num-1).*/ -#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF -#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S)) -#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF -#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8 -/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: In the slave mode it is the length in spi_clk cycles of dummy - phase for read-status operations. The register value shall be (cycle_num-1).*/ -#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF -#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S)) -#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF -#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0 - -#define SPI_SLAVE3_REG(i) (REG_SPI_BASE(i) + 0x44) -/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ -/*description: In the slave mode it is the value of write-status command.*/ -#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF -#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S)) -#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF -#define SPI_SLV_WRSTA_CMD_VALUE_S 24 -/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */ -/*description: In the slave mode it is the value of read-status command.*/ -#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF -#define SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S)) -#define SPI_SLV_RDSTA_CMD_VALUE_V 0xFF -#define SPI_SLV_RDSTA_CMD_VALUE_S 16 -/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ -/*description: In the slave mode it is the value of write-buffer command.*/ -#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF -#define SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S)) -#define SPI_SLV_WRBUF_CMD_VALUE_V 0xFF -#define SPI_SLV_WRBUF_CMD_VALUE_S 8 -/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: In the slave mode it is the value of read-buffer command.*/ -#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF -#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S)) -#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF -#define SPI_SLV_RDBUF_CMD_VALUE_S 0 - -#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48) -/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: In the slave mode it is the length in bits for write-buffer operations. - The register value shall be (bit_num-1).*/ -#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF -#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S)) -#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF -#define SPI_SLV_WRBUF_DBITLEN_S 0 - -#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x4C) -/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: In the slave mode it is the length in bits for read-buffer operations. - The register value shall be (bit_num-1).*/ -#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF -#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S)) -#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF -#define SPI_SLV_RDBUF_DBITLEN_S 0 - -#define SPI_CACHE_FCTRL_REG(i) (REG_SPI_BASE(i) + 0x50) -/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: For SPI0 spi1 send suspend command before cache read flash - 1: enable 0:disable.*/ -#define SPI_CACHE_FLASH_PES_EN (BIT(3)) -#define SPI_CACHE_FLASH_PES_EN_M (BIT(3)) -#define SPI_CACHE_FLASH_PES_EN_V 0x1 -#define SPI_CACHE_FLASH_PES_EN_S 3 -/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/ -#define SPI_CACHE_FLASH_USR_CMD (BIT(2)) -#define SPI_CACHE_FLASH_USR_CMD_M (BIT(2)) -#define SPI_CACHE_FLASH_USR_CMD_V 0x1 -#define SPI_CACHE_FLASH_USR_CMD_S 2 -/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ -#define SPI_CACHE_USR_CMD_4BYTE (BIT(1)) -#define SPI_CACHE_USR_CMD_4BYTE_M (BIT(1)) -#define SPI_CACHE_USR_CMD_4BYTE_V 0x1 -#define SPI_CACHE_USR_CMD_4BYTE_S 1 -/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: For SPI0 Cache access enable 1: enable 0:disable.*/ -#define SPI_CACHE_REQ_EN (BIT(0)) -#define SPI_CACHE_REQ_EN_M (BIT(0)) -#define SPI_CACHE_REQ_EN_V 0x1 -#define SPI_CACHE_REQ_EN_S 0 - -#define SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54) -/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: For SPI0 In the spi sram mode cache write sram for user define command*/ -#define SPI_CACHE_SRAM_USR_WCMD (BIT(28)) -#define SPI_CACHE_SRAM_USR_WCMD_M (BIT(28)) -#define SPI_CACHE_SRAM_USR_WCMD_V 0x1 -#define SPI_CACHE_SRAM_USR_WCMD_S 28 -/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */ -/*description: For SPI0 In the sram mode it is the length in bits of address - phase. The register value shall be (bit_num-1).*/ -#define SPI_SRAM_ADDR_BITLEN 0x0000003F -#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S)) -#define SPI_SRAM_ADDR_BITLEN_V 0x3F -#define SPI_SRAM_ADDR_BITLEN_S 22 -/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */ -/*description: For SPI0 In the sram mode it is the length in bits of address - phase. The register value shall be (bit_num-1).*/ -#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF -#define SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S)) -#define SPI_SRAM_DUMMY_CYCLELEN_V 0xFF -#define SPI_SRAM_DUMMY_CYCLELEN_S 14 -/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */ -/*description: For SPI0 In the sram mode it is the byte length of spi read sram data.*/ -#define SPI_SRAM_BYTES_LEN 0x000000FF -#define SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S)) -#define SPI_SRAM_BYTES_LEN_V 0xFF -#define SPI_SRAM_BYTES_LEN_S 6 -/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/ -#define SPI_CACHE_SRAM_USR_RCMD (BIT(5)) -#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5)) -#define SPI_CACHE_SRAM_USR_RCMD_V 0x1 -#define SPI_CACHE_SRAM_USR_RCMD_S 5 -/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: For SPI0 In the spi sram mode it is the enable bit of dummy - phase for read operations.*/ -#define SPI_USR_RD_SRAM_DUMMY (BIT(4)) -#define SPI_USR_RD_SRAM_DUMMY_M (BIT(4)) -#define SPI_USR_RD_SRAM_DUMMY_V 0x1 -#define SPI_USR_RD_SRAM_DUMMY_S 4 -/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: For SPI0 In the spi sram mode it is the enable bit of dummy - phase for write operations.*/ -#define SPI_USR_WR_SRAM_DUMMY (BIT(3)) -#define SPI_USR_WR_SRAM_DUMMY_M (BIT(3)) -#define SPI_USR_WR_SRAM_DUMMY_V 0x1 -#define SPI_USR_WR_SRAM_DUMMY_S 3 -/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ -#define SPI_USR_SRAM_QIO (BIT(2)) -#define SPI_USR_SRAM_QIO_M (BIT(2)) -#define SPI_USR_SRAM_QIO_V 0x1 -#define SPI_USR_SRAM_QIO_S 2 -/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ -#define SPI_USR_SRAM_DIO (BIT(1)) -#define SPI_USR_SRAM_DIO_M (BIT(1)) -#define SPI_USR_SRAM_DIO_V 0x1 -#define SPI_USR_SRAM_DIO_S 1 - -#define SPI_SRAM_CMD_REG(i) (REG_SPI_BASE(i) + 0x58) -/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation - will be triggered when the bit is set. The bit will be cleared once the operation done*/ -#define SPI_SRAM_RSTIO (BIT(4)) -#define SPI_SRAM_RSTIO_M (BIT(4)) -#define SPI_SRAM_RSTIO_V 0x1 -#define SPI_SRAM_RSTIO_S 4 -/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will - be send when the bit is set. The bit will be cleared once the operation done.*/ -#define SPI_SRAM_QIO (BIT(1)) -#define SPI_SRAM_QIO_M (BIT(1)) -#define SPI_SRAM_QIO_V 0x1 -#define SPI_SRAM_QIO_S 1 -/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will - be send when the bit is set. The bit will be cleared once the operation done.*/ -#define SPI_SRAM_DIO (BIT(0)) -#define SPI_SRAM_DIO_M (BIT(0)) -#define SPI_SRAM_DIO_V 0x1 -#define SPI_SRAM_DIO_S 0 - -#define SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + 0x5C) -/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the length in bits of - command phase for SRAM. The register value shall be (bit_num-1).*/ -#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F -#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) -#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF -#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 -/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the read command value - of command phase for SRAM.*/ -#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF -#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S)) -#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF -#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 - -#define SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + 0x60) -/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the in bits of command - phase for SRAM. The register value shall be (bit_num-1).*/ -#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F -#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) -#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF -#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 -/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the write command value - of command phase for SRAM.*/ -#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF -#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S)) -#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF -#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 - -#define SPI_SLV_RD_BIT_REG(i) (REG_SPI_BASE(i) + 0x64) -/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: In the slave mode it is the bit length of read data. The value - is the length - 1.*/ -#define SPI_SLV_RDATA_BIT 0x00FFFFFF -#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S)) -#define SPI_SLV_RDATA_BIT_V 0xFFFFFF -#define SPI_SLV_RDATA_BIT_S 0 - -#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x80) -/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF0 0xFFFFFFFF -#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) -#define SPI_BUF0_V 0xFFFFFFFF -#define SPI_BUF0_S 0 - -#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x84) -/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF1 0xFFFFFFFF -#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) -#define SPI_BUF1_V 0xFFFFFFFF -#define SPI_BUF1_S 0 - -#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x88) -/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF2 0xFFFFFFFF -#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) -#define SPI_BUF2_V 0xFFFFFFFF -#define SPI_BUF2_S 0 - -#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x8C) -/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF3 0xFFFFFFFF -#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) -#define SPI_BUF3_V 0xFFFFFFFF -#define SPI_BUF3_S 0 - -#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x90) -/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF4 0xFFFFFFFF -#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) -#define SPI_BUF4_V 0xFFFFFFFF -#define SPI_BUF4_S 0 - -#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x94) -/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF5 0xFFFFFFFF -#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) -#define SPI_BUF5_V 0xFFFFFFFF -#define SPI_BUF5_S 0 - -#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x98) -/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF6 0xFFFFFFFF -#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) -#define SPI_BUF6_V 0xFFFFFFFF -#define SPI_BUF6_S 0 - -#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x9C) -/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF7 0xFFFFFFFF -#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) -#define SPI_BUF7_V 0xFFFFFFFF -#define SPI_BUF7_S 0 - -#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xA0) -/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF8 0xFFFFFFFF -#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) -#define SPI_BUF8_V 0xFFFFFFFF -#define SPI_BUF8_S 0 - -#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xA4) -/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF9 0xFFFFFFFF -#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) -#define SPI_BUF9_V 0xFFFFFFFF -#define SPI_BUF9_S 0 - -#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xA8) -/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF10 0xFFFFFFFF -#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) -#define SPI_BUF10_V 0xFFFFFFFF -#define SPI_BUF10_S 0 - -#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xAC) -/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF11 0xFFFFFFFF -#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) -#define SPI_BUF11_V 0xFFFFFFFF -#define SPI_BUF11_S 0 - -#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xB0) -/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF12 0xFFFFFFFF -#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) -#define SPI_BUF12_V 0xFFFFFFFF -#define SPI_BUF12_S 0 - -#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xB4) -/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF13 0xFFFFFFFF -#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) -#define SPI_BUF13_V 0xFFFFFFFF -#define SPI_BUF13_S 0 - -#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xB8) -/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF14 0xFFFFFFFF -#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) -#define SPI_BUF14_V 0xFFFFFFFF -#define SPI_BUF14_S 0 - -#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xBC) -/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF15 0xFFFFFFFF -#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) -#define SPI_BUF15_V 0xFFFFFFFF -#define SPI_BUF15_S 0 - -#define SPI_TX_CRC_REG(i) (REG_SPI_BASE(i) + 0xC0) -/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: For SPI1 the value of crc32 for 256 bits data.*/ -#define SPI_TX_CRC_DATA 0xFFFFFFFF -#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S)) -#define SPI_TX_CRC_DATA_V 0xFFFFFFFF -#define SPI_TX_CRC_DATA_S 0 - -#define SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0) -/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: page program delay enable.*/ -#define SPI_T_PP_ENA (BIT(31)) -#define SPI_T_PP_ENA_M (BIT(31)) -#define SPI_T_PP_ENA_V 0x1 -#define SPI_T_PP_ENA_S 31 -/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */ -/*description: page program delay time shift .*/ -#define SPI_T_PP_SHIFT 0x0000000F -#define SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S)) -#define SPI_T_PP_SHIFT_V 0xF -#define SPI_T_PP_SHIFT_S 16 -/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */ -/*description: page program delay time by system clock.*/ -#define SPI_T_PP_TIME 0x00000FFF -#define SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S)) -#define SPI_T_PP_TIME_V 0xFFF -#define SPI_T_PP_TIME_S 0 - -#define SPI_EXT1_REG(i) (REG_SPI_BASE(i) + 0xF4) -/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: erase flash delay enable.*/ -#define SPI_T_ERASE_ENA (BIT(31)) -#define SPI_T_ERASE_ENA_M (BIT(31)) -#define SPI_T_ERASE_ENA_V 0x1 -#define SPI_T_ERASE_ENA_S 31 -/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */ -/*description: erase flash delay time shift.*/ -#define SPI_T_ERASE_SHIFT 0x0000000F -#define SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S)) -#define SPI_T_ERASE_SHIFT_V 0xF -#define SPI_T_ERASE_SHIFT_S 16 -/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */ -/*description: erase flash delay time by system clock.*/ -#define SPI_T_ERASE_TIME 0x00000FFF -#define SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S)) -#define SPI_T_ERASE_TIME_V 0xFFF -#define SPI_T_ERASE_TIME_S 0 - -#define SPI_EXT2_REG(i) (REG_SPI_BASE(i) + 0xF8) -/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The status of spi state machine .*/ -#define SPI_ST 0x00000007 -#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S)) -#define SPI_ST_V 0x7 -#define SPI_ST_S 0 - -#define SPI_EXT3_REG(i) (REG_SPI_BASE(i) + 0xFC) -/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: This register is for two SPI masters to share the same cs clock - and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/ -#define SPI_INT_HOLD_ENA 0x00000003 -#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S)) -#define SPI_INT_HOLD_ENA_V 0x3 -#define SPI_INT_HOLD_ENA_S 0 - -#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x100) -/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: spi dma continue tx/rx data.*/ -#define SPI_DMA_CONTINUE (BIT(16)) -#define SPI_DMA_CONTINUE_M (BIT(16)) -#define SPI_DMA_CONTINUE_V 0x1 -#define SPI_DMA_CONTINUE_S 16 -/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: spi dma write data stop when in continue tx/rx mode.*/ -#define SPI_DMA_TX_STOP (BIT(15)) -#define SPI_DMA_TX_STOP_M (BIT(15)) -#define SPI_DMA_TX_STOP_V 0x1 -#define SPI_DMA_TX_STOP_S 15 -/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: spi dma read data stop when in continue tx/rx mode.*/ -#define SPI_DMA_RX_STOP (BIT(14)) -#define SPI_DMA_RX_STOP_M (BIT(14)) -#define SPI_DMA_RX_STOP_V 0x1 -#define SPI_DMA_RX_STOP_S 14 -/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: spi dma read data from memory in burst mode.*/ -#define SPI_OUT_DATA_BURST_EN (BIT(12)) -#define SPI_OUT_DATA_BURST_EN_M (BIT(12)) -#define SPI_OUT_DATA_BURST_EN_V 0x1 -#define SPI_OUT_DATA_BURST_EN_S 12 -/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: read descriptor use burst mode when write data to memory.*/ -#define SPI_INDSCR_BURST_EN (BIT(11)) -#define SPI_INDSCR_BURST_EN_M (BIT(11)) -#define SPI_INDSCR_BURST_EN_V 0x1 -#define SPI_INDSCR_BURST_EN_S 11 -/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: read descriptor use burst mode when read data for memory.*/ -#define SPI_OUTDSCR_BURST_EN (BIT(10)) -#define SPI_OUTDSCR_BURST_EN_M (BIT(10)) -#define SPI_OUTDSCR_BURST_EN_V 0x1 -#define SPI_OUTDSCR_BURST_EN_S 10 -/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: out eof flag generation mode . 1: when dma pop all data from - fifo 0:when ahb push all data to fifo.*/ -#define SPI_OUT_EOF_MODE (BIT(9)) -#define SPI_OUT_EOF_MODE_M (BIT(9)) -#define SPI_OUT_EOF_MODE_V 0x1 -#define SPI_OUT_EOF_MODE_S 9 -/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: when the link is empty jump to next automatically.*/ -#define SPI_OUT_AUTO_WRBACK (BIT(8)) -#define SPI_OUT_AUTO_WRBACK_M (BIT(8)) -#define SPI_OUT_AUTO_WRBACK_V 0x1 -#define SPI_OUT_AUTO_WRBACK_S 8 -/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set bit to test out link.*/ -#define SPI_OUT_LOOP_TEST (BIT(7)) -#define SPI_OUT_LOOP_TEST_M (BIT(7)) -#define SPI_OUT_LOOP_TEST_V 0x1 -#define SPI_OUT_LOOP_TEST_S 7 -/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set bit to test in link.*/ -#define SPI_IN_LOOP_TEST (BIT(6)) -#define SPI_IN_LOOP_TEST_M (BIT(6)) -#define SPI_IN_LOOP_TEST_V 0x1 -#define SPI_IN_LOOP_TEST_S 6 -/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: reset spi dma ahb master.*/ -#define SPI_AHBM_RST (BIT(5)) -#define SPI_AHBM_RST_M (BIT(5)) -#define SPI_AHBM_RST_V 0x1 -#define SPI_AHBM_RST_S 5 -/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: reset spi dma ahb master fifo pointer.*/ -#define SPI_AHBM_FIFO_RST (BIT(4)) -#define SPI_AHBM_FIFO_RST_M (BIT(4)) -#define SPI_AHBM_FIFO_RST_V 0x1 -#define SPI_AHBM_FIFO_RST_S 4 -/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/ -#define SPI_OUT_RST (BIT(3)) -#define SPI_OUT_RST_M (BIT(3)) -#define SPI_OUT_RST_V 0x1 -#define SPI_OUT_RST_S 3 -/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/ -#define SPI_IN_RST (BIT(2)) -#define SPI_IN_RST_M (BIT(2)) -#define SPI_IN_RST_V 0x1 -#define SPI_IN_RST_S 2 - -#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x104) -/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set the bit to mount on new outlink descriptors.*/ -#define SPI_OUTLINK_RESTART (BIT(30)) -#define SPI_OUTLINK_RESTART_M (BIT(30)) -#define SPI_OUTLINK_RESTART_V 0x1 -#define SPI_OUTLINK_RESTART_S 30 -/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set the bit to start to use outlink descriptor.*/ -#define SPI_OUTLINK_START (BIT(29)) -#define SPI_OUTLINK_START_M (BIT(29)) -#define SPI_OUTLINK_START_V 0x1 -#define SPI_OUTLINK_START_S 29 -/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set the bit to stop to use outlink descriptor.*/ -#define SPI_OUTLINK_STOP (BIT(28)) -#define SPI_OUTLINK_STOP_M (BIT(28)) -#define SPI_OUTLINK_STOP_V 0x1 -#define SPI_OUTLINK_STOP_S 28 -/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The address of the first outlink descriptor.*/ -#define SPI_OUTLINK_ADDR 0x000FFFFF -#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S)) -#define SPI_OUTLINK_ADDR_V 0xFFFFF -#define SPI_OUTLINK_ADDR_S 0 - -#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x108) -/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set the bit to mount on new inlink descriptors.*/ -#define SPI_INLINK_RESTART (BIT(30)) -#define SPI_INLINK_RESTART_M (BIT(30)) -#define SPI_INLINK_RESTART_V 0x1 -#define SPI_INLINK_RESTART_S 30 -/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set the bit to start to use inlink descriptor.*/ -#define SPI_INLINK_START (BIT(29)) -#define SPI_INLINK_START_M (BIT(29)) -#define SPI_INLINK_START_V 0x1 -#define SPI_INLINK_START_S 29 -/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set the bit to stop to use inlink descriptor.*/ -#define SPI_INLINK_STOP (BIT(28)) -#define SPI_INLINK_STOP_M (BIT(28)) -#define SPI_INLINK_STOP_V 0x1 -#define SPI_INLINK_STOP_S 28 -/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: when the bit is set inlink descriptor returns to the next descriptor - while a packet is wrong*/ -#define SPI_INLINK_AUTO_RET (BIT(20)) -#define SPI_INLINK_AUTO_RET_M (BIT(20)) -#define SPI_INLINK_AUTO_RET_V 0x1 -#define SPI_INLINK_AUTO_RET_S 20 -/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The address of the first inlink descriptor.*/ -#define SPI_INLINK_ADDR 0x000FFFFF -#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S)) -#define SPI_INLINK_ADDR_V 0xFFFFF -#define SPI_INLINK_ADDR_S 0 - -#define SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C) -/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: spi dma write data status bit.*/ -#define SPI_DMA_TX_EN (BIT(1)) -#define SPI_DMA_TX_EN_M (BIT(1)) -#define SPI_DMA_TX_EN_V 0x1 -#define SPI_DMA_TX_EN_S 1 -/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: spi dma read data status bit.*/ -#define SPI_DMA_RX_EN (BIT(0)) -#define SPI_DMA_RX_EN_M (BIT(0)) -#define SPI_DMA_RX_EN_V 0x1 -#define SPI_DMA_RX_EN_S 0 - -#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x110) -/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The enable bit for sending all the packets to host done.*/ -#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1 -#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 -/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The enable bit for sending a packet to host done.*/ -#define SPI_OUT_EOF_INT_ENA (BIT(7)) -#define SPI_OUT_EOF_INT_ENA_M (BIT(7)) -#define SPI_OUT_EOF_INT_ENA_V 0x1 -#define SPI_OUT_EOF_INT_ENA_S 7 -/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The enable bit for completing usage of a outlink descriptor .*/ -#define SPI_OUT_DONE_INT_ENA (BIT(6)) -#define SPI_OUT_DONE_INT_ENA_M (BIT(6)) -#define SPI_OUT_DONE_INT_ENA_V 0x1 -#define SPI_OUT_DONE_INT_ENA_S 6 -/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The enable bit for completing receiving all the packets from host.*/ -#define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) -#define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5)) -#define SPI_IN_SUC_EOF_INT_ENA_V 0x1 -#define SPI_IN_SUC_EOF_INT_ENA_S 5 -/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The enable bit for receiving error.*/ -#define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) -#define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4)) -#define SPI_IN_ERR_EOF_INT_ENA_V 0x1 -#define SPI_IN_ERR_EOF_INT_ENA_S 4 -/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for completing usage of a inlink descriptor.*/ -#define SPI_IN_DONE_INT_ENA (BIT(3)) -#define SPI_IN_DONE_INT_ENA_M (BIT(3)) -#define SPI_IN_DONE_INT_ENA_V 0x1 -#define SPI_IN_DONE_INT_ENA_S 3 -/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for inlink descriptor error.*/ -#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1 -#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 -/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for outlink descriptor error.*/ -#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 -#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 -/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for lack of enough inlink descriptors.*/ -#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 -#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 - -#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x114) -/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw bit for sending all the packets to host done.*/ -#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1 -#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 -/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw bit for sending a packet to host done.*/ -#define SPI_OUT_EOF_INT_RAW (BIT(7)) -#define SPI_OUT_EOF_INT_RAW_M (BIT(7)) -#define SPI_OUT_EOF_INT_RAW_V 0x1 -#define SPI_OUT_EOF_INT_RAW_S 7 -/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw bit for completing usage of a outlink descriptor.*/ -#define SPI_OUT_DONE_INT_RAW (BIT(6)) -#define SPI_OUT_DONE_INT_RAW_M (BIT(6)) -#define SPI_OUT_DONE_INT_RAW_V 0x1 -#define SPI_OUT_DONE_INT_RAW_S 6 -/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw bit for completing receiving all the packets from host.*/ -#define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) -#define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5)) -#define SPI_IN_SUC_EOF_INT_RAW_V 0x1 -#define SPI_IN_SUC_EOF_INT_RAW_S 5 -/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit for receiving error.*/ -#define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) -#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4)) -#define SPI_IN_ERR_EOF_INT_RAW_V 0x1 -#define SPI_IN_ERR_EOF_INT_RAW_S 4 -/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw bit for completing usage of a inlink descriptor.*/ -#define SPI_IN_DONE_INT_RAW (BIT(3)) -#define SPI_IN_DONE_INT_RAW_M (BIT(3)) -#define SPI_IN_DONE_INT_RAW_V 0x1 -#define SPI_IN_DONE_INT_RAW_S 3 -/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw bit for inlink descriptor error.*/ -#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1 -#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 -/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit for outlink descriptor error.*/ -#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 -#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 -/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit for lack of enough inlink descriptors.*/ -#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 -#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 - -#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118) -/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The status bit for sending all the packets to host done.*/ -#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1 -#define SPI_OUT_TOTAL_EOF_INT_ST_S 8 -/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The status bit for sending a packet to host done.*/ -#define SPI_OUT_EOF_INT_ST (BIT(7)) -#define SPI_OUT_EOF_INT_ST_M (BIT(7)) -#define SPI_OUT_EOF_INT_ST_V 0x1 -#define SPI_OUT_EOF_INT_ST_S 7 -/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The status bit for completing usage of a outlink descriptor.*/ -#define SPI_OUT_DONE_INT_ST (BIT(6)) -#define SPI_OUT_DONE_INT_ST_M (BIT(6)) -#define SPI_OUT_DONE_INT_ST_V 0x1 -#define SPI_OUT_DONE_INT_ST_S 6 -/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The status bit for completing receiving all the packets from host.*/ -#define SPI_IN_SUC_EOF_INT_ST (BIT(5)) -#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5)) -#define SPI_IN_SUC_EOF_INT_ST_V 0x1 -#define SPI_IN_SUC_EOF_INT_ST_S 5 -/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The status bit for receiving error.*/ -#define SPI_IN_ERR_EOF_INT_ST (BIT(4)) -#define SPI_IN_ERR_EOF_INT_ST_M (BIT(4)) -#define SPI_IN_ERR_EOF_INT_ST_V 0x1 -#define SPI_IN_ERR_EOF_INT_ST_S 4 -/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The status bit for completing usage of a inlink descriptor.*/ -#define SPI_IN_DONE_INT_ST (BIT(3)) -#define SPI_IN_DONE_INT_ST_M (BIT(3)) -#define SPI_IN_DONE_INT_ST_V 0x1 -#define SPI_IN_DONE_INT_ST_S 3 -/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The status bit for inlink descriptor error.*/ -#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1 -#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2 -/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status bit for outlink descriptor error.*/ -#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1 -#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 -/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status bit for lack of enough inlink descriptors.*/ -#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1 -#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 - -#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x11C) -/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The clear bit for sending all the packets to host done.*/ -#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1 -#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 -/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The clear bit for sending a packet to host done.*/ -#define SPI_OUT_EOF_INT_CLR (BIT(7)) -#define SPI_OUT_EOF_INT_CLR_M (BIT(7)) -#define SPI_OUT_EOF_INT_CLR_V 0x1 -#define SPI_OUT_EOF_INT_CLR_S 7 -/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The clear bit for completing usage of a outlink descriptor.*/ -#define SPI_OUT_DONE_INT_CLR (BIT(6)) -#define SPI_OUT_DONE_INT_CLR_M (BIT(6)) -#define SPI_OUT_DONE_INT_CLR_V 0x1 -#define SPI_OUT_DONE_INT_CLR_S 6 -/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The clear bit for completing receiving all the packets from host.*/ -#define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) -#define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5)) -#define SPI_IN_SUC_EOF_INT_CLR_V 0x1 -#define SPI_IN_SUC_EOF_INT_CLR_S 5 -/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The clear bit for receiving error.*/ -#define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) -#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4)) -#define SPI_IN_ERR_EOF_INT_CLR_V 0x1 -#define SPI_IN_ERR_EOF_INT_CLR_S 4 -/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The clear bit for completing usage of a inlink descriptor.*/ -#define SPI_IN_DONE_INT_CLR (BIT(3)) -#define SPI_IN_DONE_INT_CLR_M (BIT(3)) -#define SPI_IN_DONE_INT_CLR_V 0x1 -#define SPI_IN_DONE_INT_CLR_S 3 -/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The clear bit for inlink descriptor error.*/ -#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1 -#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 -/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear bit for outlink descriptor error.*/ -#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 -#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 -/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear bit for lack of enough inlink descriptors.*/ -#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 -#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 - -#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x120) -/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The inlink descriptor address when spi dma produce receiving error.*/ -#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF -#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S)) -#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF -#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 - -#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x124) -/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/ -#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF -#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S)) -#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF -#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 - -#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x128) -/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current in descriptor pointer.*/ -#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S)) -#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_S 0 - -#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x12C) -/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of next in descriptor pointer.*/ -#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S)) -#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_BF0_S 0 - -#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130) -/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current in descriptor data buffer pointer.*/ -#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S)) -#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_BF1_S 0 - -#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x134) -/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of buffer relative to the outlink descriptor that produce eof.*/ -#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF -#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S)) -#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF -#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 - -#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x138) -/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The last outlink descriptor address when spi dma produce to_eof.*/ -#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF -#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S)) -#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF -#define SPI_DMA_OUT_EOF_DES_ADDR_S 0 - -#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C) -/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current out descriptor pointer.*/ -#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S)) -#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_S 0 - -#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x140) -/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of next out descriptor pointer.*/ -#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S)) -#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_BF0_S 0 - -#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x144) -/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current out descriptor data buffer pointer.*/ -#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S)) -#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_BF1_S 0 - -#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148) -/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: spi dma read data from memory status.*/ -#define SPI_DMA_OUT_STATUS 0xFFFFFFFF -#define SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S)) -#define SPI_DMA_OUT_STATUS_V 0xFFFFFFFF -#define SPI_DMA_OUT_STATUS_S 0 - -#define SPI_DMA_TSTATUS_REG(i) (REG_SPI_BASE(i) + 0x14C) -/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: spi dma write data to memory status.*/ -#define SPI_DMA_IN_STATUS 0xFFFFFFFF -#define SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S)) -#define SPI_DMA_IN_STATUS_V 0xFFFFFFFF -#define SPI_DMA_IN_STATUS_S 0 - -#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC) -/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */ -/*description: SPI register version.*/ -#define SPI_DATE 0x0FFFFFFF -#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) -#define SPI_DATE_V 0xFFFFFFF -#define SPI_DATE_S 0 - - - - -#endif /*__SPI_REG_H__ */ - - + +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) +/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (BIT(26)) +#define SPI_WR_BIT_ORDER_V 0x1 +#define SPI_WR_BIT_ORDER_S 26 +/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/ +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (BIT(25)) +#define SPI_RD_BIT_ORDER_V 0x1 +#define SPI_RD_BIT_ORDER_S 25 +/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 4 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_QIO (BIT(24)) +#define SPI_FREAD_QIO_M (BIT(24)) +#define SPI_FREAD_QIO_V 0x1 +#define SPI_FREAD_QIO_S 24 +/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 2 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_DIO (BIT(23)) +#define SPI_FREAD_DIO_M (BIT(23)) +#define SPI_FREAD_DIO_V 0x1 +#define SPI_FREAD_DIO_S 23 +/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: two bytes data will be written to status register when it is + set. 1: enable 0: disable.*/ +#define SPI_WRSR_2B (BIT(22)) +#define SPI_WRSR_2B_M (BIT(22)) +#define SPI_WRSR_2B_V 0x1 +#define SPI_WRSR_2B_S 22 +/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/ +#define SPI_WP_REG (BIT(21)) +#define SPI_WP_REG_M (BIT(21)) +#define SPI_WP_REG_V 0x1 +#define SPI_WP_REG_S 21 +/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_QUAD (BIT(20)) +#define SPI_FREAD_QUAD_M (BIT(20)) +#define SPI_FREAD_QUAD_V 0x1 +#define SPI_FREAD_QUAD_S 20 +/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: The Device ID is read out to SPI_RD_STATUS register, this bit + combine with spi_flash_res bit. 1: enable 0: disable.*/ +#define SPI_RESANDRES (BIT(15)) +#define SPI_RESANDRES_M (BIT(15)) +#define SPI_RESANDRES_V 0x1 +#define SPI_RESANDRES_S 15 +/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (BIT(14)) +#define SPI_FREAD_DUAL_V 0x1 +#define SPI_FREAD_DUAL_S 14 +/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout + and spi_fread_dout. 1: enable 0: disable.*/ +#define SPI_FASTRD_MODE (BIT(13)) +#define SPI_FASTRD_MODE_M (BIT(13)) +#define SPI_FASTRD_MODE_V 0x1 +#define SPI_FASTRD_MODE_S 13 +/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ +#define SPI_WAIT_FLASH_IDLE_EN (BIT(12)) +#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12)) +#define SPI_WAIT_FLASH_IDLE_EN_V 0x1 +#define SPI_WAIT_FLASH_IDLE_EN_S 12 +/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI1 enable crc32 when writing encrypted data to flash. + 1: enable 0:disable*/ +#define SPI_TX_CRC_EN (BIT(11)) +#define SPI_TX_CRC_EN_M (BIT(11)) +#define SPI_TX_CRC_EN_V 0x1 +#define SPI_TX_CRC_EN_S 11 +/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: For SPI1 initialize crc32 module before writing encrypted data + to flash. Active low.*/ +#define SPI_FCS_CRC_EN (BIT(10)) +#define SPI_FCS_CRC_EN_M (BIT(10)) +#define SPI_FCS_CRC_EN_V 0x1 +#define SPI_FCS_CRC_EN_S 10 + +#define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC) +/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */ +/*description: SPI cs signal is delayed by spi clock cycles*/ +#define SPI_CS_HOLD_DELAY 0x0000000F +#define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S)) +#define SPI_CS_HOLD_DELAY_V 0xF +#define SPI_CS_HOLD_DELAY_S 28 +/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */ +/*description: Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ +#define SPI_CS_HOLD_DELAY_RES 0x00000FFF +#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S)) +#define SPI_CS_HOLD_DELAY_RES_V 0xFFF +#define SPI_CS_HOLD_DELAY_RES_S 16 + +#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10) +/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */ +/*description: In the slave mode,it is the status for master to read out.*/ +#define SPI_STATUS_EXT 0x000000FF +#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S)) +#define SPI_STATUS_EXT_V 0xFF +#define SPI_STATUS_EXT_S 24 +/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ +/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ +#define SPI_WB_MODE 0x000000FF +#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S)) +#define SPI_WB_MODE_V 0xFF +#define SPI_WB_MODE_S 16 +/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: In the slave mode, it is the status for master to read out.*/ +#define SPI_STATUS 0x0000FFFF +#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S)) +#define SPI_STATUS_V 0xFFFF +#define SPI_STATUS_S 0 + +#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14) +/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: spi_cs signal is delayed by system clock cycles*/ +#define SPI_CS_DELAY_NUM 0x0000000F +#define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S)) +#define SPI_CS_DELAY_NUM_V 0xF +#define SPI_CS_DELAY_NUM_S 28 +/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ +/*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_CS_DELAY_MODE 0x00000003 +#define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S)) +#define SPI_CS_DELAY_MODE_V 0x3 +#define SPI_CS_DELAY_MODE_S 26 +/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */ +/*description: MOSI signals are delayed by system clock cycles*/ +#define SPI_MOSI_DELAY_NUM 0x00000007 +#define SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S)) +#define SPI_MOSI_DELAY_NUM_V 0x7 +#define SPI_MOSI_DELAY_NUM_S 23 +/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_MOSI_DELAY_MODE 0x00000003 +#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S)) +#define SPI_MOSI_DELAY_MODE_V 0x3 +#define SPI_MOSI_DELAY_MODE_S 21 +/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: MISO signals are delayed by system clock cycles*/ +#define SPI_MISO_DELAY_NUM 0x00000007 +#define SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S)) +#define SPI_MISO_DELAY_NUM_V 0x7 +#define SPI_MISO_DELAY_NUM_S 18 +/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_MISO_DELAY_MODE 0x00000003 +#define SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S)) +#define SPI_MISO_DELAY_MODE_V 0x3 +#define SPI_MISO_DELAY_MODE_S 16 +/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: modify spi clock duty ratio when the value is lager than 8, + the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ +#define SPI_CK_OUT_HIGH_MODE 0x0000000F +#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S)) +#define SPI_CK_OUT_HIGH_MODE_V 0xF +#define SPI_CK_OUT_HIGH_MODE_S 12 +/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: modify spi clock duty ratio when the value is lager than 8, + the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ +#define SPI_CK_OUT_LOW_MODE 0x0000000F +#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S)) +#define SPI_CK_OUT_LOW_MODE_V 0xF +#define SPI_CK_OUT_LOW_MODE_S 8 +/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */ +/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ +#define SPI_HOLD_TIME 0x0000000F +#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S)) +#define SPI_HOLD_TIME_V 0xF +#define SPI_HOLD_TIME_S 4 +/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */ +/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined + with spi_cs_setup bit.*/ +#define SPI_SETUP_TIME 0x0000000F +#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S)) +#define SPI_SETUP_TIME_V 0xF +#define SPI_SETUP_TIME_S 0 + +#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18) +/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is + divided from system clock.*/ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_V 0x1 +#define SPI_CLK_EQU_SYSCLK_S 31 +/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ +/*description: In the master mode it is pre-divider of spi_clk.*/ +#define SPI_CLKDIV_PRE 0x00001FFF +#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) +#define SPI_CLKDIV_PRE_V 0x1FFF +#define SPI_CLKDIV_PRE_S 18 +/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ +/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency + is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) +#define SPI_CLKCNT_N_V 0x3F +#define SPI_CLKCNT_N_S 12 +/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ +/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In + the slave mode it must be 0.*/ +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) +#define SPI_CLKCNT_H_V 0x3F +#define SPI_CLKCNT_H_S 6 +/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ +/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave + mode it must be 0.*/ +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) +#define SPI_CLKCNT_L_V 0x3F +#define SPI_CLKCNT_L_S 0 + +#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C) +/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation.*/ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (BIT(31)) +#define SPI_USR_COMMAND_V 0x1 +#define SPI_USR_COMMAND_S 31 +/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation.*/ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (BIT(30)) +#define SPI_USR_ADDR_V 0x1 +#define SPI_USR_ADDR_S 30 +/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation.*/ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (BIT(29)) +#define SPI_USR_DUMMY_V 0x1 +#define SPI_USR_DUMMY_S 29 +/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation.*/ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (BIT(28)) +#define SPI_USR_MISO_V 0x1 +#define SPI_USR_MISO_S 28 +/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation.*/ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (BIT(27)) +#define SPI_USR_MOSI_V 0x1 +#define SPI_USR_MOSI_S 27 +/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable.*/ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_USR_DUMMY_IDLE_V 0x1 +#define SPI_USR_DUMMY_IDLE_S 26 +/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable.*/ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_V 0x1 +#define SPI_USR_MOSI_HIGHPART_S 25 +/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable.*/ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_USR_MISO_HIGHPART_V 0x1 +#define SPI_USR_MISO_HIGHPART_S 24 +/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_PREP_HOLD (BIT(23)) +#define SPI_USR_PREP_HOLD_M (BIT(23)) +#define SPI_USR_PREP_HOLD_V 0x1 +#define SPI_USR_PREP_HOLD_S 23 +/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_CMD_HOLD (BIT(22)) +#define SPI_USR_CMD_HOLD_M (BIT(22)) +#define SPI_USR_CMD_HOLD_V 0x1 +#define SPI_USR_CMD_HOLD_S 22 +/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_ADDR_HOLD (BIT(21)) +#define SPI_USR_ADDR_HOLD_M (BIT(21)) +#define SPI_USR_ADDR_HOLD_V 0x1 +#define SPI_USR_ADDR_HOLD_S 21 +/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DUMMY_HOLD (BIT(20)) +#define SPI_USR_DUMMY_HOLD_M (BIT(20)) +#define SPI_USR_DUMMY_HOLD_V 0x1 +#define SPI_USR_DUMMY_HOLD_S 20 +/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DIN_HOLD (BIT(19)) +#define SPI_USR_DIN_HOLD_M (BIT(19)) +#define SPI_USR_DIN_HOLD_V 0x1 +#define SPI_USR_DIN_HOLD_S 19 +/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DOUT_HOLD (BIT(18)) +#define SPI_USR_DOUT_HOLD_M (BIT(18)) +#define SPI_USR_DOUT_HOLD_V 0x1 +#define SPI_USR_DOUT_HOLD_S 18 +/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: It is combined with hold bits to set the polarity of spi hold + line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ +#define SPI_USR_HOLD_POL (BIT(17)) +#define SPI_USR_HOLD_POL_M (BIT(17)) +#define SPI_USR_HOLD_POL_V 0x1 +#define SPI_USR_HOLD_POL_S 17 +/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set the bit to enable 3-line half duplex communication mosi + and miso signals share the same pin. 1: enable 0: disable.*/ +#define SPI_SIO (BIT(16)) +#define SPI_SIO_M (BIT(16)) +#define SPI_SIO_V 0x1 +#define SPI_SIO_S 16 +/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 4 signals.*/ +#define SPI_FWRITE_QIO (BIT(15)) +#define SPI_FWRITE_QIO_M (BIT(15)) +#define SPI_FWRITE_QIO_V 0x1 +#define SPI_FWRITE_QIO_S 15 +/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 2 signals.*/ +#define SPI_FWRITE_DIO (BIT(14)) +#define SPI_FWRITE_DIO_M (BIT(14)) +#define SPI_FWRITE_DIO_V 0x1 +#define SPI_FWRITE_DIO_S 14 +/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals*/ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (BIT(13)) +#define SPI_FWRITE_QUAD_V 0x1 +#define SPI_FWRITE_QUAD_S 13 +/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals*/ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (BIT(12)) +#define SPI_FWRITE_DUAL_V 0x1 +#define SPI_FWRITE_DUAL_S 12 +/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ +#define SPI_WR_BYTE_ORDER (BIT(11)) +#define SPI_WR_BYTE_ORDER_M (BIT(11)) +#define SPI_WR_BYTE_ORDER_V 0x1 +#define SPI_WR_BYTE_ORDER_S 11 +/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/ +#define SPI_RD_BYTE_ORDER (BIT(10)) +#define SPI_RD_BYTE_ORDER_M (BIT(10)) +#define SPI_RD_BYTE_ORDER_V 0x1 +#define SPI_RD_BYTE_ORDER_S 10 +/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ +#define SPI_CK_OUT_EDGE (BIT(7)) +#define SPI_CK_OUT_EDGE_M (BIT(7)) +#define SPI_CK_OUT_EDGE_V 0x1 +#define SPI_CK_OUT_EDGE_S 7 +/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: In the slave mode the bit is same as spi_ck_out_edge in master + mode. It is combined with spi_miso_delay_mode bits.*/ +#define SPI_CK_I_EDGE (BIT(6)) +#define SPI_CK_I_EDGE_M (BIT(6)) +#define SPI_CK_I_EDGE_V 0x1 +#define SPI_CK_I_EDGE_S 6 +/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.*/ +#define SPI_CS_SETUP (BIT(5)) +#define SPI_CS_SETUP_M (BIT(5)) +#define SPI_CS_SETUP_V 0x1 +#define SPI_CS_SETUP_S 5 +/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.*/ +#define SPI_CS_HOLD (BIT(4)) +#define SPI_CS_HOLD_M (BIT(4)) +#define SPI_CS_HOLD_V 0x1 +#define SPI_CS_HOLD_S 4 +/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (BIT(0)) +#define SPI_DOUTDIN_V 0x1 +#define SPI_DOUTDIN_S 0 + +#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20) +/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/ +#define SPI_USR_ADDR_BITLEN 0x0000003F +#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) +#define SPI_USR_ADDR_BITLEN_V 0x3F +#define SPI_USR_ADDR_BITLEN_S 26 +/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ +/*description: The length in spi_clk cycles of dummy phase. The register value + shall be (cycle_num-1).*/ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) +#define SPI_USR_DUMMY_CYCLELEN_V 0xFF +#define SPI_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x24) +/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/ +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) +#define SPI_USR_COMMAND_BITLEN_V 0xF +#define SPI_USR_COMMAND_BITLEN_S 28 +/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command.*/ +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) +#define SPI_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_USR_COMMAND_VALUE_S 0 + +#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28) +/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/ +#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF +#define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S)) +#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF +#define SPI_USR_MOSI_DBITLEN_S 0 + +#define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x2C) +/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/ +#define SPI_USR_MISO_DBITLEN 0x00FFFFFF +#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S)) +#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF +#define SPI_USR_MISO_DBITLEN_S 0 + +#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30) +/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: In the slave mode this register are the status register for the + master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ +#define SPI_SLV_WR_ST 0xFFFFFFFF +#define SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S)) +#define SPI_SLV_WR_ST_V 0xFFFFFFFF +#define SPI_SLV_WR_ST_S 0 + +#define SPI_PIN_REG(i) (REG_SPI_BASE(i) + 0x34) +/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: spi cs line keep low when the bit is set.*/ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_V 0x1 +#define SPI_CS_KEEP_ACTIVE_S 30 +/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (BIT(29)) +#define SPI_CK_IDLE_EDGE_V 0x1 +#define SPI_CK_IDLE_EDGE_S 29 +/* SPI_MASTER_CK_SEL : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ +/*description: In the master mode spi cs line is enable as spi clk it is combined + with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ +#define SPI_MASTER_CK_SEL 0x00000007 +#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S)) +#define SPI_MASTER_CK_SEL_V 0x07 +#define SPI_MASTER_CK_SEL_S 11 +/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */ +/*description: In the master mode the bits are the polarity of spi cs line + the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ +#define SPI_MASTER_CS_POL 0x00000007 +#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) +#define SPI_MASTER_CS_POL_V 0x7 +#define SPI_MASTER_CS_POL_S 6 +/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: 1: spi clk out disable 0: spi clk out enable*/ +#define SPI_CK_DIS (BIT(5)) +#define SPI_CK_DIS_M (BIT(5)) +#define SPI_CK_DIS_V 0x1 +#define SPI_CK_DIS_S 5 +/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (BIT(2)) +#define SPI_CS2_DIS_V 0x1 +#define SPI_CS2_DIS_S 2 +/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (BIT(1)) +#define SPI_CS1_DIS_V 0x1 +#define SPI_CS1_DIS_S 1 +/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (BIT(0)) +#define SPI_CS0_DIS_V 0x1 +#define SPI_CS0_DIS_S 0 + +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38) +/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Software reset enable, reset the spi clock line cs line and data lines.*/ +#define SPI_SYNC_RESET (BIT(31)) +#define SPI_SYNC_RESET_M (BIT(31)) +#define SPI_SYNC_RESET_V 0x1 +#define SPI_SYNC_RESET_S 31 +/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 1: slave mode 0: master mode.*/ +#define SPI_SLAVE_MODE (BIT(30)) +#define SPI_SLAVE_MODE_M (BIT(30)) +#define SPI_SLAVE_MODE_V 0x1 +#define SPI_SLAVE_MODE_S 30 +/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: write and read buffer enable in the slave mode*/ +#define SPI_SLV_WR_RD_BUF_EN (BIT(29)) +#define SPI_SLV_WR_RD_BUF_EN_M (BIT(29)) +#define SPI_SLV_WR_RD_BUF_EN_V 0x1 +#define SPI_SLV_WR_RD_BUF_EN_S 29 +/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: write and read status enable in the slave mode*/ +#define SPI_SLV_WR_RD_STA_EN (BIT(28)) +#define SPI_SLV_WR_RD_STA_EN_M (BIT(28)) +#define SPI_SLV_WR_RD_STA_EN_V 0x1 +#define SPI_SLV_WR_RD_STA_EN_S 28 +/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode + commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ +#define SPI_SLV_CMD_DEFINE (BIT(27)) +#define SPI_SLV_CMD_DEFINE_M (BIT(27)) +#define SPI_SLV_CMD_DEFINE_V 0x1 +#define SPI_SLV_CMD_DEFINE_S 27 +/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */ +/*description: The operations counter in both the master mode and the slave + mode. 4: read-status*/ +#define SPI_TRANS_CNT 0x0000000F +#define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S)) +#define SPI_TRANS_CNT_V 0xF +#define SPI_TRANS_CNT_S 23 +/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: In the slave mode it is the state of spi state machine.*/ +#define SPI_SLV_LAST_STATE 0x00000007 +#define SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S)) +#define SPI_SLV_LAST_STATE_V 0x7 +#define SPI_SLV_LAST_STATE_S 20 +/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */ +/*description: In the slave mode it is the value of command.*/ +#define SPI_SLV_LAST_COMMAND 0x00000007 +#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) +#define SPI_SLV_LAST_COMMAND_V 0x7 +#define SPI_SLV_LAST_COMMAND_S 17 +/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: In the slave mode this bits used to synchronize the input spi + cs signal and eliminate spi cs jitter.*/ +#define SPI_CS_I_MODE 0x00000003 +#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S)) +#define SPI_CS_I_MODE_V 0x3 +#define SPI_CS_I_MODE_S 10 +/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */ +/*description: Interrupt enable bits for the below 5 sources*/ +#define SPI_INT_EN 0x0000001F +#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S)) +#define SPI_INT_EN_V 0x1F +#define SPI_INT_EN_S 5 +/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of any operation in + both the master mode and the slave mode.*/ +#define SPI_TRANS_DONE (BIT(4)) +#define SPI_TRANS_DONE_M (BIT(4)) +#define SPI_TRANS_DONE_V 0x1 +#define SPI_TRANS_DONE_S 4 +/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of write-status operation + in the slave mode.*/ +#define SPI_SLV_WR_STA_DONE (BIT(3)) +#define SPI_SLV_WR_STA_DONE_M (BIT(3)) +#define SPI_SLV_WR_STA_DONE_V 0x1 +#define SPI_SLV_WR_STA_DONE_S 3 +/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of read-status operation + in the slave mode.*/ +#define SPI_SLV_RD_STA_DONE (BIT(2)) +#define SPI_SLV_RD_STA_DONE_M (BIT(2)) +#define SPI_SLV_RD_STA_DONE_V 0x1 +#define SPI_SLV_RD_STA_DONE_S 2 +/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of write-buffer operation + in the slave mode.*/ +#define SPI_SLV_WR_BUF_DONE (BIT(1)) +#define SPI_SLV_WR_BUF_DONE_M (BIT(1)) +#define SPI_SLV_WR_BUF_DONE_V 0x1 +#define SPI_SLV_WR_BUF_DONE_S 1 +/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of read-buffer operation + in the slave mode.*/ +#define SPI_SLV_RD_BUF_DONE (BIT(0)) +#define SPI_SLV_RD_BUF_DONE_M (BIT(0)) +#define SPI_SLV_RD_BUF_DONE_V 0x1 +#define SPI_SLV_RD_BUF_DONE_S 0 + +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x3C) +/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */ +/*description: In the slave mode it is the length of status bit.*/ +#define SPI_SLV_STATUS_BITLEN 0x0000001F +#define SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S)) +#define SPI_SLV_STATUS_BITLEN_V 0x1F +#define SPI_SLV_STATUS_BITLEN_S 27 +/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: In the slave mode enable fast read status.*/ +#define SPI_SLV_STATUS_FAST_EN (BIT(26)) +#define SPI_SLV_STATUS_FAST_EN_M (BIT(26)) +#define SPI_SLV_STATUS_FAST_EN_V 0x1 +#define SPI_SLV_STATUS_FAST_EN_S 26 +/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read + register of SPI_RD_STATUS.*/ +#define SPI_SLV_STATUS_READBACK (BIT(25)) +#define SPI_SLV_STATUS_READBACK_M (BIT(25)) +#define SPI_SLV_STATUS_READBACK_V 0x1 +#define SPI_SLV_STATUS_READBACK_S 25 +/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ +/*description: In the slave mode it is the address length in bits for read-buffer + operation. The register value shall be (bit_num-1).*/ +#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F +#define SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S)) +#define SPI_SLV_RD_ADDR_BITLEN_V 0x3F +#define SPI_SLV_RD_ADDR_BITLEN_S 10 +/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */ +/*description: In the slave mode it is the address length in bits for write-buffer + operation. The register value shall be (bit_num-1).*/ +#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F +#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S)) +#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F +#define SPI_SLV_WR_ADDR_BITLEN_S 4 +/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for write-status + operations.*/ +#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3)) +#define SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3)) +#define SPI_SLV_WRSTA_DUMMY_EN_V 0x1 +#define SPI_SLV_WRSTA_DUMMY_EN_S 3 +/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for read-status + operations.*/ +#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2)) +#define SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2)) +#define SPI_SLV_RDSTA_DUMMY_EN_V 0x1 +#define SPI_SLV_RDSTA_DUMMY_EN_S 2 +/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for write-buffer + operations.*/ +#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1)) +#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1)) +#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1 +#define SPI_SLV_WRBUF_DUMMY_EN_S 1 +/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for read-buffer + operations.*/ +#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0)) +#define SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0)) +#define SPI_SLV_RDBUF_DUMMY_EN_V 0x1 +#define SPI_SLV_RDBUF_DUMMY_EN_S 0 + +#define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x40) +/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for write-buffer operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S)) +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24 +/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for read-buffer operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S)) +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16 +/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for write-status operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S)) +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8 +/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for read-status operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S)) +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0 + +#define SPI_SLAVE3_REG(i) (REG_SPI_BASE(i) + 0x44) +/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of write-status command.*/ +#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF +#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S)) +#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF +#define SPI_SLV_WRSTA_CMD_VALUE_S 24 +/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of read-status command.*/ +#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF +#define SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S)) +#define SPI_SLV_RDSTA_CMD_VALUE_V 0xFF +#define SPI_SLV_RDSTA_CMD_VALUE_S 16 +/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of write-buffer command.*/ +#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF +#define SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S)) +#define SPI_SLV_WRBUF_CMD_VALUE_V 0xFF +#define SPI_SLV_WRBUF_CMD_VALUE_S 8 +/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of read-buffer command.*/ +#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF +#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S)) +#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF +#define SPI_SLV_RDBUF_CMD_VALUE_S 0 + +#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48) +/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: In the slave mode it is the length in bits for write-buffer operations. + The register value shall be (bit_num-1).*/ +#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF +#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S)) +#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF +#define SPI_SLV_WRBUF_DBITLEN_S 0 + +#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x4C) +/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: In the slave mode it is the length in bits for read-buffer operations. + The register value shall be (bit_num-1).*/ +#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF +#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S)) +#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF +#define SPI_SLV_RDBUF_DBITLEN_S 0 + +#define SPI_CACHE_FCTRL_REG(i) (REG_SPI_BASE(i) + 0x50) +/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 spi1 send suspend command before cache read flash + 1: enable 0:disable.*/ +#define SPI_CACHE_FLASH_PES_EN (BIT(3)) +#define SPI_CACHE_FLASH_PES_EN_M (BIT(3)) +#define SPI_CACHE_FLASH_PES_EN_V 0x1 +#define SPI_CACHE_FLASH_PES_EN_S 3 +/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/ +#define SPI_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_CACHE_FLASH_USR_CMD_S 2 +/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ +#define SPI_CACHE_USR_CMD_4BYTE (BIT(1)) +#define SPI_CACHE_USR_CMD_4BYTE_M (BIT(1)) +#define SPI_CACHE_USR_CMD_4BYTE_V 0x1 +#define SPI_CACHE_USR_CMD_4BYTE_S 1 +/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 Cache access enable 1: enable 0:disable.*/ +#define SPI_CACHE_REQ_EN (BIT(0)) +#define SPI_CACHE_REQ_EN_M (BIT(0)) +#define SPI_CACHE_REQ_EN_V 0x1 +#define SPI_CACHE_REQ_EN_S 0 + +#define SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54) +/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode cache write sram for user define command*/ +#define SPI_CACHE_SRAM_USR_WCMD (BIT(28)) +#define SPI_CACHE_SRAM_USR_WCMD_M (BIT(28)) +#define SPI_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_CACHE_SRAM_USR_WCMD_S 28 +/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of address + phase. The register value shall be (bit_num-1).*/ +#define SPI_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S)) +#define SPI_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_SRAM_ADDR_BITLEN_S 22 +/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of address + phase. The register value shall be (bit_num-1).*/ +#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF +#define SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S)) +#define SPI_SRAM_DUMMY_CYCLELEN_V 0xFF +#define SPI_SRAM_DUMMY_CYCLELEN_S 14 +/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */ +/*description: For SPI0 In the sram mode it is the byte length of spi read sram data.*/ +#define SPI_SRAM_BYTES_LEN 0x000000FF +#define SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S)) +#define SPI_SRAM_BYTES_LEN_V 0xFF +#define SPI_SRAM_BYTES_LEN_S 6 +/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/ +#define SPI_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_CACHE_SRAM_USR_RCMD_S 5 +/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode it is the enable bit of dummy + phase for read operations.*/ +#define SPI_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_USR_RD_SRAM_DUMMY_S 4 +/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode it is the enable bit of dummy + phase for write operations.*/ +#define SPI_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_USR_WR_SRAM_DUMMY_S 3 +/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ +#define SPI_USR_SRAM_QIO (BIT(2)) +#define SPI_USR_SRAM_QIO_M (BIT(2)) +#define SPI_USR_SRAM_QIO_V 0x1 +#define SPI_USR_SRAM_QIO_S 2 +/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ +#define SPI_USR_SRAM_DIO (BIT(1)) +#define SPI_USR_SRAM_DIO_M (BIT(1)) +#define SPI_USR_SRAM_DIO_V 0x1 +#define SPI_USR_SRAM_DIO_S 1 + +#define SPI_SRAM_CMD_REG(i) (REG_SPI_BASE(i) + 0x58) +/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation + will be triggered when the bit is set. The bit will be cleared once the operation done*/ +#define SPI_SRAM_RSTIO (BIT(4)) +#define SPI_SRAM_RSTIO_M (BIT(4)) +#define SPI_SRAM_RSTIO_V 0x1 +#define SPI_SRAM_RSTIO_S 4 +/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will + be send when the bit is set. The bit will be cleared once the operation done.*/ +#define SPI_SRAM_QIO (BIT(1)) +#define SPI_SRAM_QIO_M (BIT(1)) +#define SPI_SRAM_QIO_V 0x1 +#define SPI_SRAM_QIO_S 1 +/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will + be send when the bit is set. The bit will be cleared once the operation done.*/ +#define SPI_SRAM_DIO (BIT(0)) +#define SPI_SRAM_DIO_M (BIT(0)) +#define SPI_SRAM_DIO_V 0x1 +#define SPI_SRAM_DIO_S 0 + +#define SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + 0x5C) +/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the length in bits of + command phase for SRAM. The register value shall be (bit_num-1).*/ +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 +/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the read command value + of command phase for SRAM.*/ +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + 0x60) +/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the in bits of command + phase for SRAM. The register value shall be (bit_num-1).*/ +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 +/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the write command value + of command phase for SRAM.*/ +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_SLV_RD_BIT_REG(i) (REG_SPI_BASE(i) + 0x64) +/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: In the slave mode it is the bit length of read data. The value + is the length - 1.*/ +#define SPI_SLV_RDATA_BIT 0x00FFFFFF +#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S)) +#define SPI_SLV_RDATA_BIT_V 0xFFFFFF +#define SPI_SLV_RDATA_BIT_S 0 + +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x80) +/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 + +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x84) +/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 + +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x88) +/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 + +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x8C) +/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 + +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x90) +/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 + +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x94) +/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 + +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x98) +/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 + +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x9C) +/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 + +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xA0) +/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 + +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xA4) +/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 + +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xA8) +/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 + +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xAC) +/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 + +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xB0) +/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 + +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xB4) +/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 + +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xB8) +/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 + +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xBC) +/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +#define SPI_TX_CRC_REG(i) (REG_SPI_BASE(i) + 0xC0) +/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: For SPI1 the value of crc32 for 256 bits data.*/ +#define SPI_TX_CRC_DATA 0xFFFFFFFF +#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S)) +#define SPI_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_TX_CRC_DATA_S 0 + +#define SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0) +/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: page program delay enable.*/ +#define SPI_T_PP_ENA (BIT(31)) +#define SPI_T_PP_ENA_M (BIT(31)) +#define SPI_T_PP_ENA_V 0x1 +#define SPI_T_PP_ENA_S 31 +/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */ +/*description: page program delay time shift .*/ +#define SPI_T_PP_SHIFT 0x0000000F +#define SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S)) +#define SPI_T_PP_SHIFT_V 0xF +#define SPI_T_PP_SHIFT_S 16 +/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */ +/*description: page program delay time by system clock.*/ +#define SPI_T_PP_TIME 0x00000FFF +#define SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S)) +#define SPI_T_PP_TIME_V 0xFFF +#define SPI_T_PP_TIME_S 0 + +#define SPI_EXT1_REG(i) (REG_SPI_BASE(i) + 0xF4) +/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: erase flash delay enable.*/ +#define SPI_T_ERASE_ENA (BIT(31)) +#define SPI_T_ERASE_ENA_M (BIT(31)) +#define SPI_T_ERASE_ENA_V 0x1 +#define SPI_T_ERASE_ENA_S 31 +/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */ +/*description: erase flash delay time shift.*/ +#define SPI_T_ERASE_SHIFT 0x0000000F +#define SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S)) +#define SPI_T_ERASE_SHIFT_V 0xF +#define SPI_T_ERASE_SHIFT_S 16 +/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */ +/*description: erase flash delay time by system clock.*/ +#define SPI_T_ERASE_TIME 0x00000FFF +#define SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S)) +#define SPI_T_ERASE_TIME_V 0xFFF +#define SPI_T_ERASE_TIME_S 0 + +#define SPI_EXT2_REG(i) (REG_SPI_BASE(i) + 0xF8) +/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The status of spi state machine .*/ +#define SPI_ST 0x00000007 +#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S)) +#define SPI_ST_V 0x7 +#define SPI_ST_S 0 + +#define SPI_EXT3_REG(i) (REG_SPI_BASE(i) + 0xFC) +/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: This register is for two SPI masters to share the same cs clock + and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/ +#define SPI_INT_HOLD_ENA 0x00000003 +#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S)) +#define SPI_INT_HOLD_ENA_V 0x3 +#define SPI_INT_HOLD_ENA_S 0 + +#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x100) +/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: spi dma continue tx/rx data.*/ +#define SPI_DMA_CONTINUE (BIT(16)) +#define SPI_DMA_CONTINUE_M (BIT(16)) +#define SPI_DMA_CONTINUE_V 0x1 +#define SPI_DMA_CONTINUE_S 16 +/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: spi dma write data stop when in continue tx/rx mode.*/ +#define SPI_DMA_TX_STOP (BIT(15)) +#define SPI_DMA_TX_STOP_M (BIT(15)) +#define SPI_DMA_TX_STOP_V 0x1 +#define SPI_DMA_TX_STOP_S 15 +/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: spi dma read data stop when in continue tx/rx mode.*/ +#define SPI_DMA_RX_STOP (BIT(14)) +#define SPI_DMA_RX_STOP_M (BIT(14)) +#define SPI_DMA_RX_STOP_V 0x1 +#define SPI_DMA_RX_STOP_S 14 +/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: spi dma read data from memory in burst mode.*/ +#define SPI_OUT_DATA_BURST_EN (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_M (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_V 0x1 +#define SPI_OUT_DATA_BURST_EN_S 12 +/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: read descriptor use burst mode when write data to memory.*/ +#define SPI_INDSCR_BURST_EN (BIT(11)) +#define SPI_INDSCR_BURST_EN_M (BIT(11)) +#define SPI_INDSCR_BURST_EN_V 0x1 +#define SPI_INDSCR_BURST_EN_S 11 +/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: read descriptor use burst mode when read data for memory.*/ +#define SPI_OUTDSCR_BURST_EN (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_M (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_V 0x1 +#define SPI_OUTDSCR_BURST_EN_S 10 +/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: out eof flag generation mode . 1: when dma pop all data from + fifo 0:when ahb push all data to fifo.*/ +#define SPI_OUT_EOF_MODE (BIT(9)) +#define SPI_OUT_EOF_MODE_M (BIT(9)) +#define SPI_OUT_EOF_MODE_V 0x1 +#define SPI_OUT_EOF_MODE_S 9 +/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: when the link is empty jump to next automatically.*/ +#define SPI_OUT_AUTO_WRBACK (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_M (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_V 0x1 +#define SPI_OUT_AUTO_WRBACK_S 8 +/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set bit to test out link.*/ +#define SPI_OUT_LOOP_TEST (BIT(7)) +#define SPI_OUT_LOOP_TEST_M (BIT(7)) +#define SPI_OUT_LOOP_TEST_V 0x1 +#define SPI_OUT_LOOP_TEST_S 7 +/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set bit to test in link.*/ +#define SPI_IN_LOOP_TEST (BIT(6)) +#define SPI_IN_LOOP_TEST_M (BIT(6)) +#define SPI_IN_LOOP_TEST_V 0x1 +#define SPI_IN_LOOP_TEST_S 6 +/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: reset spi dma ahb master.*/ +#define SPI_AHBM_RST (BIT(5)) +#define SPI_AHBM_RST_M (BIT(5)) +#define SPI_AHBM_RST_V 0x1 +#define SPI_AHBM_RST_S 5 +/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: reset spi dma ahb master fifo pointer.*/ +#define SPI_AHBM_FIFO_RST (BIT(4)) +#define SPI_AHBM_FIFO_RST_M (BIT(4)) +#define SPI_AHBM_FIFO_RST_V 0x1 +#define SPI_AHBM_FIFO_RST_S 4 +/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/ +#define SPI_OUT_RST (BIT(3)) +#define SPI_OUT_RST_M (BIT(3)) +#define SPI_OUT_RST_V 0x1 +#define SPI_OUT_RST_S 3 +/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/ +#define SPI_IN_RST (BIT(2)) +#define SPI_IN_RST_M (BIT(2)) +#define SPI_IN_RST_V 0x1 +#define SPI_IN_RST_S 2 + +#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x104) +/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set the bit to mount on new outlink descriptors.*/ +#define SPI_OUTLINK_RESTART (BIT(30)) +#define SPI_OUTLINK_RESTART_M (BIT(30)) +#define SPI_OUTLINK_RESTART_V 0x1 +#define SPI_OUTLINK_RESTART_S 30 +/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set the bit to start to use outlink descriptor.*/ +#define SPI_OUTLINK_START (BIT(29)) +#define SPI_OUTLINK_START_M (BIT(29)) +#define SPI_OUTLINK_START_V 0x1 +#define SPI_OUTLINK_START_S 29 +/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set the bit to stop to use outlink descriptor.*/ +#define SPI_OUTLINK_STOP (BIT(28)) +#define SPI_OUTLINK_STOP_M (BIT(28)) +#define SPI_OUTLINK_STOP_V 0x1 +#define SPI_OUTLINK_STOP_S 28 +/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The address of the first outlink descriptor.*/ +#define SPI_OUTLINK_ADDR 0x000FFFFF +#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S)) +#define SPI_OUTLINK_ADDR_V 0xFFFFF +#define SPI_OUTLINK_ADDR_S 0 + +#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x108) +/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set the bit to mount on new inlink descriptors.*/ +#define SPI_INLINK_RESTART (BIT(30)) +#define SPI_INLINK_RESTART_M (BIT(30)) +#define SPI_INLINK_RESTART_V 0x1 +#define SPI_INLINK_RESTART_S 30 +/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set the bit to start to use inlink descriptor.*/ +#define SPI_INLINK_START (BIT(29)) +#define SPI_INLINK_START_M (BIT(29)) +#define SPI_INLINK_START_V 0x1 +#define SPI_INLINK_START_S 29 +/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set the bit to stop to use inlink descriptor.*/ +#define SPI_INLINK_STOP (BIT(28)) +#define SPI_INLINK_STOP_M (BIT(28)) +#define SPI_INLINK_STOP_V 0x1 +#define SPI_INLINK_STOP_S 28 +/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: when the bit is set inlink descriptor returns to the next descriptor + while a packet is wrong*/ +#define SPI_INLINK_AUTO_RET (BIT(20)) +#define SPI_INLINK_AUTO_RET_M (BIT(20)) +#define SPI_INLINK_AUTO_RET_V 0x1 +#define SPI_INLINK_AUTO_RET_S 20 +/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The address of the first inlink descriptor.*/ +#define SPI_INLINK_ADDR 0x000FFFFF +#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S)) +#define SPI_INLINK_ADDR_V 0xFFFFF +#define SPI_INLINK_ADDR_S 0 + +#define SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C) +/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: spi dma write data status bit.*/ +#define SPI_DMA_TX_EN (BIT(1)) +#define SPI_DMA_TX_EN_M (BIT(1)) +#define SPI_DMA_TX_EN_V 0x1 +#define SPI_DMA_TX_EN_S 1 +/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: spi dma read data status bit.*/ +#define SPI_DMA_RX_EN (BIT(0)) +#define SPI_DMA_RX_EN_M (BIT(0)) +#define SPI_DMA_RX_EN_V 0x1 +#define SPI_DMA_RX_EN_S 0 + +#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x110) +/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 +/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_ENA (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_M (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_V 0x1 +#define SPI_OUT_EOF_INT_ENA_S 7 +/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for completing usage of a outlink descriptor .*/ +#define SPI_OUT_DONE_INT_ENA (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_M (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_V 0x1 +#define SPI_OUT_DONE_INT_ENA_S 6 +/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_V 0x1 +#define SPI_IN_SUC_EOF_INT_ENA_S 5 +/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_V 0x1 +#define SPI_IN_ERR_EOF_INT_ENA_S 4 +/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_ENA (BIT(3)) +#define SPI_IN_DONE_INT_ENA_M (BIT(3)) +#define SPI_IN_DONE_INT_ENA_V 0x1 +#define SPI_IN_DONE_INT_ENA_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 + +#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x114) +/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 +/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_RAW (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_M (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_V 0x1 +#define SPI_OUT_EOF_INT_RAW_S 7 +/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_RAW (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_M (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_V 0x1 +#define SPI_OUT_DONE_INT_RAW_S 6 +/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_V 0x1 +#define SPI_IN_SUC_EOF_INT_RAW_S 5 +/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_V 0x1 +#define SPI_IN_ERR_EOF_INT_RAW_S 4 +/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_RAW (BIT(3)) +#define SPI_IN_DONE_INT_RAW_M (BIT(3)) +#define SPI_IN_DONE_INT_RAW_V 0x1 +#define SPI_IN_DONE_INT_RAW_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 + +#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118) +/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The status bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_ST_S 8 +/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The status bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_ST (BIT(7)) +#define SPI_OUT_EOF_INT_ST_M (BIT(7)) +#define SPI_OUT_EOF_INT_ST_V 0x1 +#define SPI_OUT_EOF_INT_ST_S 7 +/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The status bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_ST (BIT(6)) +#define SPI_OUT_DONE_INT_ST_M (BIT(6)) +#define SPI_OUT_DONE_INT_ST_V 0x1 +#define SPI_OUT_DONE_INT_ST_S 6 +/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The status bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_ST (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_V 0x1 +#define SPI_IN_SUC_EOF_INT_ST_S 5 +/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_ST (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_V 0x1 +#define SPI_IN_ERR_EOF_INT_ST_S 4 +/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_ST (BIT(3)) +#define SPI_IN_DONE_INT_ST_M (BIT(3)) +#define SPI_IN_DONE_INT_ST_V 0x1 +#define SPI_IN_DONE_INT_ST_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 + +#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x11C) +/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 +/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_CLR (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_M (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_V 0x1 +#define SPI_OUT_EOF_INT_CLR_S 7 +/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_CLR (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_M (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_V 0x1 +#define SPI_OUT_DONE_INT_CLR_S 6 +/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_V 0x1 +#define SPI_IN_SUC_EOF_INT_CLR_S 5 +/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_V 0x1 +#define SPI_IN_ERR_EOF_INT_CLR_S 4 +/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_CLR (BIT(3)) +#define SPI_IN_DONE_INT_CLR_M (BIT(3)) +#define SPI_IN_DONE_INT_CLR_V 0x1 +#define SPI_IN_DONE_INT_CLR_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 + +#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x120) +/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The inlink descriptor address when spi dma produce receiving error.*/ +#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S)) +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 + +#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x124) +/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/ +#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S)) +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 + +#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x128) +/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in descriptor pointer.*/ +#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S)) +#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_S 0 + +#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x12C) +/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of next in descriptor pointer.*/ +#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S)) +#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_S 0 + +#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130) +/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in descriptor data buffer pointer.*/ +#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S)) +#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_S 0 + +#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x134) +/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of buffer relative to the outlink descriptor that produce eof.*/ +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S)) +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 + +#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x138) +/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The last outlink descriptor address when spi dma produce to_eof.*/ +#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S)) +#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_S 0 + +#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C) +/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out descriptor pointer.*/ +#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S)) +#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_S 0 + +#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x140) +/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of next out descriptor pointer.*/ +#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S)) +#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_S 0 + +#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x144) +/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out descriptor data buffer pointer.*/ +#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S)) +#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_S 0 + +#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148) +/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: spi dma read data from memory status.*/ +#define SPI_DMA_OUT_STATUS 0xFFFFFFFF +#define SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S)) +#define SPI_DMA_OUT_STATUS_V 0xFFFFFFFF +#define SPI_DMA_OUT_STATUS_S 0 + +#define SPI_DMA_TSTATUS_REG(i) (REG_SPI_BASE(i) + 0x14C) +/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: spi dma write data to memory status.*/ +#define SPI_DMA_IN_STATUS 0xFFFFFFFF +#define SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S)) +#define SPI_DMA_IN_STATUS_V 0xFFFFFFFF +#define SPI_DMA_IN_STATUS_S 0 + +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC) +/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */ +/*description: SPI register version.*/ +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) +#define SPI_DATE_V 0xFFFFFFF +#define SPI_DATE_S 0 + + + + +#endif /*__SPI_REG_H__ */ + + diff --git a/tools/sdk/include/esp32/soc/spi_struct.h b/tools/sdk/include/soc/soc/spi_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/spi_struct.h rename to tools/sdk/include/soc/soc/spi_struct.h diff --git a/tools/sdk/include/esp32/soc/syscon_reg.h b/tools/sdk/include/soc/soc/syscon_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/syscon_reg.h rename to tools/sdk/include/soc/soc/syscon_reg.h diff --git a/tools/sdk/include/esp32/soc/syscon_struct.h b/tools/sdk/include/soc/soc/syscon_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/syscon_struct.h rename to tools/sdk/include/soc/soc/syscon_struct.h diff --git a/tools/sdk/include/esp32/soc/timer_group_reg.h b/tools/sdk/include/soc/soc/timer_group_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/timer_group_reg.h rename to tools/sdk/include/soc/soc/timer_group_reg.h diff --git a/tools/sdk/include/esp32/soc/timer_group_struct.h b/tools/sdk/include/soc/soc/timer_group_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/timer_group_struct.h rename to tools/sdk/include/soc/soc/timer_group_struct.h diff --git a/tools/sdk/include/esp32/soc/uart_reg.h b/tools/sdk/include/soc/soc/uart_reg.h similarity index 97% rename from tools/sdk/include/esp32/soc/uart_reg.h rename to tools/sdk/include/soc/soc/uart_reg.h index 8cac4bb8..df614a88 100644 --- a/tools/sdk/include/esp32/soc/uart_reg.h +++ b/tools/sdk/include/soc/soc/uart_reg.h @@ -1,1167 +1,1167 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef __UART_REG_H__ -#define __UART_REG_H__ - - -#include "soc.h" - -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) ) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) ) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) - -/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: This register stores one byte data read by rx fifo.*/ -#define UART_RXFIFO_RD_BYTE 0x000000FF -#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) -#define UART_RXFIFO_RD_BYTE_V 0xFF -#define UART_RXFIFO_RD_BYTE_S 0 - -#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) -/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the configured at_cmd chars.*/ -#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 -/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when rs485 detects - the clash between transmitter and receiver.*/ -#define UART_RS485_CLASH_INT_RAW (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_V 0x1 -#define UART_RS485_CLASH_INT_RAW_S 17 -/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when rs485 detects - the data frame error.*/ -#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 -#define UART_RS485_FRM_ERR_INT_RAW_S 16 -/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/ -#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 -#define UART_RS485_PARITY_ERR_INT_RAW_S 15 -/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when transmitter has - send all the data in fifo.*/ -#define UART_TX_DONE_INT_RAW (BIT(14)) -#define UART_TX_DONE_INT_RAW_M (BIT(14)) -#define UART_TX_DONE_INT_RAW_V 0x1 -#define UART_TX_DONE_INT_RAW_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when transmitter has - kept the shortest duration after the last data has been send.*/ -#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 -/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when transmitter completes - sendding 0 after all the datas in transmitter's fifo are send.*/ -#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_V 0x1 -#define UART_TX_BRK_DONE_INT_RAW_S 12 -/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/ -#define UART_GLITCH_DET_INT_RAW (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_V 0x1 -#define UART_GLITCH_DET_INT_RAW_S 11 -/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - xon char with uart_sw_flow_con_en is set to 1.*/ -#define UART_SW_XOFF_INT_RAW (BIT(10)) -#define UART_SW_XOFF_INT_RAW_M (BIT(10)) -#define UART_SW_XOFF_INT_RAW_V 0x1 -#define UART_SW_XOFF_INT_RAW_S 10 -/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - xoff char with uart_sw_flow_con_en is set to 1.*/ -#define UART_SW_XON_INT_RAW (BIT(9)) -#define UART_SW_XON_INT_RAW_M (BIT(9)) -#define UART_SW_XON_INT_RAW_V 0x1 -#define UART_SW_XON_INT_RAW_S 9 -/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver takes - more time than rx_tout_thrhd to receive a byte.*/ -#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 -#define UART_RXFIFO_TOUT_INT_RAW_S 8 -/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the 0 after the stop bit.*/ -#define UART_BRK_DET_INT_RAW (BIT(7)) -#define UART_BRK_DET_INT_RAW_M (BIT(7)) -#define UART_BRK_DET_INT_RAW_V 0x1 -#define UART_BRK_DET_INT_RAW_S 7 -/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the edge change of ctsn signal.*/ -#define UART_CTS_CHG_INT_RAW (BIT(6)) -#define UART_CTS_CHG_INT_RAW_M (BIT(6)) -#define UART_CTS_CHG_INT_RAW_V 0x1 -#define UART_CTS_CHG_INT_RAW_S 6 -/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the edge change of dsrn signal.*/ -#define UART_DSR_CHG_INT_RAW (BIT(5)) -#define UART_DSR_CHG_INT_RAW_M (BIT(5)) -#define UART_DSR_CHG_INT_RAW_V 0x1 -#define UART_DSR_CHG_INT_RAW_S 5 -/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - more data than the fifo can store.*/ -#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_V 0x1 -#define UART_RXFIFO_OVF_INT_RAW_S 4 -/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - data's frame error .*/ -#define UART_FRM_ERR_INT_RAW (BIT(3)) -#define UART_FRM_ERR_INT_RAW_M (BIT(3)) -#define UART_FRM_ERR_INT_RAW_V 0x1 -#define UART_FRM_ERR_INT_RAW_S 3 -/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the parity error of data.*/ -#define UART_PARITY_ERR_INT_RAW (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_V 0x1 -#define UART_PARITY_ERR_INT_RAW_S 2 -/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when the amount of - data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ -#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 -#define UART_TXFIFO_EMPTY_INT_RAW_S 1 -/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ -#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_V 0x1 -#define UART_RXFIFO_FULL_INT_RAW_S 0 - -#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) -/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena - is set to 1.*/ -#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 -/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena - is set to 1.*/ -#define UART_RS485_CLASH_INT_ST (BIT(17)) -#define UART_RS485_CLASH_INT_ST_M (BIT(17)) -#define UART_RS485_CLASH_INT_ST_V 0x1 -#define UART_RS485_CLASH_INT_ST_S 17 -/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena - is set to 1.*/ -#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_V 0x1 -#define UART_RS485_FRM_ERR_INT_ST_S 16 -/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena - is set to 1.*/ -#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 -#define UART_RS485_PARITY_ERR_INT_ST_S 15 -/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ -#define UART_TX_DONE_INT_ST (BIT(14)) -#define UART_TX_DONE_INT_ST_M (BIT(14)) -#define UART_TX_DONE_INT_ST_V 0x1 -#define UART_TX_DONE_INT_ST_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena - is set to 1.*/ -#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 -/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena - is set to 1.*/ -#define UART_TX_BRK_DONE_INT_ST (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_V 0x1 -#define UART_TX_BRK_DONE_INT_ST_S 12 -/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena - is set to 1.*/ -#define UART_GLITCH_DET_INT_ST (BIT(11)) -#define UART_GLITCH_DET_INT_ST_M (BIT(11)) -#define UART_GLITCH_DET_INT_ST_V 0x1 -#define UART_GLITCH_DET_INT_ST_S 11 -/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ -#define UART_SW_XOFF_INT_ST (BIT(10)) -#define UART_SW_XOFF_INT_ST_M (BIT(10)) -#define UART_SW_XOFF_INT_ST_V 0x1 -#define UART_SW_XOFF_INT_ST_S 10 -/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ -#define UART_SW_XON_INT_ST (BIT(9)) -#define UART_SW_XON_INT_ST_M (BIT(9)) -#define UART_SW_XON_INT_ST_V 0x1 -#define UART_SW_XON_INT_ST_S 9 -/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena - is set to 1.*/ -#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_V 0x1 -#define UART_RXFIFO_TOUT_INT_ST_S 8 -/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ -#define UART_BRK_DET_INT_ST (BIT(7)) -#define UART_BRK_DET_INT_ST_M (BIT(7)) -#define UART_BRK_DET_INT_ST_V 0x1 -#define UART_BRK_DET_INT_ST_S 7 -/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ -#define UART_CTS_CHG_INT_ST (BIT(6)) -#define UART_CTS_CHG_INT_ST_M (BIT(6)) -#define UART_CTS_CHG_INT_ST_V 0x1 -#define UART_CTS_CHG_INT_ST_S 6 -/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ -#define UART_DSR_CHG_INT_ST (BIT(5)) -#define UART_DSR_CHG_INT_ST_M (BIT(5)) -#define UART_DSR_CHG_INT_ST_V 0x1 -#define UART_DSR_CHG_INT_ST_S 5 -/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena - is set to 1.*/ -#define UART_RXFIFO_OVF_INT_ST (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_V 0x1 -#define UART_RXFIFO_OVF_INT_ST_S 4 -/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ -#define UART_FRM_ERR_INT_ST (BIT(3)) -#define UART_FRM_ERR_INT_ST_M (BIT(3)) -#define UART_FRM_ERR_INT_ST_V 0x1 -#define UART_FRM_ERR_INT_ST_S 3 -/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena - is set to 1.*/ -#define UART_PARITY_ERR_INT_ST (BIT(2)) -#define UART_PARITY_ERR_INT_ST_M (BIT(2)) -#define UART_PARITY_ERR_INT_ST_V 0x1 -#define UART_PARITY_ERR_INT_ST_S 2 -/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena - is set to 1.*/ -#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 -#define UART_TXFIFO_EMPTY_INT_ST_S 1 -/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena - is set to 1.*/ -#define UART_RXFIFO_FULL_INT_ST (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_V 0x1 -#define UART_RXFIFO_FULL_INT_ST_S 0 - -#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) -/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This is the enable bit for at_cmd_char_det_int_st register.*/ -#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 -/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This is the enable bit for rs485_clash_int_st register.*/ -#define UART_RS485_CLASH_INT_ENA (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_V 0x1 -#define UART_RS485_CLASH_INT_ENA_S 17 -/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This is the enable bit for rs485_parity_err_int_st register.*/ -#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 -#define UART_RS485_FRM_ERR_INT_ENA_S 16 -/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for rs485_parity_err_int_st register.*/ -#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 -#define UART_RS485_PARITY_ERR_INT_ENA_S 15 -/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for tx_done_int_st register.*/ -#define UART_TX_DONE_INT_ENA (BIT(14)) -#define UART_TX_DONE_INT_ENA_M (BIT(14)) -#define UART_TX_DONE_INT_ENA_V 0x1 -#define UART_TX_DONE_INT_ENA_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/ -#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 -/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This is the enable bit for tx_brk_done_int_st register.*/ -#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_V 0x1 -#define UART_TX_BRK_DONE_INT_ENA_S 12 -/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This is the enable bit for glitch_det_int_st register.*/ -#define UART_GLITCH_DET_INT_ENA (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_V 0x1 -#define UART_GLITCH_DET_INT_ENA_S 11 -/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This is the enable bit for sw_xoff_int_st register.*/ -#define UART_SW_XOFF_INT_ENA (BIT(10)) -#define UART_SW_XOFF_INT_ENA_M (BIT(10)) -#define UART_SW_XOFF_INT_ENA_V 0x1 -#define UART_SW_XOFF_INT_ENA_S 10 -/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This is the enable bit for sw_xon_int_st register.*/ -#define UART_SW_XON_INT_ENA (BIT(9)) -#define UART_SW_XON_INT_ENA_M (BIT(9)) -#define UART_SW_XON_INT_ENA_V 0x1 -#define UART_SW_XON_INT_ENA_S 9 -/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_tout_int_st register.*/ -#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 -#define UART_RXFIFO_TOUT_INT_ENA_S 8 -/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the enable bit for brk_det_int_st register.*/ -#define UART_BRK_DET_INT_ENA (BIT(7)) -#define UART_BRK_DET_INT_ENA_M (BIT(7)) -#define UART_BRK_DET_INT_ENA_V 0x1 -#define UART_BRK_DET_INT_ENA_S 7 -/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the enable bit for cts_chg_int_st register.*/ -#define UART_CTS_CHG_INT_ENA (BIT(6)) -#define UART_CTS_CHG_INT_ENA_M (BIT(6)) -#define UART_CTS_CHG_INT_ENA_V 0x1 -#define UART_CTS_CHG_INT_ENA_S 6 -/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the enable bit for dsr_chg_int_st register.*/ -#define UART_DSR_CHG_INT_ENA (BIT(5)) -#define UART_DSR_CHG_INT_ENA_M (BIT(5)) -#define UART_DSR_CHG_INT_ENA_V 0x1 -#define UART_DSR_CHG_INT_ENA_S 5 -/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_ovf_int_st register.*/ -#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_V 0x1 -#define UART_RXFIFO_OVF_INT_ENA_S 4 -/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the enable bit for frm_err_int_st register.*/ -#define UART_FRM_ERR_INT_ENA (BIT(3)) -#define UART_FRM_ERR_INT_ENA_M (BIT(3)) -#define UART_FRM_ERR_INT_ENA_V 0x1 -#define UART_FRM_ERR_INT_ENA_S 3 -/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the enable bit for parity_err_int_st register.*/ -#define UART_PARITY_ERR_INT_ENA (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_V 0x1 -#define UART_PARITY_ERR_INT_ENA_S 2 -/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_full_int_st register.*/ -#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 -#define UART_TXFIFO_EMPTY_INT_ENA_S 1 -/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_full_int_st register.*/ -#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_V 0x1 -#define UART_RXFIFO_FULL_INT_ENA_S 0 - -#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) -/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ -#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 -/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/ -#define UART_RS485_CLASH_INT_CLR (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_V 0x1 -#define UART_RS485_CLASH_INT_CLR_S 17 -/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ -#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 -#define UART_RS485_FRM_ERR_INT_CLR_S 16 -/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ -#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 -#define UART_RS485_PARITY_ERR_INT_CLR_S 15 -/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_done_int_raw interrupt.*/ -#define UART_TX_DONE_INT_CLR (BIT(14)) -#define UART_TX_DONE_INT_CLR_M (BIT(14)) -#define UART_TX_DONE_INT_CLR_V 0x1 -#define UART_TX_DONE_INT_CLR_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ -#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 -/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/ -#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_V 0x1 -#define UART_TX_BRK_DONE_INT_CLR_S 12 -/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/ -#define UART_GLITCH_DET_INT_CLR (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_V 0x1 -#define UART_GLITCH_DET_INT_CLR_S 11 -/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ -#define UART_SW_XOFF_INT_CLR (BIT(10)) -#define UART_SW_XOFF_INT_CLR_M (BIT(10)) -#define UART_SW_XOFF_INT_CLR_V 0x1 -#define UART_SW_XOFF_INT_CLR_S 10 -/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ -#define UART_SW_XON_INT_CLR (BIT(9)) -#define UART_SW_XON_INT_CLR_M (BIT(9)) -#define UART_SW_XON_INT_CLR_V 0x1 -#define UART_SW_XON_INT_CLR_S 9 -/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ -#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 -#define UART_RXFIFO_TOUT_INT_CLR_S 8 -/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the brk_det_int_raw interrupt.*/ -#define UART_BRK_DET_INT_CLR (BIT(7)) -#define UART_BRK_DET_INT_CLR_M (BIT(7)) -#define UART_BRK_DET_INT_CLR_V 0x1 -#define UART_BRK_DET_INT_CLR_S 7 -/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/ -#define UART_CTS_CHG_INT_CLR (BIT(6)) -#define UART_CTS_CHG_INT_CLR_M (BIT(6)) -#define UART_CTS_CHG_INT_CLR_V 0x1 -#define UART_CTS_CHG_INT_CLR_S 6 -/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/ -#define UART_DSR_CHG_INT_CLR (BIT(5)) -#define UART_DSR_CHG_INT_CLR_M (BIT(5)) -#define UART_DSR_CHG_INT_CLR_V 0x1 -#define UART_DSR_CHG_INT_CLR_S 5 -/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ -#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_V 0x1 -#define UART_RXFIFO_OVF_INT_CLR_S 4 -/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear frm_err_int_raw interrupt.*/ -#define UART_FRM_ERR_INT_CLR (BIT(3)) -#define UART_FRM_ERR_INT_CLR_M (BIT(3)) -#define UART_FRM_ERR_INT_CLR_V 0x1 -#define UART_FRM_ERR_INT_CLR_S 3 -/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear parity_err_int_raw interrupt.*/ -#define UART_PARITY_ERR_INT_CLR (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_V 0x1 -#define UART_PARITY_ERR_INT_CLR_S 2 -/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/ -#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 -#define UART_TXFIFO_EMPTY_INT_CLR_S 1 -/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/ -#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_V 0x1 -#define UART_RXFIFO_FULL_INT_CLR_S 0 - -#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) -/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: The register value is the decimal part of the frequency divider's factor.*/ -#define UART_CLKDIV_FRAG 0x0000000F -#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) -#define UART_CLKDIV_FRAG_V 0xF -#define UART_CLKDIV_FRAG_S 20 -/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */ -/*description: The register value is the integer part of the frequency divider's factor.*/ -#define UART_CLKDIV 0x000FFFFF -#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) -#define UART_CLKDIV_V 0xFFFFF -#define UART_CLKDIV_S 0 - -#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) -/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */ -/*description: when input pulse width is lower then this value igore this pulse.this - register is used in autobaud detect process.*/ -#define UART_GLITCH_FILT 0x000000FF -#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) -#define UART_GLITCH_FILT_V 0xFF -#define UART_GLITCH_FILT_S 8 -/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the enable bit for detecting baudrate.*/ -#define UART_AUTOBAUD_EN (BIT(0)) -#define UART_AUTOBAUD_EN_M (BIT(0)) -#define UART_AUTOBAUD_EN_V 0x1 -#define UART_AUTOBAUD_EN_S 0 - -#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) -/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */ -/*description: This register represent the level value of the internal uart rxd signal.*/ -#define UART_TXD (BIT(31)) -#define UART_TXD_M (BIT(31)) -#define UART_TXD_V 0x1 -#define UART_TXD_S 31 -/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This register represent the level value of the internal uart cts signal.*/ -#define UART_RTSN (BIT(30)) -#define UART_RTSN_M (BIT(30)) -#define UART_RTSN_V 0x1 -#define UART_RTSN_S 30 -/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The register represent the level value of the internal uart dsr signal.*/ -#define UART_DTRN (BIT(29)) -#define UART_DTRN_M (BIT(29)) -#define UART_DTRN_V 0x1 -#define UART_DTRN_S 29 -/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */ -/*description: This register stores the value of transmitter's finite state - machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ -#define UART_ST_UTX_OUT 0x0000000F -#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) -#define UART_ST_UTX_OUT_V 0xF -#define UART_ST_UTX_OUT_S 24 -/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ -/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in - transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ -#define UART_TXFIFO_CNT 0x000000FF -#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) -#define UART_TXFIFO_CNT_V 0xFF -#define UART_TXFIFO_CNT_S 16 -/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This register stores the level value of the internal uart rxd signal.*/ -#define UART_RXD (BIT(15)) -#define UART_RXD_M (BIT(15)) -#define UART_RXD_V 0x1 -#define UART_RXD_S 15 -/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This register stores the level value of the internal uart cts signal.*/ -#define UART_CTSN (BIT(14)) -#define UART_CTSN_M (BIT(14)) -#define UART_CTSN_V 0x1 -#define UART_CTSN_S 14 -/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This register stores the level value of the internal uart dsr signal.*/ -#define UART_DSRN (BIT(13)) -#define UART_DSRN_M (BIT(13)) -#define UART_DSRN_V 0x1 -#define UART_DSRN_S 13 -/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */ -/*description: This register stores the value of receiver's finite state machine. - 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ -#define UART_ST_URX_OUT 0x0000000F -#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) -#define UART_ST_URX_OUT_V 0xF -#define UART_ST_URX_OUT_S 8 -/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in - receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ -#define UART_RXFIFO_CNT 0x000000FF -#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) -#define UART_RXFIFO_CNT_V 0xFF -#define UART_RXFIFO_CNT_S 0 - -#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) -/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */ -/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/ -#define UART_TICK_REF_ALWAYS_ON (BIT(27)) -#define UART_TICK_REF_ALWAYS_ON_M (BIT(27)) -#define UART_TICK_REF_ALWAYS_ON_V 0x1 -#define UART_TICK_REF_ALWAYS_ON_S 27 -/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1.receiver stops storing data int fifo when data is wrong. - 0.receiver stores the data even if the received data is wrong.*/ -#define UART_ERR_WR_MASK (BIT(26)) -#define UART_ERR_WR_MASK_M (BIT(26)) -#define UART_ERR_WR_MASK_V 0x1 -#define UART_ERR_WR_MASK_S 26 -/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: 1.force clock on for registers.support clock only when write registers*/ -#define UART_CLK_EN (BIT(25)) -#define UART_CLK_EN_M (BIT(25)) -#define UART_CLK_EN_V 0x1 -#define UART_CLK_EN_S 25 -/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart dtr signal.*/ -#define UART_DTR_INV (BIT(24)) -#define UART_DTR_INV_M (BIT(24)) -#define UART_DTR_INV_V 0x1 -#define UART_DTR_INV_S 24 -/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart rts signal.*/ -#define UART_RTS_INV (BIT(23)) -#define UART_RTS_INV_M (BIT(23)) -#define UART_RTS_INV_V 0x1 -#define UART_RTS_INV_S 23 -/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart txd signal.*/ -#define UART_TXD_INV (BIT(22)) -#define UART_TXD_INV_M (BIT(22)) -#define UART_TXD_INV_V 0x1 -#define UART_TXD_INV_S 22 -/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart dsr signal.*/ -#define UART_DSR_INV (BIT(21)) -#define UART_DSR_INV_M (BIT(21)) -#define UART_DSR_INV_V 0x1 -#define UART_DSR_INV_S 21 -/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart cts signal.*/ -#define UART_CTS_INV (BIT(20)) -#define UART_CTS_INV_M (BIT(20)) -#define UART_CTS_INV_V 0x1 -#define UART_CTS_INV_S 20 -/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart rxd signal.*/ -#define UART_RXD_INV (BIT(19)) -#define UART_RXD_INV_M (BIT(19)) -#define UART_RXD_INV_V 0x1 -#define UART_RXD_INV_S 19 -/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: Set this bit to reset uart transmitter's fifo.*/ -#define UART_TXFIFO_RST (BIT(18)) -#define UART_TXFIFO_RST_M (BIT(18)) -#define UART_TXFIFO_RST_V 0x1 -#define UART_TXFIFO_RST_S 18 -/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: Set this bit to reset uart receiver's fifo.*/ -#define UART_RXFIFO_RST (BIT(17)) -#define UART_RXFIFO_RST_M (BIT(17)) -#define UART_RXFIFO_RST_V 0x1 -#define UART_RXFIFO_RST_S 17 -/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: Set this bit to enable irda protocol.*/ -#define UART_IRDA_EN (BIT(16)) -#define UART_IRDA_EN_M (BIT(16)) -#define UART_IRDA_EN_V 0x1 -#define UART_IRDA_EN_S 16 -/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to enable transmitter's flow control function.*/ -#define UART_TX_FLOW_EN (BIT(15)) -#define UART_TX_FLOW_EN_M (BIT(15)) -#define UART_TX_FLOW_EN_V 0x1 -#define UART_TX_FLOW_EN_S 15 -/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to enable uart loopback test mode.*/ -#define UART_LOOPBACK (BIT(14)) -#define UART_LOOPBACK_M (BIT(14)) -#define UART_LOOPBACK_V 0x1 -#define UART_LOOPBACK_S 14 -/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to inverse the level value of irda receiver's level.*/ -#define UART_IRDA_RX_INV (BIT(13)) -#define UART_IRDA_RX_INV_M (BIT(13)) -#define UART_IRDA_RX_INV_V 0x1 -#define UART_IRDA_RX_INV_S 13 -/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to inverse the level value of irda transmitter's level.*/ -#define UART_IRDA_TX_INV (BIT(12)) -#define UART_IRDA_TX_INV_M (BIT(12)) -#define UART_IRDA_TX_INV_V 0x1 -#define UART_IRDA_TX_INV_S 12 -/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit. - 0.set irda transmitter's 11th bit to 0.*/ -#define UART_IRDA_WCTL (BIT(11)) -#define UART_IRDA_WCTL_M (BIT(11)) -#define UART_IRDA_WCTL_V 0x1 -#define UART_IRDA_WCTL_S 11 -/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This is the start enable bit for irda transmitter.*/ -#define UART_IRDA_TX_EN (BIT(10)) -#define UART_IRDA_TX_EN_M (BIT(10)) -#define UART_IRDA_TX_EN_V 0x1 -#define UART_IRDA_TX_EN_S 10 -/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to enable irda loopback mode.*/ -#define UART_IRDA_DPLX (BIT(9)) -#define UART_IRDA_DPLX_M (BIT(9)) -#define UART_IRDA_DPLX_V 0x1 -#define UART_IRDA_DPLX_S 9 -/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to enbale transmitter to send 0 when the process - of sending data is done.*/ -#define UART_TXD_BRK (BIT(8)) -#define UART_TXD_BRK_M (BIT(8)) -#define UART_TXD_BRK_V 0x1 -#define UART_TXD_BRK_S 8 -/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This register is used to configure the software dtr signal which - is used in software flow control..*/ -#define UART_SW_DTR (BIT(7)) -#define UART_SW_DTR_M (BIT(7)) -#define UART_SW_DTR_V 0x1 -#define UART_SW_DTR_S 7 -/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This register is used to configure the software rts signal which - is used in software flow control.*/ -#define UART_SW_RTS (BIT(6)) -#define UART_SW_RTS_M (BIT(6)) -#define UART_SW_RTS_V 0x1 -#define UART_SW_RTS_S 6 -/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ -/*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ -#define UART_STOP_BIT_NUM 0x00000003 -#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) -#define UART_STOP_BIT_NUM_V 0x3 -#define UART_STOP_BIT_NUM_S 4 -/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ -/*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ -#define UART_BIT_NUM 0x00000003 -#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) -#define UART_BIT_NUM_V 0x3 -#define UART_BIT_NUM_S 2 -/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to enable uart parity check.*/ -#define UART_PARITY_EN (BIT(1)) -#define UART_PARITY_EN_M (BIT(1)) -#define UART_PARITY_EN_V 0x1 -#define UART_PARITY_EN_S 1 -/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This register is used to configure the parity check mode. 0:even 1:odd*/ -#define UART_PARITY (BIT(0)) -#define UART_PARITY_M (BIT(0)) -#define UART_PARITY_V 0x1 -#define UART_PARITY_S 0 - -#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) -/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: This is the enble bit for uart receiver's timeout function.*/ -#define UART_RX_TOUT_EN (BIT(31)) -#define UART_RX_TOUT_EN_M (BIT(31)) -#define UART_RX_TOUT_EN_V 0x1 -#define UART_RX_TOUT_EN_S 31 -/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */ -/*description: This register is used to configure the timeout value for uart - receiver receiving a byte.*/ -#define UART_RX_TOUT_THRHD 0x0000007F -#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) -#define UART_RX_TOUT_THRHD_V 0x7F -#define UART_RX_TOUT_THRHD_S 24 -/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This is the flow enable bit for uart receiver. 1:choose software - flow control with configuring sw_rts signal*/ -#define UART_RX_FLOW_EN (BIT(23)) -#define UART_RX_FLOW_EN_M (BIT(23)) -#define UART_RX_FLOW_EN_V 0x1 -#define UART_RX_FLOW_EN_S 23 -/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */ -/*description: when receiver receives more data than its threshold value. - receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ -#define UART_RX_FLOW_THRHD 0x0000007F -#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) -#define UART_RX_FLOW_THRHD_V 0x7F -#define UART_RX_FLOW_THRHD_S 16 -/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */ -/*description: when the data amount in transmitter fifo is less than its threshold - value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ -#define UART_TXFIFO_EMPTY_THRHD 0x0000007F -#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) -#define UART_TXFIFO_EMPTY_THRHD_V 0x7F -#define UART_TXFIFO_EMPTY_THRHD_S 8 -/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */ -/*description: When receiver receives more data than its threshold value.receiver - will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ -#define UART_RXFIFO_FULL_THRHD 0x0000007F -#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) -#define UART_RXFIFO_FULL_THRHD_V 0x7F -#define UART_RXFIFO_FULL_THRHD_S 0 - -#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) -/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ -/*description: This register stores the value of the minimum duration time for - the low level pulse. it is used in baudrate-detect process.*/ -#define UART_LOWPULSE_MIN_CNT 0x000FFFFF -#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) -#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF -#define UART_LOWPULSE_MIN_CNT_S 0 - -#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) -/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ -/*description: This register stores the value of the maxinum duration time - for the high level pulse. it is used in baudrate-detect process.*/ -#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF -#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) -#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF -#define UART_HIGHPULSE_MIN_CNT_S 0 - -#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) -/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register stores the count of rxd edge change. it is used - in baudrate-detect process.*/ -#define UART_RXD_EDGE_CNT 0x000003FF -#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) -#define UART_RXD_EDGE_CNT_V 0x3FF -#define UART_RXD_EDGE_CNT_S 0 - -#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) -/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/ -#define UART_SEND_XOFF (BIT(5)) -#define UART_SEND_XOFF_M (BIT(5)) -#define UART_SEND_XOFF_V 0x1 -#define UART_SEND_XOFF_S 5 -/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/ -#define UART_SEND_XON (BIT(4)) -#define UART_SEND_XON_M (BIT(4)) -#define UART_SEND_XON_V 0x1 -#define UART_SEND_XON_S 4 -/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/ -#define UART_FORCE_XOFF (BIT(3)) -#define UART_FORCE_XOFF_M (BIT(3)) -#define UART_FORCE_XOFF_V 0x1 -#define UART_FORCE_XOFF_S 3 -/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear ctsn to stop the transmitter from sending data.*/ -#define UART_FORCE_XON (BIT(2)) -#define UART_FORCE_XON_M (BIT(2)) -#define UART_FORCE_XON_V 0x1 -#define UART_FORCE_XON_S 2 -/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to remove flow control char from the received data.*/ -#define UART_XONOFF_DEL (BIT(1)) -#define UART_XONOFF_DEL_M (BIT(1)) -#define UART_XONOFF_DEL_V 0x1 -#define UART_XONOFF_DEL_S 1 -/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to enable software flow control. it is used with - register sw_xon or sw_xoff .*/ -#define UART_SW_FLOW_CON_EN (BIT(0)) -#define UART_SW_FLOW_CON_EN_M (BIT(0)) -#define UART_SW_FLOW_CON_EN_V 0x1 -#define UART_SW_FLOW_CON_EN_S 0 - -#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) -/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ -/*description: When the input rxd edge changes more than this register value. - the uart is active from light sleeping mode.*/ -#define UART_ACTIVE_THRESHOLD 0x000003FF -#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) -#define UART_ACTIVE_THRESHOLD_V 0x3FF -#define UART_ACTIVE_THRESHOLD_S 0 - -#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C) -/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */ -/*description: This register stores the xoff flow control char.*/ -#define UART_XOFF_CHAR 0x000000FF -#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) -#define UART_XOFF_CHAR_V 0xFF -#define UART_XOFF_CHAR_S 24 -/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */ -/*description: This register stores the xon flow control char.*/ -#define UART_XON_CHAR 0x000000FF -#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) -#define UART_XON_CHAR_V 0xFF -#define UART_XON_CHAR_S 16 -/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */ -/*description: When the data amount in receiver's fifo is less than this register - value. it will send a xon char with uart_sw_flow_con_en set to 1.*/ -#define UART_XOFF_THRESHOLD 0x000000FF -#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) -#define UART_XOFF_THRESHOLD_V 0xFF -#define UART_XOFF_THRESHOLD_S 8 -/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: when the data amount in receiver's fifo is more than this register - value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/ -#define UART_XON_THRESHOLD 0x000000FF -#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) -#define UART_XON_THRESHOLD_V 0xFF -#define UART_XON_THRESHOLD_S 0 - -#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40) -/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */ -/*description: This register is used to configure the num of 0 send after the - process of sending data is done. it is active when txd_brk is set to 1.*/ -#define UART_TX_BRK_NUM 0x000000FF -#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) -#define UART_TX_BRK_NUM_V 0xFF -#define UART_TX_BRK_NUM_S 20 -/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ -/*description: This register is used to configure the duration time between transfers.*/ -#define UART_TX_IDLE_NUM 0x000003FF -#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) -#define UART_TX_IDLE_NUM_V 0x3FF -#define UART_TX_IDLE_NUM_S 10 -/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ -/*description: when receiver takes more time than this register value to receive - a byte data. it will produce frame end signal for uhci to stop receiving data.*/ -#define UART_RX_IDLE_THRHD 0x000003FF -#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) -#define UART_RX_IDLE_THRHD_V 0x3FF -#define UART_RX_IDLE_THRHD_S 0 - -#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44) -/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ -/*description: This register is used to delay the transmitter's internal data signal.*/ -#define UART_RS485_TX_DLY_NUM 0x0000000F -#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) -#define UART_RS485_TX_DLY_NUM_V 0xF -#define UART_RS485_TX_DLY_NUM_S 6 -/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This register is used to delay the receiver's internal data signal.*/ -#define UART_RS485_RX_DLY_NUM (BIT(5)) -#define UART_RS485_RX_DLY_NUM_M (BIT(5)) -#define UART_RS485_RX_DLY_NUM_V 0x1 -#define UART_RS485_RX_DLY_NUM_S 5 -/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: 1: enable rs485's transmitter to send data when rs485's receiver - is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ -#define UART_RS485RXBY_TX_EN (BIT(4)) -#define UART_RS485RXBY_TX_EN_M (BIT(4)) -#define UART_RS485RXBY_TX_EN_V 0x1 -#define UART_RS485RXBY_TX_EN_S 4 -/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to enable loopback transmitter's output data signal - to receiver's input data signal.*/ -#define UART_RS485TX_RX_EN (BIT(3)) -#define UART_RS485TX_RX_EN_M (BIT(3)) -#define UART_RS485TX_RX_EN_V 0x1 -#define UART_RS485TX_RX_EN_S 3 -/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to delay the stop bit by 1 bit.*/ -#define UART_DL1_EN (BIT(2)) -#define UART_DL1_EN_M (BIT(2)) -#define UART_DL1_EN_V 0x1 -#define UART_DL1_EN_S 2 -/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to delay the stop bit by 1 bit.*/ -#define UART_DL0_EN (BIT(1)) -#define UART_DL0_EN_M (BIT(1)) -#define UART_DL0_EN_V 0x1 -#define UART_DL0_EN_S 1 -/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to choose rs485 mode.*/ -#define UART_RS485_EN (BIT(0)) -#define UART_RS485_EN_M (BIT(0)) -#define UART_RS485_EN_V 0x1 -#define UART_RS485_EN_S 0 - -#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48) -/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ -/*description: This register is used to configure the idle duration time before - the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ -#define UART_PRE_IDLE_NUM 0x00FFFFFF -#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) -#define UART_PRE_IDLE_NUM_V 0xFFFFFF -#define UART_PRE_IDLE_NUM_S 0 - -#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c) -/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ -/*description: This register is used to configure the duration time between - the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/ -#define UART_POST_IDLE_NUM 0x00FFFFFF -#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) -#define UART_POST_IDLE_NUM_V 0xFFFFFF -#define UART_POST_IDLE_NUM_S 0 - -#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50) -/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */ -/*description: This register is used to configure the duration time between - the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/ -#define UART_RX_GAP_TOUT 0x00FFFFFF -#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) -#define UART_RX_GAP_TOUT_V 0xFFFFFF -#define UART_RX_GAP_TOUT_S 0 - -#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54) -/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ -/*description: This register is used to configure the num of continous at_cmd - chars received by receiver.*/ -#define UART_CHAR_NUM 0x000000FF -#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) -#define UART_CHAR_NUM_V 0xFF -#define UART_CHAR_NUM_S 8 -/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ -/*description: This register is used to configure the content of at_cmd char.*/ -#define UART_AT_CMD_CHAR 0x000000FF -#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) -#define UART_AT_CMD_CHAR_V 0xFF -#define UART_AT_CMD_CHAR_S 0 - -#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58) -/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: refer to txfifo_empty_thrhd 's describtion.*/ -#define UART_TX_MEM_EMPTY_THRHD 0x00000007 -#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S)) -#define UART_TX_MEM_EMPTY_THRHD_V 0x7 -#define UART_TX_MEM_EMPTY_THRHD_S 28 -/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ -/*description: refer to the rxfifo_full_thrhd's describtion.*/ -#define UART_RX_MEM_FULL_THRHD 0x00000007 -#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S)) -#define UART_RX_MEM_FULL_THRHD_V 0x7 -#define UART_RX_MEM_FULL_THRHD_S 25 -/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: refer to the uart_xoff_threshold's describtion.*/ -#define UART_XOFF_THRESHOLD_H2 0x00000003 -#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S)) -#define UART_XOFF_THRESHOLD_H2_V 0x3 -#define UART_XOFF_THRESHOLD_H2_S 23 -/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: refer to the uart_xon_threshold's describtion.*/ -#define UART_XON_THRESHOLD_H2 0x00000003 -#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S)) -#define UART_XON_THRESHOLD_H2_V 0x3 -#define UART_XON_THRESHOLD_H2_S 21 -/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: refer to the rx_tout_thrhd's describtion.*/ -#define UART_RX_TOUT_THRHD_H3 0x00000007 -#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S)) -#define UART_RX_TOUT_THRHD_H3_V 0x7 -#define UART_RX_TOUT_THRHD_H3_S 18 -/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ -/*description: refer to the rx_flow_thrhd's describtion.*/ -#define UART_RX_FLOW_THRHD_H3 0x00000007 -#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S)) -#define UART_RX_FLOW_THRHD_H3_V 0x7 -#define UART_RX_FLOW_THRHD_H3_S 15 -/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */ -/*description: This register is used to configure the amount of mem allocated - to transmitter's fifo.the default byte num is 128.*/ -#define UART_TX_SIZE 0x0000000F -#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) -#define UART_TX_SIZE_V 0xF -#define UART_TX_SIZE_S 7 -/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */ -/*description: This register is used to configure the amount of mem allocated - to receiver's fifo. the default byte num is 128.*/ -#define UART_RX_SIZE 0x0000000F -#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) -#define UART_RX_SIZE_V 0xF -#define UART_RX_SIZE_S 3 -/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to power down mem.when reg_mem_pd registers in - the 3 uarts are all set to 1 mem will enter low power mode.*/ -#define UART_MEM_PD (BIT(0)) -#define UART_MEM_PD_M (BIT(0)) -#define UART_MEM_PD_V 0x1 -#define UART_MEM_PD_S 0 - -#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c) -/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: */ -#define UART_MEM_TX_STATUS 0x00FFFFFF -#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S)) -#define UART_MEM_TX_STATUS_V 0xFFFFFF -#define UART_MEM_TX_STATUS_S 0 - -#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) -/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: */ -#define UART_MEM_RX_STATUS 0x00FFFFFF -#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S)) -#define UART_MEM_RX_STATUS_V 0xFFFFFF -#define UART_MEM_RX_STATUS_S 0 - -#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) -/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: refer to the txfifo_cnt's describtion.*/ -#define UART_TX_MEM_CNT 0x00000007 -#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S)) -#define UART_TX_MEM_CNT_V 0x7 -#define UART_TX_MEM_CNT_S 3 -/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: refer to the rxfifo_cnt's describtion.*/ -#define UART_RX_MEM_CNT 0x00000007 -#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S)) -#define UART_RX_MEM_CNT_V 0x7 -#define UART_RX_MEM_CNT_S 0 - -#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68) -/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ -/*description: This register stores the count of rxd posedge edge. it is used - in boudrate-detect process.*/ -#define UART_POSEDGE_MIN_CNT 0x000FFFFF -#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) -#define UART_POSEDGE_MIN_CNT_V 0xFFFFF -#define UART_POSEDGE_MIN_CNT_S 0 - -#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) -/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ -/*description: This register stores the count of rxd negedge edge. it is used - in boudrate-detect process.*/ -#define UART_NEGEDGE_MIN_CNT 0x000FFFFF -#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) -#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF -#define UART_NEGEDGE_MIN_CNT_S 0 - -#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78) -/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */ -/*description: */ -#define UART_DATE 0xFFFFFFFF -#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) -#define UART_DATE_V 0xFFFFFFFF -#define UART_DATE_S 0 - -#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C) -/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ -/*description: */ -#define UART_ID 0xFFFFFFFF -#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) -#define UART_ID_V 0xFFFFFFFF -#define UART_ID_S 0 - - - - -#endif /*__UART_REG_H__ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + + +#include "soc.h" + +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) + +/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: This register stores one byte data read by rx fifo.*/ +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) +#define UART_RXFIFO_RD_BYTE_V 0xFF +#define UART_RXFIFO_RD_BYTE_S 0 + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the configured at_cmd chars.*/ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects + the clash between transmitter and receiver.*/ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_V 0x1 +#define UART_RS485_CLASH_INT_RAW_S 17 +/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects + the data frame error.*/ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has + send all the data in fifo.*/ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (BIT(14)) +#define UART_TX_DONE_INT_RAW_V 0x1 +#define UART_TX_DONE_INT_RAW_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has + kept the shortest duration after the last data has been send.*/ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter completes + sendding 0 after all the datas in transmitter's fifo are send.*/ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_V 0x1 +#define UART_GLITCH_DET_INT_RAW_S 11 +/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + xon char with uart_sw_flow_con_en is set to 1.*/ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (BIT(10)) +#define UART_SW_XOFF_INT_RAW_V 0x1 +#define UART_SW_XOFF_INT_RAW_S 10 +/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + xoff char with uart_sw_flow_con_en is set to 1.*/ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (BIT(9)) +#define UART_SW_XON_INT_RAW_V 0x1 +#define UART_SW_XON_INT_RAW_S 9 +/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver takes + more time than rx_tout_thrhd to receive a byte.*/ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the 0 after the stop bit.*/ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (BIT(7)) +#define UART_BRK_DET_INT_RAW_V 0x1 +#define UART_BRK_DET_INT_RAW_S 7 +/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the edge change of ctsn signal.*/ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (BIT(6)) +#define UART_CTS_CHG_INT_RAW_V 0x1 +#define UART_CTS_CHG_INT_RAW_S 6 +/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the edge change of dsrn signal.*/ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (BIT(5)) +#define UART_DSR_CHG_INT_RAW_V 0x1 +#define UART_DSR_CHG_INT_RAW_S 5 +/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + more data than the fifo can store.*/ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_V 0x1 +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + data's frame error .*/ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (BIT(3)) +#define UART_FRM_ERR_INT_RAW_V 0x1 +#define UART_FRM_ERR_INT_RAW_S 3 +/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the parity error of data.*/ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_V 0x1 +#define UART_PARITY_ERR_INT_RAW_S 2 +/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when the amount of + data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_V 0x1 +#define UART_RXFIFO_FULL_INT_RAW_S 0 + +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena + is set to 1.*/ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena + is set to 1.*/ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (BIT(17)) +#define UART_RS485_CLASH_INT_ST_V 0x1 +#define UART_RS485_CLASH_INT_ST_S 17 +/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena + is set to 1.*/ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_V 0x1 +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena + is set to 1.*/ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (BIT(14)) +#define UART_TX_DONE_INT_ST_V 0x1 +#define UART_TX_DONE_INT_ST_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + is set to 1.*/ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena + is set to 1.*/ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_DONE_INT_ST_S 12 +/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena + is set to 1.*/ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (BIT(11)) +#define UART_GLITCH_DET_INT_ST_V 0x1 +#define UART_GLITCH_DET_INT_ST_S 11 +/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (BIT(10)) +#define UART_SW_XOFF_INT_ST_V 0x1 +#define UART_SW_XOFF_INT_ST_S 10 +/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (BIT(9)) +#define UART_SW_XON_INT_ST_V 0x1 +#define UART_SW_XON_INT_ST_S 9 +/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena + is set to 1.*/ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_V 0x1 +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (BIT(7)) +#define UART_BRK_DET_INT_ST_V 0x1 +#define UART_BRK_DET_INT_ST_S 7 +/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (BIT(6)) +#define UART_CTS_CHG_INT_ST_V 0x1 +#define UART_CTS_CHG_INT_ST_S 6 +/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (BIT(5)) +#define UART_DSR_CHG_INT_ST_V 0x1 +#define UART_DSR_CHG_INT_ST_S 5 +/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena + is set to 1.*/ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_V 0x1 +#define UART_RXFIFO_OVF_INT_ST_S 4 +/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (BIT(3)) +#define UART_FRM_ERR_INT_ST_V 0x1 +#define UART_FRM_ERR_INT_ST_S 3 +/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena + is set to 1.*/ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (BIT(2)) +#define UART_PARITY_ERR_INT_ST_V 0x1 +#define UART_PARITY_ERR_INT_ST_S 2 +/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena + is set to 1.*/ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena + is set to 1.*/ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_V 0x1 +#define UART_RXFIFO_FULL_INT_ST_S 0 + +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) +/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This is the enable bit for at_cmd_char_det_int_st register.*/ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_clash_int_st register.*/ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_V 0x1 +#define UART_RS485_CLASH_INT_ENA_S 17 +/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_parity_err_int_st register.*/ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_parity_err_int_st register.*/ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_done_int_st register.*/ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (BIT(14)) +#define UART_TX_DONE_INT_ENA_V 0x1 +#define UART_TX_DONE_INT_ENA_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_brk_done_int_st register.*/ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This is the enable bit for glitch_det_int_st register.*/ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_V 0x1 +#define UART_GLITCH_DET_INT_ENA_S 11 +/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the enable bit for sw_xoff_int_st register.*/ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (BIT(10)) +#define UART_SW_XOFF_INT_ENA_V 0x1 +#define UART_SW_XOFF_INT_ENA_S 10 +/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This is the enable bit for sw_xon_int_st register.*/ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (BIT(9)) +#define UART_SW_XON_INT_ENA_V 0x1 +#define UART_SW_XON_INT_ENA_S 9 +/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_tout_int_st register.*/ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the enable bit for brk_det_int_st register.*/ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (BIT(7)) +#define UART_BRK_DET_INT_ENA_V 0x1 +#define UART_BRK_DET_INT_ENA_S 7 +/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the enable bit for cts_chg_int_st register.*/ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (BIT(6)) +#define UART_CTS_CHG_INT_ENA_V 0x1 +#define UART_CTS_CHG_INT_ENA_S 6 +/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the enable bit for dsr_chg_int_st register.*/ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (BIT(5)) +#define UART_DSR_CHG_INT_ENA_V 0x1 +#define UART_DSR_CHG_INT_ENA_S 5 +/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_ovf_int_st register.*/ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_V 0x1 +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the enable bit for frm_err_int_st register.*/ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (BIT(3)) +#define UART_FRM_ERR_INT_ENA_V 0x1 +#define UART_FRM_ERR_INT_ENA_S 3 +/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the enable bit for parity_err_int_st register.*/ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_V 0x1 +#define UART_PARITY_ERR_INT_ENA_S 2 +/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_full_int_st register.*/ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_full_int_st register.*/ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_V 0x1 +#define UART_RXFIFO_FULL_INT_ENA_S 0 + +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_V 0x1 +#define UART_RS485_CLASH_INT_CLR_S 17 +/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_done_int_raw interrupt.*/ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (BIT(14)) +#define UART_TX_DONE_INT_CLR_V 0x1 +#define UART_TX_DONE_INT_CLR_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_V 0x1 +#define UART_GLITCH_DET_INT_CLR_S 11 +/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (BIT(10)) +#define UART_SW_XOFF_INT_CLR_V 0x1 +#define UART_SW_XOFF_INT_CLR_S 10 +/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (BIT(9)) +#define UART_SW_XON_INT_CLR_V 0x1 +#define UART_SW_XON_INT_CLR_S 9 +/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the brk_det_int_raw interrupt.*/ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (BIT(7)) +#define UART_BRK_DET_INT_CLR_V 0x1 +#define UART_BRK_DET_INT_CLR_S 7 +/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (BIT(6)) +#define UART_CTS_CHG_INT_CLR_V 0x1 +#define UART_CTS_CHG_INT_CLR_S 6 +/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (BIT(5)) +#define UART_DSR_CHG_INT_CLR_V 0x1 +#define UART_DSR_CHG_INT_CLR_S 5 +/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_V 0x1 +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear frm_err_int_raw interrupt.*/ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (BIT(3)) +#define UART_FRM_ERR_INT_CLR_V 0x1 +#define UART_FRM_ERR_INT_CLR_S 3 +/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear parity_err_int_raw interrupt.*/ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_V 0x1 +#define UART_PARITY_ERR_INT_CLR_S 2 +/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_V 0x1 +#define UART_RXFIFO_FULL_INT_CLR_S 0 + +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) +/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: The register value is the decimal part of the frequency divider's factor.*/ +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) +#define UART_CLKDIV_FRAG_V 0xF +#define UART_CLKDIV_FRAG_S 20 +/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */ +/*description: The register value is the integer part of the frequency divider's factor.*/ +#define UART_CLKDIV 0x000FFFFF +#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) +#define UART_CLKDIV_V 0xFFFFF +#define UART_CLKDIV_S 0 + +#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) +/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */ +/*description: when input pulse width is lower then this value igore this pulse.this + register is used in autobaud detect process.*/ +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) +#define UART_GLITCH_FILT_V 0xFF +#define UART_GLITCH_FILT_S 8 +/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the enable bit for detecting baudrate.*/ +#define UART_AUTOBAUD_EN (BIT(0)) +#define UART_AUTOBAUD_EN_M (BIT(0)) +#define UART_AUTOBAUD_EN_V 0x1 +#define UART_AUTOBAUD_EN_S 0 + +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) +/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */ +/*description: This register represent the level value of the internal uart rxd signal.*/ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (BIT(31)) +#define UART_TXD_V 0x1 +#define UART_TXD_S 31 +/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This register represent the level value of the internal uart cts signal.*/ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (BIT(30)) +#define UART_RTSN_V 0x1 +#define UART_RTSN_S 30 +/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The register represent the level value of the internal uart dsr signal.*/ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (BIT(29)) +#define UART_DTRN_V 0x1 +#define UART_DTRN_S 29 +/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */ +/*description: This register stores the value of transmitter's finite state + machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) +#define UART_ST_UTX_OUT_V 0xF +#define UART_ST_UTX_OUT_S 24 +/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in + transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ +#define UART_TXFIFO_CNT 0x000000FF +#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) +#define UART_TXFIFO_CNT_V 0xFF +#define UART_TXFIFO_CNT_S 16 +/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart rxd signal.*/ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (BIT(15)) +#define UART_RXD_V 0x1 +#define UART_RXD_S 15 +/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart cts signal.*/ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (BIT(14)) +#define UART_CTSN_V 0x1 +#define UART_CTSN_S 14 +/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart dsr signal.*/ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (BIT(13)) +#define UART_DSRN_V 0x1 +#define UART_DSRN_S 13 +/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */ +/*description: This register stores the value of receiver's finite state machine. + 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) +#define UART_ST_URX_OUT_V 0xF +#define UART_ST_URX_OUT_S 8 +/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in + receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ +#define UART_RXFIFO_CNT 0x000000FF +#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) +#define UART_RXFIFO_CNT_V 0xFF +#define UART_RXFIFO_CNT_S 0 + +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) +/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/ +#define UART_TICK_REF_ALWAYS_ON (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_M (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_V 0x1 +#define UART_TICK_REF_ALWAYS_ON_S 27 +/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1.receiver stops storing data int fifo when data is wrong. + 0.receiver stores the data even if the received data is wrong.*/ +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (BIT(26)) +#define UART_ERR_WR_MASK_V 0x1 +#define UART_ERR_WR_MASK_S 26 +/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: 1.force clock on for registers.support clock only when write registers*/ +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (BIT(25)) +#define UART_CLK_EN_V 0x1 +#define UART_CLK_EN_S 25 +/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart dtr signal.*/ +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (BIT(24)) +#define UART_DTR_INV_V 0x1 +#define UART_DTR_INV_S 24 +/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart rts signal.*/ +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (BIT(23)) +#define UART_RTS_INV_V 0x1 +#define UART_RTS_INV_S 23 +/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart txd signal.*/ +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (BIT(22)) +#define UART_TXD_INV_V 0x1 +#define UART_TXD_INV_S 22 +/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart dsr signal.*/ +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (BIT(21)) +#define UART_DSR_INV_V 0x1 +#define UART_DSR_INV_S 21 +/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart cts signal.*/ +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (BIT(20)) +#define UART_CTS_INV_V 0x1 +#define UART_CTS_INV_S 20 +/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart rxd signal.*/ +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (BIT(19)) +#define UART_RXD_INV_V 0x1 +#define UART_RXD_INV_S 19 +/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: Set this bit to reset uart transmitter's fifo.*/ +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (BIT(18)) +#define UART_TXFIFO_RST_V 0x1 +#define UART_TXFIFO_RST_S 18 +/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: Set this bit to reset uart receiver's fifo.*/ +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (BIT(17)) +#define UART_RXFIFO_RST_V 0x1 +#define UART_RXFIFO_RST_S 17 +/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit to enable irda protocol.*/ +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (BIT(16)) +#define UART_IRDA_EN_V 0x1 +#define UART_IRDA_EN_S 16 +/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to enable transmitter's flow control function.*/ +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (BIT(15)) +#define UART_TX_FLOW_EN_V 0x1 +#define UART_TX_FLOW_EN_S 15 +/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable uart loopback test mode.*/ +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (BIT(14)) +#define UART_LOOPBACK_V 0x1 +#define UART_LOOPBACK_S 14 +/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to inverse the level value of irda receiver's level.*/ +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (BIT(13)) +#define UART_IRDA_RX_INV_V 0x1 +#define UART_IRDA_RX_INV_S 13 +/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to inverse the level value of irda transmitter's level.*/ +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (BIT(12)) +#define UART_IRDA_TX_INV_V 0x1 +#define UART_IRDA_TX_INV_S 12 +/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit. + 0.set irda transmitter's 11th bit to 0.*/ +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (BIT(11)) +#define UART_IRDA_WCTL_V 0x1 +#define UART_IRDA_WCTL_S 11 +/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the start enable bit for irda transmitter.*/ +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (BIT(10)) +#define UART_IRDA_TX_EN_V 0x1 +#define UART_IRDA_TX_EN_S 10 +/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to enable irda loopback mode.*/ +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (BIT(9)) +#define UART_IRDA_DPLX_V 0x1 +#define UART_IRDA_DPLX_S 9 +/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enbale transmitter to send 0 when the process + of sending data is done.*/ +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (BIT(8)) +#define UART_TXD_BRK_V 0x1 +#define UART_TXD_BRK_S 8 +/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This register is used to configure the software dtr signal which + is used in software flow control..*/ +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (BIT(7)) +#define UART_SW_DTR_V 0x1 +#define UART_SW_DTR_S 7 +/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This register is used to configure the software rts signal which + is used in software flow control.*/ +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (BIT(6)) +#define UART_SW_RTS_V 0x1 +#define UART_SW_RTS_S 6 +/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ +/*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) +#define UART_STOP_BIT_NUM_V 0x3 +#define UART_STOP_BIT_NUM_S 4 +/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ +/*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) +#define UART_BIT_NUM_V 0x3 +#define UART_BIT_NUM_S 2 +/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to enable uart parity check.*/ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (BIT(1)) +#define UART_PARITY_EN_V 0x1 +#define UART_PARITY_EN_S 1 +/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This register is used to configure the parity check mode. 0:even 1:odd*/ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (BIT(0)) +#define UART_PARITY_V 0x1 +#define UART_PARITY_S 0 + +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: This is the enble bit for uart receiver's timeout function.*/ +#define UART_RX_TOUT_EN (BIT(31)) +#define UART_RX_TOUT_EN_M (BIT(31)) +#define UART_RX_TOUT_EN_V 0x1 +#define UART_RX_TOUT_EN_S 31 +/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */ +/*description: This register is used to configure the timeout value for uart + receiver receiving a byte.*/ +#define UART_RX_TOUT_THRHD 0x0000007F +#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) +#define UART_RX_TOUT_THRHD_V 0x7F +#define UART_RX_TOUT_THRHD_S 24 +/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This is the flow enable bit for uart receiver. 1:choose software + flow control with configuring sw_rts signal*/ +#define UART_RX_FLOW_EN (BIT(23)) +#define UART_RX_FLOW_EN_M (BIT(23)) +#define UART_RX_FLOW_EN_V 0x1 +#define UART_RX_FLOW_EN_S 23 +/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */ +/*description: when receiver receives more data than its threshold value. + receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ +#define UART_RX_FLOW_THRHD 0x0000007F +#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) +#define UART_RX_FLOW_THRHD_V 0x7F +#define UART_RX_FLOW_THRHD_S 16 +/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */ +/*description: when the data amount in transmitter fifo is less than its threshold + value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ +#define UART_TXFIFO_EMPTY_THRHD 0x0000007F +#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) +#define UART_TXFIFO_EMPTY_THRHD_V 0x7F +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */ +/*description: When receiver receives more data than its threshold value.receiver + will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ +#define UART_RXFIFO_FULL_THRHD 0x0000007F +#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) +#define UART_RXFIFO_FULL_THRHD_V 0x7F +#define UART_RXFIFO_FULL_THRHD_S 0 + +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) +/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the value of the minimum duration time for + the low level pulse. it is used in baudrate-detect process.*/ +#define UART_LOWPULSE_MIN_CNT 0x000FFFFF +#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) +#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF +#define UART_LOWPULSE_MIN_CNT_S 0 + +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) +/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the value of the maxinum duration time + for the high level pulse. it is used in baudrate-detect process.*/ +#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF +#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) +#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF +#define UART_HIGHPULSE_MIN_CNT_S 0 + +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) +/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register stores the count of rxd edge change. it is used + in baudrate-detect process.*/ +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) +#define UART_RXD_EDGE_CNT_V 0x3FF +#define UART_RXD_EDGE_CNT_S 0 + +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) +/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/ +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (BIT(5)) +#define UART_SEND_XOFF_V 0x1 +#define UART_SEND_XOFF_S 5 +/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/ +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (BIT(4)) +#define UART_SEND_XON_V 0x1 +#define UART_SEND_XON_S 4 +/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/ +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (BIT(3)) +#define UART_FORCE_XOFF_V 0x1 +#define UART_FORCE_XOFF_S 3 +/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear ctsn to stop the transmitter from sending data.*/ +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (BIT(2)) +#define UART_FORCE_XON_V 0x1 +#define UART_FORCE_XON_S 2 +/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to remove flow control char from the received data.*/ +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (BIT(1)) +#define UART_XONOFF_DEL_V 0x1 +#define UART_XONOFF_DEL_S 1 +/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable software flow control. it is used with + register sw_xon or sw_xoff .*/ +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (BIT(0)) +#define UART_SW_FLOW_CON_EN_V 0x1 +#define UART_SW_FLOW_CON_EN_S 0 + +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) +/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ +/*description: When the input rxd edge changes more than this register value. + the uart is active from light sleeping mode.*/ +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) +#define UART_ACTIVE_THRESHOLD_V 0x3FF +#define UART_ACTIVE_THRESHOLD_S 0 + +#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C) +/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */ +/*description: This register stores the xoff flow control char.*/ +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) +#define UART_XOFF_CHAR_V 0xFF +#define UART_XOFF_CHAR_S 24 +/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */ +/*description: This register stores the xon flow control char.*/ +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) +#define UART_XON_CHAR_V 0xFF +#define UART_XON_CHAR_S 16 +/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */ +/*description: When the data amount in receiver's fifo is less than this register + value. it will send a xon char with uart_sw_flow_con_en set to 1.*/ +#define UART_XOFF_THRESHOLD 0x000000FF +#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) +#define UART_XOFF_THRESHOLD_V 0xFF +#define UART_XOFF_THRESHOLD_S 8 +/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: when the data amount in receiver's fifo is more than this register + value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/ +#define UART_XON_THRESHOLD 0x000000FF +#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) +#define UART_XON_THRESHOLD_V 0xFF +#define UART_XON_THRESHOLD_S 0 + +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40) +/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */ +/*description: This register is used to configure the num of 0 send after the + process of sending data is done. it is active when txd_brk is set to 1.*/ +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) +#define UART_TX_BRK_NUM_V 0xFF +#define UART_TX_BRK_NUM_S 20 +/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ +/*description: This register is used to configure the duration time between transfers.*/ +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) +#define UART_TX_IDLE_NUM_V 0x3FF +#define UART_TX_IDLE_NUM_S 10 +/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ +/*description: when receiver takes more time than this register value to receive + a byte data. it will produce frame end signal for uhci to stop receiving data.*/ +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) +#define UART_RX_IDLE_THRHD_V 0x3FF +#define UART_RX_IDLE_THRHD_S 0 + +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44) +/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ +/*description: This register is used to delay the transmitter's internal data signal.*/ +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) +#define UART_RS485_TX_DLY_NUM_V 0xF +#define UART_RS485_TX_DLY_NUM_S 6 +/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This register is used to delay the receiver's internal data signal.*/ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (BIT(5)) +#define UART_RS485_RX_DLY_NUM_V 0x1 +#define UART_RS485_RX_DLY_NUM_S 5 +/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: enable rs485's transmitter to send data when rs485's receiver + is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (BIT(4)) +#define UART_RS485RXBY_TX_EN_V 0x1 +#define UART_RS485RXBY_TX_EN_S 4 +/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable loopback transmitter's output data signal + to receiver's input data signal.*/ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (BIT(3)) +#define UART_RS485TX_RX_EN_V 0x1 +#define UART_RS485TX_RX_EN_S 3 +/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to delay the stop bit by 1 bit.*/ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (BIT(2)) +#define UART_DL1_EN_V 0x1 +#define UART_DL1_EN_S 2 +/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to delay the stop bit by 1 bit.*/ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (BIT(1)) +#define UART_DL0_EN_V 0x1 +#define UART_DL0_EN_S 1 +/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to choose rs485 mode.*/ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (BIT(0)) +#define UART_RS485_EN_V 0x1 +#define UART_RS485_EN_S 0 + +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48) +/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ +/*description: This register is used to configure the idle duration time before + the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ +#define UART_PRE_IDLE_NUM 0x00FFFFFF +#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) +#define UART_PRE_IDLE_NUM_V 0xFFFFFF +#define UART_PRE_IDLE_NUM_S 0 + +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c) +/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ +/*description: This register is used to configure the duration time between + the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/ +#define UART_POST_IDLE_NUM 0x00FFFFFF +#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) +#define UART_POST_IDLE_NUM_V 0xFFFFFF +#define UART_POST_IDLE_NUM_S 0 + +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50) +/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */ +/*description: This register is used to configure the duration time between + the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/ +#define UART_RX_GAP_TOUT 0x00FFFFFF +#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) +#define UART_RX_GAP_TOUT_V 0xFFFFFF +#define UART_RX_GAP_TOUT_S 0 + +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54) +/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ +/*description: This register is used to configure the num of continous at_cmd + chars received by receiver.*/ +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) +#define UART_CHAR_NUM_V 0xFF +#define UART_CHAR_NUM_S 8 +/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ +/*description: This register is used to configure the content of at_cmd char.*/ +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) +#define UART_AT_CMD_CHAR_V 0xFF +#define UART_AT_CMD_CHAR_S 0 + +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58) +/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: refer to txfifo_empty_thrhd 's describtion.*/ +#define UART_TX_MEM_EMPTY_THRHD 0x00000007 +#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S)) +#define UART_TX_MEM_EMPTY_THRHD_V 0x7 +#define UART_TX_MEM_EMPTY_THRHD_S 28 +/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: refer to the rxfifo_full_thrhd's describtion.*/ +#define UART_RX_MEM_FULL_THRHD 0x00000007 +#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S)) +#define UART_RX_MEM_FULL_THRHD_V 0x7 +#define UART_RX_MEM_FULL_THRHD_S 25 +/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ +/*description: refer to the uart_xoff_threshold's describtion.*/ +#define UART_XOFF_THRESHOLD_H2 0x00000003 +#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S)) +#define UART_XOFF_THRESHOLD_H2_V 0x3 +#define UART_XOFF_THRESHOLD_H2_S 23 +/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: refer to the uart_xon_threshold's describtion.*/ +#define UART_XON_THRESHOLD_H2 0x00000003 +#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S)) +#define UART_XON_THRESHOLD_H2_V 0x3 +#define UART_XON_THRESHOLD_H2_S 21 +/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: refer to the rx_tout_thrhd's describtion.*/ +#define UART_RX_TOUT_THRHD_H3 0x00000007 +#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S)) +#define UART_RX_TOUT_THRHD_H3_V 0x7 +#define UART_RX_TOUT_THRHD_H3_S 18 +/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: refer to the rx_flow_thrhd's describtion.*/ +#define UART_RX_FLOW_THRHD_H3 0x00000007 +#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S)) +#define UART_RX_FLOW_THRHD_H3_V 0x7 +#define UART_RX_FLOW_THRHD_H3_S 15 +/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */ +/*description: This register is used to configure the amount of mem allocated + to transmitter's fifo.the default byte num is 128.*/ +#define UART_TX_SIZE 0x0000000F +#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) +#define UART_TX_SIZE_V 0xF +#define UART_TX_SIZE_S 7 +/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */ +/*description: This register is used to configure the amount of mem allocated + to receiver's fifo. the default byte num is 128.*/ +#define UART_RX_SIZE 0x0000000F +#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) +#define UART_RX_SIZE_V 0xF +#define UART_RX_SIZE_S 3 +/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to power down mem.when reg_mem_pd registers in + the 3 uarts are all set to 1 mem will enter low power mode.*/ +#define UART_MEM_PD (BIT(0)) +#define UART_MEM_PD_M (BIT(0)) +#define UART_MEM_PD_V 0x1 +#define UART_MEM_PD_S 0 + +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c) +/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: */ +#define UART_MEM_TX_STATUS 0x00FFFFFF +#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S)) +#define UART_MEM_TX_STATUS_V 0xFFFFFF +#define UART_MEM_TX_STATUS_S 0 + +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) +/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: */ +#define UART_MEM_RX_STATUS 0x00FFFFFF +#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S)) +#define UART_MEM_RX_STATUS_V 0xFFFFFF +#define UART_MEM_RX_STATUS_S 0 + +#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) +/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: refer to the txfifo_cnt's describtion.*/ +#define UART_TX_MEM_CNT 0x00000007 +#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S)) +#define UART_TX_MEM_CNT_V 0x7 +#define UART_TX_MEM_CNT_S 3 +/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: refer to the rxfifo_cnt's describtion.*/ +#define UART_RX_MEM_CNT 0x00000007 +#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S)) +#define UART_RX_MEM_CNT_V 0x7 +#define UART_RX_MEM_CNT_S 0 + +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68) +/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the count of rxd posedge edge. it is used + in boudrate-detect process.*/ +#define UART_POSEDGE_MIN_CNT 0x000FFFFF +#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) +#define UART_POSEDGE_MIN_CNT_V 0xFFFFF +#define UART_POSEDGE_MIN_CNT_S 0 + +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) +/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the count of rxd negedge edge. it is used + in boudrate-detect process.*/ +#define UART_NEGEDGE_MIN_CNT 0x000FFFFF +#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) +#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF +#define UART_NEGEDGE_MIN_CNT_S 0 + +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78) +/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */ +/*description: */ +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 + +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C) +/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ +/*description: */ +#define UART_ID 0xFFFFFFFF +#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) +#define UART_ID_V 0xFFFFFFFF +#define UART_ID_S 0 + + + + +#endif /*__UART_REG_H__ */ + + diff --git a/tools/sdk/include/esp32/soc/uart_struct.h b/tools/sdk/include/soc/soc/uart_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/uart_struct.h rename to tools/sdk/include/soc/soc/uart_struct.h diff --git a/tools/sdk/include/esp32/soc/uhci_reg.h b/tools/sdk/include/soc/soc/uhci_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/uhci_reg.h rename to tools/sdk/include/soc/soc/uhci_reg.h diff --git a/tools/sdk/include/esp32/soc/uhci_struct.h b/tools/sdk/include/soc/soc/uhci_struct.h similarity index 100% rename from tools/sdk/include/esp32/soc/uhci_struct.h rename to tools/sdk/include/soc/soc/uhci_struct.h diff --git a/tools/sdk/include/esp32/soc/wdev_reg.h b/tools/sdk/include/soc/soc/wdev_reg.h similarity index 100% rename from tools/sdk/include/esp32/soc/wdev_reg.h rename to tools/sdk/include/soc/soc/wdev_reg.h diff --git a/tools/sdk/include/tcpip_adapter/tcpip_adapter.h b/tools/sdk/include/tcpip_adapter/tcpip_adapter.h index 4f3b49ed..f1a0a9e2 100644 --- a/tools/sdk/include/tcpip_adapter/tcpip_adapter.h +++ b/tools/sdk/include/tcpip_adapter/tcpip_adapter.h @@ -136,6 +136,39 @@ typedef enum{ TCPIP_ADAPTER_IP_REQUEST_RETRY_TIME = 52, /**< request IP address retry counter */ } tcpip_adapter_option_id_t; +struct tcpip_adapter_api_msg_s; +typedef int (*tcpip_adapter_api_fn)(struct tcpip_adapter_api_msg_s *msg); +typedef struct tcpip_adapter_api_msg_s { + int type; /**< The first field MUST be int */ + int ret; + tcpip_adapter_api_fn api_fn; + tcpip_adapter_if_t tcpip_if; + tcpip_adapter_ip_info_t *ip_info; + uint8_t *mac; + const char *hostname; +} tcpip_adapter_api_msg_t; + +#define TCPIP_ADAPTER_TRHEAD_SAFE 1 +#define TCPIP_ADAPTER_IPC_LOCAL 0 +#define TCPIP_ADAPTER_IPC_REMOTE 1 + +#define TCPIP_ADAPTER_IPC_CALL(_if, _mac, _ip, _hostname, _fn) do {\ + tcpip_adapter_api_msg_t msg;\ + memset(&msg, 0, sizeof(msg));\ + msg.tcpip_if = (_if);\ + msg.mac = (_mac);\ + msg.ip_info = (_ip);\ + msg.hostname = (_hostname);\ + msg.api_fn = (_fn);\ + if (TCPIP_ADAPTER_IPC_REMOTE == tcpip_adapter_ipc_check(&msg)) {\ + ESP_LOGD(TAG, "check: remote, if=%d fn=%p\n", (_if), (_fn));\ + return msg.ret;\ + } else {\ + ESP_LOGD(TAG, "check: local, if=%d fn=%p\n", (_if), (_fn));\ + }\ +}while(0) + + /** * @brief Initialize tcpip adapter * diff --git a/tools/sdk/ld/esp32.common.ld b/tools/sdk/ld/esp32.common.ld index 8d5a9c42..5c1dba68 100644 --- a/tools/sdk/ld/esp32.common.ld +++ b/tools/sdk/ld/esp32.common.ld @@ -88,8 +88,7 @@ SECTIONS *libesp32.a:heap_alloc_caps.o(.literal .text .literal.* .text.*) *libphy.a:(.literal .text .literal.* .text.*) *librtc.a:(.literal .text .literal.* .text.*) - *librtc_clk.a:(.literal .text .literal.* .text.*) - *librtc_pm.a:(.literal .text .literal.* .text.*) + *libsoc.a:(.literal .text .literal.* .text.*) *libpp.a:pp.o(.literal .text .literal.* .text.*) *libpp.a:lmac.o(.literal .text .literal.* .text.*) *libpp.a:wdev.o(.literal .text .literal.* .text.*) @@ -97,6 +96,7 @@ SECTIONS *libnet80211.a:ieee80211_misc.o(.literal .text .literal.* .text.*) *libhal.a:(.literal .text .literal.* .text.*) *libcoexist.a:(.literal .text .literal.* .text.*) + *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*) _iram_text_end = ABSOLUTE(.); } > iram0_0_seg diff --git a/tools/sdk/ld/esp32.rom.ld b/tools/sdk/ld/esp32.rom.ld index 6cbd2fc7..b61bc7ef 100644 --- a/tools/sdk/ld/esp32.rom.ld +++ b/tools/sdk/ld/esp32.rom.ld @@ -125,7 +125,7 @@ PROVIDE ( __divdi3 = 0x4000ca84 ); PROVIDE ( __divsc3 = 0x40064200 ); PROVIDE ( __divsf3 = 0x4000234c ); PROVIDE ( __divsi3 = 0x4000c7b8 ); -PROVIDE ( dummy_len_plus = 0x3ffae290 ); +PROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 ); PROVIDE ( __dummy_lock = 0x4000c728 ); PROVIDE ( __dummy_lock_try = 0x4000c730 ); PROVIDE ( ecc_env = 0x3ffb8d60 ); @@ -1349,13 +1349,10 @@ PROVIDE ( sbrk = 0x400017f4 ); PROVIDE ( _sbrk_r = 0x4000bce4 ); PROVIDE ( __sccl = 0x4000c498 ); PROVIDE ( __sclose = 0x400011b8 ); -PROVIDE ( SelectSpiFunction = 0x40061f84 ); -PROVIDE ( SelectSpiQIO = 0x40061ddc ); PROVIDE ( __seofread = 0x40001148 ); PROVIDE ( setjmp = 0x40056268 ); PROVIDE ( setlocale = 0x40059568 ); PROVIDE ( _setlocale_r = 0x4005950c ); -PROVIDE ( SetSpiDrvs = 0x40061e78 ); PROVIDE ( __sf_fake_stderr = 0x3ff96458 ); PROVIDE ( __sf_fake_stdin = 0x3ff96498 ); PROVIDE ( __sf_fake_stdout = 0x3ff96478 ); @@ -1404,40 +1401,6 @@ PROVIDE ( slc_set_host_io_max_window = 0x4000b89c ); PROVIDE ( slc_to_host_chain_recycle = 0x4000b758 ); PROVIDE ( __smakebuf_r = 0x40059108 ); PROVIDE ( specialModP256 = 0x4001600c ); -PROVIDE ( spi_cache_sram_init = 0x400626e4 ); -PROVIDE ( SPIClkConfig = 0x40062bc8 ); -PROVIDE ( SPI_Common_Command = 0x4006246c ); -PROVIDE ( spi_dummy_len_fix = 0x40061d90 ); -PROVIDE ( SPI_Encrypt_Write = 0x40062e78 ); -PROVIDE ( SPIEraseArea = 0x400631ac ); -PROVIDE ( SPIEraseBlock = 0x40062c4c ); -PROVIDE ( SPIEraseChip = 0x40062c14 ); -PROVIDE ( SPIEraseSector = 0x40062ccc ); -PROVIDE ( spi_flash_attach = 0x40062a6c ); -/* NB: SPIUnlock @ 0x400628b0 has been replaced with an updated - version in the "spi_flash" component */ -PROVIDE ( SPILock = 0x400628f0 ); -PROVIDE ( SPIMasterReadModeCnfig = 0x40062b64 ); -PROVIDE ( spi_modes = 0x3ff99270 ); -PROVIDE ( SPIParamCfg = 0x40063238 ); -PROVIDE ( SPI_Prepare_Encrypt_Data = 0x40062e1c ); -PROVIDE ( SPIRead = 0x40062ed8 ); -PROVIDE ( SPIReadModeCnfig = 0x40062944 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_read_status = 0x4006226c ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_read_status_high = 0x40062448 ); -PROVIDE ( SPI_user_command_read = 0x400621b0 ); -PROVIDE ( SPI_flashchip_data = 0x3ffae270 ); -PROVIDE ( SPIWrite = 0x40062d50 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_write_enable = 0x40062320 ); -PROVIDE ( SPI_Write_Encrypt_Disable = 0x40062e60 ); -PROVIDE ( SPI_Write_Encrypt_Enable = 0x40062df4 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_write_status = 0x400622f0 ); -/* This is static function, but can be used, not generated by script */ -PROVIDE ( SPI_Wait_Idle = 0x400622c0 ); PROVIDE ( srand = 0x40001004 ); PROVIDE ( __sread = 0x40001118 ); PROVIDE ( __srefill_r = 0x400593d4 ); @@ -1569,6 +1532,13 @@ PROVIDE ( xthal_set_intclear = 0x4000c1ec ); PROVIDE ( _xtos_set_intlevel = 0x4000bfdc ); PROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 ); PROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 ); +PROVIDE ( esp_rom_spiflash_config_param = 0x40063238 ); +PROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 ); +PROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 ); +PROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 ); +PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c ); +PROVIDE ( esp_rom_spiflash_master_config_readmode = 0x40062944 ); +PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 ); /* These functions are xtos-related (or call xtos-related functions) and do not play well diff --git a/tools/sdk/ld/esp32.rom.spiflash.ld b/tools/sdk/ld/esp32.rom.spiflash.ld new file mode 100644 index 00000000..64af6a4b --- /dev/null +++ b/tools/sdk/ld/esp32.rom.spiflash.ld @@ -0,0 +1,23 @@ +/* + Address table for SPI driver functions in ESP32 ROM. + These functions are only linked from ROM when SPI_FLASH_ROM_DRIVER_PATCH is not set in configuration. +*/ + +PROVIDE ( esp_rom_spiflash_write_encrypted = 0x40062e78 ); +PROVIDE ( esp_rom_spiflash_erase_area = 0x400631ac ); +PROVIDE ( esp_rom_spiflash_erase_block = 0x40062c4c ); +PROVIDE ( esp_rom_spiflash_erase_chip = 0x40062c14 ); +PROVIDE ( esp_rom_spiflash_erase_sector = 0x40062ccc ); +PROVIDE ( esp_rom_spiflash_lock = 0x400628f0 ); +PROVIDE ( esp_rom_spiflash_read = 0x40062ed8 ); +PROVIDE ( esp_rom_spiflash_config_readmode = 0x40062944 ); +PROVIDE ( esp_rom_spiflash_read_status = 0x4006226c ); +PROVIDE ( esp_rom_spiflash_read_statushigh = 0x40062448 ); +PROVIDE ( esp_rom_spiflash_write = 0x40062d50 ); +PROVIDE ( esp_rom_spiflash_enable_write = 0x40062320 ); +PROVIDE ( esp_rom_spiflash_write_status = 0x400622f0 ); + +/* always using patched versions of these functions +PROVIDE ( esp_rom_spiflash_wait_idle = 0x400622c0 ); +PROVIDE ( esp_rom_spiflash_unlock = 0x400????? ); +*/ diff --git a/tools/sdk/lib/libapp_update.a b/tools/sdk/lib/libapp_update.a index d7894d77a317c138d0357102da864c7ad54bd82e..40af8532458d8a5486648abfd2d8b4dcfe12fdb1 100644 GIT binary patch delta 198 zcmccdl3E^67}Na(@OJ_3E^67}Na(@OJ_6J_G=NANT4IqjF*n~l$4{D_$-sQ_&d^jQL(9pG7GiuTMl(!4?CbId!_N`e^juFTJ zCQHM~4dGghFShSjVpL#a6rKJ+g;7kZn3;irIhKKefl0_5L^5)mV`N}pVq(>rE}+V& zk@643lPUp8v9Px@F)%Q3urf1)DE1Xh3=GWE7#J9sMRh==J;*3UR}k|PNJ=Lh#0&$8 z>SlrsV2uaqWMTgWGKYn|4`enYN5=Fys*FmEa?|&#GHToAGBYr+>P}%`U|`@-1+n!y zL3%m%Gcho*>Vw$KoCW#C46Ftmj0_Ac94#Ox5Y^v58c&2(cIuwXNYS~2~y3!^sUs_Fk-7?qi3@J|ldCN|y5l~I7{GXLZSMq)yy zj0_Bnps%iWmIPro_^SsQJslJZu%QnMm4tY0t^h^jMJ1Dl^9*7 jTe~r;Gai|q?8c}COIP4zw|%u6<33lI(Ds5J#$Or${LZX^ delta 739 zcmezNitW`awh7YghDN4l78Yg`l}dT57#Q8E7#MrPKzRDwEJmg2E0P&`CSQ=@+IVLr z6I7|`^aXB=;+q#U+Zn(_CLh=?w)vlNvNDQ5UHE=6m;gjibY7e%Ol0$c?OU^89FPI5 zmWCDv3X|jW)EVz=-><}|z{JQk{ecRjm{dA50|Rp`0|Nt-kU5BC4N@k;WjS6kS2gyC5l@a1hfA zB&wSUHh?vlnSp_ch5aeW02cN>klBnJG1KR$GAc0&P2aD|sBN3b%)r2^JB5LPfq_F3 z#MbKs>E+nM#K6F+4`MTO7UUN*uo`eMGBB`kRDjeNrZ6%v@NjfaS65>+wq#{yU|`@) zXJBAp29SwUm>C$@dq8Xfj(?2PFQ_q!G47fET#ZqkQDZv4I-?z9@pM0R##fAW z(=9a^4aEhSKqg7sFfuTJFq@CG4Ko9S&GtqO#*geg!3CLaIf=y?&Ka2n(>o0qUr)X$ zEYFdWT9%od>Y1{Ajv=F$0Heb6=Z=i;8JA4I?!@TN$TMBtnbDsyWO}(XV>x5M^!Fg1 z!E}2UuwXxknlt^r3!^sUyy@JojLM8X)Ad~$)tQd-PhMaoHa*XkQGn?`|MUh|Mm5Ga z)0ew4sxz`rKMzvzLw5QPkm&2_@@|akj26?~LDY`v`EHC_(6nQ=eSsU}RaY1foY1yU J?qPha0RYbhsW1Ql diff --git a/tools/sdk/lib/libbt.a b/tools/sdk/lib/libbt.a index feaba6919faa80400c0c28de4f1e332e248ad810..f5fa06d32f03fab711386e45274ccd4252a7c33d 100644 GIT binary patch delta 1065088 zcmX@o)y;Bca}Ub|>3SmrBSTXYLj?r`1rR_c6%e>}MGmF5BS6jE*u4 zB;k5eHBec7JxQ*mvgM49GWA3S7yJGd479=Zv@)1TbL&a;8JFe<2C{JU8wM^A?w-TI zg@o&oIr!Mz#Y-57!MvFp7)ZeNq$s9=+Isx1<^S}Bfu^_~$pS&92MpA}LUZ>p!119g z3_@sFIPeAo4A;XL^rA)fGB683}R3$&Kkgg6_?#%5QpK7 zXBfm`_-PD-I1-jPSv+Bos|OKKEU$coL4IBVgM!i>2yQvUpfKePcKl!lg94FQv0Q)wE1tQ6pDam5z~B|`WePd$UuJ06O#a={q}lJG_W24yH#;j33* zP~n4O{T2ol7%qFkph5&zz4L-W&FBLht2b0I5Q{aKXE12gg9s?rOfX?U$6CvOFwhd$ z)6#H4X6tSYsAtgK7%+gio-)e~o`x_Giw(bNFks+%Y=R_;8K0ZOKrXJwrqR@Y0Ry$L z*#Qj(7&ea$U_it5=mK=+*JHSdst&Nar@??1*Ar5JL*B-vfPosgo)|-HcZM*Kg6(!J zVIUIM6RQxc&iv2gSiMteEU?2;x%VBUKfa?h< zps{>CK^Icf0p2_z3^43-Y5{}Ksd^AW8TM5(U?3aUqiOb2Fkyh>ga8IVDq#PT76x3n z9+yPGgeMFr`05gd05WjkY99tXxE`M*#d5)Kc^J@f$c`Ka1g=NsAlRWb9~h{O!#+qb zVBmUef@oq9cXSvi!BKt^47hMTE(wr$Oh69y3T zx*qHbsO1T3XE4wi*VEfVH2dmF^Kmls6b7o|dMX>38Zd)_6kLx_aoYbq3?Q5lzJ!4i zoYhdnfCJa#lE4tp3G89OhjS<1U?3gWlcR}>dg@7ZbwL*g12u7d!HW_GQgES?2Ll{W z>0v0O4A-L=P_)c~fe7NFBpo+#`Tz*OKNs7&<)qq(=se})sySf@^>W+ z*lD7YZ=+V z3jmC!FHF&uV6iYTvzX2}Nk~H|k%57MnSsHC0R%J{d>A~ZUrgamo9=L{Qebk!W%KDV zyVNm z1K2XCZ9Ghx9GVi13=E4jpcXbVFlchXUDLslCSjarWI8$Ps%pIzkA@-xLnjl+0EBU1 z76a704vsVp*)$_Xn49nHf;g8)0#zr-Jxn0?FoWC%@wo=bT2Od_@g4>ShBaUo1H%jk z28I>}B?g8V1_p)_1_lNf1_lNl1_lNRr~(cK28RFt?Ke-~u!T`(dcb07gXw3c@`^BW zOn;asE6yk}{o!6l@yScBnM}VDZZ5)DGQDvxqc~#=SeS7JgjzHG;2uVC#yucPdUC*Z zkLep$HgHWpchQS)`ksA^64Mhj>m;UMFq4#+UL&i(BesrdmM%SzTaFf%YPGqGO*QH*SLj0_AcaSRL$OhP`Obiv5c!wQmTiGhKcg}s`Efq|8UnT35d zGXnz~%Q6NA26kpfj`M5`3@R)$I2ah1MIAvVg@cqUMuC_uAZv9}LCjLN>2@!Cr0Q## z7#LV`z*a71VPIe>KF`3wz{SGSAjZhRzzxbLER7&00|O68h9!uDfq|uskr8C&I*>u8 zObiUHInzN*CXi?Zm|4KWz`(A03nZGu!N9;FaRlsfraD#z23{7Bx45KR7#SGq`D8$G z$9I^8fq{{)85Bl*K_I0JTpXMVOBop$_}$nT7&sL{b}{ffF)}c4DuErsz>>khz`&^t zG6iBHr`=UX1_r)+U;}wLKn7NT0+eqb8z?ifw6HKRa5`^bgt>szgO#bCfq}1siGhKE z?*ki1!vYQl1|~jPP&hHL>|0_&u2!7#Mv(Y#x4HP$>9<*aG~*AP@RAGcz!V@H>F?`p;!%sArJif6TzZ zz!T8$_5?vO1#%}RC{Q>-JWf!;U|?ebd4vO`gHwlrp&pcu;+Pp21VOSO z$8myU7fdj)vE+kfKuKpVGXn$I05HM8#?lFs0l6D22-CBenSntFWEvaGUYH_~!@-Ie z*jP@$1VKKi2gely8_QjgE|6Qp?CtMLLaQ+01E?yxBw_PPfQ2gaxLSWOjZU4 z@hp&sT0pS?stILn85kIzq3AY{W{hDpkgjKpWi()55ETPCqaI`sDBvLmZGszA4>G6; z=m(Iw1t9xd7#J8J z;aLl}zW`(cNK(WE3SBOw&}AxSU|e42KhN4XKx1C1yaN~ zXE(?w8BlO<1~D0fWO*1E82sRxK_$yUb_NDTe zU(RXdU|^60Wym~GD9ZJM0_+FO@qS<>w>cOX#IJyS^#fGxO@O=o7bvU#VPs&C6k%Xs zsN!N^kkn#eU})uHV30LpU|^U4aVt|10|SF{eHbVJMHyjcTY=3s=44<{0h=w#2r^uX ziGe{C95CXHAk*8J7#O6)7#J94b1^VzLQ+4-JV`kQ28LxIC#xLUm{C{bItv2>2s7$w@Pe8ltPBiX_30Y%91IK~%+;d_ zsxLs8Z3UBN2qOan2(!Ip*5qOVwTT!Q*c90`mDm^n9)E(f{}p%gc%JrJ}@va zfH3#3>5BJ!JtjYR7&LvwZY8_r8Sd#}CuJ3<@6T-%p5Aj(R#2Rkftdp$$0W|cAluo*$SBBYC_HVWxcp?D#}3mE z&61LuZm=nUV|tCeGspB>-5LDTH$JV96GBO15OgDU&D?0tcBW{-I0()bGxIj4+B+no*{VtcA!esF$PK+_rH-y?q zOrNlliG#6adTxk~#Poaq@f?gZrk}2^Q<&~>i-~3WdmVYU=?@-CvQGEw7UrA&|6qgU z^m&IH%mhH$6jZk`GDLwgP|$Q+IWbvodr%9N;WJ~vr7Y<)gD*#pzt2n#Au(E$oFkoQ0|$N?alYkEL*tvJ~BdYJ7XTR^sJLTz`1cBAf2p2Xh#cV zGYC&*fb_yvLVIPq7#J8pHN+{91q_hFAH)Qe@*o-(y=ZQeXTWeANHr9*vurTW|*my``(N3Go+I#pL|Fw9NGQ5(d}cfOua==Xj?OhWOmllGKWL z$S}%eg|~{+jly}wU6M*ta^s8A;**l%!Q&?J#i_Xk8Ab6WiP@>(Xe`L61j(nQf~5mX zQ%h4l67y1WQsYY)3d#Z!ixP7u&wV4QoS9dWT2xe8P!gY#S)7=Zlgf~hoEcx5SX2_9 zlvtWllvt8Fol(wLZ1Vh%Y||b8*Guz3T~wNvlb@W;FnPmk@#*H*WR<2n{Nk3K-0+@V zs4OJ0INKFuu5(dlNoI0l&h*6VvXaxQr}}Wlfd+xnO7oJ7<4YJo>fnw-_Gf%~QDQ+s zY7qk{bPUbnA>%?|Z498GM02rIVsUCnWkG6u$@KMk4N{XQd}5vM$igTwS?P_?WbZGW z(-(J(D^0&(&L!;%u?6IExE+u<0NavLP*TnS;Ts#pmoVfe7H1<{Sd>~^l3$cMnfJ2_ zFGFcwab|j6YKlT;9w_>xn2J-UH%_e;oxbRUtPo2|VoBokzzKNMpmLF6EfLxNF%K%ah4p0`qP+x}W2XD)Y>cxZ8E(20( zgF6`cnVgm$4+^{KU6~EC(>Fwl=TGmoD(13-`2&)gp@HF^S(fTnl%MMv90bt~ zP1EsdIf?0r)R>n)+5U|RA1FnD<0c;D%IS)%j4IQYurUfK7MCQJloo@tj#EgyufL0H zyiMW3o}m_A6G~;KuaS~JjUnbC#FnqWMz~W1(hoxUVL(5PJCis3b^>0evX+@ zeEOv|9OcvV*E(=ampzfnG2NiaPhhgZSB~lPRm3@_&+GE%m~OzL!ZF$4tHAVtnSw0S zWo8R5n?cT6m>pB}&8foFO>e*?$#0<&0w$sfMuOqbD% z<(V!&Cz)q@{_IAH=^NiP*i7Gjl9^}v1*KSt$s4{)Os|;^6gAt-{Ii8| zxOSV5yKOw$7! zWraCG-4>9C*rzZ2tsq)2%>e4YfCMbSjVnFqs5&GL7#WNhoIsM`CK&?*BZDyms1XAa z0yTD+7^E3;7$9mvJya$J35H70kPEbT4&rw~8$pm5lVF$+Z480=^$ZdWo1m>CumFPu z!!c;<2-MmE8E_jsJ`L&agZMw7ttCj5N-*$2yPcrnVnzl723bbP*fu1pBpCD=A+0GG zALMu#o?c_8=)|nT;5hl?KYe~s*9jy8GLVtMWV$?4q5t%GAB6=b_x(4Re$OXeY5Ika zwsO<|eY7>0KJS&Rz;w9}!V9L}V^o;Vb)Q3sF>88cC!hTEfH$%N({HTu5tyF9$S5$q z=BTLvio#Gt~UK3#NXj{NjDuD%?cpr)!2 zgBnBp^hUu-aZXU9P>4Z;p=J8TfOL7rb<+<%a}ehQwO@r8v>5JBUuab=F9>SOfs6-r zFNGL%7}Tcw%1en)pV6x(F^!p#jkg$70>g^`>8#9*>THliHeH38QI{K3I6&+1?f%S+ zwv4Qac`5n1+uK+ea~atnMI^Xku$`NYQIv6d_-hHi>4`V3g{PayFbYl={SY8AeQl*Y z4=<<#%)r2)0ZNRj)AI~um8bLS^0H5Nxuh*Py;D1zXL{w4LW$|DeiFjdUub3Xuz?)S z=sP{{b*lJu&+H%`RghL#a#aV(LXsyVs4EE#JVu%6c5y7?yulD@8IWZm)AiU2#ix6^ z7V|J_OwY>>5}$r`tAg?3) zHn%f~#lQfH6cJ;{qy~u14eE|CFff=y)q{#W5S!Z-qTU}W4(h^z*xYUq@%nVA1Sp|^ z*f5DIs5mHtgV@~e5Dnc>aZrZ@#OC&Zh=cMW$Uz|AgV@}j5OGj;1c|FKFo3frw--eG z5X2l%;$UC^ak#x955hDf$kgGv#ZqUFjXgnRH*$9$!`571( zxIx373=9lXP;ro>L2PbNSBZgv0Tgi{b3l#;vALn85Xejs$h;qD29SZ<7vcs`=!uvz zD1&(*4mT*w7#Khu9R?9IurQd-9XS11k+obss4FRA4oMnHAV-)(91Ti;AaPLWf}#_| z200F7Cx{IyWI*PN$U^4HK=}p41_hol)EtnbL2Pbl`qGAqgF+g_<_>{&)IhyvkY-R0 z1^WzC1~Wh$B4PnaD=fwAcHI*@*p;M7{p`D(;4F`gzG_W1C0@hSVFXdybWT5 z6oIshC@?U9Y8_Cr1hGLW5LCW^)PUqcZ0-n$i zaZp%+XB)Ud^I!}N44{5J$O2HHfc*t3Y(S&#AooMrAPYs57#Ki(WUzyj7#Ki3e~@7! zRuB(>*xaD*I%v=pq*sZ70o3^ihlv#=@<43vSdgPZlX4(M*3;`s1jMJ_)K{5)_G78U zblzjJ(bH{q#-~pI*)5(9 zBUH|1`paGM3NoN-nSp@;G-M4j8RXNGP!%!LRd*v)+<}UMS~w43?CFWS;}xc#^ik&L z1+{Q~Ld9FA&qdP7!wB&axUBu$2Ri;nf6E88{Qh-rq`b7{cv{qDQI`7_iiRl|bVxAz@TM(-i#LCpNRGEGd#9I26 zPi6XF5bNPvKKbci4#s>MOEXowx=mI@?s(2O}uycbD) zCWH+Mgk=y8I1u(Cu@57$Pa?6;BeAa`vEL%GKO?b!BC-D?vDuj185m%$69kR9KtnGB7X%g49FVF(7fM1!*8QXdaY-fgu~jhKiSh*ii8*5F4Zy zL$tW`WosMGOoK8$oPPP0zr{4{{u| z)V_rz{shE^s(;7Az);T!)$j?b0aSdmgJ$%gF69BSp=y*sY^Y`(5F09PzzPX!Q1K2L zXon>|SCAU0IbI+(R6Tfp7Gh34LkW^Z1=Ju=UC;~?hbUs`1+k$9O#-o@25knhp=$Pm z*ii9v#u<<}RLwOI8*0vN5Ze$G{tOHZFF+iqX3)AAm=D0q7NFwdY!F|9Dj6lv z#1T~72*ie3U;|=9#T}sPL6wg;NF1sr6vT!)BB~z5fl8!<*ig;j)UYhz&L86o?HKzW`!G#X<9HpgOf4RIS}dl6V7RgIakE3=E$^Y^dg+ zAU0I_Lj4 z8eBnaPmi9^-of!I*-P7oU^4qiAS4a)Tl43j~6q3n4`YF2~TVDWke zhT|X(RP#j;8`Sn?U|_fk(hOz40*OO|`X>?_JYNV^!w(w2hh|X)5F08EUIqiru4W){ zP&=1_fgu3Iu7`HJl0h7(BQim3P#=hafgzWJfk7C`u0RrR0L$IfxDF05C8xyat&KWq$*SL)9>X zraYi#3nH<_Ky0XbEhM%Hhz-?i4`M^QB@E7-3=G1`pj9~x3=Cc%38y=^!?!7s9~6kON{v#VbH;XiU_C*ii9K5E~lceIPbed=`ieO}Fzotr7L>YLEo9 zG~NJWLp5wcV(&&`@1L&tSzo;V6q3+IB=%J#_8lbl10?oyB=&10_GcvacO>?IBsMb_ z*y)fmjT^!NX9RvEwm1@78i}op#8yXQ>mjj?kl2<;Y+EF@3m2$Pg$9%dl7v4JI~a)_ zg~X0SVkaZ9(~;QuNbF)Hb~TI*8gZ+KaTpjF+K|{?NbHG7?5RlXIY{gUNbKcE?A0*# z^um=!($f_Z6(ptytQD1*{v%tShYjR=M$YMZb93aTpZOOeF`Z|hl*IHuAl4ZRJD%w= zv1vTKy`ZKowB(#Py*D;ZoN@W|m&_5$(@Q!yC8o>lN|czMGs}{P@#SVyH!8HzKh?3qcs6rO6bKIFvnmx^HZ@xa3MCp|wctEz=p7REj4aLJ~TL#6F9} zzKF!Wjl{l>#D0dveuc#TGd*!hr8pz|^xP$t;*y|sC5+JGNe;fcq350D84sFna7nnhy zbtW+OM2I4=nyE-^&~O~1_Vj)8eS@cW#-($!f+~8B=?jlr3xk;w(--zAL6|zz3+LuQ zm@d;NzOsZcW2QUqOcVz9`az8y(2xhLnFwl8fsAXJelS-Aq6E|w0j-9GDFJ0akdigi z3wI_$4BRt);sMcs=`X+faZh(R?Z`X*s{*6;^qz&jveTF5@e5Dia!}NFy65ZCkm<3D ze0iql9*dnYJ@axV_w)bKA}=5VZ1G zg2b)_1qL){8G*V7&{n-ahz+fY>p*O1(_=P>4Q)zn0tby2|L7fRuanPX7G$%wmXy! z8dr+~v7zyu0A+*3)1Yk7fL#uh4Vqmkg0ew{RvDBHYDR#T`wBtRN2DMk8LfN2!+t*MwXn^)TlnolsW@2Sv z5Q3H&Y*04y^hU#k>gf)~3ANKX&q#$#*A2DvnEp3DB4N7iW?zZvYxQ|mrvDTyQ3(L0 z1_lNO&^7^BN9qlz#)FFg0I{Kok_A*MLfN3r0E|$!3`iWBKsBa+)bbRcp7EwgbNWS1 zMvv(?-xTrGLleajkU}W?0*DQb`#VVN7f9?cNNmt-1gv4e11eUbdL@w9DoAVtBsQ-N z631h@uBn+gW5RUZmL_qb3XlvmHe0~#=}dp+^rvq0ug1vuAO z!Te&Y2XgHb0hZ}CZHgk(OY|58rdPBnN=!G%E@qj&K#!3J%w^m>z43{FFypD|2iLF* zPrtB0Qh;{{XhMRKfdMpKCNaHHLq&Kx&&x=j=`HR>q9UMV3Z0DtHD|UkGBD^v^d8X* z5a2vu4cdamz~D8#R-aLx@yYaq$;#r>IgZr}aJtw)mOXe)Kda9uKV9Kj9Lw}O&#gtK zF>4BN#=s?I4H)I8UnuipnSO)^6ba4p0-Pmq*<1rgc}9`xAJr6vr!O#I6q#O7?#03w z1aZL`14aSf9vcRR6`;^#U|>+0{&9hl^z?>CDHcX~h#DC~Mgd+ETWAP_7UoXBsHiT@ zI)jOU!4IM&2c)FH7GaFW^hCn|>FE~|%UKw$AZqp)G74}?*fD??4R}qzYRD+h3d$8+ z5NRGGMgiUyJ7{Ep)(uP#TwEhO-NuNKgVA96!K8BW=`lu(0-O`(;HDZ)!%$ROi z?Ik{ajS-^&V-AFUfmM@b`VAvS9>$#Mg*9H{(;YHpS$IM16Hs9YiUX*^2{JA$f+*sk z95X#pk5O0@+&%)SgU+kfc-FCWND26Z$k(J1E_ce zrA?dZ7fl$YS>K5=Fl>M*@%S7qpxYA0zyK;uK}zhP^XDK38iEQ9u>BBXo)`lI_w>eZ zqQbU1ERbnB=v*#CO#}nO9;kyrVlY42LX7~`5+FlXN;5F{PfsjY5Ek@6lln2;u~b@I z5H$1*ZSR0IFc?ptSSl?pnhaG976Xkwt1>VIfc+pFhvpWGSO$g)XnJ;?p7=gec)E;7 zB?s$nRR#u;=^srPg{RwiR0{BJh-F{^H4;GHcAuWOO-P#cye0!f<@AX|?@dJGH- zYzz$E(-#I6$+KpdFffEdG=E6vW*16KF44=^S5QzeG_i#4RNYu6EzW9UWNKp( zb*2iH?Na89H{FDqm}HwAMVgr8njA%ynBA>IU|?biV_;wr0TuR4lRzs9L_rCP zNhX|ufkhG2&|%s$z5F1f8RN0(>kcx;Gp0`GJH+V8=&?QG5Mu-*N`_`b_6I z!f49Gl{Ve}2%`(*w&^WL7?l}Qr>{7|7|iH4{m&7`V#asV3yw0HFtJ2WUv`vHnTb7V z`st&L#*C8F{~u*k7G4?3z`!PUB#nWAU2L@)0|STH_UWd_7_BAclNcC;#ZD$NFo-ZP z^#w67aCw3j7%;7#-g%7Cf>Ch#p<|5hhDXB~7_>2b#yHEnHD7#Nhqii{Z;l*Ni185mT= zO5zz9RK@x<85q>WHh`LYVh`mQ7&OFogfcK_ifxo(V9*llk!N7g789F(c&-U=(4@o*s6BF^lo)^n)iDT42Cg)w(+ms@a)J_p3=CZ9V2(Tk2WX1+DF*`scLuoJ=gLrIVBpGR z`pwS3z@NdD&*aI;z#zESg@J*qfC;3IK@ik1;woYS?eSC))K+F-;3{Lf#=yX!B={wX zfq|=>={PF`gNoqQGzJE)3XnDR45@;e<_rv6l^`BN8Uxp<7zPHe8m5mN3=I5CTn$W> zAWLjy7#O%3nf8GCX@Vsn-A!Qij0{|o0t^gX%}k-33=EPij9l$ZN8lPdz;-hTCi*cj zaCI_OF)}bP2@0h%FmQE&WjF+D>Os!xW)fjyVBlils?=m);Ob#&~DCJ^Ty| zToPc-41z1{85p=EnWup^2@9SFxkZW@v=4+s@HR+Bn%RJffq_S`Lx_QaONMz7Xg8{$ zstyAKmmD)F{6z%6>oG8J$uloyVqg$s;L`PEVBk_@_U2+>;OF70S7H7Iw^0?@Mm4C7 zV52m^MsYxl(gYjD#lU4J$-uy+&AbO>6f>6@vpF{dgCN-L=1`MlLm3#jEWo~F6#N28 zZdPCp69d;tkUOmFnc29(4zXiygzL74>IVDV0qTydSOx|zN3d=VNR&8%Ih+h!hddY< zxSW}txfvLECAeIfFLN_6@PXao1~!TBKo|o9mpeFY`7A(=_5k~u?>d7OC~Jcq&X=Ih zz`*4Nb_N62)_4X6E^p>uZcuUnnaA}XBqGfEk(+@*3KUzC(=VQ36rR4}45KKIEUPLH zRM;6LEXSkD>JJks0*QbXatbqW8ApRcgtZPPI|m|bdzO)h*_!p)bf2?~N{rRh^UpGh z*K3C{FmN((Ei(hTo)u&%S5pcD16K%?ZNk97l?P!bfU-h4n9a|{RmGaf%K%OM)vTbz z&mj225R|!CKk+ayunDqrGB9w}vU2epva_1`a_MP@1Y|1!d!UP6jTJ z3a$oLF1f~%X=j1T6*9;ivt zQ49=Ry{w?l5u0GL8ACk-S05{=)Zi41uw`K2>SqO&NC3+@9IEmOdp5C*Q9pae6Obvwu{UR*O+i{WmWiR6}g zu2~4jFmTO=xP^ghjU@vE*Bn+SJ_ZK<0IvD0d*QklAnE2>h^%=LM6=)%P%JElc!Yrq zv{{a832Qwc0|VFm00suGb&wcj=i12nldm2YK%1b(hJqq_GwVq{(4sJ|m23{OdP03_P{}i2N<~OKuPBis~t$UH`g)Nop9a9k#(Oy)_fA88REKA zVApvuaHWEx?lfyP$Ru{IbF44nCY=YHRL>yjrs9N2Hps+ z%dF)B3=DimJ`4<8SHKCL?;j|iUj-*pK5vlXYv5$Y_Z?J&Uk67NpNRzn1J@03l=J-o z<))jgKlvCK`0N}R7`SeMLy>P82Ll7w?Rs#?@P&YqSb%{+oO_5@ZBbuNGhqGXqzTHUk5fC7XvJ z0|UPdmo3{}K?VkaoRVw?E;}|*GGq`uoxs4rWzV((TuIrAFfedAuz@Nm35XqzU^}D) zB|v3`Q$3g`&A_!6<1HS}UDBC)?JHjCDfEX1HHVW#F2(V^0hzldZHnKBt6@kJnimd=-k~mik+iQ@c zGK;bqxMIOd7z8`GK;>T?+f2|A4}z0G2`8QnRFVraaEV(pFmNTX?Gj>O;FaM@VzU)y zVBkBU!oa|l3=VU?gRTq=Tq)pi;u8jymZ@MH_)deuH4PjDd~+E=?LDv`7`RS@l0*jE zcaVEHxU$%Cg&7zG>mxzNWP=k5gWxJqJ1GY&!@|JB0Rk9U>)|+yPfQrH@wt8XE z-digz5Xp8|7@DcR2{SN=fb$Kgl_LV;GVri~Eaf-gYGuO!h{eFe0y2hQfonF~PZ0(NK^9O^GY8CO z5M1EJz`!+^?Y{^p3r2z>WgZ)=D5%O61GO9HvvG@pnsNT1Ci((4K~V;VdI7;lph#WF zCN9drAR-tFim@eZvZ4$O5`wEhrOq-oWl;tO8BmKA+)$C^0X0{g!DJDbTqyt&X$F%Q zg+c68kS8=iO@|e1?IQ4|>Nd7qQ3eJvA<&{+u_smx9{R+?gOrwoSea4BT0)V$++iF)BsN ziGdcW^00tZv$Al;bwaF>FZtTo)_ zqT&n;Y%iu;TxXQ62eCQWN?aKjxT`^B4-Z?R4g&*sjkGueg8-XdA_D_=ElAvlO~{LZ zfxAvyoPoiQ&Cig5fx8}*?sC`!-5D6T8$s*>w(rpl4BSniQmBMY9%N@Th+VnD{^e)Y>7&z`)AE-BAp3=Zts;2JTLf6ByX^ z)EF4JyFhFvHh+Ew2JUW<5*Cm_3=GXMa~K(z7J%H><0j6)z^cF_Z9Lub2IF$ZzUdEd zFdE3diDh8mHD?4ljO(il0|RdKuX=(`Vmg zwB~A(096UR9gN}AAKYYAtv8WmVBqKA?Pr`K$-p4^Fr9&ccLLZT20>0U1_s`VVC{^8 z(-IgMcqf5Xfl3OH$Oy2@g(@-_7G`)ACF-9`fyRP(Shh@$T(hLj&g1mYR47~fn%0vX2%o!MX4}fJP1O+%17#MgDf;GtqN_#Lc@E&43 zBF(^{Ao#$Gfr0lh?)AkLF;UIk2C%Rxt)Xe z2BXRJjysG-dLa@F46K6g&I}B^cNya)K;3|aq6`eY_ZZ707#P?YxHj-IF!0`IyaOs4 zr%ZowhtZueV!FXyM)&#|pt!C9cbxf!cRX@YXZcfaZq;-?M|#4^xK> zsOd4wn1O+}k!gwysHhVFg+>$80vV8ndq93^26Na2y-XPxcw3m($bbUPQjLLux0PuJ zs9+Q{=V4&rZ3A<71h0aY)AF`69g$&R;1fLI&A`Ch!E`|ev=f7C1}H!~neKpey)pqM zNG4Fq<`v*w#k5YAfq}1GjDdl7HQ42RQ>WYBW0bFNkY!-tSK!^i^aJFJEKoFV1hc`X zu`uv%VghAa7Qshs3=F)RnS5kG#Vwl=0|W0Crhl@K;`S=2%gq9^fy)Hsi>*w%K&Eo= zZf7!)V_*;z044VwV7D*`P7Y^a;N8gtDlb?VxCCXvsfbBH4s>12K~a$}ujS z&V8RzuigP9%)@((=_<$^&@dtIaj^5DhMoW$$|SfDl&(%f3>BOz!@$6M3e4eP;QFG^ zz`%QkX}TN(1Fr(_c_w3d1_r)Tkl+O-ki+>*(ij+cFM?gl_r-~Uf%g(qw;TflpRpxF z3Ip$DCKeFqPBH@n?-dC99!T?5u#*_Let}ZzH73x|6c?xg!z;&Z464DzKrT{X4wq+O z5KfY3U=RTj3_L9Mpt}BA3IhYLCAh=RwQ0J{14d)U9n%9IFp3Etkq0H^Qy^WpK)M{J zmp@=M6wi-jVBk9fDm$3=f+F%fnE7@3{s)Yr4uvTU41DiFG0i0C#=yY$55$Cwx$rSC zCMz&7hv+)Tqwkt3&2u4pAdB~{91yaY$#wX6Wb-MjSMsa13 z90S)vE(QiZDaOeP3=I6-e6oy^iVO^b*@+Acd~%FR(<>h`8pr7>fD*R32?GP4GUHYS z1_o9Ju4ka8k2>Q)kTwlIO~xf4Z7D$v418M90&XqH(fW*6K?kG>a!N5U@EL+t@d$!? zynIGrWded*r*l1G^b=DB4fHU9l6)9r7Puhhi)4H{J?{~ts{0{DP(jR>z^J4IEr|IN z!MY&@F<%l=Daw}&Er_{N0vQJsEhy=tbDDEPnBT>D_0h2ppun=fv*#+2~x1~buoTa zh83)Q-HhL-2R~uds}E8Fr9)7N^04rMY+#WBlSjegOrSB6eZC9~eEp1SAa-dq0|Vbg zMo|?824Mvi1_lvO;$`3x0u2UF1`BiD2j#n&jG%ItYmGAl1K%8QvCEah%)r367#x^f zpR5=d_*OHXW|;Prk)3hNbdINts`V}^p!Ag>$-uz3iBU%dR&4WaX0%WNm7<_xn{Nwa zfC{+S2CduV+sYUNYAX7LFfj0)gc$9g%)r2R9?XVjjq8kDstgQbl`5c2krf9zR?ysx zfq_{p(SU)0MeLFf0|ToVi^=pgPZ@dGGCp9CGY6jv(+iMhPzlPX3bqnbg7T?>%QqGVt`qSL41DTLM?mTY_%xa9 zr!RO0E0Wp$QaD4}r^f#IIXfQBHiZb%uVXB|L>?LC;tvQrrt_dP($DPdydOJ!EnfjKlCu4LUCM#cK~+Mu&6`Er?EKq|^v85sET zn4uX+0~DM2%(^-Z42lwrd_~Oax}cLfK>eF=B1$g)&>~+Q^K_69Xl8-09vtC(Tp+_5m^WxJFz~IiVPN2EWCrB| zzAkr!z3{O=AZ4v1-#8 z82IKvbXS2&r-k**t3ldNfpks=5qhBM=l^QZ8czgdE(4bfs3cs*d<~@Z14tFv60je2`Db1#?*icp{?M#Ca#yDe7KVtJeI~4I{o51@XYDgcZ}-w zfAyf<558l}AafW5U+6F}@EvEC)q{0E_)aiu>VaxeQ1^rHB(td=s6YXAKlo08IgsuL z-)Uw?Jy6ra5>%|8VfF=0m4Uk-d}qNNQ1^p@f$to1Bq%q6dmntR=b2OWz}=51Q0!h{ zE(Gb4m1bbzyA2LHehIz@%qR3=3Hl){K}Rt#@I7J%6-8`K+a&nU@gGX2+k#z@Fi zEZ;k@Zc*@5EZ=)DM~s2%mNf$d-zR2KeQ-Yb%KRE+@Op6u2EK1#B@7H)NuU(}o%sq# z2?yUVW(@4&B~!8)sO(|^&6TprzXA=Hv#@*stutekR{%AN*jT{58%FsJpbW*%0!mCAjPj14 z1jxbi5Y$^@ly?9ncTTXJ0HeGlF9QP~7g(Q2J)=C>O*|~1#2~@Qz@;I`z`)1LVqyR~ zrjU_OfaMq5O@hd75`wxZOof4gPnZSNa|0FgA3;^62+MH;1_nhLMm`A^Ur?L%F(`^8 zSx$gz_~)P?lVSk{Cg0h5P6h@(X|TWf?tvP1GGP1o9)jE`%K{2c2CluJFpy^f?Hu5` zp9E^Mu%sF?FbJ0#GBAj6>N7BifLIJXV7s_fL0VN=xIhD|Tp*8YuuKN2UI9`K3M>&& zwE)c+_0^zqTc1Udoq>T1bObV=AxjCU{lx@o9vZPUfY^$lqQRI2v;ctXCa735VVMCE z2Q9JXvt|M1I4;nczkE)RE>|Z=uL}!@5d(v;un_|TG>=UMH4EKXY6*P9n^#J5G8Sq>gc=Yj;5d(t~Xr)3p69cO#zp1eC^p?+zN?IUsrnSio4E$Lj zuQ64pGBEH@0W-m)BhwsYK;v%wTN0*U_{^wWZ*R=Nz+~>nz`%b36bh_j{HLZFGcd4c zrZDiI76u)`%~lAS>^=h;Clh60k`QBH;6Gbt%)r2^&42!oF#`izUjhRI{{@gP2DVrq z1_u6%AbnyCOv^G7A$`iq>X`1MvsA^p8pz1u{HzKi3kP;{_AIr zK@$!9{ES*A(6%GL0HYkp8G`A~3=I5&j3&km42**B92pq+g&9GKpM`;IAIQI=j6aPT z7$h5+_{ABcLAoD-rr9OHy#WS6(B2S!Nw5SX0|&@0*(RXjO;8YWGH{vrGcfQ=F`Ah$ zFetV#@yjsI0(EsoL9I4fMvzLr4$#5da*PQew{Yc~fLi^GE)WX@a!X1X z_+7y=EDT)cpjA3OH~gp+V*aR?h@UOWuqo#?#+^W0dd)l}p?Z z6aBy{co?`onK3Z%`!kw=C_er`#>a3IgOE)O2CIjf7{X{WJ>WZ|q-3@+XgMU;W004^ z8E2R=Fi0+8;*Vquo8I)DQB?z!{y88K5(|zHV*${Szx;7v!#o6oY#A8%;~5`LKmVOk zn(IBt2`v1{jBV4ud}mY>OEL#Fr}+yRx0y3AK)h1KXfoa42cuN|By$D^#U)JqWsIeu z>JJ#P}34L>{ky?hkWbo85sB*z-fo?x;_I#1b-uAm^lLjUjoPnO<))Dxq$jY z&5WRGm2Wi<0|S2xIBxl#g1SzvjBTKWa9p23bNX$Jhd?K~uz=hy3SLhnU}R{;z@VHl zUGXQQfrDi#0|Psw@;*7xdGX4s-k|opvOQ=y5u<=+$07DNk(OvLCb;L>Y6OIVqjp;NGW0vSeg$yl!|SBFav|YGLSF_0}qR_E&~HoR~!R_z;cj@Dol(5 zt8Ps9_|2$Xzs-t)ft62SgN8NCgpCjrdU+Ta1U7+|s&laI1Wnp(=22i^;9|>HV_*>2 z0xI2k*hGaYv9f1B2LSOVFV#P9C7qkOQEL02r8d zB{DDw>;-9KWl<40uxt9e-;81rpdmmGHc+!i;4rAwBf@stm4QLv$S!LJ1_`!LybKHi zM?ogauqlNxFbEt6>6c{#O@j!W_$?1QV2Ot%(vX3H=?cgpr(&%c7+6gN&N@tw`NOCb z2QpCrV&X-Ri6U(8q!<_kE`jP82{zE;ErH9RJShn={VK?GDTwLUK&H!pHj^<3+yE8- z3JgsB!VC-oH&27?kP)~uVfvjvj7p3XrvLxLC@upsUV?##<)je<1JiU+Fh26OVPIet z5O{iSy3t=oC2^2Nd<;yV%^4U3UM_^lys!>mA4(S;h>g z1_j1_({=tcN=QJZ?LY}jnQ^8a0|P&ofI8#5=`sHq)woYV__~a8_S1X+Gpcg^0trY6 z7&C60zUM!qgdS+YABP~Q>nLCbu5CHN>)r&+!5l8ZpPr zQv3=9I`@GpgiKR79uF@jPNhoChm zzRJO>cmz*!GcX8LFoN2~0^lW^0+rwrQjmd%r5$8=w;2P2Ko#Rmkl_XbwTvcC3=9I( zdzhFMRY4!x2~VshYe0F`_q0=MM$q^#Bs3O7jW7WfdP~6G zi=5*1ALU|Y)lsQY#`tNVg#+%;S~gp-3$B%5B>9jr(6a8fXDv%1rLF8 z-d{$LSptH+plJWc_{0sg&YXt@G>^cw8#JNupD`6=yodlNlL@H!1bc;x2~v)MD<5vK z1c%^#bp{3j9;PqT*ReD4s91p%Gw`q^>VhUSwt%Jtv;{!rCDS*Mc>)3gOtsVRu`{Vk zfK>7@aJ@-pU=R>t@^J@;v>4Ns>CzlbMmpO-w?ly^E(N5Su0Rd_3!3+c=3rnDkYVZs zY2Xr&W8(6dUdh3v%JmE+AR?g56f%7U2a~EcNE46XY*6A-X9@u&1_mA$PLP8(f?TY@ zB<2COQio~D^dB5d+6rK$22iD3RUm5&nbJUtWCV=(rxi)af5NnH1{JfM$I_>$DgI zT$n)7E-DDN$rWl7SGz0&gMb^8gC}UTTfl?qD%@O8sJUSEUSRbc3|xyr^4?4vLFxqr ze3?MYPatK6A5{HJP+a;m9Z+Fl;HZb#768`G!@#vwhk-#Lkm(^rcQBK`7px2jf$9d^ z77A9+A=m(_;lseHco=wC3P5Wazos!T2!u1qd4U}q$iibct({zw5mp~R1t2fMD*-%44!{h=v zOjnISi-WklL6+t*Jp`#26Ub-EoW7Ww$+f;06xXHT*(MPNu2Z0NRmLRf4bFp=Ot;{M zRzVHb2h|YOOiHSt(Y;Dg$ks6FsWLEd3NrgLFbLE#eO6;&;1YZeS~FG$*3Tn26BNz$ zOrW)#0+7&c0EdS3_P(lO; zb30h00BGa`q{9VNeEz{3I>k>&acN)VHnoO~D<6df1^rZIK+GcZVl z)9ws#K=6T1T@{$gv>G&GvI|t)%x1a)VsADCEijwQ1ZrLL{Qwn8^O-U6NsG(YNfAd;zQ7GI9ov_$8jc5n}Y8wD4CsLssjx? z#ete?Cz(!w*l$f47z9o+v4W-zK!<1woM!R>v8S>!FbJGs0#)yP5A7Kk1kN&nsxv-) zP$hAW2~-jDse%TJ&ohClQoh$9M_*u?3L3vttp~;RMJ7-M&sV|@Zu3jJFfi~f12vs4 zGev?XysAMxiYrX7Kx}nG}@b0~i?A1VG!&Yz$nr{tOHPYRuUI;0}W( zGgIJnZ$Tz+?j0b3Q~@()qrmA41)0RHi~>QYP;)Q^GB7v=LiKYpaAn$pYAI&EKn4c> z0s&j*Wq}L~g0`Tf;|69k2=-0?B*^4izYV5|iGk}hsKoMP_6r1c2UrC{nJ<90o+$({ zFbIS(gF285f;FJL8qN%IDvKbv^Butq>V0p3RG(4Ipz3prV3-vHgFrMhsO;MzxDu2~ zW0*nZ*&e~?pvF=xGpGJUd^O+A!pCrs= z$H+JRqA-&Z6Sw;Gufj}<^^%|jP|GaN!oU#1A`jZkCQ!!=T2E8LBEJ#TP;Fp-5X`_( z!y*rk?KW_1%dpB*(Y}%yG{~F6C=VW6SOreIG8pBPK?Up@uv`wKyz2B9qD;y4 zpgnp#ET92%9u`o&z*P(?Cw4IZ2?n>kb~E#Yfu@N-iDeJ-VbGZ)f@?vg#9pvDEP|k! z4uO4ORUD8Vfihvx^vcA*B?>Av_cPxPg)Jc#IK=E1#=sy3I@gdvtV&_}DKREdwwWM1 zqNhIW?fK~A`3*2PBI^A5H$tY!M7^o=*idEIit_%!JZQ3=G;|Qy3T+owz}=j6piCps_0#ZqVE*^TY$Sx)KZw40?=Fj0Sp)(I5c^2CdWK z3=E7b!26mq-Byyxy&g2fGM#~e!3@+BXH4V=m5k3A7#IvP85ooJLGA=O!u)v{ zhG?)) zrJ@-av_TC)#)ZNWG7JoiLE3rI3=E75g-c{X*Hvmy3S(ekTqIlok_*uXjSn*}5(dTS zQ$_{`ZBT=Yaj~$S1Oo$Om_cy~1LIO*P^hsnF)$c|&a?x&0<~!f zJye=0NZKr(fq`)%FAH?HKIjMx#yN4(3=C#pryr7LQkLO3!@$5`^VXk%fpH5bD8NCh zJwd1RFwTjd&M3nq!WcbWOoquX29^xW-fA&0Fzx`W1)V=+t`rVxGK02tGB7ai;na#@ zV6d4Co$}-9Dfn*F1K+{kMMB=Y3lT5w#83u+qaI+W;L32&!XBZfELBzmW7;JkCqXC1- zJq88_=QA*y85lU;GC@2Gt_GwTG)~8Y&W6wc4P}EfBFNXElbsmnNG35b=!5o?GBOE( zwx7&mVPJ4bs!vH|U}O>il_Q{&Y4kzMd>NSpK)X^>SQ!``!O4k50F;~iY#UyC6KdAU&R21lqgT^H2wq6TRO#WhHV6X?tf@4vY9egz?SQ{u6 zfzBmh)Dt)i)8@?1zyQ{k$IifD50V9In+ZOV0IUmiW;UqgV6+kV3DdP5rt1+%7f2SY z3w-7T#EGD5024rY%TYkTJ|5~uZ4RhqVH^w$_8@7nHqae~FrP6(jxu0$6G(;Wnh(=; z3Zx6UN`6Ka36Mlp%)np>x`PFjt!6;Pm?s{q)nkld;`qVf z1iB!Tsfb}CM267;R=*g&1)XbihJoQILWIR%DWt{t1y{bcAVg z@?>OSU@Bq|N}S%W$Ru8`od|XVqcco_@l?>|l+g?fhD#V37(h+}Z7kAbjAEX667Hk} z5JNJcn%!WUoxVUM8le*QFbP97CI*I-GYkxiAu>$GpuEjoG+kARiQf|x7~A0z42BL& z5SuSS#E=5RFolVMAv%VE;Tc2<>}SwvYz1c+7+8{~*D5h-YImhFFfgid!3xF)pkz0v zKAC|*AGAV}QH=|f^L}$OFz825zo^7yR1YgA!RZ@R+=2=XMkB7RNzjA}I+hZgD`s&q zFxZ1+!KvUV=o~KwaA68MHyuNkLoeAtlW+uEo>sRG8%9-ZtxYV_;xh#l@}8!0?b8n)BW< zFff2a?iQDP3N#oDc%UAN=3!v42g!mx(*`;#1(Jp07#SEqchoRG;R=Q6S_;#30i+8g z3)aP14=V2=+D?JGlAxB$C$4UoHVs~=Wx>1*4ECUVjltUL5W1|G7#K7_x_)sTgz1_K z({%!*3nUBH#Rxj?3t|`O2t5aou6hCP?=Wo&d{E20`4|}NLDFDtWe9B=%nS^mJ8~E$ zxph;a;V~7a>i|d>NEWOMv@4i_0W>%WX~uv~3j@VmRw_7>AFcfYD~i5q!Kgzq8gKoAxJ}A8rT_-EC{*z6q?o)n4k?W6DCN*Yb(MSe$G;8 zuDk{^N?g^c4|Eq)5yJCP*jCVDK|RJOEVha; zLv00}2MBU}SvuVD{G6b({Xl7b`g9%*CVBl0>0rk*+Q3VeMrH_TH7O8Tp-mBBV6X?tf|JaCaH}6&l7LQC1o0R-xKuKsy6(bsaR@RnSi)3*bsB@t zmt-)^U;z18j)B2G6C6O0(mI-{hzruZ0fk1?^sAaoT8u}gX)#HP&Ci0BhmGL!&`pqm zK|6Z7z7~^_CrWt;Y5;;(?J#z531>mw(;*1;#b!YU278b!*e!1$ZULPE2&xrLvcR<> zCup`DWPj-NQ(8_ToK zaETqR&Ey0xx?H?6K&^8wkXjdTLo1jIRPNh4XfrUx=fE4JpjHy-RJsMA=!oSi%7%Jm zrx4U5PlOm4>_M_%kMIkF+Hi(2k4(-6I}_B20JTUB^rkCBF>y>+&|zX>1$k`CbWI&5 z88GwmbT1tyDX0@9>26F1W7aU}Rv}0Wxoa$lDwSb4VXRR~Q;55yA`%_8@6+m^6dK#29ol z3CQt=pp#?&o@QXs&V}UGMY>E<;2?0Feo&W56jC068cZNXHBd#}F|NF#491|FLcoTA zE_VURAI_bg2G@2Td`SBGAxD5n*7kgsA|BP(Mg5L?@^l3F0wkb1UXU zb*_WztY^3h(h5@o*2)6j#thE?pyQ%IB?n^#cQi~ZXtOrB{oyCdz+eee0oDoG01eg& zI!6_3X*Ks$n9doZQ0E>7=>)3)9WVse3OWXjfx!?|d+$HPz_2189G;9G491{nIR)w- z@UVbJ$+b8V85kH}fg9MM<`Lr@&H@Go?RlYKQBd!RF$fZXZ#h6RykZOthM=kwWbA*a zu~rPmpd5JWj11_OCl=61yw+6Ear>Zyb)mPO%}JWR&VWhM>SQPbg96A9P?HK|NJIhH zZOmK_j10!0O)_BDX?=?WHC(_Q)8F7$-mK}2hD=_Jv!?qPGD(MV`Tq<9!*7UbOr;DA#-JlR!ATLc?GKa`?F%6ZZi69{g8aiX3=ENlV7r;X6&zD3 z8-pR}G8~Xh@$~nGOroK0&oD5w!xb?Yg97B|83qPp(6vM$1_KXEd;kN3%|1;A2F4}a z;NevU28M57C+{tSHPn`HgLIaNGcY)E#!QbiVloh)Rmi}A7`FhO!w+(z#q@){u42=- z88Hb%I=Qvb%u)@Jcx%KY&&qn1fnn}+L1QLa#-!=`#!Nblv!=%wGdXDso@HQACRsp`v~Wnd@=%SMB`#xcxXUl@jAr6!2ep_S7(lDc8SJNDFlAEHRjgoOfQ$r* zGfJ~EFx;19V9)_=B4U(e1g+d>o;ac2ED$t&C&jpQy0RIQo;GOD2J^%v_28n}umV<6 z8-osS1^XIw1TZMVmCL4YJn1Sn-9On?bh<++6X)~|W=!nKR%KvEF?xY(B?c!@k<3)Y z5C|0p4VQsp7}PcZ)yIVpaY!cv8j}vJ42GcFzP!&eFtkAAL0Ujf43L&3)1}Orr0YS< zePCHw3RuF(V7QF|()+!RB*Vm!%3uhJtgy2T3~#^^Q6Qf)7=B@3U`RU4z`$P)b~N+E z$@Sn`e@eX`V+<%17z|k%85nZUGB9XDlrS1W6>u{cib18Er|&ms5;d2x5S015oxeOk`wWn0uCiVcK+V3nrPwm1h|k)}m-OEM{b2*m{Mf4UC zQ0WSq*#I{XKsq5o2yPJ^Vqjpn0BRAO5@D-^R$Sdu&^lzB6a#}jNETduJOm|ENS`W_ zk%8d_NY^tF8<;KzX$A%hZO{mmwlo8SJxCg?Eew1dF(RLW#zR4AymGpu6_eQXkCsf5 z=4KTP484_b4;yANFff3sfkhB8NHs78HcSjEEkGu`1esu24{juUgpPyoR6$GujW@(F zaeQYm23?~7GRs(<5!7U6U@&xHWMBZ*Cq_`UB@7HEARmFsJx~hd;$#9PQLY!v4AAD- zDp3XoMkR2a4XQsF=PU$;KX`OOsa_N`yih95zyKb62aPLE02>_5{FyNbRBjkDn1GhQ zgCZVWn6xr5Xk7%=WQ#ymF$3t}XvR6>)v%&%5f7wjGiw2jHZSD?$t;v+U@!)aK|Kbg zPEbO4f0lva7swuU=o|zqxLRZ|1XZ^n|MFIYLxRzY!B~%hf#KBj`PNJ_ynm}181%s< z=n=+;(@$74sVQxYVPIf930?#kErVSBz+!5}bO9SCP4Qo#JO;XhmF*k@gCVHw1_jua z=>axOqO3ya7#Lno&$3}MWDBonV9+<2zR-p#M{A{o33liq|A78dY~|h@28OpaU{^Cu3}7$@1q`@Y1RYokig1S(P?xXA7|S%#g~6BsS`-+94n79i ztWpQ5fL5iu@=jlG$HXQHYNA@yf!rDc%Fl*fj1VIurk}H8l7_T@LG5mk?tZ9lUVA2C zh>RJubAAjV!!HavcN^?(IZ!9|Gy}t5sBAS{-xsKiNj=CtV$(O41(Fj? zG+7xKe5T*9XOgYwY+zu}e`5xkapt_h$-r=0fq_B)D<}mraDo!}PXz`BNRNY=6Vl^2 zP^+UL!oa}D!U>x8WDIhVG-6<2WaR`kYQSX+Xbf2bbZ$61=i7Q{*&?L~En8d_LBrHc z3=H5xqK+Fhy9J5Hi0SnXOiJ~$z^$d1aA)o12RUo5BFtHP`9aP)tq610e)z->#90UU zA={=52CcdD4C+I>4P&<|}gf+JjYL}KW)Z1Rl3=Ebq6=1Jt zftJQ2HTq!fm?e$VH=b}6o38A{B%}=*$2r&tNC<^#n50!fB|c<83N(ofT0Eq+8+7PLB&b+r_ytaFCDVOf zm@Lvjr^7N&yijXq?8v~t7{dvgnMqP%U;xi?f_fvM3YsyA)4PQMGRN7i0-fXBufo6p z+9ApSQURXp`i$mlkam!-J6fi1yzDAAozay^q8?Px%xMAnI*O@;fx)m6TAS^Kh%ryR zRST*)KxG%WQZsC0U|?uyVqmxgQ*fb{!EhP_0|O|byaNj&5(;Qo8FYsyD2fe1aSgIx zwH0g~cyMz1Ze=F!>5E-qB@U=P2U3&N3W=Fpu1t~0vBo-7_=%u2Y(#__4ybe zJ+YH*3=I0*8;``W->0jHN}W-dcP z24m2+Qjm8|KwUC$iWZx0@6IGq4_bPm#i7r@z{mxz&Ox_FGtP-RR#v| zq$X%!E&-Ih`9-zcp^?2@6&l&kR6(;?pmGB=nJop1Sq5X!B?D8=F)$c|#`;0+8WT{B zH2)mPiP22cuemcRFus`n-JMCR9@H)?R%2iQcL#oS!ny>ke#h}UB zHZ^D=vQdqJ!5$7)dNPSkf9%1e3?AQ^Ii1^+NnRaPb8Ld>hSY(KE)2%)u*z>C zs2zNof#D}evnAW=a|{g1ozo|HGO2`sYG0>Lu(imwFK8C*E+YfOwsQ;&@la{d3~&sr zR07@hbPyDhpb8KanTDXE1mubNozoj@nZ%~cc`*sqgZ#V&q94*uT*Jh`0B#fRgbrX| zhsc7{2RQqfoMeKu072yesNe(-!hvD{+;kUV(0I|wz@YWd2{fM%9t8p4nmXr44+Dcf z=qP8#Fb+`V^IMI9VfuP6CJx4v(|33=$p~=t!XnWPbT!bl=})|v)apS4pdgz-zKdp> z7zk=VObmdIIdw9C)~7KrFcxxL=zAbGaz+exOwQ`mLohk*Y02z!y*TjHB5_G9EC?tKSJNht*P2cU!qzuVv z;2PjG1H&SS1d|VwAw&YyR|DyI36ik12i41eyFrl}4JxsWTNxP`N?I8h3}-MhFn}iY zC40b<2+D{95mpjwc3_}fl&g~RAPWEY?0`L zbp#~XAsqp5`2Z4zbdX`?2vB*f z0_r|6fW~zh=bQ#vHW$*(92xy!36i}dn7A4%6uH(<7 zlPm@b<(HsA_Zo1;yQZIk!2`T5;w31IPiZhPc!Ik>uR*;Z7EJ~QFJB=B2F5p_vpSe2 z27rTPPd_ZTAx2O@D;PlW5#0|-Vi)|GnfAD7#sRwnL`uib41zNQQ2~Gw?ZxbqK z#b6Ao7C;RK$l?!>Mc`Dz%b)>rsc9xZ0|Vn{&@M#=aj^S&CcuW6KQn?nAg&2r-}3kz z1H*5Kxm=*OzX_<;`8&NgfJv736I>Gu)5+=E1DLY--h)~*ASJ)gF)(bNt{=!G>dStf zfdO2)3!i6TxHbXoex`{5pa#LjAO>Sl`6Yjzfx-A70|SFLh@r#Cz+ir!fq}vF9jK1= zWdenBIM|&BrcVrHl5nh@2%E`@VM3Yw0kz2GUc8ov^3(>0?h)0>O1G@ zuL7A=j6r?f*%QGI0`;h%EjG}25-6%ct8UgqWWhcMjRreUcMM{Zm3=b>7F^j(px_G9 zf{hsFGQF8z9mJ$wKRJzofw3IChWCaRw2u5V1s36Es_6_2j8nnq=P+qAFz9HRGB7Z% z1)sFTG%*ZZK7uCee}Mc_%+xsv>K7ets9(ah85rzAvfxs67HDA+gPQ;|1B2dV@XEFn z#(MC|!6VwxmH=o_%>p#j-oSJXWEyCB(<6{+prvh~GimHWvfw6PC@2&e3_MFmQ z1P&ok7#M?!S5Q%C@)cCsLZ*Ud2Q#VE_du*=oDH_MUI%Kc4$#g#zq%vOo1)~ zgRwnG8tnQdU~>#XB&Zy}JsIYD(4eCcgCS^k4I0 zJt)`QhH5EdU@!q)-v|L3$nRV>rQ0LWsyL*S%Z z08+04D%=i(`TO)37z}5E#!b&NFf5)f6vm_knR|YMi2slX23#5o*7hvNEk3Mn1S{OF)A{H2|FoVj9paRif07_2A10+ekum@Q^N zOOV9|&=TaF0ce33DEEO@OM;d_GccGe0$qFsZtF*ZhOm%Ug_wYBgZ4yzM=&YWgLg53 zmKK6s1g>2~88jx(U|=wn1eI+LV9%}qd-lsrm}ecpo>etuU@!x(8gya?)xN=ou;Sbq ze6SVs!~?aEg@Z24poN1qhR_uXpbPX)fIJkyY+y1I>Z4hPP#+yNWMHrdNrTJ8f1t?- z21C$tfavoK4B^vHMKZ~;rk`hEsG9y3!~`|NW=|K0Vv;cdE$CW56B5-$3=E(_a0XC+ z;S@v+zM$(nBr|{(blsbt5XEG~J7X5iYlX}wr_YaKl9z#1NQib0tdUhX3z9(JM==Sr z7N2KeXr0a;&7_|hJez?*8{B&628R!0kj`~;1_s7n@RD>;7M%`CKYh%g!-NBkpp%vL z=NTB@&w@A_)ENN{oPr$9F&iQVDyU)@Z5Y67O}o!CFzC*nK0lgCp0RuS{%9sext$T9 z#mC@i0*#C_&Y1ys#%t!2)Bi;?Nij~JE*Zll8+HsX^B?L!W6-F>VsIrr7qo1d4|IVP z188+L;~efeFz@iOfYLT&kQwOa4MqVL(9vz6Lvc(%3lY~(?}=fO)rf(sR)VTFC`v76 zU{qlNC5;_M3=Ae9pY5K0F@{Ogt$Z#lyjOu$UpHc4FaVvR!MK(MG;qgk49zF)b7A?! z7&MIv&bXi}=RjHi#dL>QCd+#8ObBQ|_&BJAk_jEN=bH-&zETDTCr~qrsfa-pBE)C{ zszMAHz@rzSkhTPi$AIPn!Q&F30X1K+SQJwk1B2mJ@FEumhBUBPG*giRXgJ-4!2~oW z`?nt2tphcHz>Rs3lffB@pFsoUPtyp{ecHFdAq%?5mT`{IJecoqgMF`P%)p=n+WN(K z7kqXT)5HL9(*YDYpu0O6AFzC%3(Y3c#?WliW(;ZuF*683hA#Jk#`YPELDR{Xrgz3M zsq^y9hsB>3>&fYR9k|@NG#?gR<*cBD*kS_f3RQynOHCLUAgk`H zSYczrh+GS+R=Od!L3$_Cb9!C5r=M?d<*8>d0uAslM3M!STMWja73Z%&?O4#LAGiwz zYF>c6e*&Tw(#;2T93bv)2DSZWgYHXW04)n=oMX8F=I+^GckVDj?y^DM#mu0;08;;~ zOJEXW{5$<%0+X19L2VkatGd8R@694ukbDMP>;MZAkOahCh?EA(B%mPKzKDTg z`etP&;psZbOfvOnAQr-10v;>}^@dGglULyK2t3!Gnx z8^i|>q@QIyIsH{Klb&L;I0FOo#0iy|++9JIie1v>RI!yME-^q$Aa z03H*_o_;QcNkaPDc~C4yvzIcMs1!3OF)(-+GBGfK1~pbpXG~=huV=i#z+eIzcxN}fWZ*7QqAxJ1H*K%JZNkSROJ{j7&0<4Fn}ahK_oz( zTu>X`_5uUL(diCpOky73F-H&RBKntLWl_u%=T(9SpnfnI&^d{q`H)J8 z93($57=mv02IaIqh%h*(8Okt2hS63)1UW!4%Ju)h6oa7&bk*$9>2~Q%5|Ex;B6QM_ zbvYzUSEVySml}f_!XWnrLuGcQGifP;Y%@LsHOCk%DERbQo$Q58+;9)@U z(5@lq`esnIkPDS5V_-0rU}azcWmiL0Rt5%8xb;FLVd1973JIb`5Mgk*8RxJ9h*#Iif!EF!F?Dm@#&<&6B;L?^KGH?XSq+q@vg9b>2#+&K=nM|Ul zaVud(iX(cF0^a-t3Rd@(5U+8lFqmk98bZ@=W-=+)Z-Z+M#i?~ZOsff0>uHct(BT;- z4ig3j)8n8%MkctF1Fg?sobv>3ZYH|945srzHC8o9bvRyn0!E32O{t;dcagG6lA!vFRq(K8B1knJRAOUG$&?uaKAe%`vUSTb)thWF+ zCnYUmWwsRy=t@eai2;zdwJo@99c&4$)*9TQSF@VAF11Kee<_ExHF(4BRLH+r} z3k(b=rd#B~wlsjoAVGo8zjnG|h^yH2x?CnD50GJ?Tmu@Hf~=0p1g&W92XBsn3{ZBi zWngeFFl1ot=LRtukrw!YMx;PS)~|)Q?{6-XaJ~6z@aj^~^_!-tpnWl*OXnFFK%*6m zb3)g_5@`uIeqgIs%fY-tOX!-KTu_n&rN_z(43PCRpw#eUEhuC`;Rjw62uclqAwrPU zUekPWZ|+zB4Gma&57r<4t_{A4J^z`)RYfq_AN{qzO- zOcJahw(Io0`Am`$6E83@M63t<6;vM@fwpa)XJ9Cu{w|+MA^sD;vY&~)Wy$G~6-Qvps}g`gfAr1|E|#K6!2a;h1R8%!tY0&}oa zciVwBk3gJS&%p2ntPSi|W@ZKk@BpSKPXkCB$gRTmP`3uzGcZ`fRDhj25xkYy4m9+s z!ot9?0Ayh{&o-FO4KSTg>_MA6Ko)`~=p{f6MaXjfw=8xH44{O~*v<0+qzyE^Zsq{> zA?P$a%eO2L6<{BhfwdZfW;H;gUV@uJ8(qYv&n;%+u+-WNPKS&ZprwQ0?NFeOIcTY~ z9YhAy2?VbO0GG0$0Y^|N*1Q>#oAodQ96F%d;5tM(NDU}`Y`MU|@ERfnvd>8gvN4lo%k;()CK2TW7Z?~MwtyW9k~RiS z2!Ndf+NTL}PQ(_7bIz79$>^K`m4l!a(KjwIFq9%`+XCA#b_cp9Z4XqNRw@eXLb@dyh811N((f{VezkQua!)9@k-0|Ure z-=OlK;l8^p3=E(_XOV5wd&`(4tU#mA8rvXdf(E=Dlce$=Q1opFxecNkR7`?ZgDMwL^o2rIpDkyS zG~~F*z>tYhZ3tRG09yB10~Q0-XvUzmQ6K|Mc7Tdk$UKy81(SHh4bWmxZLoVmwKC(J zr`tg#9_U~TZGKRbi!lg1bSVOAEtt*$HT0~(szFPE80SdtfT^~Isx|?Qb}3w(KBt07 zy50^h?G2S?Fii$^{U?FV04@4voYT1zR&-7RD?04}8J?d4K5K&25xNcwbYup&e4E3+ zW(RcA!_5&|W>h&cFj&G=fXj?^j^NV|5Q7Gw1{Wyk9`AqzbYdlJ`I8qYOinW}NbQ8k z7<9R^O`liE#0yERpz{Gh8Uvxy=PQ}S#4~q-Vke5JNDx%X88euGHht(^oc^bhN!}B5 zw;}`dj1QJwFyE~d0EOpSM+OE%P~*emA_K!om?<2f+1(-m24j#9!4ZXYW=B;OlZ+PV zcmW0mP>X|cP95CL17I^jdm6wSE?h1$FgQ;?PzBrZ2ue55IfyS+OfvP?LF=0sKq0|6 z=i)9{)LjP~!WaZLBH$te!|q*B&w-o;IwAq&Dv$)IF;@f@v}Ry1-DCqA5CB&%=87-Ok(wa!DfI6#yOF2GyX!& zFaagCjEgWQF))};04;0a1_dGmL{mFl6Sp8JkQsxFL7GayiS{^XEHz3=w0kn=^2doP+<^Kwl)nB^)q{ZlQI zaQz;z&(4B2bq8>7cX$P8aI0tqQXx5Bz&Z&K{kUR%=4`YxCXzk4daJq_R zG-qHi1;sC7u4c^tLafyMU`T#iYK?B<0ZH?dz0GgHoCFJQ(oS1~C>ohXS)`PTy zyAVy8CnE1KERBW0;v$4W5m)2Nz~Gt$ zIu|HX7<9rv^TY-9Ixj%GjG~1#Btf$Q%j$J3eL$XgE-^6J9R{aG z=84Pd8H_>Bn=<`EGm}(8IoJi+ppM%d?jsBg4&cMW%7sA}^lfs5ol{i~Ij1UE8@zy^ z0_+^d5VM=0rF~VxpetKIXRCoO>V&KuhOMakdKgj^#Wqc9IDLG7!DSf~oNun%sb8is{VM-e^*ZSvj$vJf0u!W!@6vjEH;TGCJEri%-2e$8s8$&%bNbNB!+=OHyXxje>$U;yQ!Ynjq zU@-j+DpI$DEd=efW1KVP7%aJN2V3~d4Z56jC)h?cci1UayTIp~F)Hgwf%*x1VAdmA z)v%=+!N(w}aDbs)3ufSm(svNO){Iu3Kr z9k6p;-J#C82X;;&+&T9l&Vjh*A*O3UnFCZn%N&Qy2+eM15~>He#^5;IHQ@Q9JD{=* z)WinmYeP^I9+VO$f;w-1!469X=PH2{Fo*pGJ8TZjVgJDnI{|kXwYksT85qE2$CpbC4ACdR9%ltFTVXH(&EU%RO@G(HBv=0x zY$B+jWt_7DZsJ#{iQvX9!(~t^Bhwu^EHZK|{D^;Jp;C z1x5^v=3pjs5$k+#7=UU|!$xQuOZFt#Nz=o-m;|QJ?u2be*a(%5o*vl6BsTq0CzDhv zcs~VbRS0A+WfU{l|No%fJfM4Pv=l+(rct0mlEI7-G!?t$6l|w`l&GdL1B0LkEcT*A z8!Z?Zj69ImXMtDPg3`)+kbU})SOWK#PBSp5or0w1C0$Iyrl7E~It6w!cq|1pe3+8M zz+n7>fq?}C>{;vc0p z)gM2_z`*t&3^dvp85sO61sNEaPBPsGiGzms7#P6f0R@Q+3>?cqjq*Te&?&+J%%Edp zIY4_~xKG2TqZoqTf~I;F%AAI^X*7PHVqgeN0iC@2fLZr6DEvTYZw9^x-A?e3x!xWu zbTy2DAy5)@)~gUpAXsFTA_GGp=xyP0Iq01-Xld^ngoCesFH)}C4fH0RLZ|G$q1_lu3U&9ny6U4v(!u%pE!C46m3?LlpmcYOO!or-4 zp&P;&7(kephb@$un}Gp@Mb@!|eoSRx0Aa2m&JgxM1_lrob`QA|#lQf%jCmy-cb) zAjg2PkYwmGeFg>)=C5T6(FkQ=0AY^jp);Zw7(kdSXZqV-CMD+pp3s{v3=AO5Rmv55 z%7K9agt_E7LP0G<5awd#4(;(}U;tsRF7^=6T`eHY@hY@Gl!2jtdQcyemgu%r1_lu3 zcorJQz`y{)Tnf`C_Ax0l)=uBr$D~+q&mWqS!oUE+TzC0GeK{ByK$zb46oFmUnlhg=O|U;tr`N1;~~85lsAe>PLd zEhPp95a!+;5|+Wh0K(kQLoS#wFkCQUsApjJ4fWPyU;tsRr<@@_SQ!{Vm@zr@LL>tN z2y-Q{hwhSMU;ts>53Hd(A{iJ!m@9`P6m-T82=o4B4YgxsU;tq*CeF|Z69xtl=8EJ9 zEw*A{0Aa3=9HA~Q3=AO5b&w}?wLb&H^eg>Lg7t#Dp?g#q7(kdSn>Tc)9|HpjbJg>P zb|*0~fG}4-Z)jL70|N+iE#?VL*JEG+VXg??(5Pqz1`y`j#T#lD%D@1^Tt9e2gM=9v zK$zf9R>yv=91$N1&y(TFqbZWXrv|s0|;|Da)g4W|3H|_jXl&`nt=g?xmNRreo$dx z0Ab!{=FkvR1_lu3Enp6{0G%#6{n11wZPp733=9{x3r%8TW@P;k!@%%iy3}MQdD({% z3=AO5>&+4hTFwr_ys<2yZ=)C(-fj<@%v7T`-G)bln-8?ZhnbiFf+DnfBKP0hmrC1^h9lD(dl_H930d2KQoE5FIHz{X5{3b?!d?+I^EBp zlx=&)XQpM0j7`(|zcSe~-kRR{jY&j!y%Z-q10xF)^MzC}gOT~@^b22^M5cFrWs=j_ zoXW|>z{p(B$;JROjERAfg^?Lk%O#K&3yr0ORI`HhKbUUtjY-6I0dcCIN^vqXFfu!F z@-Z+n+k>3L!o)lq)A10qUrk@}jY)%X^7M=7o`cALn*QS(lafXcA-h3g!pQt8t-TrOOF2FFe@=_(wyF? zT`D!bn1wk>WO5AH^^DAKmB9=q<|#4L6$F?i8Q)E3W@Qc#`x(v24>qk`1*+gzG$+?| zM;>Nz#_s8jtjxlUi?&Z?Wq!gkJw=;YNQQ}10vvU-(l}Yb`kqNb_03M3-WbOv$@qNw zK`v&w=>^3OJku92S+j0`!o{q~tkk6iicMy)<|omdykO09V3t0O=46{b@e7ma^bKo- zIaubZa57C->`WEjp3KLb%)+>0`*9)W0!hY|(=BwE)fo>=PtajjXS%L9ePVor@bo!4 z%zTWmr?1vwR$}}+{hSW77*n^>^z%B*qWZIxptf>?b`>x(u!46VFt33NgLe4Ch4)R@ z(q-0Tx~w!kKuJTC@!|9WU1oLmuS$%}%$&^A3j{=^8T+R10x4OnJpE%bhbZHwX?n~- zlIN6RwtxnO;Kn^vo^GhiEHYg|U5sP8!^Z@+=?mrxu}q(+$E?lxclusEW<91UD%1Dr zG3zp|fzpSe^evU?|9?h^PVd)e7G!)qeW5TePMNbk>PX zKVZyk&U8y_x`Jw{$n^Uq{v6vyO_;w1^CYH}#it~eB*y2Y=56QfU{*4f1Px4rhAcrR zK!HYtL2S_S4xZ_Oz1sTI9pnvpw%6}v-r~b#W-$GscC|RGp`od{>GVJ@7D-04>5Vfj zM3@bY&89Q9s0p(e8X8(mKe)aW%7TfRPcL+m0E?MVXWRslHJhHO1vbpk%yhaSH;X8v zAxzH5Xu9FLQsL=0ZG8o%ztyhhW-&B0GJ#rUXaG}YU;;DNz;OCRt!i-=Ljz0m>4h6g z#aRpu&5dAAGB=!VXi))jx4EI|bVV(95hhD>kZGdKmN2_5r*G78mtZk8wltY;C@Lkq zeIgHwGUN1rQMK&T3nF=?rmwoqAuwIes#;+?6CcYh7RFiI?+UT3Q)03-nci#4GLy;D zc)Erei?)!VDMNgGT4`Q#e7uUGp}C4bj6)M`9nHzR`(QJn=1(&@Uu52N%L&ib!mAB(^RR+Zc&$iNto8uIbF` zE;$WJXfYCdbz@a#Ts(cD8>_hI zJ|vk_NbLJa>^Dg4Ur20z(Dr7i1B|CLy0eN)h9U_iA+Zal8@jV9*Uv{1T7$&ig~UFO z#J+>Xeuc#TkHqE{Km?*V5?dLGtq);CQj9f(0}gd}Bz7VEKmyp=HA_y~` zkl0a3>@*mA`bIBS@A~^NE&~I@8zijz(f9BC*qv*m)2( zBoY=uIN(TFi^M*O#J-Beeu%_=i^Tqk#FiIBgoPFo+Z2iID25aXzDN?0NbFQ3b{!IX zA`*Kp5_=^Qdn*$AAQJm5j1BVtO&EuPf#E3<`y&$jFA^KvuYpF54XBR;W&0zsqmkI@ zNbD9Q_H=OuhI&}?T8t#I9*MmhiG3W2eHn>;ABp`MiTxdk%?z4&fI5^P!A@e3MsOI^ zk=UU1Dlo@^F8_eBy^z#|BC!*Y*x5+z^658yS({b)BoWC$8i}om#EzKW=*KE9S%oCj zj>MileWM?%c<5dvp;Jigdr0ihNNfhsElW_J^C7Vfkl1$91^rpYLvxXYs*%_ekl3q` z*gKHeXOY;qkl630clxvTOHPtT_8sp+`^tm5^ipwsc7ZgoUr`y#O; zk=Ut7>_Q}VEfTvEi9HpGy%34L7QzN?%Vl8L3E_ZCgQH07i_;YYS+g1aruPQ2irZ$& zB0N-z#O^|3PeWoaLSnC<{xFbL+4dfi&}$?%=o&Lva+3m0B11z&9f@r^-7$z&U$PKM zs1AwUGrcp2Rk?mQlF$hx_BAB-Yb5q}BsMeXxEiR<{77tRB(^#d+XRX20AYhl7X}6& z2nQUVnMmwXBz7YbyBCQ)6N$YOiG3T1{S1ly5sA&DfK+CV;YjRQBz7(my9&kz%>{PAI1CI7bCK99k=Wa&2Zpd(Oa4a^;sKpc3w5v5^ra!J z@%3FuLer7htC85-k=W0W*uRn39H1+{phk-#v6Ye7u1M@)2zz>YD661t6NCef%n3;B zrAX{eNbF-s?Ay~XhO&xFGJ__op!V}4v8AUohOzc1?ne?jgT(%a#O4BRa)BD5h{V=K zVp}4yU6I&<(?5o>S~Jd?t{cuOUcVJd<{%RLEE4+}68jAj`x6rT2NL@q5}O4yvkP@8 zHxgSM!Ujz+9UF-Yvp>8uf~%C<9*gq9+)cOtRRA+f#D0Oq z{sLix=H(d}Kqo%KibfuFLXjqFNu@#Znu}JJpBz7qhyAg>!4T-&21F7uW zh$L|giG3M~{Q!ym4vEbII&dHAP(dWN91`0SiR}(!gUY^87>9v@AsLBXh{SG~?ikIg zY_|bPXfG1`3=;bx68jwz`;X@IMbWHEp4y-*`k-#LKw`Tgv7?dL8A$9hBzE_7-WXPK z)n!ORn~>Q1kl3fDd&aOT*Z)EiV%J6_OHm}YG7{SmiEWR>_C;dHAh9!$*tJOPE(jaE z%b#J!^p7#D%91A_V&Eiq6^Z?1x^671cs)C4Wj8dCM3C4@NNjT?wkr}l8i}2b#4bi+ zgAUq)<<@#zpYBwH+oaKLU{kHp@M#6FJ1zKq1akHmhB#Qu)NX4XZ-0Y4I3S{Er> zXdp?LAhE-c*hxt24kY#zB=!O%_Gu*cMyX&Hk=Q4Z*!PgwZ;;rG z1_(3xkl4~lY)uFo68WGz5n(CB2O2u61y3RJrRjLABnvdiMuldleFU8xs34m<_rxh=GCO8khr4 za}1A=*zb|p%q9pQ2q3X#k=WWuY{%(=$*kh4IY>fHNbEi&_U!3PlUbGPPaz3iM`Axg zVt+(pvx3g#fyS8>5?dXKZGyyhL}L3Pv11@?P+DYQD1>mpVNr*~?m=QNL}IT)V(&p> zUqoWxLt?){Vl#q{!iRc*&kSjjLUa1X6jt$iZzTB$Bz7tiy9kNhi^N`p#9oiY-h;$G ziNwB!#C`%{LjvR%gaZx`5zzJqsDl-e*w#pF4 zNt{Ju-$Y_RMPh$MV*f>AbApa~fO z>|ID~@LlUrb507HqkQCV=v0ahaK1l3fBz6=MI}wSUfyB;7Vwb_$^$ZNPa1H~*OeFRi zB=#93_Dv-A4$AVh1C!i;&oLNbD{o_B15+ zA|&=YB=$ihcKrh+&Ko554s_659lc?TExqKw{@W*x>ZX&;sFr z(jUWgB=$BW_8}zpc_j8bB=#>PHalnoAk@)nNNgh{ww*0f`R|1!5st(zM`F)FVlPEv zZ$@HYMPfffV!uaXgASW_bR`4S5mHEObtJYa5<47;o#KR)XbX`f z>XFzBk=W~y*t?O~Cz05%k=Sg`h#1m9Vw=L)Apd*9I1CI7*+}dPBsOR#EG+0IA&JjN zVy{JFpGRWfL1Mo`V)M8#Fa*L3m2yG2)CP&|iNp>=VkaZ93y|1#(;W*y$qGs63KIJv z68jwz`wtRZ&K2PlZ6vlO5*xI866W*_B=J%R8x*Vz3{4OYI9W|YV(&m=A4Ot=b~(Zf z{fZ>c1lmRfO=1E_Y$GJLJrdi;4XJYwHNCQs)w+HIlKfsI_9-OxbtLv{BsQ-*B0!{& z*y>1ZMMy9yX&Hk=Q4Y z*w>KQKakjL-iXAa;XOUCgq6$C6iLhpiS3WXjzMB)Ox*cXu4caYdGkl0_4*bKgi zz~F(fAu%EW;ecaA1&M8d#I`|Vdmynxkk|=G>>MO^1roaji9Nv=sm7UuB(VaCy#<38fH%ROsNNg6+DIy@>GceRM2p~8N zGDvI+X0E~gT#(NVy7Un3y|0~NbF898@zXzfnh3`15SSo3#Z3cu$I?r2Otuw z1rpm8i5-N*PC#OpBC(s0*!@WCwMgtkNbK7XHe@RI1%v~3*jFSrGw2LtNC+}WAhA`E z*v`|ZRVPds5{Ho3AE)oFW{s~;0^Ohr4XAu1b`27{6NxM{3C024b&14|Kw_sNv5Sz{^+@a@W};d{`(0LsU2egD{kx3KEB^FGgZFgV<0t(?D#f znz*%?Dyb&6fkSLE+E9z@QA`KouE-*ieH)kl3k6>^vlP1BeYe z%Z7o0p%aNc35g9p;23KDGLSgvNFD|ThE??u3=G0h&Q_2FRMBB1_C+N29S|Gp1JD*! zST1;jB>oY^hMMyS#D=P81RWy-73Tr5KY}VS1_lNxCLF$nZ$AJ!NG6#u6 z4RSzYyMowI^`1!TgFxa?^^qVpR80~RyCM=a&Ik>sA_oxrZ@0ve9FME6eIyPbR~%W86v(D#D;1> zSOx|dTL{Jm`CkLXfu=V@B(@b2+Zn`$I@A-yh8h}##LfV*q2?4Kv8#~S%^)_^oX%KK zeFZgWE=U5(-i^e52x3En>kWtv+6KtL!0;iKfk7C`{tXg`s$m0NP6-VOF(kG$hz(Vv z24X|h)H7&r60|Ub}5C^Jg8Hf#4v>u7Q1;mD`*$ZMr)tmsap$<9&Vnfy30kNTKo+7bdf!I(r zpX)&!sG@%$Hq;=dc+dqakOU|MVnfwPBe4}gY^Xt+AU0Hu35X3f#{$HLs__7^p=tu5 zY_R{sKpd!|cn}+^C=0}f8k7fOL)FxQ*ibd?NbDXE8>(h1hz(V<0K|rxvjoJ3s@W0` zs;{7m_JSm!>_Z?nRMBY=8!CPY#D*I58Hud}x{?bjZi>YA2C<x7fY(Q+N=2#?l35X4~pdQ4As_8&t&jYcc7A!|% zZ$M&i1F@lcuY=h2P|imX2g;TMoudY2n}XO-iyc60sJJH*J08S_TAYEzE<|FNgV<2L zGmzNRHTqb2>W?CcJVj#vMq-O*FfcGeO^`!k8-UnQ+bxmUPDpHj5F1)3fDY7Rg!(8d zgMmR<5n2hPA}J~Wv7sri6vT#VZUC{N;;kSyRD3EDdjW_IRkIYthN{^BVnfAug4j?; z?9BjG0?;IX79;^xbPb7p8^ngHc>-cX)w~C>p$2`1_=W*=b_8=K0|O&e4G$7q5X6S6 z7tI9wo?#-W5RwB)KsBg>*ic0dNbG1Nb_IwH^;t8B4LYEOfq|hNWGIw92_z0xGZ(~$ zn!gCdhKg^<1hu81oZTP^sGqK~G#`U*eS#J0R!HK`AU4!DsUS8qRB}LUb#S0C6y!ioNd)n#LE=y~T}bR% zNbDs!ph^IAYc^>0Ba*~s5c?^}7zTztAU4#310XguR4#zn&``OF#J&e&L)AP7v7u_- zf!I)UzQft|3=F)v3=A+Iiy^V)k=QyQHdM1465Ah%oeE+@LopADU5>=A1+k&#w1L?5 zP|h3>2da4~5_=sIdpn2?4Xq;}HdOCfB=%zv8*0uQB=%P%_CF9C8oKo?c?=AUP=k1p z*cwP|4=AK6<-Nr!^ToJfjCgj z+n@%4&iFqD5{GI&kHo$LVnfy6KvMq@Bo0;o2E>M{`2bY|UhbZcD4sdV1&Zhl0dG>OuK00mOkS zN`Wfc!@$5$0ul!)VqjpXMPfIB*iiLtNb37R;!yR|Ky0X*l}PNJAT~4#4&;N%e?3Sx zI|4EY%07>z=q?ib1&9r`;4O#^RnJhsz`zJ)3xL>A3&cTe(81849!&uQgD{k>1`>y; zsb?@ja2V`CY^Vh;AU0G(BoaFr#D-{Q$O5rJ=UFo_Fyw(OfU+w=;!rg$AU4#@$w=%O zAof>K_%kptECz9)idKNwP|ce`Y^eAS5F09f7{rE(p8&C;;+H{esQ3*K8!G-7#DVwlDHdOou68kZT4OR0IiTw@4hN=f$0Ko_~ zpSuWD{zEy6MTlZp3yE!v#I^*nq3WHG*byK$G_(?t*jY&I8W0<*cLsMMq(#|*wA>*LSh#qu^T{as09;1Y^WoqgV>;R_Zb)%W|uH92t(P+K;lp} zTS`FXKU88bNCL{f3}QnqzJtVmio|{mVnfyc2C<=rg07lpv<3TxfvuE*K^V#wEJdUP z1rQq~4)VV}jKjdd5Cmd_PWxtHV2A{-S4281uLE=y~RUkGr*y}-T zsCYjTdlrZdRWrX7RQ^L1?E^_b+2@ehH$d#?5Z~Mdv7r_}Lt_5{v7w>GT87BRd`N6@ z5F2Wa3WyCcCyc=w!C?qOVizH?TanmHk=Xl@*f)^aZ>PVV!zx~{RnEY`2(gF31&JLB zVlRN42pA1wL)D}pv2&5wWk~FH5F1*tP6x4}dRKth&^hmQAhrXjYyn-z3F1K0=TQ(F zs^J_G`#y*bEy(wI#n<*2t(Pv zAaSUgXe4$Thz(69*&sGleGP~WRo@I^yF$!t2bl?FPXdX9)PU0VTo4Cp&>|2UB*DPI zuolFIif;n3q2hZ%Y^eAl5F09f2E={>vFs{{4Ylkhhz)J+zXY+NdOuZw(l(Uy9V7u& z#88PSv$#QQs6qT7HdKu~hz-@NfyCAYv7u_rKy0WQTM!#+jvInq&kzIRKr==v5<3rx zT?Jx8HTNO07bCIPAh8dD*ibW1BeAa_vG0P|Pe9?%z`*bd#DQAy8HvqX#lXM_6&FKd z%OkOkk=TJCHZ(dSKy1(z8w?B#F;xrG;9IECR68j>E4K@E7hz(VLAIb*%|0{?C%}&2TY^Wl>Y6b>IC|eH1 zhFYKsVuSXigC;7f85o42Y!i?;RE<4|4Yk-8i5&!DL)FAqgW5JwMM+2!xga)Fya>dG zT2PI|o(N(?<9HSldodDwC5R2xy9tTC8_uq0V7LnBFfhDAV*dlNp)O^uVPIhNg9JNg z4FiKPlq~`hhpLeWv7wGu0kNUt`XDw`+!4fviu-`r^-zgG5Cel>^#RkQ)bhAP?(Vnf9bfY{JHeFemZ zir)gUp&{`OiTxdk&0C8ohQ*NB@(?yS{V}M5I8cKukl2n$>~Ihp8s7;>>`WwfK8Ou9 zrw@re9f`db#DyUhj#Fj^5tAf~2Gc93k zkpClL9MB!JNbCv_8|t`5Bz6}Pdjg0JHFPEtdp(E^)w=_UeGrL#ybe_ULp5IjNkG}p zKy0Yy_eks?NbG+gHdH-3C={V=Sr8klR}G1+kHj_wu_5Z~8SD@o26rTO1c(hyjPW3L z03`b**E28(L)m#Caj2R~5F45>>p*O%cqfPr74HMFq2lwvY*6?!FfgnEb08M%0kNSL z900MQDgOe94K?T{68j#A4OR0T#D=PQ2Vz6b`HsZqYCyDc1?xc^&_!kp3=EQZeG8)~Qlhz%9D2C<>y4j?vEJOGKE1Y$$YOarl@4lM(*VG~?nM?ei~0ZBj= z^@7+?@hKoS)S$UY?9CuHG`{yBv5z9LPlMP{y;qRfuNpw*Kh)J* z%4TUq1Q$Pu4Rw$Rhz->%4`M^bRX}X0xITyt6}JGfp=R1NGB5~-FfizV+Mhlk38t4b>0_*TBG#4ibl|&jYccYRZw=y&yI;RHh-Z=OeL~g4p#?&D%g6&<%kM3=D@r zY^eBYB=$oP8*1n)B=%<{_D>KSs+XyWfq@aqmH@G#dKHn_^;$?A0}vak!4brcgyaZ! z5F08UfW%G$v7v@$Be6@6*o`1IG&(v!Y^W!Dniv>_BS7KLz`!saBmq^l2*id4?{W|u zD!voMhHBmmVnY+@Sr8kl{u&bdHi!*X^900(s(B4!L(Tcp1j?6C4p%dx3>QXX%OJ5e zL2RgcXC!tAhz$*`C=eT}CK-ucfyABxV}r_{^&k$^m)k&Ws6o4$85o42?4uxYsG18P zHqR8GVnfy2 zAgOl+i9-$b0kNTKLXp_nAT~6ulpxsk47CUjLnnw0)jSu8y$^|f8HxP_#D)g-dk`C{ z_XiT2uN4uk;z(=-FdG#93=9lvAP!WsJ`&p%#D==s4~ZR)#7+jWp?XU}Y-q68fY?!x z9MsUtz#t4|cZ0;CYNpkLIMAS*4PrwjRwA*tBe4&G*iiMyL2Rh{OCUB>{5psYwd?^B z`x}T2^~`@L8|;6MHbf99gV<2bI!J6M5F4u58;Ko)#Et^7p?XV@*!@WC8A$9^ZJ_cW zYUpN=1eCo8iG2aYhWhe4h#dn7(%Wqe48lYh8m;;VnYowMPl0_u_Hljs3Q_UY|tf&prNRC1_og$J0Bzt zRZ|6G!`lD#AP!Wb4~ab!#D+Rz9*7N9vjW7v0||+ZAU4#3tspkk14lt@sNQo(?8_iF zR89RI5C^L0F^CN{=m!#;v4equ5h^YYVnd@z0g0`N#MTF~q3SJ=*nS{3RBt$h4NiXy z2@nq0JDDIh)MsTNHq@Y5NbJo>>^(^AOCUDXg4;;!CrIqKAU4$eUmc+GA8LV0C&HJ` zNbD#O8#;570AfScXCkqSkk}m{Hq;Rlk=V14*b6{xkU1d#Z-sFf7#Q{;v2P%;|AE-h zxM%HRU|>uH2NnZo7Xt%m*&>K10uqO+kq5D%(W(MsL&fz$Y^b+bkiCv4to`l4n17brRu^7ZogE(|K z$e~d7CXhH(%>g9#DG<9JbSWnT1H*X`2dd!)68jy94R!T*BsN1IqRQq3v7zShgV<1W z~atr8tiRI>~0VnYUVT$ z8>(hDhz+%P34{$!e+*|p9H@p%AU5beBG8$8AeTbf4?*HkHLpQzsG%P~Y^eAz5F0A~ zAH;@=^Y$aslQ@VCx+0c=fkCDpRQ^LPPz6aq+14O7G}v8`*uF^YFc2GRPz;C-)mwtZ z?gFu)BdZfYY^a*WFgD2lhd>;tOHYE>xsXJ3wx5AP7|Ol@5{IgJ3}Qol`2xg-s`-P& z=AD4>u?UEr2QgD(0t16El&w4gsr=UiDS{em3}Qnqb3$SVBC%sYY^eG~5F4sK2gHVo z7lPPO@fr{tD&7cUL&WPDdO#eg#6%Dq>bhA->@7&_y-4iqNbCnl?3YOF&mcC$GKOCu zc0ME|{((XQw6+Dr<(!BVTp%{oL6RUgwDM2_v7rW;f!I)ktUzq28ZQtVsy7&k9RXrP z)g*%0P&FC#AP&@^IwbZSB=!a*_CXLE>WC8{Ht5Do1_p*R6B!tUq3r7*aj2R{AU4#p z=O8vz{1b=`8~^zZ;y@+XCLuyX5X6RR76Y-NY7{|isJI%44HY*4u^)lLlYzk$#D*%m#D=QrntpI6t9boVkPy_k zl^`}$=}r(Es`L;N`#6XVRdWHvhN`&^VnfY&jl}+f#Acg}D1iAPY*1ciV32@tz@eZB zVnYK&AH;@Q<_Ka#E%O4gp_ci9*ibcbAU0G@Iubhv#D=OV1+k%OY9@oqGN?flK@w2* zR1h1gVJV0W)vykUy&1%Ys@Vf#L)9Dxv7zSNL1KSJV*i7&LH-w+f(RB_B(@q7TOY)R zhKdb{4YeQ)iJgzc?m%KsL}D)ov7v?ZhAE)349eMwBykADhFW$4#D-dS2Z{Xy#D=EH z{~&e|IQAHrr!p`IL)m;&5&1$A#D<2D9Ec6kThE{g;y@+zKx~KvgC&R!6}JPiq2it( zHdNdX#Dp-j*MitZpzvp4U|0g?Kzy(kiM=1hhKA4yB=$ul z_EQiWYQY;2yBK252T({r*}p;JP&I7R5DjYXdJqRHAqHYYT_+7|f25QSfC7y#Mpa%U$V)IXDU|@ubOCYiJKy0X9b0oF{ z659>LhU!g0VpoIM;LxpSU}yqyKo>YNFfg=DXJ8P9vL}MX!HO6d=78AH;9Uq}L&evC z*ii9}AU0Hd4~PvFKL}z&#ZQCSpiAx<7#J>q*!57$u0So;VPIf*29khkehp$n)x1Yi z^93XhHI#h@0|O&e4L67lEtI4|Y^XUZNNi0I8>*(>2*iOZvIMcA26-c~Ly*{MAT~7E z^O4vUNbE)s8|urIAU4#Y8$j$bNbcA&gMmS~3_6y*A0z=)bPB|VI_Nxz4HdryVnfC6 zgV<2<_ekttAU0GD^GpT?MyO@%AU4#;;vhCujlxV&`48o&f+V1d^gwK=xG9JYH7Ej! zU5&(^gT&r|#6FG0zK_KI3Sxsi04jg}fH>ulU}2cWz#t4|bI(E)pJE_3)Iri9Hb^sQ z5EjISife<|P;qMz8)}XV5<3dShDKlVETr;32T7s`#D;2aLt@Vav7r_$0I@3|j$Q(C zG?cv_Bo0-x7m0laiG3Z!hB&&O;SPuc)%*d8%{iNafe|XMhr|v6v7r`3gV>c2N5s!& zU=W6~vq0idHO(M4#4?5s5F4syCWsANr@H{ese%}^1Y{7Dy&fbEHE1u04HZ8QVnfBx zf!Ng$y_Z0Gq3pXLaj2TtNbGMQHq=4C>p>i-2A(;H_!b7SYaoV-&tYH?hO(7F;!s1a zL2Rf&4j?vEO)Q8FRg(f@gKni|U|`4qnFD1PgT!I$bn8GIs6l;5?8zWD)S$T__C1J$ z7J=AMgH|K44}#dx#B~aZeHn>;2gHV&^KuTubonE!qV>N)f=~nb=Q1!bLfL9aY%3(T z9}+tqiQNlgLmfN?#0F(A1_p*1a~T*w*D!*dzZfJARkIGnhHVzu4B|i~j)B-v&8I+Y zXt{6;#D<2{V_&n!`Acfq@aq76!4Qc1eL})f+%=V_=Y*$G{*A zWosfSGDl)Nf!I(B+(B%pK|vrkR6H8QhME%(VnZF54`M^rRKVCEN7aHjP(^JZHdIkB zhz&Jp5fXbdhz(svzZ1lUsyT$jz5!xG)5Aj~_A4azhk2kv2&$QNJ_7?Il+6!fLwzO& zVmCrUNNPR3KEB^F#xfljy46cq2dl8HdNdd#DKWn?9EK7Q8|vy> zBz7ATy9dOEXl7W1#9ocW-h#wFiNwAPVnZEq3&aLZsDk`<59G5Z5Q~A~B}f9Q=nIGq z^}$aN8>)tB0Rsaglq~^bLmjP%#MVM$8-UnQ^;RG@)O^Q!5C?Q^H3I{K>jDM_&`d7K z837=1sG?{P8|sJz5F09<4PryZ3qWkBIh9E4eh?e#xEV<7g-|vq{V^;DaiE%aBeBnb z*ig$ZgV-$~r!g>G2RRhVegqPSs(A}yLml)9#DLGce2rNkA2? zMq+OTv2Q>$>;kc&YL0@~P+y(`vB3s0FkD7rzXY+Np815t{*AIg3oy944lzeNlT!ccZ3NF1sr1;mCrG!w*ziWh^}*CBfAD?l8m=0+s; zbPyZrg9S+Jl}PMOAU4#X9UwN;oU=&mYe?)*AU4zyKSAs+Xe0D5$Ol~z7jY~`RK;Q- zHdI^z#D;2C2eG>$>a`a$FbG50W*~8>8b=Tt>U%d38!8?MVnfBl7K0k0P>Dn&i8K%! zDqaX;Lp79v*ii9C5F08!6~u;$F95Nj;!8nnsQ6YS_E8ucl>aV(I8Y5&L2Rgor%3Gg zAogvDkH3J}P&NNR>{}3V_9YAqjL?wa2C<=aiZqA~HD3jZt+@nL{zDZRAxT(**ieIP zmq3Dd9wP&T8%P{#aUh5dH8c#whN{m&Vi!R57BVp~RD#5zdOJXDi28bli3kqES|s*H z5F6^agCI84vQtRx^B^`<%?%J6s^&3>4Y7dXIfxBa^Bu&7s$p0P8Vdl0KLY~;D~JPC z#0O$S6^Vk_P=n-<*d`!0G?K}#DTgr3W=SJ#4Z7`q02_9Ky0Y`ekArvB=#{R z_IV`sQxF^KxOdAyK*ig&(k=UvrHdL=365AY!?Eqp!%?Saq zq2|QG+4T$zX>bk$Lp~C_6~u;G(1*mHj>KL7VnZ!h3t~ep*oMSD17btXxr)TT2V&Pl zC7y#gP=nrr*ieHQRv^VO5?da`hU(QoVjCi{%|UFaISxqdC?s}$9ulVT_GiG2)-&At**g!6&eeUJi5Xe9%KFqAC|68{P<|FuCJsDud;+XIOm4`M?L zkTejxA7W@0$WSP|6eJE+(+pxm#e0z03y|2`S0a`F`#=&CAch_S846{e1&Koqy$xbR z#h-%MQ1Le)Ht3`X(2-;yy-@aVkT_Hg=PCvUMyR+jhz$}4l|ND-&LoJ%a;q2^grRIr zkT^&Y0|SFOhz%9@Mq-B`vEx8&sQOe8dosk#OpuvSb_qxvs-}JwsQibPbS+2{{UA0} zdw5Qq&;n5U80SCH6uL2QUQ^$d?e9H>D*kl2i?85kI$ z;vz_FO(eDjhz)g|J%~LG;yCBk3=G0hwjW3wswNV|hI%Xx#D)z*RDd{8iCPdFs-Ydk zegHAF2gHUNIu(gM4~e}6#D@BQFB1D068k)e4K?#lJ%|G}^dl0Rdkq5vBUD@tiLH*r zwnk#RAhDxBY^WoWk=Qv%>{1Z>0kr(D263R4^&_ztBe8dZ*wE$She2#;)SLvdp?WVN zv0s4LP)B@3V*f&7Gp_}e|InZiSc~wn8i);z0$mUrys?*o!Eh}DgD{lsi6kC`#LfV* zp%xb+v8#~S4InnyoO%X^2_O#Cvgsi9Oh|ms23ZDWF9V4~)oejx?+3A=>E;NC4OM>@ ziG2-;{St}&55%sAYG7Z-z`zJ)3m~yok=S}jY-c344-z{J#D+RF7Q~(f@l4`61_og$ zI|n2VRa0LN;y@*uL2PI%XflWm_1PRG_CgRFs%9044OO!d#D?gC;%#XUi6sCY1leHCJH1c(h4PXe*8K*X~_ zY^aCxLF~_<@MmCPs0VSNhISyadqHeyYM%yTL)9zbW){qCgbH zhN_VSv7w&P1hHY0kVa4rD3HuSY^Wj!5F2W-H;4^2$RBDMGcyB2JV+d>CIg9`3t~gn z7b2;z0*OP_w{8NJ|4>DpAPK0&GeK;qqD4sT&xqa6svg;RO==ABYXL zfPE`ssfGX&TN1>E=5I9+8)`u;5<3lvT?1l6&1~HYy5kwj=|hs30%AiAnv29^cw|T4uF^*o(ly!O*#lfk7C`o&pkwb(-db zIMB4Z1jL4FUJqhJ#kYXiP|YWh*cXx5&p~Wx7<@ot|3qT5Zf9U%gqkC{9aL#TIZ8+p z79cj%AV(y&7ZN)R#D?n4LSokihj5_F_oT z9p28sAPi-n1BpY`+ySu{PuIK8Dqgh2!UM;48l;h^e#~U8{`VmY66fVs3WvNY^Wj^B(^USJ08S_IwAv!U5Lc4 z2eF~%w}IFzA&%$*IRe72XP63-fGS!HVnZYt_8_q@f!I(rH$m)G5QFZ541%&>fW)C{ zzJb_KasJ&542)2=Du@kLqXS~E28BNZ1B1bC1_t5P5JRm&5>Q2+AU0Gy3dDwrCxX~( zAnH>=dZFwBkT_IL9f%DT?*Or(;{71@T8Q4s^&rhq&ODF=RM8p`8!EmR#Dtq&51s<8#Jq2lf!HdNdX#NG(e8wAn|WykITwZEW>GC+!;2{0GLhAL`A zVs|02=YZJI1h^E5y$*@J6~u;`zX!zL1aZUxkR!nCdIpBmAPK0VXCO9Mf`Q>Z5}R=^ zqF~`dVhba&r9f<`If@|mW{72~dl?vnp=<+?I8==th+Pkra0hXq>{t*R>a#Q?c0Llj z6vT$AuLrTAhPHv&TOby9fh>lyr-H4`LhE*WWZir>; zK$bz-J3-V1U7ehp$n)qeu9LFZsHFfe=r*#$bh z0%SGg0YnMN17brB6$G)Nnq@$2sJJ4C4K+v$iERvGL)BY>*n2^yGced4U|;~16(F7` zNF1srq#ne98X5^=LnV?y>`Nf!3=A0{Hq@XRBz7wjdpd{>%^eGn*ej9Pn?P)+ndd-k z*dnm2AkKb>Wj8@Cg|eT3#GwxQ1Y$$Q|A5#~apr>z44}{h>1IF3z#x18#A09&0*OP_ zC?K)5L2Rgp4Gx0Jf2amakOY+Ngv5>nv7rVffY=8i7NmeIgR=8M;!riUNbC*}8){iE zhz(UU1H=Z4gVtYwI8cL@A+gsZv3DS`4 zU7rY&fGWyIVpoCKP)F2**ibcHAU0IIAH;?lGy{pf5Q)7CiM<(#eFVgYbtO-OI7c9^ zI}dUllzj^%4z>6xhz+&)6^IQL{|aJ5#kme6vau8rTMNX7nrV;3_BaeG|Dh6*APK0U z2_W`Sh=WoNGcX84*;OEMsAcsaHdK8t5_>ihdl`rgRlgd( zzJtX624X`s^Bh6=QW(TO263qP5e5cfC|e064t1OX65ATYhC0aM2&nvrD)I+OKs6^L zv2&2vH6S)reKUxC9Aa@h$YLma5=b1XW&sj=HHZzhcms$HQB%*bAH;!bzKq1agT#IV zVnZ}Ad%~TK@>d-kL_Gyq!3=9j7G1M~%LpiHK5>Q3kKy0XQjv}#7 zf!I(r*OA!IKy0Wv?~&N7#}UnTJ|wm{oL$erAPeF^H5($at&rH>AU4$EAQ1Zu#0O!= z85o42>_m__R80i+s1}#Nm?*_4<(QyQceHMv*8N`O_ zeU8Nbjl>o_fk+1uAof{^2kK=`Ffa&1IqDz@sOwCT*bX2z)HkjmHdK8Whz;GK90OuQ z#j8PVs5wm__Bn`UZ6Ld#?1><8SouF6#DPkz1hJu-H-OmZA)2>lFyCm9%oq3p>ZagZ9&P~tog2O7MKL2Qr&0|Uc45F0AK8N`Na-h;%x1Y&be5Btn2 zSN{RThN}6A#O6PR2nh)!wjvT+9mIy}wMJsQAhCUs*kMTQ91xom+LbGXaKK)!Lt?jp z*iZ}RBC)rE*ia9jMPffiVt+tl^PEOX$RKtjWYkURG$<;e2AO~)plmlJb_5bT1&LjN z#I8YN&p~3Z0I~N%EZYQPL(Sg@VuMcp1yv*e7D#LxB(@6@+XIOmfM7E*giP1{ z#wu5bo5#XUQbgnE(KQ;^s*kl6E)*o%?atENBv#ws4V z6-j6(68iuW`v?;IG!pwf68jnw`_^>d@2ukW&ya-PA+bLpv40`4{~@v2&LU!#3yCd+ z#1=zh%OSCqAZ$>gV_?vPaKM>P7m00(#I{6YJ0P)Lkk~#*>;NQoI1)P=iJg3w8{vcW z>A62x#U+c7mm~S1`_)Y68i}f`vnsF0}}ho^xmJW;`RTLgxJp^LWdiPEsVq#M`Ft( zv6Ye7+DL4DB(@n6+X}*-uKbHtP|_8`0sGGvi5)oI_ZO>pZY+{eDiS*riCu`qE=6M3 zBC#8h*quo1UL^L^=@);oic2m)5?X@9UNfEXH>-H)b|j(QNbEyM>|;pmvqeQBz7ATy9-A%O)`><7GtfvLdm0k=TL|_H_HFwN}$TJ^8!0+pw^O z%&DI(i#X&rNsfVm5qcczUl1F*-Qb)&0|O(Zcw^{MU|?W`o@B|bh&b`^h7#g%xV+h@B1XBRvIia>4nUfk};lff0I!({2zOdb$yxIs^Qy zpKMJA21e+?D*r)j=(!eWv=FC1^lKx|JTTK?U|@u9;;#jO zECU0>6%ZS`w)HQF4PBgNV2fCoGzG+lF85gtVnf&M90IW+>vQTE?t?hc6(rm27#J9# zi#_gv*ef88V6$gnV1zD%&;+re%NKk=Z0Kr)WDpy=x}XZghAtME2x3Dg|5t$6(7F8U zAod1O_%kptyaREd^Xp;`3=E*vn;@$#Ky2u&ayp0&oh7aVv7vLR7eQ?3bm$8Z8#;4o z?a08u2%SvK0xZn zmx0*Ov&J_<+039NX|fFU3_>9c3_J`B3L)oCyX3j#{plgCIL)oBP%kDtg z77PpwkDzR81_p)~P_`o|2|?MQbLxLW*`W*!3@maCV0+_0WgQok13E%Q0LlgxEz(dn zC^;%Y*`QKD1Ik{&z`&pfWrOm8C6oEs5mHux}j`Ps7!>iT|g(WL)oCqQszS0 zAm1;BvO$+T)~|$eKvlygD7%n>fnhh44JyTtK-r}X3=F5BY)}YYfU-e_=`|=DwAuVV zlnn~4r%*O%XWVNj8&srygs|%wK*9JG!U65oWZ;lzU=V^7tH$oH~PHYlwqL)oB% z%{8HH&}qK)1Z9KHH_d>uK_Qn1W#@pduY|HeRah02UB|${&;VtFLZuDLo&ic+6QP{hpp!tL zY*48@56a#Lx+NCM1{E_Kplnbnuno!vU2D1r%6`Sbz;Fo4e#^kXa16@+z`($86U2r# z8=lBBFw_f0F))CF_cc@k6ujS{Y*29hg|b0c1~DrzFo4v9e9Q@DgUSqkC>vB}h(g(* zbR!LAgL0N4lnwH*4wT&qn%XgjazF{h63PZulJ-zGXak5VlntueyrFDR2n9mfpz0$_8CNd#WDF0o|;28OkxY`|3lfJ5|>$#fk7ySfgy>3fk6z!jsw+R z3=A?*c0I@kN>C1HR!jrR76p}VP__bStqzn8Dux}PY>*?oplnci6#`|0>Xaxb8&pRm zK-r*nQyP>FY7^yv?m-udV_=xez`#%hl>oI(DxhpoQQ8b;gKFn4C>vB^PJpsOQ8o?A z2Ay9#2g(NJf<;jF7X}7~6;L(5N0Lr#zWMDW3 zWxFymFr0z10~r|@EaaUqs5UP)3 zVA#RPz`zCK#4#|OVq{YEbqoMg|5QDEl2F1A`fq z{gaV_!2!xafXEQM{Y=^SvGBGe5fU*}dF)$p1vX?M1Fr0z1cQP?BT!69< zGBGeb2C+e9HUk60ODG$Z@ZT$e%KtW_x9LAwGHp=?ltA_vL_9WYW1WrOyLRzlgVj0_C*P&O|k14Ap6EzHQk z(5(zA{}UM)WEdG3CPF1t85tO+L)p5F3=DIjYy(CHhQ&~}86yM3N+{cfk%3`7lnvh8 z1!adaGBE6hvOziGAe5cR$iQ$M%1&lvsAsqY|Klu45DCmJp;pG zMg|6HFo%KR10w^2B9#4^k%2)S%KpvBz@Q6d^D;3o7(>~@ObiT`P_`Ho1A{%3EzQKh z;0k4{FflNAL)mIf3=Dx#wjmP(LwG%uV+G27P_``-14A;D?ajo%kO^f6GBGgZL)i(S z><49MFflMRLfKiMEC*$Svf>0NyM&2>VH%VT%9eAW?D`r|_JeXjd2}_D-3-cpQ1(P7 z28OLr_Dm)Qh7%w*s1d-xz;GGL24$yPP&TLy@c_yO)p*aKY)}RE2FeCC%RZ@q+W#pG z44~7re?TQb4UK*AY&*S zoSxLYM|bPvO&%K`nyn03FuG;5F0w= z^9{-dx%wBB4O;xntH!_}1RV+zhO$9wB%y4O&*Y(OaZqUpWrIRU8_EVXb_^lxdInJO zX%69l(}69N4Qi4*L)oBSizk!~D#rbx>~sbOhEOOQ)X0p6vO$f^L?|27u1trrr!X)u zD^Tt*%fusJYz=WrLdA-B32D%{URt26fq{L)oBa_*^La z9Vl9%Y*5pCC6xUSbXx|L%~{XLz_1z05dt+dKy2vf+8HPt6ug(9Y*1pn0cC?4mJgw9 zP!sJrlnv?=zJ;85rcDY*|JI z2305<)Ns{?vQ-!v7!09oO-2R=b0}Mzk%7Sp$_7>IK2UbOJ|hD|FqC7%$iR>QW!p0{ zFyunnK8y?uJcP1AE$lZ?_8vwChR;y;K2ZDrCzNxXk%56l6A~R~85tP(q3mmn3=CpW z_D4nr23aWk8zTdQGL-#;k%2)I%KpX3z@QIhGchqRSU}mJc7q+1Ey%>c-~wXT7cel$ zF)=WBfj9*W3<^vP3;|HKJ`)2&B$RE+#J~^_Wt)TA2T-;p69YpThz%WiuYs~b*|iDE z1{KL2P&TOi=!3FBUA+1!P!6c9o&{xt^5_C68`J_`24#bW=GH*jph9L7lx+^mK~OfR z1-uW+4hQvip=?mGeICjNRgBjl?0N=JVRr|@VE|P^kDzSOsQ(Kn8#Idl8OjEY2YiRJ zL1O@1S_}+ApwR}T234u18Gz-KA zMHmAE!vZK96e`Q0Y!1*pvrslD*KCKfL7}n_$_6##jzHOlLpnMP3_@iL3<(Sj3~W#~s7=cQWrMPu5R?s? zXp?}l>p|oBa!?K^=v1I=Py*C~vOyhFJt!L#bdDf4Xi@-FuS40OPzi>zL0K*m$_BOn zQ=n{6uQ?ma28Bu?=&n|was~!au#`e2Kple)5F6x71_p*cC>vzK6et_iU7rPIgG#go zP_`li1H&>XTN4yDP_`Ze1H%R=+lhgJ;V_5|8lMHV|4%|WAPdez*`Rp63T1;Vy9s53 zEPDfDgGwh*iy6uW>1EbsU=V`NPjW)pAaQ;u8)T*^lnrW0OM=+-)eH=v?4$$YfSN0y zTmWT*G+RK~AkB7AHb}D*lnv4w3Sxuek%56B8p;OgO@p#QYI31$P@AzB$_BNj>MNlf zP#drw$_6FIPAD5Rbut;s1|_taP&Ozl&WEx=W&2Vn8`P;-4P}D@X(N;k^4oSO8#J%F z7s9S*08N4(hHw}_dGsWd4Jzl)L)oAv*HtJRG)H+G$_7olJcP1AP59?fHmC{z7Rm;V zo_~h2K@)I4q3q)f3=DsDLFIof0|V&n4FNsScpNA%F)&C%*`Q!lg0ev?t+kzu~_kprO4c#Cp8`S?`h=6iHDL)R%2DQ&qplnbSWI@@W zG9VAi1`Xvlg4m$yk%57s9m)nddIFRUYM#%8vO(E$5tI!|)GPEr<$nVM1E?Xe4k{td zz`(Et$_Djt_d?mAtaTX5234acp=?k|cOJ?HC8(=VHs~tw2T(SsWBMA(1{LQYq3jY+ z`Trft0cFR(P&R0~ghQW!L8yU&0pvM;C>u0WFA8OYCfKE+?5UtJ04N(Yi=ql;gPQFY zAU3G+586QkWrIS<3(T&EOs55aISdRSpM^o$TA(oiC>vBjB|+Js0we><1`Sr^LD`_W zq7o<@RDo4N*`S=#0A+*P1Z_|@sDss259NUBn7JS}s1X1ft%kBeE?p00gW_)&lnrv| zK`0wk(jAAgLE{Ifp=?kQdk@401siDO6Uqje`2otV2O0Ve$^jYr2g(K&nM?)@3_{J2 zK?x2h8)PUClx@Ypz#tD|gC_kL7#OsmY>)+pP&UYXb0`};^a5pr+6vAFp!Rp629**F3=FAIHptK%C>vyG5tI!wv;xWo&6dSGEqNWv z2AO{s$_8cK#~^ln2V~m)C5Y3(0B!-lg|b1#C#X#&1e!Mi)$4`~3?MehK|D}4s2~!6 zvIQ9!7?eS5(2xh{PCzIdq+TD&1{GqaP&UXj_0~`hsGaW!WrON$A1E6XPr*<&D4HUn zY*2G89?AyQ3#m{xsL@dXWrHfiawr>AKh;9nApbN&*!AEtzZ1e?0Oi+yC>vC^Pld8U z^LPuOY|zllawr=#>b(}q2Az1m8OjC?z3hatL3>m7L)pxX3=AirY*6?6oFSfCitT>~7HDGn736H24fK-vF56A4f@189&L%I0BWV3-SKi!(7WEQYdWnHU&WLfINj4D}3K zpd3(7b~lvm#KgdG5Xw$rVqiE9WrNPhJ_}`o2CFYa*-cCg3^$?dNlXk3_o3|VObiT9 zp={8c&}%4r4-*5!M=%>S{?Ej~@Ey!yU^v6X!0;E!zQM%6z-$bOzlTf=44hE*dnN`3 zekl7Z69a=Nl>Lv1fk7I|W?^PvP=vDCnHd<=p=>T@1_oUyo0pk^!MGmE5nyIuu!OSZ znHd=Dp=>2)1_oCs+me}qAppv@V`g9ohqB$685okF>_lb;hFmB+lbL~`9LmmTW?-m= zvWu7*7&@Tr`ch^FhJGlgj+udBDwMr~nSo(8l)aOgfngz(y_=bVVL6n2fSG||EtGwR znSo(5lzowzfngt%eUq7i;V6{-h?#-mG?dN3!oYA5H2x0C9zrY(4A-F&qAUyykDzQ> z76yiwP_`Ni1H*eL+mVHV;VYEw$-=I)W76t}wD0>zQ1A_^aJ%@#X!3xS=%EG|l0A;UcVPJ5Bve&XOF!)2+ z8(A0_LZR#}EDQ|MQ1(d{28Ki^`yvYiLpq2Jx-0k&3j;$gh||r$@RNmsp%}_$Vr5{c zgtB>A85ruJYzbBdhE^zBhLwS#8_HH?Wnh>HWgD|HFieNCEm;{D=0e$ytPBjxplnZ& znd_k(Z&n6|9ZGBDhPvQtT}0A+)wNDhP8p!IVM3=AisY>=T>plndT?lzPS>eoGlvOx`#=TJ7NPw^JY1~p7R zL)mT&3=BU_LFNBs1_n?o)>Wplp6n``;VN0d+!xplmr%(;LbL4U?on+5QX+3^`CX zs8>`3WrI2x6;L*)xm^ckgNEH&plr~bRTq>EYHd#dv+EfcK%I?gU=9NVsHMCB$_A}y zTm@x=R;+D+vOx=Pw?WyUp}B)lHfXWR2`C%1?(ZCweG#-W7s>|R=zI&x2CXT2P!Hui z0o|(yWrN1)-ay%)iKFjOHX|bg!#^k+G-StO&cGlvje$W2w0;E2HUiCZL)qq__5_Fx zayxYJ@}O)`@3;iY2K9)mplnbZv%wtH{-4Rf0BXaxK_x&Pj~*x+l#(Yw*`Sm>1Ih-q z;paiw!Jz9gp={8o*eWO+G(Wuo$_912wn5pTZr2_tyAss?KLq7~Ix#1pY)}jJ9Fz?z zH?Bb0pu~Iw%3jF8!0;Nx1|zwZR)MlX^LScNHYik#p=?mc)Dp@Dbwcc+Y*1czhO$A? z7Y1U3hEzZ~3(5vLv_1*S0ncnh*`Vx~2W5knSe8K9AV*X|*&quVplncK(gtON(nk-J z4a%02plr~D^js(#v_5PJgk8@7%A>0w9EM)dI31J?O0?UcY*0||fwDoXy$?azpnky# zC>yls`V5o}S`&63#0GUJ7#J9yLfIf6zlO3wQS;FPRQ}InU;vfLU!fA9qLjmufk6nm zdY%u;25A<7vO%NaQcyOiOQis1gY>FF*`VIE4wMbbSw>JcsFP{|Wm|%ZNjoS9)bn+L zvO&Wq{!lh(3^)wR1_fgblnqL-=}yY;HydhEGtoAR`0A4=7s- zR5C)@pao1UR*>k^0F{hTHmLh10A-tiW>vxLdIkp2tfxGf138{r70M1`WMI&SvO)bf zLns@xg2^1pPGw|Zu!XWSK$rhO*`NhXK2UZ(BLhPilnt60O@y*R3z#zMp&ZamXC9Od z>erP(*`R)1EtCyfG}sJfgO0H7gtE6XGBET**}EAT7^XtmpmPA`LD`@!{!5_jBcQ2Q zD7*ePXzCTpc>tPvg|b153HLzRUqEZNplr~L<~b;vn~8zp3X~06Gk6!uwqasmcm`!V zGcho{hq7In7#O}n**;7R48N^F<^OyJh9D*e21aX0oP{tkFmOTH5ljpW0#J4|69a=7 zl%2=Kz#s!rg{bje<)`u69YpS zl)a9LfguLUzQe@8kOXBv1+9jJvOh2}Fcd=BphLdPp==INR}0D(WoBS#hO)((85laD zY-v!h3&aK;Z7s*lz%T>Ena{wW!py)h56V_!W?)zXWos}qFsy>IZI~GtHbB{~%nS_M zq3keFw+qUSV`gAD0%fN#GccToveTFu7_LLvpgv*!Jt$`qGXujDD0>Ps1H(Hgdnq#m z!w)DM)F))Nfke|uW(Ed6C>zxG6NR#GF*7j8K-tfj85oqH>=(=o3>r}O2WAEaBM7^m z;RiDVgAIhk@Q;~+!3oM{VPRnKfU?+A7Rpv(VPHsxvJF`n z7&4)3V-^O6d?*{#Z>)f_y;v9+>TE#e|9l1p9~K6N7N~?D3j;$JlpV>!z%Uicj$>h9 zm;+^}voJ6$g0dS}7#LPS*_|v54C|omeijCXEl~D!76yi0Q1${A28IJr_L_PY28Lr$ z&Q=x%hBHw15f%o9OHekb<9Gwg26Y@CLfLm&7#N;I*-u#*7~VqJphMk1L)o8M7#My+ z+22?g7?^A!(f5aifq}yoTK@lMVPN2cN^r0;Fo;0e0;~)SQcyOi)2RYwOR+LAXh7K- ztPBj+AU0?km4Si55y}SDitbQ0sI?OWWrOAvBB5+GQ28GZ<$zYPXF=JZ8m|z_2Gw}w zP&TODUJGS|hV(n2Y|xV09w-~s3!4vOgVyGNmS92Ipz3=Yhz(jaz`($;3(T&E?0z^4 z;(%tBKr0%dY>}-7=)HV<`H?Y|vulgCI6^JK=FVQ2DsC>ykJgx;IGcbVe&;m{5i9^{S^|DYlXeLz=$`%8)|4l#~ z=;lQ$C>x}~0m=qxaDlQxjtd8|K|unVZiTWz>hnNsP`e7W78J?`iMN8-pw1y^w;YrW z5}yNNgKm}qxpV=Dvknpxn?Y>oj>w%*Hb}#MC>zxHJPKulve{`U82GA@fACwK67f=MTL3660P9&5KQf~ld zgPPLLAU1SYrYDpQQWFAYgB%wPWrIR79>T6?0QGW;KparRo`Hd(49W&+?gX(x>*_$O zVW4b~_*5tx&Gl&h{SNapm28sWNvO&?r>d3$#w1a^GbBkMS&)i4eBZDL)oASN@FM+)N6JFv7wt=eV}ZRgMy%J zP@0H>r{AU0@683O}@JCqF)4}!8mIU*9u7G_{zh=;O4g;gq)4eB3e*F!m=@xFX08x)sK zAU0@$7Xt%BFO&_kU<#BCN<_1uY*4yc0A+)!+GS8SsNz`zWrM~EHbL2-ae{47c0H)m zc@o3{^`Ai_RZup_vfEHL$Ttt6Y|sjr=TNpJXhRy54a&x!p=^+4KcQ@pWq+Y;kX-`K z3=BfhP0`ZMpz{APq|{S_N`QQ(0cC@HrUzw%d}ab=gK~itlnojUae%Tx3lUwQY|sEj zIEW2e^ufTu5DR64JeCY)^MK0#OehDG|taw3!sS|6|k#0Kp+WME)e4`qYOgKZ#o{ZR%6kT3UuI7cBt~k^9ITWEll_XWrGU6`fpGUXcZ%;3j>1? zs8VNOVBm+cLBS;oWrLzd8p;M0w~A0UD9fos*`O4z3uS{s(HP1GRppjYHfVgw9>T6? z0F8RPLO7twZU%2C8#GMf4`rKy3Mdd8v}lKcfguCR201Pd$_6>E1j+_Et_sQqMN1!aQ_dIx2LhTs@o85o2>V=W8}3_MUa z$WUP@8)T>?lnokMm4~uHzE_2^K|a=ovOy!LhOVIU{}clQXb9CDDgm0;w}!Go3B(V? zhMqAH31x#UPJpsO7NZ4k*P=1+hUB z{GjEQP&UZ2>rYplnb%@dL^RjrVc8F)#>$MjRO!7zCkgkX~^p8&o;T zLfIg_icmJFv1(Ee;(!+KGB7aML)jqBZcsMJ;y@@H)Z>YOvO(j0aZom>DVG9egKF(8 zC>vC7?0QfuWipfla_LMc8&r8LfwDpCK2}57p!nMeWrJEu z+o9}K1_p+`P&Q~8@nI+%+RytL%Ki+Ry@Ij@7#SG;L)oBZ9IWmPU^CSi85lU-w_g)r5A$Non64Ym?$1~< zy%t0@Og{^vu1uGWVfSZ}k(!AbP*{)~5~$HubzGcia{Ul+^n z$GBzsUy$gM>ArCwEwa<+#eqfN#wV zOs@q|FQ%VO0GX#aT`rN`k8#5E+(eKTrRn=X+!@n(lR)MwPmfCiJ7sMWyFcTU>3=~~ z%yi#mu;b@~sDkNlLDZD#wkcp|_JXLK>337u{h3TOr|YG%`!V@wPOnR4_hVcz{cI|` zKjVbyvT5x8OfK5f^U~P;m}GRO?@MF%V>~jQH=W&|iAQ&OTspfSW5e{dATEQ!^nW03 z#dO~cc7Mhj)8~Sy57Xa*sFLZnne6_IJ=1$Z)SKydGeNF4ny#0{?#HBJJiRW9-H)+i z`q?aybtcp0vcbWTo6YXe_+$FsY<7PpAJgf4IqZInHPd5r*!>whrmqE2Q>Om~Q46N~ z=7K|RE{MvR{uV^dnQoiM?$2alKD{rG-H&m@^t&LgfW>sZd~i_J=7YoGY(Bd`lZWMW zxdL`S#xv7%3&0Vx7evjO&RfXt&v<5fEQtCueQhDTKa+^<^nZoyeoQ*H)BTFr{TO4W z&n;s2XM8jLZ4tXala2j!yJB`f#yQh_i$RtW=z*D0lT^uM6H>A7DPRmE?dg( z&$wfHE{HlZeJ_Z*FrBxI-Jh{ydMt=KFnw(qyFU|$+w^~B?0!rNZqxnB+5MO-+@{Y1 z(JpS&-+|}=x9N5jV7K&Eu=_J+Ouq}FN~Y^pvimbOOs@q|C#IjRWcO!cai1<%1&V6- z>3JYJ!hQO_Dt14{JJWfq+5H(`OpgUoU#73E2BkWW>Hn(P{g`+>ru)^f`!Pv)OrHm$ zRXnD@s{zNDZ7sV$W6Shj5Vd0ZT@dwTx^5jPiF!`2s{^~~Y#lfi%GR^{Gwzw53!)xO z-&+rIjMsF&26jIt4X^2OAlk=k`nm>oKgJ!?|2DAuGf8+)_iF@OGq;i5pK-3vP?$Cylfr-wCzJmfolSu=YXW6gBg7IuFo1Hb8cE$n`bC#LTOaUBAt z^Rj0;svmM|xD%%OxpWDgq&!mzzeP1WLA7jFF-Y#~3#yQhtyV(7iG%}{I>tgp~ zyfOVRNc78e-)?q)#uL-$cC-64Ipj@$*Uj$7IAywR4=6bnP4DYr_hZbNeiy_wD4nj? z3rEyF1rfHHz%IbJWxDSKkfq)X45z1G z>=hE8-UAX|GJP&cn8%NSVKGGb4oLXP^tT}44FL=c1t3F2rt3~*=VwfqZaa}(omC-_ zfx#LiEIhqtBD(-%%=BK6a7-WrgBe8l3`qFR^t&M8DS-?OH4xzolge49D@2)A+jUWaFz3GA1`Gu$NnZzytDt#ugtFuM~Gcbfh zl=Dnx7hp1(Fe(GP@en zov`Wex`o82|DDXv&!jPLI^Ps_HP#Q|3=EqfihZWA3o!OfkDbD<&blOmfnfzicn(Oo zWBOW;jB8rt3~;S7)6Q&A_k> zBAf#fj+tHy5_XAUV5ox#?*R$lnSK@|d?bc}!2u%7GXrdh>;jAjrpJPWJK{j0^{`z?Wcu8h?EH*BrmqDFFNtGd=$_vAm|uAMo0*{4UpxKZ zOi-|-FfeFCOtG28F2HzZy6-G@b=DY!aL+7IT?QC{_CYhbn`)0GNvHnP5U}%R} zdIqF?!SuTzDb|Bi%Xd>a0i7;0ZSeB)npJEl5}Be9lc@2U0GQ&%nSpoiS8PWcpi>@|5X+LCRIY!rn&tg zV@*Mb=YYfwE={ikiI)_Dk{8(NdqCnIm!_WsiBBkm7e+jb*aa99rpqp3S7%*O2+xf% zAmNJXxgg;ag$xXW(+k(uh)iF*h@GEt!t}i$;X8#43^owQ`~j(6F`aiYyE>~x5d(u7 zBouuYv-30QT%I1cm|cz4p@@OO1fqP-VsNRm7NoqS2o&gGC%#$CF2E#kW%@sm@|Ge7 zhBAn9n#g9^Lr)8&@4 ztFeZZFfc?wl*cS*7hvp|p1Yh~oplXDcnwIo$BpUxK+0K4;U(`MkT}Q9>3l2L)mS4C z;yx?D^<(S`kTInU4A~IV=d1vwyj#=Pfs{*>!CmtPB+het`ah6(Oc?`%9VF@5t^{Wq z-<6=Uw2Xm4A7V_;N_GLpC)4MGgwK?LvL4t^cUFSx@H^Artz=hYWhiH0$bu->Sp}{J zY*(?Xv*wh;b4LwGxMO-RNcc=S14A-I^_f+m%JJUxd#ga@T?GS!7DQZTHM;;4$NlMg ztJ&39V=5RJG$Gqk@6qIz)I6NO;5avmoJwN>ITDu3~xCunRC=m@d19 zU7dAC6)2B^ogT9W6djMJ=dEE^W8F~&DmB64Ye34cOy3Jq{-TP3K?q{_pEc|PtbY)E zm9^{wtOC{WyygSq>r^u^h(gqttYsHqa;cuaZwUar1_lX; z{1Onq0L=f$FE29vEXcf$8jyXA6ADD8e+BX9)WGw%%m$F-!R8gd5EYs3x`Caa^+XK= zgAByH9FY8z8hETs*#NHLmu>*n!nF(x4G?8dK+0Nb5ta2ub^*pC(`7fZt1}*%?z)j( zo$X2|1B1ln=|vmal~^w@vM@MIpSh7;neol^y&y%E)1Pi+S7#D9JDqP6s5!KfkwIem zM-xWj={}pl6iP%W{Jk>SL2MR9rI>2pBBXQrP zOq|`_W_ESvC2364?Jp~cP4C?dF2Lt*W>;tGxi$URW_C5k zE7RYCxD5}ci)~?7V>~n6b_=^Y6UX)GX%Klu*#5;w7fdxF~!@@Y%kb!}R*OY-l8#I0d7K9K?S1cJAm<2(z zNX(3E(bHvauuFs_y3up3H&_6#tc0L@;qu*HfpFfg42 zvDw%*=uhWA#3&;KIzN&rM~#7j>9hzV0|VC))9JQ{7$v9I-DGEXTdu>vz+}k?+AqQZ z8sY;TlfVsH#>CFR#cjgCz+}S+S}O#W1MLw3%keXCfp*L?If3Q4IEAL4zR7OSTOrB7 zz_f}Hw7`|GbGrB~c56w{9(1PljBcO>J^s853`}3Zhm~?Ynx1`&-BWNP=-dSsW){}} z$_xz5EbOzVAHBt{q;?%NdmwHNI!{*|wDf{W+(VFofmuA?h=GAc+(?0eft7*j(RAM1 z>=K%HBp4XjoIODUW(*vl+3QGV1_rPzSs9o>doS5sOqdxMm|Ca%-DVf#wUlIFVAlh! zL}6enoL+dFU0l^hm4SiX@H=Q!m2JBMXp;_zEx>kHgn@zG_#p!Wg9zJ(>1%JZi%Y30 zGcd55fx=0SfrkaOc!q}sw6un4^YnYS*|qF1$ucl-Xg&ZfQvz)(VBpXNZA}nQ1r1b+ zCyOvJFp58rV_;xnVCCSLmc_!rzy?}D!Z97hWMDI&?tX{eIyVh8$}G+dR(%Z=@#1R2 zAm4-L@>#@>>N7B~iaQuHFtCXit1&RJizhQNFmQ$G{*jzMh4FK|wrCmVrT0Jj9xTK}r0EJOhKW z_#FcV1{LubT?PhK@i;yP1~qY0B?bm{@mB&23>xA*W(*9P;x8l_7_`J4EEyQI#X~I^ z7<9xdbr=|Q#V3Hy_|#+IdZ@s_z{$@93SO?Q(^uVPSEvtR1@rcT_TJ<{*dc5T44lGj zAaQ;fPFpr_HU2qGIO5ikgXPHy4! z09(QWG0GFHTZDmY2gochws4Sc5l&yWOK?Z|fz>kzq-2&caQcJYApo&D0IXREVp1TO zBh0{MV8p<{8N@aPWRgTZXDFKtI|G9t*d1XIcR-8^2O9--M+8_m8^nc?U>n&Pxb|=| zFmOh(-2)jV&KbiN$T@hBJw6H9G?X-+vtj2F_$~nDa4#{G0*~C_XPxIHiJZ;QP+az`&UX z4g$U>CJYRm>0m!FaDf&sab~ckvNJI7uz-w{0%sD=ZERoJ85qPZSQ!`?#E|;qMf|z|DB%mTF)*+(aItGKFmUdl{^UNp9?uCA1_rKV2Mz`X*~IB` z57^aJZOs`NxUzadt2Wp=)fpJLvO&?$!p5P(z`&IQVzaSbnx6H5UA5j_hk=1BeKH3F z15<-80|QrH00#qu#7uDp1`)1;pBxMfY;hpN3PDT;wg;*V3|vM3IT#pN*z_zJ7`Tc- zDT9OUj41;HR|zQOco=wCHgbSGxCdmWi#7uTS1E|eTEkU7my>~k4YZ?{s{*8tf$a+D zI7O~X5Ql}$L6U)is|uusgRMlEfq|MxN1S-K5V{P z3=CX#n>iU6{MekPhdpFhW?VA8>LI%kqsa8N581^T4^BV&kX>2Q&5D76YZgck8{1wE z1_rL#OpFW+9BkL8Gd^OMU`(Gb^@v^0B1VaUfouLbP6h^61#ap8Tnr3ss(K6z+%ljt zm4U5amw|y>7Q|*`OJ-qU;Fbfinb>ls7d&DY4-MC0VBl5+39+)>Qet4>RsvO4Y;4n5 z7#O&fLG=*_+je;d25uEl@yx|m!ok46tqM{vz;;obfq`31j~P_XE)-*6;8q8TORznj ze&-RplADPT0|So-D7!NiOE56-go2n{7U~QPJm!p`kmDENsbIXz&A=e&rOd#UnBMxBUCn&C3IhXAGgyjGP{f3Rfu{w`;b-7lpwGa- z)5>Vh4T?fgnDKM)Ok-5wVPFvKoBrrAyDp>Tbb%-A*8YJ~3=BMsOd!Ybuxtd?Z|$-S z3_NnoprGU02r7FmnL)B#mWm7vJl4!0r*eT-9P-#e*iBXp3_P|F_QdJ4p0LX^9-qGJ z3A>`1lL7++uMtQyQz<_K18)wP3EHN`I}cFmC5%U=VyUz3nNxz7!}5c_kP@37yX$WR4_Qnt{uE`uV5q ziW>TY3=F*T;IL#A+^xjGz^ee}FbRt2GBEHeGJ;Ybv*48J63^H}#S}qRQ!Ha59|HqF z2X6x7K|XLOH$P)nXRMgM`Wd?-|15n52Hs3Y(3V#g2Ci4rZ$D$#s|O3_!vyEcGBEHK zF#d&@Qp^~~&%hw~3*?6qu-y!TtECticuT<&EDSs>di)FwTnCI97LRI0ILZHUk514PybwBtcMs*D;2H za^@wFP4$dwJPZu{I=qdH6#@(lf~7(X47^Q@Euixj1W$=GFz_~mC0GPOi>P^980!QW z7&ruPPQU-0U6OIx^q5WTf*kh%WZgu@EdmS-BKrjx7(_pTW)r!ZEEyPh zCxeB#Kr3~5XEKU%gPMk73=F(;7!^S5#h|!c3^tmJUzve{cQu&J&%wKnF<6j+K~NnO zH|xO;VGs-kxoQK5Go9rnyKH?uC~h}1f(mUmK~U+yyM^(+00RR%1DA*Z0|W0?#@_-A z3|x=37#Mg@f(_=1HUp(m2s=cTfr0lvV*@Bqqd;o@K*Tu}85nq(!MTph#)5%?R}{?V z72p+Tx+=)Pz*l6*z`!fPR1XRszB%R$47`#|pe)1p9h4fSm_UtL2CjFYTqVu4T#$i* zUx8PaNnVJ7K~UP7fq_?!DGwAvf+9kojz`K?S)MVk6;a$(vD*|eLOxJtEuFv>ndfXd!2_`1- z=@oC-t?Gk78SntpOc4eKu05b^a};9bZ%~nQ8p6&5CC9T&dq5fUKko%5Sy2WCL9iDu zLcIv~)g`d6*ciANK;_3}rk^4V4E#L2SDB*V>aRi7&jOi#o#_i`qa>T)ECU7x-WyEY z*%=r(7`Q;^kMiDR(iCN2P!wh4y~FeduKg}lyX5rrx9sZtU{fA~-6+7Qls z@oBstnSO{eFz~bUeqqW08#Ueh9lO3X*#Cc_CW6z%Kd?*K1Y@Q*zGIiF-z5#oZOkQN zV9jjIkHDHiu48A0B#bwpVw3}1&#^IZeF8azlX)LVJrgevvyeCggP;m1zwm;UFbG}- zarnU;Mh334pejUw`JEU81J`>{aU;omhn0bWYZ9o$RA&x;!OFm(D8R^T&%6g@64xt@hl=`SczxiW(iCS^}GpCx2kb7Fz_Zq-O9lA7G!i1Gm8WRgCY|nZz^*W z+^}?H!!nQz8AuTM5!#!MsU~fr0M?h+PSeR6cPlP__q0 z3*R|V`B4q_H=hp&s zB4H8xkg}7^)1(*}*aUq+nd20g!!8&I%0#D`7fFF?{)M10 zIK#Y7ih+Ska4o2+JqzaW2s%yI{micB#RqciZLkaYC3qh&Yl8aj;N0*KIaNG@rV7wm z{=ARDNuE>iF)ITD?^7^`OR!}6+|TTijC-eV|IDsd&jBjJ-Y|nY*TRsN#9Oc(B7*Fo zWbzKo5fucr$$8&{IbsZ4exR8D#9Sr~PGn!1eL!w$1^Mk8SP26I*CtR~@;kGs47gqQ zi@6h|1nk`3Q0LwR8B+fTtbt7soJ9YElPEg_*L+aT`;R$7hJis*hLM+%MMf5up_o`8 zr4G2PW@Z6pcQ&PIAoVOP;6^Z`QWmJ_U}FK-wTwzrK~*|C3#cgIU{nJ8mxBf5Umiv! zbI`p9yqsW30Y;@JPzlb(0@5hLs04Nr4+|*QNH8*R{RJflUY4mKH;FLv3a~`O-6V+Y zCLySsz$LOU3#jz~Dulm)$`=t94Os>T6&Xfe36^!B;h1{R!JfR5ETGurn+H-N#R3XV zKG2p|UTLtu`D8#9nhe-JKG2R)URf4Ua58YEfO48VOS&ur1J@2vqEliyCdC9!n}?wDczN|% zwt&iF5m5PQ$kGF9iJ35g`XwwgKy1*FCcMThOF-=VpbTWfvH`^Y3o2TzSwKArt~sEb z?!;085(n*f=5=Aolw)8JDFIpfLI|{Wm@5FJ*NvqCB)(*Nz&Cac4lkAsAl}jG4d2*B z>i2+30zVc|6PD{WD5r$5+yzO$02=~Yg~`JbD96CSB??M*VJyEul5+A445FeS6^bB2 z7es(A=Mi-Uu|Uzvzy&&KlD7fk(o-P4T&(_F3=B*^^cWcUrX}$(Fo?0#gH{Lg8@*Ow zU{HMv+5yC<`r4F%fss*F&VYe|iBVOJpMimyQ5AF&2@9j@3|EN5#Tgj*7**}9L3vB{ zFKC>Ov0l|smw`c$QFS9|*CeBAfC&SGFr(^JMFs{DM%5lZ1_n_^)jTl<1~Ep}ClU+{ z;*6@Gb9*HiRnJH>Fi0}0a!4>RNHMBDm11C!W>j4!1UlVL`tQf)3!@$5l#ZHldL6sLYXwRftq|Cs;$fT;H3F_Xe zUeRG-U}jQHmSkXHVNzXZ%D}+Nq$(u|8ii4vuf)K>&ZNpL$H2hBq&gck_{GG)%EP}T zUXg);JtL)vfqyAz-!22&4U>8X2L5FraSjF^mMNfN?n*5N2L9zBo7I>Y`BzPX>sbxa z(*!E~)__VV4hAOB{Y3n03ltd`So!!jfG!4sn7IqF))a;ffhH5JMn@> z&?ZQO#+jKq%@`Q?_ky&ss_-8unf~f0yPj}~5(9$-+hHRH2L7WUjWTTZ)3txGORDaY zWnf?e9c;vZN?eJ7fz^cnEa*xMh-=S5T)TaG<}Y?xd5{?*Y+<0L-X&1uN`mdIE&~Jq zWl%99$!0%&=`VJb`r`%+4E#4+K}HGiKQ#i4o`VDS8Pq6w1_u7;pfa5UqWc9%Hy;C2 zuL1)D|4UY71_o9E{x?~0eQ%NUy+hLX9;#2(oPmM=gDps(0{`b-pj$5>ZvTR$@he2* z1px*I{%;_s^Ra9(=~zuCAkdz z(Tt!PP(`pTr25f~!y&$N6!5<6mJ8KHonldo($1%!@GcafgZUOaG_kP?xP7tcpjl9~3ba zjG#(R0NmZjWKd&Z5QqTBU>($SP{W149;}T+ z@FgfaH86sDqXLk?ZDjl`%)p?-z@-Vwxy_7+Kt>7hw=#Nxi~^g~1~X~;r@!p#_4%Mw z-_6Ja3M>)+UdAbKg?%uEAQk;kE5T`I0yu8?1l2$RHW57RDZs#G2ui|}7{fp&3Gh#0 z1cg5&Xr>~YG!0^sKv8Nj1ON1T#;c%4H3OFzs82Y9aREg4Y(~&co)F!0pt`4nf^RP4 zLlICbRhWZ;fqx!Y6=;zAEvUP#2huyA@h*rG<6p#Bp$<#`i=jqTfueQ^!~ufk77Psh z^-DpcL=1d_iJ-D$8JHs=I2V*QmxDP%fPd-NC>_*XG1fD$$r|7OM& za7(s8EjbLzvRlDH#KFMT0P@#1#ukuz8UCG&pfmL${@Mjnug$<92pZYu-_2+y5Av8F zXi#7eI81p2XIO#COE5=3P-ptV|LlsfTOcMKV(ij@dG9dDB$z=*kPSKt)(bW07?>j< zr~?Yf(H+KVAj1Xt?=h-q!km8} zYPbui75{*-9$X>{_J9hrhhWqB7`SGDbU$JQos-Wm!2gUf5w80=R5xh$i2ns6X!eLh z5Ht_V{}LS0oD5v^Kn3_KMgvW7!T6SOHC*#MsAkaUA^&@@WgJX`!P65MIiym`K$+(g zV=hRW1pik?(0S~TsQZSj?K?ypc+ipm2bjYp7{JcJ!2c5*tUQn~{snd#ub>Smf`5ZY zIQazYr{81bkW}Ra+4K)=fd~T+3utVV3pDM`|DSO?$aWEaPNuf$GE5v2(rsFxRN?^2 z-aJefm>3v%1VMMg@$)kEO!sHvkW2%e2+uFTFTiwO3l_kFOyCMa@EIuS2!TgcI3T)& znR>K9r5l$4D4B{d%>xy%BK%@ZpcBy{eicX7ECJP=F#Q}8hk_qi6$1~;9MI^gIw-Nq zFx>_j!No7f6r&BZUmn>A1&9$0T%cw!zaobyO7A3za#I1s$TNwDwz#LA&$)NJU9L(VoR0LIA z7GMK-1eb!+wk1;)$TUH3P+@Mx)Sv^(W!j($(wYf0=Pbd%!?HvUG@%mKm? zZ^Oi-!{ETcFT-!g^c`ddxV*N9ItZL=9hl+;LGceRB^;rC1D6s`V2*%b-Sqh^9FqQE z3tgcWavfr3VBmLSnxq37K;-veQrCs~*Ar?wSiKimJqH693rL|i6X*bOegS@8rj+UI ztQ>OnU_}97MLY~#-$B)HAd@l3p91{BObg+Lh9Dan3Rce{xC@jc!oaFPCH6&7nUDpF z(Qu{$kP$rmkxZajGDxb6f*KJm&cMJQ4VK`jXW(IZ2hx@es)S>hHiNVY@Fy~<>%qK} z1l0zvCX>N~i5!A_plC?}j|%e%f~)6LCQ$Xv&%pHwR5GM9y#$#g#-GpB4L7L(*`z|S zNdg>#0TyqsvvnMF2R5SI1dO-j z*j^O|9u{rTcv2jwh?vBbqR+soYKL3(f=; zM*Pg6RvM3>unhwPzaTScdS5{BDJVw@GlRP3f`a=%@h<}A2ni;Fniis9(}V?2gBl6q zprN;V1`$Z&kzfW*SBf!kT>=%SQp}%0p}2-$ff;muvY;X;nJa?X41%D0MfsJ${#qeu z&ceXJuL9<*WZ(dK@v{MRaS$5=*J4Qq27Wc>O`twX0lzJCxFG|BU;?P$<_2an)C=AP zH7q=s-+(T~5ex%Kd4f5~f{Q`1-~~214H9lXpm1YI7X$~5FW57=3>;sW85q(Hp_Vc+ zaA|>j;K%&mfPq2Lft5d$xzU(`LGS=*iAES$4}+j1h!f8I*&vsJfkp5JC_zUsgF2rZ zAZ1?^GpO*~BKR59(v4;YCEFc>S|G>8FoTlm9ziCM&tjQDY3zWYHYgI~m_fDJ5kYX~ zj%Nnt`V)fviVO_=iJ*{XI3xIO`gu+cHGR-2Sp2DAe|-^b0i~`qFz2h_0wD$l{&X@=71Fnuqa&v)uy>%uL-g!fqSueV4e_* zk{ihUeC8@81_luprBsl=3&5sWuqbs;pT)%?t=$0X_7;N$?O2rVftoyJ;DB~uQPKp( zK{YpvK64 zX3*KW>K;4{3`{qfm_f608i^n#Xmm~^3B&@4X=XAo-DUzUFl69iF*0Fb&;oVtwOc@= zQbnK@Gz_5ARU;Ya_?j{>=zvOP#v)db5umk{~_)1}l(5!A6-k3otM+R>KSdoe!YNIOjavlvaCTW>NOnSw~ zAzTkK3AEtKlrakAQiMq#v>6x}K}WbVfcEh-&e>${5X5!~jYb9N!tt>Otdvpr8RICeTT= zJS?EWIBO3L1_nm(kqe;HAsFX?PRO(cjkGZy1&y>Z2HAp!+8B?5hT0f|Z9&(@G9CqG zCB_h2V_A@1FeeleIVV8cL1RKDpzYouFY8-?9m%L~$6y88RS$9k0}l&maL;-*XzeEG z^g{+v{4maWYr()^0XqGV@yXliS^^x>^^hzF@&5DA77PrGp>XfdgP6?3p~7Gy!@vN} z8GE5(r3|KwkYoy$1|1Uu$}M+b(ulxev}P~^oqqvx7bs{z7q|1Uc=Ca=OjVo`1A|?k z7-%3HbPF*9$Qs5uHkJ$w_TU&{W&|apAIOOjbaW*&is6aT4%D?|6bBmtI+22Lj)WDc z(3!3z$e{xDBcxc70C!*+Lm|b86k{+b8H5>tiV;u*gNqRbM$kHIa516-I>ZlDjDT7` zMlcoNVgz)~I|G9WXfX{a8eUj}qk)OT1QA&5Rv@wIM+G@VRbbu+l^AweAX`BPKSECX zVVv^?;@p4e&NW4Gt~s)EL1&PFw(v7rGj6bgmU@R^&V9?oz+ePZ0d}qgxX6Gz_XyZ& zQDEl=FfcHHBJVL+Z2CeW4$*oP=dystvO$;VLT*Q5oYQCx3SD_nY5^}rG6$U!500>K zMvzkU`NIj>|vY)bIx8CXn?%{ zxdx^L>>6QkMGMcdOA)Stl|~FaELqbVL^wq2C)vURXdc)RMyw1Bx}ZTl#(9ub7OV>z zerB8p9=c!*(FF}aGeXqDGR#6okSUCi30jgN{fpa*dkhpCN zD z7)V@QVFW4t!-}4AZZO8%LA}q<2KBxb8+yV4wJMRyiy}L)?@Lu8TEo=-7I-u1Yj1c}(5Fa!W59J>N@w25F7#LrHN8_KfF)-+Y z2ILuEL3|XZ0~(NLd<~9j4t53xUC@|3<7@DkJX8Hd2Hit)3=B|trim<&;_@9M$RUj3 z;NlXrH3FP*zA(nvL%pxg4)uNzI|G9eOa&6he_)qYNMYFCZM_=B>fH| z&0M~W2`10z!C(eDmJF0pLA4R+<~SafXVWi;b4apHa{#4;>F>ok#OgupYwXad2A%f} zDx??{nJOKie*FUTt2_q-gAq&x*soro1>cC~Q;!4KuZ(sKR-hw~KvpyGuz;o{?8HG; zALtHENJEuzPO2jVgU%Fw22ln^b0$!0Ig^8d0n%DFXG)zuQ-VW9)gII;umX3VnI}%D zcMJffXb4|H50qILt(mf?Ka$|kVSG28Uy?(=9&~UTxZhyU;IJLkZc74>V}KgMpa@}{ za|C29xQ(6!wzY?ofkBU(je&tNg$X3b7-a@(4E};PdqJl^^00vVu?`B%3=E8=&?S5f z46fi7uY(fKnC8uI{Wm)%UJ&d?;ZfeV^lZgVj(7{OG4lMox|oHIl<iu01-lb;!Wh_{cbN2Cpzd_zhPtzmn}NXyrULBFIS_Y(+W4SQb#wu{6O>0m z2@8}7;~_#!h!!KG1A`f;l?Hb!=-eM37O&}!G902}POcz#fdcyzIIwqfgG%G+IWind zu^>69J7H}x#@|e!L|B_GbwFVc4%ri^F23#x4_Q$C2MXD*)7Q&#NHVUTeo~f0mhA}G zQPbbZa;U_C*yz@pFgLkDtp!ccf}1zSyy)QsS}}rDOHFmduywQB^bN8c67YZmZ4cyO z0nPZ?fsRaP3;+idB;!nVXJF6;7b^kafMN{N4U=SGU(G|1ZRqt>9+D5 zQgEk23VYDppxp{#P~il2DyS39I7illfkF2HXwOe6GiX?ZF-R9QxXuXWL1VO>8KjOe z1m5C$2esb^k&t*iz)oTU)mGpxl5q^94}%$~iv&yYkT3(y2ioOIF)%Pr06PTI&pq$K zz@V!-ol}8Bnjh?fiOgX4gy`x_H&)p{jchJnX8Kn~9J1cwjE z!Jwi9#%^daquCv)u%(;!RW$Z1*$VZRx|LhtkGs*umhbk z&*+9^r-&~DgDz;QkI@ahLXt5^S5%%Mj)Bn)ynGU7r#p(Bo-813(#Upl`GWn9W+!M? z(JluRn~6wvwom`9!XX)g?589Y^Hacn(nB`C7K{0IQ$Sh04$0&%(=${#6zVty7!e(R~sFgk+Y$Rxmg>lXtKL!R}&;%yqeDH!o#vonL3?}0O2rpO{G=<5y z5W)-51VRf385gsFW-&wf7#MV~s4_4xE@1&pWHN^9YEL&%;}ER} zSI;<>CeCbDK(C>faWt9 zgCK?O30VAri##YVM7PeEfr0TPOST}W9iXAIK?O>Z%tW&zEtGKNEv z*I5>j1yew-168CT*XjGiU5C^s22HZsb%N@mXJFTX+JKC6CV*TAHuf3B*dU0pFIYe_ z%R$ESfK-CaZG)O?!(aufkfF&|eR`rghiLX!kU_cZ3=E9_VBQ29`yXN~bSQ$66{Kz# z$XM7g(rc)x4h&YH(Qc@zDY^^{cJ-jV1v>hk0ens= zR*(#1uob8$1TLjOC(we*qVoZeQmRvfLlRsTJ%U>2!e9bQmY}kTArR~WreZ`9@4{dP z8<_^xNsuwq=Nb$QcHcqQRfdCy3qV7fjB{p!+yq($#2C&BS_Q-yqzhUG#2C&BS}X)> zZ$+`r3{+xZU<`o|b7etn1+_;(V-X;SbOeIhFCz7zY9AE5Agdwuv4}e8uoRHhi@{cd zj*n%WqZI^e!z>0*UoZwix?_t`CNGwtOkOO31YD>tc>HN8c=CcV%nTH8<|dGEn0`%@ zLpd09fiUA9ux+5;596H0aNG8v*tQ47w!J8}?SdAAmABcq--wiupI7=0hU>HtXl&J0vaL*&76QP34#SVsQ$ET0L2!l zn+Y2S%?N?Dthw1hEo%{e1_oWw%sV4D8))X8F<94ddW$xPK`clmbR+^4lOV4%inFPO zK%2Ox{Lq$l0zU(T5ljWRVciWnT9g4ker_28_7Edd3o?AVpbk=308$Bp)(6;S>M<}d z>VWzy;Ctd3=j;z*V9*6E`(o5#15a2%OAG@xkjyH6q_*@{s70uQnV>~vcKboy9Y3(K zptFw|=j;e&V2IEKt?ps;V*{g28ztAP>A1s7)(HoPf%QTK!lLHYc32XVbCGs z<%ks8#XNaSIeq{YBsXUN6Cz*vIhg~eeE47#9YM~o%lLjf3rApR+V_y^XYW&^2X z41u`00_*_(v2d~z|tKgtAiFu*)fCKF4MtI2AwXNEyhf&jFc=iV24}8L14cf(Riub6ptBBA|69s33wgb9F#%A5GBE&fQ&2w}X* z23o%&Ai%(&`vf#vd5aCS1cotG2b@@Mvw;=^bPF&r=zy!eJ8YmzdW`@B1EfT`&vtrx zfdPjGq)7`J+6TFnD-!Bf0}e%SH6j-Yb}Lf}1ENi93l#$o4uR)M!P20+ErLz!A+sXOVSos$u$Q4AjV1f7|}I7c!X7QR93pjo{TK?VjLaCio> zgTk{^kbyyWf(iozqgpUKNHJrGE@+tzV+cEFZ3|hjSH z42;2$EEK~IDkt^96Sd$<8rIR79t8>AKqF`+y*dgKx*YlpCZJ(EQ0_kk6+_h0Od#n* zXh^+;Npm5FW1SdGK&ciKejL#d6N@!K(x3q!aEAhP4-72(K`ME3&pq3w?j_Pf&+jA8i>R+`O@hIlL57@F_aK^(#8j40F2 zK!lLn9?lGA$lXhbv+jc0Lsvmf&P8DNfNn`=oU=EEfk79XDHeevjWGz~x<%}uMJ|lN zkap-|_7{?%=!TB{En^31gO$ZA!I2^j%byG;uu`LXy1WUr|JD}+4m?J0L@BlgA_Pvx z;E{wFMsEf)(5Lpu`2POHYHH1FB0w z4dB!4)6bf4Xw_q@QLnIP#zJe(r>mJld$OkZfqAyN;L^A>^*(Sw`-ZUnqz z*NlTYIZg=brRfMpDVwDb5lK#NougCXP5d>o*qXN)1bptb*u{2ZXQ|FCH^K@N~1jA4l3 z2v~x+9|uX!^UXMf<3Z*1C#cIjAS*jSnN%Pi>{#S##Dl>k1e!hxiSex(zu%x{!xc zVD3L14{?9DIW#-ogE$A&0*7@4{y>C~leGiF{n7~#-<2XQAuwYw1GS4_?uVp$(9%yk z15m0D0>=*M+A795yon6Z-b+vr#0NpTpw;S(LEv2?jKR8EprMLj4#>&}-7lc!86g~? z_3p6P3F82FbdX{PR)(IQo^QdSZv={$dk|+bx*!IN{y>C~!~n=jA*~b!1}jis4U}T7KE%9%)r3*9}KiW zGwd$SDxibrn3O@{3}65jx8Vg%;;36DGcd4%7921zXqB-rFxbfJf*SB(Veo*R>r~L8 zWy?U7v0D~sm97{IXpx;;3~1S&8VhJ~90#aEtxaZNaA$D42pSwRW9m$1V9+W`W?=Am z%E!O}!tCCjvN8+|veR>|IV3`*RT&sSnB$IDz5)XS2y?JAdTillU;trOACH+j3=AO5 zn&9zUkbwb&1ysE1g+RApFfedN@OwS6VqgGa{)sGJ&vZd2Lf^9HkXH&?2AS`%-(QAPO0|N*P9-hAOeYx251S3V|>G1)A6Q=u~;1b{d+lE8enI|!&EIuW% zBr!fGHE%k<43Fq`n+6Vt@M+PttkVl3d8MZN?GRL$E@x0Ju>I6^j=a2je$X5qsPWIh zz#xOf2CedBgo@iEiTfh4laSc?NbDLUb{7(R0TO#Hgbk|57#MazIN-lywcI1J$F6R0D&K~pJEwh$6q5{a#V#8yXQ>mjjCk=Qm!Y-cbV6#k$K8^IiK`eO)0 zVn-mcmM%#QuTA{*T0FQ$*w%UL>{%5?dOH4LSt_X0axcxPc-= zJv{rFBS{1!vD1*)ZAk3NNbF5W?0rb=Q%LMuJ{TDOKsccE z$G{2d{6k$Qj>NV?Vh2yZ=*#JzxE4uh7ZUpf68kw4n-esd12Y1uK9f^GtiTw$5Dqwq+L72( zk=Waj*q4ylUy#_0phhUv5u(!@{WAZoQ z;*t}Qgytc!*G#t!G(;I_0#ii~b3B5#O zf7hPADTvceG77XD3Ti9poI;pU?b8K=Ij!sOB1ykOV*fy5OM$u)P$M*u*j`BNa3ppr z61yFVJq3xq0>TClPB5H;aKMTF-t@b{oZ^zapusYzol;0_jp@80ocfZ5NJ4c;?4IeN zA)MBpkC24kBe6L_6VOmowUO8sNNiUmcI5P%A)MBR>yd=^Ah9nXvF{+UUrcum2llSo3>kl0_Q%Z71UOWGPD(ySK}J7aob80YDFKhPK))Nt@L zIFy}hCL}G^{u~U)Q#l}bt`b9_*dy&|ukl5Fe*r1bxV7Y)1bmBQQNR zK9PaJ8Fc;+ltH)u0mpWAhE%#6QFu$Ac=1T zv7zF-Ky0YR`=E{h&0c|yf3swSD!L9*1ZCd=v7s6sAZd6B5{Ih!Fnw={j`;MNNKT%5 zThQ(dsQM@n8|r}+5F0!;$-t0d%D^BDWfz0Qp=!X(sG(*yA&K{Z*ii9_AU0I*Y9#hS z5Ze!$hK_?cP(^n^Y|!nh3=9m9L2Rh_8zlCBBsRYpBArQs*j(T;ghAGffk7C`)&Pk^ z9c=_+Lmg*s21-LvMWB<(8KLYDkRqstI1n4Owg7Y&D#%bMI~ODlRZ|XPLk+C~v7u^O zk=V0AZ14(F28JatHYg3Pg>e`d7&e30P|e4X*cU)-sAbncY|!b$3=9mnKn{YkpMu1p zYTkp`PzQYhv7u`IBC&S?Ezv#E%O7hL5n&V z7#M=g85o42>{yUER82aF4Rufshz${UW~c;lpc?v+*z1tkM?q|e28PohHh5N>f#E#J zGXCj7F`QcUjG)nUs2V;bwgiX`wOAI!hUzsyVmpA?P`z#-Ht4ctP+!r4fk7C`2A!P` zD>C9iYM^GOfY@OS(|^Zsa>1JTbr3OdLhJ^yp=QiSV(&v@-$i2o04-$u}u>!H77TAN>P;p-* zb~F+@6Nz07VnfZWhng=9@_#=_0%|CDeHWBH7bFhVun?vJbU!;t9I6I%+8iTP%~6mz zlnojhg^7O!i9;OO&Fg>lxxe5>O4PAU0G{1roah#D+SeAH)VN6=Gmu zm<%!q%AN-jhpJf#VnfYb2Vz6T_aL#4gV;f!@MmCPxB%in4Y~p~6touh2}m4j5O|$C zl>G@L4psjRN&SD2I8+Ur4FdxsRE;DOTN%WLI!LP?!~umH0|SGe4FiKPlx+zThbnRb zv7v@~g4j^;5D*(G9t&ba^(I2i0dWgK;!rhJNNkwBVE;EGY3M;xG#SJOnZm%pu*`;m zff35y24X`Uu@}S!Ed^s>U^oae2g*JJ5{Ig}4q`(caRVnZ#~07pi9^-Lg4j?sMM&&PFg7Uv zZG>?^1rZYaJrbME0pV&v5F506nSp^p)PaFP7|K=vi9>y<4PrwbVE|%7#jQbXsJM#* zs5J-G>;W|hw6s0~Nl_vaI}OB!s?S1FUknn58d?QnL)G*mvFC!=P)95Qu|cbXL6^#} z02u_~Fl+`%Ko#u+v7v?@2C<>yw?S;E_$ws#dk`C{=06gf#}N^7GDvK75F1wh>wq{= z&E_CB)B+n28|t_k5F4td9mEDr!!j^1bUQLI2t(P^K;lp}3qfqCIm;?v zJ%|I9xCUZ_)=z_4=^#U)?57}csG1KTHq_9sAU0GSbbb|DatB3=9n0L6$+;hmaJV1+k%qUIMY9njavs-yyLXK${Ao=CC+3FbFF! zFo5?Cg2bWb$imt63=B#j4pf60k_LT{I8=ifhz(Wag~ZN8Vs{|1mx9<(hpqv!L95jn z7#KEy%!jgfgT!I&|6?Ey)UwkcHdOOXB=&P8_D>KSYS3S(p`g_Oye^3PLJWy54Pryp z%eycz2rDu$fYjG(fFz(6>x0-(MNUZU1SEDjhz)gI9f%Fu?ZUvo&;&9R%I*b;L)FXx zv7zSA1+k&xt08P~`eWD$;egT^!)Xv3YS4M8p`gCNeULcRpchE&w;(oD{YNDAzd+(p z^^C3z42)1UB1mi_S5Wy6mGA^fKwTFAVk?8)!w}-iz#t4|$AiS7YO+9Vs0H~THdMS8 ziQNxkL-kIEngjC8VvsmUFUbFEU>pVphK(RLRKr#z4f{aiAPo!*3`aq1sG1u{>~BbH zb~i*Bzz1T3Y-M0z5OQN+5Qeg4-9Y6()YTdwMNkW@L2RhFFNh7*5D3)_;wFN`q3W}c z*!dtfNC5)_Lot&28jv_teKUv+QB%(_4Z&g9g2X-zVnZEq3B(4SNW{Rva1CTAl>HDS z4ps9WiTxLe&Fzi|2}vZjI+zU#e+C8yQxFGgs0R`|4T;@~#GV6ULoHqmVuKd?FfcGI zcV}P_hO#$-#Gz^qAhFLOvG3G_I8Y7mk=VQ*pjEDr1gHXHLk-dfu|dTd0|SG;2Ll7> z0tApME08!;jRz7t42hkB#4due!TxW6azF<4f!I(B79z3tBe5@l*ig%^gV>;wgn@zK zHpoFx_A`(;RLw^a8yffDKy0Wuizlf3hjN5G5%Hve#MTC}p_&aqY^ZuWB(^USI~v4> zIwB8=-Gjtl3}S=Lsb^qV1>%4fgflQOtn*}G5QegMg2cg!7#NNtv9BVrA0x3pg4j^K zzmV7hUJMMdu`x*`wi1Y44;?f!1#zI7J&@RGNbFW5_8br!>bS)qwiYPz7#Nm&F)#>2 z*_%M(P&Io&Y-lJR0Dy zK8OTp17d@g+%hmQIQTFy2t(Q4AaSUVBaztYNbFK1b_0kF4fa+L8*0uB7#o!TR)9EA zL)U}YI^cj{*bK55%H9VOhpIV)#J+{Zeu2dP3}Qnq{sCe`&EfV1E%1YwFYSv|{wskb zbRiOIz6=b)P_`jR9BQ#W65AJv9gW0J1F@kNXM@;KbLx=T9UwNu%zB1?5C^n^6f~X# zvKY#q2NH)UVpxO3-i5?IfyBNHVnZ#y0b)bVd5y&W3SvXe`~za^gTf!=X+H)AVbH1k z3=9n1eu#7+iNsb%Vw)ndosrmnAU4zy!5}u&vP2|y0TR2q9>jraXaKRHj+l(ZUJPPG z4O#_agZ68I3M-JKq3oR?aj2T(NbIXf?8iv#k5D$)|No&JP(bkdBYZCbVnZD#3t~ep zGeBZHfY?xr-9c>7t~Uk-25)}`24N^W3?vR!lY+#~_Xm~#Pzy>x5>O58NbKn#HdOOG z5F51R5ww^aWC4`D79~+6T}AVt!H3(1LrU>`~k6{1~CUPFff9) zIn?P)6$+#PdeFTYp0mO#tt$&QfVGLwo0L^WJ(t!ks4YgPv z#0H(;#lXOz9LT^R3}x$q#Gz_zkl0>G>||au6G`@`qtH z$TBE<8%P|g<_Hq|5)%6X68jwz`wxf>HAg!Lk-&{W{eMQ#Rtg3N2D2ar2G9f-$oGy& ziu{q-u}JJ}Bz7f;4K-&8hz)hciT}A2bx$;f!H7k z1_p*3NbF}w?EfG(R6R>D0|RIt3*=}CB)0i<*>XX+s#yeLL#9NKrQ$RwG32}u!bO-5`0K( zVGtXtUOWWiIFNb;kT}#q>L4~$jTI6*0*Rd;0;=7it}X*ffX?_}U|^^M846{$g2bU} zCL^)uf!I*X7K7MO_1lox$3SeT-m@UKH7FVw7%qa$2eCo^zXOthDtd*){(;113q_z5Qef3fW*T<;m^Rpa1P9Yxb6-T`xO%V z2NGL2oPmK6YLE;P+X%#ldd3=w?SjPi0es5F4td3&e)1nF?Y<#b<%oQ1Q(mHdOo|oL$era16wOy81j4`zeSGjmvjP?C(fy z?nnj(MyOtSB(@zAI}V9mgv71}vFo9l`#~Hidj%4EHxm02hz<44O%NM&QZWMq!`(;* z24N`s1xOsK<}-*5_3;l78!FBmg(y|)IY1n!gcuTA1&M8h#CAYpM}ycj)f_CR9Cf!I(-rz5cokk~aKHdJpv5_@e7 zsQiaY905syT*Sb@a2mu0o#4d4z;Hf>fk7C`z6BD8s(A`xLlf645F0A~1BuNRi}08T z5?cwuu4ga-aiA7h#6m0s)#V-_ai|4>NbE2W8>&7ENqsU%9I8GG#D=P=MPkoJVy^+Q zVdej35C^n}8#K)TG8D=_1QLh(>@0{4wcrwn4HbWY#C{E8L)Cl%v7zStfSL(fRl*U6 z$bN$LNE|T`8>&Gnj)4Jm#vVw6GDsY1s1}F~Rbz|9_64z_4hjLWK?m(IFfc@b%z?6# zLE=y~g-|vq{V{+Y0hQ>5N`TVrY$Wzd5F2XHCM5O=5F45RFCwvTA+aBT*igNnk=TOq zpzYWE? z*E29|0db%{*o(wIhQvMtVna3GM`Hg)V#_2jFfc;Z7=zeQ$60~cp!0bd7#Qpl7#M`1 zY)_Cltald<;y^W|BC(5+*o{c+eh?dK&}1_nkbTLp>jjKq!tv7r_xg4o_*KQg2yF)#>&*dYHGAW2jr zvAaQRsDq{;vF9SOmw?z%3s!^JphFozT}hAyQ1&j6I8@C^5F09fHwje!LpjfoB;F&j ze}dRh&4S5@G@*&aHU+Ukd#xE580T`nx@;S#xaS5Wq3uZQ-AL?1NbF-s>~l!$OVexHIK}JlA_+Y~V!uFQ zzei$!Mq>X)V*f{Cv!@_}lpBdHjKmg)upxVSI_DU>383A`ZH!s*Zsih&-h?^Er|Lt{Va&`nJ)X0)1Ps{^jr{iWcpqZb!R&7 zCr*DR9-HZLpE&)PRBWcN`^4$T=rR58Cr*FHoaw%wIsF-1rq2aYbEdxqQCp_le&O_I zyfM8OM17ck_Y0>#6Nl||y|0{pi~-YYzjA^ca27;0Oqcz}>Cf0RJ@*@@|8$uTDIC*} zeB<}k(??1=|PSflDgI#d;Kc_$ApQ*B3{){nGbGiH(H%#5j z<UauFJyZ&&1;~y^e+J7^BT}S5_{6#t+k{f~YIgpR#h5GYNQ2k7MKV zV_Y+REgP3VDDptmoaw&o5KBOm%k;M(s$se<2bVwNo9VqEDrNdz5Vd2vE+@zizv*?H zTz-rR)6a5(HOg{v`7??5PtW7x@?*@HzL$&3pV4GGFE=!s%83L5cOxe zFAtYLqs8>OAZpL_w;)Pmx-BmkDB1P$g6s&Hevg;SkFjF9E+3aaVx~~|QKjW3@b3v5G^tWOlOOmJC ziGwZa73Tt__q!nK$8=o@E`LU!>9rDE{!9{S)6Yq8`7u73E-T69&p2axE{HOjzE_gV zpNS!JI-e9c=wqe8LBAG6eVG1Nip!sgBWt>!G?x~m|MW^}E@jpem5dBmrY{6B!`m4c zeotSxnO%7L9ceBB#-QnMrMc7@=S&xs;ZkReoNf!E&P-1QQJvF!Ww_Lt6uwX2Cc~x1 zxN`bkkZ8tqR#`4}*67^~4Ev@V%5o_)N&cAruiQs`daf)NKV!)BT995ej7 z!qfN2atSbAn0^){yyO=H!;9$)D||$z^U87YGk%#aE61hI+QZMtpgR4dG?(!71?k)Z zj9aGXf`n6yK<+mDCMrCAf}%8sU|PCfzP^Hjf}x3}k%5t+snK-9jY$&Q@5*sWb1-h3 z{!@+1obk|fLv=2#h?8tC#&auX{USgx_{0F|LUxtVzkEZ4ytCf8}CI<1_qW}Y*#^tT`+L`VPIfjxjlWeI@cb?hV2C!T;3XN zP*)tBEiS(OMgZ4LCdm-iP6h@Bu6dw^_IVKYb|wY}*7EIL!CVh@;5r-|C0HztO$??B zRw`&P-k*LiKv8V_nFg*M?Da#UwsUd}3{26C3=B*{ppGgtBZmbq=8gg6Z9K z)lM!29%fYr24-E*(Qr(n(*rxX6vVB?7#LX8rZ6xtFg+GzU|`YM3Sw$Z@95+*bT>3& zU|>113KWWLJfaK?EGI#1Hnv1P1_qW>k&Fxs91I-u85kHq7kP4m2nJ>r_G6$st+Q1b z7+6k&4jki3nAXLmD7#Oafq})6aRo>d=oAvrMatl#`q>${oTuA$aY+k;_AjzHF@kRW z;d%*j%=B|N*~OV=7?{L31Q{5Z#ZnC!7+A!X$TKjo zGBC{sT@M}5}x#%)8FfcviWnf_U1Sw*g zIQ?BWmwLS#XwQY%2GHrEVu4~H8~zJ{Y*-2kHnG`y3=FJd7DfyVY+^;K3=HgI(?Mxd z?4%h31E<(yLk0#ev00#-$;3>w85nrP4y!XT@QO*vGBEIoae!|26O-g-U=R@7EzQ6n zD0WYZfk8+toD;OX{1Yz&gNRuD^eH`D;`J?t3=EQDxmpYiQer&%3=Gm@rg{tvGGb;N z3=Fbje@z(}b2J&b8CD+7bzdn*P8_Hf9Z41yUZ3=HfM;AOT2%gnpU|=s`0;yvV{KL(_z+MElT0t;D zk%57|4D2B#L32h12KI8M3}yy~dKE#?g?Q{0V0%&p3qZzJf;njnT+=}lku^*^Ss56( zc+D9Y*tx)GiSw|4?y%+31{o8=3d$s0Zy5H@H_9=kC3ctm~~c3ZYp zYzzznIVIT)>~?Hd7(wI3f@yjT4D9x7a~MIFZ0-i>b%2~YDR@DGfq~r-tXWFX#gu`8 z-3iQ*X5hLA3Rh>gc+ky&66|hlpbJ$5*;yDE*xlJcr?WE%@_}6E0k(t%Vv;9Vvj_v% zCXi8HY}?ov80z^&*nQay*~U0nPVa4lkGU|`Q+ zJHigS7z|{dIOrB82KH@iAsh@0VxR=aAXWi7pkEAh>}v@Yj`;Z;3=EQ`77QE-rx~W-n!qJl|H_zwfg>3tE~To$z`&96 z26UDc_x)FGO(>yV_@LO2AvAU!se#Tz`&6M zVzaSz2s1En^qY68d-2BtXedIkoL^iLcN3`}J@3=AB3 zAeGW0;tUKT90d`a3=C`)Aj=9tOa``BDhv!9MRB0|n=R0Sfq|nKl-@YlK&1pn2`D;1 zSLzCIf-DTv8h!%_YRWZn%u1_q7_kUj=BW@ZLA298P)hlTBk1Oo#{ z6-W&Sn=i=q)gYhnu!Vtct*v3=Vqg$p%i>{R;HU+O`><(gGB9w|32`wn__4`PH=o3% zT>njpfq|nLWLyOU4@(Nj^Prn5L2AI&7!w2d{46CdXt?q*FufIGVBl!Y2RSxWmw|y( z{Q(mLgY;8F#t7hp>iXJFt`Q)gyi5Mcuq#$4(kaS68hA`A>%8X$2Q1}0aKL7FE( zP8H*4VBod}`GHA9h=GCI<1~X70|S$+1Oo$iC`g#gM~#7j+Z=rLI}Z!UG4yzRO{byGca&%mtl*oaI zSkTFBOk3m`7FJkwDT1_qw< zV5S!6{_QKE%Y2!{)EF3eUVt@&?^1maW@du4{R1)ix!HIG7_E637(kVA?^G^@dU0L` z23|HEamGwu1_nM*eDX+uFP!JwF3Z5cBMDZ`z~y4iz`!HL=+4W)z|YMi%Xk)KMjyya za*W?V8=3|G3otP7$b&E8VidGfVqoA=0CSiGIdvEqcoe~xbukOtNiZ<*C^0hfg6`q{ z#1qTFz@rSdo0Wmf2GlxJXDsDqVBmTR$_rtPGeHr^!V}2|x@JKjC%>G5Ckos`WDv;6 zWZ;PgvzZvUOw<_|cw!l!g51Z!lfdZ8$G{+%GQD#emx9MqZcxjeYnK!Q15XO02IUsjcfsGJ>xT_j$r9?dgS2*ad`x?eCAd`YX_SZ2A z@h~uOiGVy<&-e%wWI8;JjDJ9;h6*t-@HBygk3ld>oPmL-87#pf$YjO9z|+FWBmlaI z`m!kl15Ya>2PhH+lR))W8zY|ps98~?&%nUb4pt^2xDHg0@pOQtBm_@@;;R#^Nk*^) zJ!Q>0@1)HEi;;O3$HKF?%J^2|JxC%htnaF4%z`!8vEWp4Z0?Jnm zT>Tad3_O#;!d#-DbUTx=8Ize) z3=D#Abr~3V)`K0*AeavF!3HpAI`>R2&iZr#Q1YDxO8=V}{RJ2pSOxn*DR47mv;YGG z8^mK<7>flM7}y!Oc7S}bm9bucfr0CaCIbV{Nw8&Hp`buN4`FA4V*fs)4JabbL2CX$ z#6ic3@h~%iaxYhyIRgWaDAQ@sR4uOnk2q7LAOizmIjA!#0dAl2tuX`TStd}K!3R2( zibskG)YW3(ngnu!G?TU<0|UPTk1W$-K?Vjvb5IJ9W6}cW-!xFgAa!4;*z&*202EZX)8!r zfJc+bK!|}s@HXg9VJ)x=83gZuGPX9@Lrj9!3JeT9I^espSOiU`H_qac5?l$2J_Dww zAR~BqjF_sXubIUq$7ntM^eir^`fH##w_vgnVqoA^;IU%5A;iGI_Y4#f)=Z$HoG$?s z<2Fn;K|%A7g@J*`7VHSVSWq0=F|7oNXNoc~@YqAx@}SsvV5$O5?{Vpaid9FZHX#NE zE+tUvb_P3?t5K1GfyV_B@?4;8**v*m34TVN0w#H31_nXUQGPsyOyCsAz!eHA0g9M7 zgc%rQnHhOXnX*A@z@=+BxHkkUfEgHgDwrNHg3^l)DDhM>{Q}>Xu4V$Y%(-5H z()=1GP}`cz3sm&3Wdb#Yd1ZLkGYN`78@fCjn3{zd82EmHe7upVAH)VVba^&0Z3eMH z?OdMCOtXa<7_`9+U7jsW%Rv%d+zbpnTfvGLxN1RGZDZOGy58M@XAhI_^xipK+Vz^C zjC6oW7F6^91Csi?*o^{=a<`^0p37xXF99mso-w@wX=i5S zdBwB`uKhJkJIFt8Ag&c;1Vz(Zrky+t4FBbLK&kLOIMx{$8MyX>qU|G7jVJ>HKReGC zrZ;e-zCw*U$H>6I^PTB654bzBGKzzN>nEtTU}pXSGKrmsjX4c&5 zJ{toAS3D^4)S0b8Y|!~O7bi ziGiAda-b`(cs#*!Jd6xno0J(Cc)Xa8ft>vvWMnYdL;UPKVay%k3=H*^8cDPoq8WMJUC1u9I7nL(u*p8=@kE@1|hUVO7awNfc_Jt(*E zy#lpC%9ue(pKm)zLpd`j?ehHtSx~_YN|t<}19y2U!Rdq#bkj9Y6*zkNK7b0xYH-l- zodbn%4cKdZqM$@l3w9{qW>7w<0|z+YT~Io#2PaTIXU2L42A&3HPzk{YDv)>@nL)Xq z?*zzoP0YTaG7WV8I!`k*Xpn?~Yd*+DEzFJ*3=CZ7L0Pw**+7zkLD)f(fkEVt5Cek< zh{eFe0`fdp7s$gC!7MIKeC>1#0rhg7ltb zR+9o1tA{}q%_%U4UGNAfyPsw@k^(g+i&z;L>UqvE+etAna0v>4vea2Hhet31RQjG{ z_L2e(_<>Hx<~h$CCdI%Yz`*4O3j7PqNgz#!Kxy+f*une~JP(+6f(A#yRl-B$wEqa2 z_Gf^c@)(@?IR)3SF);8v~U(6-R_+Y`2`Ui3ft4^YaP2e%mD9{e zK}tAyelbhRfHEs6z5Rx|mlxF9s{aGlz$OUJiGRU4k)45y1(fywF~5*zV33tzd<-VL1Y7xiQLlfl5?1@Fj9AjBlLR9JmjI{|<7H6=9R)7J z$Roh=8tx`RWH$*x-2|@Zguy*kP}L?4if0j)9Wo3I3Nnm55-fJ00q=TQP*Rs<0YxWY zJE*>pVgZFF-%e2CmInKquL+dMWWe_EMT1&{vMiwBWZ>ceB~p2o?=lPwTuGp0sl*Z{ z%fKKED(ppmfpP?h#lQo$i>nh<`KhviMr63eK@D0BmX>;u@|m)*9y+KlgyybdP;Sv@ zSkz24 za$+$6iTi`18;gJ(1B0*$SR9_|!C4yAuLqAFK;5Pc zO3+>`4j}cRAoagNy&a^YVJ)ci^J4+^gt)e_GBEIju;hXiSAZ0Q2++8QECT~qy%Z>& zhOu;kWY>XYmx2OgBZ$}wB2I#cs~`fD4j8zUK?QvS#B19?1vDQkX#9&y6BHCO;E`&k zgSre1ywgDA8KR*6Ap@ULy8;7);zZCOA){hD=x91d#V??#EXI1p?R*Rj%#4aG#taNB zjEW0+85md@6}#9O7}yvUzbG>>urn%pfCe%d71=aFb+@9nH3I_|qvCEQP;IUF7Zf#& ziW6iQ79fkB8-vC^1?R6$vTfkBN?Q3TWnRA*FNuEM~e!KnCIkbyyyQ4y2@v=|lt@h~uG zGb(CXFfiyaDy|1z%*?3hCd0s>$EY}skAXp-QSrPQ1A_shBIu%3LqF zk%5(mZ^;S;&`@z%)mWfq`%BP6Y-ARzAKB+Mvmk43O~~!D{Q-at#<5_%>Yy zjl{Bj0ktvVGe#1qKGDW>W?RzP%uE zRu#Sj^WbJ51e?uv4>WRr2sAXs!3HWJ`3{2$ND=T*E8h{2atRK$Q-%x-d`HcuUtGy0 zUVokkbO9j`ix+42C0M|mgP0DgeE80T3S+407eJ;9Kuo^~ zGF^o2vM2)s-zCr}pak1t9R>!z%b*fQl5IZ^0|Vbxki(_eez7qy@LdDhEK|=0>UHzo z0Cl<*7?|ejGcfSoTn}=94Bs8lr5^0ypu3CYfO`-J^l>sU@ZAR~5nu<674ba)wSu8u zeF$=l1OpGtF3_y<5_Sd#zDN2>3=FISd{05gP(w_8mJe!6F@VQ#`JO|J1-tnL$jy8V zOw0-l416zJAsXMjf``XjB_UKn=@@8o@aI>MfgF5)qTmMp1slk~v`dSD zf$yKIG6Ms@03RbG=m2X0u#HTNU=`pNJ0CN6Sd&8#Y$XeLII^CPfh$6tfq{>eF%_g+ zh>wHutug}xL^mh0ZZ4>94^Z~tW(4&e_yh|;LCeFq3)CeN)CZMCyo{h8hX4Z?BS?ym z5p;kyzX6{hqk{^}SRsV5)05Y5Db#}aqH zP@SNPnoouiRH1S(aIF9(Xjw)d6^I4}#zk-qipUz2U>ZQjiSQ{i)~YZt@N@C0*E3#% zYtVpb5XdXdW#H2Uk3exSa5?CLhK3o}K{V(xGO5D+q6bkgsL9H}z^4x$Amd=*0-fv0 zXTW$5q+Wv0m~j?dy$Mu3X#RrFlu?$Afq{cx5Y$oNGXvYkDfn&rgtc6f^`OotpCwp~ z2NHi);27W)oCGQytidwEg6xb841Bg=i$w&%sn?DXG!!nzz!eTEh#VOCR2dlfMfjW< zKf+z%3UviIN4tTIwo!nA9edNVEqnJd8O z$Ec?U3k`o{a|58}N?0*4@C7o0>RLVqt`3lUgBbs+GBC(GF!F^lzJu!yN7fx00nsjy zlFYyt$p{)H;uGAX$iToC#RytfAt+Fi%fJ`S2r7b91VKlK^TmKukcJ>=(1I@(>{?Ah zaB__UCs!@OlIefeaY@#L#!~na8A0W>uH0V@1_r()urt&c;B?m%<3T+nJw_FP%|O9p?26WXESh+|IytgqwkZFN={&9h@_B8M8s^ zr%zeWrC1MQf@b@2K&_I`pc12y(F&wag0F<}1V|k?2bV(41xIZeBdCPo5c~!z9Lm9} zcmy9RF);8|FoN220+57K3ASF4frq66WH{(*8onyVT9Dxee6@@c8Vn2q5n$8npr(Tp zLOoa;hu}9*CDXtN8XXgW1ZE>+xiABR4g*&|sJ?1uyah5!fUlJ?31k%5q&ApI(|a~> zsnC4`$%H1fpgz?tti?&8Vgci?BIR z-7i7GH z5S(bvz`$3(6r6MT1n+_B!)0KOfS^C9=v)rw2nlL~I4i&$5eBYSPzke&(LxiPP}VS> zgr2c(&cZ!_ax&3c$Gw?K7+HEacI;9%f#1i5M( z<4uqT8NQv2iCQrAyP)b{gX-?xjG)V7I0To0D(^ku2;mVtV+m@4fH?w!8$p4$kFkQA zfk8y@Js$%D-+o5W^k2OM16LJ@dw`J>w7^G(?-1jCxFv^?Ejfa0$x*PmP)m-1IZ#WE zLoGQ9N}MOa8B|p80LUMZxdbtY^{2qrOBgY5odeZBrx`)Zh4^{+&NIqr!~A#wYCYIn z7r`;WA$Vqb!e%a!`qv=Witt@yEQTw;4psgal%#J!f)G5}$9EH~mrD>dlg)RF5!C45 z5uC%tz`%DKqMw0>1=L&N$_6?54x@%PICk$bZi5?sA8Pny&}hH|MpbaDKyV(YK7R-{ zosWTQ5=i$W##V^#XN;exOKjnitIq+I&@aIWf|G$u1k_e}#drv!=q;nI4$QmnpjLn; zbokzb4dnn&=f zm_B{q7B0ysaK!v#1T8S(6$DKT@%;wRI`M%ghWP$~r=9pAcKrq0B_L=3vg#k$1`!4x z7SI$H*L+X~@t@IC2V84$GD+x8H{8l4UN4~w%Am_Y1rQI@1yG+<5OhHgA1{-fE@<$C zhb0KqYi0pWUU8{`T8Dg0w?Kvn@Ch)1rl=up8bKyVi--f%>Jb8u5_3Qd5(XQ@!@%_h zRAz`U8R&vtAjY%svqV8i8+4Of5|&cHPlG-{y8#09!QfM0}9naN^$z&0+` zdXTGl1fPKHR%f!%g9L#N$Obb|3e;fw1+qbePlu@kBnh@b7iz;(P?f9)o^|37>;R=} zeejeS)I0;Id0a<9^{pY3mmUKHzYL!-6PrFPQJK_3jamsZ$`s;Q!LOh|H3M@v1@{;; zFz}g!Ib4DtK}}l=umL=R%RtI3nLum!1Oy#HC5;u6kUppgc>=P~nyCVO4k!-`XlQ_k zFLM=rPoTTx7@833rh_)Is1P$${xHcvcsj#T}u31D9M*V2*%b z8K|%0%=8{KjsRX9#pl8VO1q+hU^loz-M|&W!oa}i#-yUpz`)PL=fSiSYGFMCpC{Bt zum&%%1`Y-;X>A4uK5wR}APoY1zD(bs8W{Nepz3)*m5e{sg<#DAV9h)XTv?#F2xK}6 z(HzWVYyb=J5U6Ib`cNkDI0}bgEXb%Zurg46l_=>nbP&KJYv3eqLOm&mjet}6+u3*1IX22ZkZ2rAZt;xGlA==mV+ z&Q$Om4L<`{2B;`XXQ~Dn#l@G!^b&4VHqU4hF6hpc%z<2{a7CX9;S?%&lhvjdSo_w_sr4o6iJlG4m;c639X(Pz#yQ z6I7xuW?BNu-I5?zE@c9ZF7O=yWv=B+pe{L|JE#}8k_pty<}1@SVz=N=S z2biir%^e+3$R1)U1o>|rC@mggItR`Tr$MRVI1{LO&8G)SKqr_$?PI=eAjh3#0yTm8 zK$`&hPBDQRv3zepCHrY69gthZK#o4c1ZrFI@q-44&N6`-EPSS*RC$gG)Ij4C1obh` zGlAMsd>tT{TwtmM#Y6|FG~~O;1Zp$#od-!=V)_d*)CANnyv$?^Dq*uhKD)wn4#fTs zQgfBb4ivJ@pbT*hTu1Qz1Ucdc(?pPv5h&ztGJyw+0zrCjF@e_G^KAlk{_cSDD4!b0 z_jj4LX*1L_@EryD_#V?|kc+;8Y`M>*0&3LG0F4Sf0N22L$sjcknf8Ii*+Il3aP`Lr zx&fQ-36liK>?V+9Pr(H{UjZn=JOdY@eD0v|ehw~w`F?`*zF@Kh1(Y0VD$E2noIfxlI&ony}zGP@IW_ z=BDZypdES%W@v{VbomvZ6!QdA1_u5$d2MXQDgQuV_@Jf;Im~0-J&756*Q3P24*wV3r+@wrU&yI zMh1oi!POusPcSE0@HEJ1FR;;Rf*PRqsSkLPCtVO6G`?WZJk<~@L+5NGiWq+1EdiV z#SChNY!O@!DpR7FK}GZq!5g4N5W@^Ae)kB@m0)1ti)99tod*P$f$F+AW>D+#h#n;^LC$Y7SUobGafOCj_;D5qzGt>R;mI|o{5m;+WR zz#_LAH2#nawpoxx4m|Li2j&T}$gKfckk1S%H$_w2>$O0h zEd~qPvB)uiikdQTR5-B6xq@P;96Ukj#vC{)9<#VL1A_yjTqUTxIUgKKE{t-YrzafZ(yRxMcrOME#xlxPfQrN=U|t-f9C*-X zDR{w2JfoaCsD4-u_E-X=9Jq(Qk{Q&)PGOV-kB_ecTbs%#rwl52Rx^W!$TJw_&Vx$3 zHDI|MMmYyif?f-@A(v6E0JI*8Zynfsd5m(5piHrz8MOGefKjd+lw~)7oswfkAKzsNu-B2OQ80g5lFA9_A9R2gz_SaDYbRv#b$0|0}2p-p{OQ&AHD+(8%N=qv}#VX~|R-CD5&6rZ4|V1UfB zF;1|xVPFt@2)Z#qj0tovoY)OnZqVi=b7|0Sg8S3;j&O7{z`!jw5i}7i7S0UXi*yy#JrR4)%D})cRwfPFi&U%$+KZGc0NRTLx>8A)fvXI3 zg_|%V=u!(F7Eqz6!q39Mz^K6p+WQ8&;fHZfsSN{zDrinx#2z%=6~$=Cpu(Wu4!UC7 z0z7g6QVO~{opH_|8wLiASs-s)FltVJafC~TU*4X9K^t_wr-W46xg}4MDec8(dcg?UrMD z2NDPQi-7?wZgiW8fq@@<3%79+=)yE*P@ZQ6t@CCu{sr2krXp+2zyKA<0bRGK3Q8#u z0S-{2aI#}yFaZ@3mW&L>mq6FG>Ic``!Som!+A%PI)n(X06POT#aT5~*1LNvSgsKRT zD$r!g6qqVba6!bxU~J9Iz`%HRDMD?X9Rq{$Y|sUlcXy+SN`YMb{-Rwv+}- zQXwR^-1NP9Le|qg^tdIa`)se^;hl>lxqA9Tjx2H8vq(a>kk~Jf*y8L6^FehQ%vna$ z59)D?GbT{29lBNDq8i9Hj-2JOOSU|0&_fHV9)BsMrhKpl4%N&F=e`zsO~bhaMMalD{n5UN)a ziLHvnHsl7Kj{;R>izMNR#12JbCnB-)kl2+->=q<;KN1^UE<^3w3KIt%(|riW0Ubw$ z#D0v#{xN-{5x2OfFb^Vr<&oHiNNigqHfTK!EI>k$#1p6Q{p>70{l{l#9?$hi;=7R8 zN0Hdqkl3KU3CzqlNaEk8Pb^Fm_vGb8I8hOat%t<6L1G6Yv15_gS<~+tb6Y2FMiM%J z#0E8ZVXnA^B+ki)uwD*{t&POCKw`U1=aq>N=Pg4L>Yjd4)mU70Gm_8=B=%J#_RHyK zO}NFU-+5BZBdG@3dI*hQBP6!nbWv08{=`Q}Lhq5-ilDj`s!bP(?SjM(Kw`%ru``g^ zCDU2WxUCuYPIolp7FWB0B=ZD`{Q-&nM__v0)kHB{5kW+dDIl>;k=Tw%Y+odH)bxvH z+{(P2NJ7)5Ka2|#m)wsebOwoiYr3I1xBm1Rfg&DWWl(DY>UYEGmFC>aj0w|u1&hS% ztC3_TAhG8lu~#6mw;-_(AhFLNu|W&mVM*pGlK4j?_Fo7av~PidK?t-r9qK%V>8=*s z%Jl(ALa|8f93*xH61xS7JpqY52Z_A`iM<7heG-X%6~cxTmk%KvaB=w-iTx9a%?fHC zLftNe#P&mCMH+amgb{YA+(O?@wQ7$t`Zn1Zt~5 zweusfwUF2rNNhJGcF6R-dHLduh0}ShxRs}CxG@va!Z-{J4118+ zkC52RQV2)zBeA8C*r0&`m@kcy#O;yT-bn0lDF%k=cWk*c)UF_jK15=_M`Hh$nx19H zT~^;Jjc~~%BsOS20L=C^NaDMY*yoYhcahkikl6o`*gP@_yQCm&P=GNo7(h7S1Y?WD z_CjJuAhFYs*d<8pCL}g!=_||w^N_^XBC!w4fbO=07G@WaB<>=y-ypG>WD!2#oBmKk zRlHseNyrF^ZI8tEMq=k8u`7|-vyj-!kl34$*!z&!ryy)d0A7P|zybIOiTw_V%_@g* zyD1Vo42hkD#I8qTuSa6rkdmR#cD}r6mum{0mIE=(Tg~Yyy#J+*VzK_IyhQxl0#QuWB z{*A`Ekd0}^`<5*u`?0jvZ$k0gEviTxXi&8~=)8H5!PxlJC4 zt%JliM`DK|v6GP4c}VOkBz7ATdlHNd^8Zp8hk=3N2on1O68jDk`vnsF3lf__3E=@A zB(?++TNR1zqQtO)H#6E_^zKq0vfW&@>#1>FNILjEqh8%zC2;qQJ zV+suLzhtXdy&LX zA+fI`u|dm*U{-!Y5*JYe`xP_>&A^}t;eh?8kHii_VrNg^>&~rT4?0B$X5J1Y>7z*O zOGxYoNbLVeY|x?sm^u2OkzuHx0+HBpNbDjA8nc0-d9NC zJeo)jg0Vrz^65^`_2d?>kAaCXFfe2yvCELy%}DHtNbJo>>;p*bb4ctDNbG+|Yy~Z_ zyCB!r=t4N)P_sf}yCbnfkl0DnExkag2uWxM68k6;`w|lS0TLTL{{u}e{GhoYC|eeZ zZI8tEL1ITj*pO6|2H}9+UWLS-gT!8m#NLj?zKO(shQtOPrUi>kF&%I~fz4M&VjJin zb=d8u7kYDB8%{xzUx>tBhs55E#6Ca$qBpmA{XZljZqTF^G%Qq+*zQQ|5F~aI61xS7 zJrRjL4~e}RiM=1fhJ@oo2nX!X_eg9(J%s<|kl5NtYWLSoNHVy{7B??PhVL1Mo`V)Gax^_nCN z!7c(jLJf&+jKp?8V*5>B=*O*`*o7oC9f`dJiM8k$R z%Jt!(nMG*2PC;T9BC+d`*prahTaefXkl1IC*f)^aPmtIjAZ$oH{ef`6LBs)?Cxkjk z1c|MH#MVJ#TOhGrkk|o8>=-0=1`@l(7^%i-K$7S|V$VQgFF|5&Kw^W|=)wZ_1d{j_ zB=!R&_8S-*mN)?*)+9GDvI+X0E~gT#(NVy7Un3rvtYXEjI? z9Z2jcNbChj>@`U29Z2jWNbCzp>^n&87YKGe!xsdHfx#4!Rd|rt5=d+nB(?z(+Xjj4 zfy53$VkaQ6bHQw3aGGPN1alzl*6E=^+~tY)Ah9)(*k(v<7bJEh5<3lvU5vz@ zI9)fGTUqh|lF(Ts_O0oG!QA4EtkWBVxi{Be1g+tKCX0JW?AJ)_A4qIA3xwlEkl0E{ zYy%{=9TM9Ii5&%DgHkC2Lk5Hc4y7_Ab_)`F5)yj>5_=sIdk+%(6cYOe68jkv`-=rq zFM`Pu;WGgww*BNRpuOF&jQbf$oY4wl4L=fF7KyEm#I}U6 zApzwM;eZ1w6p5XT#4bc)*CVlek=V15*r5FZFo$kO5zHEh5oIOO603D?Z)BG1n zTn?$4GDc!MAhCUs*q~LOFmqav#JgZ@kpCyZI1CI7(~#J6k=RF(*r$=$7m?W4k=S>U z*pHFeFOk^qt&xheuSgQVk=TqjhQ1Ma_ z8+xzwR1h01UeCa=5X6CAzq}g621_t7YzMLRAO;--v7zE;L2T&#!`DG+!+{7LM}5smD>7Hra>a3Rj3=DIom!@$mGhgjunC`!sU3B_}G;RS#f$0y| zi-=FZk;W~+>e0=>pfEjAk5PD9IydO*1i^G}b=Hh-28NjFj3$i2(*x4E1y~vGf%q4% zC@8ZY>0w~tnclcWNtyA&^o=0J7p5~XbWc|lmlvM?A)Q+ocI^P;L@5atBU200=@;jQ zsWYzG?wi3atWdut1axjGDC$`lPk>I9;bvrD@G^n~BuE&9nIJa>Ftf04u?F2OzSXRt7_p0;6NV42DTS}bY|YQ#R( zXJBBK1YIV;@?D?7fq_{Hv^bTSgH_D}eB*!<=#**}R?xN)W)^l<(82mF%q;BFHNb{~ zHgB+m$}%vph=8tNW%)H-zLQ&l=aU)(1B-4o$owDEy*s%T#C63P7?{*Hfke&=F)%P` zTm~_nrZ;tR8%jo+FfcHkH~|u2*8m;0e-gxIW7nI0rjuJ*AWEHqf$6jnBLf5XN;3uq zrs?u>IWlbAOLRf(-j-Z(M%(FzUEI=wpjE?6PK+RLb6*A7GW}vpuGsYAE^am6zmg0L zOsg2bFfcIii%wtG#ceGKI^>>dJ!32r0|R#~9|Hr^7si*Mn<_p}|JB7Erv_?oFo@NH znww&v@`y?78Tg8UUeGBvVl1E&I~Z6lPp|9dme8!0WME)(2Hh>dz`(hefq?;ZJTlL0 z(A5(REWh<&*9@>2Pv76oE#~<^l7WF;?;&V?C_69c2zPxDn}vNj=n!^;=gbTY9PFlQ z3=HgsqM+mM*h@gCo*04H0_=4l^~V1h7#Kv@^`^`9aEn{(sW33Gn}OUe$H2=1I;WnO z1$4+T%VN+$`{p147SO>u9C;u$EXgVi3>=MMX5RFI9&Uqr(DoMwv0zXEDF!+ahe@oD z9h5@eSbz>EpRWSC>wpDx{Fm5zkPF35fNpybV+P-Kkgo>1>);RQpky%y(1~MWTfys# z4}ta)iP?g;kndvwtuHnOZF~@0ssLJF+{gmD>p+HwfkA|UWx9MXw?sV)XjO~Y9?&8U zF(XiN5d$qAVHWEHr3P zC&e~tf)+VPfHoJ3fyScv#jJTij(7?>&`L~32IL4QE|4Qm@qsQ}2%f&Jms`AkjWOuL zg=8Jjg$q9oKo>56HWkWEic3!u}^w8TJdPi?VcOVEW2poP}D zVur#BpbHncK^p-$`I$gb#N9PLzK>hF{vODmT+Cph$)F=cLs-G=<;)BWoOuv-0_fnw zatK?9gMoolm<^;xK!($nZ2=ntgCOW80Zu!%*PsQ}LZFS7oc3&+K^F-K%?D|9U;||j z38BxD3=Eu(V7*d8`sNG_oKE#%o-_mZPh$oKPG`1IHU$LT^|Y7&zV8 zK#7t;C=cX153nUH5TiW7nnf76*MiLQVgsGkCLqG;%cjl_bCe%gJ%b?VA^}c+usZ}G zRtJDJ*9$?63Iy|n8MvcC?g(Og32{d#TOm8l9bpi6K#U3p8wGVo1Xwd0#D$Sy8`&AS zrMMXwIHTB%LH7rUbH=c(133zGkpO2bSP6sBISz(;2F^IP9wr6`0ik1-3=Ev{Y!ew7 z7z7!(ZPghVI1|`vK^s+MIFr~II2aiCLHo`*lfhxm{~VM{Qo!NFUkM7QRIm;F8N3V( zoN3@7;CBS6NeBCZfqN1g0|RFU+b(tn23{7BaS|*#pwoXjx3PJFZV~{kD`pVu0j-o1 zyQctJ`w!}vGK-}%fii1`ASj=Jc1W=?aPQS(VBp*j_BF^51_sVUY)v3D*g$)`#Fm0u z+hTd@x1q{*T$t5qOb4t8tMu^H7MH}bHXOz)e-EzZjYI!nK9I_R@A`U4BXH&`dREj25D{r?PI$GIzrDHREV(ffy#D|m!LEHSrkFX z4upb)xy3+RO3WES0mI7z^1lEF&ostk+zbpt$oWeFt~Z6-+8?xBhldedr17$x z09Cm%pu;2On8Udl7`V5C%4|zW>GlnD#-cSd$VBeNpmXhPAnaz)wisIo+kX0vDctgm zebaAD;a02{QDk7?H3B(@1+-k1HwVo8Xv)CAI}c!vm0|W1Q zFf&x1fr0nR43L5cpi6pQfHluHW?r~q!Q`A+{gl{-{S6;yr2GM?vUU=ZNoO<>gL0|n^x%xT=}j6bGNoW`xl zuVKKzz?;dq7Ic9K19$rLgVVV6>cN8fFhN(4I|>*<+xY}Ic#9d&fJ{jRg-Z$8ZU!Me zX$A(~Qm_OI124-QJ_ZJEPLP5!#ucEm@@04{82R}b7=&J{GBEH~GJ*nl&xJCiXNl!g_=85nryfX{5V&3&&hcE~kf?Tx$#F_qT2DfZ|9VqfQGrEF~l@|hKcit_GvEXCnxz7kNFz{|= z%oJc?;69+uz`%PFY%sTjIVeFx*uH8E47~Rl)p!^fxV1rQ{y@Z!fkJ{AoCUd~EEyPh zMZs)70bX$?XVA&(psm8Z5==s%e8FF90ZPM6p!~!CWcrMm+=?2Y(Gy-dCK1qXFQFc8 zPr0e>js{nDN*2uQR#z8COnMoyD!k*95X$hY6foh2*Cv z&f=D0?44dSi(8MeY5Hmq@7DBVv$z%NlWiFocx{*tgB&!Im4SiRmPty8fq`Eg6i9YV zlR@HnVhjwt_7L_NEd~Z&2c{HI>yaC@R+rb2sQ`4J$T}tl23}{d7rA#TF);ADK-lkX z7#MhS!E6CW-U230VFm`F>k14EyoF3NctFEq4BUC3EKtPsNeFzFJ8vmdC`b`Fik)hpFZqQVRe+?}96T?V$B zdm6}1E15tIGj7n4J-n-!?y@l$FmU&Pf@(DrsBy#%THeaLh6&WV;f|DKVBlTL1Ztn~ z$?&dc`VBgD{q1y-Io$eEpcVx07N&_Hp#?mkG{Q6&G+@phH$8R^w{<P)f7g&H#DhEK?Gwo&2Bo0#mmL1A`FQ&ljP727B`o*qdw&+{Zzg z_cBwu2m^xv5ARi`6L9s{pz1+~8t`6c@&upAE|d?-t2dZHXMu1qaI1on%uS~0pd-~q z8F}w8MTx?!y9?DWJKc9Kw>m%Al!st93NXt3o!&f`+ak#q6k*Spu7I>NGxEM-0-eVS zaqVlEc94JGKwK;22@37EOpC!MvV)87_u#l=U}WG1ojt_+ktt1-fkA+s_Y2cCuuG=P z&g0gv2mAjo)I@M9`3H6hn-FNQi}yb`n%RXevVhJeWd0 z+@QsJyaLQIpwrB!fyx?5W>rwF9SMpOb!I~lI}wy&Y?y5!=dAPEGn zn32-3GczO&A7BJ!80PMqy=hm#R1LZ z=6!GtaZn9lx5gv6RgyOW>ev;a1fK|Q8L%)iaBrBduz*|C2OM+h$htF-bn|9HG&687 z1XYq*%%{W|7z7x3bD8BO7#M^OfdW4de1Q)G1Gm-m#s%EE^=+WSw3Hc?Q2Aeis<|>| zP^#m<2D(qDoEemC_(7{CiC z-vV-66SKJp0|S37s1|Ex2KV#0PlCMC!mJHy`sq(ESjer*C^CKCLT**5^Poau8aUjz zxj?noJaCM0b6QTnyO3LxF=#sbB5qa2Pt$c5aVsz;PWM~HEzT%5J#7)Uay@AE5br@| zP*uTwALNWf5WS9|y7w?xTtJBTDDw>|&_)%I;4$Vmk_-$CLj0gY{W$Xv(146k9;hL9 zf|&($(72ExNZCnd0nkW;5Em%Jo&s~&g`R^NX{VWGKnINrC9yFui1VId)&QLuE_51H zy`BYgc!aE{%P;0u^O_H8YuyGrNI-)30rO&MSjvBhoE{!Q)5CpGf%_Pox;cfKLH(|$ zU=Ej%|MdRF+>(qtrmtMgtycdH6s&KUuP`w%2t!&AZ^3qm2<-<|%kRJ(Q6W&nn)f}J zBgVk(4~qCt%pX9t#l{wV=9@ods0sb1=$*{ma1u@-GjgTv|P-jN=4L3NXrr zgGzHQutpI^IdFdAVF9&}Bp4aEK_>_D^0I&q`IHr5o-4AMo zK+X~8W&<_$HCXb%=ZH6hl!HP`1XR{Tn}oig%&O1w5p>~XD<~rwvKWC{U!aiVHDa*? zv8_O%XUyUSVh4Z<3=@_x5W5RhidwUP`WM_!O&Az>omiwm;=Q0++J)sY$c>pkDXmLZagB!h86@hlDTS03Q;50(4&^qoO(JZa_vw z&~ZSVjEZu$;6uXg>s7#~g#QCwE5WFE4wNt$6)ixAgfJ?)+kj6AuLreh7!`T-z^8;C zv<9CN4mxB|m{GA*34BU8Xn&+AqvBmL@FC&NlHfzapF$1^_mlx2623tKd`NhaGy{V) zqhhWw1A`2s;x*=a@G0SEb-<^DTN#2+311})J|$d3iGe|pQSlfX_>}N+8}KRNWuPlr z85Iw!A)gWsI;%^aQE`bH_>l1XLf}KfHDwtXv=|k+`M`&S^I3rp3BSq>TAQpmS(X8G zNcd!ahI-H`;VU)3r-Xx!tTAL%ER_MD65gc_J|+CTC={2u=tmPjy_;uHw7J=vkWZEz{|oX z$-ux80y;2pc|9mjm6#a$R~?1xSq;&{2+Fr>K;;ex1IvDS1_u7Mixn6c*!cK2h$_O& z-w09LZp6UAzX^0I2nV~VGy?R7#R4sfbs_qdzK^v1OHYKo0owFwDgdF z+XV$71_qWoa|Q+yCdGB8N6e==rZ;6JJ`ed9`Q`A`$kT!p>~ z0|Wml(D7YtCj4jllwb}y2XP3fi0{a z_K*bo%IT`BxDD#pf=)2IIa85=flY@04(RqoNbuc7GW8zBRM3G>{P#gh1UNu_Y5oVG z5?2Ib!$Xh_5)8a7OXL_BSayNN6CZ&_=hy`JpU#21^%;_>&q1cvbFi<}V_@Ka0Vlhj!79LwdVXf`$O?xL*iIJkU@4M$iEr5Z#=}y1AgbCxX&2H)9XzKpCMnP|)%)E&)ZQkjiwyHQXXHJs@Wo z@C!0(slc2e1T$#5;~H+Idawh;zz)!3;0|VCVBi;Ld<;3cn_r4C8m>|&%1I7~|^%DHX zj4i4#pPN9{cYtEhlu;6Va<>quRm*P%wvAKBWO~6`ZpnI3cZS~*EXD(gFDr0}^9n5l zp$7AvKeD+2 zP;+@e^+g~fr~>3;;N}1w>k`EH9CC6ue;DHpxbARd-J%f??Sd)E4E&McVL?72vFUTx zaZ70AgJ!^D!0AOp2-KD3j|IC;QwW?GJ&y5(AnaA{OODm>M)OHAUib^ z;!+0gC!mYhvKT=JtO*G4=Q4(Z)K4#2&#hPwVuD7*LHDe19|4sIg^Vidpa~!T62?s+ zb>RG23N;rTk!6ga@`FPNw4<889IT2*s0(x&d<7$@%_IOx7L{P@1sQl*l0c1)dQgc~ z#h4B<+|u@nOX ze>39|kWm8st&Bb(qrmQLgPAlvX9Kr-E~^3q1AjLoALvkR5&mArX>f&oFohr${ZK2x z`F#R7{`iDIJx%_J;L&aY2JQy}3=I5}7$ZO?3Gh#0ybL#KD$Jy58@Z+G-+}I1o58pU zqHZ>$fF>+z=0Md=0tM7uMt{(W+(O$q85sEIfmMNGAsRGhBLj-v`Hc5LMu_n*VyuE2 zu^4K^BGB3NOQ4RP3OclEDL6y$3DsW!m2k_zJOQB@pdxTNm?I<<3gWB)b3_=pLqH|R zDn=#HLEHlTYZ$k~Em@0f$vUVdpn)I$^^lNZ;9dl>awB6KNHZ7zX2$1m%?Vqey1^Q@ zf;Dh3aJzwAwT?SI-Wcs&F+=`l@TUZ5n_|G%4X~W!l0cr))abU$OfJN?II zZn=8U0tWt<;E3g9;Eo2h9bPf6fhc;*2)DAj;SAhYErgH`vClS`Ts+j}U0r z7{5A`66o-323{61kPWV&n}s!)oY+w~?rq{Xg*aB|38-yn2Ig=IT?HKgY7XXb z32g#3H7&pf@CZ!>DYIny1~OJi9aNuKG5yhFU=R_q16gRz1nLZfn$vQiaXyyopza|H zs6)+d3o0>fnCkQxBpC!``0bdA^jYx0k$Xfz@*`a5I7qFZX7u z2dNj}_hotjS3jL)2e)WFSakqcH4g*#R8T+%GOdTG4rY=yfVn*c+4NAbdJdsjP@NJ6 zRt2h4yyX}exUYaxS2)ufkP$rmkxapGBch;2oB@qWMuR0d>Oo73K-yA44T2aZeb5ot z0{n?gi{aXmpxVGyb~1R(oI^+m6hA581kDF&^QAI@nhN|3+@M>J_|utEK_+qWXE9xd zo0JVT2{f$EpTo34j)B2}gMk}#j1GSu(|V8wG5&leb3>S?3!oanRu@98-T~@;7BPXw zDEWkrOb_45tyg~^q*sE!k_mK$4y3101=ZUPN@LYbe?iBn3#|afat#xwAOi!Z5NJl8 zzn1A7=+tbXHK6je4y>O?=mx0DsApOSIyD;-{|(>}2bDmFK!YMIRiKOKLAQPJH!?Yc zPR$k&;csU82X}c3vhA(l6wV>k4T_pJuqqyivF%`EK^gxv$UsI=#_wP{0J2wuzl*8V z2o@6E$maDx%>#R&m+73)^yXdMg7xB{EZYyB$deKJ0V)M2fK5<<*fkMsmkI+f%TkbC z@gTb1u^?~Y~eo%S6lnK-&=br+~Kg*dwU0(iNP_Jnv z6Q~!6URa)iKPM)He;^7m;bF;MQw2Nh&zm_Thl zerZsD<}4Ga0m82cN{Q!~Kn*AUi=fat&jf1w@P7oUzrd6X@<%Bsv@SA%nsWRVpu~EK z>3KcKP$f`%?J^UnYUiH_^4S%p9U${|ffQY3(g2mD`$3uD8o12oe+~+|8%)(8`#}Rf z{5P4lfJQtLKzeU6v4F&Pfs)c4aJJ+J-9^iPmkHE5;hzaAY40)J1v%(4=;&_#`%HYG zbTUVRfr0-4xJKpI0x5dPv;rjl6lD7&aCOFi6=cg3CMHnhbOp$=r{IE`e+4MKpMi@> ze()tS&%s43|2~ky7fi|^j~9bFoG+OoL2Mt;pu`(caaGU255A-8Ex5#C;BEyKj_;X3 z15n)Rpg8yr&NkejWwHDW;6ZopbdcNGz-$2tehy|!Gtj&Ss4>L}9i#sSN@rZ)nGZH0 zU69APnUg>VX$yfCTk-QSf8zm_C3-5LiyU~N6AbS_IfsuKG~diER0gtxpBdD{;t~1} zN=bsupdPM(&?Qie3NwScrGi4UK!GCy<_HOaRuS=wf=v?^x(SL?aj+Ah{c8zkX#e^q zsEH!Q+-AzaAW*-CUxB#{l@oO^Q0U0I?3JontXb5JeFz{#6Hp>DV4egrHkIFuna7*~>MRSeZU&+Cpj2oHmSAMy z1X(KsxmX-YGrs`oFW|RjZUE`O56XIOU^au$d{82&_h4pbVqi!R0?kVB zdxAO1Lc2je_5$0JCIt4257;m1LZJ1v{JvmE<}z@;WoBTQ0JD^dftv#qvVP1Opd+0f zSouSlSAi~}><5Kx7+4R3&|7u}2L5nnPzbUJnVO|DFz`n(gGN#}K-w}<%%H~57NIGi zqA;2nRGaJ&@&l!(7-mpSu}27WEH-~EGpLw9AT$S5Eypo~8nH)&z;$#yGpO=D0Sa6O z{zPyBI3wgez2E@1n!X08_)Z1;>x+;Gs9;P3bG{0tgH{WqgE`-Xz$ID+^Q!4b4{$4L z^MQ(=Y_LImEON{E7#R3-m_b7h0xWVppg79~drgoDC9irM2}yV?f1VK|2;X(47tZW#FK7V3D%~g?c%7BF>FP&SHAwL2hZriPPsE zTVPRL_=0~Tkthw6O;)}Wfizyx7|w7vr?VbJ^w+RnENq!qO9 zK!$;VfpJcTH3NedDCaQ3B^b2NfX)N+U1^ zVDtbNYK+0U(hyCc_8DV{E@-5X(E}XxjG=m^+zbqiUd$jz^U~FXG2y??~Mg|50kQ=TsGB6mzRDhkp$OLi&=pJ^4@4*ZV#vqHCLKqmn+DuP8 z$t^lv;V8EPKUn4n0|Ns{#?lrdlX8?>Ar0hgA6tmC9T-eO=R-rC4QhFquL7MVD9HjE zfd^TW1P=IfwhRnrSqzNQETHIDU}9jdn9ac8)~?*iwjv|BrHu z*+zkm!u$euG-w?+;~dZ)BHeV5{x9Gz9%GOmGw7IyZ%iPWIFRYFpffQ*{OLi*xQ%`I ztr-}k85kIpL9Y43RAI-!V4!8qz~I8nz+eDc2GPvSz+ebdVPs;>z_1-0@}{71W^h<+ z06U9;VcYbJ$G8pnz+#b%kns5h5)+%QdYoG!iZ=utG)zU{m;~h}?MBf40WC&QaFl@@ zFlVtnXu1rvUsQ_`#AXcA0Sz)UYJ-P%K>IFC&7r|z90;|y*B%liTaI(9SW7}IVJ~Jd zRVe};B*e=CDqk#}L8l0S(k{bcutfVMG(12zyMV(ZfrWv=5T?M$WO~X8ZUrVm`{`{bxE1RQKxZ1x0C@+r%9nADha&@n z7TA^y7(5d+76DFy}xQ_x~NP^?&h>|zQ5 zg_co0$O+(*PJ}@n@vj%9=TWeyty zgCR@>*e@5@Kn}40l^25c(``?2D=^wmk2}RJD>BCkmO^-;DMa_j^!`)a(jlPM0wW(d zp)iK(fXh4x?>!p>gM}L?PEiww31c*)0Rw~62~dWa1Mc*KYz3V?&p3zCnSntkefqys z+)7^hAq))foj{=)#Z<&#!WhjoF@OQICW^rtY+^L?XT~4~2B%=qp-Efe2GxKIr-v>K z3_7}?yuX#{;qFf*)dgrEZJk2fa^W6oOD!`>6$ks*9Xto-I zigou828L~L83t3(u0&7-8-w~JpknEZGboZpr>mafmXZh#VPG%?-RBBcvI3fGY+WEq za?WteIK_uBFod~4teO~P!WhG7#bEr5fdTBl0yAm z`dt|q>_IsUv7w6lm;2xzJPXxFoDelIXD`eb#J?a z(k{qMCYH4Vj0_BKI2ai8z)oOcc{u&_d2ac7Q28PbEBM)2z=eJrCp1GI@#-9V1{$XI2{ zz!1sBz@T@P9dxwi7seUW3odY5*MquBIy?*vdP_hj&ir5m1(Oeme+YD_?N6{duHs%m*!O(OUvKw*NOH$PGI|^3I^9!5>B`9|i`{(i^?GptHOFGAj5mFnk5ce*~T7 z0O4EmGBD`92if*QgA*0e!P8(=!a_@O$d@-r|P!c>5D zo`mR31~sQRm>C#AiIuT{=@m#Ts5$ilq!rYZ5fxxyFodZ9H)R|IK$e0IZ)E_bKL#&w zN@AI~p`MMw^bIH*f*LrWO^TrM!p;klQ}ZuzOWA;$nn4itOl1rVrin}p44^Dv+{(nj z0IFO{p^}iIu#|zpcpAuGPM|HiM=x-aD*xHp2ztGt7!>Cdim%L#%82^a&wb?sRJQ2w7T zdX3wm9+Ynx!}Wwg*C<3Vf*JszRkGkv0O^K=0yrn=GeUDh3uB%iG!JPBL32W;5CelD zOa(Y6%muY!ApHt2CI$vj(ZslvaRo>xC?o6v>3nJx%E0g(q!p$FoD)C?uQM>%uVQ9k z0M(u6{a{UO$b_CDXr0v&W(J1yJ`4;DpruUU#x}SN1|?r9e@KwpUFTLe1_h~}KO{&& z=^hk(EA1H=Jm6xW#z8RygYgkY1_n^AT0ecpb#5a_Ed2o2i3|+ephmvC4olWrOpvts z7Am89118e}l`#x}I3wl;w?YW0@#-3YaK-~B1_n?^A`&5H3K~cS)%?bPnHU&A4Tdr# zNl;%ER81QjLG#l#sPRv4aLcfQ8tONvv)zPc#~i34$v}u3JZ^H!NP_Is4Me!1ff*cN)}*`fZ7V6==uwB()6^G+yc{8Z*eOtgW^mu z2;$HZ1_sj%SmDv>RVP&8j< zU|;~n#wMs3D4&6DmICFe3ve-TLlcs(ECfN9)j7bO18ID_Jq8^!TFnAlu?Z@-LB~Td z&It}?V9*N%onqYpmT>`%2bqE@;?q&}CC zfx&yVDgy)4Nv68#yKZw!`)hzsF0%p+#X&Np-+a)xIVTIK7WF#|8o1$N0o9;>P2h1+ zmczlIuJ=t21_r+?pvgR57Eo`}Zysp8S&Ze>bd@{Ys-n|$85lsAH6h?KI|BmV_*Pb&IY~!KT`$<5aw*>4A`j5zyQLWi`fIgH?MFrFa*w$ zVPF7Ze^4n4!W^#yG?*C}K$x?D&;KPW0|N+iJPA0;z`y{)oRM4sew+*pAj}!e9q>>0ERCjrysjt8WNb7&Fr(?|^m!kJ1t$0XSK6+U%rlXL$;@#2 z`BrYR>1VTfe3{Hmrpx5;craNoOy8KmBRst_hlhvJa(Y`1k0QSXLwtN%XI;ER`9WeYL1OPjVjo9hgC?#()gCAby+jiKhQww8HN2qa zgHJ+-vehBt)30CE5oC0lt{7w`&KNh{@S2XeWEDgTWGX`k5_|gehdX%0>vtgu9YTmXqJgTw}{tA+W>6iGZB!UpdFV@QT@z;0|oVoyL~&p~3Z zKw@t}VuQ9B!Yn(3Bz^;l{T_)e4?cz*>H`PRvEop+4-z{Qi9HjEy%dSP5sAGQiG2l$ zeH)4W2*w8a|0RsWz`*bUiTxdk{SS!^IvE7!OCEU!1{hlyi7kc1RzzZJAhGqq$B;vP zY=$IZi^O(8VtXU8gOJ#fNbCe8b~+L}4~bohVAnI$AUF)oNbD{o_CzH13?%k^B=#~S z_F5$N79{p=B=#XN8x;Nw3=Aj19B}$$xPZjIj>Nu)#D0pzeuKpRjKuzh#AXEbpr9em zfyCyoN8*Sfv1O6iDoAW?B(@O}+Y*WGfW&r3V*4SnL!oT2|6`yWkpGjB*jY&IHYD~; zB=$}u_Aw;(QzZ6BB=%n)`Bq28La54g&*d-!4q^B_#2CNbFZgY|sXJn0h8qD*);Nek8UY659%i9Ry<6 zLp7v=I8b&A5_o}69S{z6wKWpk1Bo3oz4RcDvg8aT zp`}RdozpiS2M?W+HNhlYIU5&(^i^N`q#NL6#zJ5fNvlsj z#MVS&dn2(UAZ$?Qkbxl;!U1RN;^|+H^0-T0LlSz7#AcozdW^@qJ`yx22(>N^iCu!k z2JMxDg$Q`i5~}_flA6m%?1xBfX3$&|RJ{NaTLr>~INJ@v0XsWty5eyjal=j|p=n6$ zB}nXJNbD=qGmrD=OUi<}dr<4Nkk}T}Hy-D)X6&2(5M=mPB$?|->?cU82-m ztm~seCrm>P&p=|=AhG8mu~#9nw;{0)A+gUPv2P)t_=eyxFoBN$gF1*0i7kc1RzqSN zA+ha{*j`BNa3ppz5<4HvhMv`0J-zTWPk+5UXhaxlzYY@H3W@EH#EwB?XCkrNk=S#P z*jtg~#Qu-OmYu%x43D*B8fZ2I>fT}`_QdIb&+weCF9)3! z4V4C;MGa+x&!UF1!DmrJ+2FINp=|J3)KE6~ENUnld=@p74L*w+%Kn067x*Y@XYlG2 z1_tn1)KEooph0ygTL+14g~awiVuvBIQ;^t2NbCkAb{`UZj%6?+E1gD?_=Lp%kHqG+ zLa0|lV(TNZZKv~|=Mm@4K@yrU-S#|>c>N|Mq5Vi~&~O|qQ{F@p7qCXy20m398Z2HQ zap+OUexOU~q3lSII8;qCh;0u}APkuxHY}_QKpbe2E&*wVvg<+OP|e^YsiB(tk;K8L zP(#(MMiSqN#6ALIL-n2ov7zQ)w614h5N3z08F~nkfGT>0#0DKh%?Q=-8R|ID8lyi* zYM4QD7Em=}NNhC_8|pY+5St6)d(ffMpvekwTC)L3Kox;@qBBAr5egEAvXhb686Y-P zeKCj)RZ|0ELoH|kog@u9RF08>0eq4)RLx9~8Yp|74d{GrsD?#I8o;MYLltcTX@IH$ zt$k#KvM++fK|{g}3=FrB*pHFe-#~1rdeA~um|juP5uy;i^$ei>`HT<_gE~Tj!3xBN zY6hPY4Q0oI#G$^=0I@-n;0z25IiS;~q3i~bIMf5JAU0I}1P~i4J{81<9OT5nFb~Xu z#LWf}8|t8)NbEyM?DHTt)X-}nHXlUqEs!Ii?57}csG846?0+CO)Dg_}po5s9iugcm zsDum>TMLP8g~SG*Dh;*F-Hw4lm=Cg~DjZ2o0unnF#D=N|ojeUvUk_SgRRofNT3iWY zLlre4v1fqT&`?>3#9oEO-VS0z^&UWCUjwnBdha8#U)X^LQJ@mPK@w2SLZFkRp`ijk zh8jGn%)lUP&%huIWosa*F+*ZIg4j^cxPjPE_5MigR1h0%Zw3QH9-PC#P>#fIKw|fS z*ieI3f!I*TZ2++$?Pi88Ajd)3`$6JRHD|!=>HDtmNY#Vppk9IaPzQbnv7vgtL-m6e zm9RN5Fu;ldek8UChz(UQ;Q%^dhJgX3UJ)b?HB$q`2CX0jO)G-fP;n~E#J&h(Lk+r$r2ZaA9IE~)hz<4SClDJd{vE`I>g91{U|@u@ zMM3O(C`TQ{0mnZBg8>rT5{c~uVnclv2Vz5goC0El=7AX)7&06g7=)qhVvsmgO)ZEG zbx;$C4Hd8NN8-!`v7w6Qf!I)k7C{XKt!vv15{IhU17btf9Du3;nR^~24pnmliG3Hu zhN^!EQC|;Ub^8h=0oCvk#D*#oc4A;)gtApYY>?@or8gip$Tgr9woVKT!cevqNF1uh z1Bo4m#7;qC7datKz|?{yppIw)u_dR!yUru-2`Y~m7#P-o?18ekgQTJM90IYS+Kz+R zQ1NRZHdOrwFnhY+4IXjOVLYIcS+s(6vTl_RDsw~i53vs0^~FXhE5P0>bS*7?CnVG14!&^ zAT~7h-bZ4;Kw^Idv1P%{3kHUN5DwTjb{7T)(0MB$jx2}`HAoGKt&hY8t^Z<#I@As% z4s~ca61xzIU4_J+-~zh71Zu%dkOY*y2#LJ{#D*HW5s7^m#D=OrgT%gy#QqCnLqn9= zm4N{?R{`=EyDI|&=#Xr%|Amkw#Gn$OGE)mA4lO~p_(k0|P^nI|G9-l${HbhH9$-v7yG* zg4j^;4iFnE-V0(w^-hGE1FHPzgT$d~R)E-0HEW=1K*ewU4v+*?(Lp5kF%TQ7;S`dF z%OG*6`a2*t)IpCyZ0OY_&q3;;>`x$ZsG7eZHdHT@2RO_?V>=8CydVx#LI}i$YLEr7 zq2fv)HdI^}#D|L+5Fpb{rRY>)&41H(BG8!CPi z#DKgY-ab zsJI1)Z3)R2jvzKPzFj>T7=$$$7(lB-LqXzDy>UqFWDpyozMdf+Nkaih0;-`J#D*wh zsE4WnEgbC!i9^-QKw{4Yv7zc0BB@^m5{Iha3SvXm>;$W+XJ7y=DLo02fGWC##J&z< zLp9t6Yk;VK0uqO+e+^>vecBt8JE0O+kR)D#*ib`1BeDM=v6*}j zK63)Gq3PBW#0D*-V_;zL^&}4K-&ghz&L80*DQ@_&SIUy=LjQ4+BHJFqHEQBmq_Q7sQ69JtkiU21ckF zZX~uMhz)g+782VSiR}hrL-j@>vGWk@dWKFA2Ws&I5F6SMnc~a9APi;C2Z=+~tOBv2 zj@yaE-Unhs)tm&ep=!>7*iiACAU0I|IhYL!e+CAIuV4Vnfv!fY{a$b1Xq@s0VEQAf5rO#`Oh>L-mH$BXOcZY^a8KBn=rLaj1r35F4td z9I6JiPPZK-4plP&i9Hp>hN_>5q<#@d+#Y%(*-8)xs%R}#5on?BHjp^fX9q!Ss0GJB zY^eGRNbH+P?DrrxG=2O)Vl(lqmC!#NBLFOb;pKy0Yy??`Ok0E7?3kl6A_Y$FgGs@DyP z9fibB2C?g*ipoJ8D7yiPJq^SLyOe=pJ`#Hc5_=$Y^a&_ zOo0gBa3irrKy0X?QXn?eP(38J4-z{RiJbysL(@$*hz;tXFfcIW2Qn}SL)ldzaoC7? zD~JP4TwNeGRPz)N8?-Bcfq`Krhz%8Aj>O&sVng+A2eF|R96(}U1F@k#zK_Iy5eO>( zp%NcK5>U(jf!I)kgn}3t7@=%wB(@=l4b^Lf#CAqv`+(R`Gb2H4s5!YXHmLmRhH)4e z80I6fHzTnxBC(%?*wB#p1Y(;)3Y>323=G0hHY3us3lE454Ix1g8>&Vs7}Pq0a+HxI zOhIg@&+L%c?nvwq5F6@<93*xN61yLXJsZS^_B|JX*bu#T3~LY^h8;-kQ%LM}S&#zT^@2{D>s<1Bv|yiOn1W?hSxLiXDl~hr|||&iIN)yj~7TNEL~#iNrQQVw)hb zZIIXwNNf)zwht0J1c@C1VS|zc149CY19oo;5<3%#or}aSLSmO8v1^gojY#ZHBz7+n zdrAms$Pp4b3^R}<79g>gAhFjVu{VI()A!9(pSFF&YaX9qMw97(?RfneeWv@`^ZGMh zm_FB@*Pls(WBNOLUO&by(`_Ai{TcsE?{(nyXA3*KPevA>*=X&z`GkQ#a3!+-4+j{Z( zGv1iq3!)B8zYC&zrt5n1`ZLMMPp|U^>p1Jp>(5v)UDk)!pK;3cTpwP4CLV?9`+Ru) z7+a?E`ttfSai~v^^X2tp?3upS7p&+nh^mj!q$To83(`&&O=dqzf&>AC^D+KfA< zM+WdJvl)Q)lX_2Y3gA^@eNzJ3PWI7+QF!{E0A2ycj_GFuc-5HC*yv)tH1QOy3vCtHxL| z{b?YtI;;I+28Kn`1%r5%nIAr2fLtf(6T~aPD)W$m!2)7z35Xx^kb&Uj~EylrZ0TPFFgGXNL=UG^nW1nDW4b^G^Q7d%PTYPneH3RtIqm{iIKr= zI@li{(z)4%ij(v8^7R!I6bwx)jSP$oO^v1>oGqR_y}-PXbvthe?=em`sPM)zX^HJ0 zV|mxvFmBtvU>5JR$J1KWM3^m&&8Iio`UpHi>UHdCspd&bV!R%0K>w z3??(9=>}}V65Ic!350MknHg;l$ro7P&JJ;!`Sg8T*u}Riei!(@hso4zI%B%PvFRV) z2nS4G@Jd!-yTew&BuGrDyS+^h9Cn$dz#kxNeg?_8R%-jBNo6uW!#%=WWg*m921RD8RnoA4bm#%DUIzsE zr`PF;vv2SHDm-mB%pyiTMTzZ>8$~Y3Fm7uXIVZAR;^02w(WjP#Z*IJGK?9@ zlG`W!6iZ@f+_v?r_#$}7GG-`COy3*K>%A>p{4_jf;iA*R#aXvoCW<2>y|95xe7j7x zcnuTdw(T=>#dk>}*#R~xVEe&#Bn@!0wttu?ewq^!qQ(Z(=Y@%jm@UN@{&l`wJKCMB$lkuk)7p zm<9K0+qB1D7HboxW>YH=oWv*`vF6%x$mW+qb$LnN7uji(!m zN(paQeJ1gj*~QqHA*m!WzBr{Iz9==FAwJ$M)XzD@)88*XUd7zZ!~jFY3|++3X!=K8 zak1?+uO#Z#kOEV3yOf~hV^9?S6P7$EizFky{f?nzxCoOy4`?@%#r9k`$-EpC`5&7k z#YGsmZ5KE$nJ3KXHog9qq#~o+^o6%1vl%x|=e;ed!>Bvm>b9h|xTUo@3j+fP3*}gE z5oBNhVK)2ejk9EJw(qztdB=j$XnLYnwK$8pxtS%%=VIHBiAcF}Gn-j5Oy4LfB|KeG zK}wU!$P(;}$+KN7w$D!jF2!Z`65AQCOD*z(i7>hei*G-mD9y@g6v7HRBZA`+=%}eY2pe?h z4qG{deU*`cflY!9q=uU%j)8%JZQJ(mTGCs*VMZzL_LAIws!Tdfgwb^RM6GIx>Eb)J z9j8yQDde2q@J6^`T68Vz^nyrUspVf&;WX+U0Nf>4e*ui%eNqbA7h`8*Pj+O@%#&@J21~M5LPOm>JFS~t#o=lSv zh*uLLuf5&hQD#aHOcx|5&dFp5Gnp7}&wePw&kSPJJdu$XgsB1Bwd1Qy7kE$E@#+7f zYS|$^sQX}Rv^_>s_96?T#dbYC*;sp+93?f{1h!AzE^EoclLH#iXa3B>z`$O-{nl>T6O0lS3qZG%{$gNY;Hv~3 zyurY^nw5cpuWI_Py|QYI)!QHLl`Ugqblo0tMAnI!v19t|EuZ=TAYWoI%pnZEn2 zYyxOco$Nc=Rz{2IXRphOPv7-UR*Ko&z;yccce2WimfL^7ljX5P@soI{bGciBcsuF;YhieCX5!~-G9uc#+K6=H`qCR3y7jBc~{5X^bf2OpPs&b_kl97#K_s{HdtA-FvRwoGO$sV3CmT zM-|yHN&c)AlbONx`m^$@*qF==rcc}_ue&|siu`gXB(0L$<-`>Z>M@xbZGY&haEKMe zSn93dr3+K@F{nslJ8z`|lK@QQ;B0YmRzpi;L!;>r<+#+D7@Viy3s4lBUeKv9W4gcs zG5+n+T?&^OnPfjq|Iw{*W4eK6oy7ElssxE?y$UK~aU2W`;4SP7ER53J3=BNi*clk2 zr(5+ZSn~3)GcYhQvAVD`FtEIz-q5R{lgPu$z`)AF#KL|RR8p{j$_REQMvjvpQ>Jk- zFffA_5-_lU$|GjQDA2uEOE?%9m~~S@%skL-n2L)*%p0JqB9+#Gn3k*z3@pk!LA!n# znVwAN?NdG9Tasn*PxqrG{pMqaK8>s)tza4a52meaYnF0LoSQr?X`4vG|H}aq3 zU|?WnU~vFBPc0fGbPH5UMf8Ad*v`Sg!0taCB)W==fq{d25r~-&x<^)WDo7cN14v*y zHv=0|OWTE0BHspd&tb_&pgJ7p zxEL7t_}_qzbL1E1WMB{gpR_5+FUrcmAjBUEx*eLooQ;7&gg-)pje$Xw{~s#@gBbrj z(A7`;U91cY68y)fKb)W-TYr?BfkBSnhJk@Wp1+QhfkA=4gN1=XkzXBj=L$a`4+DcT z|8fQf1{Hn@76t}Y{t_+*1~vW{pe^M5dOQpa8vNUs7#KA916UatwD`BNFfeHIf9GUi z(Bba_U9`fl&kVYfS(F7-y76vfs{oxc$_7ey{N_vy42(YfM?p!A-vX3Y`0s<#2LBc= z1_oCC-z=c3&BU&N&J#Hf3U<&W4dWa>Rt5%fP=YwZ&cGlp$iTpGo}GaKbV($`t?4Hx zD(G^7`3?*W47a9DQqZk`3Yv8myT`%6z<3X23`h&(95a|PA3?@|V&@M?om4i+QDva3 z-9c)XfDd;_VPjyBPEKNAEZYG-Wrcx3MxTR$p@a>#C0-n~x{iZ`fk7NJLk+ecbO6vT zb_Ry6(*qwWh)q8%8G{K21H&G$m7o)s#6cr+_8{kh#{9uS3`!B+91IK$icX*y z2>uE(9~4fEbCf`b6)>8B!vZwv$~Y&Coq<6aG-u9e!g!dGfq^kd*@lIIfzgEVJjg}C zDr-T(ZwBUBGcYiyg52UdJ#LDEWK0M*U|;}Yo)qm>+zbpL%*V~BWdJ(k3v@#4 zdo9p)lpxHLsFlOPzyQKr%F`34D#%L;#BplPU}suFOjCHt$hc&>Dn_C@)(y)pEX0l96~9xzhVU)gxE4&(6T9Z z`mSn)U(+YNQusXm0k5y;^n^%`!0iuaEA%iKpmP-4Hw z$jHpW$vl0+dr7hBpXMrLF|%`WO`Di1#<*;H%{&Dwrmu|C6}yW>8MkadH&5X_%k*P* z(w5tAELKoupWd0*pg!Hv(JrV`T^lsj_DpA8UoV; z?BqG7|5>ddF?~UP1JCrFBW@DY1?=T{rr)oXm6)!-PlacC#u|kQjN;P`WetU=^B;2% zm~JpzP-MHoS_La6CUc|hIqMZVm>HK$|GG)RUJ{gYg&4#cgu$tb0SrLP3XP^4F7=n6 z))+1@-N(h3LlTq%g%~6mDxm5>=}(A3nxSj@+RX~?pbqu7%?ih-pV^`?dwa%Kg+RvX zFVEC+PrtBDL2~-dqs2VaW%*Uur(f8nC^-G)CTSiS&;oyuILN6WHn;Kgq+JU7j3(13?NYF2 zG~a%1mx2(dVHGF~K^KQLfY`hcV_Vo57=)qhekAdQ(*=(xh%@e;u6aa3x&9_d2CDl$ zhz(r~`WU1e$_7;tj8HWnL25t&1)7Zlse!T?Ks6{-4IdI)28j*2HI)%`Yb65%gAPa> zbUzlzv2G9!h{+HRVnYqeM`BL~v7te^7{rFESr1}^f`@^DVGD>26+ZxCYlDqs096Ap z51a&vL)BbhpRVVpC1!gYN$frn`xz4Z6%zXs68qcquRAi8b2&kU5Y$*+B(?|=TLOtK zkHiKY%nEa!7LvFg65AAsZ8<%WD@&ZwW%|O2BI1&uJHueQ!;w@)Z=ZQgL7J(4BB-zg zAF#*3Z~?>y6}$`#3~xbfE=T|sfX-@xrWH^(fDsz=hd|=c7@ordsYpONmOtUj2~h250cFQBFfcel+1U&X z3_egc==h`{C>vB$MnKu115e|i>`4p^3@K1HsPfE!vO$+tRD;-{5CsjBH$pieU$#Tp zprqUjWrJ$0$xt?EWfbUcWg%V$(0%R<^P%FP(jIi>I!GK;k!}NtL!)UIlnpZfEQk$_ zvdgRt47x)6kf6H>l>i0reJC4LfquF7P^arWs&JR=M)4OHKyC1Q&49-GTqUeOMJRQ zqO1U8&Gg=L3hL7Zj?}YE7nvy{GQHuV6liGoE=Y949$%K}G48@VlLP*8OqV&YATT|` zU07hcfo=oObdU22JYX(ZGUvR40ON(}wdWPo8MjQo$So;8eZuYv0j34I)6bn(P-FcA zYEVxaadh7)Se%3j93=A8l7hX_MX5GTX zz+eZ_QNXAv!00o5FGvUIa8>^46W6GVO#gd9fuHG)!F0Zh3Tlij(?9Nz5ue_Ws4T$r z!eDwFNK9vXW3;XK^f?z51Q;Er8&-RXPruQr2x2RCDvD2k0}_{*{`aDSI_m>w28N{R zisJIZ(`_y(2(b1TF)&z654@zH%<9C$zz{UuQHD!+dJjly3LgVQCu9WrfSfeT^b8Fr zUPhbg$1W+TvC8r@FnCOFl;skc{xYYSpJ|2dbg|0{YK*DVZ7(aRGrCMqy{w?lI+ve; z;obC!mlc#*uh=m#m`vXZVs?vy?0I-uL7DlkB6J8`=8A#nB3=>yo-J%8> zAXmJqpv-Eb#lSFaI#_kgRR#DM3%EOJY++(%0PapI+O#t;FfcPPfDS)oV9;PlU;yPr zP}u^(EYk(`<>aRy-^#8qy}+DNVsgV}4iH0u@y>KXcVXqp4VMKtTOeu~5JHM@A*d9H z0v$BT0IkzirZZYFnq%tZ!Ko9}pYUO1U?>3T^ar_tg%u>$1LCVspL0zic)I;{1!?DyXJ#aWODVH!PR+ zoBsEm0tX|*^gKy6s#sJvGB9*-+_?cUU?T&A&y4AfH>E_TpQ&Ty6a!0&MKHl-!2)0fmTs&J42Kqc z;NgZ_&m-B$z%Y{o&X@fFbIqMga1&xCfgKJpAM7zTAuqTrSOBab{umDfgTkZ<4>|=W zGB9*?c5w9kfN&QwFm$bg=#W-&V_@K6lCe-}6fc2GM%w*K|iV8yS5bCO1Zgl}wgGo=WKM0f*ol4v6}V3=B;R zj&>rsrICT5NrOR60^Kd3$TqIITtUeq0Lis$xV%cp~q+i zQ`oQRigOud#A`me$v_h&Gmke!kD8PMIK?W}JOTxR2Gl8#q|3!44Raev9Vj5oY94_j z2t5$se6W+%Bs3w$!$ThATfUl0$3P2z(H+GLbrdg;HAI)1lp@$sLN$+$fif3Tz)Zhz zQ(?{Ygj)(?ZYimmd6}TjHA8-JW;`ShLqrgKNZAmdTUr4!2O*ve&etIE=>i>G3e)GT z(2|%QAm%DDeZwsUgXsrE1i7Z)$M%9V$vBrh&%YVkYxS zOb_^+Br#oQpRUC8g4+rzF_ZZbLvRyV7#Mg!o>gRloGS{lAB34$*sDQj4l=Rlg2s(l zSTplV7?>E@j6j1Wn?WZS3V{wvWMbqH0xM$$9e2(0X8MQQ3gQVdAbAdUH;@bqE9m@V zCKmR!4A7yx-JoG7@K7ETBgaLMd7#7apd)#9ObiUnI^dDKSP&C3k_R63QUo=hm>8M( zn5U=TQ81`~3p(+fha1!q=r z2F5&)A0V44b}=z9sDKo)v4G5D2Mv&d_#B|28fgY$5hex(fmTq1elu7T0|Nu7B4nHc zs$xYzr%Ezz1~EbXBvFuIVxaH>H5VDgKFPhO*f-#2CK!PzAM8q+1q%eqq zwlje2kPKr0jqrgCgqaUYg%XT0tl*o#u^3;^z{Ua!aCWB?^%#yL{#(1fGK4of(Ykja<~8dn9m zEs+g$X9@#jA}D4zGB7Ymf<+S0)&#fJ0S@fdMl#SFkZKNYs-QoJ9$SHu5br-1E z1BC`?e4cTR8YcsT2&jT#>;g^EfJTs&^g&fi7pMSd3|8_1YXX(vj3FZ5m_aKKyGj@t z7~X!aL znDHQKRO3M&gr}Qa1_lODu6Kp#2Gkelr^QPAqI*6cvfaakljE8nG{4j#3ERbF))aOf&>&|i4b|>N^Dq&i50`LKnG~&0mz(% z*v$bo2F&tN=Ziflp6hV36bh z1iBxrIN zl0WO=Edy|^reX&w#bg*k84ncTpgUj~=jie=Fo0W{p!TmAXh%Mn0cz2M7z`?{peC^* zTo-6MnsH799|MCbxOJ?^2x6}VSclZZD%N@i2CbQ(dRG^ebRemPy^9gFbb)~ZT)qo4XcdB*i~7I# zAX-4n1VBpxKuu~NZBVxagjo}G(wG<+K$t6*MF({G76@}mG3xAPWMBYco{KEnlB^62 zAj~POeU_Pl;Vfv40jIR~6$S&11ZXFpL`B+kmf%xA@I&Fv}7B+kGfYQn(G=P7I=IbH9XjLGzgj|{{mr9ol{ zB{H2&j0}Q|lbs}{Pe`qkozA>bTxPP)V<{sp24)VBGEg^Kk()78oKcv8K?%ux2?hpb zs3KO7B9-X}XGuv{V!Wo<^mRho9MiLT#JLTToFT!$psmMX zFKHv0#|Lpf1A`8V0BB}my52Jd>*-a$dAXyD}5LY=7VTZ$;ikM1ftGDg+VmLuppRWpmxee&@>Dq zLlj6F)N*5Fh?>4(p0KzWcx4d-$VVU+sJ3Th2+E%xxHUl3091E@JOgqChz6-(X5jog zAH)DD1xbKta2tam2yCK0Xj2Ib*hCPk3+%@r5Cxi2f=GZ^dms{frtkP%E>q718dd;n zg1H*qa*$zQ%Rvm#Eo~snK{UuPW(Lmx^Fa(y9Rrd8(FedI@0|bUgBYOd03-pT|H33d z3{Z8=#L8eW|3Aa@3!Leq({*h0xVb^oXb`vBP2YQ0NJbG9+>8uCAPN*;5IGPFRFX3? z1kIk#I3-GS`h`c_ED@k$8)O%V1{nl)Hi!WVM34lC28AKm*&qg}^aM$OXpo`I44nVw zgBT#wK@uQ(+4PN<&5ft~J#^)se&nH~(DcY74I+`CZ~}!HsM!FbL8S+X26fFrG^qcL zOoRGHAU>#j1)@QT1w@155JZDw0z@yHzTt&}GB3!fpu`MH$vx8>P1MB$X=4*RXx5mC z;qi3AcL}l6^$#nlZ7)cbJH|M@`L#mWbfpSS)#*21D`+vjVVKVHM!}hVGb1B2BPa9p zd@naqeHI2r1|}9JW=2kF21aIPPF6Ty2+o4YurM$(Gfppfs~|DmMm3Lfy8jymllrMl zV6#9{oNNq?oS?QLBLgdFAc}$67%B&~fE{k25(6VM6DP<(CQeQUMov)S4cBE$g0AUG zOgzG3AoJOn893P)7}=PaIOV~v;hes3qKdE+!YW2iKClnj85lW1*HgkRybe~+3~?O} zbLv6nuz;P+$jJ{;%3Q}O2xc+DHL-%ikC_?d5>z|7z+uh?R?Y-c&H-{O3n$1}Mo<`l z{J@ONQi7;u289kIGcz+M^Yp!0a^liVoU&kVfI<%{$H@%#f#CFw`EtV36P(q!>Y2c5 zAmSi4OeKhoCCm?lorfL-%tSkn3G9SQP7Ve}W-d-9h6qsnV#Mq<3Ti}x33#S>T!BPS%C38F<8 zCmYzM{*<^hADoy(kzFx;W09$-E;A#i6M9}-$OOv0%;>@^nWk60Q}{eRw^Ej005qMD zTUwG@5nq~@lb@VDz3#n&v4EqGV~}rraEN1wYrKDetKaku?-ge929~Clrg|jirR1c> zmrS?%uOQ1-5dxZ3oNibpt0-7d2Ijb@mVjwbm+6%s6f(FIK@*(u;3>@M4?ZY_aU-lO znQr<~q1p;008xdQ(m7NxOrq5Rq=a}xlkeOrp2f9x!BI0Pd=r9A@!188^~ z#7vnUFrQg``U9a@j>!UFS*F+3D{xHr%U9!>zM)H-XY!h_Jk#Ihsqsut5Q&wT{@+ZL zXZjwU3W@1Fo9cL`zp=39nSQ2ITVmQGS)Sx(6(dw)@|nWi7h!ze%f!vv&-A^fz7o@qEY=p8ey%HC03pT-T2iJoea)Okc}~#!Bv9c!Z}P{l($hE0 z*9Kitv+$~$IHT6|^%p|Lr@xu0%`?4XUmef%J&Uw?7zL+K=*dx@K4GCCNMWLHkT|30 z^ujH5aG?telEryJoe9vvN1$;Ah3OC1D2Ou}P5-x5Ph8TLfq?-e18Przf)KRm2gK%` z-pHFRJY6ABLtuKHZX%B)sN(^W1T_X=#<_y--J1@wR1!2m3o>UqxG~4T08$ES1@KN6 z)QS|I&VPnkV7fuSHqZ0|OKXYg6V^+sO#dKjC@`IGjiTUmgbt5SBRL- z`a?l@dee6WFD^t9o!)4tEIj@HcLg>sL=r^^PCxTqL6!}gPT@+Yzx=N7cDnmd1p$z8 z;?tl1P|!s-)9|N)7_xC7KFB2Q>GD4n_@^fcHV93({i(n;UGJyDJ|=Sm@CFKI6LSN| zt^?5Cii7J*g;`9@EKH{#cq%J89kdUS*~H8Yyc>bV#LN^dE;7Br)>p*T#LUE;K`*Je zSPzmNl9P&&x!_!jEC9|B(;3qRjw3eFyt^!>Fr90ol#nE7)&dk`AHc0qHwMU^2@DK6 z(C{2I4_5GlLETcv}kt0|RLGg%NxRA4CpBGBfDaGk|sifH;s&fD?!b$IJ`{ z44}3+NB}h5#|U1#2I4_5GlLPsDF_p40d(s+RE(Lygy9C14bcxu+)x3q2L#O+K$ot9 zgdh&Eoqm3KqyF@NHhm(8azC8VpI(1z$ypbAp=6 zLJV3AtOIwJ+ zfZ-*S4^jg%?;Dg4YJm$e7(v^e3?86SNd_SX69!>WS;oM?02*@=VlacukTNhZfW}0G z7%Uh-lh`1`KqZP0gB61>R6WRWAqMN|>i-oC#1Wg6%q$HNRmt?w{|ajLkgNpBJ4gym z%%KXwnFz6y$HdGOY40K^gCfhB86fj4kT&g_m|2208$$00Gch-S?hfJrT^VL#ZeR(j z0u@CdRkV9*UTRThvU7fJZem`_^h^I0^pT65we#d8;}NA8QsoD#Ai-RSufU5FK-DnV z6Y-!X14C|VZgFY}SP?`N(v$!TKy-mi!KvJeI+I0xW2PIrDT_?k{3FaW-O^Voxg&@J)P8NXPFfURc%-QPQ1 zkY7Y(dgp!%p6Qk$zC6=EeoU2^-nr0^XFBKmREg<7I07g`;ydWDvTgyNNl*aVB{T9m8Gt2BjUQpnf&iN@-V){$IOrGgq-=<1TkNl~} zGkxucR0$2xvIo#oQ;;rb&;)?k(4Ywcu~98z)Su4xMgrzW6>f>?Cl`af1hOHMQyGhw z=KWF>pMLUZvG()@z6z}9ZVA=p6`r=jh;@1=cL)!o_w;*G_Ttk$+rxRLa|TQB$Uq$h zn)Zan7pT9B<3Q3M5t9i+SfSql<}J4FP^DRvCtIK*&@9b}OchEwbym%@Ub z5)6s}XxNBAt8S1bAU4R)pw&_!HpoGsL;_-i!UmMGKx~jdK#2sz2I&K>767q9dYwTY zu!j_KUQjkD%s?0Sg4BS*DF$S}h!_I{Xe9$^tP3Oo3aA3829Tj3IgmKWGLXR_^&kg; zd<+r?r8W>777?IrQXp~Az(0r$iwMwQ7)Ttnh6Tjt292nKX4XJw{(uYxWpB{2%OFJ{ z1t2!eP|(;cNE{RuAU4cU(ABCSanKT85Stq$$-n?^#(~5^*#^|4;|7&wu#g4?6SVlR z2c4@8@)bC!9Uuh(IH(;UaS!q-NDavM;GlMZ1S!Z2kT^&$IH;lG;GlMZqzQ0PJ3!I_ zs2mfKU|;~Pi~x<2g7nIOX7<3r>i|gT04;T9U;u?McPJ?Q85kJAQ6Ry<02)mM1v|)4kOB}JB?=rMDIXNd zuqXg^xj+sAHOWBDB#>TEbb#30pfZnv0ep!xNDU~8r$IdiikfL4`(bedDs@Cag)K+{ z2s=Uw1yF(niGy+h$VVVHC>Maz0*DO?70|i_5F3Kzcz)hiGw^C#SqWH z05dclPKRAD+}nuIVYlQVz= z(HT;Bf&&q%92|&Had03yLkdrDAUZ<|PjDd0F))DUgFwj)WIQMU%Ro+sst3(>gTz4@ z6qMvdpz4=`Ga1yf6-XM^L)oCf1?Nzx2GA-6kU<~|Kx=M6Y*4JefvN`uI_Ss>m<1q5 zfz-fbRSr_Pf+7+mt^ulKK^#~NfMOCP0g3?-8x{eem;{M~axsXF6033y44`5P6q6t| zpvVBRVP=A3)tLc2PzYkf%mnEXsh4A50F}~NARovvFn}iGKzxuvpxg~&!wdpfLCy@| zfd&v8W)Qg4c4lAzMIDF@YnOsnnSeq9G>(b5*$m^q;Jr}ZESkl`Q>EG|LY6hMZ8s)BM*oVh?Y zVu9E&LqSU*L3%+!3u40z1&!W-#6gJ{#D*0~pw@;6$W;ss3?MlWn*~(Efs21vNcjX} zbAxJC1_lPus2xZVsKf`cVdCHxpev-X0t7f^Q%%KiyvPxrHxQkDcc2$WVC85o42Y|u&zVY%sD zAZbtxgU+)6NkiG1VD|K5wo=N|ZR0&urt{iKNl1bk=L`%CAs|U8I}*&EZf7T@JpH09 ztNiqs^2m^SP+gRw#B0>%dATo@bFI)t&KK?4b(_+x++U@&n|F%DycT8c1s zBa(X13Iaw822h%2V3;_4qob6#A?Sz|m|D=#DU1y|WCg}Pf@H?U>4HvD;-Q?NwMS5A z@FTHBk=W8mY|zmwFyl0k#Ep^IcGG>Gq~hyAhp)htu0xXEjl{l$#J+*V1|7o!(+e7U zWQ5+G_7)TmP&NZ-?iy6ygEqB**idh1LD--=lYzkm!~vyF&}0!40|V&H6i_mC28ly8 zfQB9!p#}vZiN}E0pzZ_%14H8Ug-@Nu4I4m0pz;dTc1L1QLSoMbv7y=)PS-soCC+;m zBm{NE{pkl2BgAt*f`p(Z{Q|L}I%Ggg$e<2W0LHjpZ)sk4ySi$QFtN$WstXt}Tn74@-hnlk#!UnZT85q`q zI8aA!0kNS59R;zWN3~xAv7zFRL2RhS|3Pev>Gycq#Oj4Xl{ct{107od4J0`b8`OmZ zt&0Y+p=$I%Y|z>yQ11=Ih9+$n5F4r{3dDxmp9Eq<#j}yvjUYC}Q`60(6;$h2f&`!n zcY)YYhaLd2q2ecz*x++GAO|Y>ps3+J#$5BAd5dpEG<{N<67SJSS z1>%6(RSXOacI*rc!cev+NE{k6!5}u&*AXB#R6G@lU4+E00kNU#LC5F7(tkIS_yl&) zLA_9eW`QI?%@+p9VL6OYM{EL#Lk$9-#RU}yAL1c3-K?)cs~&Wi5-i>P1F46q;Rl_0 z0rjychz%779ee~cA9NxSOs_3S4Kx(pkl6kpHq>n~AU4#TR0tc?uwr1ygK)q(tOdk| z8q|x#o`%Gp4`M?NT?%4D4Lu8DLkq>r(+wwyh}VAt2|Mjw;PBJZN_+UGB5~3*`XkDsG4{X+XR|Q@*o_r|B69usG?dB8+89B z0|P?`hz&KU7l}O$iM_PZ(Q<3lTV~AU4#EMj$rSI5#AAFo+E`Iv&J^`Y#j2hBoMOxe$%J3XnJ~3pIf_ z&{WzEVna294wiyd?u(Jc*MiufUM2$r!wwJ|YQbJ4_Aw;(9S|EDXit&Y@3=t6ze6Ry zBT2A;N^hv4py_y6l>j<%j}a=af~3X@#D<#VjKuaqVuym*P)8?$*dTL2V@%mF4g&*2 zBZv((2y_%1EIKA5iO&JCp$09Qu6R~X+2|=q2&(NJ68k$68*~g3BUBq3&-8ibLSpsC zJPZsl|JWe0gFtMkdC^Gh6eM;ohz&Kb7{mtohk=2i0mO!;gdPwZ8ky5TY-rnk77zGF zGtl@n1H)2~1XR&_5Zh#WoS&3j{aFwjbOId%1H(-a8>;yp68k-f4Ylkmhz(Wq4~Z?p zi%80{NNhDEwmygrwaW&?R)FSPR|p53Z=*qMXsDzhv2&5wWgs@xpc)Vx>Y({Z>=j7t zeIPc}%;QMx3%p24^Cn0FYUq6s8*1nq5F6_IA0Rd~6q)(pSEezrgEk$2=CVLb50J#A zk=QCoY&{SgWDclYr9 zq3jNjI8^;C5F4s~B@+7}9|MCItkS!QB=Ho)hWhvwhz-^J4a5d@=|E?a@-r~N^ooPn zdehqy`OR#NKy0XbGbFYh659!h?S;hloBlA7Uzs-%Nho#t+LlOhzXBwoawK*&61xG3 z-GapKMq>Aa+0*OR3dv2sAflKseNHqt&-6Lgxe|;)(>F%(iceplti(EfVxodPW9@Xq zW(DQx3Wl~kjPs@+v~LjS1#LrRgf>;SPEXuaAnpemy@CmW_G7~8G|=D^jC~8#tAtja zpyeVkanP5xMCZlEOT;;JzkQlQ^j32W5l%nozb9k~nxvK2%(9`a_XI z@##I1!aR(&(|z4t#8p9uW5VnL?dycGL8ldT+Us`1CKQjRfjp+V>#IA3$QCL}H&sVuOxUhUvYDBo5lM2P;C~ zfW)E2;AbTEcLY0(ff3YUgen59_=aibK@t~0VuQ|Rg{hH45?4iHYfjHS*eG5PKAaP3 zH0U4*m^LRQrJ#L;F!2Z^@dPAx3KBaPiCu`qu0&$jLfD`ZgMpz9!U30 zX-MMpk=Too*sGD)>yg+ykl1^W*hfIyfM7m5fh2K#x@}2;cy9Mu zKYe0JfjDE#bj8&&;*1&7C&p!qOO_%js6=8nPCpozEuPzlBs2+$4ITx6I&B`3IB5SF zBedw=2oi^~cObF%AhAI^&lsV_^`+^I%C+KbcR|uB)9>wz)SsUDP0e8XOurg~>6}uE z+|wUSk>Q;_(O64jx@@?r#B@(DA@1oi{x!VQce;mg8^Kz}pb=_V?0_~@!$$c)6Wp+1 z1Fc&WR+!E-(Nmch>O|0VrLgjJtM6rU(@pro45k}gQUtBKk(HPp*&``2-FAN@_w<5# zG2ZDj%j_kl+cF1mPfy?r<(*!6NK|5ar+bLRbWQ#+iRqk2RVAk9{*~vRF3^|GJ3Z3B zhI{%PFCpIPb3tMYZWeP)*Z5v0z{IFDUGA5f^7K-BGvRu0(twUwnSufUIt(-e#D;b< zK%*qEQ~f@H#G%6+8laH@=%@mC?=Q4Ny%{79EvQvM9cpO72s$keR=#+F`k->q7KkFK zO9qY9Lm)P^G6$ch2o0rgAaQ7ffzmB_X%MK`W@caju|dPb>`*qSu^|X$gBoCnNEa#r>KHqK*wB#hhO$8xghAP$084@j3plr~9 zSrwEGn&1PCYk~HsgGO0F<60ng6sSDufhq#cA54I91D#L+;(!bV4S0drAm97} zX@6Akes(5HxXtj=%x2L5{8lsS$%Xs1eEr1$#G?4O;jy z70L!JiI@##gXWkPg4y*944_=Q9L!;008MnPhO$8mJobUu(3E@<$_7~sItx=s0%Gws zs5r>t2T(T1;#W{M$l?!BHpt>{P&UY3hI-HeiV~1%X3#`E$WTx^03}Kg8#IpuKA%#8 zfdMp=A_G+qT3G@*dqN1BwX8tmQjj#^2xWt!88q+)QUeOnK&Ut5lnq)%06vpaih%*Nil7xL4w?(-hO$9xD<(qOpb4+(P&R1JaW0e%nlf4r zWv^mjVA#mYP|pBz9cYEXZm0xkqgJ#$)plr~rtR0jMS~&nZrW#}>XgO0TNF0<`85kH6Ky1(yFUUpdAdVc! zMGOqNP&UXxnngeBnqHj5r4XS=NLfIh4?S`^J z(=_!5p&ZcE`)Mc}G|zk$$_C8`gT@p=7VlzUV0a1@2hF^{hq6Jf@SjjNDA<|V85lt7 zLHj~Ep={91J3o{Sng$kyuHIKt&h>1A`GrTme#O*g)B!0?`f1 z29+%VP&R1rH4MrI^?(wgY*1+BK-r+7h%zV}G~L+1UeCY)vJ4cAZBPkNFiwE7LGcP2 zcLb>cO>i!Oii36!tb(#ZseJ>K4NBqLplr}o?=C1Cv`pqKhz+gSE<@Si;|8unIUpB- zP6`$RRZR>G4DUeV$`Id!21$fKwF?6S13L!;1BeYuH=yH!L2S@m8|WB!5F1p4i$m4$ zO)tD2xqAAM8-$2a~L1KgIKA0LEBymQI>3_fZi?aoQ#ir-Q zXE#r`Y;96eg+??BsEq_=3m~yUg*~In^fXr=eO2ht22m z5>??0afK|Vh?{<<=i%eHgRute&aAjZsHEQFgGp?4EpMKz>0L%0f z$|@q$8xmv%IM293X7uBxTRIiVPj{%6Vws-sxkzMsfm4wHCx;u%x(@%=J$g}D&GB89; zKX`#(WV);)FF&u12Lre?0vRAU-LYCodisZ>preQb14X7A?5Pmob@60i04+-bsSuu? z_{Bte`i8i27RD6F(ZEx_m>5W|G!lII(d<|Wa4w8*v zVPI$h2Zt=^kU`K=Jx~b@lG5>EV0gj+TH?XLpfp{vR!Exl4hsW=F+_GS$+Wr?Pf0I!W7LW$ONN0$U?))}mzgNeaM zLm%h}7T~?%$H0)m2ywH{biv(C(yX96Oy)sM*^|I7pz9F8z%T=<1eC2nUIqmk=>8DU zjwDz>?_gtKxChZ!@gZ7(_eLNC1E??sInZEwp^~yRE9kO@s_7Gzl$Ciw7jXtaO*NW+ z@wiKyC zA{ZD>Kut579=k+Rn)L)H1A`~TITMyh3h+uqA+n#v^vEe;(ySs}3=HgGC8CX>Vi75t zLGvgAV5#X(j`9oWRzx8p1k~{XxepWwv!VK+JE<6SxEL4&A^Ij{%Cdmg!hqIHfRYD; z1Lz(Zh@6auoB(S87Xt%7m@f+Mri0dnffX_^B!HDpR8kh1ezZfCpS6ICfq@&M6ny9a zlF}NujiU0PvKUEf0@wo3f#2W~9Z6;Z7XyPR#5`{_O`wSxs8k{gVwDoeVHda<7(PIB z6=0EKfk=TmE%1!Vz`y{~1(li(wF_hz2!o_5rXRF-5}Cg8WgNfmgeV3EP;U{GWI&tN zV4)1UhzOL_KzcyfgNK1(`gB7hbz$2jpu=<+AZr9cQVMYl3_k=Qi3POs4Q9kvG^_7R zGcfdl4;mK*oyCuAdafL3eZ<1e?84L3O9VJ2@);OFGt+U?4UbmHv&JYfFie1)NS<-D zLO}OMDFXxO@F9?!L2CzL7QR8V@Qo4!!wiVN6DuSIbbZPZ*$T889HtL+IuNpJT9g?W zWWa}|%l<<1>yruwhAZq4zlKZ?G!GCq29<80U|68dzyLbZAH)V>kcl8H2C5JlAPZ|j z;x`N+ho6hevoe6LtN@9Dv9KZR9CT4bs2;F50|SG%A?Wb$!u^5XzxHG-+o2alX_%bS_SW9SRV7S8y@k#Xb#BD;-tkcaI7~H|C zr!Pq77T|qg!@wZG#sFF+%-}u!;F>fU7ANo;p5=`VE^g^(}m+Ag7|SgnL2vLQgx zL~_~|O%WCoV`D?KjlSTE^0?~6jkc>~E2c6D7$a|6G&V8VJ~LNQNgl~OiS0Lg6w?Bc zM8vnp+*4!{pI+!BA6HBAaYvX}(?er{XpEJ$nyll}l__ z6j9nI4KtZhP*QyRAAP0YB`6{yOO+Nk!9^xYNo>EWuH3=QlLHzKVgW55WGUXBsjWQ8 z2Chg@Qk>Pu*xbwneBeBjO7L{I4COS?x$)B-%o$~-KdAEIpRTb-l4tt$3}wCPFU#$C zwzFm`J2Ot#+07_1Jt0fkV0wX=pv3eELaq|i4`eCZ)EgijsjS7%z`zqM0GZiEignQG z$)K@wW>ANiNeHyNgNczNl?#05*<8?FW=DA#7?{LBd54LKy^5ECfrSNp>@u@5F9QRU z6sV`p#KOJ6(TG(OM7!CnD6B)PtX4|Ek8s13*r8XRI)1a&uKVdSU-sqx`sU|>-MojJD)QWQkv^Q*D2Y6uWDl7%fP_k z!pOkD0osbo&%kER$-uzk1eRmVp6-{UEX`OlJu639S_(AF$?}B}q=D@#$b?@IHn+g^ z`8mpB?zcd-3>SDZo9mti zs4?ao9?*SkpotFV8PosdC94p90po)lvi-(7S zftBkA=nONiy}S$z>|9$o7#KLXE^{z2aB{VS?tbH{cLr5wT(zL{qq+Q<7#MiD6!;hz z__)N`85sDvp7Ss;2yn6RF)#>ntpN2Gxr{*<>u`Z?s}tcWKRHU=ZU1t(Xw! z>I9vu$+Ze}!4?+}3j>1`7w8-_X)Zq&1_l|fekKM6SuSY-1_n7U(0&woE{l3z1_lML zFg6ATMXmr&1_mWASuW5~VG@iC3@Tipa!8dc2z00$7w85%b*}dU3=A4vpwR?Pu4~*3 z3|d^E+kmvWKqFr|T(|id7<9Qnqi1>yYz}-34BR2C;OGR6Q*q}(*gFIm7`TPmK;i;2 z_1v~>prv(!IVIT)+;(iBl)@kc>XUQZv+;l~#uNGnIyl>b4K#2hA#{O8(W?%!Y?BjN3d(F(iARxi*##Rg(h+7T{UUxRo$Pt5(upk2iw+Gk`7Klln z^G2JTd_4I<4TYtz6%AOc$dz?}~E z1OwYOkdYZ|pe261EFkls*t*c3JfHdPJ=2A<1IpccOX56@L5@K_hv3D=rD4SXWk15axpOQ z++bS73TjTW{Q+Hnd6NmWkWW;Uk>?K6>UvNn2W!6z)eg4q9>hAKDVz)pJomwF{x6=L zTFJokfC;n?nt@RaY|TSxc!|k^ob?E-P>@l~62yB9mJ?zW1Em?BCrqF;Bg`lk1qz|3 zOrV4FMHm@W*-Sugdd8#*Iz*b8k>?fDces;Y!<;nzOp&rA!LI!ZmD&WV z`o1%LV+D;>v#kZ0{ga8AgMmSSljjdpA!yhNto|=lJvc)DfnCNXvyR6El^x@GS`AMF!As( zUj%6Y^{9Dx!Acl}Kr`_?{9q0v16wHQ{Cxpt(1n3)py?qVNoG(H&*lUQadqa)pmRwD z75#b&d@*91K+?zY?SfbWbb;R{^+*QO^jvRf7w3O&BxRXHYwefjNqqfq_>QWS(Rs zXk{p9Je&bEzREb~JvRe`6lk<~2Ok526zHUz!+Z=3(x4IBb9@X8GVs%L8Dv2h?lMYA zfErk!h3RMneV$$r+%9Uf}IIps`HGIiMwTV23_|IrKe<0cyH~ z&TUlyjm3hDte+1x(~voy0kHJHRQlRv*1(aGqVF!vuDUeIS(E@S`$n#P*pxIo|J!8_K8Ey@Jh(8Tw zKo^04`ZzM6i#kC4T^ZOtATqFfKxClTPB5^8?!o}s3+@bvGN^#urdk8)dz@gZ0yUKX zgMkVt*{Omq{bM=FGzlaQvVozV0W84|N`lMzpj`@P2DMKhAB#?h`$zo(XsiWveYu+Y zY&Hf45a!cRH(+640AWUP^$K4Cz`qT-fNg`A=c42*Ee zW79vXFpEwvD0X1wN0rf@F3_kf%_u)zr%_p*(P(k}&XjedQlRY35%Q1a} zd?d&8|2AR*)9pcL{Z+82@J!cPqaZPT-(_K*=?@eld8XTj3P?}1VDg7=JkzC5G4pJ1oT8k` z%xr98KK<=<h%h<%6A*m!eJ~J<~BtAJY zCnqT}IUDInC#2ZfvqeF2`pP-V4yyU^ORT^rK0(feg2X0LY<(=_5S^@`Av#@XuCmqi zwmB^Pki(kx_NB2;KQmWZkWmbBgwt0gZiDHa9|L%%^QtqlPk-`LQIOGO`aLCX<>@oE zqw>NA4GL6w%!^ttZJ;?qyeQx+6~&Xa)_$%rUI_8kjM z&-751neO|qfhSZ6A_O)GR6s%xk`qw^wdxrdKvgX_sDll2dRwl_jC7Kn1giGDJ6s&22D!)_i6CL}Y0dh+`nqptJy) zS_18X1$kEmg`n@+w+0%b^3#e>=x=?vH&-6F4g%b5IL4^jm0%l?H;UhJV})48l-0C#dlNRRh{t2%F?pMH1Hru|c8Cz`&pnT5u0#TOo=2LfD{{ zRtyZWAP&^fWDpy)mWhFZAswU{$_CwTzzAhmBdKXYV)r7k7a*}WfY?y;w}IH8kYr$B z*u_(i*dGZR#AAd?TmvZrr3VHEhC3iORQx>>`#*>cHIx<9G=i$<Ikpv7wr4L2OV01Z~>@Sq5eIAc;>!Vy{4A?*Or( z=74qp7=ccl2c^D4AcH{1H!(0UTn8xvB}|a-L2Rf7&?p3>==5hBl;!IGg2bWf*+6UH zp=^F6wgeJe3&aNHTLuOOV65AET1~nfU7#K1@Y^c2rNNmtm1&neG)BpEGvr29O zNr0M#3=9lAL2Rgoz0-SD*~LRa<9x8tKaV60x}N|hehW$b9ugb8-XCh*OC<3R)Ay>f zi`V}~68ewCW&<@qq1w2R*q|$WVOE0fXM?fjkko+2a$w?`NaDIkY*17&vNKHgep;(H zed;|q?d>_6lzSMX_Ji8dpm7`q28M?qHZ;3_2eF~qj~CS5g61I5;2kWngVy&kf)XPG z149)^4KzJX1F?mtXUP{yfv*e!EjR_OfCCwK6SNo+bj3Xb0|ThzB?PtaJxH7#Qlc}0 zM)E+4L0he%Y)~;J0b)blAqQoH#8sedkQOZ{8{{lK7SMt;(0m_gz6B%!&5hs{i=bg} z1_lN%s5oe7HwMH8>11GFNP@CKbG#W)Hb_k#lnrX`7eU#e0=)&qh6X?vl+6qp@9Kkc zKz4&yDMAxGc#)zo#K&tvYJ?%@QGk})3JEiSJ9Rsu;-D2T`=M-*Wk;cGP+@->$_6#z zFGAU%Y7n$BScpTIfdN!w-QRw2tMY%Q>3?=qsIbm3V_-0t{_u*T@bm{&QUcQz;*=$( z2jm+Fu%0kuVBncfP@n^$*@ch*rhBo{eV-E0IP;M$U4Pqio(-vb}0)? zFG%EOnV#}UKxBGCORxZI1X#KdB;5m&PIx51GF=2Do$)4GfVIP%fk9>ZL6Ec$i@d;e zhfrIV>0dY{MWz>Ak`iEDW6r>kGhOhyqVRN`-O2*fFU%2Pne6gcWcmVLKaS}!yOlW@ zw@h~YD?Ytux3U0~=}^zbF@4Q$We%|F=|`4JicFs%BQ3xxVZp!SYn=YX;R(+c0|b_bNz zSiMCV7@kc3Xu>Ewz2<hK);}eWw3ZQaUF;rZhXr3C%$0(B zW}Ri(v;ca;?^%|;%!?Emr{_OaHWRghC{bi!Sjoi0q{;Y^fkDP@`mU$S_onOIvX_{? z;hC}uK^!#9 zP(3~TwQ@3J+w|S9mF*ZOP5<>;S%V$4G?H57V+^AKgE**hdu)2vTV*vy=jjvQ zDl1#OVPjwr0~Okr*clkaK!=Im164Q57eSMoCz$?&0uej_@n05nScx*|mQI$FOybku zyj3=n^J8aV06UC}K><9WuNV)SN(I$846=6H9o{LwW}2S&-HLnql$~}))BW@6gr+O- zq_a$~`>3qIm@s|*M`eA+gze`)Do3&ibA#_`0NpbHx|9Ocx8|L0{Y_b#k#jm@PO`-I z{BO!v`KCMgYVb^#kTT?%UK^{#GyRBmtjP2SmL@FI<^S2~Os~5pEHK@`D~M-$fv<+d z_6Mvg#Z1!+cq-$zZ{kqVVq#3#ewRz7m{k-M{-CozLFYVyTnl1HOivY1QD*d*-YK9W z9SZ6`fkZ*mc%TijBC?R442TWuLxI8{Bo3;#Kx}SM1;fC=0E%~zUXbaaVJDCpP{jCc z|0$r-%*hKH!H2aF1g6hjY$;yv4;n#(whJRcY|zQy3=9mhpvg@rI|E6)4T(J�J&u z3=9mQ<KWE3IS(=)G>!&p{oDd6f>!RJNlcicw;*w- zW>(Oy6ewF3iLD7@LoL$-v7u_fCny;02+w^@AKecU;w2!(D^7JGePSVzn5JDgul> z)Ay>WsI!8WM@K+}|A2(AOy^ZsQD-cfez8$Xe7b|0BFppubrl|%K#97F0BZ>o149Qy zkIy7A0Y-=EYt>cMS^qFGFua~__)S!J`Wtl>f$1Cc8d#=jsHm_$2Tg!Xzu03XGTl}~ zg`XAF8HBEl`ryaKGCe~>g@^IR^imBKb=K*;@LKLevMkH=9U!>}(~pAWKwT{ZNDaus zCNDT$R8s{snqmv0?o3YwQ5UB7YO1I+ACrfybDDleQ$>K0ar#|N6?Ili1qKEUh;|t* z6#=FnHq-UARMc1#6&M(e1# zVE8z_Fic!zIc!~?4@$6mC4q0nM5i0BD-~w3G_thZ9(zHBos-dWdg@IT1xCy1`**2GOrLjC z#e><*Z$=OTgW zTOO-QOkeX@lwWqfd zW1p(3Pk+N>&N02`sj32_@AS1G@v!MvK~%={zaZ(9FGT{=O`fSrFqTgDeWt2DeTP}2 z!1R`9syd8y(>Fd-^=Di+o$+LksLSDKjrRr~_$N9W!N^KL4HS9nXwS2L%=# ztbmBheqdk#Rd=B6S*sZs7>+}4@B^JA3ECEJrpRbu0JatCJB=pCY)d5H31skCPIAmb zax2#dRTG$>IS}I813suuWf3%3G1;NBc{zvRU6!-VdzpBort@_xC{6#cl#zYA@>kW9 ztc+RH-~Lj4KYhU|b&2T(2PGw@A2=k*HQmo9hHv_vJ&Y35suLupPv{Ah0Ix-x+;ClD zT3s#}Pe1cV)kf^RE@Whofq{jQ7c@_5DZs!`HC^tns$@NAqaZUA`%-ZR1{O2WCKN&N zdND?}9iXwzwbBd>%tD}p7?~M4W=SwGFf*~TN-{98Yz8e-69d)$ER*CJ7?`C%twClE zR!2bw24)WS&72Gj%q*)qezW-FE8Lv;z{HLlSxgRuz zx{47r2hV+lje&t_H6v*87x(Vz%l@hAd+r38y`FI;Xa&ku(E7M9jG)PT9(JaGj2ui1 z416;33=B;F89}GTG4Lj(Br-5DFoBjfGcvI4kYZq9Vq|&(()(q)+<#SZ`L&?M&;q8? z3=E6{cH9gMOahW(3=GTyZmbLpECT)0L;kB8dli9(Fa-XA4sQ`y3i7eQS5S}(MDTzV zaY-{UunNqTXJB9xI4sG)z%Eds%)r1Q06LtBQ-BAwd`;jRXu%ExOXc*7|5e56Z-Mrj z2=IUglLSE9FPQ{fR6v%3MkH7Sj!J>dyC(xOZz3beyqlaL^LW`97&rx-#2Fa41WtmM zZV9{-V_@JB_%F`Dz$*YcxQI`nONN1gUqA^otuL@yn1Ml1poN!#K}aA>f`LI;0JM=& zgn^|#RE2?o-4hgRf-Io)!9JG}bh??qIj}#Sq(FfIIzWg?;0b88oWN_)I!6IsP-+p# z0IiY{*u?~L*HlrEyWYuy+|?)ya@Qe61_o{c(7l>G0-(#uc?A{-F);86^hko-6{x_# zARrK1FAH)QX!=x0pj`~)FkvMI1`z?!`97ioC*(obnS=J=i3?m8WnhpH*e=b$ASvJ^ z#K0gW@DnsaE}$vNz#tlql-1bjFd7}N#40ebI6z4V zbdWZ)Ksu<;BJfZJ6q|>|z)L0M#`Qtc!tfH$MXd$9zWc zL5mD*<)HOT3m7#)%Y4+tKznJxE@xv0xgeOikac=FlbWRX6=ntoP9umON=n{%LaJaG=f!OtovLKJ^ za5gf6PBP;wQDI=Yz9lP@O=?yVBl8PW=jNl={9%`5sw7t17^^r?|d6TUVF$4Dl!@PzVkCM za6V#o29=n6prdCvA2WjzDJS1$83qQIg%;_7<#6gzpr{!SBEv zQNEp^(0vc)h%vD3<6>ao{KPB|T0Fpnzau6ulzGz`)54&dwZ+qF@hm zuz)1Nn;!tWShd6zn7(7Lb!97#Y|ar5PAFd0Fg0ZW3YS6kuTi z?Y{xXTD>5$ql6%i5)A^aUlV3I11hE%8Q5ln;y{GuB4|;v3?rumOE_o+ZX#$7R+0sj z0=VNrg@P0dC@{G_L7Jt({^tG&3Md({ecY*_)F;aV3QYz!P=A?Io<+b4wCem0NJfbz zAGD&Z9&{QTXj`l>h{eDOwu`M*gn@z6j|G%6#s7iIBQCL9(>vJJ9P6!A7#O%@CW5vC zfh#61InXI-0?R@DZ-I~Upb~a1sQzc*he)eLax*XpsDNf+1eOYeq>q8C=XWBY>U1}# zog&Z$u1?zpLDlIgPEfT4I+2V+fP)oOZDoT_FA&I)U|`^8;H+o41-F`8Y68gYG|(7= zK#dT{?4|sm!hJcY?IdtU095tg6=GmuWnkGM&cMK}7|#t_eGaNmxvh4A^a`kebk!+> zbnTJ_%^R@12Q6^6n+>WNYCuf_mn86#b+D%Juk|2ZWuOBy1R6k#I0UW&>VRjXg3p7TjFBS z+V>1ekS9wdK@M#IwLk@26u{Q_3oJ4bUXfwzyG7K!Dp!&20 zblRJw4o`dicaWw3K$doZ+NlgutstX1L2O2;@1Owa0_PgvK@;*UQV(Sr7 zYz`?<3C+_BV)ICGfLdpLAO{ObF@n_hgANQ9k$MX}+a^gL5Q%{2`MmQav)rv~xDgLMVylr@1sZqUwgd(glY1B*XM z^J*qOxSDm|e4q_Upb1w2@PxNODma2=LA?S7mKad5?NQ^a2eq?!_Rr>HV33*!^6deT z*$j{%J_rg*7Abkqiq}IR^EjkVsW33`90oavYi#TX&Lz`&;t@*Ov$F8Ee0aG!;ThY=K1EPSAmI38X`Ph zYK%MKQtB|N5_ym=9mXqgDP6`1pz@D_K_-Lei;W-ygRF@V0|U>mJkY*}=b#MCzz7O^ zZqOJs4;v#WxVafYO2ohc%fRm&_$!{m9s1`U3DlrAVD}$0>2Dl&B1MV+nGlBX``Jif4fI*OfflFYu z9H_sv2jp4?aWl|iBs#oWPXrklq(CiwUTsi;#K0iFS)PGGfLHG?NP=6Kfq_>alt&pD z#IJ!iZtxn3f%-@oDS~42rzIJ3tcM3JeUq{vaj; z13T!3&l5t>G^W5H{!yx)fq{cJ=q*U4G6w?#Z!oC*V~~0z#=yWE0`eFOgSa*aNKrU= zzCA{ffq^#yq6l=3GH)bAk&F(n#uQ-&2H7tl7wUlGO7=d;Km$V_@KQ28EFy9s9%^0P?IX zXuBD2D99tS8$}oxc%wk>XJFaR&A`AL4RWU3O;D%sCKEHLtdUP-V7kc!Y7xpOfmk3h zg-iyf+f1sU<+}`=EEk0t7!*N0GNu2Za!r<*MTCJtc><_fmIb9oWhPKhQx=paRrEni zx8yxQ^BJnwBp4VNT|tdJ2GGiF#yKZN7#P$*d6m(X5!85O3{nScb!P-6Wafz<>NJW{ zOBfhE7>|PnK^PbqrppMbad?B;Kui-Ow0e{o7;cI%FhCY%YlDW~uIn%`^oW4YRET1l z7@@-$4KhWCF@}jFLx(Yz(SSi0v}o;-4g-T8XiDqt^g?kpV_T3R;DSVsK@sFA)!U#6 z93v#BE*6D3)d^H`FBK_8rO&oY8K0ibb2wYQ+D;p>`~A>iV33yp#|ZPpo_cVawPVl)9q9#1uG*lJMBeH!Fr-OLzqpN8bh?bF zn!GURz*Dd+Xs#I~I~O9W1Ujfo2eyiyK^Js17FgW_1_lO@x+@TM(`SjQ@e6~7RKT*J zHS-`@Zb`5mN*fqJ?umosF9uy!Mg|73I?&cmkUA%by6GHZYW%{AFj*5uh#i$sS$i=x zejz)UENGV$NbiB^31Vud^`ITLpiGN1Y9YliD2%~zDa@bH%T!lf^1h^016k-23c4Tf=)q#1R4*DoA?-Qrtg+O zb5p+z+)c28*GUGSo3IqT^&msQZW3is1lewK7qq?*)JO#13C=j@fD8kJX;Nt#1EVU4 z$rz*yn%HFot-a=C0bST`0$QEN2wt2F+Ooko2Xw5M*=j`w21b1llQGB~)cH09-MS#l zz+jQdz-S9H-;9xg!LlASI>%@S8l1~!WMI$+89POWfk9Ok;*nw&23=6O1`^Zr2c4J% z^h;b+1;GNK0W+2->IHgB7@>-pB+R z(x_u(V6X<&zaR;7&@eQplivUutWHcRV_@9IbU}`R;UXgggDz;HAt=IhLCFNn0FA4G z7!391poN5>)ilfH7#M6oO)AEtOrYixXa+>{s6oYe2CM{hp0F;c z#0D#YRFa%5p!TRqIH&;vx)Y57wBep{PJ|)@gWV)hQzQ%IEG{Mn25=IoXUqbpkzl+3 zpsFDYq)wZOfx*%qWIzt6t>y*dnt?`c=75q(BNGFI7O2pVQ-mddb5IrnEo50O&%j^_ zPEi{`O1Fb_ZV+H#VB82ADFuyxXe)r`&~zCX8s)(WESk}RL0gZJfdN$b&jO1@GnFvt zFvc)iFzA7jD9CT1xG4dpUr=Lyy8;7)Wt{>81LJK3NfUA<}(XwhX^&oG8+hkin z^&2B7RvENG8TyzE1H);EF-*k_4BDV|RZ6-H46oo~I-qr8;7U=4K^t^CAjsyw5NVK$ z+d%hb=`t|ru4I4&r#7fR08*r+2=i9GF6g*OkeDv$WGRqqv_CK~Fn|Kt1ELDF3{8&> z>O&pID9{n=oGhS(0I7C(LGcMXpPPXJbd?O_93dqJ27ORhh%tf@l(wcZGcc$<1NGJ; z89{Q4!Rp|&70o!8)r*0FX<~pjC_`M6V_-NAv6A^SV~`GGG*b~M-kBx_Fld7|CW6YM zhhPOT8Bn-@8cZOqzo+k)QxmN>*9CbENdW^V3+TWNRnXo#M$qBj3=E(HIT+_uD={#r zfjVZ4dl*4%#vnCCP;-0_Bj{*P#$avGv5(HW3=FACAS0ugIR5K^w%ipnFzA6>Cz5bs z#%M-UP#1JIpAQ3rss}#<10!gR7;@?);~Xhv1_m`yPmfWA3Dikv3{nFvjARsL0?9B2 ztAXN!QH)6e6hs9BXGrK18S&%TIXWZ@5`$R)+d8ToLO2y z6J(*FwcrZi!U;4s!Z;^GnSsF(Y^4&|N(Mbpe*w0-ER=Cn3OU9(ktz%fjz*vXQ%xptCshwLCYcU0hcOCt4Tq{S$gO%{Euf=b80UzqGBBut z#@HG4z@0b7Abrpv7NZ`MD<~tdvoJ8Ifkv_z^}##k8AH@SLs>9hs2XT63&so6g|#2F zK}9ggbMK~a+{G(4eT$-+Fk|s_0cADO>30>?`0M>a6@@L>9pK`9PAJG7pw2m?EzBLD z?m43^*jiN<1_oVF6Q&+i)v8VfdE5i68x--3a}I)ZgL>_Z9#Gxj;-OoYfdMpT2`UMT z7#MUx+bqDTgcX!k!0j8c>1|4C0`<2*?g<2&2not>AQM5|ea1j=P%;LA!*V(#ESW&p zo~qh|Mh4QrjWbZ4&NwGnje$W8TpOh^f@&kiAT>}IpD~RQR1z=-Lo#?eB!h?OfvUg7 zU<0R%Dys>*{sSd1(C&Q(@Lgeyb2fm?16N%+F!Mm80gO2?^Y}nbv0P;H)`J3Byx!># zs3rncDhv#u!i#avOHEi!91gCDK{ts(dMS}ipe{FKu=6!x1_n?G3L2+pjAe3FXJ9aV zE6l)IkfG6tpsYz*l5E^SZ?1Z2#|>3d+tfLd2zW73#1V8(#9gMfXf%F4iC3sV6$26R9c zxFH5ICTO~>D%3Tg*artvCeulnF+Qx&K#B($15*JurkIt10o-B(8MAqMovNCG6DVvz z2OWV%t{HQfv^1ffYJ(Xw6J!ib1=yIiAY&$ij_}fDU=Y!q{y zifjxF;EEDt#HHzT)zlR0Wk8LcYH$_;wGJ8QIBUaFTs1hwnXoZ1sCA1oFfdj#ftuiq z!D_z*5WEm`Q0W`Yz`)S2#lWCZT$IefSkDA9WC0rkgGNem2?JvTn7^5gfk7A4ItN$D zpfcx&4nsYIE~u6R3xU!Cs3g?|t?~wofMx+fA`IrBVi$Cv_IbD^Q^1BEgIh8c%)be; z1k}t1>jy;yL_g>VV^B%NuMKnL04G|WEDF+2wqY`M*=t>PW z>3TI~1_o`=SRkmn1g*%{VT75i3u<1fsW33;g2D$>`{+((U|;~%DPW(23Uyu3iDRJh zSr?Roj_EQmfO{06@-;#S)i$IWd&WK%oqhOcfmblcL_NL z2Bs5CGjtdj*dPn%6=fM27~EHa=6_ByZ2*abhEo_Az~Ti`P_0|;|+aCkjYWMBYcPIV5i140Z8Aj}!W?j^&=zyQLWSJ}OE zR2djRm@|{zYrZT4!~9gxG`t&!7wAxb5ayiB;iV)1S^>nsz&W483$(u!ggI}sds#Cv zFn}=U8+I>HM<0YaB{{qlCriJvCj%>ghWAY8H&u+f((`JlGktrmr(o^Jlc1{?ANpKMF6K z-4-;H%&=m*pk-6+^aEv@EYlB2YVd7;Z=uG>%HF`j$jr*gHvJ=ip7?Y=JGJ@K6>bId zOh1s2!^X}J-ju+yeT$u%ITPc??Qa~^^q4iKv4FNGFf%YRGjZ~RMhsb)n3*_*7#KN0 zZ7fCx&=@uY1M`CEelBX663bZ_nVC7689>__kPZr1KmELmni1pP=}fL_dWB{DP{2~i6x2gIjMQuV}sQmi}MsGC+5W$6&HYo;{ zGfn@vNKhCwNC7^A^f)9-(Jt((>R+fRJK;j@aOdPZ(1ttz+!^A=BLSf<{ zHcZ?cG(gD!*+Kz2p$4>wUWtKWy0DeCASbBV3$iS0`onG`_2~yJO?b9v6{@XZo<8A6 zFc0WJB(S?c#hcXhkA51;(+&Q*@k~$HQ4Bs{fM5W`0B1{&R(-q6rMHwxp zUwj-T!fa_^G+l9~h4}OjRpAoT8*F_+LWa{DZGDBAEi5gjGq$LSGFogGZ&5R3V$7O; zajKE{be{Vh0^1AP)H)a$?WR98mJ#1B(4nTq1~S_Jm#V__m_9XbMvLjWerhrxHYc;C zf#LKCeQGL4E)f1&pTK z5A~}pBo4IF3UX90hz)8vgT_u_>On)MAaPIx z?SSe9HQ+!as4z94;Zm3y(D4W$Ht5(C(CDd%5JNrKV$i55NCIRKs22%hgSy_JK~$JQ zpb=A$I7kg>m;l5E#V}|96{ZF>ZVD0ysR13t1!9AGMWA6+m>SUNDM%co#+eax%n{U= zUegQbtI5}cQV6KW1X2%bhk-iCAoZZ;F^J6#3NZ!-22d{On2MeV}O}mMG09~;K5(jnp zL2Q_MP!<7+gC=7@Y?%6QPzyi{6+vv6dQjE@sRxbwfY=cApfmbGcfiLnFo1ePLZCzJ zpgsWQDUb$GWe8$JG%zrLMqNPSpy_K68)gA0Bthb!_9KW5Q|}KoAGFyG#D=L)0*Uj+ zF))DIBOnfU<@9rxHKVqdEL3~KnF#9Eh=8tFU|?VXjX{Fgppzv)n}$U6Ajd3#h7UpF zpvVQWxmzHC56ZqEaZm~dv0+Xz1BFcn!Ui2kz`*bg!U2Z~D`R9<#P&vFM`CBzF`<^-Mw0l1#QuTA1~0#csuu(eHbU9rNNiaoHt0N5SV(9hiG$}%L3%;{H${@L zMq)c6u|daz!3^?65(ghF1u}?%fguM;yaxJ*!U;8KB9ev` zNbGe;Y|ueaFul8x#E&7d?;^1uBeB7UfI#f3X8@g31v3b=SO&)C1@+h=iokb@!^9<# z#O0CLpk=NwHQ*CLpn46F)R-f&?Z9kM_%kptgn~KX^v3|c2NbF~5lI}>a)Vg_z7rIx zrUXe%Hxhdy5_>uldoB`ti3$>DHxm0G68re{hbPp;>#raQflhpdx#csGIA~uOOq?5Z zWCqlY;z(@JA;B;;pan@Vwl$I(4H zNaAn!ka8+BXgC(Ch!cs;kHi*5VoM{j6_MELNNhbMwks0b8^QKs2t;rg!jagqNbD3O zc0Ljtd`l?Q(H+zGo>miQTsU3Orbe7`&-90<)x@W>oKdr3RGEI!rbgV*4m8vNRqTz# z&O~CDA+cMgPqeKOub+=3v<8X23yFOkiG3G|4LWub9L)?23}2AMK`W$S;yi*33^29? z5?ckro_^S_Mv&2VI`3IE@!VR77`Q}fMq+m&vHOwOQ<2!Sk=P57*vpaFYmwNSrx)7S zh}Z8&5;}^+K7+)*fy91_#QuoH{)fZ{t>1-tSzHL=ePtxJ0far>ds2;Hy(feN_ID@} zI}wSUhs3TzVz(o)CnK>zyLVuYSc4>f5{Z2k!Uknh28M?a4%iXzkl4SF*leI7FlZW+ zMq;ZWu?>;fHb`uDBz6!IJ60HUmoe1P3?zwSBz7GVyAz2$6^Xq7iG3Z3{TPY;4vGB} z#s>MH6*O-Ebp#KH4LXYkv@lnMfk7C`mIjGK)o3EIT|n$maKJG{fY?wqNgy_8b{up{ z7KjZsrx%GmO$1a(K_ymzBtRPwKsUT0v3DV{4};iHL+^vwP|Kcy*wDTEuRxB5vcH1F zp=y{xYqz0nIS?D-=z0bt5CL) z4K;Hohz+&t0Ei7b-wPCYM??|le4PhLKo#9ZV*dcKA+BcN0nGqF)rf)Ez93T=z-OYu z4n=STiG%tHpwowt*fAhB)X}N+NSr(*b~%U*HFPqF4Yh0*hz;tfFfcI81MPx?vR8t{ zp=!1xu`hwxP)9!lv7u@{fY?3^pp%ms7`}>4Kli~*j7dHV6 z8`QgFU|`4vv7v^PfY_kf83qQ13ULMoVJN#9Bo0;62Vz4VFd4*#iZ4WBA3$QC08 z4rodW#&$;1-~(n)e`lK_R}b390aH^276%!_z|f4uo(W<@9kB?By&8$V1;mDi?m-Y6 z>d>DcHZ2gXUKm7#J>s)I-^KK;lp}FJ%}QG8v%~p#2QOiVO^( z>9KzxMNl6zgH|{~HGuXzGeX6MK;lrnYDjE-B(?(*+jIIsWjk@UG_cTgv1SRm`srXc zBxSBfVsAlWpFm4WoR*M1yTg{ zlRbzH)!+eQgLb7eFfjPYF)#=#Lk7SSK;lsKsUS8~O&$`v9EshC#BPO}16qXECkHBq zp_a`ADS{e055$HVx&n#42C5k}qPYZRrC$Sh8px6#Dp+k=R6{g~4K*kM#DlwC!I8cN3gV<1mj)2%u@pB+HRQxiC4bjYS1H^`^c?4oZ)jS8W zp^kVB^^6N61H%W9I8^=ml9}X6|}YvszDuzZGgmfMq>L+4}6~}UY~&^1YVv8 zEm_(@;!ySkB=$@Y8yevAL2Rg%JCN9Ckl3%0*r5G?;4M<1dy^Cy7#LNdnMVM^0cT-l zB(@F`+Z2iIiNsC;v7rHy4Pt}l4j331@)a2vgrV#zkT_ILD~JsZ|%rgTd0adgd z#D;1x0Ch=G(&9pv>b9;y@LpA+ei4 zY^a7#5F4}-nSp_!7i1`uJp&{TRkI9}wHq@XwNbFTe>>VIB)X;-S?CT&l)b|gN*e{XT??G%cQ22uuH>e^~uRMqi znjT|dU{F?NU=W6~^+4iK2iYL8-9c=qqkTYZsQNGv8>&7Q#0DLE!@$6h2r?7O&H?3r zSo5d~Nl_mXdpZ((C5R36*(N0RZY1_05F2XoNe~+}rN_X)a28}Slzjsv4pvjo!0-&j zfl7P_vB44y4F5oE&^kg;`cPwF5QegO)exa2jl|YOVw;25Q1u}oHq^{$5F1qUGB7a2 zgUqala9;>^3C!6c8J#ej|ttRlftohMv&12V^LeeF-EEjhgEqHdOsf5F4td z{w-7ksCE1oBmvdHrp~|sYol?4*ia4p>I@9RPLOqa5+HG?dRY(~s>T3`?S;hlgX#qp z32`9tP-yv|4&i{y{~Qn-YES`^hDwk))UrAd8>(g^5_>fgdp%SyXf4)$kT_KD2_*Je zbx`>aHRvLehFeIA?t|D+HJ^~!JQ@rPj8Jg_4M?bfW?wg_^e_k-9_b0#CHp92zys$Zx9D*vI1 zwtys{>~l!$OHj?A1y+wh;!w@6k=P$VY^dHZNb3KB#G&e$G!daCieO7I=p#4`#+r~| z1T7bIo*wwXQoKG8NjelsIu0ZbH9Hx^hT30-#GZh}o&wbiS_HNLBo5WP5{bPI#Doq;pDRETP>XjUvG;=5P>YWtu`eL8uRsj~ty+8m5{H`e1Bv|?#D^>2xSXs zgVHCIBZ(xT4Pry90TU#)EfU)c#D+#kAcze*#GwwV1F@m%+d*uI zntFyAAP%%kJ`co(NHDAiu|cIK0|UcW5F09f48(?xjhq3oq2hNzZ0KOkGY}g(D)|P) zhN}6B#AefBU|@uez4CxKP(`9hY&j&hIuhFeiEW9*c0ytYgV@l)<46!2YJL`o4IS|= zs0VSN5^W$hG>GOQv9}?y4}sW$;DVgtIEW2Ze;LFEt#M&sV7LKdL&fhPu^%I`pF`Q8 z^vCcH$^jYs35op^iTxLe&7_OST5L#cUL>|45?ca^ErY~X)@4wFPmZZ0N$4Q44W=u; zR1=r9K@xI7VtY&v1WAV=3B@3>6Q(zUq;rsjN|4wU(>K0U6R&SU66!%>Pe5YNKw{59 zVlP2ruRvmNKw@t}V(&p>AAqnSsrER81BwKO)7#&^RO1$^zXsZG4o&Q$pksES86pJ4 zhGrV@LB7yormY}x=&(vXXju<*kl_i44ed#qffiLj`(D`~HneL5UZ?@>ty~3(8$eqR zZ$KPq;~l&u0@@f41Fa!|wvRhOY-rOIbcZk_vS+@NgG-XtF=8?=xu2+9VXvl#w1aN}RNCR#6XJB9eot*{}2Su#{NF170 z)SzsT1v*eR=*%6^orXe^kkK*=s5oc=sU4IJvdaU+u9t+YNAm%3K;!bD#x;lyO@OIT zHpqf(C>vw}=+J2)8HfetP;ro}2LFLjhC>vB3oq@7J zWfAC1IFMdYIdcOl4k}yjK-r)ucn@NO;t|x8gt9?RpWje6FQ^X>Iz~?jw5}dBum-vu zRTVM-&kJRP(w#7r4RWX?lnqMB@=!LYWCbmy1epUWK((RbpiM1iP&O!iI6&E;;{e>j z?0U#?=e}SL0|RJsDj3QJ)%cN6HfU!}Jd_Puy_yPTgA!3Tl%2%Dz)%KdgHFV)g|b0= zqMM=YJO&1aPAD6+ShgRuk`v_WS_TG&sZfay1_lPuN=}e?9|Hr!La6v;1_p-ZP&O!W zZGy5vyKi?w+3Oh?81_TiTR`hlq3rz(3=F5C?1P~B5GcDIw2|gIlmps&bQj77oi+0q z%D&0KzyMkv3Ubg3P=!x zg9f*Sxj^N=Dgy&(@vtOR0#xS9L)l7<3=FDJwhHL504N)@c-Rce2JP4eU2G4s%!ZMH z0dzAvhz%NW_JpbdZNc`3vO(*GL!s<6#(D;ZXeg(Ek%1u*$}VMOU`U6us~H&>a-nR{ zg_6Zk_9R9IhDs=VCL;p_=b7tOARvQINIFl>dgK^wz&L)mv285j;i z*$)^Q7>+~P&lwpQ&O+I57#SEYL)l+Ij=l-y{9|NbxDRDBGchncg|a~#&fi1Xd`t`s zKcQ>^CI$x3Et(+TfHt1pvAW!wj&b*gA!C6wBu9@$_`;-V9ltF1 z7#KhcYlT1=nt_1Fvx%;93bML<+wu7=CdhC+zBFX17(8}sS}h9Y7&B$>4MaQYHB~I zI4D#?plnd|gKlmIsR8*X0kljP!~t#BPlGA~Rh>CdHmDK;or(@p1FD2T=Usx>po*ss zssyk`XBU*cih+UQ0F(_HYB~mGgDRU-P&TNtxeH>08V8`W`Jrr3^u6Q-mH*Ho zBG9eoLM{vppmgvRstD9d`3+@*vN9td0|Q76C>YtHY;YS8$_9m;Fq93d$|a#}P&QV9 zvO#-B^q}l?Q2XB$%E@71V6cX=LHXMe$_53UJCqFyx*#YUG%OSYW%n~MFn|u{1UU{A zikVPx&{o}iC>ylLrxMCu!oa{#3u4#1Fff32M@;~6pko!&plnbOffgwXxk6I-BB;1D z0|UbfC>s<)>!55<2!U=y1gQt*x?NCl&|cL8P&UYlV^B7zpsPOv<$$JiFG1O{pn(o3 z8?^TZbT1;vP*CCm-SrJ(gIY4LplUz`&Ic&FoPmJ>be<+i4Jd8>fr^99)MDaiU;v4O z(iR7Vod!M(f)B!B0PXk{fwC7fKyE(=X#j15Re*|vS~zM@HYm~QK-r*uWkygosKpFA zofD)Nbb5fzc3D34a6TrRHPg#v)cqJ+rXQ72_h&paT~t=xpGjox^fXy@Kc<+q)3?d0 z`!P4y9T^3xA&lVO>rsIJ1~ zv1z)RqPibv$R@ZoAo&Ri2Cu&vaK6b$`Z`=~GqI-!ryMZ&g+IXZ$n$ zDu^nXuBxW)&-i9~shYYrW7hPAYU;|2DbtUtsjD*vOmECC7oT47MnHhcWY=^tb#*ny zoav751jMJyWLgO@c1%xIS662R^&Fh1Kg?GUnZ8tAou7$e_w;Qbr9U7_S8!O+#Icv1Gcern)*4$NuSVn(AuPCv-`%FuFt3%}Hk$;Pg4nzyR96 zHGTTQcLMUP3cL&qb<-c7la=IhFMVM)y5#lU)54qXPhwoFNiuZT~%9MopHhR z#Dz)X(-*WxuuPBXmFHo6Fuhb;U7Zz_9n>J2a}s?7IBSl5Z!; zM5b$g6yRq(GF?eC(gHCY%HAmTUr z2Dn+KN z>Z|iJPMO|#s6u?YkG{G9>js405)l805a^ala4MMt;@=TsU=W|~=+7%M{iwb=KkFCJ ziJ%a>-hku2k*E zYOHqc3=Au#2L_7^PhW6MhGlw!u{saqp6R*9>gue|CNnT-PyhIgUwHb0bZ!AAk$Kbi zf%KRxXJBBT-uO*aboxJIbwT*uK>wB~No?0MQD@?0+_v4&R{et|qxtlO8%o7M7d(kD zn;Dxs=FCJQrTq#K+p%uFm8;^W;y{hUKQ{r%$ORV>WR z%_jQ?%Wj`tqdvt7ZmHgLRq^e<+toKLo_=6`sVJkxbOVbD3Gn9UgX>F0m@N#AL3cep zoo?5oCa~QqM&l+2lZn~%Ic6GC+x1g5_Asg$8lzccX<>#cVrgJxwp}n?W7ir~YhMa$ zJ`iKvw*8cr<^dzdBip-UH50<7GhVI}VKOiQd0Lp+($E;Z8=J+_z|dm5-WJV`Y)r<6 z(;x2ARNx1BFs(E%IX+&+(!juSI^%3j`RV$*HF+28mjsKYg{8^# zg|RN`Oe_z!--^}}3#h-G0@*wby6@)z=+bZp9tMVNWd;V&#%9nM9SAeAu$yW#FfcK( zuM`K}(!-jWSHi%uNsEDj348?*6C>Lm&|N$eK=0mvg&A`CY%E`dM zBnE0CuxtaJJueBq4d{R(g98JT6ljcwiG#IFgMopGgZ+*Q0|OHa>jEhd#oh)w7nFsG zg&nlCl8KRHjw}NM3+P@GW)V;emSyVn^=q^gc-ujD59xx&G*}p=r{7tlB`-b?bWe~P z=sYSGP#cRy<1%PXZ}N1ZwOWQ!pFzj)p8!?PEbO+RWAjgf*lg@i6{kD4;OY(sZ*>++C^>DeLh%qp*xI)<0 z(;3%kIWy)=cU`BYU}^z6_&b{sw0WF?e+S6m959EGKSYy(fh8AwRS66KLeL#bd0-9) zfB*DZ>$KD*|AG#$FJjDQVqoB21vG65(fNU=S8L z$pN}#nI#2uzP~5vtSuG;TX_Zsj>JEpyG}svO=uMQysmMlDIv)d~y@9Fq)~85sE3IP{r7*X8g(neMkyOG>O5 zbSAYCQ!pz7gBTl!DbrF`1_try>2({mtTZO`GB9x1GJz~$YCVfurOT59zdlo%K|0>BFR6ga||ezP$!@PlSpIl`GhA@7b2 z4WLUw}4pj5Cyviuw%pQV90 za{P6I3=ACUV2(TkCn)W4gYL5d1u`Q8cLEm!14kwk=yW5#432!Je9)b;pVSx_I0~3R z>KOPpfG(^m0$Z)X58BMYQ3m#~5xKHB92{3=Dis91TqKL6$^=Zb52f0;Na>{&OJTHi6YMGH|Z}g<3OHH9G?XcdsS` z1IJ>f?d%K;f}krlg}}s4&=F+3EFc&1ad4brst28;#=l3Hfq~;J*c1kS&{ZoO=fE6B zNZg!<#0>+t6es~+U^)wOj||6ECTk7`2L5%Rlz5Hl0_e05e$Z*d9M{4Al;8)u^aj`@ zDF$vC9R>!Dn@n6B3=Djn9QT=8L7MBqY92s+19rzlum(m*tUdzADii-lP)>Rbb_X*9 z_e79CpD?*YjC#p*9%K~Qq*ur$y@r}p2Xf&XWRu>)OsYQtI^h2u(?p0-pP3{%85kfA z|AK7PSEx}^pev=mfjLk|eTNyv3%bSS2h(j11_lX8slm(~2)dvKbb>X5h%;zgqe!+o z0|S$YxE!d|oTtvfP|w1^9S@2rE@n`E;_d=DhnpFcG591n#F@{5oCE6Tb4Y*3>?nPpuuf12@Y50k6a84;$R=S zflU&>1>J`cj43rb|=U^X8YM-?k*pp*X>$XnH{pi-ED zUmIj=4eLK{1_n0%YoG$EmQ{?0fq|W0U5J5!qmGq}hk=2EpB+?K*Rz7kdrk)KvrG&O z^&AbXN<82k-pslkbngw=+!kbWTanFeLpHY^VlD&sCy?A~?EPL4%GE7xq9+ z0@oA0te|>=jh`P>3ih#nWMQah;N%C*W^nYgf=X;3{`DaDP5?VGfFE>C4#z~WC4u}x zppcpb<^=IS0^M6S8SJoN{(GSCnF8j7FmT@hWzVUspg~zaFOC_kpfOB{TV^7=Wfs^i z^-#ym204a-lYtv_*%8MaR?z4uUjWB^){~%1YrtW$09p4!ux_a4MG(#W6F@b{Vu(i= zxTk^Yza^}o(+#+7K>@!G5`*j<8(CRFm%@Ndt>@STHI^BaNH()x1>G^pzOp zYc)tC$R>{cP>aAZaRBQ6dT>-6gm{2~dle{cA7b?a>GtM0#(EU4`#7@h6Hwh?%_kw6 zA%*ZMux$V|18D8z;P9vNX0*EF)(mk11B@_8=y-3Iyj=ldq7$C1~|&a z*UK<4aNGn3wK(W3JdRu7P!wkdsksdf7;#2W;^4Rg_NO@5L3hC}W#C=_YOvg61zq3G zy&9zBG3#u8Xd$s4G^FtfRFr^N47@BLw{jPND%)qQ2l*Ko1h0WqfXZ?qP{sxm4BRcC z66zi6BanhWPzCi2LZE_O2-Ln60!J+OQ;@Q+tQ-Oi41&S}3=B|V2Nebe4h}YudED`! zYD5^q2Aw<3ApvIdv2kd!^$RdS%L6SoPa1ZyJX)+f$Ia5*%)9 zxq=J~{4tss4i<<>o@_5cBjzFu+?=4=*NY8wAqAfZhcDZ9xTE~Q z8W;ppGRqh^{K4)JfLI*>wps{cR3Mlm%)kxWroa)zRw>B9z$d{G%El-Jb4M7&9T1bk z!6vcr*Mq|?0<4=2;>1X>jqD8Epd}?7QEZ1nMu~I8u-OSQFbHH8WixQZf|W4v{|2Rl zIJP@X3=9JNT%bG=&jzXx1R1zzf=ZkOHeMkH1~D0qB(@2l;VEBG;gAdta`7pkDkG&H z98luypnysR+aP`kREnj6gFyTjC~u{MJ;A`O!NS16k-_FA#K6GE!I8xVI^&Rk2FS>4 za5`b&Zv#bc4p@SPftLkjCwBqJjk#=dKn~&H$Y+xfW?&Ep=j#Htet~)h21o`j1c#0| zXbOy@44l5iB|yb`IUDG1c&Y5vN(PQfwqu}KOK#9nKO9wTmxLG?xZ6P2xz@88fX=rC zhTKD2_Q`4g>!(P}Mz`EeJFsz%L4F z-OOVHovXmX588{xF`q3CblDg`11KgIu%(EA;++Rn?kr@>5@BEv;lBxT-4ZrX(@uha z1IQW6*g%I^%P{b=fO-SGEPkLnepo-WBESlnqiSgYM|9$+$%w4 z%1N+3J}!={Y~rE}3<9}{6$~8Lz&W6vK_E9XkAdSln8(Dg1xj!?z#JBS3s9@#CYZy< z{}YrfZ-Fi4VBq!vrH$KcXG9nnxHUjY-~pSyCBzGfq`E_ih+T%5z-Tai<3TO8`okb~&0r}$eoxQs zSz!yhXb;*qjRKtmDhX~5bAvXmb9yp|ih*tvWMp8-6k}k3cnIVx1~wh8j74G$4D2`f z7#O%RLB=t#-&KugVBpFEDPUn|Q($1=$_A<7UrPuYcPOq-2}5$j)BD(bjfor z$b7aNT=iTM3=HfFoD2+H4G=>?iGr&U#Aafbn!fdrmbL8;UNv3!u$Fl4AteR|u6|G~$+0_t z*b_jNggiTF!k23zFAD>M0{a(!1_rLlAZ-rpKjj!0xTb&{=g9s_fPsN)I!L^ponMoI zfolec-N619bRFhQkk?w+p9(WDaLo!4WnkFAK56>K!&>6??<5!)xaNVBUS$XMEV<@` z7W!O+1c(&q!ah(m*fOwy&Y$60uopB=#{|-|#6W_9LC^s-t^=-~K?DPfJUase*D`OA z6sSEW1nSsOFmRm#1rZDA%5<*FV5UDW0|VDBFf)sdfr0BMNGBf;7YpNL(9PICLD9hq zW;5_VlVo7vVq*j)H5Pu*@ikoR;PlVIZ>Pb)z{LUPa5C_+fIQEw1&Sq3#!yKHH3mLT zE^bE9{XP7k5kf8=Mo@xa;J*fP5-*s;$p35lf}>iB^-Cog7`UTB){2A8lfJ{qCC3;q z&A`A9I>mxZ9xTeh4_X_-rNRh`TNeHrPzq89tGdH4tj55=rNNjg&A{-0A9RKUmnI`9 ze4ohpN-;2S=`ez_B@3er=ukl}UC3A~qs%!_Q0Xz&gIW+gj546(qq+1Mv!xjr1Q=zk zv=|t;jKDUFFv@@qYvVFz1l{#5$|y4ll)_CJL1UT{j545ukGRYj?Llj58D$JX7Fsfb z`nDR3GRHuv#2W0~6h@geQ0BG+^HLdQ9)V1;XMC?E$-t1tC<8j!h06hKVLGGCeHI1= zE=NYt`4$3Yyf8a0eE9w6ttGZsoSFw`>2IB7F5aCtF$Nis0p zV3cVBB|L9N(DC`V7#Vn3R)cQAWAOmpp2y+|y89OtGoaghc|e(jlYtv_#}}6m<8Mg@ z2A0cW3=G`5GeCFyg4S2BkY->2D|29wbz$W8^Sds?z`*_&R7CrOk`4nq=(tJl01%sr z9WBxE&IBge8CXt(E|sqY1&M40BX>)T90LP8k17KLcPog= zz#gpyYP=-LF)*;OD}%1$?Eoc80rpQIeO;h5DZ&ow3vzdZ#A8j^=YTZyf+Q^1L7ge? zK9EEN`%TadyAwd-G3>dr3=G^8LE<&+mq54nP6mlLu+QgXVBnqt5?{c68pNIk5?{iu zufo8Ko}hAObom%piy%cPz#m&@DI=>mOR{7mVkoZiiLrJ`zj~{Gq8ht!`wGPsf~q! zWs5Qc1NW_FIR-Wcwi50;U#54R(vtBuueheBT=3oaEOWaRD_7<>faWF7&KL@c3 z8CWKRLh|K$P!!Gv#o$L!@{kqb=l*;Vber&PP@?{lI{o7*Em=EIZOZ)zlx)@5qe0>F z7sS?J2VKa){SU;}Vh8Q#+sitVupbc#L?qlJKg8BmO}l1IR*w3{xfO}4BV`Y zAm^L%r*JYbaC3nR3TysUQ1a#h7j8EEpyfi`yx?NbfgjZT<>mv+xbTB^&2jUCWjy#T zLD4M$mhs{D2RTd-TjcM$nKrJHL#+Gy?;-3|JQzzszJd z1_o|fFpq~{<}AqXa$ryK@yqO$XJFt4mF)El4E+2u${?;Hxbzd?mjTu7+*)9sAivBr zP#V<+^Mv?iKzG`3>wt|B=4aq#0i^@ZFLDeF&q4R8f{HVF25wc5{|y+qK&BRgTbvtfa4%*oRAgY__XnlhC7>_?bttcZoV^spV_@M|o&M{LmT~Q{5G z2XoXRMMER#!d8%Nq72-iD+0MUGJ?iv_%gV+GWsfkdn4Hl+}ju-ecx3e3$}wf0{mO$ z7#O&BfH?~M_d%RpV2%NQG{{xE!5jexaEF~>r~f^xC0WlQ%D}*V4D7EI2JX3_BIP(^uOb5jUjz3^#-~aQ z4E+6|Bz_8sHP`!1ur00Vtk)SH# zI>@-!U_H_njNBg?->5J!@E-wXh)-ZP1OHr5%zS421e)#S4*->)Ul>6xD-Qmjpsey0 z>|Y-K0MU8|2JUZ+KU6^7DR6!D9h??r!1G?*KfoM0@E9WZPq3R6!1G?*zZgN~o*I7? zDCPWSyv@kKpvezv8gl;uJIs>b6_lm;!1F6s{LLUI2!Q92Z1{^o@hQjzs=R8aPd=|D z&A4;=`tw?nj8W51p4U=i+%)~ec`eC$(AXxoITNTrT)+<+0_C<~0u_i0`S*Z|G)wS& z)gpe-Mr3X)FlRBp9LOGfu%%1*`E?i=xE;VVAj`lrYTS%g7){ibVP)KaV$0Xg{)C>|iQ zaePMHGnha(QSdJY6+<(@YzF=>po}w%3Dgah<6jRlXEr#TH2D2N>3c4iqs0%pa+iA^ zn4`lV1TtVgn4`xJE^!tzRj4vB81NqfmBoudPON7zWZ(pu%BBWw1TisitAdKq#Y~`a zKRyobWlUyj3=I5Dpvk`FU^WB4Ix7PM_X@DLKm#Vqpa7Hv6-g_Zgw$a3QrxSV8q^pV zM2ta;lSQV3PBjz(U0%v0asWIpB_qke5X>UN$H&0HDl$hEbgCZrH&D*o0ydbt4b)0H z0%l9AsBnK~x~<8;AdsAv&cOWz9PkYMdqAQ06D$!X^9s}i`Ngzo`s_@;R%aOGbr7$fjhN- zSY*mTMG8BZ_m@THEyxre<_gf_X;vA~E*5SfW>71$f=wm|R5FNwC#*s^WbS|(3EZO0 z`xzM+!Z>6=qk-IFV97WR8PEtIw>a3)1P+-eAS)!8LEZKw4jB(nDJKI~S;Qgp86+nQ z=9O^B7=Y55GBc=*ISxvpX3U^Q#SL+p3Xn!~Fz=4I3}}x#w*{E@KwL%?l+Y}} z4t*jnvvoS(6)kB-jp``N2_#-aEqCUO%ik4J;1}JvDz;0rZkWmKN`2Qh#a< z#hjp`JApY^i-AE#g@F^)4hN-8czf_K=#Ds0o&=>zs3@n68Uq6;f?<3`Ed~Y<2J=A$ z*K+U}8K}JC1eIZ+Fapc5GjM_gLE!@B^QNn zPhwzrsx>`OUO;sEf@@j|hFr-E3@YFYb5t0k!B@vAXo3z*0@b1n46i`jH0EsAVPH`E z2s(qZo_YK9kJq#`IG%tG3~ORmpRRaaOUx2<5z|>6*oBoEd?3kL%$Go0y@Np$f()X` z3=B%3_1j>FfVN?P9I{s%;*i$sTEfbT$qWn^wV{q-V^9LE^ara3bsRvdC3GOFFI?AB zX4OpwEhGGKT}wmLESZ5JUI(g?0pyEP1_q^LptF=gz6RY21k%0?sy*(8mU4g-)Yqk; z>)2U95e*J>kRQNtAJcR{l@FctcCg z%1(-bfiVsgTA*cYpmp_(a}I;?LozoLSHu^yx+m63r#3AD}*Y&K{y7sTvjkUkaoUCs;& zZ$ZbEZ3HJV$nAxO`V0(;;3T#Yn#9z_KuK&fIEl?+WMD7^r;aVmAY0)`qX&cP3JzyNi*5!Qdt+ zex`wfFpnz?8XBUB!=y#gdJW&rXLR6BFg7O1=u$Y&s%Ro8;T z0+gu4rVHND5)o+Kj+B=c@q&gW8_yc6YSYq(J>^rilUYxP@o*Gt&>g z*A<&S<&KsxIBh+hzUGdWf@=>be{TaD23o_&IA@t51A|!s1LF=xQ2bqCVqh=>rJ9}K zrs{Lh#x{5v0#5Bo3=Hwp1@CHU@_`(y4BA!?3Z-cvF|p}!ceRAobHVWw&1lTPU@iyR zyDtD)Py;$Y7#u&AMhpyUtEKtr1}~05?=RSQr@8W`J(>G++V^C#+v&|0%J5}P13=DxLqA>j+^NSf6R9}FuWS*}3Kuf~shXw-! z<9g7_Fotx{U88d*m@zP@fyE{cvjp84zZuMr0!4+=4n_usFG&pC49c&dG4~PTs!b2Iq?AD> zvYJ6$Rm{Mk1nQK5y`ahjiDnx!NaA66q$Mo7Kbe8SAFMi>(V0OBwC5D0SQWId6jGQ^ z_j;sd6su~%z@TOeI^&xOya;SM8v}zPIL$IKtAkF<4hCg+7I1O>ij9FmT^Do^5-V6O z2Rj3U5@@I6DNst4g(W-CHZ)L>s+mLF^WldspNJA@pD4%$%Am>)Bpqu$-H}^QY`WTG zEg^oe47eyuVqlm8)fn?wOBf>a7Ml1^LuDqzWwf9n#bg1={-+;n3DtwLg|r1EsNmVc ziIIWfS~6(k=O)mV75d;>%NewgWzJ(u1_m{-r}e?LmNYxeqlRFQT7oBuC zme};WPqZW<5}>QTKoSuU38|+r2@a@#r-CH(A&L#4VwXT-V$-KQ)sl321TIw}w;LLR z76CJcgFOtYHyG!%TQM-06fiJ`gS`hjWkVfYEk}amc>~D%(bL~Q)iQ#309MAg0j_nuunl(LMwtBbMILo ztvTxg2F8zIpE5=vDgsaw2Ndr!Ayy{7&=S@JITBu(LF~)|EOl=W3UGJIKB)<&7MN?&UUr-P#LxII!j z21TVZ=&}P)z3>1c!)OGm9g7$kY#TvmRF*J&hKMswbYM^hZ5(}X!@$7i05%0w*Mo+& zz-jd)G>l!QJHF8po6h=1OG*h;V?;pIf^Iog0v%ETR{R&LxF4h#+BDOJ2GlW-nAr5b zH?Z&qZBYP)?O%w*(KoQ5odMNh;t28OAGpjxs7y9g#`rBv59n|OkYS4)A&DgWEi93M z(ke*irsMR5?{vkcFM6vb6bNe5gOWbD#s%j&W-d^J#e6lWqooMX0HA_~aZZR61A|#n zYB2+&GI+^j9&)6pf+Gb|Qb@nk5(xVRO5( z)|eHPBp8E13Br^WREi+yTd?6t3=HR|H@?%-WK@{G`kj`tSfMimgBrNU7hVmN2;a0rE7c!(to)D$kNwLAiW4xUSmf3Tn=SE>cMX zd-4w`(SoLy7?Z#*mgQk!Py@GUA@ZR6!!*E+&J?gbV;HDHPXqfPi-&>1a3ZJ#PiF<0 z3r^8)j2Wz;B)xpgJCuj>TQTDUb=&OpFGlL(qkS;H2dWO~Aaz<0BLQO5?|;-1V0<_I!$&O<9cMQN29x6CJO;*lU`>BO zZ4UEvP*e6Nc)cnp8Gx<;V4SmXy1^$c2}m^yPJED*o$*Oaz!Nm6&1eW-zXZ~730wze zxHB-Q<${KU4B2*qMm2dMJsV>-P+A5Zh@k!yq|gMcZznGUgL=>OgP*j7H9!$ALop3 z&PfA1N1cy>K@Bu}&IsXq@G&qbhAA^JFs8GCn+73@??KLk@Fx-j^ z53nIjATNQEqY^AAAXY%)A^D4zYJ8q2%#Sm`MuH9%Py>&+%>b`Vd&>ujf>~fIK%1Z8 zjgr6UmS8kWOgyJge5NHf{qGkoAxJU+ok;*rhho$9ziMf-eFj@UJ>jdChyf^$llYMW zYQHBDzS#9uOCYuqRMZ{>djOQ0AmwD47tCuAnLd6a0@`^KrzlaH~s!MEh+PJ-V6*e0t^g_V7tDsf%^W8A)rL|4eX;1 z(Dm5xp$*WX9iZZ&Zh9b>p4fD^?^?p(KF4%#RL?4dX2aQ17#P-rC88NEL8Cjy49cMM zs{~UR7>RCbM$3UFUl>3=BgQ$~ePEqnId;%6-A0gu z!JT9|_USjiYw>}-!5E?e_JjgE*b|`|<)DMX71=?Xu$U$~z>_OH=Vtjpa<0)2Enx|e z1C%Dgx^kc~NRUTY`Ald0qa`-I_=lE($zfku9qGyrDoHL0z{X5m!B&Fqp96)QJ3A=V zfp*HPFPwh;hn69v&VvPBiZ8@kou695^%^M*3@yG$p~o~aK!q`eX<{IQGUyx)P#H7> zF3+Ic%D}(?3fK)`F?hf#fld}NNnv160)-gJFAV0OJ#36M?67nNI%ke?PMaUh4>ce^ zm@`Zlgn6O{?1_tlki1z3_QYR7q|#d%R>wK{L43gV3mX5?en>uGG-OZ)9Ty35W-(X- z;Y`r-ZwHVwyFfR@fa2Wz6{tC~0`5#udya9=G=G>gSAd+!U?>D@p{`&DHAm)x_~6(U zTmg3WJ|T#+SFvxOzV?@v3?#^5!%M3E5C^}7IoRGG$-&^d8Ptjgxi}mw19!19=mb#G)v7#JXZ)5qYLFaYttg3c&?0+t7@ zNKgVbOThIuZ0Nyn+8-@Vb&%D{Qy3T+zzz?9cy(ehC=Z%3C?A4KbWRWWqa^|fsE^Rr z%kcn6Kz01lQWly5YHW#ffC@jb!{)r4zW0xoWF*+_!4S7gae%fd!rd;-0do5vkXyn1 zY8ehtR^S(9U{D9UT^1~FCCb2{1Uj|`>~>gNuqF^894q+F(`qK z)&vJFq#47^z_4q&qL7~0^rrt>!Zx4|)H%2|2Gt7CnP!jy0LXYgqca18c@-#qEaU){ z$e=U=x=Dp`j??su|6%PjaJYcm1yeb-1(HDvA{n=V(-UOUOg)r=!M=cjaT_>98H3co zgO}UDUXT}OU{D0@cV*lTwt+E3{W)mTWhVz{z+t91a<>y~PZ9&e$q;bhPMxSN>;Y8`uK4?r9bYKyvN&N*Z1RkaZ9SsB;;uHu4t70l*Q(=r|DFzL3s=i=gU$LoLLe&`jMsoxEy#k#C>fH#<&I>;^d2T{MI~?$ z%X5NK3203T!aQ&*Dv5zXc6y_jo{F4u9q6w56b1&va8SrZgKBDJP^k^7k-Vl0GHZ)K zh9w?Ai;fPEKC$VZ%-T|Jpw{m~us+ZrFtprZWn^GzOJQKx3YLHvD8R_T01AqeU@?$l z24z*y@OUxj2lnYCqf@>3WXm?J=Lhyrzl!TMAa7#SEq5-N-cK?d`W(?2q6iog@PTWC+8D6FP)}XbgZS5R(`fIwQboXL=xuwn670jG3IE;;TiH zfkCkb)Jn_b1UJcp8O&#bYAt>?Q04=rebD)vjB}PoLW&oDaMNkCBm;vQxNE@=?pnMB zIl~4tX(9;bgNEZ_bB)TdB*fujPP96;yIgC;C2VPb3ymY{;p6Uv|Hz@Q2m0|SlS zfMbe*!7)*qfr0T9D9ozCgLG@BJF;mT)Psw*)1b=Zl@tSmK@e#2=rpKg;g)7#FaQ^X zr$ObQjx+;<6F3c@1tno$X$A(+T<$qgJXL@=pjo-|AdN?)85lG{v+jFiVYBWIpd}Tc z$-x8B3=HbvDR>D+&=fo?uMDUnhbBDB>3`X@#Wg^a=E2br-jX<*xm!Z91_*BKL z>55W%V$ zUr=$f6(YtuF@Q}ORI~p!FW0hy*V^;AhZU8_U4p z3>sEqd;}ie2TlAk&gqGVWWYz@;eF6;gpelG6Y%iNvV-&gOrTDLu`j5mmI9XrdEnY$aUvw3q`-sp7P7Fm zrVO}bI1S<_f^N`}WdUWSd#oUVi_=$dYs*T4mo>ED~WxgT`G-7#Ng5;RCiH3>u`RAT9cGpfH;RRSh1< zV=Z9>HHuV0qv=bh=kaRGvh7F$bvdU`c2x`AA_9IhA=&8nc$ zZ)o`eGJ(M*M2CTaQ3i(C>3{jOWg>P7F))BIZzq!* zXsG}Q^ND#(7iC}oVYl-l3=AO5bHyEW!x{+lPGWNFm1AH4Vg6uuF3=`1(4O>}eD0;< z3=AO5(J;M`Ut6_aP=+18xQe5ax+ta^J1RzyQKLdzsvSGBPlLFpn{ln~Vkn0|>L_x;tqy zFo3WC1EZS`D+2=vv-!G#j(`PWwmdh`04xaeEO%$-XJ7zfuFZ_@r??mxK$v?cvzw0+ z0|N;2us?LWF3P}gefw+yZI>{f#FVo5l*E$6_?*vZaXuy! z9HW`tw=(Lkk}Wd&kWE}uK$lD#KXzJ0Q0pJ z65AMwZHdITM`D9c|AFcCMiLJ~V#gt|iy`dk)`2>vl3O4gQ0s@`AQJoh^v*yXWzT;| zLfoLSJ!rsy&O(RTsfQ$Pjl}jqVuwxt8mOaO4?1-mrfm|E^a3O{=-_ae8qi_kFgECb za2OkOCOC`@ItLua{)A-CKP0v^Xd#e4^qyva2nX!tN+k9QBsS=XY?z^+k;MNau|cO_ z!_&^OKO0IccHpLnHZ+j zdHUO69dXH2Bx%rz%P{GN>9Qd@%8cu$JBH|pdxDNNhRIw*((xLJ{R4^323mmuwNx63 zZ9jcsh>o~qB9c%Z61!&l#Sk6kdeG23%(fj!(x4N3VdA%u#9tt>zag=?`4Q<~9Eq)r z#MVb*TSM5OWdRHf?hp<*LW7am@ks1!BzF1q-u@b8+igff*OAzNk=P=jSsG~QC?K(Q zrgMhrSWA{72{j?HCrpnG(@~b(k0f*kiG6GO%rG70dNI(1BGhnYB(@_N*Hq0S3I zVuOxMg{jFw5(gcf3KMTZ5}$~~UWUZpjKn?;VS@%^85lt4sKN|-0g(X5E$BQ|m^cHd z{RnlOBobQ{iQRz2o{Gd?i^SfE#C{??JugDXE!PM%QUNvF9*JFx#O_35FG6CkKw_^$ zVsAlW??Pf9oURzDBOVIwY(lN%0?m0t*%C->6(qJ75<3)$oq)v7p57a&(_9a_s~#3= ze4xcDP@_RRvtZ(ONa9{d>>?y~9TK|>i9HR8y%~vp48n#)=_LpU9F6yo*sqY-pbaZ9 z2Qh)xtwSBkhs2gbV%s6Hy^z>pNbDqW&>fUegYu9hs*u>A14LmKPeKx(hs0im#NLL) zK7_ z4PAgFu?C5K2#I|gi4EH31oi;~1H&&QaW+XrQ4P953Z_OLNgT9K9V#xxV2UK+fW-Em zzBEQhS+WvIs11odYx=_&9c9&%NJ7_;*iVqyAEs-@>R8uXfmVt`ed~_I4n<-oBe4sS z*!4*4UL^KxBsSPT!;B(^gWI}nN8Bpr;1mp&wkO-Ss0NbFNc>}yEuM@Z~<)3?Uy?62PoT2}{k*C{0S zJ0vy}XfzV4h7XA?g~SH!|AG0{2ua)yiS32N4uh~E0hELSoND zVy{ACZ$n}qLSlo?=!7}+mhAMR1f95gC(zmts0aO#*p*1^9whb*B=%Ay_6{WW5hV5n zB=#L7_6rCb5(r-*9B?2ofF>WH4iZ6PDUMw zy@diIk+~wVgOS*YNbGzhb}bUS8;K3R^d9PuD zBhDx`T{c-qe7Zxjj)Y`5Xw@auJkXg*u!wA$UYM+7&3I$_LXgrU$vOs-#-Iz^p-LT) z*nZP_Q*^RbPa_H4Kw>{bVt<-GH$~?+6OYRDzEmBt=^IjY5^QIKrum`9u0UcRLSkP) zV&6kzb58e7)3H_!0^N@dH6k8~or}b-oW3?qC%FC&lF&;eHalpz3~Gc75*vJ#HdNde zNjwaR9fQP9LSknivGX8oNWv_EaKLd=g~V<|V)r7kHz2Y1BC$^+v2P-=pChrqBC(ml zmrO%_BM90}0%gl1v2~Hy)<|qmBz8CwI~9ptjKpq4V)w(?Apg&WaTpjFz}I9$9kCNh z{3;UrF%tVD68k?An^yyo)ufTw;9IYu=9_CERq(Dzih_~YiAd~xBz7$lyBmo;6N$YX ziMVz(o)ry{WzBe6FkvG*gf&myr?Kr{DHM;9Qm%j-cL(1lYB3=Gwv z3z?y8@a@k~4WJvJVZK>}q<%FL`yhx7UR}z-a0-ci8HxQ2#Dsyzz9{8h$N8>VuMz?GcYg|fY?yY;G3YKjsxEW4P{RNse!VWf!NTH0AB<8s0<7Y`nn7Z!caE&R%B>Ac!JbG)yIL@P;u}*$WV46NSp_ByA%Th z1Nf$6s6jI!5@3g}2C<lzkT@4ps9U#D+TJ zi!P{l2IVm6F~Cz2JBSU{EP%vT0AT^-EBObOF(R zzN!Z*yrB}WK@w1dz96yxBC$F385lqpjDdWhh{QGmv7rvN0kJ{*X+ReX=rb^Y&cOt! z_XdeW)r5lB5Kq=KM1eR^i4+hUBEgUeVnf9nL2Rg@T}bQ&AU4#|E0Nfnkk~swY^dJr zNbK)mHYofV7#PG27#J9#iWHF8Mj$rS0&66;3lcjJ#D+RF0>l;s`Imtq#(;rA7|Kou zi9^*Cf!I(_Hq|3>+CglnqG=#DRP%f!_Er!Z>Y#l{?Bhu6vmiE9?=vL!HxL_Y{$CJV z2wHeE8Zs~lLz=b>qJ|9cT%dx))&#MkYK)NB9w0W)w~?UhWcO=hz+_int_2~8^{At_Cb(1RLvO>8yeIXL2Rh_3lJMD z?!v(E7Q}&S{)WWnF=Aj~ggQtRi7ki3Rspevr|T8zh}VliqTSO7bo~Z|9RiYu+8GaG zgY9HsNCB~-;`typRJ;VlhKkpN*ii9aB=#f_8>(h5hz(U!zX-&EN~{I3p%R-wY^eA_ zB=!X)_8kx#>Vc<7?B5_ZGz?gb5#hm$#1;mzMW7|Q41@#rzA6&i8pMVg4v zB$gntw;-|iBC#)n*w7fdgT#J{#Qp?gL(OM1V_;x}vO&jYg4rPdtAZq;2I(QO&5_u) zAU0HU01`VAiJc8%L(M5cV%H+ECxY0}ke*`(susn-Ntj`Q83Thbl)V~B(KZkp8Xdbq zY^df-AU0I|I*1Jwe*|Jf#h-)NP%}Ruv40}i^$h&xh`5wMVk;uC)j@2iK?X={HxL`@ zV}B%e1QI(A#D?lkM`G84*sP%N2Q794b08tnkHnq|Vna30Lt<|Mv7r|4MPeUAVxIxA zp?a?(v0sDOP`zL3kvM;m*vu9T450Z0kdtJP*lHj)G^lk!Y|v>O3=9m077Pr+P__+7 z9ID10#D+$P4~PvF4+pWmq19pxhy&G}ip0)CVz+?UP*?XNv8N%i7lGJNb53^v7vD+0b)bNl|gK%xCV#~6*mU4q2h8*NE~+%8){hq zm_7ZUf|*=>1&9sxO&y30Rnq}tLk;Z*u|fA9GcYhrwqjrqhO*~@#Gz`|fY?y+tw`+S zAU4$e3rOsn5cc%*RXSpzX#-GZcn>mL3dCYy_yv-On$2pB2pldD8!D~{VnaQv24X|? z+9R<&kl0ZmHqU|?WqvSwfqhO&D>;!rg+Ky0WZ=7QKz z@hu=WRD36h4b^)IiG3Twh7?pEK^&;-ej%}$Z4eoQ6U2rZBoAUkEz<(ALDy+BFfi!Z zFfa&1*_I%2s2Ud#8|olW5F09R#%hz)g6Hxhda5_=Yi4OPDp#D*HW z2gC-gwFKQA4RR2aeHtVVRdWr*1~~}i|JxuAX!AG&1H(%Y8zjNN!0-XYhHCf@VuMaP zVPIhR4KftUX0t^M@(F_2P`#=kHdL~atrs<#1&-HF8R2eIX# z&FUEt4mf|W1F@l+wpVphG`%+)CcpC*ej6O>p*OfW(Ed^6G-fbNbE02Y<33*21clQ0VKAX11Nz*Ez<`{ zK-m^ZY*!E)syPygorJ`$0I{KZ8XVw-~4P|bEo><|zeYH=(Q zI}M4Q17btM1?25$pLt=-5*ig$7Ky1*S zGX@5R6p&?5c0NcPs;0^b)DnbRT#qC%6U2sUScJsh0b)ZPaS(}p3WVr(VnZDl zgv5?UVkd&wP`yPUc0JUBN)QLM^PPc#q1Ks!K^V&J0Et7@Oa`%`j+g;rL&X<^*ii8m zAU0HdGl&fp-vMGn#m|G-Q1SXJAP!XG0TTN)hz(WrAH;?_NWz7Iff349L}HtR*ihd) zAhA7>*#00kRBtAP4cbD;z|aKYfb-upB=$-q_F*LUWhC|;FnfB{hiWZ330H*UbdcDl zVD|KXTlAIdp>9kD3xRE9C_`e`Be5rf*iiMekl2fn*n2^2X!xA~u|ZcUGcYimab;i- zhO!@k#GzqX{}jZ5O1wj2Gq`~&Wr%|~k=Q~=Y)KFsYMBa%tp-uA;l{uKx_AS`vjd4k zEpq{}q3ZoXY;^`}kQ#uC-UCttwd^>E4K?#B68jd24OR0L#D=PQ1!6*ig;ENbF1y8)|V0hz;7v!oa{#;m*Jy3}rWi#Gz{XKx}Vl zvt=@f1C^KuVnbcM7{rE(Z$x6B0I{KJ&Vtxb3!Wjd-y^XZJrGHP3yCf40cy5DeJll% zfLf*sVuQ{|VPIg;^k85RhO$jS;!rjAAU4zy0U$P1O(qh%2#MVSVnglfg|R`+mT52! z0|Ucc5F2X23J_ZxlD5`>906r-2Z=+~90IYSjyMitL&YzF*ii8YNbIK|Hq@Md9-w9m zl*8`Hz`zJ)%YxWYm#QJL^^w@7AU0IJ9TGbL#D?mPL}Di)vGYM}h(o8}@6=%f&0T`L zS?9^XAPhQ}iGhKk6QPD-3WyE$%pxTAau6G;{s0pDBog~Jhz)hm6D0OqB=+=_E*-&o z&^}TI1_ov?1_og$o6if;l9dFpp^nf3v7u_5k=Q;+>^Kk`YH>Oey8ww@4q`(Bf+4L5 z!~tyw0}ZHw906rd1c^fx%>l8Yj#vm{L&evC*ii9}AU0HdKZp%A=LDENeU(C-T>Tpm z8|t{vAU0I}KM-3V6c-E(Ox_F(!cexjH=;V10kNU#)j@2iy*eN^RNNWFhKhTD*idr< zA#6~pXJAMNaiESUKw?)SvFkx>sOA|+>&VC#D?mXM`G)N*iehj5$tFNUl0fCvoIufJQ6z< z#D;2aMPkoHVsAuZ?*g-@`}OIFgC@m5sra%l1B0*;h{eEg4h^aaHdOp4 zhz%8I_d}$49uOO9jwlja8^nfs!vu+4Z;Qln2C<=ty z)TQ-fU;s^`fxNR2Bo0-x2E>LsdLxMK53N@BfH+WzgCI6k!x<18Dt-%z{R)Zw9>j)P z`~!*2=Z~mL#gW(wNNhEKPzHl)b^u90*%3(WLL_z-61x|PJsre`I(i<64LWjzfq`L> zKLdj>l)Vik4)x4#5F4Z(l);XHI8cexAT~&Xfq~&B68i-b`!k3QRsRFThN@={K%@f> z5F08k3}QpoOMuu=2Pp=CG8mL&4w8T-5C31UOlvj-w_zZeo* z5yXb7R|B#AL8oberd2>3sDv4a4K>IS#DM_2nQo)MvFIHdIX; z61yLXy%fZTs$Yl1-j2jR0%AkWxr@Yp1!6wDpzJCT8|uquBz6xH zdlHBZRX-bvy#$H93&e(+a~O$z2F3>Epqn5L)SypD?EfG()YV*|)%>7id>I%R_<|W2 zgrRInkT_J03WyE$nI?!06*mE~q2iVxHdNd_7?gvcoFI?{R8csH4HZuUv7zGWAU4$E z79@5r5_>U-4fXLFB=%M$_HGaxVop87c?5^yDTocV_ydRyI(`Cl;u*-tQ1*Y2I8+T+ z2qLZUgV<0t5=d+<5F6?sVm<|g7l>^M$*z7O3=G0hb}C35s-^(M zhK5Qhhz%8QMq>AY*ibc-L2RfwbCB4Z>OmZ+>vkitk07y6f!I*Zmyy_ykl0_5*n**; zbL}A>&;YTaj?)LRtsvsYp$rV589A{3?LZPxMV=rw)YX09Rd=E+8YUCL&cMj*cBi)E3`~%gmA#F=t5#o0I{K( zXCko|gV<0c0 z>0OL9a`kc`HdKuf65AVz9fHKp09}Hqc)x;pNi$H9s2dX1L zB{-DRf+W!eVna300-1H`rm`;p-e zNH2&D^8W{r1XS}^5F4tQAretOv4Yr8aS;$3q#1O^AQIac#D;pt28r#8#P$ZUp?Xsz zK_xhplZPbH0%AiA>P2EtLt@VXv7vgGf!I*Ttp%|iAimrf$-p2CW$yurL)9Dyu^}F= zXE+1mKqYR2*ia2mkl4RKY^Z~nqdQzHxTOqN%kl0ZmHmD5@GAaSY z0iA#f8o!TXU=W6~D?#EAmol^?v8N%iXM@;K4=e?-q3TzG*ii8;AU0HdCx{IdKU@#u zKqXFq*ieZ}AU0I|J`(#a68jT~4ORaK#D)wnGcZOoFfc+rz#0wl4CrJiK9D$6y(Eb3 z&AOM`ABQVjl*v zq0xH^#C8S;BEz{@1_og$`w>VSnyj9K*iiMKVnIa#RN_051XCQM3}Oedp&EohY^Zv1 z5F0A41Y$$Q)j@2i#oBQYM{HzZV6X>?L)Ex~*bp`K41Nd>Lkfru4X#`yb{P`82E>MF zW@trX&jzufdY2%v*CMfZg4j^KXTfYx_%kptTmy3;LH7p4h8px0iTw|W%@xnU06H!b zq(c~qErY~1058>;3%hz)fF za{|OcpwqL&6A)=g7Q}|CQA1+eB!DJIp+V#dl7O=Pkk}z0HdJ#461xzI-40?y^-e%y z&qQJ`1+k&#tb?=b85oX$I8e=Jk=WOe*pEPLsOHy5Y{o=Hy~KsY7Di&rgV<2LmPl+T z5W5~K5dq>r9g&E{&O&0Bf!I*>labg3{M;bFQFsx5xU=W6~cY(yAYL0@~ z(CDi_1>!&@u7cQ5iCZ8xRQxH34HbU{VnfBhg4j^;Um!NrGUg-(21Y1b62yjjObLmt z4Pis_pB;z;)ewZljz(e^g4j@ls*u>tNbG(P8*0u9B=$}a8|vtbNbHwMNXI99MUwbA zJ#n#)cs)xpVpxS6iOrA17DHl7A+eQ^*lI{@JtVdf65AY!Z4F^V0>>G`0Tne2?nrEZ zBz7wK^n;RwQ;O5_=*NdnyupE)sho5_=^Q zdo2=s3ycl&{|*=jw3ZHueFTYp8i{=#iG3Z3eH)4W7>WHHiTxgl{W%#_IYNE^8%g3n z5}Q2*DSaTZg^<`{NNhPIwh|Is6N#;hVAnI4A~+0|NNh(Wwks0b7l|E+#EwK_$0D&) zk=U6?>;f=b9-QVFO28Zly9SBfFn!`O9dXZYB%w)2>}g2sxk&7VNbHqJ?6uQBF4GY= z+=(P~0EvABiG3Q0eSZ7jWjdFqFosOOXszqdIA^+|jjlgq#`HoEwPgB15cOlapslVy zqr>z>5OrkwMiAvOozV`gA<$0OpI4-ckpXlW2k1aw;pv64%JS3C*y*Y;#!UYRQspz< z(O%b|F=YBg5alxcA&BysZs?%v&$wWEBZ#^){i1`eKd(wXBLnFCOprm!(-qAMg{M0> z>KZUsOfPiQ^=CXV{UC@sGhNV0*PmCWk&yv(^A1R{_Vj~F>eAB_GGtk%_c-aQFm9Q? z(Mi{z@xydRXI+0ri|K(Ns$u#<5H)4`M-X*kx}%G(KjWS06J2!unIu}LKXTFaW2~5N z=nA%~(N))H0IVv`;_ert8P(FkR4H*Pn66^h9@E ze_n$QMurv!1_qFOe5Y?b#Vu+Mjbs4LSs{dN5reWpkHgTi6@^i}@4evDhD{{)F%neG_?5}h@D zR)DS_d`1W_r|PX>Wpw{p5vu&y8D zoavdty8cWGtETS)aj#703;_p1B#7#mzA^+9*c+z*3eojrjG68ks_V~qVfxHakO^C- zzY5j$V>~e3G7RD|5Y;pNW|*!&lgzH^TH(5Wj6TyV!*%@`k4!%aqFkm+M(Fx8zL}m0 zq6(((1W^goIU~X06A7X+rmu|D^=A?|F#T7gt{;=Z!RcO6x_*on(`QD3{qPb*t(a~Z z4N`P$dRH{q^Eacxj@FFP^=G^>y%I#7n0^vO`AnCL1q)_^s2|gJf~XzSIpe_b6$zqh zrmu_xMakvqzv6WLm_)8j_lno`V`8~FeHMsTxjFq+ysjT($8^gCU4KTC>75C>^BF^? zYbNSyGhUw_ny9PH`r{2F!;ASVA-1_qJoA59pAr|(GA6<}4~$-tm7J<-)kc>04x zT>-{9(?2HasPrm>Xu9*H1By9PQfnmaQ-eg^6#*@(Q$$lx*k;jA#>=?l`i1sHv%d#32B zGx|&~OwrY1GcqtTG&P=nut!mn(Q^9wXe~`93$E?YQgoxD>ZcVkFn~|1Wnf`U2Hj%6 zgqwlklL`X^bcz^Uz%pg(GB7X+f`phE*?1)w7?{>EGB7X+Ie`{HFmi-)GcYhSu^!c9 zU|{;o$-uxQ77dbMVh0_w&*ZMmz`!I4x~GDLg*7v;gn=m#Bq9Z>NR^mb*dOUKFfenl zzS06w?C;bV7?@JU7#NsA_uexw{h$7Dzpet$Q5gmXW?j$`yG-iSc@O9+7|ao5U|>-L z9fHl2$;ZIJqOlcpo!KiD1_l;QUPcB6W=5uCAc}?km^cFi>%!@=2Xu8A%cgf9(3NHi z(3oD}1PF2cybAkV4PK#1FKp)69WU&P9+8gHuV}N1_r@{ zEDQ_^Y`X5u3=BeYA`A>{dLSl)kiP%}1DigG%_3CA$iTp6;LFUwz#(KR!@$61_?>}) zfk((hl7WHE=sSZZ1A~B2J4l1^Lk0#05ur9^1_m}05L-eBG*`}MdX0gBK}Klf^qNDu z5>adA7#P^h&oO~E;Ir9ugRJ(|V_;yj&0%6-U=WH?WME*k1F>0z6hPM5gLHE+FzM@q z?u?6LW?*2-Rc2sdcLs$kQe& z4D5|yMV*2S4D4NC<_=K?2KLQh=IZH|hjnEoV>B5U*srYtok1G_9s#p8BJF)*;-Vq#%nU=gxVWME*w4Pvu0FsX1cFtFbNU2HGR!hUZN3j>2tm>dHG z`~8JrqpU<27}y_t2OCuaGWH=8IBBQqGcd3}0h=3(N*Tn)Mj8{|KQ8Sz@R8}bh`f$T?r-*vFVvdbmb%$f;`2+7{|iE zAoh%zfq|Wq5#$K5s_6@k=t?LjN-{98^Dr8+GB9w8unRCAWMyFBnk~V=z%IxL@;(EX z>h#-3bS3M1Xr*IFt7-)NHZ|73d{f{DS;+N1_pM4*^CSf90Er*7#KJOX3H=z za0xiEFfecnRPr$}@CdwPVqoBv5?HCiz`!REAy0%S7&v-1urV<39$;f&-~-9=fo?@*U@B8$ zVBnYpO6{ypAbtEyAW2R(4t=KIYzz!spleq+44AfpuA1bEXJKIAFa&d$8CcH?F)(l# zFv!BLZv_6U3R3V3%=l*$6N&a72Oia&xT(<;-X>hlfjCnSp^L2F&5*x+l-T zz!A#?x=ERjYmXcQ14kU#8Ue0qHIVb-!7h^E`me~qz>&xl$;7}Q$;Bu$z4*AUYW*S5 zanGq>lVrI!=n31BWEDIU@rD3zrug0|SQ?^F>AmhI$UJA0R1dX7CBtTyY>% zWtc(E6yOp9ur3z?9f-p$&c(pM$;@HK3_5ifVw5@5s2orlu>gCOk;_e- zfq}yc%wb|+y#vy0&726*%)?>Fe20sH0ixL+su}Ea2dF!kK^fQ)teJxg6zcUHPGBA< z1M5^!rf_DS$Hl-PD#78(tjEp3AO;RZH?UD+#WD;G9PZ%26CpTi2e<&`slV?L`IA58NCWX%haH7|l_=HdVql8Yf8VPMSz)k{lQ zU+^;2Gq84n0)8DN3fVa}vL?Ze-2^puE2tLO%xc8Pz`(}9dJLp_3#%O;0|Tcb$9C4) zAoZZ?pJN9rxUl3-X5iS#3TmP;f|d8CWNQN|xQMptGwvy*T!<-r!?ksD~t$ z{ZO00zCVEMfrAhaFtDxwrL;q=%R$z9a~xw;;)nVEII`vw$eK?=G=m!_9H+pp^I~9~ z2r6byvpxZtRL{u)#GPi5RKrt%=&oPNZTLx(o~)*TBh4>@}zux(<#gu_RC)zrlKkmw`bHbO zKy76XeK3cWfprb2CNp50BEZ1F$--g6W+uqMzy)e9bC`lPGjM_0%N&q?6C)R>!OUUK z1}bKlxKj1&85lS$z&vIKR(DVlY035jWRwhtEnBZ30|R$XNj3wA9UCY)GjPoTm9qA1 zo{S6(0$iS;6zRYQs*NQemN?z zgL08OTRo^~Vc=2$l`|e-OIRRAd4hF|FtDb9%<^KJ3DPaX;mal>1ap)hSUm%GN@f`Y zhd?5evm<$ecvE!g%P5}p$m^r9DnhLf- ztQS;@rGbM$Oc10d9qb7PRv%EOB70X4D}2gxokf{F5%$FXDbzkW$XfQVufVjLU72JsOMk- zS;}d^(aLs5n1O*ivxtGC4HAaj-~eq0a|F0kGO`&sI=~zS23AE-jnl=pMwo#?)PSRh zjZ=hyLCgRYguP&MBvXqRIQqb<8CajOGca)Uv%LU0DiPG`oWiCk!oa|52s*0>TmbMH zf(`)UU;!D!slYLtZKVhU1J_+pDL4nrX5cyrYCg|pTQ34?StfzXrg>~zL9H^bf1qqW zpKZ4Y0|O726sT}rz;;js6z`0n&{)WJT!eu^gli7SbxYXJiZC!pa0!B(v5f69=&UFi z1`d{RPmP`4RY9i za580GF3rHeaT3ht<{`?!z@3{|!N741oTwSNb2IZ8IIe>^Ok9x~p!|OW%wyqt z4|45IFo%unC@87jV*3d4Ap`3kP<-EJ1Dy@e3Nn-90UPLicit*dSWD}v2m=Ejs3-u3 zCj(QsI0FNxF{p@Tny<{j!07>Ig3ib13vJLu44mAI%S0I%SeJns$O4RiL>U-(*~J(b_&@{$ z2Mfq_P65seM$ozNT!*9>7&t3ICWDHiW+es&&MFX(fst#?^oXmv4vh8FXI|A+i+(80 zz`)rImg3_AonFe>0_N~Du$F;*)yl{Vifv%sN#RSeN}iB`i*iZd_>-37HEGC^iA2=QnzFmPpoG6;*%Dn$kcu56GJ4x!Va z{!Zx9COHPCsi00_E{`|^gYXTm`n3`a3_>$N>Khp#H3G!!)5Ge0* z&1w~8VAvpJBhA3TH3wwo7NH)H&*w7LGcqt-5$cy@VBneu(tK6O2^4noL4EaWknq|I z8lV9U8QL;1Z3KB{L4r5~15=;`0|VER%MuI>ypJUq7$CJhsLE$xy2Q@Fz_kq2_~HEr zk^*%q!SW2kHe4$UB^elm)`LQMl^_$S87*{Fj)8$|HK>qh6gsKSz`(Tz#AX-z1#-$- zP?T}<(V7ku2z`%6|6mm?Gpa8iHW`gd2=eh-E8iU;Z6Qq%ohl_>L zObXQf1jQRGn4Q4D1v;vpi;WSKLRq+?LG=$LA9HZc2PH2KaK7PW;9vm-3abT30Vm@R zNl>ol;%00E8MqNd@Gycxih=7Q$f>+w4kMT6^vO4M73)2u7#LVjgOZUr*f^;>j9hYz zOrYT}HBj8kgGCv*K%4TpR2V@~&cZcco`Hc&9jxjOmlG&^X)togFfcseVgT8v$p{MH zC(_?R934hb24-QDz6gpNT}Dto;b4>oT}r{F#|Un$@GwfR1_g#bBcBWdg8-xSLmdVN zE+eqbB8<}CK^;J2#xs%(45EzE7NBfl$_N^jm0*(lSt(v_~iF3G@9!zjHN6w&UCA~FmNwT#k#K_!3}Bk0D>8;sJ| zKnc&A@u(OB!!1Sz4i;ZCbQpv{7eR3cfY?kzpusurKoFZn z=$;k>19uQ8Wv~eyP-bA@4hD5bd4xbCSll6Z85tP(W$&smFmQ)~)N?S(PGMtU;0_0I zxEN*4H5nMVBS0J;Mp+I$1_tg(kj;G4zuwm6*Kp-yVBn4hrDAnPSx^$=js>MK4My3& z%nS_NaUdB@M%n4pb?)d&N(W1VYD|!r4x=n+EQq@R)CI(E;f}5vi%P}wriK{a(aJPb(3_@JG3=G_Dtn#4Y z?pARI2JQ|}Dijc!4DxRmC=rSXnS$Kf4H7pI3I?g~1&Lb-{Q`;ify5((Zpbn)aMw=& zNyG@X$T2W*PXtNS2wea**C&I-8-(_PG)w`BFA%x_Vow8!FA=(=%D})q9VC84=szn1 z1NSVD_z58wCI$xX*&y*3Lgq>g4BYcT19opfEA<$-=Yzz*2pNFvS_D%6L$+R%k%57G zF-Ss!Q5Mu~p2dRir7BtSly&p70Qp_j|x;lva04VmNOF)UW zpN)ZmO;nzN0ffQvz{J48vXqU1feCcI5BK5OvY=@Z?kn!{3=BeXApc$kWoZT>&=3vx zO;CbkVPFae1*;@dvak!s@*o6#C z8$m()GDx0*f$0q>N}z`*?z6nZS+%9;B& zD8Z@-fhuS2KOnZ6P&FvI`~|T!rc2z{<&~-irR@J80UfRgH3kN525<{Vk8AdH`}?{I z^^4>g7)-c8C!KS%GJMQ^h3;3IhqoDn$l{8fjHfj+12UWoKac!zV2+#lXNV#RwX0 zX6Khqov!^rSGxWz$eVIt_w(^fH-H=iDc1SdCjpTE0W&8ljW}q$(_clgQ%4gvEBg4SJ zy&cRE;JP8tz`(r&%u(Pn0(pEFm}9^-3FN5VV2*$TxJ%Bxm(i1vfgym)bNc#+x{?~8 z9zXX1a9G5Ed&Jxa!JJqw&`IjthrpaTu0_*7Jk*s`(Et_D$H4wdVPNe6`SLiU0jN>j zzT%b-Z_gQeNc zWb9XEVBo6fVqoC@1ZFdEv4ev7GvicMP*3bTDCvG-1htnqxY$97`YYHcJY1_m-ulKk zTNTt3ldT8wzJt@G40v9M`v;gK2Ofaq{t5Pn0(dBt`xhgqC{yDCT>{Phn=zGQZGudo`lptw5LBuPfu}gMrgBMx z62AhNH;rorD3}$&vo_PYGC(Dh8kjSKt7`h5$GU3u7eOJa1s0pfU7Tyez-Yp5D^N+`#WY2kfngPQQcfxZw=WYY zZLEC_DE$!>?2xH7Q&5Qw$`BkZ(?FBbpn`a{Dzst2 z#K8I*R93|>EdceaLb+|ynfTQh7{J5P+?h-UpyTnlzJlU68|)xQt_YBqa=;cjah(Gt zs9Yw{RjMHtgS7l&ejR0j9$V3;X5%&zHnIJw;E9tmmabRV0(T8Uq6-2lp~2&?O>V9H44oIhf7BB?D^3tN?ofG$<1S>cQ>><*}7a zTh$mCAhQqL+nGQ&g$M|6F)%RH3vhz2p%eJV1)3rTm7~l8f}ph&0$m`@0-$SZ*#yq< zfToDGLE~KlGTNXi;seYK3|tJXNuZcN0=7^}MTPq_Qx_xgW4v)m_S`nB^K#pYz)&EKhu@0j|HXpe@wGD85rDHq$NST|4g&A7#KWQq(RA& zn}vCS76XG1i?kf5&|_uZpvA!OghjegpMim!4csIC!y;V*3Tt*S?=OpV5y%uCW@*r3 zL00LDpju3b8PxEsV3U3g%KjqYX|)gz>HGDdWFX26D)PcOq(Q@w++twKI1Xvh&?C1v z*w6$H>AxT=B$z>+{v;0Rl_1Z`fK?W8Nb`V78d)%}ghSdB#8YMlRSy*$a)||*4BYz6 zH$@m2dc>tcH#u?}F(1%kU|1tAeH(Oi61NHSH7y2)E#lHue5|lN(!TwZ{kZuOmBtBrn)Fhm7f{suF~0%vq@)8tD*c&3 zgrv^^-$Bf!4?qb!{dDn}y0yuZrQA)wq7#SH2?F{nr%1hpcf z!E!t*(p;cujREs`Riv9hHpGHe3aCiG=B#I6;7(v>(q>?gQDI;MHPk^#6PhbISgg1i z7}!Ah6qG2TqHOoo7#KkD3*%qVVqgGaFdtNKJpm8Rfyyg3P#FdaBd{Dh0~<&X6fRIc zM<$C9X!#DPMOwqG`bJmS9^`~FT{I_nF)%O`6)-ULf+eC@LF6rg{+9`M!m^&QA|)E+T+nu1f_=z+G1Zi{L&`AQdn$%z>J;<*lwT7dZH~fMh_y zr)F*eT1vDW?6w_Xx4qPdxNSKHh&3Cl+qCr|ZgYO8E6fTCIq&Jw?{uZLK+zSa4{~M{ zqalM*JOcwmdjSK3QYp+y9UzMf7#QYFU+_*>QxO!lTOsOUVY>vXR2>vjaUeH}O?$5^ zraA+3$L&e5J6D6O-ttDFaQ;(m}uP1eZ;3=EH_zkjbQUk{4dKVa?A z@W@r3#lXM-icSGTu(?bVofyx7gMBa=>;qdPh!5U_Qvs+8 ztno>Xfr0T8IBPRabkK+gUAg?3;~*;o1JgtiCneCC%V6Ju)*ga?wE?{7|V>tc8dtE8@IM6ZJ`V0&ozzU;4E>!|0V6cHrP+zMXL1Nbaqpq+u zh95NbLASNJgQ_3U^3gmdP?^MT%D|un>L@e1gGTkNLH%}(>AfFywXEDg_uhGdYQPJO z3=F!N42<5OQtKTf1A~qi=+;IbkY+0;1_mY2LCav5fR>oV6-+;PPfKz-*C$;`<@p5+ z3_Qk=&@EzMPzr#>R1(z9&c@Rnx%I@R$9#enU~8c=4aN}PO!}lN$qMq#g6SJR=}Lo> z?9S;IKIw`$t}b9;xCA#H6k~=A$~ue;3?PZuC=x~tN;!qo%xHdP7-L4LXQ&^ zB_~0#R|igntY!=h+Ta@HBq(YagS0Mz7OtEG)h82~7#Q^ZK~a7hq|9Ir0|SG!83O|( zuPT8~F9+EI&ucTLPyC{5WD9cbCR31SqhbCqU{DTafcWDyvJ9gGgHi@GKGi`57bM3| z7yGI!9tUdUv4N^bke%RKQ-r~g+l+xhuY#R{f$=5C6QJGUjB}QQJi*Tb5(Fhd#vrg$ zL84Hnf^K{OI~8;^A1LEYG=s$3g0H$VJ|G9HFh(&Ify2~+0cuMDC^P;7*#g>u&p1cg zoPogz)Dvg?1+fKDrNHW1R&z*Fl>4SDr}ll*6=uwwzUZ5-l25k<1A{53ugWM5*0+g?fx#4fHzbWQ^1zlGz z%?MJ<7^3I^+IuF;IMITE;R_Q3gEHtEr*j1i3_qs}eAg9$RPUf8UO=H^U@_fLPfu*R z=XYHpaApaZp732)8d7;Qf-)DlV4gnvyRMu9sO4lP1uEQ3zym3u080R;Ee%Ts2GbMM zZ+_QR76;jjNHMVTOMJTHQ!TOSnm=?U`EG&hO;9W_FqmDN9`Hj~MEfhqga;s(hk^Z> z#mvB<@EufgK=_Qo5MPEfc2DpBp(}0zvIf)^R0iF}1@hiPOHe`tnF`8vMhr@zgKWV` z0dx)$$g?*fZusy+S2!0IWuWXA&0MsV3Dg!bV_+~|C&R$NSPPCh8?fJ6tr!>-z@=U- z*kz1CYDKBVAT^+Dbe5TcLE{JLI?@J4&}wAHU?tF**kF4>i|s-7=1nj7sjI2=4DM}E zwk~F1U@!*Xk_#$f7#JX#w8NT#!PIm5;h(y?g5WZBIwPo1^<-gSQ2a5S@t3YJxRm^B z1@kL|5-5bh)`1cl$T}12>5i|o#HRcHf|Zh>!XG4)Z4F6a&A)Vo4L+ecM};wl3A8xh z_$z3o`$ljGG=M{(-v;ccW50CeL&1*P40hBvu%kd;-vai!2rB~vI6Ka_ft4KKvwg^{(j!*;#D`*2f z$T6|DkiaYb1FHbiK>4G9fnf?%X3Za6VJ5D^=?DMl$_hOLHDg|Z9kUDMt~oB#Km5@Z zaRkk`GQI*2Nihan`G7j_Zy8KM4 zZP0Qv`me5FJ*YQqyc=|Dofv3sKLcnbIOCjddyua|*J6t?fr>A4HUlBRvw0eJvSZXnO&eVDU=B$2P-E+nINShB&Nf`&Swl&e8bAX zz!<>8_f=k%HXb)~_~mD6|rhZUz^K*&n)1fwE3F zc(4dml1>Br@0ugbf8AjJDY7##n1ZIA7`vH3^G-L|85kf@(hK&}PmnJ_B|OL%9*$sN zfIR^^D;iWRCPBqYL5&fnVg?3f(7A+}1q@6KjZ-)3iE)BD7ogH`!PJdJv zGBAJ?K_XNcR6FYyGBD^lfgQ?P#K7@iia`m~69Ol2&>=aXz*S+4ntuJQuE6w4Mmgix>(oSoq%5-6`* z7BVn=oBo$kPX$uZf%ZT_^OYl$o@_KoIk;pIV=x3+V+^`vj`1$oa?o*0jB^fxEC+k_ zF2tT7uss*y_JHO;7+gWQ7Zed-&w-B3g4%MPNl#V;P{$#~4dy7xRPYk}w;T)%rre;eyd-!W zijR|l0n%=fW(HO49-Ise-~a{bgr*(PwS^$}*tjA))QCX|v{42Wz{;Td8kBmPT_Gh* zH;bOKL?9>*K$#Y-q!5$`L2YPPNbz)sMNb-1=YR@XkY=9gjBI*h)1_JUWK?4c85q>v zK-NLqx6E7~91KcNp=E(OsL2S8(IQqo$$C(e)i@JWq`QI#5X!+>TEQLC`*Q_*y@r#4 zLE#>#a&QHEoiSJ;2GkCBWd^BZ4AIB}MXNhAXn_*bLijXz`Qr|Yj(o7W*FjEt z%*(*Qm=8`DjKPo+rVu=&`2)pPP-_DeOv~M;GfL`-P2a_)Cm{zadv?2n!U@#;VgMb- z03LZ#2elud0mR0xXXMi50kgRWY%^%ThJrgN^FsKH!I1L04{S4I6rzm`N^~H5D?K1_ zJCR*axE^FLBo#6+n1Sz8UkLU9s5k}Hm5g&h=S7=>8*dB27P@jVFqmH8U|?We$h=<+ zwA>n2oGu1ixqyp-K@qfen{f%)q|IE&18p!zNPB|)Iz3EYKw!EthaPmy4Aj2?xiQES z;>O*adb}zO%Ahe3kW14bx)+6GFHkV;`Ahn{Rb2PkD60Y_FnDBk9n`oV(i z2-pX&xL^Z=N0>o#XN!E__2w|*4tephY=2E`AcJb4`Kzcg+J z29Pfp7*8;l3WEk40?acR7*B!+V9#(fh+y>385nY=CvxhUL2?N!|EvOuiA~?lsV4=F zg?(P&5CQp38RWN&LI#E#P_Z&_1yaPopnL<`GyDOOVJ^D@?%{%Jm>5O}2IUt}c?oZ@ zY0PC)m_Wr#i2$f^Zo#1B4(pU>f?5m(3=FZ}3=Gplxb#fG^;YflUM^U62JP_y#l@EC zfn0iG)6a0}2`7Sb#$|}nOl1lnlgq*VKr;sAXN(LCC4~$O&tcLG49Y(kA^li(AE;}d zKwJwRwsc@n3Sxo|5mZ9@-V8p|9k}((!A{AYUc;>?18MlYfJ$%jfh3DP+Ntc&2aQ(G%0!<_q=#qb@W+IT>E(# z7<9l*%DJEx9^(5$0;5tMZb7#O7dA+A>8(^G_m zgc>w?L_lRS`She%K}A9B^bS5fg@lGeh;g8tX?z1z`~-qGP($i=nE+UaFOUV~A;usD z&;%)CAPcC&#~7>u&QHNCAonvyAqr$z(a0SDagQv&o+LPPz>BEIvJ4E2sbFJ3MHHwu zXPlE70L$R1VC!!4Ffc%@NQYXX4r`^t3^G0fsuU{0Zsr5W!Gl1UA(dc5Kr`s3%|Z+| z42+d5p#1}8ybKHq!k~hok_DugF$7Y^SA*>c=Vf3}d=F}2)qq_$6U4tV{Ubj#{NDyZ z0t__d1n*XxLBn4w5aM4O0X<1b_=BojQ07a7%2W!#ib&9aDM)4pRAz&K9(1Id2NY+J zl=fIaPt}l7oPohi2h>E60q;`*1(+(>uYJJ`3~EU!i42S~tf2V$&C9@GDkwAEQczD> z1SAOwJ$Y7e1cho`pI#uSrwHyhR|O&b0V)Q;Z357tpCC7F41)OM?Jq4p5hXuZG6Rip zfTUkQq^Ak#L3^o_p#GPit|+9Z$=XxMz+gAsUr0|1%#50zC!{A1$wdqZzbzHg6EpzL z0-1ppYclR-fwh$0f!hjlp|E(|3y#MOJ_ZKU@6(?N>Dh*WlifjZd@+V<1cJii5DO@n zm?j1&g7%Iv9tKBs8$SbsGN`o#s&s5a5IzRA7{ES;jTBUcKz!UI42wBf`Mw=0b5dAO z((YLx1H)CgIiS%M(3mEp0fRDVzdk7azDJUc0hKMvCm0wQK>Bz?rz?o)Nz~7PW;syH z)%XKwXwn~i=F&5;x95hzyzLK;(wY3A^}zz5LvXqYe>!OZUIb4B$e&2~fl%UrUC zk%7TD9yD=Q1NQJeu!rx4!_sgK*u!u6A!+!HsGf`yIHK#oUey<1V6f^3bz19LK}j1v zpduI!b032etcRft%aI<_8^!d*rYDHOl4>k8sn&xeG$B>_OsLp4keJx?b7FeJ^~VYs z7*2srjs}edDV<_qU;v3J-C5gL;ghVOVfdhV>X{MnEEPqqv@MJ*aZs1l9p-;hMNry<6s)k64NAZaW^X|qrTO6G2P%6&Yn&M8WJNPDn1ZXX`Cv!y z6<}a66$iB^=d*(3?g=n3C>nhOh0#K=*8c*~L9vEtSQiwtQCk!VnV9XC&=X~xFnytf zo)jc`!e-HqM?!peUji1R;EBBg28MsrB=s~Qia$al)HDjB*jEx(>MDZDp8^JkoT%xH zAGE}#w@T_kCxCsSGOMDdGk(<-o4!X9RuWV~WnMr{`zfg>1xYx2p)wlN6{YlyASE0x zsEq?Dy^E#v^xzY@V1ki-@y9v1)*UI(gx`rBEl403$qq5Fv!F}f289fb1B!F5cAi=0uknLjA<7D*IAu_NT^@*{N$X+D_iv$j6fL;UZ5uN@( zMo&@dYas)}t5~?T%AgzpO4nR*)1_tgqzpi8P~)*=54cqdZq+fGF)+yQ0(Im-XGJhD z*nx88oHGdw45lBZr^@Q-a?A&d=XHhq??o_lZ?sKyrpZ}4FZ(QpQ}*`T~o4bXaS zMhFj7zu179F2dlAfp)^s;J=dqOVW0rJ8D4}^BPSzk%Og2SmG^;2L*-bbZu!paS`yS zCOG((L6hsIct}t3ker^h1ISmG;=#UVE`s=Mq64T|Y{metQb7HRHxPNqNCneG2L|O^ z(0&6?!gN`A=pdH%bQ^hCHWGveaCQQuWn3+4)X@Ow2$Y z0w-1t218J&8MkUPFfew2Qw(TF3FDm2$&kK$2OFs6aYmSd!PI-Yu7aK}qxtk`1wDDj z+0&~P^z0cMrtenJllKG%@C0xGhlw&UD1w6+!p{Qn!GR3n*Mj)qP@V`5WzdcrJ5XB- z6ts%dl@;|g8NH|bf~eBz<%)WmYP>}Z4AYVzVKs4My$WMA^TZAHpujR@P~O16z#v(~ zz_4rjF-1LjuxB4kf2F9W$i`U2z#y7DT~J9+Us1J)fx$2t)rjr&49X^q3=D=v3=Bcj z6P5I2Tx^RN7*Zk1K(&4VBLjnH5d%XlRLBria2hfw=R(CnXY{EsMlqT|#MMEWEp+-p zB|R-|wiE^i1#tiRCV0~lW00}{0|Nudf>%(}3>efw*)DXtn6jRZm~sXKgDEJ>F+O9P z#>~I~S_Nt9IXyyIPo4vuZ(p!on_jQ1CuL-u0ZWbWN^)Wf*lVCsPsD5x=v;nK4n3Cw zNtO?k^(37@mDmfYYRE`w2?K+2Dgy%p=v-o^RERln8KoJp#sF*r+G+Yn6+N-(fhu}3 z;ME675G~AQ|MVdZ2vEG3F)00nX%uCI^ton2G;UPU6VuuO(F9G|ps6YFl#G%Ctlt|0 z)$|Rd$pBKWfToW?{;^7f_{UXMPXQux0;;+YD$}W|CnndN2KEc10fW*fn6WIN(z}3x zVHZ^4B~?9P@kCH#Umn)S1x+-AY~h&hsHP`2T}Tbq6YYiS^#w_o*Mo+_)6&6KK&FI2 zGuLaF7#MPk7#Qlo646W?{~@8Fe3FTQ0n{0r43>yuDrI0$zRJYF0BTchf{TFy5K_Jw zGAO-*xrhPU-F**H#|TP=tkZqf^th%os_RKY>LoRhB1pYtrLHH!3rZy594^FQs60Jd zT~AWXA{*BBOlJpW>Q&+l45sPRyVUjcMZqnxEOt=Muu=kA>RC)br>>{Owmgf0L2>u= zZ|ZtR$`wTn41$>uPnSSvZcxg&z)VQoBxvZ#fX4@lrZ<9^%|)OUGK)0y)YaA885p)h z%_stmn1I&R7{Ou)RQiL0|KIcv8hVzH=mk%k6fiJ&WkKfq{4`-z%{FMnPs@T>J5y6n z!=$eW;y}=#BskN7Dz@EO5J6B}!<&)df$9PVhTl-_3%=@#^DBXN3xGVO4r)k22ld>v z^dt>Hqn>7=N(>B)^Vne{0|MZh$1WEZwDZ70`&5#FL1EMMel0!CdPf}w2FCedVa71U z?dqT*Ik5I-DcF$JVsOCkl44-c*bOR(m#~AjiZD$K0M9al42M+y@cjNU8{r#xX9qSa ztdRqjgrpPZ>3Q0EoYNh&VeP3bXl)cfJyBZ^+Cl~$Oa=<{X&^DN>FeN%L7f|r#9fHQ zQ*AwEHc(V@=1%9+(NhCw0*zd-bxfeK@n|N{7+4IW1%vtz1_lODR3o)G86cAkX6%X# z42(y?VE}3wae{+zW*#gEkAlPMrxXK&X&R_~3E>+{GcYJD2KDP9d{DnW6x2C70S>%) zX$A(xJD|k~C)q)}Mixp#Q!&U~Xy}1KX|6RWEy1IcutG7g$RX6ovx*Mp`|%>IJr=omO)38WU>4YJRN`Hq1Dl=pstoC_}2 znK?k2&Q}KNT>pG{;SL)N`JD#|V32b``}@FY6V_P=RX^YYfti6}`h&N+?9<)!^i*^} z#(=ZGB7-5wZnH|zT(=x}85Sta*}<-=2fJ$eG(9~<331S>Hqf*c$arN?uz>u0CLaA)ELv=<5 z28YAa3=AwMnVhD_>FbGefyM`%7D+HLESg@guP0T1fS-W@gn6DaIlmHRU;ts4HXQ~A z5awFJ=rUWHfdPcs4>G#w@h~ueF!vv3m&fu93?R(0m(MAYkAVS%c~x8lL>L%AnBy3y z%L^$61`y`n%IuP?$-n@@-1C`TcB?TkfG~SGW4+6HaRvquW^ZG3dBe=W0K)837+q#- zGcbTK`yxgc4RHnr5ayb}=yac%fdPbh#au#}85lsA=PQ#-z9a(!2=jbra+$%xzyQKL zKbf31$TKj2Fki4sfI0&M2=j0-yUbBwU;yEIZe13aP$32e5a!lqaVgbfU;tt67tAi| ztPBhw%=4VdMMRW=0fgCu7@b7L85lsA(ZFT4Is*d;bE~j8ZB<}k0AWUBm(3gu3?R(& zn#mJr$ix7dXJO0`AMY0G=N#hc?+21MHUg)Ydt9e zGjk-Ap?+%AVF-2#Y+B*kMTQY$SFC z61x?NJ$d@hCVl1lLr6mBk=S>U*q@Nt|B%>R+z6+LA+eQ^*!oCpYb16Agbmtl&%n?F z;eg6_jAXIubhJ4n<-oBe5%x*mIEBpxv&p;@!u4-y-^oID4-S%86I36jJHB=#O8 z_6a05XbU&Y;)h7$py67WxG-p#8tNGnBz6=MyHEhMvJtAN7D=LW`o}hXYspJULidr_ zZ>PJq>nlsjfQBNWx;2s5=F=NN(#1$Z4M^<1>3iGt#p^d93GGEfMa)5BgHGOnh2&l&@smjGt4QpJNbGk=Y-Z4^ z38~PE*wX_$^}UVy zVO$0VhB-*=TS)9@NbFA{)6aG4i-qcmB1%VVB(^6KI~0jsjl^z4VoyY3&zWx7rLW9* zYIzOeTZ_PBNuP>_#MZFA{qu5_>5U8?vrpf;{w|Wx zD_jAXE)u&E!iH4!tq=~_y%VQz z?bqMWn*f?CfSR2<{cfbEc>Pi&p^ZrFy-4hnNbIXf?1xC~w@B=tNNiTn4i2c5f=Fyx z2pcq+&%mGw;eefLio|wAV*4VoBazstNbJJtsT1|H>z^VCfwyx(?Uw<~qd?jENNj5) zwg(bB8i}2b#4bi+*CVmJA#6|~!N4#B!U6kfF%o+_68kU``#ci+HWK?e68kd}`#%z! z8#Jy2^_Yah^mCK+H`U)p5_^Hf{)WV6QAE^XLP%@{B(@$B+Xjj4g~X0PVy8jakTlp0 z;eZ2S`gFl5`r?c`r^`;!7oYAh1=IjXl4b{uQ$qcqI=yg;zBOa@^o1a$N2cf-NM1vd zevHKaIGuN@ezs~JXr(4pcQq2b6Nx=_`rN7dzZut0@13SEK7GS9{RCS((9SBTHg6<$ zDiXUGiQS0AUNhZyy1upQS0o`O(0CryH~}QK%=ER>^@Ho{k%W4X*sGA(`;pjZkk}89 z*guij|B=|Bv&LXW9XDv)7U~p12pf_vK?fbd6v;v)z|o_O#MVS&>m#vEk=Qm!?06)0 z4idWxiQS=Ik4S9OkR+BMu{R;HK?hgE9C{8({0Yysq#LBByj_Y{S1ly1&Ph1 zi3m9XB(@w9TL+14g~awiuRbn)ljBH!uD` zlK2N=Lp8I5##5neSr8klSq+J;kHoeHv7zcgCx*jvmOn@wv}+0!Dmn}d!eDki14BAU z0vcR7AU0TnfuR(M-3?+xEuMnJo{Pj@3}Qp|?m=RoM`GVVV!r~h>!F5z263S5KS*q5 z(4q@y9D|O4W8?xw5(5LDE(3!wl&u6(1NDG9hz%7tKw`Ur*iiHRk=WDkZSi6HdGvRJRc*JEeDz-f?BMO#5O=;n}OI+_5Mig1P~hD%(J8sQ7*)_C*jIVrDeMEd+<*F%tU&hz$xN z1_p-jAU0^FDgy(x;xr z2C<=fbCB4jNbE)s8y2t&AskQ`GwecQUq)iTL1KSJVso1yVpjx-EsMlf2C<H8|l}PNFNbH?R?6XMhYe?)DAU4$hACcIH0HgK*dZV`XpuJq14HEWws19O-7EdxTFld`GFbG50 zW*~8>pPZ4{z94ooI6*K3f!I*>(Maq<5F6@y`#@}{_+bzmDt-}(eFwybs(EM*YIi^__yv-HvY9Oy7#N{!Ne~KCQ48l;hGe{h&#t+1Xx*! zc?yYr8Hs%p#D*I54aA08{1?Oqo#_Eu8)U`6APi;mSRt~oDu@krkd_rF5kNItfFz(A z9Ff@JAU4!N2}tZrBz8WC4b|HQVnfaB1+hVAt%2^n1UU%Go&ypGsR8+aIfw&w(RL*E z9uOO(h=GCO6cYO?hz(VL3&e)1c?x1f#b1HgP|N-yvDvK|7#N}Aveux+C)8(ZAPFd2 zABk-WVna39A+bY1Y^eHJBz77SI|syu>g@!vp$?q@Vk>}SyPjc+H3Ne%gu^f&Bmq^l z3dDx`W)~8BKZp%ga|*Y_>z8*0!}5F6_1 zH6S)gqxe2P#nmVnf9nL2RgaKN5Q` z5_>fgdmD%i)w>(ShFW|ciG2f!UH=Zmf%@z_5}Uyu(Kt{9v7rWOA+a4mY^YvOBz6!I zI|9Up>P&VvkfH+WJP6n|-=R`0tFif{+U=W6~7lFi~YSx0-P+x8W zv7zDzkl5#t*mscF&p~Xc-Zvn&DzqiS;K0DZ2(?TEi7ku7HU_bwKDI$(yCSi@L2Rfw zSxD?IB=#yK_GSlAB?Q%Q6eIz);2aYBIuiRehz<4eHxOG5k~@AmFfa&1*{qI`{0)*3 z0I{Jy76q}PdKExykT|INR|RpP5(XePNP>ZZ!F0OrMt$-6WRMWl>?S1kLL~M9B=&U> z8*1D=5L+GO5(b7xjtmUKQ1)ApI8@DVBsQlL!tKH!b|N%}BtRUfW_={K1rpl}#D)f7 zFcLckiJb~!gAVv)U|=W&v7wHr0I@;a6&V;9YMdAtgrV$qCr}JQ6-@;xg0dGQu{R>I z_am`Sg4m$7&I}9;=RjGB7ZxfY?yG-3bzhhIk){4Gr-*NbFTe z?43yLBOo?Z?@16FYUU**_6s*q2?BNXN00=R{R@fB;LgCn2-Pft#8wBfp$^gmu|cPT zF)%O~xic^bL)o?U|p-TY`rI_8ZiZjI>Tm91_og$dmoablOQ(K_vb)tsOCFJ?B^ghRLvU@ z8>;3zhz%A017btP*}dSUY&`=Hhy#^S0kNSPG(l{rgN%^a9w0W(vLFsra~%@99n7B2_pMqSHi*0)Bm^~YD~Ju%b_I$30*TGxgK(E15?dX_hMHr5 z#I{6Y`-0d|^Xv1FIORy}UJx5<&@?3Wd?fZ}5F2XHWhC|;B=#o|8*0vPBsPmLI8#BQ zNCL!x8l;HCHV3hxnjMhXo=EIa5F4sD4vAd?Vng-TBC*?$*fV`WMFdpyc8~;=eE^Al z4a9~TbRUWR0*TG!hlmbtB(^Mw4b`iL#MXzgLH;)baiE#R0mKF!R>Hu*;Nr)?APi;u zgT$d~B0+3uMv4Qmq2d`JHdH(p#D;_3dEt>*nPgk?$ z*Q!4RWTe*i-}!^m2h?@n zK@w0lLjb~OJRmkyvn+@WwM+xV25qTlU|`S*U|lqkMfjCf!^B^`@f`Q=$hz%8g3t~gXe}LFf z@xLH8RGd2mG0q}|#8w5dq3X3jY^dYxKU=W6~ zO+n&NH4Y#))T^!_HdH(qiJgeV&H=GAp#6wK5C>{#D-yd8iM<5GhI(%;5_=mG`w)l? zHRm)E`yq%8)%yyG{W%n=68I02fNGWuV_*QC-VUmBl#tjKAU4z>ML6rcMV+fLf`pgQ6?Tp0s1hJv&gOJ!6AU0HQ zAriX^iQNEVL-lqd*!2waK^&;&6-exjNbKz(HdOOzB=!{~_B{|A>f@&%Ht4)R1_p+g z;S3DIQ1%y)I8@Dl5IX}D{tOHZET9DfPzfONy^#-w_mL(&x zbCB3gAU4#)-KI#KDM;*DAU4#X%}DIyVD|KP$MwbQL8p;3Ffe?IU|E-b zL{vz;AU0H70>p;8T^7WKife$_P;p%l8!B!NVuQ}oV_;yg0kNTW)w?2bqCsq^r&5sE zxk&6{5F4s_A`*KR5_4=p+_LO7uO!tfl#hHCzR#QurI{tse9 z9l;UBz`zJ)%YoQXz3ND810=Q?hz(V59|bBppqx;U1XObz5<4A^~qj)N!ma2p{tyvBg1b(DAJd z3=Fa$Hq;y|5F2WlBZ%z`PG$_QF$@gCP=mumjF@()sPKhL&Xa~Y^ZoOhz%8Q z0I{LseMsy%NbFTe>>Wt#BOo@&5ukK%1IA%sV0ehc{tjY8ea{e!@I5CIn;*mm83bBu zhQ!tbv7vg+k=PDM?C4lf6#~_q0+N8Tt3Yh1=4K>z4-$J4hz(Ug8;QLU#D?nKg~UFL z#J&zqzWpp!o>c=75hN38?08AU0GpLp%cmV>Bf7vVz!9-*d)8LISj2O%@~$ z)eE}Y4rZn@*M?YEce| z4K;H*68jN|4Vx5s3F5dzg86L%1A{P>&6tR&irGMHXtW4|*w7#s1F@mvDoAX75F4t- z1jL4_u?MlC;x37xLI^71k0cQSVnfB_L2Rgo6c8IKUV_A~2eF}QrhwQ`HA|4#TaeiM zL2QtEP$D=2;y^W=2eCmC3=9lcKy0Y^eGnTe{shE^ioXZ3q2gaaY-q^+NQ8tUXgLc{ z5+W1@L2RgAnIupl1l0_>hJg`ut{LdE5Rf9MxHX6k)!+tVL&beSY^eGK5F09<3SvXm z7l7DM@iGt_>bU6$c0I#-5C@t-c7xbZMGukKV#y2)j8JhSBz7E1TsG=JnHdOpI5}Q2*(Qy?5u|X%(GB7ZRr7$oE zL)nTTai}>uAT~543_)zDxJ^BX1C?+Dv7r(^AU0Gy5X6RxXMxyI@q7>)Dqaa*i9H*My%EHQ?f=>Z<$$ywMq-}_v7rXNL}D|iGB7Yg#d(m}N+340Y|utx zn;@}mL2Rf)ol`-B8Bl|gK@w1Q4idWw#D*H$jl`aU#GVCWL-p=NVjn_c-vF_p<~)S6 z>lqkc!8r^J-$87sK@4dKUy6a)P|fm4Yz-u~HHZz>>w?6N0 z#OBUGG}}aw*s@4$OHe-+R$se-Bz(YbVDQLbU=W6~gF)iZY!(M%L$hBphz%9b1F@mv zbx7=H5F4td55$J5nG9ls#6kX_2jV~_7K7Lz2?hp+wIFsR#6f#OY^a(;AU4!-$Dj@c zmBi;k;!wS}Ky0Y``ye({{1u1|75|xmRQ~@1Nk9!1%4A?*gtDcP*oGiBG&-!1*v?37 z9}pYr=pYaqYECf{dp?3)&#(i*VK|7yz7AqTEqj2(eu>2X1Y$!i`wwD6E#t^Sct8%s zhMJ>}#5Mr4LE+E9z~BwyKsARTv9myIsODlMb`27HI*1L`y8?;52Z?y8*<8>fH@uL&fV4fH+Wz^GNKQAU5di zOVIKCAU4!-pODzUk=TMch@35j#8yUPYl7HNbBrKtNK|`(IM6@~L}EuFu@gXSsOC&0 zc0Gs<)!Tu@o`}Sr4q`*~E$%R!py-4Bw08gv4QeG$Zlg#?HVHHa&hfq@aq)&#Ss z-@BzRUJttS7_^-^mw`bT%8mm`LjySz#D<1`9*7MUuLQB7;&mW4RJ;d?Jsre`s+j{~ zL)9z?v7zGiYd{>R#5NE+98y~C2C<>4C?D~Js>XMP@1=V28{ zA_(I9b$JX7!cg{3kT^7ij)2(EpgRd-L&dLv*iiACAU0I|F^CPiuA6~@;RT2dHS-UQ z4e~#0J_7?IR6-oYhWbDOiLHsmHUhDshK7RJP|FfP>=1|tQt}xXgrV$wkT_IL6^IRW zXhS}z@_5HpIAPL1Iv6GS5S<`#(>5JDF zBMFrwvFnl8%}DGHBz6xHdkPYJ1`>M#5_<^}dkusQih2fy4G<1E)^;GV_aLzkBe9Po zvCkv1FC(#UBeCxzv7aNcUl$-H{m)1e-;vn=k=V?Ii2f2c5}O~1Esn&NMq(=?vDIO0 zkpJ~y9MDQcB(@b2+YX8ChQ#(lVh16y!;sjqNbE!;c4i?`($7VbC`DpdBC#8h*sVzH zUL^KJB=$@s_FN?PQUtr6VI_jYumOp^1&O@}iG2WxeH@8>8i{=wiG3Z3eIJSa7|aHR zKLZ29YcL0#{utgPvA-d)e<86!ccQ@B+iXRMG{J|&7D8f6A+hC<*lP7i94#ca5fa-B ziEW3(c0yu%A+i0C*kMTQC?s|glnpLt(xxwbq%ZDQ1Qi1XLnRWs7Kz=0#O^?1_am_< zgW1#hJo)9O&pD|ovF)+GKo8@A>4NzN{)`RN6Y~xHc?BjiGRy%jS7l^iV4Z&PlZo{7 zfHp;z>38xCR2bJxXDl%AXH1wLSYY7Kt23FAVFgqv_wO4SjG-Z;UTjn7*>eK%FsS`o$sx zf5r>b6^jl0nIvXRFDf?hW6YU;u-L$#am#eU5|F(!85uw~YJ)DSQJ(%#L0NiwM~Q(3 z69 zVc^eXFmHNM1=zrY6<`AeD-HY^OQt7+s0q_If+&mWj8)(;4g^s>(-(p$hv^@y4E&jR zmP~i5Ht=IyF@0jSfj?u$^oP|3{!B8ka%Fr%Yc6qFzk@Sa0y2F=6_{1_OV_1=9^14g49;OmA#7@MqH4I{i|kfgj_U>55GT z{){`O7lJ64=?6j7n(2bg2L4PU2c{=A8~8CsOyAgS;LrGCI%A80KV#1HKoIp|`a%%( zX8K1ERWseO6%?mOr%!4H2iL<^1AoRD(+%6eHaCK(Ez>Wy8Td1?oSLrGZs5l_V|rn` zfj?u&^n>jN{!BXOrwer$_%WWCp4egF&zLfOV+SZcFHUFbH1K1RxHvti)4-3hV*0{P za0>beq9#mt>@x6Y?3q5X%fO#W;M(*@U0^ka-QehG1W_K-FM_Bu(-nIR{24z?FYGb! zXHt1Q{ZNmAALD}Qg1um+i6E+F`bH4tGo7)|z@O1(dSD;OT_2_|>ND_T+%Wwkh|BSL zx>G+mawhg0_%oiE{;(h9rSH>?CK&iJu9@CA!N8xWnedJwcT7^g&%$T;19GrQ=t=>`Ifjnf6E8>qAHbYx`MF`dzbQFwX)NchO~M38Wy zGb6);>4~mR!qXRkgd?VJ1PKQwGct5ce>f{lc>02LZUM$S(-~(NsI&I8GBOxW|M-kw zbox0yb2g#Gl$0X9e0>E&6H6llBSTYT^XYnfr6rjxOr}4S<5FiV*gkiLfx4hLXbU~~ zN=XJ5Mr~;Z2A&^^3=EH?ru*m1N=PLsGB7YRvDXVSFtC6Q!eA?z1_owPP=A?)pNWBiSrK$G z56g6B1_oxG0??X;v)m#K49vRKAa?ci^{WgNw9fD_FtDg?0*NqiF)*-bTm~_3Nii_6 zXlgTptYKngWME+PmYdFa+E8k`@M;4gCVq+O`lk)0m~v&O>zA8JNqI{!Ft9i=c7PN< z6<}asafPtixTeSR+el5HxY|I2iHm#s?$riLjQgkGTWt^*(g50RD=-aoIHf?o5(5L1 zz;R9n24(>T83qOx0YM=K237`^D{}~tR%oFfMFs{o+eM(d zPUxpN0|T2Kh|MBY0b^*r2%nS_N zp9L8h*aaCuf(+bl(-YSkNUFUMV_;wx0S6ch1Dl;F0|UD#V=KsnbPfgv4$r-y2-!4! z!CC_;r6WQN3>-}$?JNRZ3=ABt+$;erK(Ll-LUi1_q8vpupl{ zvaZJ8tXY37&vU1 zKo&4^>j^V3aM*!4Ox#OACfYM8fRY6Fr|EOo8K~J7N-;2S1b`KADR6`_Jz-^F;J%{B zz`zmC1PTuZ?qE3v295|O(EU72++v~(3>=Y68yFcFIJonttv8T#@{nX;;D`a6z{_nV z&cMJC%LKX$osT;}jDdk84s4_VH=hgx14lgAatZDkAeSUEg)lKNNOH$ck6v$}R=-7n zfq^3xY>q6q7swN7V2&L38Xg7)j&v|bo`D?{;a^x87&vBwPAOnuo6gR_z>&$s#md0I zmBEqE6v4*8!2MK~fq|od38apJ`#T#014j|qY6Wi4iQF7zV81DG-v-rTCW11YRwVqjxn;9}xvU;#prGPr2E`ng z1cx|t0XqW&Hz;#(NHBi}oh!#}3{ox0?8nH!z{0(qnSp^riW%hEdJgVjkd!p@7e)pK z9`5NNjtn!%nF8GNLEe`G8!N(n4-|Rw%o0ot3}Osyb3rks$jr^oz`(`Bp~AciZlfx) zjcQOE!6s>dP2zx3%DW*@c#X0!Wti4@^>ubGk!=nS{_(P^_!6s&PU!d2)g@$?_J1vaTL$ zC?^90Z`O3i%?2Vu6F~Xhg0&2$bPDJ6hbxRFrrU2eV6As&1zE|q4;0%W5cXD(%kv;? zIgmBwU^W*QM-?kS7Xt(L4nYP6j%rp=@xZ_>2ePn+bpa>nDj9oFSy0QmgOh=QojVs) zV%4#(0fi8EqX+{7M?EX3AmU_Ty9ctOf%OPyJp%(5Cr2}DB;4E{5TP8Ng%g4$hniioFMKlP(d^q?66>NH&FOY0dqna*g%JJa7<-Q z1-ZqGV+N}tH!QSfBD-Z4!Y%a-9J3*gVPFdY**}N%14wrO$9&doxb6kWx)&mJGjJ?| zXy(2LDmNBGJi@@1#KgeBv4m9@RC8_z1^hZl46<`pp?3 z`y@m&q*OiycAXakTQjJTIL)fb!@$7B&T)=)I@}%Sp(afSrS=P;n677FV_-7@Wx$K9 z#XJlQA`u*ySyg!%7(_3E+;at-;6-ymVR#jsNJU*hCB-#xG84TGDp9V3BTCcVh zqg=EAl*n#^gIe?fC{%8NLs1lTmp8|4aKMNA^@bqleq~(+5(3@1!Uv8{w&T(a3>+M6;BsIOsCE#Bu-AhMeF-p| zi;Y8*&5(})n%%Y7K-ryv8=T#>!73Ob*;b#ig&A`1E6a;2q4kLFVNV7Q` zs2E}5u2EuO;III5m>JkYK*gLTn=Ky$1D6bkE!!nN1_qv-l57SJJ2p^aWvJ(N1C>?w zYzd4E30TI1D6CxDBEJVJHjCDfS42xHVNvE2(V^0 zhzsi@!8Wopu&o3YVNqHsyI)RZRj*W*26jG@QpmrP^ zsJs_sV7m{>3<+%O`572QWH^%8j06}MM7uy~B^ey%qDde>r+~vr6x3qiNCjIUS}zG| zU!{SAKooS;Jx4m&6AWx`K}Ajm+Z&L3I5@J{k^~qSxUYhY%m$|u25w7GRI+7&Dtor$po~<-RwBT_!1f;0x~OLZU0wsOmR}1nFz|u14XA;{2jVht zvVbh*GT>-sQxs%i;K?jv;An#cArCk_+rbD1_lvs(A6ItOW1^j7#JkD)j-Zz#wH=e zz#zlG$+Cw7)UN#iCZ#w*>?|-jj~B!?1e3=E>Oq_+kS~})vAKe+2E;xNYDDjcq*G;3 z(mDxdb8&H8W$OjGDL1i#f#VuDRWtD9X67+)TnBTQxXVE0*$psTZHLY}{U; zly-~F3{6N$w42Du4(ld@e9ZyoFmi8T zW?Bc{wl%1 zz*z<6FmlhE&b8OTf${ou@4W_U^|m4m44lniDL(ExSq28q7BGjOfvrc9fq}D?(OQ^+ zfgR-3zo3E`+J|BlV_@Kv1h;?Lq(N4BGK-2ZFo=PQR!tFDxPStOL0E??BT0mTK?rm` zA6F(Qm>7gKWf>T_vZ5Fx85mfEoFy0-xUxZNID{60I!rkrjT#VJi$JjovQ>_OmM=28f{(LA8G)h|MGvHr;cdfwk>rIR*xV?tVD!FLF#)zz7-X^J^kQ51M&J~DFz0veo$n~2?>GN z6F{Dn7Xmd?xh9%3GcYI!b%Jc34ASNxlqAl;z%>QrI7gu%P%C0ONW5NXkvszf*9;K5 zLFk$kLYMd%dBvvU-N?}>#mFbG`*1Y zv6+MnK!)rBu~~#bmzHqt2C>-~Snh!8g1t*YLuH$p7#O(DfI^OC9w*2ALNHGJ=N@6eC!(j3BK{-2Ye^raK=r5Ryp+jVnC_ zr66%|)|0%$$R)=Jx_5}%WqRR31L1m51ha7e21SB8SmF+MJSYQcFse#2Fg)OX0!kg4 zjG)kbBDDZyy$&NNx3Vxwg@Iy1ml4#|;9!(80Hr%UFpq~(Y7;2N^cg|78VN8;^(rth za2bJJAi^lc$jQLKWz6_ejDbP4o>9sbl<-X%L1SVPj8bKwI51=UF9y2URjLJKp(W!i zF$M+=MyWKAE3LsEPGOW%26ad5z`RsODbV%BT=tCX#TgjV7^N~nj&T56n9eBG$jrdN z<;WN*&cKktC^Zd~3Y-|fh%qpfFivkeWFS@#V%IQA9S23NJENf_14AvNRK6ku1D6*g zmpB8%4MwS}peXWYd@IbraEp^LGj}#2^|XJWMG>Fa)J-z zZgB<%mMfrUgKmT*0|WbN1_p)s!2`50v;Gcqu6M}ZQj8l%h;P6h_0y8zU3(q)thp3Zp0K#lS9bd4hha`kIL6(^{iU;+uM2)ThYOaX~65CZq;r-8(m2+fjaVBnq(5Q=UIbGAL#7@St=x-25)zCupng5~Qc$;E zhEZlOr~+OIl2Krk;g@A#;070PDvUDhpmy^597YBPEk+qo8;g4*sI6wiD6<6=$(ulZ zgCs^7P`93YAE;kb#3%#m{d4aJja(En$_RpdcmNc8(IucX$-u(Ez-}bNzyQMFcwl1S zWC4xlvP=LeJ-kB-H2%zeB?S~2|3T4x6_k4!gg^r)+&4i9jfH_l9uz3IoMjjogiE;Z zY?&^1%s{3dbiF9|W6*dehY&c`JOSBT0Io{7pM%(i3@lclV1Ahoiqk?+lzs#y9BC1L z?#~nD7#M_FLCN_GC@2_&UW3MVe}Y1f1zgc`{|2R86(LYX%l!w$Ruj4cN-lpvY>nwV zj~Vbvsmd`haQ_Dh=y3l7xsrhq#L?r{oBrUKfkOR$83qOu?(?8PW(608rreuABbi*_ zQo@>hH7FE#z$KdvH|QWkZeDPi=fEuh>fP~yWn8!oKuL`sEaSml28wgJC76BKHA>0}Q3=F>9qKqJqmT-eAXKpdD<0`m8wKKOkm{Y}F015*M#_4hl z3^h`0peT@J{KUe*@P|+8Hz==3F@lD3+4-ebPCs+pK)T)!WTPC|{e1jVk|4*(gUdC3 zeyJW%m7oab3GhpS>Tzx@Fi((QY9S~mXoGn|{8DHuMVOy~lLeFj*tf_qFf0dk zi9q>Qo`Ee1WViw2DH#R^Hcn8gb!4p202Rj$+>03vLGFG83Z*4r?=x_-fztm{Fo%Wv z!}Pur2FCS)pdp!cV8w#m2SA+lV2(PZHQ^`^EgwZ0*cd@$q8l0agDSBM?yZcx3gB)^ zHUsxIMo`LU;Qk=Oz`(s7%n{%=0r_UYyNm~U85qR5Pk=mn4;%s#3~XGWLhk{iqyhs2+a!?I z*I=!Z7L42<8P_N=FmQv$x4A!o*$munpiutIxJd~#gs~Cix-X2Nb`S^mM^I}23ib#O z_j!=7zA^4l0`;HV>Os8k;3O#no?+qs0p`eo+Y#J9!QM~+&#-X+Vg!|BYTTbd$@4d3 z4I=}CCii1d_WlEQm?ig4kZ<|G(->CVPe4u(08eAsaDM{1Uyun@57lymt05uq6oS@N z?mwU+RsqbL#$5#pWkv9;$aHQ_P(iE)=FH&!F+KLQfg00cf$4MfZ6xYJ!srJe35r)MFlRA$A;?AcVCOC2ehsP^9l+Ku15f>MJA$Wv zmUFKGxz!1*X9f2zQ0jCCb5?S%1m!_5ri}^=^$e?cl5$cRxP6&G31N*?GAQ)@nC^)& zFz7H!$$_$27}#(VMkxkRutb4*rl8^(l=?YYHp?+U=8aB(28lpfkBNcpDk!RAnD&C& zNuk{7OghR84B!!A?o1|M(AGHa*`QROtps+FBeychOF3Ypow%=ol20zv5=I6FXYM!C z_nt9O^uGd{H#`o~1DQ7BGUA@Wv<+nHVNkfw1hW~qZ9(Z^789sDE64p6WX^1GIB9UZ zgCck?n4`sQJze*#fn+_ngjvXBq0GQwz zlo=SfIJlQFeFIso3@Y=NgV_w+t3mO#0_+9Qz{yNd7dQ-50I@8FQVT&1j$cek(_f!8P^$k03ZZ{Y z|JfKA+*qVegLwa$($yIlJXoY+K#|MBoU6{j;KL%-3!2$sWv*3cV0gkJ)d9+2Y~bGK z9~P-#P`YFX^Zv3(se_!v!)yUMW0h5EIU555w-7U^%~!!D^%+zhiGb&lLO7&a>p?*; z$_y%o!Z@TrBYNCoV97WRDbOe$w>a3)1P-aCAS)!8K|Sjv4k>X^!j%E5EaH&b0+N#j z^GZ0RK7x44%%CE>fISIhHDc~nXJA+(E~O|G!oa|7!n|0W zfnkfd)B;c}n=*qc+a2Ok1t6!HF@q}p8{$%+tG~I;!Mr=-QmmkGvH2U>Zy;Si6%>|UU^lTyNX-Q$J#Vl_RV1VuK;^0rSi72p6f-EC zeVJFPGcagKNNon?ML*`9AfA*|I7p>GGpJO2p)6$y%5VY9C)F7k-Y83nfYL({GpJGX zL0M`iD5(T9gNm|m%2KA__z4AD@l#nU8&u?mfqB1_r9cyV+~Hu}Z)K_Hpiqwh`}2>o z)FM!Rj|B7nDoa^_!XSzn)OBG{kvag1yJ)Z+kBZbkke6b>JYE&4a*z$NV3h(YQU}@U z85p<|n9r*-FvzGdu!CC9ptK2Zv(4vVU| zd6aI@@&r&J#W)9aH=TR|17o)-^imoH17-#W#$J%P;&agaci)uhr!E>O`Yr}tLOBr> z@Jtf}lpPot7(h2%RB13UC}n14Gce8stxqWe9efJv9x%=X^@t~eECRLf7@nIkFsKFV_?{*G5z9I1JUWemkfj%k55m$WFX29Rxkmo;2%`MtV;$;&Y*sxRv_rY@Jk@$ zK+BUE=TvGkFetnLU0{0!zP|1^EoL z%b(Mnf#H`X1A{ta6lfi%8fedvh&cm;^z?O?4P>~%&VhIkV#ce>24akf(;2TA2-|9F zLtOD1ZeOC;G>cv1F(R~5B@W=<;a0G=YJ19-eNzq|o&@%-^z7M$7(8I{U zpbrk=Kt_-=3_#Nvj6sYLcQ_b=)|i**Ffg!!7AG($gSMY;V_;wq)?r{UXyjmEV2lE< zW?`D>q7ROoXvW2$Hj^r7*A6Hw)F5HOz;I6+5*}4o4TPPw%o!M%bU=X^&FG-c7{fHt zL7g#{(O8`^j%lI`gZ4)T28K{AkbD$~&!7sr=of4p=x_y46h%$HaMi#v9qdzZ#~kEH za1N1RFamkfSciv!ff2loqzs${K$pUq6fiJGfbsxi5F`OagZ!)r_DBq9RSwfc2h5;< zsWUxrLx~a(gBs|D0Fc{xb*C3Ru#yZ=1;sunk!pkD0mJ|$i-`^l492dYj8q8_kuBRHY6XJnKLj<(S-y=5d(uN=;$|)H4Mgi zpscb9WIkx$1LGV$Jq89-a8}*~8dPHp0{L|l*s5Si7TN;xE2gcydecANH4vM=>bikY zJ;**4J+OU{7-vugZ4!A6I_=vGd|NoAKL)bb2pp^%^cWcQz){b|2+Ej07#SGM3%D2< z7`ed1WsJcF4?&m7@_^f=OcMjtKvgg(8Bc-O!&Jne&KS)!F+iO$hLh2ZK^qj;PSag( z80at_onCmuKtv8~ygb-=#$d~$5(Y*^aI#**#K2(SHhu9814Y@Z`mjW*3OW!FoLE2^ z7nE31ra!!4V8jZFx&G-AHx1MjK=!ZG2m6z0q6gT1P&#BZX3z#LEY_PIchf-37Gx$k zO^GuY9o1)Guv!he4jR;oW?*Oo`+lMU1A{qe=##Mq;@co|a2(Vy_D$b-(?CQXoVDt} zSqn4hV+|k?{`01RFsqX}14G$#!CM9*Mxb&+6SR6*oiU2h0OUGQ@-piJ-JZMv91NiF zuLZjx(U5^bZ^!iTTL#*i;BZ<3Rxq2HfdQO(3k_l6q6R9uK^_+~oWA;&ffS^y0-av| z$qeF-r?(8W>p>d8o|a`W0vT>oDa63QcmN#WAZzQu);1b}tQ7>yfa-vC%nS_XdZ1`O z011d-^9>MLP%DEm!~pEJ!(g{DhJsxNx}OY^$kaf0z=4ADts#RntYlRMITsv_pbP|x zM&0QTZ&`^=KXBVXCehoRfk6$lJ15MXfx*iN5|gD23~Hd`ra^fj1ug~(zaj<(ZP2nu zP#}Y{C^*eAm#$${XN+MqgVv@X2Z4RA#9-7o-S&=wB$KG|^oTnKig94qKLNYmnuUQu zjfa7OA<3M9;SO) zGBD^(oqqj}fjr~>>EG`d$h(7c3nOHK*2Dm7c3uVsMh+%W)-qv*#_3j5Se#ma7XV$8 z#I(zlfgy;MfdQVmPE3!zYak^Fa^oGidl=L}#V5#(f2L2kYak7&LK>h|h_MMI6`a3o zAj}62_;pa3s_7r@8dzH7nKLjmL;@0~V3`jL3=AN< z&P`9eXCUJbV!neaD%#2fij`spNbswvGD4Jst}#<*jABNUS2bs3fV3?F7$I#7S5t^v zAKo(%hNNTAxC1O5i`+MGs0RfSI5u?{j6lK6$pUJs*)9a7Q3obaO6~`z2^&zv zNArRL2Xtg4D93qEe{kPG3Y^8Wr~kiiAPr{rOqYLPAX5)Y8rr?kz=9=CP{LubO9qV$ zoM75##=yY#9}JA_7#SGs3_ue(Cz-B+#6dn`U;vBTD}V;2a+pEQLI==9EC{puI50{u zFn};?g5wJw1_lu3*~a9ctH{8h3p${I_q79?A_D^m^S*NMVPaqaVLmZOaS;Xv5N1Ef z=%~fbzyQKLPnn#WSs55W*nvl!fdPd1gB>@@F))BI_j6`Pe+~u)5a#~F>^M=Ffnnly zxrYXiWqA@)%HmTJOA_OAQuC%?bT3t!ey_|XX1e_?JDKTcL`=lCZ}@MpjA?qigo)0y z4n2YCvn(y-w=ZEbe4@-`XgYo3<0xS!bA#!Pw!Xs57G{<(hWYfywWT6VW@gg^Gn$@G zUpGxoV7lB*C4=p38iu=BnaoY5|6gt(HT|xxA&<5NLwtN%XNfI;($EX7d`Rl9<3^4ZB=}Q9)t$FR( z5JKM5&(07KSIt8bszzdWBC)4VR}@nhXFNOIG0;$4@&%I27bG^r^uj2^VeO4Chd2^gp*gW7jcU*;pR ztC864(+g(_h=(pf655Nz{)ohu=0vy>v@RFsdQcAz#-56#X5n<(*#e+z=`Di|^(DU| z$uNQPFw|iJ(;I^gl_l+wgnW?LQPcMZ8^%kXLK3=;#C|$GaE^fZ^a`c`9$pb{g!`1H zr-m3RgU3W+PK!g5&Ou^VAhCOq*t3w>E0EZGk=UT=J(&65ki?lmZC4%8>Inu01_1~M zoZ953ONJUM*ZU#~MIo^>kl3|I>@Fns3?%kiBsOS`I?OFck;FlZUtr>QA>yFPUj~Mk z5DwT~Uy<0LtBGM6ctN!nG^Qkx*q|~Krp5?KJOYVbiNv0d#NNgW>IFg#J%l82ZhByt zp|zwqA0i%Akl04kmxdWCOC}--|;pm%Sh~pNbGM&Y$i~x54DRA!iL0&6odng z6E!5ZF%sJYi5-f>22H%e;-n5qybFmv4T-%7iM?9@bd4L-MaPjOlt2|LRNNei4Vnyt zSr$EgWrSg{;T0t5he&LBQ2P^Vgfg$TvKSGlEhs5R*L8LL-t|vLhPWXA~cjlk=V*eY(pfrJrdg&i5-o^&O~CDBe7c{Y)}L;Fo4z!L4Cxq z5F!Ci%%BCsF!8-e;-`_=H<8%Sk=URGZZN&fpixAq#{`ksPLiObxS^dZN z7ZQ6K5_=I6d)@TEafbWrYo!pGsSAm{4vBpTiG2=<4cc}GbNe$S@lQzXe@JXD(9i_b z8)6VPBw&>w9B^RjA+fEH*ltMdAS8Ai5<3ftU53PNLSpwJv1dt7-<4n(SI;Da2n2p4 zwj~nV2Zqi7hkzZ=&Jp`X5L_pfx=(qd^zo!q|$SQ5>id`bcbBB(^saI}(YVj>IlS zVmCwBpn)$22GAT8%(5*I39!FUBC)R_u^&&bO*T}X?y)kOhgU@&5m`>t53YQo zJp<}sLv`Go{x;Pxn=yL2ZT*e{XTf05XnDhQ)>kl2<;Y1h*=}Hpk17xTS(Ly7=)p0P7MYIM$m*40|Nsehz-r4 zl1OYdB(@ER4OQ<5VnfyY`+_)7LxVLS7J%jw(?H@-4cQ*guij|3Pf1IpUg#P?rU1gKr8?eHcg*>XHNy8#G4Fz`&5A1zNZW(Nqo+hq}B5#D=PGM`BL} zv7vhBA+fiB*ic{WMPeU=up#kt2E>7CevQQbg2d+1MjVR;x|kKT6$a!y86_Q}VHHZzp`MLqbh8o%e zwE#5f+6xkgnllH9y#mArsRzZ+Mi_^If#Eoa%{qOX48L6ceGnU@hyir`0|Nsilr5rz zV9O%0jX`W^P}?A}U6I&+AU4#|(I7U|%qkEY>d*!dTM(LcT67o~gh3NMpz9k!5>Q1; zk=UC-Y^a(&NbE}>Hq=44k=Rd=*snlrs9ru@1_nkbTU-|uHBgQQNCIlH9*8XjiAy70 z(3TGf+ZH4aRpSL>L)8Q$u`@wzsDp}-*wskvMi3jM7jy-}R2YYWfnh#~4Ygn?hz(to zu@dA6D0>S?9IECF68k!c4OR01%%1Ki$FEh-r^mp+2o;wHv7x1!Du@jg*9WnoW?F&R zA`lPT=`k<}L)o4naj2RQ5F46~BSCDacsdfh48#_JM)6b#2W;v_5F4st4~Pv)pbQKQ z2SAoV+1EhgPz!E@*iiMKL2Rh_4-gwF&aRIrqQ#Kd3i_ZZ1}zE(tqK82KrPTiV!MFY z&?xgoVuvBI<3VhwIjJBv)SL-O?Da_O+aNZ`aiG%Y5r_j?EyKXT@Jye9K^V&Z2oeV= zVqjqSkHi);K-9LDE@1XOc561xG3Jqg5y zS~eHNhF+_@(13wK7|LD)5{IhU4q`*2V-JW86~7E(L&WPDZh$yYiN_!|M1tW3hz%A0 z1Y&~@V`pGs_zq%2EfY6{%uj(5jsgU9g2eU(v6VpK54uJH#DQAY1Y%2p zjAUSFGh|>8hO#Gu#Gz{DfY?xnE(Ecm;_H#vdy&|uk=R#3Y(2aYca!&F_hMnr-Rr~@f;8vDqam?L!!D3#DOa62C<=v zrh?d@9a z5yXaS&O%}rBe82hY^Vngg4obtI{{+LLp*cFlz~AQ%DxT~hpKr5VrxLFfaf3%RN@ne z4GnV!Gelv>3SvXmh=ABoLv@kZK1l2wBz7+ndm0jZjTzD)<`Iwt)Pg(H9V-mQJ>MV+ zeMVw`M`Hg&Vl$Z|sv0gNHsADx6^7#Vl1M@dNNg1(wl)%5ABk;_#I{CaJ0r2(k=Q;+ z>;MSc2^=Hg5Du6fjl@nyVy7dq^O4xa+ifci4=XU5OlO>B=+8K1dLW3pFnuA2%9;KV zL_L}AINK0(O5j8g^3=E)!MDYv^45HH=WwWHG zd(1V|V62#4IM)z#vf@Dy6*FCMo+0=UM-Vk-`o?*N?-^fAUpU_obfVoy5Vd5w;{rp_ zS#uLX)Q9O0LDYijh6@e-87rnYE;RIK5?MC=(n3Q&#s||C7a969$t<5okPk*t5NMZ{TUOs2QD!bXJpb@KRs)yp%!m7^!ip%5Hn6UTq7yY`ePFVgTnN^OAVD7 z4^Mx%)KHyuh7SY7`{|9}M1`j-EHe~fl6W}XXqllJYkLp_!;I;PdW^!;3qax=uctSG z#N~q-7&;*02bLKMFix3%ahahy>+)a*hIP{&{}%~Q7g%m6z$Ef+y3%q(HP+Br28IRG zeU}?5Gk%?3xZF^k)u4fa!2)8yhUJC=j2Y7pE;m$XlK46O)pA2M#uw8CR~V`@-k5F) zq8g?rf~bJ$ognJN^o=VFwb&qs+D$(gz$M9KU@`rJ8KVYM#nI`%=7vdacUWoIqfpP{ z!vNZn20CwyaUN*#{%z3yEOiD3(0Wc#aDXrq3u|Ux2?H|=`yPGpS$95?3=Ay2`V0*4 zv+i0zBD+D0T0xfwGB7i8IDt;4V`2?6U|?WT?>g98H-?D#uLUGVXD z%9@~a?^ut5Pr+knkc1w8rzj6PmySa~fq{W#hByNQGvxTYBh$N287lCA##fqhvf;ffC_OA!&(*w2BAXG8dRYFoeXk85lT)#6ertgf@cqtq5s=4ki&g&cwjLD|AGS zfq_rxf*b<_zfdSM1A~B2f*u2dpb)Rrbjx#wGK`kf!_FD%xha9pILHU>S7Z|55(OOz z2U;n{!oYG^i-Ccoa4`!51B;Y2{5(E0&~Xs0A6Xa}`2VmlFbLcRoe{~BG5ypzL#cXg z70`Knpcvw0xxm7}AO`W|T*d%41_q&xpl-C#LeLDl&_*GUClB+3JPBIr$RadX739fQ zO^_!+hjOtC#e&Y(5IUj@@+4@Ki%aOD7HDrvl@bF3kC2K2$dkuq{F}fVPH@bik4{PaKaMMv36@f`x*_H z4uB4}<2wRMnucHwGXvXdP&^nhfkKK4bY9^i(EgGK)59+qT4`i}j`V?^SIBn@6dBO- z3i)P(Ha9`fE95&medh&3HQP=#_<4mqpz{iUuro05B^V&iE9Cp2jX1B65A3E$uroOL zzD}39XejBl3KWsh0}J`I6%hv(^7(?!wuxf`nJK`RssTFa2E5ryg0COsltiY3paTo} zW=$`@XsA{XTA2qsu#j&C=)5lIfrWgnLg)t;a)1sb0q^NxU=szMK$6KM$IigO13IuU z2XqKrF38mdOdxd(d|se)A)yBr@_{A}VFwoSRfFOkWV9E+K@a4<0NAK_qN5C9XPoWsD$0&*b_2gezv`rjZU^FZf$Ko2bBdj&d526|v2 zBp%=g79It;?gG;(kooU)85lUA2NvD{9j(R<-i5>iIbet7v$eBZenVl0fp8Y_F zfq?^hU?HD8=&Ttj<~xj_6KwcETLU_5mp|| zAa8Sj0i{|`W{|tNc|aC;F@v1Jz}5{)4&Ka(Tnr3spxJwl0OtK%3=I6B^>_jxf`L<< z1!N5y6DY?Dv)Vt{SrH>ak{WGcfSiVQOYzTLCH#ELgi>`c_OY*kUDFuL5#D z^fW^^P*Q-NW;hQd4n58AH7MmlPBY{Ioo1-a!@$6|9dt}YHRNPCz5}2pbDWj({qz`)Mu2`bO(SV6n3Ir#R0P9B1vW_XPWlr$SyZ*Vg(@PJM;%!Qi^JD|ZL!NO3_ zz{$4&45B?!^*8+w`{ME63lZm8x(5Y2pspu!M-n&D+oy|RSWk(YsijSW=cKu$B{0i9;J8)j-f z2k1CMP~nlI%D}*}nYA0FoPiB=UM|NL*6AQ;fKD?6C4W9}p}2z;TqyE_PcsBHKp1(! zrx}8nf(&c{pb}&^E9ht;9?)rqpwsUlX=Oh&t$-_<15o$ZgQMag!~+a$cR?X}h?N0! z1|8@$L(s8y5Z%zz3?aTh0o4uGd=jD=;<{5{*Lg9pT>up)r&&SA+VOx+GhEFFOS90^ z4EaFk$aB<#k23_FW>^i%_!n8h=hcBuGqeP4OI-zW&lOfsg6CcZO1xKDL5Y-mg+2oV z$2C?^GUK)ZrTy!yporr31ZCqJte`08<^(0Oo2;Oq=AH@)+*_=mP~-+3(!z0@6%;Vs z6G6H-?y!RV$qjbUT~?4w8Q6A$!toyKcF=*(u^>|)vj*}*3kT2vbON9Sw*nv*11Af} zt!#pzgZZAZmh&?(@b~b;iVsjhBLE^8*#2rVFmSwModHq+I?fAJv`i1aX(&|h2`bRO zvhD-PoCIkFM=_fms9uMjaHs;RPM{|ot_4-`65#X3ct9r{x`K{)0~Y~WY@i~50a64& zPdJ1W0Xl4;m7Yv|XFwSTdcq-}6sUmJW2?Uk>ZkC5_Q`VSvw=9Q3~Y-)m6QS7TToLL zbi!dj$dVO9#ad^n^pcNKm9hPdJ2F0zKi7F9=k@!cRE72MQi%w%H(aK_?t4 zgASGh9c2wW;gC-cRI+%mfh=KxnB)m|y9fi@M37NlY@a}y!6zK%3c_6F2iCyAn}T%0 zA;fCv35O7);3phffZP$prVlzv4|KxecDOsBCmcddf}U^)(F{G|5aPo6NU)9U3~XMY z*ok7R1Q`W7;ShB09WVGqzF4pl2EH|*bP&f@2|D4BZ$GH0i-(kQ;N^K&PQ|flfF) z2XY8FD;KbV(kdj&LQXj3p2*7pKH(6QzPLldH67b?W(Ecc=n024p!qGfH=xW_#nu5j z2LN>X6GuJUGa+bp{0}=z{vu#lm~ReA!suuFXV(nP(omUgl9WAJOy}R zCme#L6d2feL6uAw8>=t_1D63u4_gvw5BCz#Sq!~wAcG_zCme!QGq5cI9oN^-<|xd- zz!nQ?P)=d15@ulF?-FKU0OxrD5Q~A61!M{j=!8Qi&P7e4x`H zIF_)fi7+ro@I3-0pk-`2B9IdfFK~g*p<>|%k)S3GCkv=;!pQ+meB7YG zfF6y=w-%H{Z?QFjLWY5DJ}8~sX6pluIe-?$ay(%BD8j(N&n*focR{We0ClIq5y8Mx zHhup+Ls8xkke4B+A~J|fe|XPOLg9rd0|TFm4C2&6J_{8F_^E|_ucu4iH*{cBnI3iD zP|c+ZbWkDm)Iz>#TF9ps+Npw1Ep!4MsShgfSwJU5LOW6?G#D5-Bf&iwwnNj8+&5H~ z+z&eB5ORn-8>k=8nFl^jgDrO214D7i!=elfoRIz!TQF#R0n%M!+cVwZfuVT)QP3%k zHDC=qLY#F>I^qlre4yhfIO~}lKqtWSJp`Tk*udl?#=yYDmjpT%vXLnQbSxcTCCKO| zrWDYf1AKR-K&LQ*IqZB@ASbmj6@VPhSIq+Q4pR;2R5iX;px|i(b9ne}fu?6T+nGAV z7#R5YKr{249ZaAd!2%3yAS*aKnHGq_5)fxMQ-nAJgHXcspAQVx>RUi;PS7%AAu(o9 zGHO;}U|?ooQ&D1I;G6*opfEKC2F}?`bHo`K_;-slFbK$qF)#>#Oc5{vu|Soh0BD?x zfs72Rt&A7m5QVyj@H)K*9o?dzgeJr#C(_l;ztFiopHg zZGiAflw<`~H7mzjD%;$om9Kd(U8pmn*NSD9i# zN6@fM1?8-3Oqr4l3_K;AH<)y!7#R4zf?RTw2{c5>z!wM#y<7EQ84kWDpk#QP$wrES zL4$84D1Y2x3X)=A@Zg&Q^3q+frVPF;kg@l`38R3o4dlT4U``rsimm<>D0e?#Iu3FuKj#ak`5=daMjJU_f`?EbT`SI4 z;LVqeeDgrAehqdFI|Ex0=n#!JOnFia3_Km2@0ggS85sC3gTnAVRI|S#0|Vy=up1fq zK7vZ#k6=|Sd@=$I44j|p!C}q8cNrAGpP4wNK?OQ!>lx=4CXhQt7&uu#PU2)a2ujSVXLpL1&*fOjmqrC}uGM)HMbLkQ@U`2?qlMS1!mr(HmU#FJu@P zM2>>aWQ3e`Dk2VQUO>(|71=O7|EZyMJ!laQ7v!u{Nyu5Jpy37~Nyu5J=AxjrA3H%c zYB#9aA|kR{n}LA~a@MIxls*FkS1%~Tiiy~Oj*RRBB}H+OYBdH1u6|H?E+_I-m4Sf^ za`>r8As+(+*Tf~D!%s!{K~91oD^1Isl@(CMdqvJ4FTa zTY{uOr=LQkL~XcMu90P65V->i>Q$g{Vh{-f9ry$}{8U5~6nEgW0og^mKv4%d{8XfX zongBAb3^`mkZu7HV?722t__<&CP~82JQdjn8k^n(@*n8TQ)W<6!UA#|3uqxB*JhAg zL^-&&{{d-x4GI^?k*6XyAYbhS)uK!ypygp)kRwk;u7e^FcI4?rPz|wH=CCXS1B)-{ zV9zt4*kqXi3I@oTr;n#!d~PUNUns}Gz~=~x8dgRSn}P3-Gy?+{^vqK}Cy>R^Gf(+; z>41)g0?$*x&ped}Dd1!@mIDn}aB(vp1epiQxLnXPPx&N4x}ayCg1fD-Gf(-Ja4<~I zd|@b54_e30whokVAZMORfzLd(RbXJ?n+=L>$nkj$eDk>(7`RjzL6OYD#|lbY>Wm;& zclban47oHIofQ}u9`J#-IB;n)f`aymG-xjYmky&eC>1bD?*xr;!45!`4i#r$;L>9h z1JxrujM5>Xl%UV(sldP>z$pEEy1+|Akr;M41_n_^X?IZ4H)RCPY)CLl2Z7?ij8Rq& zbmXZtXzK!(CF2fR(2=Lo$)E%RJMvW86O`3qN1jU02AN{dcvcQ{(1z}06O$k`Xnf` zdNFFqfet;D76GL-Z^kd8&_hpGfT}wdanK3VEb7t>4D6r?iU+j@K_v?(1Ka(2P$2j) z-jritU{M6sCc0$`(326`VCozgWI(5$ZdGJp5K#pky5fP7`TH$V@y0Epz&w!kQa;$4E(a7WzC>tQKwIOWhhiXTbqG_8+sI~ z>=k{`QK%r>_!wntKr?92qfll4fKI}K9)&6kN@lR5P-Uw@lRR;tRIbS=TMX(U#DmHU zEk;>3&>3dwAQ^2&*@IGu(@|wXBfH!Mpn+W$T}Ign)74)asxcmz?)TbIuKqNr?+gkf z`0=PFAdggn!bApiJSwQH7KzXV9ghlPGKlblT;1jXnky7p3<}5&P;wLyi3aKG0;NU~ zkvAascZ0-DM9M+xdqLtBBB0~yx%)uk5h9?AX1MDofFxo>-hfW1nh27p5dn38xF>_e z8$_BwBQaAz;tNF9fY{SO;!8w$H9*Isg2a!A+yr@i7D)Vrhyf@RXM@CFi2MMZ>^2WH z{{BV;bl(8?e31ATkvfoFi$Lms$krP(GB9v221!UT%7TWcxR-+BP=--<3g|qql^_`f zMp<>xv=g`pRAH302OYcxJswpS)IsCk2@bRei;NwxBfsRKFP-b8NVQ{$)Ivy1?xyI52isHl96d4#q zdAP4MDKjvLoCMu*1vws71T?k?KOVJHoq>V-R-!TkgJ=o&9ne{IBJQ9g_KO-i86vbQNjnRpJ4}}@_{O7$N{MJ z3{`wCAP-6~ZdGMqsF9uu3QS2xHg?bnsM0y0!}p{ZLGwfG{L-L}P~0-$iEb`_X=P9t z%Yu14{L&&IXTXj{l@533sq_QKbz) zDM<%>EDiWvR8Y*bgQD~(sGAJRu<{ISks#9z7+-)+CG3%AVBmIS1daajfR07=2hIKd z00rF=@Ijjld~-l&)IyI%<>LUw^)j#w2X8@f?)1a&4OQx|gObHMMvz`Xz6#Jmi|fH0 z=qai3paB<<-J%R^^`P_SHZp?tvhaXTN!3E#?tS2pjQ|g1aqkCnqQC=L+y}rR83P_4 zgB_g8=M9QP=)tLcpF!F7Fj!eUA82@v`zYAU34C6l;vIgL>UWS+k2BV1t1&R}G;p6} zJgm;Zz-I)?1gF3!J2CM6lqlt`LsZ8xyJ|!PYDJ#(2)V$ z4;anW85r0~Kq&-r=BgC<%+*tx3=Dh~pd9y!5yWQTI|GWq&x{u|85mgjSU@E&^vqSh z$DsTLJ#&?BKFIgq7_Vu9Iso9B4t(Tl8iNdYmKb*CD!3g3J98C0{LcN05mY>?@p*uf z8}!UoJ_Ar~^9Sr3OFlMGod7*^l`k3O1OX<{OsoyxACUV6nYK>%{A4IE4O(o+4Lwt(WT?g@ATfR3MJtII&=d=|ITNTLT>zem;kIA`6{HLKazQ0O^kh{& zT~NeBPgdnS4Jsy}C#&-H8!#|%Lr+%a1ILLQheB1{!h)Wfmp| zw&S3{k72qET51G3Mb%4-fdM=d#huBN4O&3Jz_&z%fq^?4+>vwS+YjPEPf_J_1|^7G zrY)dTRQbH8KmKf}SpNyMNa8L?6=ZOR2Xu<+6_BZ*Q^UAtGJ)6(e4xt(xMwkehQ8$Z zK$pyL&jybyXz-l}#S-)sRX%Z$^X7qNbofB02XW5_bM*MYWz<3@(C!xlJ`GUg1$?k- zJ%b?wJIK^0pg}XJCqdg>xfe4fX@N!$xR)`BXfrVIfo_`PUJhn6@UepyG$2k^eJaAh zz~&1o!&WkV&|+X<(*;Eo_AX9jl!$5mMSfzh~8iGR1poV1yo3s}wN5f85mF}wt zMF;F;RcX*n0{moEY0&He{A5*WJ5aeG!3-MxOX83|0%}FVPF9tU0?ENnR+R?bFUYOT z3@Y?1IOL!ws~U-bPF9sR2c=CT=GA(jlU1cNq(CQknlK;K1D&iY4H`(}Hf092a(0MI zSAv`dJ6Tn_6r>S$vZ{0tD67CuR+T;jI*k-|vZ}NmD2ZEvj|zP%F1-=tduuT7nYi>4 zkh5*TyyxQ5$!rYMH+(bXt_N*i=7ycVD*XXev_ao?-k z=RsAzJF}WL=qy(0dQejHfJB10^lDJ);0Zo3^`E%3A}G4Nz+PjKkbVPlFzkR<=>zqk zs>KJaQB6X6CFnd|U*_X_pc7i9*MqXTAMpY7#P?=`4W`6p~CD^+6)Y!gaYI5)?;7*VK5(bLTfB&w1@>% zX0e0HF;EzR<=7e6L4u%gf$}+7viYGMr@x>%AW-gSVPLxlDjSoS9gIMyfG!2?iw*^i zf`S%O@`Fzz1MOB(C@x`O42Os-<{B_CFy@04bbu8+*Jof*+B5z84?|fO&^R1pK4`?2 zF+{Z}HI0F>05s&r7^-3b+FD%z8d+luQvwa-F&2Ub-au=H)j(I7FZX6(P|syxVAwQW z@Ry<3^t_*jI$|?G=h}3EtOAXQFwOz(5mCA_eZx;fWjhd?F+}Aa=rE1$86Y=7E$N;I z;y^9wSz^GzaEO6{L9K>?fdOpE0+=PHh9HM>vVdI3$pUg3Ckx0;nr@&?-OE6&Xpq$= zU|&80EiBtTz5JJpPgbhl6U`fVsH4%XZTR=^knx@dr5uQvn3lj(K84P~8Ac!N6q zQB0)_8jR6QMGP8{g9UY5Kmj`o+)M?T3W`m}Ir~7SHh|7dn#BkjnZC@#z@QsA{oZdw zSy!+vbD_2vo(7G^&jV}sWoBS70G;f5(VKyx#Ry_uNudT~G@}8?HhTsG7X}8fn-))Z z_+uzl4^pVX7{ycqauZAugHai1-&i9PEL5Es85kJnn42&#=Tmlng zWH8tQ3QQvghJDi${u+w%gOZy810w?i$S`J;>58iZM5o{Ks^Xo#?608+7f4!N2P6$i z^0)pP3aDNLdG0UBoGDD85OB6&U{LCoVqjqWtHjE{aG!;NLEB+E|35<+g356_iDsr`|GBU2i!lau6eRm>>~%aq2`PvFQnnMjDU^ z4TFmFSxjG8S0y%mEu)b%qwe&Rj7Em_puhl^w^9ripqSJ73Ch0v7$HR`1H&qCS(0K2 zOV#@rL331-*%%mfc|k`a>}S*vV_?_<;)4ol#siEXwO82~7z~R+J4p{QW?3>YXs|Od z=!4cjGad%tQo%IQL9c*;@d)GeN+u%%1s+QV20ie(*tZx#$CW06wtX9b&aS@Y&A?z_ zIbBx3NRnR-bU-#J+|`$W!hQNjCL{HF(EJW33urb+rwLRj{eZh1bp9>l9BwO^%YT4f z4jTA32D|(x*yW7Dx?p$z0=s)12Lpp1sOtCwHs(AB1A`$rv;GB_FYiEnaB}V$039XA0NP8*04fr5tU<{=ih1IKdRXDf#9_;zb`(}B-2_FGHv_}U z>4vOE`j9lr1WnZsKw@IkTUd>RA&JxgDj{wIDRp+U8VTz?^JZW$vjJPfR17M8nK=G~ z%4j17wRf<50$Oeg%DTlikkl>2W+cH1N;mVS>$4fDK?*I<)#lK8`b}yTpD+U_3uxAl zlLa)d2flyr-SlZ}Mhdp?ZDEmh2pn0U#c7a~ei$5CJ9rrwASvbuII=*Oqe4>lF{by^ zKeHLBNG<~%d~y<8x?kX9V6X%wM9{Y2Nz)D3jU>TN+dbWn-AD!Ev>s3>LCVuf>_#H> z|81d%(Q`8B#Dfk)`V3D`MxX=7=QugSocI~+M9?yMh!eknotVN8N*^K&42)mF>8BOM z2Pg7xU?(pF@xkfoJ2*XoZWz@Cm!dzI#6)!$_D9R9zW>PAmt-UC(qmP9s%_Vi{=4I1Ey($qH)TeV$&= zX`~HFI1x~3EeA-#ImZc0QlJxpLAE49Wmvh4gq1-_s?-6Lq@tNP{xhh}W`Y*fJD{cH zaj5D5E+ai~WPO_6%w?p;25On`IZj{CWh4fPI0a^S+wUotkw`r#aKJ^W76T^>XdYRo z7ZhK`%&@X_2e^fB+65MU#mu0x^p`NKI4EHT6$jEHuoPCx3@Q$6L>L&1!Hv-}W>Axl zG1M3wdF9NY!hkW%7#wvK%xR#qfHB+f|dfr1j$Heyf% z-DdzQpAA4~Zi7@WfU0)kF%o74mBi<#$M6_wfur!>^lly_E#(Lc1_l{tuo;X-pe7$E zo5wI3Fc@58U|;~nwfFQJAcX~%3=ElA6@CS62)6}o5>w@c8h(6w2#5*FO5dh8gP0(b zRHttOF+mOqnf?&O1c^3J7vM9}0>|{4>Gpg^D)pe4)?kc+9I6d+6R6=A!)Ok@sq?lA zG=mB==qR!>Ffcv>hbE{61e%FqoYUwIi{VG$JaAhS7Q>IgF{~%Xz@Qr-%fP_+m>Hzj zAH)Yo+Y?ZDK&4QWD^%Bj~CJa9p{9iXU$VhI_7%m~G-W5(dZYCs%N+fLk*u zuyg>r0{|4Wnr;x)XZc~74O}OCGcY7TWmp7^gu#K@GF?W%NFE&L+on4R80msV?@uoh zFj8RyMS!6DbVmUr4W&h(ohn8Q44Up>i$M+TXhw4e1JE4`pfVxIefkAKBYCzfjG%-8 z(xa}=z{vty76dNAXSg#kSc5u=jE)RCzd*-)Ca}P=9_aLa#yRQJ69tV#R6sXbF($Hr zRwXb7L$Xg2xKG6x0x8Nwf|Zs46c5@xiT+i7cSJz6Zny7tNDcKzSXsQVEjR zCxg3pu!x@mab7q$;-`Tuojy~@ND5Luf-W-v#fkg$gF;5O{9reOA`Fzy8$G9=7dDcZ zt}1LK%nHhD3#YFWHWKFq9lQU|hJoQAggY0Sg+5KM6*kgg1LZX#uj%WBjigv392pp# zr=Jrx(t#AWpP=cb!3&ZCUcwqxA_ZQ^18Z3tzYBkawyZR-r0oZM@!wd?4hjP%7SjPOI9f05~IvhYlXN)Eu=~ z_DYr%^;x!|2$v;R!9H0}U zp-M%j2VOIBmjvA)4bu&})(6IJoxbs!k@EB&$8sLtgGk!WPk#$C^&^tdKO{EKblK}h z%AwX=3=A-nJdoI+_AN|28%ewziQSCE?nh$Jo_>)rK)iknlF&sYHY@0`XsF-xk=Wov zs-fbb`6rn5E0NS}MPeUBVxL7~KZ3BQ>pR$M@`{1F@lZomrYGJoQf3UEZd<1+&X_lS zp@Y5h^aD4HYz*%qsd|mX{)xoq11(X7nj}4)*U?^_(QLZwO(W&$9**`Bj1AKh9qq*v z7b2-zhs554#J-5c{))ur0`=6PHh>R;hO)s2K||R_(|_JHQZ@u11Pv7e9|R3$*B}`& z5s5u-x^7vLc>O^np|eQrn@H@ZNbHYD?7v8CPEbJ)wGz~Lg+-MjlDIAs+X}+=1D6kO z5Du7~gT(GdVsA!bpF(0^Lt;OgZg|_sT2dQSz(L(&fy8#3-g?_eSrRlH4s%`;lJtb> z2SL)HDK(h%O(f~()BoN!5>Mn5L}U*!B(@3?I~a+bfW*#2VmBkP=OVFJO&2^9CtiOG zN$5Ee`zsQg3v|Xa)SsZWk}y{*A&KiDv8|BU?nvwyBz7i*4O-{Mz)%a}fa3+Uj~Qmc zJS1_@T6>uIHYD-$NbK84Y%|cA(ojcxBe9c_*!jZKyY3nVNxnc511;}_*<(CCS1e0h zG6>YUf*KWp#EzT(*418|F>Crnu`F@kawM7N>52D@#HahX*-LnW&y0rZeukum2Q)AY z6&FWhgU^hHit8eYTTH)sZn9Fh>Ir3rKEOC)ht(C{bJ2tg#aED~E2iEWC+c0^+P zBC$cYmNROB4kTe*i)wqJ}}Cz7Xl4@Lfs{g#MVV(gU?`ws_{V* z4?<#t?zM*by9i0V0*PIR#0E{CGiotFOr3}%aR`b17>O-3J@G@KIIk9HdbZp#UUy z91^=2iCvGx?nYuyM`ABVVy{PH@0s5C$jDt%2sF3^b%i_Hod$ zS?fn0nBXMMf>?;XR?kC58WOt*iCu@p?t-yFrS}3Dhk=1%ClVVp;S2NS4J7d=NbCKQpCaZNb}hUrh98YxJIBZ;OUu`8y_J~L8gTt40LnUVPP8GiOWjOV7OJ~Og5 zlmH#V3^h{~i49sh2y-*&K1mqcf4b}&e{tSyB&C(p4eRs8>!%_KEko18{R4^30-C*qnj?V3mO)}`AhAs#Y{)U) z4iFC5uRciZ2qbn261!k}Z=k)nD(I41m>Z`cNiRTRubIB^rBQah0%$xJ>OAln*-&;k zl6V#py9|lljKrRX#9oBNUWdfqg~SG3e#)rD0EyDeND}vu*q@Nt|B%>Rpvf7iL&cET zN=R%yB(~M`kFShQ*NcI=!BB0=NNhtSwmlNt7l{p8mkSHhOeAq|*BWYOE0XwRB=$lG z8*Q|hDHbnoNxM(*mIHC;BkJa#XFJ2 zLF;W{F?|(D{4o;yBN7|5jS{AwR|lz*k_Jr?LM_llVw)qe!KdXy)dVAn=OeLek=Wfx z?3qaHYNNi5f8UU!{#F5ylNNi&ywxcfSkWr`x zei6j*RoB8j&nvB3x7Ld{u>Bo5li2h+PBN&GB=?Zt2#!C`ob#Qu)NW(6G> z3$;KPiLHpl)}J288YeF4jU)s<;1;SaeY&BIs(3vYXzmCqBm!cyf)gEs1n6*AC|e&S z4pn0cVzWckSc23**)AY)s2V>ITMeQn7Kxn%Vnfx`K-i$@W?<-qaKJhygV<2bGeB&p z1q+ebn?Y3Ls_lsz3J4$=!sEsH=Ls0AC4*jqttkRni_0b)ZnUjeZ}i=Y@7 z7@mUIP;o}kF|bheJRmk`1e<|@K>&2*ER-z`5{If$Gh$$nVuV_(jU-_PVyjJ0i?^4n z4+pWK8j?V4sQPpe8)|4P5_<^}dq0Q`)q4uWh92jA4&)#x`zA;ns^$rZ4K@EIhz;xE zd;xKw5X>5%+ zkvtwG0Zr{0NbEu+b}fhv)jV8P9U-Gf!I*vo+Gh8AhB6Mhs;8a<3(c2 zgV<2L8c1wIB(?>J4GTa!5C=3h4!W<@gn>aA%Jv0`Ljxon#D)e)42TUCPXn=`;w4Dz zN)Q{WrUk@?s_6u=q2e=4Kp70mSqzeZD%uWWL&Xn)*iiA~AU0I|5{L~IzYbzU#h)Ru zzap_&KnK@C)d<7bpbRDp;(+FsLCXR_Y^d+Gk=TwPHZ(}Rkl4XU>=+OmYECAI4K-&r z68kI?`hz+%D9TIyx z68lm;hy&Gp8;Si9#D;4Ag~VpIU|@h%xcneCRIeTqI}*f(CbSd~TNG68GcaUWFfa&1 z*~K7nEe1#hR|n!iQ*twi4b|KSVnf9zgV<2t1_p)(O9lpED7zb^1nT~2AU4$fvq5aA_(~-977!b%<}ecb z1c(h)e;LGvs<{DTL&fVKgE&x$7a%s&5j<9izL+?O4LyTj+6r+IfEq{~YLFp_4K>FM z#DEOvNCdH=8qz>)sCXfW4HYi~v7zFPAU0II4aA0u zPeEeO2eF}QmVnq$HG8f65ixugBmq@)2Z{X<#D<>w{T0N9s`(9KLqp|1G*tShKmBK< zQx8?`4yq%es(nFhsOnrKb{P`82gHV^nW;$Zc}VP4AU4#T%}DH%AU0HQ{Us#MZ6x+X z5F4ub6%w1l29dQnk=Q~=YzYt>s@EKe?SRA%1F_klks1%-fD3>OBz6gi4K-*chz-q2 z^FeH=_zEQUE)W~)v%^U2Gf3?BAT~5of7yU)R?y-}1_p+IHi#=AIBgM0S_H&~MvWwh z4b`jyVnf9>L2RhF35X39w*;}F;(;JGR6GI329@loAP!Vf0f-G%R0?849am`!aU4il zFGw7!W-^EkRkIDmhKA4{5F09f6p4Ku#D<2@16xqd3gx^+l3=hy_?{cY2A!kAz`($7 z$G`wufeDHyDUdkGHK1!pKy0Xkv_NdAxG9JY6}JMhq2jI}HblIh!3)HJN`!*g5DA7T z5F09<3SvXWvp{U9cqxbt6|VxZq2iN4Y^eBRB=#mG_I40k3tBN91#>|DVqmy1eJ+!+ z11w|8+9R^PGKdWg3mqi36Nn8BM{gu{2ogIA#D?lkMq;;v*w9Gp1+k%O>Zc)b)_~Yh z3$`M$_aU*5fY?yYUy#^;k=Vixh|DX4#8yROYlGO5(2QvU;eZ3i3&e&xA{dDsgTzh( zv7wGALt@t>v8RIAP;=%Xv6myUPdI=wCe)y}APHy?eFm|i;w+$rt&75|RJ{sUq|)rdGD60anP z4e}YN{f@-80I{JVp^U2e7AzwQ1R_Z>{}pqJyg*H5C^JA$en?K5z5v= zV*7&FQ1!teHdM__5E~lQOF(SUt`i0Zh86CJ>x(vn#Gz{Tf!NUKs6PziKqW3BvF{_X zzk}FN4Qw8WM8^$cLoE|QVw;25P>0%r*ibbYAU4#lVh~#vTK<=NAnrJ70!cs>^@7+? zizk8DQ1Q7SHdK5Ohz%8A3t~gXH-Xqt@x356RQwQ#4HduO0V@BYoEIPosG=W8?7tv3 z^wJ+TPsHs(G9WfIO{gNV^^n*eAU0HQAQHO?#s-!Di(niE28KgO?9WJSVK0QmE=X)& zBz7{04Rufs61xPoRQ^Lb`;jDGgV@ke`2=D^Zx8zBg}9!G(VKyR5h~7w z#1;Xup?al3Z0MCo^4<&#ph;;^k*0+ZuV*j;aiAJ}kk~0m>;e!QItoz*VnfxpA+aZc z*r2oY85kI*gV<0ti$QGAu1!#m0I{LsYrt$!_%kptYzA{cZew8Bj>O)F#6EQ}fpL0rnXxZp&-9ID z#{P^;rZbis`}49eGBSYrDIjYtrzgG<6`o#DZfw9L!#I6Wxv?K($MlaNWeiM=44@53 zAZ7N`CxWgrO7JUUnVwT&tio6^ePV^NKcmI;haf6vx?!cUKNAbr^rlK1kjOhz&jQts}O#fJ8JfDe0e)^Vqh?t{%}^9@brKNV*y^5EsP8% zf{@@So}Rc(NSbxQV+IEE>4oC*%8WOrZ)`ADXXW_Bz#s&1{f7o)VWg{*#91vZObtw? zKQxroU@YA3*JvyzD=zGcxHkzj?a%W|fPvwG>U95nSqZ7#psS3S*rh;sBF)fcK-`j~ zJALguV~P4KJq89A&?O2?pbPgHSY|0RFff5G>Skcs4r0QtL`nml?#sbGM;&}65E0HYZz*iy($ulspWFxLbsuf^hU={`KYG*mk#K6F;mB}w4 zzyQ51sbjkTd}9Tz79j=(7RYT$JNXzGSTrt!6y8upx-F>=bc2w;)^x_xhEmfv&o>rg znyU!8H0g`Rbp3KODXE)^h)a`xiZd{;R0g~#(&eJ78n~dex2U8 zz&OtS4d~t<0q`x%0-(!7nFQ28w;l#;6#`+P8-)ZsKsO2rB!W&X7uc!Ez`!X0Izp05AOy4%Ljbhgn@0e2 z*9ETtXwe9tz;js!JqCUO(3MC60&zMF41xkHB^elm1nz)tW)cwLWMB|sU|GV=z`)@N zay!e5>0cHa>(&1TovseKXh_Hlbg@SPXnzh11B*83tenD?p!<4V`X3v@T&(+01DU(FfcF*OaR?JB+vl5eMkVb*NR0TO@)DhRp1lope2DeSq27n z0r0I40xv*EAPZ!wGca%oSb|Ov5fD^lVBirjk!N7w6-WY|yej~@5{F+P9CZ1Rz;7{7 zcvOjj!lRd+fk9Z{8aD%jh(HJPbcMynV)d%(3=EP2+Z7lXqy%=UFfd3998zXrkP*1g z#=syeV6V-!KN^9?*$zq551KL5;x}|al^pY407EC zrVAkRg+S&*ZzXyHItd+eD-jpyR-!JDp@s|$3>*^7yr3B=Ze7rU{?J>AxZkldFmOmQ zp8?-W#9acCl4kzG$iTqEy#vI7-b%#%17rg9RwC}bpvaSF)_~kfG#eCCip;8@Q$shgL1iZBR-(0>3=E)k7z`Y4V53A6L21aH85FpprJ!u*!3^@Y=oC;` zc!J$6S`D(miy7n$1~z}tJp$g$>6{DmyDE1~E`E$~Aq$3S*h+ek+XG1$TlHhb*fY7gWwY;ZHiGwmi2rI}&wj_{ap?3{^ z2c;*-T|-=;yM{DDr*vh3(mnL9A#Np5nNh>K3v}TUw>>ET*Roy$op;1-47xj~juo6g zx%)sz|HJPZngz0=f%P6&Jp%(5=&qq+xVg}~h9Ks)BAeTWY;HTmTn4uPpsOG{SWQ6( z^n&gh`Uf`&de;!7AnRoX6{l?6y`Wn$`dC3Zo|8M0v7Ui}1A5mG_iK=Qp?3{&Zv(~B zM6e}++>1e>GYQNI;?@J*sW2JruwZUhP}olab3z!{%0M}BDl2Fo92e-WA#2b9h2YSF z-Zcbq%PfRj>KQm@Lma~ZzGZ@A4l5TA0|OW6uAx@AZs=V@5ZwzAx*0eYK{RuN(gX+m zuAwqe0lkFPori&e?Jp?cA$JXNf$kbQ2sagU)exw|$L$HaSzxTxE~3NGq+z;_LSx;u9G85l%BcMaL|F))aB zg4}b36_nsbt3Y9Rl@*joMVEsv!nwu@N@k+>LAA_vR!~HVMuIZu4OUQ;izaTa0{0dxC=^9Ow|a2gW(5U|C}?LQ$DLqSkUvGi4!X+MQFJkgD?_RS@B=pi@PmR}Fmz)e+FEhT=g*Kjf+* zF3?p&-k>8(!6kqe8>j?efRq5*Y~WMa86ic04%>4+1_mbXr=W}jy=#aYbT%r79@}kD zBcIzDbmFl-n8V7zb_rDT7_fnwnp~i(hCo*daPI~MDfFr#?%$wLfnGJl4O)`V0ljL7 z`y{A21G;Lc9(<34JgCWI$rcVe3LA9S5a_UDo}7|w1`azmP^x9%1|4C@0ljL7+X58l z(5r?ZmO!r>;@$}=<=|Hhg{w0#a5%Fq1Q{#A;l`#3I=#;YlyBVGK+O{d?*E{S#o+?y>NGg)k7QtF$#Lu5JWfht|4xaLpdVBHnKCY`GO)Rime`G6zHlUP%n}P zdesmlq4NfNv+$^BD&0zycfUX+y0o@tP3vy#FTLj2{5zt*jR|H{MxquCnSRq*!a@PCS9EM|nHU(vp;rwxftIhaWrFILDz-k5@l!!pq13az5rpPOQ0dPH&Nkr8 z1>!PrvViR5syEg7$O^JeFi&U=m2vVqjnv0Gw!2PuzeS1VBi%5UF8H$1t3@ReF5cva7-|;xPq>5Q3rK_C7y#Ws^HX}3c5q- zh6n=#ryhvOAaoFP7l=NH%_8K$$iTp9FdJ0F2~7iCv|}g=YLE-Lg6=^v0)OWp%P&MdI5crkJG9c?%K+a?V?c3rs2MGxBaN67i zIp!(oS{qwX#lRrc4!W|$4#Z{=Y6Lj|c4hK%Jq89&hczM$41x+=(x7WVh5m!C!H@wB zC@=`E1hHj7Y(^n|1JKnEav%^!%M@$S1Ttexf&Xy`jT0p22bnSuKb|wY}5g|}_kV_pTE+JF`DjzgJ;xY^@ z3LrZ*pNK$DpIHLx5r8_0EDS86(?4uB78O?lH3ghN8HB|cbe^aOm?iT4OpBHWEhwQ9bDlSWHJIBy^#c3<18Q!+M6q& zC=1Ftpc`bF1@?pLTn0AKB~IMpOdxY0gEHKb;6t(mfnG!$)LEJw9~2uPL%{rcMh13JZf^i}6F^R8WMInxou#eMbQ|R4 z3T{It@LA>Hz%c?x2m?3hh9qudrd^_-689shU2OusNs5DeJ?OAmQ!s~z8rK2y&kQb!sh`&V$ah72ys6B~MH6@o661Pe6&o3T$Zxw>apOTWcl@Nd|@- zZb{H_&NfV-`vVFf@ng#b3hojHP8LwI<7Am91{%@?rA#($kgM##7do*W0-bpayC3hcrrw!7#M^= z7b5UvegVZWgU|*I1_mC;1x7*_K_h_KAT=C9hd@^o=YTY7K;l&e)WQcvlNA0v#d3GjX8^1A~GP1L&&1$>656gHW#m0|U<#kaHb{1VQZz$c08i zhqW0PcxHesXb@roUGX&&U5@M8LVBnbpGIWbj9?1KU3yp+oLHAZc zE;Irc#yrRu8i8BrpfIbqWngIm)t(FVr5G4kia3n(hr7=cE;g)Bf< z$wMwQ5-MhAsAu3=2g-bWLOEOv3_R;W<_HMc>o73zY;XhJMepK{3G6JpJ!3W663}&;i&A zph#k61hE;oQ=}Ofc%WAsaf1%U;DKIk#0}cA$io4yJ2)9QSwJDcrVolcPR8RhpwST? zZpKiMd7$c?2YR&;cLOMiL9aFf_py2Sz}FZsabMBCr}{iF-}+8W6W27R}Orm(N9oh8G)T4!YDlf zbQiNR<7^r5{YCv6jGfKy@GBEHsGJ>X?G8m<=f|7z0=%D@*J z@%piW?tBuuH$8u^vA85?FrGIMlnPmdjI|jUc!R*nK`3PU{JqBFnWt457M1ccN<`no_#Ohl*-mGBEH?28lNa*?}}n0f{dV$^@~efy9>xEm31&;GGTcBwPuSQDBsvroq6#3ohYQ7-cI&85nqB_Z5M9dAu7zokb%? z*-4;C-URCAB{9l^#u|C|fksw}7-d02lDzvt!>PrLvS&cuJ@9=+(ct@vK%;i-PZSv# zKo}ekObnbXpgB60GoTPYoTb3PAjrdeMNEl-L1-;#st$5rkr1fK&3hA+&{!B)G(mxK z>#HIIgJ22oowVr%2aILv4}(JOF=$?e1Kg?LeF91~1>mZL_c@4N$iQL*QuI<$iGhKI z2h=Wr-BiT;*;$2wL1-B$Ie!5K1%uEs4h9C^pP|qj+X~q%-L{*j!Wm|1s8x0+_IqiY5Bl1 z^)B2ibQlxKHR1t$3pKp;s#Z=ydvO&GKBj9sBJIG2nvD{Zcw$& zD+YF41vjYP<`oBXs<5+fN-=VPW}Mjhr7ujE zJ7g?f-wX1z9M}VV{L;%oY9Qq~Kfg5S#$8_cl}4aCo>vQ8^a}DzgYJ*y)dur~_@#e> z@*C2PMxeC8o~FdW5DDsygGwoR1~$+QNxTM(HA)N&Y{H-f?Z`Mu19a`81MgzS$Dm%6 z1t>8?uQcLbFU!Ed3%$~ad*$>8hm4KuCxEW_UI$hz$lU_ES$jR01HHrOGt4$o1~xlx z1_s`ZjD;$o**xB@jQc_5dS+2J1MfEQdDslx1t1HygE<1+CJGD;ygR@g1#S-zXBU`b z!0iHZ)NU}R-T^$!$Gev?fsuhB06fgc3%$b#JV3?^y~7ARK*kHb!w5X^#(NMPRO+#0$Nxh#Pb@IWP3KBJMZS*B>=jtG^Bk zMlJA^^E{s7ToVRfGqCpg;AtCPb0$#1x&S=8!)w6=Dp(hC^MeWy=>0|9RiH?>0voWH z`z|Q^L+>x*?gHI{1HHcpJe$qy2%gPe&bg|60*$N5 zahHP3fnH?9y$)32Krb@l{xH4%xUr-MxENZ<1Uf;)fcrEk|A22T0$o}JGNA%A_6zmU zVo)KonCY7a=*~~xWlSqTqbnytv**j1R!o0z+*rg5G*!n2s_A%FGPQv2UD5=_2mG2M z-p@>+<0g1O*A(%70fz_!cR#3*{t1={la>dC_Ae$8sp)nnj1}v9KnedJlOzZDnj+8% z6TJVKBz3{p6wL&cNG#0qy5MVy_JA@EE3>{X_?n`tAZy{*6fuKxD*T$Fg&;F|m|uZ* z-LgvG2h})2%%E0c1)KCMPz46Rrf3%Enj&8KHASFV2wpK}P*oSlAq|>&;1vhYawl*| zhk~q-Ud#g3>4anj+98s=V-Piq?TtDl>yha_BWhy!y-*!r*I)&VcG_BW8PD z@HIs&Qo#%iye7<{y5MVy7(q$Tlo?b#?+}-61*I1FHAP&YBn!W$C;*fr;MWw*kzruq zg3C@LfYPpakH@3_3GJLrS^{q|%=mR3g4mmIe(+@dhwg>w@nZ(gHaUe%DYB zD76MNgNm_l%F<5Y$bw%s(7ziX%zWJ4@irGSd`PtJM<2HphbMqS8dL!ibtD51ie zd^`8Ny@qOf3=Arn zS=kJX5uiiz4Hy|1l%|4CZ;Aj7@A!k3NGXHbu96H444`YXAZiOiYC-q1L(~?6)Gn6* zDF%%*F|2f9U;rPYyv2oqp~O0J>`kG=|9721=rg z!CIh;{TSOpa*Rw24BDVUP{wx97#m}#stp6gCLPd)AX{9f2W}`4oBrXfu~_hZ(CL}; zz>~WS3=Gr2Ryi6lFla3To!+HsO6nAmQ$StI^+p7AP-*4%sA(mA#&gDA1{Tr`42%as@v(}T zfk9~*=%h<9_X;xugQ_vq3N>E_NKh$EU%1*%Z2I0S2E5b#&KoN#f3lbh<%L0aE`i(*z6=cHsW--u#G`b{Sd!6ry3HkH4Yqs>1_nd* z=~q#R9hM?&UmyH#{%nA@wMnn~KJqK75sJsGcS`XFq`m(Vw#JH=_r2H8wqjbesfe)-l z4_Y2*O%J$YtO-$_0TnAXgIGTIim{e_hZ!ir$1s&KFsM$3l_qPTD$hVw{=Q3Uh!e6C{^KK_sSKH5QZ0HAmQ0!UQQ#)Ij%Dfqb_SqVU00 zV+B@FCcitK^_sC34==( zc+J?dJ^(Z;bpxDuKp6|PJBo3RnNjL z8ABim<2KloaCTS{yu%1GhiPJfNkIVv;~j8j=wWAIPy_9l0VPWwONQx|*Nv4R`3bZ> z9hRS}uNzCbhgm`|tzc#_cnmt@@ITlBkTXH|f-%ksu!7}||KQwlf}MfE5Hy>^$N-+e z`3mB%pMK}MvAjHJ_J)xWJbS|!25~Plc)_R_2Lprgq3KdLjFrH7Ma*it(+y)~h?_t| zO

1H@+$no8ETASc@@h`o1N8+!0q|%#?@ePBNO}u}rcOC)NP1gv(^yzp4YWKT6b^>g z;22~yU{D3!R02x1Iy1mJ;HpLIL3bT9CV^cA3M9}iGmLX0Y+-Sk1a==k7XyPKI4&W4 z1JGSd;MhzC%QJ=;f@ZK7Q@}G=fgshONi4=x@FW(fZ)Ru%I_5MDJdb6~&A^}!E+x{L zEI}m_(?n>2lnHhRXhD=QxIvM{1Z`2Mg06rAc|gq(>;VRbl<5zGZBn4cbVm z7RkWC0IK#IZNR<;SNoul0P6zfbWj%90nv5yjxoQ`C0KR!1Zw1ah@|#yV__puGGVd> zo5X0ypr*vgz+kM;z#sz_ieWTRXN+Z@$iT*+1}X+XrJv38g4@Q@!5~HIj8Tk6>WncU z0-}n+Oahb^H-Nnd3T9AqlyS~tdstfB0G?L-$PG)28^LK&h=+kefBp1(w~eL!z-e(4 zG%Z3xZxeVTkTD#RGPi&Yx8q@8fP~#v%&-GB>Oi63X*WIaY>C+P*gMA7I^e(qB_vSb zrP+bK3=TX{GXxxXbU3Dh?SRU>x10X)c8S<@!Mnz~65yb-2b%*5 zI?##;P^hR*54&qD#|BE6f%el2ZySqD@4IU(qzRJChblJ)g_@x{V=PlS1A}TOv|s!7f)X|3oK+4C42Ixj^&1>8-8`^*?k`y7cX-hJg9i<0 z3LNZ5&_#)$piy=J`B7|o!aZXlNYH?essRO!g9F%0;GhYE1waNg0LsDIR3u6n7#KkQ z?}8|1G+@vH6+6b$Z{0ICaLads#kVpusAksXg}GP-JkjdM3v;m=GpJ5)<%LD2I=Isa zYIqy#`uJS<*8Tj~CI)jzLa~~MXMx}wy z&W;EB02Di*@{n{!3f;Wn*zS%2((NSQ@=8_K^_0dSeP5s zX4OdmwbEUuKX_;?Ue92@0kl=?1XG*~1IkS<=C(2n3@j&^%0S|vu!7#?V#y1d(aB*3 zbz_9*sXa$)6ohH41B@18^stHK-h*=lz{<+IgYSTSG?zI zzkU8=<7N7Si793ADTyVC@u16=N}NJ`r=Ra&7Tq2vY*J)0ExMLri;T7> z+*HzIoNjke+hF>>D=Grh<=)5&P5*FPiEsNlPm@XJl26zW+iX7~vH7P*Hkw#ZzhNH7 zW19+UQA4-lf=p5EGIqAa-!N$5Bd`|9+AO(x=!-;sn^K$pEhZ4jFNvB^Za-VsU24~ZRv z#4bc)*CMeyk=Rp_*b9-^>yX&Hkl5ED>?m-e0__om?Qb>(T?+$sV+sdHUOC6MaVh>2r&c#2K}wo3@xJOGa`dVmJ+nT{69}#U$SL36c<~u7kPhKa#iz zXssaBeTqnIz3CS}r;ATlX*H2x%${!BY9emfh9o@+iML1>FM!wMlFG*)Qqh({HqzNT{YGiI*U;n~>Pkr~f@3Ctkk^N$5Bd`!W*yJ`(#i z68k$6n;A5Y0CfsK5?dOHt&YS7k2}ai@1$@*lJG%d7a_4HBe8c*U+Yk$KV6{R#6Z#z z)INt=44P_%#fZ=J$aWKD$!a9&4kY%p=~F?{mym?+BeCC3zu0af9?B0|ga$QS28peO z#EwK_ry;RRkl5h+w4mlJp6+-pMVxWp^ozO1;`MKlRQ*O`3xFJ6xQK}hTfBz7DUI|YfIg~TpEVwWMYYawh< z%bbCs6T$%(H#?BnN2mLCnTXdvKoWX`#1;aLY(d>9i^SGMVw)nd9g*0+NNmvl4Vb@E zk;DrjY|wgM28LP)2kgd9B=#aC_EseJK_vEBBsTbB8>pk-B8mS*VuNZ@n1cjGK__!S zHGrmOU=o_3F&(J5DH7WeiS3KTjznUEw%ftXDMS*lMPhfs*r0aOQW%GUfnfs@dp8mr zJjeuf&_yKiJJS_=Oqz3xKwVO(H0WqWnEky-;`5Q%+mP7Lkk}%i@dKziQb=qCB(~ag zLCGR;l2ehCE<$2om_D`F#9dMibR7*;hcObnar)O@ zlV(*3(0DdfS`~@yio_0_-uO6Cygn02s2_z{5<3HlU4q1JKw|eGu{R*GL02}y;`aoS_!ZDGQ!t4KND`ne z(=hQLNa8G@kw~a-z<1|B+2Ff#pll5!H6}=G2PC!+j16kDN5D7?3=E*vc`%C$ki>hZ z+g9d_OKwIIx`xDlH2rL4zIgpFBq25#MDs-mi7ki32H%ncb+#{(cmfhT2Z>#Q#BM=i zPlT``2e^P{-(X%?4v_#y>?S1k-szqbO_U{HBMJRLV)IOIooJ%0Y7H7@fjSSgv;bx* zXl4$^PMUspqKS3r8YHDVk=VzP*jJI*kCE6Pk=Xx{*u2wiErZ4DL3h-^Y%>SlOapb1 zD-t^xiJgeV&PQU`BC)%X*fWvX%aPbyA#BiSF$2S42nQUHUy#@gplfEJ4pKp48z8Z5 zkk}qb><}b&!t}_=Cj0Bbm(W0svjJTm17(9Rq=B+aki;91*gZ(>8A$9UNbC(r>^(^A z6A(6}G`Ircfc^RaiTwtN{R4^3qKHW80!VBbB(??;+XRX2fW-DuoGv!iB(8o7lGs5c z_G={eKO{C6XgCZSIO0fbEhM%X659!h?T5sUg0LYGo(|!F1EC0s-G;=Tgv6eQ#9oEO z-iE|Jgv35KJ#w1K>H1Zm2~4QlLFcT%68cdj@ykf;he+)ANbJ8zY;F}qd`Kd(L2D{u z=9@yqAtgo>gah_#8WOu2iQO^%;B*u5=})GcNJyPT62FGT{-QEnY=(&yua_#q0pZhQ zXP8(^E=3aBgv35Ded7$1Y)0GZvNKJ@c_ToRR?yH$neI5#KlxMnpYmO$sc%$s>t_PG5kDTf@Xb zMUN+p!@$4*zK;hQ1>pO5pltAcJWw|HIvyw+d>s#z4Ze;C$_8J@17(A+v*7S@O3;;HuyRoDBE><;?zv>`a~pc z;G1}$(%_qTplt9>JWw|HCLSmod=n3p4Zes6%07%_Cio&As5tl{9w-}p5sy5>bbifz z)_U+wJWz>Apu20J?0HD+B_KBRz`PZ@3=G0h_Fj-U^l-&fNbK_%T?AsYg7Y0iH4?i8i9G?thN@qJ#9oWUK8VCVg~YxGV}sK9 za~Ow#fdO=pHY3zxHqd=IP&PjjTN%WLT5JMhLw#liVnfd$vjg3q17&-H#Gz_}L2Rh+ zBlJP%8bT#fK@w1QK8OufR03i{#T!9vsG(g*>^UGd)S*j}*z1tk;0u7D<{SfwgU*}* zT_tb|8&w-l5iNux$v7wGrL1OEI z*`V+T-5&ztKrQe9u|an_FfcHHZVVEJvco~*P&J7lHq_!Y5F0990AfSM!M6uN#p{v8 zTR?26cptLFWF(2XAU4#XHAw7@AU0I?S1kG$i&aB=&I-8|t{TAT}4+CWecK4D}4c zP|h8Y1XR&85F6@)*B~}j{40nJ75@cdL&aG@>t~?ioFFz-Tnve=jKtOjvBB!=85oQ} z9H=9#k=TJCHZ&xnkl4vc?0gU#s<#4(-34Mp^-e}&&p~2?Zx5=6y7VGQ0(#@qRnS#J zQ1%0mI8@C$B=#R9HW%o29jF?4B(@fa4LbFbfq_BKn1MkU%C-cFL)F*2fH>fwU|{eB zv7r(nAU0Gy62yjzr-0Z{@k|gKD&7QQL&e)cY^Y_cKy1*OCD70ihz%9r31LI>-+2%R z8eBJ!*bkA|Z$WIRW=_xzIZ%rQKy2t0S0bQmfS_#feL_$*S|Bx0$ARwgKy0YR!AR^FGf=e-l_&#AKs9$Fu_qz1SAf`1^&64cyO7x6YlEQXJOGJ9 z*)NgU|3Pe!IUxUYm?L~9h{RR_v7wrEk=V{4Hb^t5-a%rABC(@EY^dHmBz8FxyVsn7 zAqf_w(?AkXL+2y0H-XqtgYF@*zaz1wEEpJI7r=q93WBPS0*g<7x57lc9&}100|P@n z= zrV+$}O7wu(P?t^wv7zE~Ky0Y^LJ%7&z6QjGif;t5q2l|I*rz~jsG9R2HdM_$OHew8 za$bTYpo-ps*icssf-bv(h7kBVAgH(kNF2&G0k;K7Q{XoULk;JEg*iiA=AU4#TRY>fuAU0IZE-O&; z6>9NakOb71k3npx_!}fP6X@O?s4uyZ*dj=5c@P__*9eJijl>3D2m~>wo*@h*0pT#j zBeAnVY^V>wHwA&t3}RqlsIq2Y5Qef_kYG zVIPPC)qEJlhAKJ-Vnf9*gV<24B;d1hJtWkcvd& z7=YN&kg!BzJ0Y=CL2RhzJS27#61yABo*osSBB!+(#DJ&Ahr-B+h>68_kpsDLE=y~bs#o0P?|w(sCXZU z4J!`7mjFQ}7J?+8?Da_Oy-4iSNbGAMHq?UKAU0I*D-av%pwCEbPS8y`&;Sy$n=ZCa zU#uQ{g%4D1Fi0NCPDf%FAhFv(Y^WLiNbDI%?0FzI)STr=?7bj1RPQke8;fcqB@(+E#D-cn1&KWuiM_-gsZ3lCl7QYRwAmhUMI`v5 z9%#s(1gU|B_&E?8Dt;5hhKk<& z9p{b2P6V-`{?0;TgD?1jinoEpp?dp~*h?U6NP=4n;efq=7{rEZK7+)*ip0JRVnYpm zkHlsM-F*WU*GFQ5FXn-YgYV*jnjh>0N^nq43`hf%T>xT3L!}zT1}!=SwUwL@H!604 z#Gz`Yg4oa?odse;#aAG)w}aSFa}L1Ru?!3h*FYSo#rKieFOb;pKy0Yy??`NJ&?P-k zaSt0J+E0uuHGKRhC0X%#D-or=;e&K{V)_sJPwIn0%AkmR*S@LLt^)U*ibX) zg4m#Ql^GZq)`8e!(00~t5XTZ6!wknkY^a0If!LruVGIlmmp~4JvhRY#p=w@$*wD~@ z3t~gnd_!XMxInWo0|SF75?js%DT-A<5>U;$NNg(*8|rEw5F2W73KF{piQR$3o&sV+ z_09ybp?a5s*cPBP!@$6>3dDg*tV3dNMPlznVjnt_?tg%hk_O#B&LriX&4 z4bzu`sD$ZXLDZJ%u3t_3nK-UYpZ3+nkFjU^)2}A}j49JiznSDzvofNs`c{RwtVD2Q4yeJO}Cnf?_-g-mz-W#Z46 zGkq$EvY7t#mx(`n#in7GT{|=a>qx z7H?r-m;mNZzaa0=GWCQh52M4>tETEq%v-1aGgaf2NMmFW;AUV*Vqjp1hum%8Uq856%PZ0sv78a3o&&L0R{%98=wru!osep&%nUK#11+XocX360|T>Q0O;xn zMz-+jGGe9@_1pCs7??rpVVTA37#J9sr>QV7FiV0q-Z3u#F{QxfaIhNcFfg!iunU3? zL||bBt>Iu{VgDiyy6S?3g?)h>0|N^qM~yrK12bry5{n3^H^K~Br^q524l;K(==ujm z(6$lgUKR!h7M*I4s6XiJAr@WGMo;EL)Axy)Du`zbF)*;Ifp$$Y&){QVVAZ$>QYbt9 ztC*>wBxtV&>k07X7wnvZ3=FI%L2NemqtorhO{IBzWf>S)PunswFmMZKPfr&&)sc%+ zVqjpkWW2`6z`zOGI{plFXyh^m&~+u;tXk7IiknJFE&!=rks)BB?C}J#QVqoBw=4N1E{Q}m>y?Odx3DXpZkGc#D3?h1mU|{#3o+xQ5kOBrX#WTY??b6Xh}m9pNd%9xTnkz-9J@Vft|?Q$fo{(9xOZT`UX? zY&={x?jQ$L>N7BK*@FDSz-|vZa?=jPW?|nAveX`A2nPeR<#a)5Q+fZn>I@9rR;-}( zz{vkenSp`ZniZsiiN6JOSfLFo$bJ_7J)qMEZNVH4{+Xb&1MR>Z9tLhLJ_ZJEd)6RU z1_tJc>Gjg4qP9JX3=F)9*H~c*4Rp8`D4{tpFsp(N`Dg-J$Gi!2epBloRt5$^b~XkE zp=Y3`0rQLL7o|<5M14UU>?eW3mXD2BpDB=yfq{STG#OJVu`1AM7Di0EYzz!iY`msS z^=u3b(jn6gWK69z&x3Zt+k&rdVB|jpvdRw3VdDR(#K6F7&!o-Bz`)GUpgMiBjHzn< zT+oj60I&)^1>P{GtLzL6{0H?J7W1*2~Sm3v?h)G?>G~pAI@XA_mOiz`fdNz)Gw@0@;?Q|u_W^jMg|5J{(Ycx zucVmGm>3x9Iru?G2=YoZ$1yQ5@bEW-OqF2UGw;)W`B<(^)tU@Fbe!0iKyay`~SZUzRywCRkBrXqrSKxKgiYY|NGgz0LE zrl8v|Ko)V|2KhAvTugF!)6n}LCY{{-l4lzLWB`NYYT6skj-sHHn$Dg+;)h$4BSsar#*GBit{iq@I~-;vp#^E)B`mMT&(r7 zf{HaZ{uiJVN%~kp`Ja=Y2Xy-dZ$G%C_u)SRa_Jrh()>}FjL(&)vzk5!TnX48IT_a8uZ zfBiv-2N<~fLB2o4`U0feoA(%NGF9ORRvw< zz|MP)6|`>$5{~DgCM^J^_6w}qj0~XLFStR+u<%}F&F5oakc!~F%&N%Gz#v@!a?cfT zf|uR`O1xLWiB$Rp=y@T5`*K6CBjiKR~tREpRAG z-vp(w+u(qa{sKz3ck03Zgq-qo7wl37?i!Ged#v+8?G8JTsgGGL`Jq|dm!E+_XaY9_ zgAj)1EB6^t-SCVxo*#5*AxH(N3>N}rY%syV4LT8v_Z=(fW--B8a0Q>47^d5( zn)2441Qm^6S(kzIZv;t${fPp~(blU{49UCYWGt~3n0|mJ~+bKo{1_6F1P|Q29 zfr?}ah$W6-OQiUdLB*;Qm?O==eFzjh&TP#fb0v7)*ti8582I0TN;Y>kP?Lp$elT6- z6$s`CGjIoh+!4ekF37;ZC&3%aHXrVeFo-)KCWV7dg1RFDteFks!um+CjqD8Eh3pIr zyishRt04Hqd1Kh_fE)!rdoUKPgn{1~bUIud+jGzz82lSR0@)`$k7F(PU0|UPmDEVcB(+LB=J1BB?pyG(q=TECA)JDQro?3=D!r!VC=Hj4uRYG4Qg0OyN`Doz3=2n1O-68Ca{R0J;N%Uk22ina2h?_>hC&9+WBOv;6@b49&j?R4XiCV-f-7kZe$S zvycsRnU4s63n+${u+-sBOc`@&**WEMg!{ENNg8R0i>~ z=zu)QI?szG4CD(zP;9PXs{pYLKy8Wr;B?9@4Jv?7g4ujryjR&kJI@3_S6T30 z1E*>R0nk+zyw|}TCVoCp8oB}Iu<*|VMcqv>hmGGIe82`e^-XX$=tc-|Y^s4+prSwsR17jO_lPqv@EL>H%ojivj0c$caC)PbsiZ=$ zC<6mOXe$k0CAinmz#pZ|z`$1p<}mWVpT0}W)PeEx^xs;hYW1-)3=DkDU@1O+F)aoL zz7{ZtpMiU;3IhXQE8}y}g%u$4SAx#z26ZqQ8Dv>NqcnUX%qK+|7(|>vSA&Rr2dy6# z0bLQw#K5g9&%nSZ32xYO*GMri@Od&n6lGwL1eJ_mL5H@3y>$d!^9wS7E`$ULFtF+H zXIP3cFtCU4GcfRHf_%)t-mS^Nz@G(@XJMbA#K6Fx4N}6v?gMJ3=YYgDAVV#lptGYv z4wPeH-U8}m=7LOSyTM<-P@I8*9dtDue*?r!(47qYjsF?g7#Nt?`Sho&>X=&9S86jb z@VA2$2yi5(6)^C3Tm*$XM=^-qc}IkSL6{wM{Rn?IsNfM{zpur>z~2K38d3I{dJGKw zy&$$2y8@^i-KPv1v0(34Wnkd%2gRfuy8?(k0TcxC>^DH|nTeoNE*03LK$XhmFHQ^$ z3=ZtJiVO_=Q$P-OWZwuXL#Klbt!MAk0kva5><0EIaZpzir6fp2_1lcFS z4%)E9zX=p7G7P*ddqAyU7Laq8^)(n6_&0;BXXD`Cz7=FA=zbCY9iZ4^U}ph&WG9Ht z#Lg(kz`(x?#Aadt4~n7PAT}EVGqV_IbfdmTf`I{iq6PmMP!KVLu8!cp3}!9`ManG@ zlZ}P{&Nq-PF`(|;U6AV-7?{~WiR#`%kO83ExcGm9Oy=X^XJPaL1^HP}bg_cj4E&#^ z7#R537(vOCgRTx2OfrURxfq{Wv9jxjO|94P?X)x+YGcY{h2VHf;ugM6C zk0KPd`9*_VXIxim#$`YoGpaC@rMtRUhNBm}t*CarP&dYa#EVN`Slwe@cV3gki zN>$ci@24=z9|g6`?drkYR7UyrAY<$qmq~(7otNJQa*PAm!gNOYaux;#en&>o8TlEE z@`0d)dpu{D6f`L-b|l?f!~Xf zQ4(|#y*%iEUVd-J`kA5(47V5=cv)IOH4cjss48T+3c7Fx6n`F|Q}aPtjgx`a0CKCY$o=D z`V0&Lfgm;u`)gHg1_ps3Q2JqGf2YF0AP@}dUh=SmhL;3FoR}CG_!R}zrWYETN|>J4 zVqg%60BPi5RCENH5(%=1k5Ta}sJ$5lO7&`tine?V33fkDl)S$FbJfB6lgOlZkJ?W5Xc2_bQl#u<1+#Upy3%^M#bXkJVvH!^_HNfTM0;k zHKXEw&?Ug7SxgKJHjI$M2-KzF0fi6~m}F;QUJdd_B`8P~Di{S?l;s#0*d0Nq9k+s* z4D8u@3=9Hopk0Y9>@z{(*a1qa0_>MS`no_VRfJs%r()L4f9|Hq}z+#ZN z1fwEoJV0P6D86JE6>oxa%1V%o0;8gdCIf>2xXe^xR5S*qgY}@<1T98IP!mjGBd957 z#HjdPm4QKE6H`4CX#JrgXgok*AE@6`#Ha`wHW1hk8uBP+R9r2@z#wn{6niD0l==}g zUTi7HzyQMFP-kM`WdRKhGn;_o`S5-j&>*+Km26PZ-(hB85V#8NN3eqiTm)`{QX2~c za|tL2Zh6Up?rkg)xU+k@rirPH_e4-2JqC@0a)1ZW1)hNHEnr{G&cGn>9K1-D zt-<~YTARqvi z@!_8Ya+n~v@C)F74~j|=aG4pxUjVuyNMKnu(hdO8(klo)Eu0 z=z3}a9k4ON{0zJ-pme|qy7qCM0s{j$!N@akZwHxf06v4CJ4=dzLBNr*1k^`%5LnD; z0cvu56k%WxSON+YQ0=rR!E10%4F5!`p?F9KPx9n2Bn->tyFAg}|> zQQ&_J;_L!*4EXF!Ip2xr*OJU#!1(m>Y#t=mY2EGP?lZJ)HAFS039>@}0K9HAkz!o|2M}SgAE)yRU1A{aFy6GpZOcm>IgRYKv3d+NkU{!oZ0yCKQ zf=o4FVqg%M31&0!7lTszEGAH&SB}3NWX^1GIBD?T2SwFfFh`630jRc_2j=MTUjVf% z=7TwU{NOTYA(Oo-1A_s7KBzQa1ae|MgCPSa$kel-8z!KhECdyzigek-UnVqq@P1RX>#KM#~~SeZem-#=lI?*gS6HgLc94~u*PsPbnA^Zv5PKLVM; z!)y;aW`|Wi2vh|LF@xHO6>RcJplmGyo}LQfkS_6_!!J(8` zkjWsR&nzVZI*48#G!i0U#5_e4bP&C~g=8=TgMbP1DoxNq^zu_dF>lHYYQyXhmrnwv zE;D9Oli-H9{BuxUZVu+%5tj!Y@Gf8h<~J=4}yx_%|dg*MEf zroeM?`Cp(|v<35Ch|6yS#kw7s_flLw4rDZBrtFotJUAJb^9C?q z&;*@XFTWDh5DWra_(54d5#*R)W>9JOO<7)8B%gsnAQWuHPi1)nUIqq%Ffi|zvOH*x zQ6L=5`>ibh9~5^H;IR0kEME*NJ0iinzsmBrK$$g)8PsWFP?0|cD!`(_ay%;XQ$RU0 z2F&ACk)J;Oqn)Wp{WVPn1{oCwPEd0jl!(E#IH=hNx`mz-l<`2x7b?ohtj53qN(nIj z5={mM5C-!>rIRao^bAxeae@jeP@sV2*cmuMf}nta@_AW;`573@IYHf=XPVIF0}BK9 zdr;|@#4N4Gz`(4d$G{-y0BQp=vuQFg2!hA5*ti5+BB$@RH!*LPH-t_5 z1_r^oAR#68Bvl3m!Fiw*sKSw!T*M$aKT?Z~@AQ&+HnS-f({U%8U2Ifp%1_r?sYq=O0n5TnGIbW#Fz#s_PQ4j973xQY+ zyeuH!FoRBS61)ad!0Z6>>s`lIGlC4}=I3N!5ENhpY3BytKPAZs zGL=t9P=Rq7Xbh?j6ikX>HUqx}NVO8<8XZte!HJ(5Htq2M;Q1u zgcukEO~4#Reo;_ln}Rt^{9&MQGy`*(`K3U>{9JnK&4jK}Q$~`)7dm^FvGvehxBi7HGYP$O6#$LL%!m z80s0AL~ihdjGM#Bz`!Ds0$S9@z--6Jz#ts8O_zaztwMO-Ydr=A_BJjC2I2XjEWp4H zI>kbG0f^1Wt|!C5APmkLOzdZ*7#M^Xfy9~FK{wnBF9xw$*zL3#7=)LA*sScQc^DXk zmw{3#8~Yco>HnQgxl}=i+X=4(iE*%(2{JGUuL7|-*-aT37=%}Y*j(%p)Ad|T#WOE} ztlI#}O?>R23*dw|f|9QQ`vqkN2H{PhGEjv5tp)>w@MaKOfjtlu09!z89d^*Q&BEJ2 z6_*A32hd>!+d=FI2Ilo3doF(hdDlevnZ7;)1AFlFbuOmj^_d`JUxKV-;Q-Z)4>m)PK4}I9;h!KUGq9hMWMB~f1&Tx#_6#-#2H`&- zB^>NW&>@u1R48s2uj6t1AN6;(l z|NQB9Tumiye)BUh2+J~l(qv$G!T%qWLgX0#YBDgq4t8m!u6nYiG)?bzRY8kX9UHT8rWe4jPf%T85o4s!ClWnM)^~qSk(aY ziWueH#2FZbb-^l&8RZXv5{&^^u7pwERF;83*aU258Ke9L2?hpXGcd0LR9%4%YEXGA z%fR5nC>)v02nu?B(8#KA6j(n4{}oUmMl*u43kxLRW5EH>0bYM390xW^ga0omrV|*G zj2Reo_@9GfA&D`@7&Nx90u&I*U_BQ6657+%+)Y(PL9;u;8DIw|@Gs|PU=Yq^+%Y}g z-BiBblaGNxI2UYe4*vp>bMwKRJpNKpz!iWw1^h*zv{(doWD);DP<)nvImP_FpeQT_ zn_a?x29&bPzijLSQt9^m8LU# zm`c{mfl^>I;}K&9h6((UptR7&c*>Z8VG6i4B-{>mi3p>-Gsr1jjGsYkuNdV)y;$KM zaK}{~8s5ENl@g5d{h%UYGT3QSjPgb*3=G0k!E!Q;@**JjOat@e80Dw3GfbZea>QIv zWX@;2WegtnRR)E}0K5o2Gca(ogL1AtqlGbOrI@fU;~HZI2L4)5Wcq;>)-yoN@CWl)_?bbm z831+w2Y(sJ1A$-;Cj)m5s9XzT%rgc#2~?xQW4v0cHV(fNq@t0|TQKs7M2O7PO0yan6b9F5adJ z_3OcUqL_-n*TI1FXfcD%vjkmL0h-=pV4U;Yl!3tj?5_}zzZio+XO1%L0&4`jk3sb* z=ycX-kl~=saEx=L%orFnK+AoPf}C#n1a!u79?X7FNHETcHe+Bg3Yq@c+f=ar0>muH zA>E)0X(k3RFzABru4YVv=>pwx%Q)wx83Tj%VbD3QNuUd9Kxc;=$bgR3O9Bm`Fa{fi zfR4*f0V!h)hJ=19DD*-1<`{`EGB7Zvod<1ej{+^5Vz>>lx1P}ml;A)%Nq`7r8_lhdqOu*-()q`Y=u7i$FZUlAN7=w-YK&QAgfjJ?j zaSRL$=gk=yAU@Lo-TMQMeo(3bMSl+X7Lw_#fu@4fnSD)VSf9Iswlb*rnyNE?p6=so zDjNZsL;^SPLFRyyz5;{9escx}GX_xln+2{K85kHqS4J_;DYIl?&<0IqF@hy-F)%P_ zgT{v#XMtwQ*ccfYjMzb^%gtFe{h+U@h(I#vv>tF{Jq09pZu(PSQ+eJ0t_%#R&|6K4 z85q<+TMW3}7#J$SV$n<>u|ft025~o#YYqKOrC34C?b8GNOr`2UDo;aIf{w=r^-h%B z7#QwD#X!12S4x1i`~!%UXg`G)x+tu0iSk9RmXc$VAZo zcXh^Srcwq5HBgA_xqEu0XWDXf`Xhe7-HaKklEc#3=HO(42(}eO}BYW3=C?ZyZ{OZ8!M30qL@mVK>mSy zR1XyLpd22JRbC?nG`|HZp~{d-D7^qv0nNFfqqAf{jZ^U9*Nk)CTQM+bfcC|K6Cmhl zP*4KAV+ARHY647!6|LMD7&Jh)7=dy;gXI}^1_nkguo0jFka14K^bG-~A~x$lX+{fN z%`gVr$gwamFzPTiSTiu#f|lqpLK+bQ%*fV(E{yg9OMN3rCPs zeZZ!JrvDk|blNa5Sc9GEgKYXt0;Wp@nW`j$6oE}wWRL)vW5Edu<7lwyARjT#k+Ef9 zuq$9-j0R76sxUJ!Sc3yA8X8z&pXk`aeFBRPP0)Qn>I@Pf z!|f+ee;8ycQZH!Fz+g2AbT;pPaFfNAnSsFyG%d`yA3QCb#>~I~iJ60tm;ucvGadpr zVsw7X3(7zd_Y8cU3#8^@WuDF(Xv#UgHrP}~ z5mex)RWUFyTrp!{V6p?JV$fwKppiyUVWu~ISFou%>t|Qcy;9GDP308>-53~Bp$aV+ zG+w~0`UQ?n(7vyUA*N!}Z9+_iok8`88XqGAL#!JE!w#q>BL+3l9e0^-3=9{bLf{I~ zkU=Aek%0l6zCooK$ldJrko3Jg#8fz>6ckI~a0Pi49IlcK5}>fONCt(aAQPy_2i^b1 zIOl>r1A|>sN+JWJAQLDbbF(0)XVB4-Amf{%#w&-K3ad1_F)+-5-p^tJ%Emu)4 z9^@iT&;dX-|qs5pHP8}fQ(?BN7+2sgJH~HdV zsVEj$LMa3%6sL33MZ-+>>cQ!w6r5}?urM&#f>xj~mVvX(I}jgyL~1#hzm}DOK?Aho z2^?9V{hgo~25rX%U+=@95yZg208S>LAOJ<=AE>Jh88kqfA3?=|8mK~8>c+qj4!&1q z`k^pW536VP3=E)M)KGKS85tNhx-l@Q2{1A+faE|ssX=na3>xOph}Q(A09Y_bhMNl1 z=YdYcv<3&LI=Fxlc4A<#1}&3dv}OV=lVA)|1BE>(oIipsk76`nPy;nL3~d=0I3ahs zfbKDhW;9^X05#n9g3^(FGU()NHP9G4D0~?}w<goEOdtlR))zxgHlP>V4TC`42!@FCQupd zQj}W4z?cbE^?{XvK@D_cB*=G(orEz^pK=XJBw%4{9F3C!BGPr86vy z0-<4~0XjKtr4s`KXrzYWB*=1mf6)2#4B&JG3W7#(@G816Fj#?GAP^Z3HUsP<~Off))p7oFQSA9BC?(1Ztr_fL>t(YDR!=?Kxq} z!0-hj2Cfr9=^T8!*9A)k25}c~sf1|aYE&{XFn|J%0bCe>YzG$xG7J)m(;r5fil()? zFfdqy)+RA7WCAxVgIo$27#A~v#536#7}P)w`KxXW4Al^`8BG{8Kmq*#6fV3hpruXr zk)WF-Hi07o6go!W(D~rPz+h_uTFSSDsdaixl&N(6Yf!BVs?)xK7@*tR7~L5dK&Ndo z@VY}>4r-RWIvFr9u%2LIc7@-JBe8;!fx*>5hJk_gB$G5q9Aps#16bV66?6`(v5qSP zgO&s+;TfF;E#^0Ia)pI8FUx*r1_lfFc>)X!oXWwj3=9&Wje#DULGw~M%%A~f&l~y- z3?R&5<_W5lK$y+P(_M*y!F{@3w5h6NnkWMU2y;YxiZU}WfU$<>Q&9#65avkq>=R^Q z0AY?)&kOPl3?R&r<9%J0fdPbh=S-gx4O%D3%fJxJ%fKLZjmh&b69WSXi;H>x6=z@o zVX+%b-m2mZ3?R(M!{+^7f`I{q#jY@UPF7%G0AYz>Z_pW`Ak2T7(ff=50|N;2?`HH) z)?{D+VX>1;-m;tw3?R%O&FHPJ$iM)?g7puXy^o4BFn}=sSw`=*nhXpe%zuW_TSSF{ z0ffa)GkF`yF))Cz*aar7uY3#)AiRA?jH#Xm5Aqd4(+{>dC~jwKHRWfW-Y#LHGdJr(826bfXVW=f%>AgQq#SQl%37tk_-$Y_RMPh%Pe)XrRyQDj)GYYjW1c{wA z-Sn5KvgAZ0p?OH`HPZ`!nTkuELlU};#C|z_;V)C=dI>HD2AEe=k=VvaY!4)M2ogI1 ziJgPQu0UdgFCT(Bej<`MXtyMz69cG*Wng%VBq0vEF$k)`4T+tO#GZ)6o{Pj@iNxMI zeeQ2leM#_TL{Q`YAxZO0fBM^0S<)KR6NXBAAhE-yEB-N!_dJFqbQy{L5Q+T_iOme^ zheM4MKw`^HKl#U0nbCLp+drn_o*76o;A@DWIy#ZWry;SIAhCBMvF}dz{c9>N`5#G$ z2ULbbjgy*Q``1*N7c{sCi{Y^8hHmBJyp>3*+NLMEm5bM}L=xJH#6F0`K8wV@iNt=2 z#QuoH{)@!s1YIHob(km;TM5FRp5Ii@>Zu3efGY*iif@>+OOeE9Be6FjvG*adPfg$Y z&(vB{7}QFD+NprV)|<}x-&9#L7D*@ziCr=MV=}+^^qBvqJd#_G#1A5|&rfgsZz^8@ z5lQGD5}OA!yact`8j065AVz9S&np7iBc_HoO4iGB7aQMPf^XhBBc>sUxwCr%z-w6A#Tt5~@LBcOkJs zdt6~Y+=C>39Ep7iiG6qaUq-X$deGV!n6?Jc;3U))eMs!>NbJ2x?88XxQ%LM>?y~D-wGm5_>L!9mcQ{!C}~j#6F0`K7+)*j>LY2#Qu)NW||(zYNjk{0Gfk<`pFiF z9XP$0)l8YOVfsc^GjU$f?gCgSET4Xr)y%q{5j0E*)yRj$mO)}`A+f=CB0<%=A&G|| zv6GP41xV~VBsTaOBq!(@RKRv@vrA+e7ju`eO9!B-+d9rO-K{0|bFOB&Ifl0ag6 zN(Un(LXjjYk=U(B?1@P1xkzl#t_xVeZk?XUZnnQ3eD@I4UEsTipzN)nIesYnBog~7 z5*xH83ufF~B=Mg}Y*x^81=JitB(^Ms4a#i{44M!QxU>OHzrqZ4L=yK!Vn-seQ<2z( zNbFi9b|(^hDiV94>~uL!vp7Re&^16%M~We_9gx`Idx@ZG;-@PrJBioVBT0j=A%aRz zM-pF*#9oiY-h;$Gj>Nu=#D0#%{*1&1E$3o%VgN1uV_@KxN2Cq#<=Rk3C{Iu1GCN)W zA4wW?y(=ter9dNZP^B73Y%?Ub3lcjBiJgGN&O>6?AhEk3Y|sQ51H*a<2OPhVLSic*vGtJHHc0FUBz77Sy99~dgv6czV}txZ55{3&U|561-i5?I zfyBOs#D0Rr{)EJ40FApsJ;R5@mO)}`X&}|^7Dy6qNbC?Kb`lc10Eu0P#O^_2&q89a zKw@u0u#*^$AUF({kk}89*zb_oe~{Q*pg}gMFC~!JYDjF8>5fm-#Oni)gq|a@KO?dK zA+ZHP=Z8U!mPKNNM*3md$rMT45s4jz#Lk7VLGjGMPzm9H)A>XsHu$D&sAXG`#1A5| z!Pg=|)qF$}|BJ-t)JBxOVn}R7(8@rVt96hh0+HA;NbGbZb_WuBG7@_o5_=~S`v?;I zK8y_-(0>KvFfcHDLt-;cw-hlem+S$}=RrLPzMcrmemVW5h?#Z0kuJh-_DF1BBz7bc zI|Yedio~u)VmBhO+mYD4NbJcFHY5UPLO9?EoR7p_io{-n#6FC~K8eHz-)aQ)-&G{> z+eqw(NbDE7NCg%6h9jtEcF+_nlr48WMX65_=O88+@$}RPQ+?@jFQD zS4iw1NNirv1vO3#)2~aIMe>$GIN(IsJl$5(?0S7A=n5C8*=~BbH7SKg1PT(~T3=BdL4%l6~NNgu0wm%X(dHP8yGv)e8NJ8_G*lUs4 zuaVf_k=V>8h(ZB;c?&cQq>;oGL2T$1SE`^(U7&0Oh&U)=GcfpoIG|}I1_p*85F4r} z8i}0?VuOyQ1I?%+vFnl89Y}2Og)LAA%>ju+FZWphas-sU8hmRERMA$DBGCR?1_p** zAU0I|2#5_8KM7((HD5wvzW}kJj{Atj{)NP52HlkcRU-gmgUkW>UlPV)U|;~>_5zY% zU|?`X5>G*5H-gwu$903)(2(mlMcfRu2qX@5^d=A+s^%n!4b=;}?WG=eEy!h%X6Usb z_mC952C<>ye?V-gW+u=|GVo@91_m}W(0X8S%3}~j5|;+Cq3TsZY|!dE1_lOAka`Ha zo&kIf3{;U5k|KW)8#E)!z`zg#VnfxWf!I*-ERaD^b}2|4s-_;qhWfq*#DG`M4ps97#D<#r zbGombnRq?;@))SJoH-)%Xn@$D#gCvA0AfRpGectgfY{LF6N|c*idtFL2Rfw zGa+nHVq;*q3gSQ=aUaBn9)bPXoPj|Y%6<38f|1dVl|8k%URiG9a zA+dvy*r2Oo7@=y)LE=!Kfp3Qa%~mroFtmcMlYz1)AgP%JVnaQ-9ErWv5>$&qC3b-% zpqej&*iZ|ugV>|>}McxsG1KTHq@N2AU0H-33NXSl+6QTL)Azk*!2u@ zAP&?}TO>C48W^Z}Dw23Phz(724M^-xB=!Ul8*1@%5L*h8cR)A42t(P+z~Z3rXJBAh z59UA=9R;zW7Mw$3Uq@ntZ-jvw^b8~pWq$y%p%#A!u|Zo@85kITgRZfGve`g)pFq_J z)`K|EU=ahcp%N-cYy%`V_^KGFdIyj=)KE_(Hu6m|86a_}X9|(n{; zABYWVoHH;mOafge17*(zi9^+_Mq+OTu|dZpfvPAF8>$|BQw)@S6(kOI1o(CsDEqlJ zLp}U{t`8tZP=ka)H?2S|lLE0JBS{Q$HVh2HP_`yW9ID0~iR}ntgBHv&Ffh1**iiNU zNbE!q8|;XB28Jv+hk>COiCqI?Lk*e_VnZ!k24aJjr86)vtO7X*%H9VOhepj|5F4ug zA`<&Hhz;8I!@$7s0K~3`YJLggK-s@RY_RJX7+65pu|V0pNNh0>8)}ddhz+&O7Q_ZE zT47*da0J~m17-Vw#Gz`!L2Rf)>tjG1s6;x54VB0Nv7zD>NNn)MG*C4iNaEmoX`tdW zki-{(*q}wM3=9m*L2RglHbB^r{C5n*f%@`168i=c`yq%8HRw5r4K?Tk5}O%x7YtNf zABi1|#7;wE=i7nGf2f95kOb5beMs!-NbI>FHdOsGB=$}u_C+N2EhIMhq8h0AKSAOk zHpu@>po?BW90mpk4iFn^fjWo{jRHLo8+2L+0|SE*=&~6o+XEyH4R&7;8!8@##LfY+ zq2`w&vFq$Xrt`ih=r)7sQ6DQ9xoFfY?y=)*v=$c_9M> zgFWct8YmllCk|9iC`b(`{y|npfjCf!G$eK@61xG!hB~4Z#D=P$0AfSMr-Il}@dY3@ zRD3Cj4He%2VnfBZ)`K`ui31=uR04d(4%F4>K;lsLLnQVqB=%nbevV8!AzR#I8ePcYxTSRmBVp480&W z)X-^2>@^@ZG^n>CvG*ad!B^~9K&Ob#f+U~@Jw#%Eoqku#OuSwKbk7S^+8o4&y3r2A z2Cda+U|?`^VPFu3vVB3~P&MEia-jap1c^h{fN#rzvU@<{Q1#P6Y|!FR1_p-NATy1i zbF0fh5>Q1OL2Rg@2awoDL2Rhzb4YCP?Keh{QH> z1vQMI5_TX7&{A9m1_n_QTnh{T?X z#GZr1UVy}2io{+y{VmA0El5JUk=XmE%j%km*PlWXx`@QSip0Ky#D0Lpeu2b(gT(%V z#QuTAW^hAfD;5YFT;ehCKscaCU=ToJOCYgjkl4ydY;`2IJ`&p)iEWL?|a99um6@iCu-nZi2Bv{%?bE7#JA(kl2%u*t3w>^N`rf zkl3q`*qe~p+mP7%kl2UZ7#MV6BhROhB+enRuOYE-O^?+#6Hj`IB=iP}{Q-&n9f|!L ziOuAWNCIp~Y(6Bmko)#o`exI#nRw1kH;Oj%V{Dn;7;Way$#I^60W?ZAX}atx3Hj*? zQqnBb6`T`9rVGTF32=&>XJ7#Jm?urQ{nIEveZwOGmgxl`*@lZ!0=zmfSq26M&gmbS z<)x=juoq^TuAs{(GF{=4lmMg4^n)>G{)`#Z1!K+p8B3-of~YIgH-e~?>5Oq^{){!# z13}cC=?mk`{CN#7GBAKPuuNiLV33^dXqYQJT_E1ffU#n_W4xI^Sb6s4LSCf~XhM1=GQTiRotkOe}Y%Z%Q}w zV|+24F~iKCv0{2)2FRRy(-&o!`7t(3{|Mr;+@J20Y39e+F@0jDnLp!{=?_6v#dO0g zGtkXejUejG^ov<${!A**rYmKe`7utIUYHGb`auwNWx8OFnLm@ji|I)@W`2w|(>LaT zEZfeQYu3-m_-FdWJTq-3N%!gd^30T2XMA8_$e8{#&rF&1V-y2J;q;FtjKb3u^34Po zlcpQyo2fG~=uMBxH&bIYn%ozwq<`kg(76M3C_PO$-cq)4{?E(zyi~1Ey~T2|FBTU^qGb z;XE}GY9KNRR#uT4t5zO1_ovp z)+gd1iv6$%=;|wG7WT!U17sLE1XH9K7+9KxK}UIj>OU5j>G@@53OuVor_<_!F1uoJ zoj$wFOhIcK=v;fXO`uDcczGEZSTsOaSg|B3Ffg!af;NOQGcuJjGBB_;sZ3`)Z74PU zf0>yO(=?gs`lk)07?Y;!m77URU6Ns7U~yvX0I3rcVPIf!g|LNrr^oZ#NKLOTH`8GJ zIDJ{UnKI+M>8Hxg;_8(_4Q_#MWzYo;XEYcXm;{#aFfcF+Ojl%JU=jESI>v;7Ww#jU z@~vzp1_qXMvJ4Dt>IqDsvwJ}IJhAC&GczyL(n0|JVG8~3=C{WqKu%!y@U>cG#GN7#tU72rU0u9fz+2n()2F?Dn*)9Sl0HFrZshD;kHj9uQ$U1wF zZVm>P?HUXWYz|J$3=Axb`5744yIz9MU}FJAC5NE^=zObXpivBg<)BGFX=aWEme$KU-<0=VmOxz`&6Yaw(J0 zJ3$5pj)ExA{W}aSpj$FH3e7+lqpcQWVBly1xtc|rmw|z!wFPu=eLo8W179BKlmHgj z>5f%qQjC+Q$5ffg)^7wA{{o7jrQQOE_(8q_-O<4;080EU0`KJ*7+3|0lo%M;1RhH; zFt7`J2YUvz-i1@(r6L0Zm%wsmkY~7L7#Mg2DnNJ52!PHM;}b}b2Hl+F2Re64z!P-N zlE4$tnf3xtKqsjPoZw<$5D~DR{-erFynd-71B0Z%25ANcDFJ7B&@DO1atsVI0#0lU z46*`UstgQr0%t@R7~}mY1|@+KQ3eKO0TTrV1{DE!Sq27Gf%jaX zJ$sMD7#P$AGI&4-16);MV9*o*Eriw*NKj{B&=$C;#=xK>;4j0#pex`YAj-g?$H2wL zq0a<5f|FZj`n+m0DY0ds&^BUv%*wzZ%En>JWXi_CAQm$HT(y~%W)BYo1BWdWD3}?! z^~4z%IPAb2CT?w6&>#mB=w>ozZgKhPhBaoY^`H}DI0C>bxD+_Tn7Y{+7`S^i7#KLh znLyFWz}*G9N-cuP2vp8+%SbXXa6~d~0EIPoDIWs^M-*5uH}@mZHCoYN4i7hn90LPK z44A{q?JLc|z!A#?+Lq48y-1K zOs)QbFarZeD%c=d?hl}=b<)5bIqqrv3=ACUV2(TkJ1Do!W@ljFn9abzz{tRMjFW+Z zBa>+(8v_GZ21h>Ae~`CiKt3s80;yvFA3w!W1h!g%yBU-;%fKF1;szB}9OX>XEDQ|w zD%?CE*H?h;N#&O3VqoB?1as0D*g!+395qbK*%=tPm^d1kK)ZUlpNTRsa5OT3G9&}{ zevogQ!0H(p*!)33)Xc=q!N9;)rpCa)v6#snbewZI=xQl20m?KCoGc(0a&d5+VXE%~ z-G3DX%1~#)rZ8}C;b36kI0xo1LgMB;ByJekNz!VEIKNe&@7c(dsu&IH9iW_|3 z80|PgxWa5xuo&`Dsin~IUfq_Gk8Fa1|3wIAI0|SQ?^BG3aomt%bK~mDp zUqH7Da)VB6-vprNZ*yj#VcZe!8FmO16HFI!- zLcN~D3C!bUV9N#N31?=|Ia#6-9Inh(Tnr3i;6QW(8zlzXD9qsw4qUMiP`>j3dt1x~ z6c(OfcZ)0b_N5RDkwR4gKyztn*(xo0CN!NzJ^#X1_nM5!N4ib0il$7n}%69I~v7VR8qj+c%g=3f6<-T$S}KO!xyxiyYq# zP@L(p{sGw|$US{xM~Se|6L|&(4hvRUZm8+j+|wVfFqWv_2g>B`tRM^7Ks(PlLLh7l zkh}9BY|u?T9OYm(7Z*nr>o#r%2JTQ$7N}+gl^6`%p`c7x!|D#YFpE0~l$mN-<3Sf@ zaf5Cn;HYB_2IXpQZwUqlj(S#5;l#dq%wh$(r5@^-*&xR-a5Avjg6yBeIvu1tfMY(Z z5a_-ua9A%u*1Zs{8>)E`L^Jm{P^qyP;t>WmO;BTI3F{Re1_ri9P{6N)#2`DzMpi$V zsr4M2pvGPTmFAmS<-iwavCRQ#-omQI%fP^;$g!OjbW9ke)Z4)dF7~*ac<^GO(=&mG8S*qd*$HIQFp~f!V~dA8HXeCJsQ|Uk{FogAfleu)PB%=tHcN zLAt#;jxWahml4$Ru`-bF6l7lg>j; zx&X>0^%uZV&Bnk6+Wo?Dkri~>yJ!T*W!5u%3=CqsLGHN%PVi#ppfJ1&PNZU>6`>s0 zz{yNZ2$c4(gCj}|bU;1F4RDl;b%PSwO>j_)JqHEuEpRA`y#U4VZE(Pdy^H`Q+&f@@ zih&(;7wl37HgS-Sd#qldCZ{7P_djNR!UxT}KR}nXfX-9n1F;x5SwL=OTLh{Yp0RR) zE})U;pMJ5YM7aJIs3>~Jstpoz1)Zo3D%ANv3u@U^W*Uhb9~706<6ypv4Bt5DbtKK%4C)Xe@*gQUvI* zfll;h;=TjQIJ#iX%-o5f5>$^Z1JtG9wvl0A;LrziSQ*%4LAl6)4RpH~7Ym088|Zv* zZZ%L%YYNuPz`Y$5DrR5~BllELnPbidDp{DgZ-Pp33pNGNeK5=nY%4%TpC#K9eg+0E z84g>vN&yB29?)G`9CmD=1kAu)3yMN}wgg571_ACWP@Fq}@8ywzSmFq_M2h=6NSPCu zBhA2e9TYsyYKS-IS7mYdgWVwju{r>(SqNfMAebY}z!m{=M-bZ~kVz68 zp=@4)Fn5I2LmUDzDjaMS)EyCE-E7?7K$##CY$H1ZTPY}VqS!$D54prSV%XY2jsjin z#1RWt!obbO25Q-{@qqdW+#Ko*3>@)npejI+fem!$3r7MQXk((N3`Y{%O+kiw1~Jf< z4~}GTn2W6hgz0xA`3gIFl29hU|U0x=bknsl%y7}$zf7#KJ**d_}yFmQ2j zWPzIr+@QOQIkLg&gn_#k6t_8G2^I!UmYbmN-6Bw0&1HKEvR{;gBcCl%2$q!#z=;)- zWedT9BlZ%M1IxhaOKdZ!ty|7k#mvAU0lF%Sqmqpuw1I)m1*E8oOv&ORWq>t1I0x@+ZB+bEI~#8 z6gFPaWqhC;9r!@GmaiVfWZ+~08N;Q(F`I2F=n|^kpg5lcW;1YuE+pZY%QhQyRTlSO zkT>VCEd-UF-0wlzd_LQ9&{bL7praEw7O<@a9T(0W4=QOEvVqPH7vbIma@`WPox%(Z z65O9a31}JHeqqp6S)45O$y^K!oGjD946P zY=1#z#C}Nfu73+EU`~QLTwEMi*>Xe}7;oJV3@o9bd#{W^vBI)Pj)8&G1I+v|-KWb;QlUVUfq^?)oPmL}k`W}%z`a10 zfq}CM%wgm{HNCaV%z<(B^kZFSYA&EXf}G7@DL(FEP`ADX%;9HXn+!6!mGP7a0|PtA zoE}gc4cb}Km11Dvlms_)*;1w(beoCS-&1E`;IsuFSj~0|WT72|y-S6GfzyHc3h45% z&!P+rd^14A5)iQgM1bzHfm9t_ES#>)Tw)9i+~*}37&zU)Y*2Kb5M^LsOHgHC;B;pO z8NntE@|`EMh8P2bIH;7i5o4%_h7~Bl7=(4WGC+Gsg-Ss+b|$!2DkKNGtUC)N&mwdR zbP;woNC}6~PEeO42PCcm@n|ck?F{m$90SXIP){w_MvQ?$_y$+~UC{zaJ7TP1SCOMb#ZlU0bSK43A(C_t8+i-sxBeWUT&^# zP{Ai6~<{AiuQ;RfEdFSt~&o za|vA&XJFu(12S`q&@_;5=PJ}QGB8{bsug2k;F<^0d{xK|6khW|{qbv%FaqZVP#D=V zuylYbiv<(J7#LV$MHv{lmN0{^zXfeLg|rJmjROXj3!skmGC7cxo&*B}AE@UDmS+&Q z;aa&+f`LJ387O2|@i2jEI-ylk3=CYWLDd1H&?nFx=4(J~b|EQQ1_rLRpzz=oIt4Ow z9Vn>zgyKNmz4ah-1cbUk{@$=0bc2^<0Rz`YkP9S)K*#xTZ36jJhJlmi2Ph4(fLzI9 z3^IN*$W_7|T-!fNfDWPt?PTZL0Wz9F$QR_nogg-okeMU{1J^DPn?)!G6mz>lY&Hg# zi$V+xTzhv&Ffg#JWoBUDIs*zh7ClgaTn00>L6LV0%mf{S!}SxSk&B0mg)vQ%fq^>- z)S_SovlAG&ok6j}#t2H4EZjz*=wb)wOAc-;Q1apcb2u3|SwMlp#t%}!$p|_|hl`Vo zn{gY+K+sKWTs(}RkYeBlod?gw3+6C#hfX){H&d*ykYr$B`vXcw;$Y*X?l5x6fsa7r zwgSbyJXn;0JC}=rflGxE6y+@3>Y${i4pw!CI|P)aG{E;zJ>WhK(xb@;3g0Kv6G86R zVFZ;KER50}pt#WmpNPf5DD5E3z`&))SP$wW@i0oS14W`fqaEmkeMV^mbp{45Be2aP zjMCuVoH64c@Qqy3plj#3Oc_A~pc0JI$)H#a*I-|4+D+2?UBV&#v149O*H0ab~ zE+TH-jMW)sL1~OT7L>#^7-hdQF)(n)fn+op zW%H(=nP?^{9VW)Wz?};c(_xeajredEfI1AijIy%RCYh-*@=aHtWF}XC095aTyvhU) z7j_1gPLQ)JK|vr>!N}dBFUP_ZxAn^r4pc7NLr-8(m2pL0|N+yqkxHl zlLa);&Qc2shr_2q2Nm;hUnvL0185YU`zk2=G6;eC)7&>fNsWbpWfREaTVZkx48kSc zcaBe&onj_a54r)K`!Q%Zl|u-eUY>xgEC5$F+|NPmLIxI3Pzb+l0!1eysQvO0lw@Q? z__;qXQD9&Y`UpzUUqGS2AhaDcF#8h}a4bTgx|sVnD5h+-x9Ktc)Pvm~x*2WiBpo zsbS4M0~888;F8XUI}H?Dyx=m>f%`8=h7T;`!u?r|fq|PJEaSobR|Yhh0G9FLUIB8E zAh-w&;0D#X+#=wjGKAYgn1R8UTa*#x(GqS@_025?c3cHFsQ%`LT%TCQeFqc<5{#=r z7ja3?0Od7F#+l%YxTOC`Gca&VF@i>u+4-f5r=Ol`CSA`9vQZA~em;I_&?)=ekP@Ar zU-}A2gCe-l6X2Hy)%4t2V4fhq^mS0e)CTi}_@$fV85p>Az@`ZEGjOti5&-*gIR*yM z4M5}1#tBNWj*Rk}p!&>#doiO6D7ZoQBy%qTd!Kw z`!CP*{u2fg)0a&%ld2B~4XmsKYZ2r=2I8y-bJQWN4$$pYU^_(_*bKNB7`QhwUQz&! z*K=(pa;pg_6EE8_9am z=qk546R0>`03L+pwqODkhYPu%fiziyH7(*k3d(C%V9sK05s-uI!LD1v4cZmW?EtoQ z8F>DQ+Yvnfw4D19D5#yldRB0ogW|v)%vs3|y6=wL3v@45J;N#<(9K)izMy-!7}iK< zf&$-<=_B~&E$JdqW(xxwZo()n016ezWSJ?bEdfgXoGhT5=GZ}H?`_cF2Dr{-0FT#j z$1q(0HDp7%)4?}cfd{6!Gnqhhmkit;pn;rhC9sPexfg?YIbe&NxHp4RPcG9EMg|6F z?#t8n%raB-f3Cv7z;+O%3Nm-aWyC#$=_Dvr+(5xT6U=7dE(RroSxlgwupIX#kU6u# z;iSR64pb-41#`5xHKyy#Hj}Iemop2&S7#Y;{{z)!i@@$NWMBuG0J{L8^?2JQw>eY*ne1<+tk1*rRc7nGk?GCfsgU|@>^HC&E> z<)u_qxIZ&xsex|!0bR4j{RJFA4BUS~dGRMxmL>y3nDh!z%i$MO>GW5#&6MhQgChMO z6R1n##v|ows7U>HhQ+SxYL7N;{rT2sC7a?X)W3YlvItx@vihw7yLO7(0>Ony-$_y%o z!Z@TsqlnyMV97WRY0$_aw>a3)1P97I8@50m;dNc_kdu zlAr{t%nT~HD>&ppH;8cSGanTO-LfUUA5{MuF)z>r-LfUkCl<`Wz-_|34SdU%^i)tR zn=*r{+#TZ5u^^|Jfjjp%#HIg&G@65Xcf_S1C*soT(_`nF zNi(WUubgWp?Y;pN!FJ4`>i?yU0I`do3;vPM&Vepyc^RTzWdF z?sW%W&-6!JT5tO8xn|P!exN}20y~gJLOLCk4!yy?R*{fi0xCg#z=o+wNS_BKAz$V_ zpv$r(r00O*-;enWh$kftYHV`*Gw)YnV0fV{oeIi*0nB&6S7%A@2esmYm_aRr56aT_ zKxsFa8C0x&QjErNZ;hBXJFt? zV15L-NsArSmIftMXjbB6apPiOUY~&C9*p16qe4OIK(VX=%4LjUpiIUzF+c^h z&IEKT)O2kI235u=rilRz;46T^)`DhuLDrs|?y%5IlOHSwI$IJX#;OBxO7B85VOG%X zQM%KYE;Li-1}V~90Cq1#!Hb1vVhRU9i?U8IRq22RivNRvHs~@WtzY5{3@j&^CQX-H zWG1c#3UXagyPZ*90JLNYd{u{@DJKI12($X=b;vLQgi8={jP;JgT6P zT}G%H2GA*^P_`%%TWR`Pzc6u0@L8u&>2xINlIexd%)})@9RQd~vyr5iPha@V%w6&? zk`NatAwf-&n9lgzOnLf?Iwc-n@HwVX@ucat&&|XoTac83&oqTf&!3+A+)SAle2ytp z==Su+SMlP8|B!TWfsPP`N{b<}m5|ta(*x=`NB+}anAJE@M3Ys?bA2DFjJO%hNR##5}R@Q+ZSf>o`s|_E9DrDPWOCerdcw{ zOU5G!n2Z=2pgvhX}NNhtSwk;Cd z6N#OK#Lh!vpG0EcgRmi~{2PP=_7l_en{Um6>#ITMk3z$%1BrbMiG3f54eEr!y!IMN z{38(SE(jZP1c%u4jql9FLxUhE*mfes^uTAhr^3Ad;6qKJ;^0F~p=|J>rcm}?B=sl32b@ABt|Cc* z4?Bg5gAY4}vcZR%LfPO$O`&Y?p{7ta_)t?Q8+@oKlnp-A6v_slX$oS4{0~0V6vSa* zU;rO#3T1;2HHEUlhnhm!;6qKJ?1f0B(OM+-P9!$yWO-QhT|^RpCl1;Z3pMB`l7tB8 ztWc;pXr&EIGx$(bsJK6pnrI|8sP_OnPSrqN(73Bf)781`ZWrbEg-RyKdH|PXXsE`B_8+0ck%o@h3ATBl zGf$z0R3ovcBC!`Eu{R>I?@TxRV`j~$Iz9J~nK-Y5D#8Ok(V zy5k!b5r2@x!N;IN9VP=hX%xz~M`HURv7?aK;42PcIS;f}A7()dlA=jS>;*{dbx7>EhzXGrWXNNgr`(2iB8s|7$OibC0PNNgP>wiOcF1Bso2#4bW&Hz2Y5kl1rz zY*2e(6^z5cz_0^}eGG|x1&RF#iTweI{SS%F1KOhm^^6n}TLX!020juMs>lUNA_$3{ zfW!vhZv|CfgCyRC#GZk~UWUZpg2X=-Z`6#fhh4B&%Np@#kkOMnXn23F8{qmZUK11IR(UMO1xBo0+C2V!$W z)N3QLt&rIEAU0IJCx{JI?^h4vKqVqTY^X#mhz%7_2eF~zIUqJvybQ#KidTc!Q1Mm} z8!FxfVnZE08Ho)(gq4+n0kq$cVG~G#72<>4NNn(ltWeFTK;lsL0}z{a`Zl$Exq2yW z1_nl`xIKssb%ZB~%?>fsSDS%B7|MPr^v7v?rA+e*8*cl);)RzrN>={VxB}nWIAU5d8v0#%xAMPI!y27H1}s*GyN{7`FqBM>1Vmj{TW@R%W|9h zGhUdU%WbaB_;~tEZgXYUkZcBq6VnfZnCS)#4E56;Ww?Z=|KT6m&aV4NoL}7 zGahp_*6St=3>x6=ztbz?$^{sGrnmB#tF!($VPKGe2p{1w7hvp|eifuk+;sXs9&dShUb`1BrLa{<6GgoJoOlDx{n%=lgNSSfT^j?ri zOBw^ip6QIwRYj+t<1-gzgX}M!&X}Pr!D3`-YCQeo+%R<}mVoVA{N}OR^|Cx{jSLJ; zH`tOq_Sn4P;afP*2)NiNArUM!i_kbxoTGFuYco}^3o_sV2ZMBTSK34dhDkTsnmG4#HA{CidG4`t0V|!u46&n$V~%1)D<)*fugS zC@fNdxNglVMFs|?OUg=2zrF=A9n+rPSji}D+@=C@eA5lKCXPK~860OBd8Fa~5zAsX z;$i^n5?5mCa!)cfXb@TRWBUJ2Ej2D71s4SehmtlPhUw?5%`LZc*qCn-I>SC#OiLuz`$~mi-7^UOIsVXw_6f) zP!o%(I)fVnlN4x*g_(nuT_3zn`?(fqe>SVBJcwf7Ed|}CU82aqz{awXfq{XUk;6cV zfq_LDv~gPmRCcl?PH&AhR|xf1U|?W|?A6{S&%nTFnE}wX3Tb zLGw-AzMvJHs~K5AcODx|{~Bkm@7b)(z`(K|tdt$JPm$#dBgmEPptJi~eu3FM>@5En zS2Hm%@PSrKvixVv2i*wC3%UfAg@MTew6lqUef9L*cyqmwcc8m>g|31MCm}9l&|duO zd<+cCLZE7nMJNSyB_RXLCRxz#^K+ox=WEnJyU!1UwtxR%VPH^T)9qtsU=W!L+D)zp zVls#I@8QCLp$i2qzysP^&BDsSz&B<3 z>O^y?`eUGF{6KLSz!A@V0JPlSoC&0dfn5T$kKKYvfR%xP zhnvHiX&T6+T+r?S8zzu582I*s_5;|0IgEVjpq*QGU=9=CUeLx`dnPqdmf~9r+Arh4 z^gafZ*Z3ZTOmGC-&C0-j24smVlN~Dq1G_tD|55PY!Z3&BG z0+}hmSFFXrz!492o&+E0pa_mcrtP4u*?i!QHA!Ftr1)lm9G48{Nb{L;FfeeWFoAa2 z$nb#{By*&KWn}q4SIKdtfjIRHa(sHAT_ous9)mms2PpN(B_!>b6_4LB%;nkB8q|i2FQ6An4&=D9|xJw#SBV7?A4$>B;3p(-|>L`q_~Cj+}7D1SIJFXv!j;F754 zaAh_JE%E^yZ_=z%B~fRusVO&&j~RAH~VQAOIp5*jPZeuv>sqr!Z>{Cj)~RC_<-9mq;^L z76jdc#v#kP04BU|x=)(9q~JeLY^$=Kf(gF`sg^NeV3!0%vL5SCkR5zn3=9IG)P^7! z*wa7-g9WP;XjeMO9*gP6(#+-R-C02#cF@iPjt~fY8_4N-5cYJCedS;_4`}=LX3*C2 zGoY2~)vTauj)8A0s5q%%b>U)QVB_lnl@_(EF`y+Vd|{xHvW_(Xl&JX*fVOAVvw{jU zP6qaOAS)VJGq~y*7!8Q z82G?0?17pDF5`MxL1i2p-w{wr-Ny>b|D1etK)XCS`dL8*j1S*ukb5V9ofyCe8ldKw z2(~1Uk00dRNnlP8-)~SEHW}=&V7|?u@R=GdR=dexz=>~1z=I4R=WC617g$UgY9E%{D`R;%Mc`?Kz4D4;7 zy^l*+FM@W_Gl5F@b&wbYZQu5Wo4SeB0_1-NzB*9dvYAyHwA-73{Vz!K7FKm01_mC` z_U#ss25`Z*gB4ux@q)K+&jU4bc){DZK}mTD5$~fTRCpAfqoTkOC*Tf@&s) z>36csdFu;w7#KLdvigCfL3eQrfa9562UNpzuz`$VKLM&YgrRIu!$bni<^gTuz6#n? z4lW0@*g)j~1Ed_#2CHC%lmj|!g?tPQOngf~ts`Bq3^U&*P)VxCR-Xzwe~9lmXoagj z8;HZoz}^h1jttmp`4|{@K%2PbL7U4zfdbYPteb&v2`FsLz#K+Cb&zIrHc5<~0jQ950&}Dp*g?Zi9L{W@4e~soP28J7E_4Ou9(OiSiNe6A0;)tk*g%%B zKuq!kYZhT(Zvz?S#n!~nz`#=v+Qj`A?kYd91_oZ}CT@^B1Rz!ifOQK&j0yyEgc;b~ zK+zP$wjX2^XcM=)00RRb*d1XIcR)-E2m1)>jtH=3Hi!%BBf&PZGq6j6Vke4?6ST`6 zw28Y#fPsM*yyrL;tb~ED5wuG;jt$h`5#ZYhD(~XiKox-?1A8o}q)A{425r;=ZQ{NL zT2I~$N-N21pfKnD0?IBaY@l%BUIIEKB9#qf0e3yTQW69zue*=HO%Y#<311~wLuo$NP3X*HMa5y&B+J=}4i zC9L55T)+lOtB`zK2o4-jKCEZpC}RVqFYarga{2yi9bldU1G@~Urs-mv3fkcZ+QbdINf*4EkE0iCkT_%$H`pNd3Q$ed&vp^y zC?ik>Fog|t!!Ey+5Ca1^;|qXT3~VeQQ+PmoxIr7t`4~W{at<4a&A?}-%)n63F&DgT zoP`f`i8IGMHqdps9DLV7;XI#h31|;GA84l>#{#xhAfx$Cf!d-A*)|9~^36_#~Lk1KNvi2->R--HQ#%9}K+Ez1ScQ6CY?q zk>dt5y@R%YaohxR*!aL*uUl-lKv|rD-5NyQW~&F~cy`cI1C9r5p!2@?lRH96SWUBfwd~m@dM=z_$mq9lH`d*ucOSs0QBA4N}g? zmo&Ynz+AF^2Rj1;XDwI(D<3n+xH>S0jSsZLnX?|uVds;OVPN2FU<8$m9DJT2J&oXj z4=z3~9tH-^CNPJGF9PJ?X0RSUzP&mO44f@s4nG5X0BEOoE8{`XUVawN4o1+;#JoAv zRSL}|>vMG(7&vsXWFuyRRk1MCv$22*TJ|WA8M7Flg3J))oXh9~ zG6QV$Jg_zfJ_FFv0rSB_NQ?~ZCqTiqfKfw~fq{pEa}jv|CT~t^9s}oMsGSZVKP&-{ zA+a#9KLIU{Udk8&QZK`~f^jFv`~X(a2|z0ulfgqjVBM?0x<&ZFx>tjBOE9o61?`?+ z!`K1R&B3{j@f%1tXx$0tda!y1h}9dw97c%djbP0z4D6FY`{_3^9))P$!l)+3z`z$F z$iTq4l@Z)kW#C&S&cMLA4J-o+Rgm%Qpvr)AJ0p`A0|So^=T64gAZ-=`3=EvRz!Av6 zmjyahU^iHTg>RQ30|VzC#*bnQ3>(61`G_GSHRlYtwHP;jK<;&4E&%~Oaju=9~7HQ)bAH(VBnjm$iTq)2CR^Q z4>StK`4*f;82M&`0^uE4hKaYRAd!LdJtL@UW9FNuz`(%yfpHcy0|O6VGib!|BO}N# z9lkn{Pd_n&Hc%PxIf0VZXRrY#3~Vgw;tUMzQ&brkIKME0oKepX+O^Ed2=3m43lh*C zYj8or$iT(|8cvj80gdQ#iZFvVstYND=B0$bg6>cgY66{G$-w>-RK#D}rRnK6b z$T6^_gSLO?f{Yiv!Br2sa9Jc8q+X{1V(2bV<<dz(*F$1zC1QdCNqdQfc&=;#AXtC0ovWU3&ds-Iit(KP|vj+#9?D#36TIDx9}2l z(5w<@&;A)u(6Our1;}ME6V$ulx&>xF1RZPf6Qq#`blk#pX$A&9P&LlQ$_QdJ@PT$u zaIry3SiTFQ3=CZC;7rTGw-=P&IKUiE1~!)I_7&!=wpkz*oQ#pups@-rZpP;z13@JR z7Z14PVBq_w%fP_J3+6C_#~!%&z$FJ0-=yh{73Lx`pygxiUZAui4mKQe_Cm5O0|VcI z=^HD|h3i3a&ceq7I$=Sb5hQVkZyqS~X)tEWGB7;gI|MohLlayCJ&}GS$H2g)!w4!Q zSQw=%L2;uCZa;7^O5X*AlpdJJ!zir=N*DT!`LYZQ0*unX4Zx=@fI>-xQF;R?zZo;? zN;5Es)-y_jmRxX|GJ;0@B^aea%XYcU7@eiT$1Pk1S!l@!T6m|yD4h#RJ=S3FrZ7s2 zgUSm#FfWx+Iuew->={2xGccqvO6!8Mg#*~j>5S45praog8A0pnK&LH$(uEUvzjO&> zy>tMm)NlqzN(H0z0+731z>+nL(o7&fxigl^f{$Q03d-1CjDFG#3^y31uYyveHzVjY zlv|);)Pfz9@~*OgNO@389TZ)ypc869If|2kJq+X~AIATnS+^OW9do*KWEp%II6xC* zYhdaeAZIY#mSbQLnGf2j5V%UlruFLWvxNeB5@!YO-9+m>AcnElJ$2$n;~;SVmgenpaEO% z0?>G^E~9K7Xq#yv$ZdLzvL>L-WJMrlCXBM|pkdBpkc=s#Y%*xuUkOOYno;%>$e*Qb zObiS*jF3X8+@?f|7_0g+tL#>g&EQ6VD23Obdb8zgQbk^@rT3lg^wSq|zv_JPDBMA|@` zB`1KyV?=mBd-x`T#A`&(fcET728lO_)cb)nOaVzO5J?2Fr-3Avhc=H9%7TUzx%YvFPKp?1K_idc`$40o#f-9BKwdlmiuMvv;$8w8T_{sv zU;troJTNh^v4G~U>RB29`v0u&k5pt-55pc<7yCJ|_$E(R zs56(WUkJ)(%#6&63=AfG<{-ta;DXqcZv!YnbAd}KYrY+zpyC0StTud(pa|y$m$?pn zpe8;yA6UkPFVO&eyaT8-_TVcAZM78u%lPosf!rquE@T7vKy^H~2&ibTX9(fD3fj9V z$_Vmy2_LArz%2%LV+9|my}&IF=2Y<+fkH%r@wO5JLyhz#(4pFrjG)QEKYY?(K$}mc z7(o+G?EKO%K&eXxtc#0Z`YXtTvS1z$zw{AM5XgZ&#m6r#q6&%xd2ngV&oAu+I^9AM z%oE_31~oXiwZJ?z2pPb0q1>mziv`&D9)sfN44A_X z9!cXq3s%O#2igw6eGzOGAD=WRsxE;!{CpOm2)_bWCcyW6dS;_JPd#WjjQcJlXxLPo z&l(gE_rM_}!N3mQ=KX*%R)v9qy$)o~Yp^+xqai@kynGg*%=L*8#Ae{j1Vzbb#&2p2 z3@m&Spu!k>Gz8y2P=@&m_9zdZ7AS>(WBj8A>JrYc2Zh0RaEg=xPc(D?0CVKP4I%EI zV8<$eCz`o`F@lOrHNFd=6#knLwC+QbPX$zQ{Q*17lCKt2P4I!|YOVN!K~4|=&(+%S zJq5X6kO@>#*7AYtNg;4YN_#4w11S3_fO*sS(m=7G2%h?#&bJU$0IGpGGx#_Jr_XCL zm#FUnB|}ZH^0|ENAPcp?D(3MP=bA8Zn}KEKgQs@5&6z-@@&fP-5Vr*rs8n9a2Rcoi z+Y+p25uY?DU08uRi}~(@N(_6j^Ox`~HDX}kb^x2U3_L;3?FgD6uV+}!w-V$TC$Od! zd^Moy26r%LC0_=pWbtD9s=~mqiWhoz1Slb`k!}OUjvo^!LFq6`-vs5^FtFh!jMAW9 z8Fv(zX9}t(K)HvF5+4d^CqXIGjM-l0tGq)-)B%{|6~G5gh{7@V)PdiC@Pg$q@$;2wVF%UgRT$f z{>QYKoq@rPMcN9KA^tNx)@ESvV3B?YYRa)Nztm;`olEf^l#^MRe`86%LlZcpXM(JdU!P%GXB%zG{_ZNbh^&%kX9=DrY@W&{~y2j;yLm!1N0DP%Rl zD{*OXCUFH@@mgFOoJ-u8LAm6Oxbz)R`@)?Wlz#q*OUHwfs|Q%+UvcSJP(JZw2DQrm ziA!^VQj8bagDeu#cjOru>bbqa!KNZ1Z3e0?e83vjB&4T<8d1K?syYk|8WPe)pmgNN zYzpE@N%MkK`ZI&d^cTv~pnYcC0nDyC3=D6SrRS=F`YB)wKPXG{gB%mg3@VhrDNEOi zGB9w5f^GPzEUf@Kt)e~*%>AV-4O)l69S-LGR+hdEio*zSSo~3zJ`D=|NHFiOva}&6 z%SADR`jHGO((^&ZV>DQfM@1Tx=D1_PJYE&)WRMlHV3h(Y(x4f9?gVCU9R>y&6$TDa zf8%kzHgwewsF~{wnp*&6ZcrMBHhwuAK$#shUJc3c9FjT=3?K}a2Ni{H!P5?)5|9H_ zDuTiYEXU5k0TKj-3zW~s@*6ZK3+e}g);5Dg>ls)W*tdb2>PgHKK-a6VfKneDOR)|E zgFI+qnJ5QO?nWI329X}n`hz@B%alPRpM`;eCm+OS67k?yICx6_=rAxSE(MuU3NlX70d&VtnFVMqj$#F9Vy_&eO>ruyZBYRl zcT?N|vZNB!%w}M5(PLoXsotZ*z`zbV>WlF!x3De)19(tSNtb~^0Mu1xP?7|#2w%tv zT9~TD1Ui)?T$h1C88jlxxR4WMJV-_b)U{z;$O*E8F}R*VRb7gKfl-7PlwUydpj)3A z=QM$I-Uc0lAi@hWTn{t`uC^JpU-la}Olcki$dV8}1_ou&d3B86xIye7CI$v&&`>Mm zH}C}!AD9>z)Qd_O7=M5@$}lr9fDU?PxTVX$pc%p##c0T&0V=6pf%uG3OdJjj8k!6Y z48LG}1qKZhP!`i;V9;cYV&-CCV$iT3hd-k#3D zpf!bofdQmMdj;s26NnGjM91(>=j$=&jGPU!u@#(oL2;PH2#T040|o}=|EvrQjIGQd zb|D)BgYtXOhQ&7UimAD53=AqCKvCMxJi&m0fiXn67j!^C2bjmn&cL9zW_m%7xvaxe z(9KHS;9?qdTAzLx0|UdMbOr`418|ful}Rw@XEHD_oJ(h5kcEgbnlR{BFfcION@rlO zoqo2*T)O^oIs-!}OjeUIn$eI!e+g7c2}GQ!m_d^ z3M9zD#sV5kV`Bl0bSg!GHp8q3)!Gd2z_A%($iScsT6xI09y|npik*SMpidg)(2X1* zN%aB-#!VccIE`D{)2>3G*c;qCSwd!5d#B*3FxLF#+R@R3tBD6IH%i)fx$F^ zmw^EyQNqE%VD=rf+xjIaP#A+5R40Ru5-|q%7eUEsDafgF&Kff?D1-XnjK<)${8SDG z24&FDB%`qnxZ`jhmM>2mRN8<-9+V7=K!MBX04h>IZ6QN_Py~8`jR)4J36a|OC z>KB_bFepb(Z=7f@#sy-VgW`DS^o0}6Wg#gQbSW*!`N5_T=LgI(7q8a>-2ewJL^2o{ z7&I~%7_>koH^_2u7B$IWU}!RhB_IZ^ItB&?kaFz<3=9kokd(#DwM+|?GbaXsJPvA0 zf`?OgnnJ5@5eE5{rVI=gPe2>tKEs_2%3KMIb9BJFX1T!40+4S&y9^lTFqtzjD1%12 z8M(mIVP`lQ7?eTd*^J!Gpz&-_#jdAp$iTqJ3)ZR5#lQgSnu5zgeb77_$g81d5U;+S zWG-9}a<+af0|SFk1_MK(8Q4#tVx|Bp)B+VUV9>8(U|@*IU|^UF6*2^Qub6>BzXz&z z160C*L4O`p?FpC=sPr;m(AokmJG4)L5@9;S^x|peBGV^NHW#aRQ)FOZbO9%5DRA7` znKLlxgASSkIZfLf;xq#WEzo%%DWEt3<@5qj456!=&<#$a%2_-qc&N1&}&h_C`}PymJ18FNTjg-kJ5uCIZ_EE6a}M}sR# zaFl`!0Oubu26>R3mKC6+oC8`A&5#84$tnxbt!ALToH;C@^#JKy3=AsYKwFX_e8ylE z&~-(Oxh$aRPsR|HE1=3Hmj$GcG1LHDBjvM5fT|?SjMr@eaia26Xmn~PK&uE)<|_eb zK66kS1WmtLP6p)?(D9HA43EHW`)kR-pq!w_z`)qY0-E~l0J#k`@5tB(UP-_htOA;m zgz-XDK&J#U_Ooc*gahJZJeHwEqG$M9jdz1g`j3S;GQh7dQ}}a)BB+ zpaOpv*u8Ar3=EK9fbbbZl)=HU8ypM{AX#w1y&JrnhcOINaPMXTO~*2ZLjq|JD3F2~ zm?knnB6J^8DD4N^lE@7Ur2}AoJvTIzc3FdyC<6lnXumonH-j#<2BpwHR)|m%)&iw` zP$=miWME+E$Y5ZwoW6Csxsha`HEMuafi@^Hl`>>bn_(^jsTM$Mpui15qv-)N%vt?F zmV%SD6oWh{d{k$H8g&Y+;DwM3kh^3V=Lp&`Feq;XHG36UL6zZLP*`MxLQVm^^p-JL z8&q;nnZ9_2xt2yUNOd46^pnA=uY**JNi#4oCL^nUKmF?rbFKPyAl1J?wpM^ugU%Jy z`wiNyUIkjH$^cqS3fj%YumGMh85mTbfhy*SU=5(M08}M1&WW*QU{Kx#YRN%l%6J$U zR6rY*7$<_)0W$`xoCDoVcq=QY6$5gIIXJf+vSnZ}k2hps05PBmA5`RnD`q4U0%n;@ z+JHjc`U zKNEJ2EkxrLcw>dB{Fa|4w?x$nC!n((SfuV<&fx#HGHiGdQB=*8V z!FC;N=6zlU20d0#gJpWqY;$SGuha8po6ClR7UnSCW(6(T0bMd`13IcuhJk@W$ew{g zJu@qtf$={pXg43|Y#|04&`F7)V!;3|%fbedH302Iu>qX~2-<4wGyMU`hOFs-W}C}0 zc1)L=V=imC46daHtYra63#e7XZ~!hd87#9OBxA$D%D^DZz`$^CdchoXS;jxp`{uwJ zv*2h+XJ9aPfaJ8(bIgSm*MKUZm5dAw+d&LJR!Cn%KY^72+#RWbsuh`QE)2444)XZ+3r%UN^5NoBSp1A{U+bicEJbO?wuFhD~8 zI}0fE-NhLg^gxTy8GnLx_J}hu825o1jK5fxP2W8i=6qNSC&3Zo{2z18h55i`1gM^H zvSVQAoGv-fT)KV=I2T1TPh3#Xz@Wnf%9SSY+z#6D$T(+_6U)dus;h3ml`3`6i~U1!)pc@DIdnsLrokfXsB z(-}5U#RO_uDub5AFrEP~p9J0Fs?q?eoX)U;YG=j}m93!WJd_v8V7Zoufr0TC*htU; zYK(K7of#NZ)`GIkFYq;2j6upgdZ3Ntzt})hpaWZ#T|oV;-(da~2?ho&P&|Nwok1Q{ zBp8A&wq%q9^)DDe<1~zOI9(VRRCqu+Mv@(*f-wkU1cdihf`P#p+)0yW2X(8NCI;wT z0%cSPS4@(D!3x}IW0YYBg}lBV0|Nud=Lel3CI7?#P#33|fkCShS}p2N09A|W3=IFB zAwfQ2fw>ersMuoA(VM<;fw@S`D;EX^WpI-z3Eck!ovft16I8k^0XGnIiNyL-vMgr{OO7d%{5sMXMi?k`!6(?sK1rY zz;M+Cv;~hDZIWVOPywemh%95M z!BJ4#&z=*M8ujWx>BNB(yvYo7q!XmZaReLm800pP!JrQ9d$7}@84W-Y$zjK!9g5V> zD+3P$l+=UdiWxx{=YobQiom9TvI6Ml8pb(w?hFj}pe?zKMPR3?N;5D(vO*DOJ;>$p z(h!$Jq#LARg?I^A`9csMoCr(62Je@K4pc$7pbe+SAlEXMf~A=z1{er}dLw0=Ad4Zs zE(iNsA9N$}#|#FB!)~zfmITGF8G{yRJ101$fVv={65-eMhQ;Qp+Mr$rs6`;`4$=|L zXbAG^!~g~@P#pr+0PRyScul{s*j$zG4K$r={{tmCNX;y{#9X>wiwl-o1i*uST3#Se z$7eDyYH@+sW-<&6%Ai&Kj9OfvKmpyA1PLVw|FsNAJxDdE4Cj$$V9-+nou8otHa8T+ z2PX|(E>O}~EX%-P2U-ius0TKUseWPrq-NCT0_k^_gXI|mE>ND)1Baj?SS_ex&;#u^ zWrXlS=RHA!(TEF_c+?9F85oVh#%z;gV9@gbo%U)1=HHQHV6X-Ckh(lTRVxEy9@s=y zc?K~C1}#vX1`ab=c0BF@DFb4cnoF{Rvd{DB)k|Te?FLW)rZX_ec|sKJT52u~Zk?HX zqQ-^34kH5tD3Su85}wdV()R=%DXh!DkPnuKVlQT}P$^|l1a%>c1Q_%qq53+&($S2@ zP<>hx8KE^RXeTr%HS7ngh+>@HzSx|9dh{}LVMvVty3++D{|)NK1En#%)8{WUXMJCh5PKlDMlcTSoY1A}@+1q0)3E>IC{Ee{&e12uo< zfD;Djbb1CuT~KQmvvi!d-S zfC>l^Z%}MRF->#?_qIX#$)7>ri~$lQ#!y*Mk1)EP(GncO4h-O&2#T^GWO+slm~;rV zkV%6|PjqCk0uApm6*JUBg&_UmiH;1~piz=P;L;jgf-ZU8F-9UZ0*8r|l|WMH@nu>mw70ct;kM(5u_gqXP)7#Xyk7#JABr_Wnq zu9(a3$H1Tr+RMPm3?3Ua2i+kK+DQ)OGX_I!VdVfhCRu@j!N3>PcV*)MjSE34Ep~9_ z0B)bl`@tL5($I25-v*iuHu*rZf#XVZ1xVrpr2|mndkK|kU1=`N2I_wC`%a&?(p*7X zB$I(b$rl_wj7AJvpdo2cs?oX&Gy4}+3%+5c9W%gBL(pc$&m02HT&4EiFBkdEC- zu*ovoa-gj%nG6gEq3S@RGK>ZcTA{FvQ@{vmlKz02JY|)+a3HiwW#UK%#WQHUAKXg- z`5N3y5M_`D1*qXnP%Cf_sFlqS2hJfg{g6k1VS|5#eh^plt~M902f4b_58_v-tF?U@ z7#I{Xp<)aS4n3eV=5Bz^1$9{&=iKpwMaV5~P=pxUfK=S(2DK^}L%^dRpsH94G_Roo zN=7>GK-n;Y5fq!C4BP?k$gd1wsAo{#3vzV?crO88PVp zg?8#4rk`D7u4D#ELHeeQkOopRSXnd^M>aG@wR{;F7{Jk$1WgLs6`-U5sR*stn#46y%8p`P;%g!l!NNLiVu_bxW)oc>^~xr`!Mc_RY@1ISNWlVO1Z8ZHFo zt7(CdKrvcpE?lpJNJroyRHe0`85?PEV!8}Y1$-f}W{xyBsEXxMVqj1Km$=g42{y)H zNP7&*3o$BSV1%e-3{@`xH3Ve2K@9=W;SP|JK@RMDJFuBZoUo_>N$gDP22sUO2s z%D|unY9)aq1yuHc0@rAI;RbWD=||U_%kY6EEJ4X6oq-_}BEh=BTsSf&lYv1ijFEw1 zUjPGxejFnMLwY6yLtil1t&C<2`k<9dpz3oAL4fh%mCDi(+^}|U?>L7^M!)Li3!vRi)NY_2CAA381!=(7#Qj^85oqI()D0@NOl6{ z;vxnH?FI%0hSiX41J(|TL}+L-D1o+XF`fj^kAS8g80UNoV_;ALT^+-Ck_oiefiVcw z4}q{VR2UeHXM(01PBVelk1z)5fkWdActOrI6$XasR-4SF!p?%c0uIIVU>PA*1_m3@ zpe$&J{7op#-&dJHLov3hFn?cV0%f%rkRZ6Y1}7z01)&@U$-w(JnF~V_8K|iMN_|n& zA8az$WCeBps;2X8HkYpN&SYSi5(Wt{XwxEqL4OXk9kLlJ0}d*tA_Y)Tnlb2uny4T% zE+b1b7p-B0$ZPLI3r38j$)GwHG}5NP;|r@%*uZ7U|8Q8vq{IWNm>`3<$~>Uz0X#{s z!UNI(+SG*U?YwY^x4E{M3#Wrt2(*TS{RN3)2K^ES1_n?WKLaAnXu_b?%D})dJ(B@4 zg|ax4fnf_&&X7SLG|CM! z-x~qxxt!tw#nl;5+#Lqhm1lTBGN2n#^gt8HjAwa3&0k$L*a*`(9#B6hObyyPKFt40hW}P`;rjKUY{A9?TGL|q78KI& zLG=d%s1#(J^C^OX0aPfz2fLFo2omTY!GX@;G#xY_%*+d_^+7{+jB`{&Ku1ZbKo%b` zFhC8_j|2^7f?5eG;8hCmK+aNK2K7R14GtZQWvI05@Uc)fpJH zOrdeE?+LA1wWn{~X09m?Zd8DpqafewcQ7z8fEH_nPye{hT$FWJCIds|bnfluvh|>X zf~PRc zFrd{B#$eS^j3$uQFTAghn9>oO&a}f^g7MyT=^f^h^`fy149ehRUmt;2iGeQfR0hwq zLHMAZZjiaQ$IQ^Vww0hh^Al#!>=o@3vSxEfC^sAueQ&_aO>#9D7_=;5(FbZ6gNniQ7)ah= z-f1pu2oA6#&;qYB1{7e>@`}-%LF*b!?+a+uAAstO*=a7!4-P)iTn;GSU&c&du*Y1C zOP3K6_}sD6=j}9?VFv{^gHFNpgFDSd>i5RM!c3I~lp;z9FX;K0>n0R=83(P*)B zfyVN+Kr2bW^#y2z9uyppVQ2&g`I!e_n%uK@Z$*bpfk=3*u{oGM6iOoL5p4Gz0-E@Z7+B ze-PhJhM}H;(H(4Uk|qNKBr$rhLkf!kV{l^hWJgJhUQlkhF*tj8gKcA)7-0;~9WZVb zxKW>)2y2yUf$nkw2ayjnvAvE5hxPQf#pVLj3-*|6v4IjAcLFG(NwI<^2(+i~-(xN< z4($ynyQD$O6^wehm7X7#SEq#RWqm$VfzS0U8tnyB<`-fYO!S^u2q{4H(Z)f4A3M ztRCb~aC1|dK^_!oszIQE{>9*M1(k;_pn7ReS~4s;7lQ+>R}&VUOOc{;88|xEfuaW- zoy);$&w%*g=v)DgzE>bVxQtxM4&F-(I)WH7FtG}3t-2O0I#7vA?6pxJ~2noZQEZ`yCJ49*~0pgYdNd8iZ`b%DtsozYCN zsM7}Z8$eN~$q0`&$b7R-2B>9{4=HXz%SpiXC|3$-A{R6ym(N@$%)kIT=><}j6oLzC za336`NDAs>&=4p%34mHEAP;{}o_=w$x!ClU1LjKLOVer7$o+@@xsXK>#|v*&TE`FGvq0W0&)QGBzY1R`7rlF}zZ!@SAZO3Xby|fC3=E*? z)dG#RgO@!`V_;waFM9%2$j34n7z$EBP6UtcX@N$u_(5ZVhBqY{7#Km9S1~YvbTH2O z4RQ)-PbQ-YFR1BwR*Qi_c?!sBCg4`uZ!HD}eL>JI4WMSzVThrOHVojUNT4G98dS)H zK_BEQkkCu0kOhM_Xl*A*BY1TysJ&Qc^Kg4=|U1%;()3=Aq@7esl?I8I+Qa5D z^`PNgmUNIyAoD%UTz425v}!@^B#@op!8*Bg=;#d(gFMJekH?_HaZfOrrNeK_lXqcc zVDRt;9bbEr$qytBD%Kbnz~Y{u4GN4_ap?>U@}PxzUN=FThH{vrbr{$oJI=bN%O5cp zuP+C6!h`0(9WS4s&cNW~D#O44!mK_%e^eM4K$tbbM^>4E0fc#jeL?rmfH3!8W?vgd z@U~e7uAPj2UpN>TK-l+@Ap-*lbM0dE4UlDE0AarUOn&nv7#Kj%~FKDkT2=m`#@|`WhzyQKry^Ow!^~?+mip&fQ zd`Fplw<| z;b&j~VZj%^5qb;^Ak5Rm=o4+kzyQL6FMUE;7#KiUK+Lz4nSlX>xn?o?);mfuFn}=M zNhaTyf(#5G%(a`*SBH;*0ff2w7=35TGBAKJcRRChiarAa2y^!^gN^`Y0L?se_cHsM z^D;1iFt-7Vk1rns0|@hJ`&OwjFn}=kOlDuu4J#nbwSm!>O^bm6gzLFhG5Y4HFff2H zw=RpXGH6|^F#`kF0!H5_QVa|r%y*c{=a~cp0|@gy@U<3ZU;tsh9ZbGQq!<`LnCk$e z?`16p1`y`TWb}>ZXJ7zft|g4VeMSrnAj~zB(bqwcfdPcMPBJnu3Norr-~PVbYI?#w zU(W4cj+wuan_kb8&ds=TdLo;s=yW|VCAP#6&}`yDP#MSonyvt+anQt83s?xW_8KhY z%)r0^Qpv3=9mf!6rpbkDnhSp#l6a7c6QR7jE}uw74lK&Bn>ez{t$V$qXjB!6Yx3 zWS$aSm4T6&iIZh|u&{-;5*srwrw~MzfsvV+laGOs6Ew}j$iNC7regjyy;s;G zno)N8OJNJs=>aJYY|~j(N=2tzidd*IuG*d;Vlj`Aapv^@q82HPo2RFUS;R5^-F{fi zLZ6Xoj`;M8QF@Zoc_l2=7;kJhk+8^PWZXJ^v7|)>_?CQCw`vQNb#hH=YuX;q6jrkhgJ^NJnB zrcYG0@MQWWHC?gPL2UYi9}#TZf2dmUuyf{Q7MH{)=N9BlH!x!s+b*eV@tY0x-qC|C z4vN#+T1|DfCzx1VW8o=IPRxrhDlUl6NzI%7aA~~a_5@1{UCYTEzVl4iI~K|_o##>% z534ok&e-Yq6Y}I4MW!nrs#BhRK{1kN`uh_OJkx&`Sx8K;Sgy^(7&=|9*g|~zNw#Vp zLC{?}N(>APpowwN8hoYc3++v$rz-?%2uwdH$V z{>n|)>rxY#zA8sjVY|?5i&^}FprkIuaE{>#c<~Ga1K0Mwt1K2W*BhBI#K)(V<|W6+ zs~8#>o0_3;ElrWRCZ;HgP0Y+0;^W;y{hUKQ{r$lDO${)G3=Pm#nHd{1B$edGC*`D0 zpW$M`H~sZG3m#QtkXgWsmEL}1y@iE)AgGKN0gaJD%Qz7;$n10^XoL|e4qE#TQv(`u zfw4hF7>o^C;{wvFHQn>Og|sUurGU7ga?l@Y6sW}sVsnGm*MbI^K;mW$3?Mb2DIAb` zP>~AagVSn(YSlCPhGtni&}wZXu}$4Pb%PfYg76ii0`;LJSPktAAK%G8Ru?`olt5666k0 zs~=Is9)0ZoprpI-XYLfI3f93%}g;yRL*kD+W(_Iw6n&t+f$&3l5_ z+@O683=9lEpyHr4N4GE#IXP=nPEQ?8$4kRwSXUVuQ8Nu ziNtnAVh19zW2bMlv(%RatyO`!cNvoOmgzt3ES04mBME_SFNZ1p$2Hx|-ZD-y545Zi zYHKwTyL0+ldrNW2)ks1+kl4qj-?g_?X8byx(ZN#OQvftZ0yRViiEW6)wnJk3Ah8pX z*saqO9W2Eqmm>*nL1G`8KGDHax&9-P&_5(L4`>l0)D??l6ai~v+3 z4N0PC`bkGiYsuY6LZGwSVDWuzx~!9>vLxsrA()U5Xh;!ilEU;zCrjn}7$l)gBz8Fx zy9bFq6N$YHiM<7h{TPY;0g3$&i7gD81*u|~{@%%wwO$v(0SB!W659iborT0MM`E`k zv1cK%mm#q?A+h%%u}?wRkodh0;eZ|S28sO>iOmZdbAkq-5)xYviEV|%c0*#vBeAoQ z*vCM##;_Q=jU@3IiTz)2x{`}!kY@#GX*bjXtw`*{NbK`S?Au6eF3?;ORIm8-y)KsG ziAG35c1Y|JBz8R#y9h;2$y#PskH4=NN$W>xSSE2zy;ppF2Poq@!jKK-t% zrMToyBq7k1A}||nP3Lv96c7D_B+Ut$w}P4^i^MiUV%sCJeUaGtNbK6_xo(!?ylaqz zc1@q?W+`s?5=rPg5}OCqM}XQaiNw~O{?yH~-}54p&^;tJXz@PGKQc&}S_6q4j>Jxx zzR}%MeEJo4ONsiWNaCB2*vF9Amyp_V)r1iK_{re%vpjYz5$7S42gXo!A@fM zgy1mzLt=A*2I!%#25;hmvXzm<^^n+>NNg7*w*T~#UY5#|wMar;NbGsjS-mZlRnH;` z-9lo&Kw^KH?(1!7T@M=Ch56PSwAv5qut+3!Iug4SiQSCEo`}SrkHlV!#NLg>J_%ui zQVavbbqEKXW1b?hKO?ajK{KgP$MGYv!511s#kG;dEs@ynNNmuWbC`$QWP=eoW)hO3 zZAfg;*_kj6=a9s2A+et!u|G|}>0`OS{vc>kCe&T$kl3G)*leKPuTV8YNNhPIwiXiG z42kW8#P&mCM?u(-fK7vNzyS+dkqz@l9g=t#5_=jFdl3?Q9TFRK!yC+;V@Tqckl6R+ zr%&^vZOMPg4tV$VThuS8<+L1LdkVqZaGKR{x?fw0rS9{&m9fY~gd zozqYUNg%ORkk|%DY#SuD2NF93iJdV0roZLsdK=I=4N#*!k=Wr#>{KLnF%lcJAQBd) z{Yc_-k=Uz|*x);pp>`dIh=Yb77#Q9_IAFj2Kw|TP=0%|zq^3ItT8d9k3AB`uj7AdA zKw`H|pBiXs&3gw)=;idgftJ>i=AhL&P?KDc*g?|`gDkTd&rhElWGT-33Q6YM^n*c` zzZnIlZwv<2)4`Srw(~*LTTnwlH`c-Yehf+c3KIJf5}S8=VTh$QW7zbyA(rC2g`jnW zP?Kt>UktGfu77|e^cIQD4O-6!RjPo*)Hg5x_Q0pg(jQczc`BC(B; z*p5hS(25C|p|MEf*+}e4Bz8Lzdn$|#^8aEOhk=1%BNF>868kn1`y~?lI}#gw12NPC z!l2b?P_`lxTOWyStA*4E@J5n|L}G*Hq+z}+MG|jDVoyY3&qrdfMPh?53x+!ABtpEN z;W~oD@Dz#t8HvpZI#dU$nIDNQi^SGOVp}4y-I3U#NbF=V8x;Nw3=H6FgrOFI4#I-@ zxEHJloGux_C;LFvtV9wA-y#eZKZ+zC1DZL8iZ>#$dy&{P>ybE1k=UD%*hi7r7m(Pu zk=W0W*dLMDf05W6pw&K52Ps3@VE==*kTQafOaWa@tjoY43}stF6@mQk0%C*K+A%ON zc!JnagCdaF$sjg#@H`!44wPL45{Ig<1+k&#H0v@0D!v26hKe6YVuQ{zXM~z_8zc^8zeZyJMq<~4cgI2%N$W8%z%;8M zvCTki(D*L{1A{#h+XIOm4Prwbmj+^khO`+N7_#&j7=)p0&^i0C|#ARifGT1)VPIf{iVGmI)j({h z#rjBW3naE3hz->n1!6+rq{VF8(RuCIB!^ptEuoI*n%02)RhpImfVuSV!fsQh$2PuMbZh<7Aik^bl z(D;4@VnfBhA+Z@u85kJzA*q@b#D=O70kNTG$|A9iL2PKq*+AJ~|GPptAfx<1Y^b3j zAU4#XSR{5D5<4G>-HgQUL1OO*v7wGT1!9A?(1K1oG-aq~5QcKDf+V1d9)Q@Ob6^-4 z7@n9iFbG50??K{FHNQY?XbAlWv7zEzW(*AQoC0D)#ic-OsCs!28*FAh1A_*f!@yt% zVnc(-9f=))#0~?o!I~Ku;*r=zNbFW5_B+8_>EuxY`-0J;_(WDq|{9I8eN#D+Rr9>j)<>so-ye<;Tq zNx~C}9SUMYEr>&6mw?#NXsShGw;{26Ky0YqsYvXNAU4QeQ2yHi;wXaL%)qb*eG4QGRr3_YhK9r|5F0A~ z1H^`^7qUUby)1|g+N;OFz@TWuz#t4}>o73rfFz)r%|UFap*A2kRNM>1R+~OA!&2N+ z9TZFq48qGgrV$mkT_ILBZv*!uMVmhKx|ED2cRFq0f+2D z5F2XoDkS!1B=#N<8*0!A5F2X2We^**C!2wR;X23>Q1&B`I8@CW5F4~=o`Hekqb;Zc zfGYY0l7O;#>=+neeOXZ?wj2^$9mIwjYp{MuvI@caQ{BkuQi1RTKzS1Uk7S6(kN-lMP}+)#O9fSTQp&G=s#UYC1t| zsG44=8Z{OMhJ_$;sG8*85kILgE&x$gCI6k^HHc~(0PD2LE=y~_d#r^n#WKz zr&$>ozJtV}YW{-QP&I6z(-NU<84w$qz*Xy!IC@BI6A&A!!4`?_hQ#(qVyA-GP($;O z*yTv+Fj7{Q7iVo0r|T72ir0gVF#z2P;L5-t3}p+tA`*fO zhz)hGB8UxjuPzeX0>p-@u?4ZA<^&?Kqd{z_-XstkbSN6=@Rc->#ZXQmNCK*;9*Nxr zVnZ#MfyAB*VnfxhMq+PAVjlvrp?Z&l*iiMCKx|kca~;HiI^qKoo7W8y5)vRb=sYO~ z1_l{71_og$+Xy5MwZI(2hFahRVnf9Pkl3LhHdIZ58>oT7%9cf98-v&& zgBTbXY>?QlNNjHq8>%-1iJj&SDrBIV^Fb0&b_Ei<6~u=6cmjwGT5r$5z%a#~fk7C` zUIh||hSquz8>)U6hz%9r4`M^bPl4DF@p^_E2oA$t5F4uK1&9q%#PAlxhKm0Hv7zET z9*FcI4q`*aWk77GdJQDDF^COSV*z4Ufx@4Gfx#KXfl7FQ*ig-JAU0Gy8N`N)=YiNz z@nR4gbZ-d*14Ao_4HfSOv7sR}1&O^1#D<3S=6WQ~9whb&5F4ub1rqxs5}Vx<(P9@s zVoM^iU+yUJMM3P___=4b?1-#8yFK8-m!-sIdUCL8ps=a)cKHgD{jG z2oi@zO&Ev`R$tG+kO<;HCDK7`uml4`9*7M(O_zazp$KFUlwAuFhpOpDVow9Hq2|m6 zv7u^~f!I*-)gU%hd?$zvn+-bx;y@MM0I{Kp9)s9W@fRRARQx-L4Rw&HHv2< z4n|_9Be5Hh*!2@Z9H^mlKy1)vItB)Y1>Ot{!cg{VkT_J$b|m&85F6^a;~+Lv{VgQ+ zdn7i44U--5>R#@hz(72(~;NHdOCzB=!>| z_A3w@q!*O`1bi777(pBc1_os$whj{86p8H(VnZzmL1M=uvC}|os4sIsY^eDyNbFU< zpzvDYK9cYxSXgZ6>g(2zKe#J+&Ueg8xj9n1v*<7{rD; zVn2ut4aQ?2HfZ-eD6IrAFbG50S3%-XH4l;4Z;{yFL2S?=Aq)%*e?V-gUe-Vc2F7|Q zhY!Sovc-|ux*#^x)n-U+dnC38hz+&C55$I=6OP1AKw@VivFqzW9H<2yNbHG7?CBsj z)X+5`Hq^(PL2S@@0t^fc+XERGgrV%SAaQ77yaZxH)jvRDvj%~43MBt=fjCe_Vn}R7 z5F2Wc8i);5V+dkH#mzu$sJIgn+ZV)!stE$Ip=x45Y^Zor5UBizO5}hfKY)mx0ju0dk=2ZPFgsG_Y%68n(YS3qp2Wp|O-&yd(}Ky0Wv|B=`# zA&9y_8^i`((*`;$DTIMR7{ab+umVXyqaYlKodjY-cQ#D=Qh1!6<6*EpymHzsKuaBuj?QQsG>U{HdOO-5F0A~7Q}`+ z^cxbJCk)Xc5k+FlA+c3JY^Yw{Fi`mqRpb5js~%z>Z_61Q<2zPkl0s{ z*xx~HsArhM85kJ7K~YoBz`z#Hz#t6fFfa&$B%q39k=Vu{Hq`ePAU0IJBN96t#D;nx z0g0W7#Lfq?p?VuY?E0f1S1>TNfjCf!nMmwKNbIdh>|-D{=!z=_28J^rHdOCbB=&O< z8|t7BNbH|T?0SX>L>^@au|db&fv!%CU|WJk=W~y*jqqssNN$W zHq;TPL2S_BZ=jjhhKQ4?%3G z`ez_E)Ux+TY_4bq21cm3a6J-728nHg#I{9Z`-9lflple_PDEmtg4j@pHh|cm!#x-n z7+Rtk7=)qhevo(-wEUk1;y_(JAH;@gUIk)9#n*$_Q1QJ;?9)i>>qzWJAU0I*a}XP< z_X`r6IR;ezLnVY_5ZOr)iLC=-Lk%(nv7tV&LShGi*w9dkL}Di)u`@tysNO<2yPkoe z3(jF+n2f|;31UMH-Gs#6jl@0(VnYo*g~Wb^#O8?wT^k1}=EXp4sD~9n?0V>NU8=DR z48l;h0Z0O>$Qs0k`rZM=hKl(B=%G!_Ch3f{aO$QYVkHC_8AZx>ierm z?0ZP;Cm=Rd?^`4`V;tyaXo!zRkk}eXY)1$iRQ@qActJQ|9SI;d)Z$Deb`cW00>p+| z+=#^9g2dhjVnajgB!~?XD>(s8tliA*yoYhH$ZHtL2p28s9v4~ z1_n^e7ZiUwNNiIiwjB~X1jL5eRnHKM;4q{iu`5Ars0F=9>}g2seMs!%NbCzp?3YMv z#zcfexxj2t_=A>5fjAHsF=!#Njgi>)AU4!N*&sGFYRW+DaFE{_7^)H(7=)qhR**PU z%>)n|8m&`7Y^eCcdL+&o5F4s!BZv)Ev{O4?$vQf!NT{ zEk*lR%STuA!Z2x3Fc z*#% z1`>y=sW$|1pgu4Iv7w4US6qQKfHue2gT$d4yph;ZNbF1`b_IwHHK!4Yy%33g0>Xym zzsn#F)Ph?eHt1|w&|Rb;S3}t^LE=y~UqEcAqkn?fP&G`c3=E7=wgiX`4N*lTwiXiG zAQe>pLp4}}B%o|3B(^saI|PXxi^MKOVpoIMP=_{w*r4NhLCgPA85o42?1><8kQ$Kx z=YTj+-z)^NK@yUV(HP;>Smu@57$k0Y_q zBe5?dv2P=>?<29FAhBN{u|GiApp?bH@CCvF`HSHX5}P3dQOvUz^iNw~;0Oc&G?@f^;ERoobNNiUmwl5Mp5Q!a$#EwN`ry{X4VQi593t=1v28L23 zb}bUS5sBT2#O_66Peo$SL}D*QVlPEvugyTpSsRfgb|A6$AhC}iu}>heFCek6AhB;F zvF{_XpCj1QS5LF#t^b4&VEBf_{)@zB%tWLGP9!!j5?d6BEs4ZdL}IHVv2`JAP$V!g z7(zJUL}-b`wnbvQBC$P@*nvpwP$YIN5<3xzoq@#8$wW$oB}ft#NbCkAb_)`_2Z=oa zi9G{}JqL-s1c|)@#s>L+1B?S2XGUW0Mq=+rVjo9hpGIO|Mq*z_V&6w%KSpA|&SYRv zgEi~kBT0NmV*duSr|+AoK5e_hOv?v)^`IMg8KG;ju7J)ug0ew3@xsKPBZ~biFT3E%=%!s9R1WsXdRxzK+Dcjl_P0#C|sY?n%qw zdI``WNKoTskl4ydY;`0y=t^GLk{BzHICOc8BN7{Q7(GmlACh`eh6D%) zoH4=2K|u}8MiK`f4FwgiL=ta6Vz(f%`;gd^kk~Vk*mGq-853&gawLh>NbD_0>>WsK z&}GChU!Fq}zly}ZiNpq7Rt!`B9wt8h=xIxDPbJU+Pf%y5A+e2+*k(v_aD+5}w<35!C|ZP75cJCYjEP0=v%sOh5TER|LBkfe){*p*1^ z+Uc(6ES2jgAPG%DVuS9RhMBq?NgQ<9G)#OKk~sK$FsS#BB8lHYVn0A)KZmd(+3_`m z1NQPKB=$EXHY?~nE~o{ZNNfQlwg?hi7KyEh#MVG!>&PQzM{AG-bj_SS65Ab#4Z2SQ zwBHis(jX-9FeG+75<3}*4L-08YJM3^9OQq{HPNtTY@Hwp=#sVxNbD&{Y|u5*F!igD z#5W?bw<57Y_e#UmpFk47AkV-s-Q=&0h~yn4(FaKE_tWQIuoSQVg(UP3iOs5jSbxWf z#0FjD%xDb?BL)T;kT{gBg2dK9VuLPhhOGm$28r81^g2P$| zu|an`!wgDC63<6s7bCH&kl1xd>^3BJmqI;amD)rkiK$3z&|SlzRYf2dfe(6vuHo4L zQUhggL1G_6VxK}{gYO)Ls=o>o2l@XVjKjdd@Cb?2BsMGPpf{*` zP9(Mf5?cg`4Z0S&9_BMGBnd+#wkZ{JBXh#?cfVJJXi zmmsl0mo&p1+BH4#vZZ+9G$iSHNbE&O?3GCDwMgu(NbH?R>;p*bBhwFFwiGwKfFyJS ziG2r&4Z1QK=DH8lMXy*Y*MqJmW`r&t;RBs*2W5*Qu_ck%%1CT=B(@$B+X#sby22P{ zz6X-HKZFfRRSXQl5DqBaGJvi%hG|Gc63<0q7b3C2r~E-3-HIgMgT$VI#0Fi33^RX; z5@;A5s(B5Pq76uF&|S$e4M&i~&mgfcAhE9_v2RbGdeu_7{w-5lTmddJ;NJ6nl z>@*~H*7S+jEX6%bk%a1y*iA_6iAe0JNbI>t?1j_+UbD2W2i z5CPqT3{(FaNzG>@_ID)qKO{Dj3Sxy2`0#5F=o)BIBneq0wjvT6bf+@RViP2BTO_t4 z659ib?SsS)MPf&)fC_e~&p;@!u3le)85_=XBdl3?Q z8H^3eg6m)$1_p*rNbFrm?0raV&=t)v$6Z7czlFrUhs1u4#D0y${-gpLse$_J8dziLHgi)M#5_<^}dkqqM0}^`&5_=C48+6$+ zBXmK|1&}zDeZ3xua~p~M1d06uiTxgl{TYe<2Z_x9I$9KJ0q9m|n8lzo5MXR6s2cFG zT5?bhsC3eu?t9x(yxsyy$Oeh+jKp?FVuNmnhM66OB%XxCPD5hnA+d{)*r2P(7=0L~ zU%zcBSl@;u(S^hY-8~Jn41De?)U(Tx)T~BgZ$e^kLt^hmVjo0eUx2V7X#;#{E7XG9 z5D8E?G2BODgD#h5gf4sf1QLg`eJ>Bmp|x70Q-T2bE1w zjy6aFx*$j&iEW0&wnAcqZj@$(st-UC2i+bG6Hi7G&p~1rz}O)FgRXyuE!b%WNkA9x zbRn_(kl3K>p<(KmAc?O*VsAiVZ%1P9Mq(dUXJD{|8FU;;;v5qD5)%6s68qkC!F!hC zlCO}2K-W>jjQcm;_nxJ4J?M65M(Fw#8PIvNP_{A>TOElFx;+}E-WEyR1&Qr}#0DR> z3pFziNgQ+qG-EKd<}1`dERd-}VuKIZg=z*}$;=3yteFT>17*)ZV$VThgKiv#ElJn} z5{FLQ??htn)c~a~s08R5Vwi@@NQ!PDvF{|Uq`M3C4LTA-u>l>psH4AY>E zq{tYFZH~kS-N*}@kM{zJL+9oLk=UU~Z1Bm&(CPAQkT{49N*bW+Yhlybbs!1o>~t#< zyAz2$8Hqg|i9HXAy$FfD28q1^iM<_s-ZIoO@Oj8kHs}&tM(8Z`MUVz4`vwyG4iX!D zOfpo>OC)j7<+m_%{v(OAX)`cD#ibay5F7^31+uXDS%vLOA6q`>s}BNQk^vn-R|Q=q z0UZ?s-LwfCoB~fEK*y0fK!fnmAsFzWJ#-WWJhlwoQ1%lvJ`CLl<^USigpLtpfJWe; zJ76Ay*sjn7ngSYBfHt0AgV@lfWD%&-3vEn^gF0N$+H*OG4P9^y?#n?J6F&rrLu*WM zM+{o&1%kQ`&`RtZhz+fKUV>Zg(8BSADq_9eLQoY8&9>nB0Gfy&g32OjLR13f22dhn zU|`4uv7yoX0K|qympv$2p!5CSZ-IS2OUuVPn>~4$c%vj zbkGWm1cVK`eUuBz2K8?Rplr~+cw$gC$eA)wHppp8P&Vj6|xazOJ~3!!X~kJmui?hFhJo1tvbReL+3Y|s^a`=M-5 zZa)fT_cJgsT!6Ac*8*OLvgd)uyr68*6@f27Y|u;@=wiM1AdWc$1L&eX(Cslo<_rv= z+w~YF85lrp(CvCWP&VkkKw&5wbfcamlnuIVPZr7s-NDEBm zF$@e0O;9!{iS|I)^`NzD44|uOK#s^`U|^U7kzfE_#JC*FZU&v}0%e1OcMFugfq{Vm zbb}2@FX)7)15oi@3=9mQ+iXDM`$0P_pyHqn7oeMMK;q{a7#MDV?&bk;Zh#gmK^1{6 zFMI-JgMt@yQ1Lj>)zeUR1|tK5JCt3($iUzS zWtTBBFoZzam5dAw@lZC%{4^-Ln~{Mb2g+W;$iPqpx|;`N*?L9>hFYk^7Dfh!4k-Ho zBLhPplzoGdfng?;eTR{O0dxlsNbd_q28Pv8aRw#^hD}g53ljsw4k(+0iGg7cl+DM) zz;GVKhD;&UGhBsom>C!tZbR9i{QVTl2AyaPnxhu7WMBXtj{FrW4$AkSIcktN=*(J1 zX$A%m8+14;H`5 zj=}(%8W*x=0G-;va2zTDs_#IT6oC#T1atT1)rd78wLi3zfd-) z-sF&BU;ya_l>vNEHmLj;fwD_LM+L}$%6}UMhDrto1_h`Ds3=u~vL`YyFz7(pGZ`2d zjG*jAptB*M?6nLG3~o?1=!R7vC>yjfD;&x`&A`AA2W5jw(iABB6R7;pf^tClxB$u) zVPs$^gRj0_BGK;rc_3=B<-3=A7U92*9P7Dfh!!yq=aK?9l~7qVku0L3?Gf*iyKE$O@s zRRcx z1SlV;L)oCLRRm>&4#xydwhK8jFc^YrEvPtXqirjc4N6emP+>MpnGf2L)oCJ`6iTomw|!dF_it3 zfq~&Il>LH%fdMqL4l@5QD0e``nHU)uK(p*1ab8gQ%qa(P1V1AK13#24#K^!P3T3M> zGB8L(+3Ji842n>;1tSB4I+X3s$iScrW&1KRFjzp@fs70cpc!|NWigBl44zQ&3PuJ7 ze>nz*dXPj7BLhPyRHA{AfguLU1|`M>D7%f3fuR`0hPI+XbMQjWkc3$e6$ho8Rwx^k zR=S~VP+FM^WrOyp&WEz?LHn1MLOGyD_y#B&)TrJLWrMDy-3w)xGB7Y4hO(;}7#Kh| zc!3-NYAalYiuW=wFx-T)L08bf0kJ_@fPsMlG$}9S3UTxguy{QK1E~1?2j(y^fKFOx zk!N54DFT)Ad{8!MFR=ua4QeIJLD?YRs6g4E><79Q45Sy7+6|!MpfVqHMHomNRLt8z z#X+8Qs)uqwO=%A(8`NqC-5mzfkOVsS4Jr;g;~aF47)ZQ{fq@|bDn5aMfdO=-7)Tt{ z$Si=0gIY&bP&O#>HbB{+1ltB>*FON=1P$dp0c9H~8*~x%0w^1FRWoR|9%KO{sIY>H zvoJC+fbJawiGv!Ppc#4)o0E}&;T%*A4U=V<^K`kXQC_9T0GHVagTLQ`{ zP;pSA)`PMqFxE3LSVB3g7#SEGpzL*wkePar=8cRD44~P05PK&h149H<&0bJWfwGS? zGBAK<=Y>G27_?XwB<=x8Xw^_QXl-*NlnqK}?I1Sj{3uY1r5D8UU|;|xy2(&Bs05q` zWrGsn3Md6`L0zyYs5m%B zK-r)^LK>6}y3RZc$_C|#S`Zu5LSbNF=uiZe|K5;z>W4~zd@~iw2Ki<-lnv^GE`+i{ zt)t~oHt1Mz(3HE7Hv-0&}Hk_ zpzIwC3=9vUY*4S|Ih1`9RKY;mpnUup$_7<7KcVbz3=9naq3mA_3=FJF3=AMgfcl5r zP&TL%;#UHd|K1D?pnR+Zk^p%Nbch9%4T@tEC>sXC>s>tps9Ev9|i`{75B5D z;&luR4D+FEP*86Iu|Z881_p*5P&UXjd!TGkRy+@4`+>rrfq~&Fm;*@%H=%4$y#Ttn zPY61!^9dyG4^acU#1AA6>LdJtih~9p_>~zLgg`!FU|xZ&?V)Ut=Uky|P-uBV*`QIO7!Vs&05C8xBth9Ahk|Yr z6bfWu0QLLxpyKtQE>b0w1FEMRplr}7t8Gv=Xw0Vv%8p=QV3-7DgU+m(0cC@Zww?!N zgQ9E+lnvSqvJT1yHRpFg*$Y59LK#&42Qo0M1ohXU601S|btros==feJdpoGV4rPOy zX!oG(0}KodPoV6>3=9mfplnbR?H!a2YV$LyFfa&#Mk+vuBS6_~p!Pp#79S)5YJAE- zB|xX7D?{0!zML+U4T=uXRf{0?py;rJii4uV6Uqi9mtZIxWM3?l4T_p{C>t~wR|sO) z2Qe^!f)O++4>AUnQ2XF6lnp9y z9zxl#7#JA7fY_j#hJk_M7nBWZ4>G7SFn~_Z0rex;plnb`^FY}33@Qu^4B`+D11P9L z6Y(Gopj@B=6$b?`X!0E-4jM?ZfQo~1uN{;<7qsIR$_5Ruc|qBrQZ)d|28Bczlnoj$ zictlX|G^9lpkPUdN*rNeV90~AFEB7LfF|NW7K40T1r>kCz`)P|WrN0i+MsMcMh1o+ zC>u2XGYQHTXJlXi&B=qzkz!omHv|D*r!BRbxXm>v8&svg;7#J8pGxi{H&`|mps5ofH)-Na4k`gk`6^KMWzd;VP&TLx0L|Eg)V~D{!$8GBqbE*KHU}dEg9nri z$`O80HYgW_K-r)X(I|CL`5(%_07~HrPzh&728J{!+Y>Zm31vqzGBA`w+0l#)40TX; zEF%L$3zVJ7$iM)a)dx8)hmnC{0#qE-+nokwgF3i#pzIz{`+pIXGo6uvVFi@Ef{}q? z9hAL^k%3_+lzohmf#Cp@eTk8Q0W_-*vg|FW#{(7r$H>3{n$-u1gGNN3g2X|?U$n8+J4I=}?UML%sT|w9Qg3Jf? zAy0x<5P&$Kp%Ksu0uVc$k%8eVR0AmC+=Q}0!*p*zY*2d(G`0g}gW~cZlnol7X3=C| z5Q=1A0JVleD+NGo&}g0jR2H6b)%`T0+G^ z4M@=H0FXGSY3~oy0|Tg?I1efg>R~N`vO#UpRZupl ziLe362JNzB*aqc*dZT-wY*0J@5R?rHp%YLxD3P9nvO%LBSD@?}ptd2D4H_GM4Pt}3 zx}XbFplr~zvlN`kUMV+I*eHmC)a2W5j2T_uza>UOn2*`WCDgR(&l)G1Il z==?f{8Bh+WkXj95gPNxd3=G?#Y*0Gb3uS}S!C@#Hl(;}wEDI$vFn}gc&O^mP=3Irc zK?7K~p=?m0^bpDhRa#HA7`7ibvXYbH1+}Xg7#IY^85kJNrhoFW>gNRoKWGy@NXUG9 zpRbiaBQI#+fPsO5LlShn^z>JLR@S_ri49QLfrKol8~IyV^Mahhz`!sABxE(c%HJw} z`d&FFiRmBxtyb`Y<|#mfx}Y76Hq(~{Sn2bEGAC$?1GK)tZu%pT5Oj3h1|(!ZT`th- zG3dq*kRs4@1f%10z96f3UQpTxSp-^i;Jm#m$V!`$7u3H6O#sU>Ffh7K-xO?>%?lk9 z@&K(n@R+U@VwKGciVo0d4M@mq`l1l4*}R|(!@$6h0os`2J>4tRs-G8B`Gf9=1FcK& znf@%)N;wo%-ZL;Tn1F8HZ1f_Xt1mw|x+Gz`NSI9)5;>hbizcek;Q2Ixi?|FfcHH@23yhzAw^>osk#RY5~ohg4W}PPQMgo^_UlwJ{TAn9)OlT zgik*dZDq|1EmJi>s~;k#bH!LG^Fm9(2#`?pbgLMv{gR;U2D(53v?vbBHUP2XrVGVd z#q&aQJg9bOjGtZ?Yh}#~&00@DsuHFji?vdoKKFktd%Xx~IR!MCgKwROo+_XN5(jn2 z7#J8VKy1(y1E^;KVuL2*Kxqxc26faJ7#Kj+AtNZ~gQ5;34qE#F>NJ4Zp!5#vD1g}6 zpv1$#&;w%UFo5a+1_torH|T*NOF$B!u`LD$h7BM#s3Fe4z_16z26d9{0*NwOGXM8igHr~pg$z;v+bMaPwjBBRLCRq71 zF|3`Qmtf_`STTKXf|Wnxis`(GR{l&1>!!ygTKO?%OkbO5<GzVY{1{hE*G&PLv~hY}ij^PZ zlIdqtto#`_OqWfy@@L#LJr_isn7%jF%Abj4({#QxD?cWmP1EDjto#_KOkbO3<Gwd~l9)C6{)~U7_kySm)9>bjJg{%NUY?a7 zlfb^|bs$=1-}G}JT4UdIxqOhv_D#>rxAJ4WGktHql|SQz>AVG2{)_?BV+%kw9Gt$c zz{-y?WcptaSLg6_zd|cN#-8bO3$6SauS|anqH3nw7Fqc-?wHGR zzO>lNpD}0p*J7)3#)|2=C0727AExguvGQlqIXRuL)XI->!SvWtaEPx3Q6ba+mRglF z-k4rmX64WLVEWNAt8&JI>9*xo{){!#dqGsk^t+@@I0nIz6w_%8!ZV+Vp*uR(_06rt?-=`7_>`9$N)+->vEEsz8BuYx+MB z?Qv_mU$vDV`AXS^`I7esBDez(TTpGn~9biGV0Z?suJE zY`OzuyZ{r=%jt3TR%)y|x(o~g(=YZ42~VF>ZzaGK@p}3?khqOL1A{)qoHrnGp7+!L zfy8t485jy6;x-Ld0!$(Ar~5Tnsj=SCXJGJyi1&cRbv{g=2NKsYU|?vQ&S>r=GW~9Y z6+h#i>2DjX)LFL}GBCtJl zMhpxc(*v*b3r|1OXeGeJ@OApVMv$e(3=C(cJMOO$pRUkk#lv`Ex^9z|I_nA(28PSi z4<2k1nV#EZ#m~58dM!w}#*BesGQ`e3O;!R-DSxM*YqC;f6)|)b>TC4<^GMJ{vwOFaK&Oj)h(_$sSSTcQWiWV&ys z6+f$rD+7ZlM0ZK2l>n=aD+7Zpgg*zwk8x#S5QFfKfcPb@3=Gl`{u>Z~f-3`q41_Pz zWhKD4X1Zd3x%hOOE-L}n6JWK4kuD4`gWU!c?sK+Qg zU8T=Tfc2XfBLl~DM;R{R={|i{0!$Jr)8qQA)L8%dFfu%t?zn|rc={ZWIu&(hh6mF( z_E{;j-YaEfkekk^nfPiW#%(79GM;%EG|6Vrr%1K&B(yW(A0SP z!2m9CR!c)OGlS_5<+#+DSVFhY>bFvp6jyg!3=3u>|#lXPK!4BH*!OX%sRhof;nT1_af`NgR zg_(tYfh+^aOu-I01_qYHVhjw-BB1s+%aZB!E3Fj5Dr6WKm~}yO^(>$(u~`&BD=Jv7 zaxgHkD1k=&SX#Ll7+91+qXR5jLJSNnYMVeU-d}tS3@jR;aVHjCRR#tYO;AstnUQH4 zBLf55cFpOGrwyez_81Vk*>_u3v5@B?X!TWN~8b z0O<-8XJBA)g|Hd;r^oZ#NHG<0O|LIEQ?s%WU|?Vg1)IdSoQHvdC4vz&e8eTdvXaq? ziGhLpj|c+;%PL0Dcp^8m7y|>#YR3Pdc?84h?^jvr>+O|iU|?AfR?23{&A`C&g%RwY zCItotmS12t4?D|0#-&UQ417h?eO6mZF&0cuUu~sVzX%k{LbE`vIU!Mf1_mafB0dHN zW}zH41_lcF7&t@}Wf&OP3_-)4JRV<17z9M5 z1Q{6Ej6og}5phsvU|=%=u_Z)6OKsRpL7tWo`7_;ijg>@wuN(sdn>jx-1A{0Jo6Q-J z)meHB3~aWbZa0GnXy%vA4#Z{=;Q?7^57N!Sz`~%UQ zMHwG4GcX9UfWnc(a61bFgHRDD5et3LV_;wunkotk({ff&m>LO!!qi`yfq_+sS(Jf+ zO(=npfq`8Jv|y4$=(h#~1E)}e3u*ML85^mQIJvrkU0!2_DT#49Fst)f|G@dm4QJF5*%|GyVw{QgzD=- zbD2Vo0-yjf69NUuK7LSuxPtPUP_;5BK+@Df0kT&H6d)2z3=AAXVcMVo0S#Sq32oB= z1qf(00*}xfIZ%Ks5(fncXlVz(kUS?SJUYcd;UO!=z#t?P$j-nZEELDXz#t;Dk{LA0 z4jLL`5EBySWnd5&QetIbkPrfGl#>(!9j72AbY7W(L0agS5(9&b&ug`dMlCo5LpHW4l^brMg|7%bsP)~9Ohu13~c70 z7`I^B#m2zE!_8sMEh1`b;=hmjAoNS4D6%wgiYuE@Z^ zVb7!hS{BB)Seb!=!vQSA!gmv7fFsi#Hc%nJ7QrEGnKAI~*JNPehyc5l3F5U#ux~i{&I>Rwa72Oia`PF1iiT(~ zhlg(&C>h0oIlO#3Rq3EWrm_zQB>lw2_H{ zL6YyQGy?-i64(SOzAvCqNd|MI`GnaS7&uaxeApQnWcU=s85lTH!7{RZ{k#ke9BE*V z93Phu0|Q4om?O`?4l0M7Kmk1)blGM-1KWF0kYqANuro05WN_p&Ed%*m8|2jjCXhk~ zJ{FLQBCy*O_?}5JFmRNCLqv%Ww5FP)oaqn?1A_`*2*`I8V0%*elDQceI4Z%MGzK=% z$P-5mlOG2I0}m5N1JgB-9iS4bo}-ZoRKPIsflhScXaZ|sWMFFsWtV2AO&kmiY%{eP z7&sO)z2jhD;Qz`~=4vsTSrko56d^Vth;4Ih>2EJBK1_q9EU=AZB z?#@Hvj)Cn1$aNQ(SU5qK9W;Q<=VAsWDz*ke1_lmpW>9?dNN|WV?*o|%DzrHym>ogm zoqV&kK%-^MexS8ed^=b{3(}d-fYzn+Jp#!{Gk;-ZVBq0X0~spA405Fap8!Z+4s5Cj zpD8Fs$TOERf!4;=vk8Jyu_ALMCj$cy4~Ggf2NweaAJ|4!WE<6>HiC`P02{>tF-j9` z6c+=VkSGHKhc@#mkV(uOX3VZ|lgyzeof2bU;IIJul##Cmlwj(uz&s`fHg}M2Yi1EH zusiIS`{BCnp}N67cYwMBG>gLF2-eI233ewihm(PAEhx`8GY4`pFmOq5xH3QFVqo9~ z`^XJ!68CLT5^@KJZ36cVG1aZrTXO;^}rB{O})6+?FGYEa^k zW%Yu|Wq>q;BM3o&iVOy}$DmZ8%31n~7J=92^!wDqhY=W{Z!Edg24z$(O3 z&%nUL$U&&KxwRGjy*f(isqzCzGkAV)tdsL1i*^Al!Z;Fth*VgTPaP$W(STN22(8x%T| zz?>jHX;9fT8SJoNzSW@cnF8j7Ft9xV<*BKxn?Y{z;+Vmj4|mHZMw z3~U=g;WdZVj+cRfCxBx<>rS}t1<1M=B6KrwEP`m}y9+8x7DGJ3z&0IJz%OB~=4D`D z^9Kd|I!Fw%b8KY&3O98Vs}acm4195*3TQLyQIK*5HVzgB297PP7eUTY-UIXD~7_F!B~LaO?sz1sT|)LFLA7Rz^Ms1|BbteXQ9ajo`GhAKCo} zklkN@5aIy_wj_}653yQ-bbE6gW8DhZeH>Z$31r;XJBJsn+VF27g-PTF)(mNa9n0B=4W8w)(5%g3OK=Y zvx36#DmamHuhC^-;J5}(X55OPw0|8OQQZGQspkeb%DF)Yz;WCJ2Q_ywC~$9qLy@}< zq~Gn=N*q_{B2i*m`l!0w4C>-yxe&l0dV3PzD36EL3`Ju(de0~N7fk&YH z4Pr5HvVh#mrUI&TpRsP_XJFtz22ueoFF+Yv07NjboduOu?^rK^6uf~eC}m=(XAl6j z+y%f9%O(kGnSN#c0aC^+z`y_%=2Bx|;NV~b8O632RG|n%*pEQ17zr?&hmAv%tzLiu zS{`Vzy#uW{gOmr_U=@sz@<4}8T7ZFpiEkk&7wNLqgA8TnV+J)L^w{`8eKNia3JeS! z`d|(#1DgXVPZ_YO3otP7uyB~Lodj7TC&$3RVG1^vfp4J*sD%dRF!F&8^WrdP1C=vO zd`kMD>IBSTW?+j3wVy26x6V1PKv53GTKHzl)-fx{o{ z4grYO0bt!i5TgRY9AO4FT~IUyv1NixlHdqs`v`YO7{nbAlfuC!LETXw0oKh1abhIc zMs@}^D^To2v26w!CC(AUrYFR}z?)f=&A<^0R>Hs+%*MdL5yzIv#K0iHm!iYKz!A>| zst^Pj*t$TuC4ud)AOi!J3`Y`MgAfA)_fk+=Nd|{G_dQUyNdbpbJ@;c!Rgem{fjbh^ zj!Odv0XJwSoFg6V2?n+%P??m$W+lYHz{A0j#kN6+fq_p4luxq3>4bsL0Tj78UC@^kpdtiP60=MdXJFto21N>sH$MY|38x2`y#VC* zP%!fkI|Bn}8i>gw!pX+CUKCpWa0h|y1_sVjuznr^&I-nQF$M-cUTFpf&PuQ#10QG&H)j=?!^p=4 za%44h0OkP;0|RFbScZkKmW_ddvlhguXJF-f2;$X&cnoZOi$U(L2Xol@v?UoBI2#y2 z#V`k-G)P$^*f=ge&{Aa1CNPJG?<&X%&0sxzd`+Oim=-XHpMlLlnSp_`l@S!GJS?0Y zjO)Ze=H)4jUdh>uqsd~0g4wk(0(7z$&9-oMoeSW0}XP3jhK#X#0+F3W`b3*Fw}FhfJ%6_ z+j0yHoU<7Jg3J))oXeO3G6QV$Jg_zfK0_`B2G055*kWX0+XM=$1&j{jU}rC4oFWeL zTxuQz=VGXx3Lx(<0S`~IFt9!4WMJT2%2)tWFT=Tl@gm6lOcsXe!3V6wRlsUjgVjnf zurW(8FmSG6TmVwb!MTo+PlADgFLrw00V~ORu*!{Kl`ITwpxrB+n;7pxRBmCk1F5VK zU|`_f3U$RMP;%M^mH>qp$S5{0P?p`!C?&zbz@x*tlaX1Hfq}0MB)AJ4Neq0Cgcuk& zcY`HZ_^#?QFmUc+`>iJT%7#KMBGV)7;%91Cb*x1J?DhVn}vQ!utIQN6qiSRvO zW?{K0|VzV#+RU#-`WhEETGWlWcertDsDhA#mQm zamD}%1_rhQ9R>!@D`2yDI5=-GP6v7Tm=Xg6=S{F}41D?^t8alhOnkAR)P5VRoQ1Ck z6zz8y14J1ZSosn`o8~z0GDd^OAtA21$9Pthfq|WY4Yb;j^FE_JC}4OvA2L1!Suz0> zT93fd#lW{vkb!~oF_^=`R|E?0CtyoB_-^SjFmOHvb2u5;W`Y9p8RKHmXzv%$aNY~X zpOOp={K8TU)(is1puh$dE=cV@9t+ObjIB}(419Y*9(e;ciGlBr6axe2TX6bi#Eq6`eeBKn{PL^r6FCL)rj$-uzX0}2LF5i^k4 zy&$%j$Qw2W2ChEPJcYPOr3wQBS3juwk`p(L_+RD~P-VxpDGK z&>}qt5zqm=1_rKqAiY;bKzWyIK4?Jl8YD2kgIbrMD6F?- zU||M%Z^0~S1_qY95)2GnOL#$J^|G=I&~6PVH8QZ+vNJGnEd%Xb<_B#}761*6fs;Rj zs14W3)v^o>BITesSOp3v1`*H>Q?AvZ#w?=1=>8>H&$YZr*kBC-s$jFW3Oh{MLf!X?JQ zz_k~2Ksbve3j+h!8Box%ECB_`Wiaz6DD~U|Gxvic`zJ^v4-Xd$V}Tq41K%-Fys?7W z41Az77`WJ=#mpm6_(Iwp9DGrr^u__s)SL{QEY6@%VcQQjSk)aq(5hrE4MxzZ%MbYUq!<{uG{I%m z6KT-(0$e(bpp4JLC_MudQ@Y?b5eK7m11Q||80$eN_(m^FmO3B3d%7slrT#Bg7S(pIEpG5r6+@&?E;poVU&I+%D}+o&giGW zz);I5{Q#8By%<3|#&0l6_kq%;HzSuc1H&yw22Peo9H1I7u$~n}sYx?1u!CYR4%Ev4 zWiU<#wtpZu`7qu9P4t2qE8M!J3JeVFp#55{Fl7!5GA@kVep?h77(|wfGB9xagHjiR z$Zrk?2JQe5n@I#TOTiroVzY=W)M8-Z4g#eBHjzwa1_th=V9?MUj|gb2o;w6|=m@{8 zf+_<8cNj$#NlC-eXYyDz#R#)nvYS|95ibi1xn>= zjI#Im7#O&tK^%2P*+0|IoV1dxe+lY{#)C4j7NhKD76u0HbdUmVM%lBH3=G`4AdU{B zENJ|jy8tx&t;;C;TAG1@yAb4BJw{nAZUzSKB9Jl@Mp<=`|B68}ri`)~f(#7YB_J7V zM%mAt3=G_*pnU)~jF3X>6sY%G4+>N!4iL%Cz@i57dL<|nWhxlCTREFy=*85p=bK&e|m#22Km3sjVdh^z;BvKu6BA`$@#ie8Yog~)Tz z09GGJJVFF?p8)p+ka&HJNRS)@1NTIbM2$!nC^RO6BpO7ffHX`2i7yaY4q{IOi7yfP z35tg4An_w2*`QdM1rk3Y@)|T7HX9`VLIiYF7WX{R?8X}r&{hNP`5^HxB0ppq7`PXK z)c=r`0jaNF43dywlm!jQaxVo%x(uUiAt-=Xf@BmJWkFjaxWUD(3ZtwlC^4-EP0DLA z%7Xg7+#5lCXd^~h(8;jen?OT0NsO|f@mTJCpz)?6Mp@9XE%$!VkaIDkY!S$Z2SD*% z0!r@n3ZQvqe`N*+5C+Es69Xp;XttH*2T1ARtBRmGZtg3M$_xx5Q$PviDyVE=5CM&1 za^D2SH46hv9Vk$4B`7m6h?a2Qxd>AGosEHk`z}N+Sl>Mmn?;0CfPsPgF=)byL*!4r z6axeI6OeNXz||f1a}c|bfu#c!;xBuY85mf~B^VgEKZ4Scj0ivX=XI(K3?d@h3=G^~ zKq15+QUgkKKS6=Y0&X{O{|4m*6%kOof%^}LttJB6(8B!}#MTg52%6gX2V!f9)K3Ft zo&O+?4xg7AXj3S-$*RXU55!>va}4-Cfc(t_<{0s%fjq{{2wL51!Y2yS&k8QQP5Bmp z5;+&REVJel1`SW}fXiPSKG2d`ZeDQ7?7+7cB*O=msdwSi2PJBLu#^YiL`4P$ZUL~A z4tGBq3Mj3#bJM$q6b zj|2B&Mn5$M2EKbD3=G^$z+u9`_e=&fiU#Je@V%P8{G63qJtrtNtOVOCz_%Tg*4BY_ z3i5%*Ho4b>IqHxiC=N6_2r7F-8QA(j<=95XJD>$c8QfbLwba2wQ`rpM+ZaK)ih*x7 z$hPfZjsV{#kmq)QISPE|L7ZJ+PQ3x&E07a+gLw|%(NpfdjG)oe0PyH3_damAMt}z% zx%Y!PQQ%Qa?gL;~$AHH(xetOlv3#Jj1i24^IdOb9K+6vfgE{fw;Z*LUVBaV3?F1DJ z#~A;ETA(QmY-ON=<~U=P8Uq7Q1NTYBL+T6+eA%FkbPAkS8Nid$+@~2q%{w+eW>BP_ z0dv^FBbVG~!OA%JHh@yvMX-&0e4v9*xG#Y@{Cx7D3~~jmOn~nbXrahWNOw{UJPOHu zmk~5{EzVaA3buRT@RVR+^XFw?;C{de+B(PfA5`+b1{)`3!N~oQ@uVgL1D`i2dwv45 z8Ti(KBJeZgc}>v5kfWfS@&(+T;@~R*WumWO-}CT&1Nr_N<5f-2;5{F>#{CWsSsCzR z0PY`PjvTnD#r+fPW(DwK0PbImpfXpD&jwTw{bmFm0i(%h4yyY8fE{MZrwXcQ_`q}L zR($rL8bts+cW%Q6I$(rbkO@@P*7AXCS|O(C9v7{I87EDTxo9P+p#^fiI#}y0J~mMP z(*RG%&*7_QXJFvg1W$9%<CS_3FiR4zvYv6>m~bDg(DK6DYN;k^TxQg8i644R9SsY0%;C++koBn=ncT zfRY7d?Sv_)9s%VfP8QH{*zBNE{;4K3OEWRB*@7Y}h6!|tBTp!II+Lds0|R)dTMZLKxVN zf7ynC1KVMc0gzP;JVx9zm@b1XtOAApOfZ{)ZyqSQ%whtKc*^mC&ZXj>&GZG7 zb2Rwgfns|uI6$@d=74Izd0>tX-)~TTJs-@`;{%s;3z`Ox*uc;4|6DJOEs(XR8aLN#0+XI zSFlOjgUSaH@S=wh4(XVBP^^eDg9^eh4r$Ol61NywGLAzUG1C*soSpiE%J3~I4F6_@q_`Q94LdnPXJ0&=zunD<;< znhSKo0=F%g`$Akg5!Al31M^;rOW#pqVBm(V%6KI%4Nm^9U@KmWOM}zD8#5^VzY&+7 z4q9vJ&aA4 zHFH!Xq(K+@aQlEYs!2#s0acj3%*XT?7&IiLL0g5n{g|(Tcv8~uK^2=nGpJmCp)9== zE3L%}xuRF*ylD)Z~Zz}#QT z(x3$`+~Hu}Z)IuFBA!K}Fgh6cy26IUW`1 zt)P-22F&ACk$w%bA{MMtKt*~zC@K<|-{>(g$fz)|gL)b*^`HeVkSxi`@|KH%fgO}d zL1`S^_F!UQm(*rp03{a~f0rHu0|64(OyrJ!|a z;B8vZKx-c6lo~NGC@cgyFfWFcfdRCOOa-)5jIjXZ7tp!3%qn8K(-+*Zl49IDefJG3 z83E8?HjKrfF-vtu1_q^7)1Tk4lIKrwVqj1MZG+5qVqlnLF#Y0H1JUWemkjt!)Ij_E zvh*1kHW@H5s53?}O$<_JjAoh`pw1Y>G%=7t8MN&UtR1wW8>IaMRD0u1D=9v(4Cpu^ zkc`Rng{$qvrtiOLr2vrt9sL86D1=BzXB6^I7r14`1Cb43WMBZvt^>)ci|(%Do23iA}G)WhDvG1ll_f(xfr{;Vmn%>G~T=c%{@CP zK4?xCbP94QT)7BXc_B!-@;1;3a-c+al>rjTyG$UV_5Fqc-}IonR>BgX7*GZckbL%T_(g265#q|AmtyEZhofsG*r@y#sC6f#bU_)5Ya zk~o7w3}{8N7bD1{pb*~)j`xdZ3=D?gfb;^7=1*W|U@$z%0lLBkJj}I`nSsGbYI^!T zD=m9(T?U4SW(*9hATKfKM}y9i0bw&(0EK~ltir;;z@Q9@P_R!x84Bc+xak+}Sy_Vp z&_12-zLkpP3?~ML*=FF>0ZOlGD;O9UK>pe@-TS_k3_RhOs58be8bAv=kp1A|Pny9L zg0e*i0FK0vidSwP}((*rAEE>P*F4LXLeb^7@SR$^XW7SLFd zV=x6d-wbrNHzVkvUomgq{(hjegGX3cif4A;gu!GwK0rl4B)&13L)jQuuKCw7764(Eh~uj zLyxS4>p?+cX9dy~#Z<(=pbR>2?E)w(nz=GFFff8@3I8}K2NcR`25dfD`7~n8v_l}*-)9@=T>|o%Ahkl z!5TqlAAmGof=XvSu@cq=6|WzyAwgEg04k4*K;d#-^2|z7 z8RYp5P#X-8!%PiyC=w`0&reTyW+hb*QizZ@W?(RQ32GV@fc*i=GN9_8an3q>SO64& z17HRy09MK{FfbN?J9j%le9&wsVOJXv`D0)Ej+b1(kPT(-}i71VI-Pl!Ik8IH7@C0d|xdCj*0po-P9e zV0xs0Ur<$Z*GrfnlE=IFvzR49cLhA;3ZA1xfq~N=temM-i$NJw--A`dQl*m5R+4I;ofsI>p{hactZ0xQKy_Iu1B2Ql z1_lODV`9>D@fTKVOdR^t?O#}l8>oY}Fo9YoN9>_Rry_$v8z{J!gM9`HZqP}NjC0O8 zfP#B^+Y2i>C9v04fxX5wF+dqqhl8C3I%F0U@1712XWf2bC8-SZbF2fz6B7d%ltJf1 zfK|sqy*ve~8kCxZl|e@ifKrnh=mZi_QrJD+_obC&J*Xg22A$OfDm@s?6hIOA7hHnw z23NrGj-c9;f$={$x_)yqFernL3;Pc$96{$aa5*zD@Hv8<5e>?xpc6j8a-dTRKyq3L zIncr0U^&n!%pf^8(2>vTj3ABLpz2=O8DvfrIFEp`KcgW7gV_vF3ttml(}7AG#yJxm z85ooW7#JAjof#Owl^>V^IxY^xU@%Yx9i-vH44PmCg)=Dh80TCCofZwQOgMXlXdSG|kdVwlnIAk3M}W^c*GzyQLmKK3$-3=AO5nqaqwhk*fvIj*tW zcgZs_fG|(6eV#4@0|@iJvY)EUzyQL$ukF@LGcbTK`$0xK7aax$5awFJXqQ!|$-n@@ z-1C_oL_j;%I2ai0Jh&McK$t6%(QW}Z0|N+iDzez`Hij+$!{-xYt^d2 znUh&u5}%w~khA?Kuk{*sp2U>0_>{zw#Q2=lyy*wSEJU{N5VekGncgm8(y)Dklr_H| zqv7<2+STGL7RCmK+jo0d7qE*O8yGUg$Ge64Ifr=q`^CqrSQr}`ZFdN;eqbmm0ctIR zjzI$5!-T|ko^IJ>ZEe_tBs3F=y&Q?X2Z?=h`r3c~;!KY@rtfRA7BiFv#WmD)Q1QhG zWt$<1J0Y?Crn5F%yGt%X655Ew-akFH*;-lh9g+|z&%sRPoW8KxTAWdP`bV_@aYnc4 z7n`k>>q|jB6{xjMNbCtn?4?NTjY#ahNbHkH?5jxZM@Z~h_PtfoZ0CfSOY?tJ3b5wI5_zMAfPHdB0h$JtDt`W__lNl5G&NbGq?>?KI-RY>fO zNbJ2x>^Dg4pGa&rQLuZa+jm>D+KNCpV8_SWGQK zlHP#CK7_RzYGL zBC%bkxAt21GrpW|s23s5s{tAeh3Yn$ZrNvTEm?~s)P=;JF}=6XTAA_q^o@Pi;;N63 zWZogMWkIb$sDWD3ANE;`PiN`3mZ;B060bmF_aLzsBC*#Yv3Db}Pa?7JA+cX0vHv5n zr9tgBHPHHD1_lOo2nQU;po0Zq@fwXJo{q#WMq*DuVlPHwgBooxb3mIFU~JIUJTUfU zX;3p38Y=gZG=tVC!4!Q*5|;*b=b-9AvpFy|#z^A!NNjH;Hs~51nEGUxIH*9&hjBoM zdm^#hk=USXabTL~BZ;p@VsA%cA4X!IM`D9+yn&hX12nG#<1mAc+JpK`4vFoE#P&sE zM{=vtClY%;f-S|c1HoZ9jl{k_{VjKbxb1r+p+87$(8LeS?Lwe_3)Jnh zNNkPitdp#jCBu+}l9AZu(;X*SE2}O;655Q!K8VCVJH2y~wROF?JfbWDU04EhfDw|o z0}>l_{|HP?43c;j61xJ44Z2SRrhW>N_#y}!lvo%THb6Mw%(4%OeFlkr3yJ*#iTw?U z4Y~#dW|;3h! zKo>y zcta$>fgFy+23@)UQbiL`;o9abD$5}$n1K%JIWg8%ggAS{QndgHf9)-ltKw_66 zv0ISXpmXJ6=78^aR|DUT$G~tDNzujWg)^+h89z_2onb9LeZdTC2}u*sh&$9>pu^T- zX2egwIK$eSaqD!(nbzXdRc2ZnNP_S5hANc>9iIthYfsOeX`QVKT386vy%k9sbm=ur z{QUI4Gp&C!zMTGcmbLhFf!WpxwiTc&N}(pTBC+QqvDYH8cO$W%O%T6GQ6Fb7F|6%u;~68jhu`w9~K5fb|Y68j$#n@0z!i2ypx3udtf zXify`GczPMXn+W&CJ0G94~boa#O^|3&p=`?gRw#W-vZ+>FfbfKVuQBpz%09mB>o18 z{R@fBp^GSD#E{r3NNgh{wu3GMLp{s_KO~75Bz6`Oy8?*~IzSDkcM6jDA|&<(B=$Ze z_8A1bp5YdP!|(!${SArD0-E22Mu!j*TLFo!hs3r)VtXO6Baql>U^XcHLFdVXIpFli z027 zY&!;qdeF4*ZV(4*=ur?Gs`)gC%>nWKd630W_AQV&RLv6*8*1@O5F0A~8N`N){{XR} z;!Fk%42)25eglSjI7b8|0aXM#KNP0O5J}t`#D;2i0I{L!{gBu(AU4#YsYvW<5Stz1 znHD&^o`Ink&S7Af3}QnyZ$@J8L1JG5v7rXtMq)ofVt)j&q2~NTVhb2DFfc;(N`ly+ z#hxHHDSS9RgxQ)x;vP(~#IjAU0HQH4=Lwhz->{3yEF77>TnU#D;3# zfy6!sVna1wM`AxfV!r{gp?bd}vAK;9J_a513iG`zL>!X;G(jAwW+NoF2Z#-|I1q^) zg~Uz+v7vg)Kx}B5XaKRfKw-%J@#0D?$Vqk~?v7zD>AU4!-O&~VtSP%vV zhBjjc24N_BB1jynW;Tcob=+XU24Nls2G9zf0+2Y=pfV5}s=gkHJr%@;CY5NWheVff1_S7{rD~nI(t~6^}wVnf3~%N&%f zpoW?vNmzl{P;nO!8??%cfq}sj#D-cNgv8DOv7sSRh{Uc!VmE`>P;)v#Y>+viGvp?L zIn#rj)3oXjfY~6wFfcqpV!uUVGh2X41&A6RB(^9LTN=a$SpYiBABi0RVnaO^4q}6D zrDtGZh_+y05Eg_+M;b^1s;Cgeh6Yy|hz-?HkHnq|VncmD4~e}TiM*<*rGFqcR6G~NhKkoB zv710_sG4378>(g!hz)hbY$WzZOHg|n8jQO@5>WPGB=&g_8>;yR68kk0`wJ5LFA`hW z3XyJPkl3mSc0GeOhy%629*OM+V#i9HR<2K#>why&HU6p6hX#D;1>?y~1&9qbrwPP{hHfv24Z44efq`M74FiKPm|f4n zFb5<7RkR$$hQ{9-5F0AK9mIx;A46iF2C<=PZi3igLm3zzA+dje*ic6^+9E=N3&e)C zr^P@VsAhR2wke1W)oh2vc1L3Sg4j^KVMy$FBz7r?4K=3@iCy20#F-3YLk-%9#J+&U zeg+zo z#D+APH!&`~$I}ig+Cu7(la! zpaNG6iLC=-gM7fiz+j5RwnJijf!I)s{SG9q1PXr!28Pcd4pia~5}V(Vfq@Y!E`h|> zMq-;FvE7l_As{yNs-y%E8|t8R5F51i7PP{z-jRU;bYu?5ePu`zAaO>hq7EeSNgy`V zpt&G6=+-a>28M+obD-=sAaSUg?I1QZTK9n1Q1Rm+Ht4cwki};}9H{1NAU0IdJ0v!n z6CzIwA+hB^Z0L1c${;pWuRe$ky^_iW#D=Ap8jx?wRn9yl29KKdlC|RCK7ut5_<^}dj%4E0}^`+5_=C4`v8OuNmnNz z98efDfG!z<4bxpj62FSXzKg_uh{S%0#D0s!{({8*fy8ETMw%UCaYn=(Hxip4i7kS} zmOx@FAhA`p^KP+jHekFmec}^q(2Z0NpIG}(e<19_GTr2xf~Ygo z6`xsyE}trVX6--ygSZRJ^drx#eHbrH7kqB*&uMUyfdQ1Ev!^SXH_A`n5LeDJz2~{L z3ZuvLjnAz?_aHI8u=eLwIK{y52b5137#Jj{H%7Y%PcL|3ZNMaRditUl)}T9?KEAN_ zXKb17_|n>+Q|BxL189F%_VkS{^77MnytLL}+%Wy&OKZ?&NrtbikF)+b%fO&A{owZ^ z;pqaetu0t(&Vl%XKZ=B>C%m>!V04&%@U^u+lfk9wLT{`=_i81+vG!-uxjcOni0d+) z@vXH#qsR0>5EU?eA&APE{t-mEOm}=|?a$aSeIkfTnEnt%J(+I!-Wqf-S0jk(n11oS zwLg={qv=W?to;}}rWby&_GjEO{UC^PnJ)Oz`Z#ODQwD~H=?niA2~Yp<(OLwwMsPE` z@N|h!)&i^yuRu5H=zg+RW-Oi__{mzGl{JBZp>z7jXZ*s`Cw#INV0<%uAxO9{i-BPS z!8EUpiAwag3cj&#lgTZL5_g|dJ!BrcQLWBX6BWEt}y}4 zyD>AdZw4K7X|9TNYsxW@2=han3-6AfUYA6;9!8=n(|5perw7X83qRi zCeTa^12YG!wKDkH6wsVBGYhM&IQZI>2_n#IQ$9&BFfcQ6ER$qlV2KfCU|@#anlgEM zHlK|Gj{!&)a%;-z>C^da6g1=c8DMv#fbKb9f!vJ(zH~(sdN)cl=&FzS=@0m9beXKB zAs3+-D1t9Skt_!-VRix^t;PmAW(sx@O84|Qej8`T?CFd6ZIl^bPd~rY5n3$@xspT+be9A_=)hxR z(9UELAxT;Il_a3~5eDd$Bto0TreCZu6R%$lI#JGi6X*sG9yXhNklnjf;dhbz+v zGr)%+GYbTPuBQ?BF2=yXD)7e>uwHVU~oWHIPS+SV2p1_s`K(7h^opcxPr zVa4foLN=1#BB0~aCV?V~lO-8+I2h>ai~FGc)0Lo8+@V)raJzt_27dL0J?ORwBc|Of z3=AS{9HvaXtPBjI8>cT4va!+-2U!Qb)Pg$&bObK+QVZ@2pkwar!MjJ8xl^aJ2-~RD zKLH)L9su4{zy-RqA{lg&0Tbvb66l>3-07gxWubRgaD&|hy|aS*2ruH!3U1JfdJgEF z72HQbo{9mR%F7KpRtI)x1@|t{F_UpjAZrA;*T{o-&^s%*kAR$)$P@y)vx0l=^g|%$ zT>~A+4ZV|sdlTq1Tj-q>-1eYIK)I8m7Xj3&K16w!fl-*3GPS7D;pere^gS_<< z6g>q@AaxAfB^(S49MCH%xG#ZX3wk95H|U~bj&dex76yiT6>e3~?E)2GucUJGg3dpN zoaT_mz-9tErM!lz9&}`v%B=O<>K83~WK5la!m89)s=* zkp~@zyqHOzoq>T@A9OJZm;i0f0i78RG7)qoMSU8`$V5;YgWgHOEeUe>If#*vxPjkE zkpObt1twE=1_rhtpaXiLS5hnhU5Ws?l7b6#CB=J?p`bl`91_e$poTlQCP=j;MiiGlMRv5o2Iu1*Jhn<}T35 zXP_%7EJ54)!8WQQ+X%gq0%8*MN(zWcnqZT->KWL$LC3snGyet|1-g@>3~rP;)Tm@o z8iC$P!EFdS_ty%%wSoyHu_%uS%Z8K65Ugg6-(M8RHi0~;j@I>v#+of#CkqH96f&Vw1`ZP9+2QX`KGBEIhPU_+V5e%FXEFf#x9)Z%7 zFsnN!1A`c-Jj~~uK5>Py^mM-!#_U21K&eBPwHhWllXJR5gPDYo1So^3vMz;*p8#u; zs02Dz|~ zRU4FSxk0D8a=`DOC}v_{sOM;4bq1XW2)cjb2Hafe{Sy##TanFeLpHY^VlD&Q98mao zu+9RR1iF6$bgv9I*oDyhCm@9y^!^EMD^Qm0W0huMsAu5hjsw*l(EBI2r-Djd==~Gi z%^*Kc1X~iwJrksC5||UjeFRhvO$IwGnEL@Je5QaoAq;F;pj^d(7wxyr~<236EkV&BXC&WPKb%5P*9vTbRK}B0V_yP*h{Sz&q{CAP{6AuG} z2kTc9w%$qEW;(O6L6-eLuXqUb7+n%k_PfDv6C0ZO=cSV8_21v}_2E6Ak`Y*#>K z?LAf{Q2R|4l=~mE?%{(L8?qZsvyFtptIYdH%`ca zPVtA{IB^?PheK|h-~!z^u>o`dBDe(5Vgr=`43H8)n+<$AEhD4|&|&l8V_;z725ofa z&;=g?&&<6GRD|lWIe=Pq+>9V&^}!rg2DT%hTF8Jc0(9gp3x^3C=wd?d3{bu`1#4#D z-U$j7GcbpddmE_Cf!;X5Jss4vv0zgGU97^)z;+xI_?B#YKt_SCoCpNnE{A;M1a}mu z_=4Uz!3~-<4&nax6fD&B`s$WvsKsJa@12uQj*g!!b3L5F;NM{3if`RQGC^R$JvO#AZb8uv_ zJp_4;5tK8s!Rds7dkrXVbHEaygRC}!ZeY{}xiOb*FUWoo(3KOGg0QSyzy?aJkSq(i zaYA%8CysEX|~$oRLQ_C`Hhpdd6iW`S<_ z0B0L;<^pjUI9Wh;a@B*boLB(5zaz5=$8@n32r@8;fNq>P z3v&5SP}=Tg1DPX^eB(qas1E99TLbC_EeG8`F@^1^AOi#MSCE51O$fev5R-wE1!N2t z=*o#)(D`DAKyf~Y4a8>P&H@=emkrd(V&UEo^5#6YN{|n^*MP!#K3hHLx)1JcpqN;| z)+)rnAiy02s>~O%bqg^th;W0Bmf~2#Hc^OyL4rF0NWXK@t-oqT%}8b~ph0H;y~qX6iruOpyS?kmA(OfYbRZUco~^1yvyx}u_u1EbFLBt;vw`d)Dc z22SWr4BU>O&Mf>U22PM|t&Ca143Lu~bwEuMXh#Tq0zdQ+^+1qSp3E*H3=CqRLr@|_ zU|s?Fhe23}D`O()4v(*(iV<>#y3iZY8OT{tjFF&QI`ctCCuf7ya0tnP+SJI0s4s-s zD#yUW3u>+Bg3K4b!BziLlz~C$3rGlZh`P`-&|%GxL)3-*rY9)bSl6Faf}fQxkq9~; zy(2`Jfk8+Da#ni0FzDt=Ur=7}29+-&LYg4;J)p1@6=G3kVBmtBl`bR%>N@p#Fo7<# zyaqauyB`!`azd>jHsq{yAq9~CCYm!dFenJ!133kHR=Ut~(81JGK+bg(dIPEwrh_b~ z7upIsXdQA^x)3PRxMqSp+alBjIud)9r!WJ<1|faW8R~ODhHeo8A5=XT6vS7A&WOU# zN*Ce=g&*=+>71ZS4ir=MwhSzaAnz?$0~+M|2RdSWi9F~=4Smps8Q=;TL@=-ff;_m) z3MAzPlJa9@U;tOx48k^CEBAsf`s4;h%_>khF$f(7ozD$9D_!USC@#T=_p%G^2RQ|D zR=SWk8^d%76&wC~kZu7XW6JugeHT`fSiynMdoL?RA0PZE44I_Sz9?zx~Shnz~wzzrI$;! z$|$7|ihq5^D9|+#j8aFYGpgB$#7KyPjy;zGZGPf1Wdx13Nia(N0foF7_#zY)Myb0X zGc6fUih+(jm%0E-7O-Q_rM7`G1nk&zsc)dHV$XO_oPi;YQL1}-p_+|IeTO*coO7v2 zP-HtXDvN{8IhXndatrL7bE#es&jl=3!zgtW6s7Kr36h|5&ZW{pS=5WsQk;R|2BVY+ zD1~`5%7{SEIR{-s%E__{bdL>-g$M%!J17bYKn*%j-r!_l+fok-10Tj$p!=e~fzI>O zZ3i9g0Xh~8bchxBs3!*oY0x?6$D|k-gg})M^qg~{8SL4TKxvtWQ3iCOF?S@$Ha;uOAt;QPz#+iS!15n-5@97M zOr$}lmV5uw!}kIw>$pAb3;I@NSGNc@G+8_=_1c zLCzufiklM^yO)pP&P7VdsfU{RR0AcAmJDE67ohlAE7j>LTdGPuO|lQlN?)exA702T(GE zohL4}5R`im=ZOcifa04S6p`0JLu;TMD$l^y2QuA&@hA8Wc907l8NY*?AE5KZ6F}|& zA4Cg1Pn939~*uflyN#hIq4H4 zh|Rz~8x&oi86PTvdK|Yvc>sEBIQIfj?tmT}&V3f-`)`cTl|bDnaQy{6HJlqFVr77sK;oKIWQ-z_&hI8Kr{DQaeDw>Bj_WXzDOZO$6mU*h%10tRR0Podgcb z3Y;vDih+${J*aKTb{M1uGC{-zI_~=^$W%{I<6tHe zh|R!V1B&KZOrUP69CrlBoY~-$5H+|#w@Y(FPy6QH0jgx?fn{{KZ-VMY=xN{F;Bsgo zQ@Sz(g8}z#P-X(3_Fd0l$iNOV^($y}4C+bH5f1%NHgyID9_VS`pfF?LJ`IYh zpZrW9nJ_8PZh!7yOcSRw8QCb+YlF1^W2$2Zo%1dA1!VnyrfKS+bH1gTL1hyQGw5Oo z9~P--&@suZ%xlyc7@n|5Ee53z*g4-)dqKejJLg-<0c0i*b2?~YJgbxnD60uEgIbFf zY*G_J85(xZw^U<2C^}&0d`k&~!W4GSw-ji^4t~zJ6zIY`ZV6^k?=Fc$iWd}Zuyekp z`JO8TI_F!;5|lQLnD?lI&iR%q6wPN~;5K2tqz*dg zTWTIC=1rMFO_v?wQaK=}!Or=XDhFwVo%1c_0tzSCIp0$ELDd)RoNp-^P!hKSA2t0{ zTxg)`W_g7ge z4^&=8F@w5G3@TC|L2(W{(OW7Jl;mJ1dQ060SrH3XDWD={2TF1Y%>UFOCwhY#;h-c9 zu5+0fIO|#DI2jn&LHQ7rnxVq%+A0hTpo9VApHXLE0AVm6bfWhO@bDL?jA93sTc9uk z%ds=Cg9Jh00_AhET;qivbjt_25gL@+Ss2)&K+VV`W)Ei-1_rqh&@mmL6JHtpzy}DH zYcMd#Z%_jrwFw&SVGNS*2A!7W0xHlLgB1$m3mF*QK#D+H?HMX<85nY>e=xNX;b;P# zGswx(F`dWEMndDW1_OgCs1|070vQ8Zx+9+sT9pFs{J;!~DWC3RW+P?QYs@`6KflhIS8WamNNY0X#fq}6XWCmycdLB9qR%>3Y!c|pgpGR}Fa&A?z# zz`)24K7zTPk%7Tb669BYa0^+PiGjfgH1Wk~BM2U$aA9I#&@N_RVECyG^R+QJL5P9x zAORh930gu5^1C8vX~SY$28Kj!i2vtV+elCUU}3|d3`zi{+7PEt3}8?WWME(bYe@kI z7X!l@s1^fD8)0scjLsgg4Ah|SX}r@5ENukpL9PIYpeBPZ$S3+npaZZ>!T#$3N74@+ zi2qE%{!3MJ;GW=1yG(26OO9oz(J|Sp!;_EL>n7P-e>v@42Iy0vxM=|^zAk_^4g&7!SrvSE9yZ7tT2OR9_X00i;UnYPzDAD&?0EY zIZe~&+uBI0=Nm9EKpb}q*>ShQj+@BJzyMlr&v0z|Lt7hFLy$w1K`y!nDqJm>gN|?c z1UDCSIy2)OdqY?Nd}6#b-Q3PbUY*+zW(NZkQUEZ5Pvv!EV_?t;VPIf5Hoex)MztPf z2Wa$$;gu}|gQg*pXEPZX7*IWH%D`YH391_)ZGTWH2FkRIa}F9ZFj&6=ofD|c1Y(2F zYyW1;z@Q8|=M|hrK*uYCveHtp6;X_aN{pc6m8aXiOXHZXX>TK3&t%8IpbWYPfe*x( z0kR!bOmnh;8g2T|SQr=>1Heb!x`DGjs}ao3AcUQ2Ag$^Q3=Bpf2Ixd>&~_3AD+AC$ znE8<9RtyXbpaX{)=QJ8IFc>}t9Tu9;q`=6}z>vWP3%Ek2XVXvF+h{O?LrGz}u!D`5 z{skij24&E`N>G?9gSMK10}r&89psn;MxelpVl-d?9TULdH9f+?MkZC-7+Di&pCVWj zXxA@D6Spx$lOcl+s59YZ2jenWf)9<^0q$3TLK<{LH{+aoV+IDpgP?;ncYs^tpdlXH z^657nY!vlD1}i%8gRa-G0Uwo}0Lsn`po)WW&PA{x(={D!l!d{XKns+> zz5^BL$EU|T+DHZQnZpv+T_#YS6v@uOU=BJ;`##u7potnIutOez9b(1-ElB0e;YH0; z1_lPug&TiNK;f!3{j{TvksqkCZ!-aVlc^L`lZ}i@7&z>r!G^{#fzIQ$0A*s(-e*XT<6%~wzQD;wj?r=Y zekU7Q#`x)Xoxs`uyOWI?KT0Y+W(qO5%h^U;7PQ>~+!Rp;H6_66K*utJQZv69T%AmP ztp)>wh8e_XAU8)d8ZjuIWME(br2$8%L@~(Aj0Oyf*FeXxYB4ZGK_wtM3>lO`JIg__ zqIiiBk^yT_R2VTR-eF{5040P8P>Es&2E~`4ei%q_F+>n_syY)BG`vKZAmMcj>fAUN zSfy(VmVtO;qKl14Jt+FXWvo1dE+`3rFMcpKhn|bA&Y;f>s=jQ&sc8;4BgTVn695;% zw%|UD80g$@aLTX;uaPt7gr1}eEg;rt3J0SPr@21U>!aeFNW2GAa6CB`UlqKO8Da|Qzg1Cu@jgSZ9Q2Jq?r zb+FoI0<^aAvw#G_C085adQd2Wi~!Y?;5$-54hM&cB7-i-x0W+N4bn1j2LY5dL5r># z=ghEx=5$cxG1!QL&UbAGhZE=oZN@pCmY~C?L0PvQ94?GOMkhdp+6-{0g@aB{2UQhc z(m_{FWHK<$1gmP`WMI%qWPn6C$W=w4`!GOz{6W?zgUUJ(LlKnkK@OL)gnLsF)T9T6 zqA^?yRAm`5=zum)NKZfQW~0RDI{lrSjbuHj32n>he}# zw=xH%n4<{u{mg9f-s^$6772aQjG zeS5%~fuSDK2sE>1U|;}wjM18bK|=x52YL%S(BF%Tfk6WtPG3OW63{W^pzaem4nT<$ z6w4nG&ej3d(z%e5iP3<8!3@;)*JfZ~kOAGCkjcRKALN2|&@mg3Ou=i*z@P}a;R2K^ zlBXZ^u(1>Y8Lm7N8hSdQv)5rAj#F19#im<&+VE+B+zt*9RR&#<-}Ng&XOT96o0*`5 z%sA%~=mLo;)AK!Tq@8R)$*=|7p1jP(z+eOpn^tgp^Ai^|yMp$%LIMM`rI%|1$uAE* zZIqd!tfnh?*@)DGnpL3w%t9M*v_dj1=q?sTQ2GU(Z?zj;MyHU0fq_>SO+6%vLH2`v zq{N^La=ZRPP>#9)&QU?&lE>DTfx!;kCB4L4t`W|_0Irlln?sdBN4A3*ps)sop983B zGqwfW1UmZO6?7E1+ygo=mk<)AKqs4iPk%a1}e|=@+E_oG6=n)e8!}QSCHp-Inpyn;qTpc8~ z)%1z4ZNw#Gkc2Xk*yYm?zP3^31>JZI^U>z%ybjUgYS)ldfi510Nxwr9|HUzVo|&f@ zqww^zW}f2H|Co95gcg9xXQ)GFA+b*)v0ovvML;cfsCoq?whj{8V*1`UHu{pFLKx8x*UlqL5e37tk_-<3T_?&yF!7iZwC6paBec=Zi@p|x4_E4clB=65A4qoruKFMPgSXv0IVYi;&n`A#BK5KnEcla1uB>z0o&L-0&%q&_^Wp zUnDjs=-_#%dv&MF`o)RYyCMmJkG6+O$0CVmBC$)6*o{c+UL^KRB=%Ay_C_T3UI-hs z+?;{oB!mO@&Q&D#LnQWFBsLeQsR?zcC=%NMi5-l@jz?l=BeBcHrVDvTi`DldiOoi0 zZ$x5)Ze)eUJ801wjQtWx%~vEg=yVR48a~j$`B3+QRsg}oRUqP!I0daQfk{|RH~nU# zESUk32Zu{361#JH;Wry)#vRk=?r{|7y^JJtfBMdEHrBkFpdJ+C7!8H6O1 zfW*$5zV^J1cw!fl&mEB=#XB_5~#NJtX!UB=)cA7j@ah6U9J>^+O$|g2XmL zVmlzQ3z691s{x>T7b1zTMPl!q{#TDpocAJ<(B0{-KWz5buK`VVKy~j#V&6q#e?(&c zMPhS;4#$V;6-8nzBC$b@Z&>tMB8h|6?l4+G&!Y)Ml88lOXCkpnk=Tt$>|P}HOeFSF zB=$xm_Fg3RN$KfKzii?R4MD^0P>9GOP;`Pgsgf=6w_am`SBeAa| zv7aEZ-y^ZXNAW|Q!Y_+x=Sm~7)gf%~Bo>1)gaghD_DF2+>8`(RP8+I&4zh=uXM)6b zLShFXvE!!uvKEMYRv`(2w#dVxa2k^M5+wE}B=&VA_T%Xb|JaB#vC2 z5|VD9bLgQ?3PxfVPG|gUW6gMcy5V0N@#!IdZ49RWxnRk|s}GuFfvUHiKKHLpw(2e< zq2oyGt4QpJ({=yZ{AT<;UG~3?_;iQ=HVJlJppkp1Nz;+o8@p;F z3xo}+Lnc8u;N-CYiM`lT42Ek$Yg~a9n9X1bjoEQ>Y1&M8h#CAYp`ysJokl0yB>`)LJsy+{iT?b-A)pvl{(1WUb>OqD=InzNBP(=$t zY|sP@0|Ub{5F0AK55xw|NHH)loCdL>YA%4-P;*`)vA=-WP`&>^Y|!3((0HjP0|RJ@ zJlOxdnusD?9K?nist#g9H8>!#y+CZJp#dN^^yK0YkfBg^JV+d>CKJSlnwbY;L&YmJ zK}Y>TCE7s}P<9W94K-*Qhz-@S0K^6je=;yIECE>tWp4+GL-psO#I~A#Eyqx< zJ`~IbmuC#|AU4!-c}VPH5F6^y1`r!GPS3!=Fa?P{7m2+LiM<|)4Zi#UYR&OP>vNy0vd|WNNgV@b|{DqH8csthUzUtV%HhWe5XbWs8HJXS}Ee8)}d}659ib9S34V%}hsP7a+0A^gyL5)S!Bh1e84$#D;2~hs0iv z#NGg6LmhMp#D?l+2Hk!D^*tYmEeuJRLZBNJpln%?I9Lrc1B1qNM~)=%dK-`!RNeuq z78JPP`y;?=85j~lYM`N+24X|iXF=72ri$u7;!rg$AU0IZVh|g20Wt#v!zvIPD!v)Q z21f+L9ta2Q;)_V^?;tkR5#TEwK+7~37#P?L5T^-CgDyURTC4zKL)EB2)qwgpx*&0= zIj$f!RK1r0s33%D$OK71U0MKQL&YnR*v%j|)Sx~PTNLbOhDjjHpzOIIaj2RVAU4#p z?MQ6!O%EXTApakLY6h)&JPA?+)%*~|hH8EWVuLg=Ffg!!Edl`rg z)eFA$0m=s7`T$|qGn@b^f?9kY#0IV9VqjpnY{&pVn)V(@9IECOhz(Wq8HxP|iOpt& zXfFwZ*q~)s3=9mSpc@*XYz2_G6)5}}7#Orc9B5D*fY?yWz*j>+#lu13P<9N64K=75 z#D+#k6NnAf+Y4etPa&NMvKY#qgCxGR9*MIKiG2`>eG$Zl8hQi7hMq8b2V^Le{TxaB z0}}fu5}OBfn*vn542W&T0BMM*gE*jdlAw?P-Qxgdn}Nik7CVC2P~W?O*ii8hBz8QA z4ONo@VnfZzMPipBu^Ws*1tHX+c8~;Uc|QXKLpR6~Q1&#CI8+Vz@(HK~%aFu3g4j^; zZ6G#O?|vlq2_*I<5F2b}Jp;pC5C?koz(bJ5Q1%;;I9L$_!*>uHY60j7Fh(ew8+45W zRE-#j4HXApPyrQJ1&M=}gE25LXo1*J^YuV?Pt?mYFn|_TnS&&t8r+fCK_E8N&~OkN zswN4#JP^degI-aUHuHihFb6!#0FImpkf$w zDFoC(@*pu)_P#R!_igST(nt&QA0AfS+Y9g_nkl4{MHmLkbfpHiZ7;2H&6Oq_Ukl1UH*oQ%E zs3XoGv9BVrZ-dxS2R%Vze=`F$grS=MgCwAA4$v(UP__w(4UJ=K5L+G`8w~d53=G0h zwiieoswNb~hDKi$hz%7_1+k&xSs*qiG10cHP#ii7>n4!ZpTDj|);HbG*0f!I(-1cKPgkkASR z-H!ofCxFDEYO0Xf9Z2j+AU0?nF#`j`bW2eA57oR8Bmrd~MPlDXVn0G+{{XR}Q3D$D zf@ek01rAVg@KqL2%M?K3Q1dn6?0NiE-6#QNSAfK! z!CMPrL)Eu~*ii8v5F08!4aA0u&jzuf;!8p7deD+dP}3O1fm*N*Y8hzJ+IEmQRKr0K z8)^{vx(lfI1tf9sbr(=`?t#Ri>`zE+CeS4hQ1N;;YX$~kRR#voN;Ywj1k?gq5F4sU z4T)_7Vnc)16^ZSK#103sp&m;Cv7zSVBC*RLY;gKx=m2q`hE7Cc&q87^2C<=r9s{wV zz6W1x0a`f8z`$@3c~RsAUF7Y&Q@a>KT6|b_5bT5yS?WGd)(qR=s`?hzm991&9r`?mdVNTB^yw z!0;J#`vsKEWy`?82xSW+v1O3hsz_`TBsTay3aI(udnc?Q`f*>4B2A z;*#JiC!o@ONYaz0H%i)y*Uv=~T7tx0fy7>q#NLd=-i^fGkHkKX#6FG0zKq1a4q-#m z(R~O9TrxdIV!uXWzei$!M`Hg*Vl#s-gMj*#9f{44#1=+kOM`EufNGFOl2AutgRjVd zsxd|qH%DUIBe9*4*xpENeDob8D{Ix#BgGIRG6(FqsR1>VPFG(f~YOiJ;QDNnG{Y=pA~NF#~3jE zWw@4o9UGx>dN$!aUh3ZnJyJ?>&JLvdS<+>KjV(+JL7HrnGCK^ z=Sr~kWBf2ZGQrlL(Pa8c5Orbt&jee4CW%|qy%KHx7$;1hnFtD(+tXixxJ#y6CfWKk z$=sRVm1OJ3_+;OtaNyY??kd%~qLp$~y*zlIcf5%w1s&40on4+{`XKE!|dtaoTjjbX#>M4z=l4 z>9%T&%cm!TxC$22yFlFO(>JEusxxkxeiKAppU#+JtIqgmx@Ly0I_t(#28P|!Lo;lZ znRDhaO!wc+E;@ZehOGeO^63jf^7rR3Fx-HgLjM3H{9*b>knr}o3=C%=htL~j+6wTR z1Tr#!7QOX@M){^EZWEGbZC=H|Fm?LFucE@!7o>9w@JeiBV7LG}44#33A!_=?XZ+Hv zFZMAoxKDpLPfU3Fg-lyvl*8rCOpRfO%gcP)u9s!|kGCGw9RqDz1062UB+bCUbB%?8 z0krNw0i5+A1QQE;qXGj16BE0mAn43@@KN(DaUdZ<(0XAeMz#<^1_l<;?n=nv@=S~z z&)GpbSYIkIFt7-M*kYhoJqzgYCMHQ^1_lO}2uTJv1|}&`mBz%ux=)UQfr*1%0(AI1 z3u}uo0|OHayPP2CaCs&cb`j7?>MR>U(>aVB_eB{PSU~I1phwIbPXAb8tH9$U!oa`` zIb#0PblFN<1uf7?pe$-TK$aPCF)*-b+ypT z2$fF%S7j?+&mqFVz-B1T$iToO1UjUL%?QL65Lyd5cGj4ck%2)(2(&bX%>=}j5Yhm5 zJAZ+e+zWvYK43Eg`A?34jb#TD$orsUBw3z-g54Y>Ak4#NQwlnVezgMP9QysBv+nIc zC#$jK3cUs$eqawWkb{ARR}pj&y$9$Z`c57O2KFwH;VfOCGXgyigCZdibnsx}LeSxd zAgPVa3=H6Kbzoot9iPb21QKO&0-cB0dYqYoffuxeo)4sqfrUwSI%AEkr06=(Ik1yJ zfx`tl_FV>ac*fM}`ZcyvVp*WW)s2{bFhh@c_hMmS5WPG-zQ)!{<0j~Ib6X~m1&rL+ zLFX0PfjLavSs(-Lnba5=7?`z25CW6TVl%Tk$g3j@aWZDKwFx*L?0}`Xadbzo6K<9EsgE>6hdZ6REV!#|;ZqPa{ zj#wrE&{=fcpFyYP#xa4c5#T;44N?~mc98^k9LRZzOi|z?-mgrrueDXHPX(QMn+i5a zmfH*DvotVAj=KhQig-GhBhSDAiu4Vv&_HHnVBf{gz`&8obPRN6KIn*d5zw&~(?Mr` z7BFo9P3v--vV)I!2L*-#w<{=^%D^60;{FUe=CYh=8Z-Ea_X5xR2dU|^2~ z9Rjy57nq7b<~xAQ=VAt>0(S5rUIk2%J+)F@_C(kU$ z#K0iNz`hX_Q;N*TL5IG9j(9JF+o+0cqZ-skut^$VlQ7F`7j3r}W{yG56QEbw9mIfH?H4JbKyGjnn2n%vl?9VPzLRC$0TaG9{X&DSq);j-XQ;A* zmg$34vvN+K+h8kg!oaQric39KLD1>$YMcxVe4vO#5De_;pwhsC)d+OfJIJDd>0XVt za`o=4APzfd?;=MCguNf+_&f+(5M*IFm<>MW{WR#bmQGMUsAdHf8w}jnK{>C6HHMRc zfsGq<3kOFnYYFHa3~o74Nmj?20SYAUAE2|h>sdj0l9Pe`Gsubt)&|ac1_mzBG4G;4oQ$ta~9sHv`8ah-PjXb_NEH#So7$u$O}h>?N!(L8tATfr|BYkQf9V^A0+n zoEvQFCRPiO{~5T~fQstPtj3`FmVtdcNb?p}dv544@1S$^xxq!>4pwl{2RY__9wX?+ zV(>BVAf_M#`zcU4u^VzsJ?NPCn{fBplt53~}8lu;2`KSiWd$Wt(Oghrag7y}%tU)ZY5zJaD56BU zKsojXD=5lE|A4~$CgdpigP_2@#R>{V(KVnHcAFIxFrv<&bbF_s735D*u!HWhf?UeL zZVS?J4}35@yAa6K$E-hjpv40(=$Q8aQ2qw77}!`qZe<4_mi>%X9(2sR2}lJv^Mf)r zABbRJpAIUV-myA>6hy%l$T2b0L(Y)p14k_Q;5v@4tZ5)+g&<`RVbHly92{&QquAeq zY7k)vyA%}R5@0s?(D%2X!;HY?ffgI6JYay72ijm2jF9p`hpm$rbmqGssIJpxs|Oj% z%niC-mqU-OmKRh>%?35F^uZif26in_o-$yY3OX>4g~No+oR5Kly9<Vg6)6>NiOIH(j$V*>?& z=zLIAq_crM!N9HwN_81*D?si69r`W@ItXeu$jEGPI$_`z07Y&N8%TnMfsF-ZC;LB; zu3WZX{0t1>GvCVuVEMX$4U|?zdu8hx7&r>Sp##Z~W#IHB3c9R;qnxb)>Ckr-(4p__ zw?OT%DmDWF1_t(-po<{t+4=;ad2_h{0|Os8+kmqlh|9pn0%w+aA!F_1tek(Y1i>kRa%^LeLQr91Gb_fR3i; z{ta^75;o8tBMI&lkTaICT@eHw`p(8u0lMpkWeu1F?Kfm&0ku)sSfc7dcUiE2YCblW zCeTUxEMkHT4D7c+R<2;P0I?H64%-h-rtH0-g7_qu4LKnKNfFt8s5b$4#F{R7$O0E*TJY>7e)47}B# zqu#->`3w}6AX6bFD$51X@$SZ;z-5^x$-uzr0cIWqon9XbW`b@-;7kKCxdb>X7=1y< zx5)}KFmP5ff&>}3cS|rZaB^0Gd5qlt)9-cJIxw!7F5hjdR=)+Luo*1H$87*Q=Dh{X z;b&ma1=-fhxLgR-)ddwV93bQJK^j24dqxKKiJ}Y)oRZ+CF8dK71_n+~=5}EQ1~E{X zI2&||J=jAa0(|uQ70`L>i$INzOpyN=gl@~kGca&vffTR^ae|KS&IYOB5V{X)^XGuX zH5kCQg6c(Z-&c--MGz#J3o;*c^t%n{==ZH4p$3SdEuh-C5yWN^DxI#}V{2XS13H|v z9V8?GJ^CGVVF2vt_c=nKqu(n)g>^Tmlo1g+C(FRV)dTXasE``yJnCK$TTJLQs3+Lx z2R{1U3UttRKPcMdgkDNAFmO!(`C4A+5vX}M5p>9ff=~^}DU;uW&Z~70k^&vyJ_Y1l zMG)bZ7zvX@b4y$k~b*BTI; zT_|$;*FT-6&VILmT=IJ2}==Zh)N%1&SsGH zptIcrKz1$!RVzC{vBev~;U5tT&{R${~h=a|8ob5glbR?hv$bNaSC<8ZW)en~nBPecJxaWZm zSXXBRsk*~02nqoW#_19a3=g<_L3%V9LE-yE${BQ$xeg;Jqp~ncfp19DWd!G6MyZFO zpweTk2XT2ArHnx-K%a501OtNrqtr7{)ER+o7GabEO>uG=Ge(Pn4}O;cC3jOs(D0T7 zqm(+x*Jg}`Vhju_j8bMG3oRLWAP2vL&Y|bB275P!Q7ROa-R;1okehrMbwPugt)R+Z7u?$b4Xc9gR00=5&~xB9LFd4Onh@Onp!CEb zR0|qt2>`K~gh0bz+<_oAix6n15qA(My|4*w2OSqF5)A4i@(6)OiMT`VF)}dl%Pg60 zKhajwY#->j*$9w69!8m&pu;R9LH6)5%FG3w(HaFx#A=K(e4q|rG>D_lD8nN>y>Fte zgsBmzSsV{aby|!vfuQp=(?Ke<8D(@pCxhmKI690npkWs70?;UnE~Ct;>9;4^s?|RO zb)iZ?3alArR6rvfrEE+L3^t6A!bM&RIxNNn4ghurmSm7WDnUU4J_a6i^0bg6=tRv{ z5R*ZO9pv=3DWEZ1Ay9*ay91O|1%$dl`no_VRYVAMmyR{~0^dq8c?{%^(Eo%W~fYB{voZmTw^2Z*7%k;07Q4 zt_C{#earN}lWoPluYp49F=$kiLkLu2aX$fBULeE)O2*GY>_P?>(3OweFCT*9(HPX0 z`v^)S;A7uGclrta1Dy!^W%~5^DYmk9psJVq4=C-b3AKR&=P!t@Av773p8kQ@T0-|g z>H9y3t;4+&6g>=#AdVjQ%jvtO*ebAt_BEPtH%@;z#a6N&bg}?954e!C;RYQ8$IS~a z{v5c^fr5Y!EaSqx5_BdnKUl_t+XfWD0$>>*?kbQg1i__W0CyQE@#l8ozE7#RNWNi6|o zDk(Uy2jt3^{Nq$j1*kZWmI*^Ycr&fGP|{ za3LtbF9oXNxwXJNLH>FvYf$y14dx2*OR<9DQU`2|Fh2tu3n=C}Krt#Q2hE=H4D1>p z{~Ivc$S^RlZvwf{krC8W=K`GpzZm41b)b~G1RN#|+@L+`+)Ke67H%m}f>;LTaPSlq z=T0x5W~)-~0xBBTF@p38a&HE4)`L0fkfLET%x+NzcJNWj8yO8jH6G|Nc+l-&u*2ZN zJqYf6P$+F@1aSnoLA4WW81u9f7fjRu#pmLG>3Rsx{_riKmQo0G265|GSFuCtCf<`68x!pld zxyJ|!I|&AMF3>pW1IBK71_oKsHAD>D&lsH*7#IXJL2H@?;y^pb1sEk67?>E?L07zR zzXqELIV#=`bi%SHDEED01hE;oEkW`3nbAcFd^^=2P{x6s6~73SrM`j#gois8HTH|O$KUmZvh45 zAF#tLxwAmEDxWNPqQr_Dv{RN_06bA*!`%c*?t)C5Qq$#T+R8DpiB7khX)D3_e|q># zTQ$a#>2))0CF?;Wq1@(7pdxeuc)*m~f(cZFF60IcB5_-SXMz@SUjoIs6_~S_`xMBd z_FyZQa5I38dUgQMek=n|7;!s-CybVJyMgR?0_$19eHIkq?qJSJ?i5fC_F{5YV5mnN z7Y|A#Yox+JLF&f@YP;$%N__>@Z((4=O&Fy%f`Sn;yJZS0)IphrjRn*q1kW~suKt4- z?d)x!;E!SQ2en^9xzm~Uf#MD{h|HbIv>((C^%Fq?tbst*F?>wiqU*}%uei-CCmnSQE)kBhGdMK}xde>DaM9~P+%plrj+%&!hUF5ViH zX4t@8-9Ic+_d&tL4(9!3kxB=d!o$1@v;dt|>M5x96k-OoDJ$5d)`6-x5%8>32#1t& zJt#UvnL#C47>5*S+>cufEE&fk1sdz)76%)ez#(M_Dmo;XLB07T4k^%G_S`aHl|>v< z4j?&MFt3C|3e z&0dL1fiHw{1zYi2Tne1J-IzhC`;E91=y*r650M zZxByPiXWuXpBYquzEG9|omI;nz#I)ZME;os0|R#u*uoFWQrRHK1T%w5z;DV@pFue~ z6l}v!WvOgXK^_+d=KfNa0!=t_hl6>)m8FV7F&Y65i$BUzQ$c|r3FiG(mU;*(Nu!uS zT`vX|DN9gPM1$pcRHSM_Q4s^?@v2CbPk%7aR-`^r9eiv&2dL2wO4`s8hK(f}G%y9q zj-W&h73JttW?%rN4;Wuxoq+*_!F*7e#R{5mV*wRa9H8P06ewUhb_NcRASfW9d^Q$g zUIqq#4p3*QP#v1nFykCPEd~Zd4m6-HRH=wmdU-nYnBP8(z(NC)UxNX9v4+6)YO z-~_M&JT{=t1kUnv_aa*2)M8ud`U7ysfP4pVp~ym za0oh?PJg@DR>`jcbjp|u$ZdOB7#Iw#LF>xk=dv4J0IghNU|=xUVPH_%13FEw6;zD> z2d!FD*I{5_0H-$4GBi+XtJ9g@xY%5DdeIVFWl2z&Ptt+Mj0WiJY*5p!*wm^qWj7AI^ zplxs<3DEXiO~xo$CWwq7gF0yS4>)o_2f>0Ix?gYl#l_}g(|0ekmDU7B&Skh^3>r}k z3=AS#3=Gc^Vp^a}10GNRzsy#&9^@2oNi57@4063vw-^Hh;|0(ah9GZ&$~DG0>H4q~ zeF5aHQjoW{gU;Z&1X8!2m4QL+1SsiW2KkaPN(*!h0mvPotPeUr*krx{0|R3WxDyI8 z^#}tfpVS*LFw{eGVhlJZg09enl<0BbT+YVEz@S)B!N3>~?gfDEm{b7WV#t^PHVJf_ zum;SkEBdhTV*nS%?~NH4)a_x(7_|Qv6jCAvU{#EUn&8vm85pKdSZvNVU1Ei;Fh4j* zr!hcES8oGIdiP&pE6fd&(b@x+0gL8=3Q5G8@lpYx8JU3)u z(3=H1J?;$HCoOESGUhy(f0B)X!IT*!e}NHHA2Lr|Pzz2OAdL`XjX)h*N@~!02ecmr?0-;kn`sR8|MZ6|Z6$+1 zsYN#nRK_sE>tE0Tw~TW@drTqm%E$ytFS6_~-!p?%+Oab*sDp}kkiii8X>4 zp18_ZxE_>x3XLFs0r>*7Djihe!%~#)VNmY#1of>z35o%dPEQ-bigr)1#WCy*45r{R z(Hm?rmZYg$4{9;QfjS>xgFyQ-8Ryh18N*D91DiCBoq<6I)SqLF1KY_M3^6wWW-cfn zgB%TWpqZE=_?TZ)V+IDc|6pM3!pOj2wj4CUa+1jxBo4Nb0W5BA3hLYEFoT*v7N?i!ewtaLnNX zg*n)T9B26~){8MPfG}_H^o_F4_R|yY`EqU#S!3%Y&y$!^7N3$>k{F+pnl~MEdhhgm zWj4IqkDRvs&ICKc*LAwVgDipV`sZye6&MYtH`@9Nvsjp#nonQoVJ*&VYHSHUm3MN$ zU%BmdA8aqO$ReM+Yif#oVy>B?;r5)bwmCAAZJ_&gpnKLPBe6G5|0rl@tqL0dXM{?# zgU-H%vPF^DTGIoC?8H@Fk%T~38N;;IAc=QQ?-jBWmt2A*v;m2|XZl_tJ9kMT(3!YU zi{z2my3=Ka?UZ>zDH3LQ=JdZI{Nk!TNUCNcv6msSw@mL8wo|Tuj3o2{iTw|W4O%G* zvjKb>FVr#Gpei29Hb-JRBe4UJ*x;jjq3SCk;?wtA#<7O3g>b+r<2n+X4U{9H8q|^4 zfk^CFBz7heyL5W1h@Jj)jlH5gy!(*E&rClnVyDdbd%CS{f;gktbWTybc*eHrZ&z80 zGcKIoC~7Azc^H&`q1IkNV&9v-QPfVEmlt%3E>v1-dhCN};A<#GsEVRIf@JE+G@k=W5l z>>|)bh%n7{ND^Js=Zf1|GhUv~D3B%2_-^_~aXV#6Sx_q)YN8er+hV$|gq?COsCCQy^w^$ zkl3KRCt*t4k;EqIDrMJfW(;aFK^^IU#P&mC7a*}~!0hQ<4Z&uNPp3yV1k1QU zb%U-{gjot249ny;=DCTLLJjDrih5wFF+DngT&r}#6E(= zzJSEOgT#J;#QuWBW&oXn3-tjH5*xJ2f>9BAR)GqVgaH!U7l|E##0HHc!Mr>TNqi9! zdmR#c7ZUpz68n-UXs;^Nb@z}Yz96xALEQ_e8U-Y_4ieh}iS2^K4n$(dAhFY7Y|tXO zA{YmBR>AbYvUbXntC56uAhFL(x0D0dF0pcU;=E#@!6K;3l%_Yz*;&`;APH3>vD=Z@ zQ<2zvGtMIwn%JmBz7bc zI~|D)S|jSG<2;G=?}j@W@Deguhq z0f`N|X%iNJFObB)Ah8*w5n;(AJ^hrTU7TSFk{I};U#Oj{k;L~Qu}@83_&ia({uPqY zHzYO_=yYAE5qwB&DI~T!659xg?S{k-LSn}uv9lm-$Z6GO5Dqx(nx^lq$`_w5p=@`c zJ_|G|0Chw;61x?NJsF7&x}qEwcI%PE_ad=RBe8EHv7aNcze3oM4e?T-gL$EjP(xx{ zBe6Y@*rC&VRqT`{JCTII=l?>D*fRa3ik&qt7w8CIsF3({K~+0z$y6kvA|!Uh^i);5 zY){ZF?l8}BDIgMn1QOd2iEWO=wnbvQOqW!%`^_5%x@i;Yfb8jt>UPKk^+li}+ zfX?rQ$|xbR4UpK;(@(0~S*tEV5&|Cw4Allc4j9TlJzZ17F1TI~bbc>X$Qp?qiNwxB zVpk)v`;pkQk=Xl?*r$=$H<8%SA#6w{1>IK*3qxkm*}PB(2_muOk=VLOY-=R8ClWgx ziJgkXE=FQEsz6);PT~DX5_6H*tEX?=pdns=97*Ug68j?(`#%yJbk#Y`Ptu^1c%gpM zL}HsGv0aha!AR^x2pbYm`4A4+y|qZ}ZY1_hB=&M7_EseJVI=lNB=&tI_FE+OZ}0)g zP#~SV;IIiN_+bvys@9NbGhP8#K5#6~+Nw^@YUVh{WEH z#6F9}zKz5#0v+kAIK5BXPP`tpTa$r-p;sMoXzvWLG&qbI7K7N(LyJ~`*ie6O2C<>y zhmhD8kl5EiY^eGNAU5=*+9x2ppzQkhAPK0VpCC5WP|yv}ut4Jg9moq6=LNB$>cv59 zsJIFeTNA{Fsxe1mJA&9y^==?GtT7n?;y@+9M-xL`7Y7oDvP(d0=pnzL%kmhZ>^3Cv z9uOOG6$Q|lx=^+@NE{j+ zmLN7%+)E2|@D)@7d=fD9bm2&lW+*!aqyefXAH;@6QwfL-6|V=eq2j$r?8zWDRLwjP zn;Vj-7lF)&u;s;68i@d`!9&C2tD|a9dt-8R09u)4Ydq(=mTg07bw=GLE_L5k_R0r%)`I{n%&a? zi9^*Jf!I)UEI@3idPgL7IEW3+DG55DgRh{ROeBdS5F2_2oi^?0iTx(4HW|3I-oOZp=!)PY^cwyL2RhFD~Jsh_X4q@;^81R)SL_u8!BE5VuNOnK)JLW zWEqG9y7?X?0aersVnYp`1Y$$Q=YrT!@ij>7jUYBu4fw!asG5Tyaj5xMk=Xb2L8T;A z;yIGUUl1D_)S#1iVHFZT=!{yZxG0DX)hma@HUY7rYHX3%Zb)n&5F4VGogoy=nXZ@X zC|3_Yi5IH50VEFfO*@DU={YfUgAUV$vZsN>p=uU_*iauY1F@mv8$oQS_%;w5Dt-)! zeF4N4X8>&)Vqmxm;y^993AGF~nfMwc4mIclhz(W44?33?$~Kt3*2GS{J_kvt6N$YV ziM<7heGJ5g`Wt*iE|h%(N&F#*4O;ENz`*bp#D@Cg2Z#+l$ryA*uCNF+Q?Y|ihJ`8; z0mW905iY2T1epnCKLd$F z)qDi8p=KI>196}dETA)9p===#8>(3u#D$JMsEFBvqwI z>`Ekd0}{IhiQS3B?nPoxMPkoHVlO~qFM+T@1qB1cN(cvBIIcxvZ$)D7L}DLAVjo3f zpG9JWt`~=8q8mu!caYdmjFGx?FOVcYAhEw}ziVz6ufmux-8RO~pD|~8FNi9ceiuYF zOxKOI^JnatUJIi3Og{^v7EG6ov-4+CnJ_&s&d!g?V8Zl$adv);XQuPU+kwssiv>}8 zrmqE2C#L_6w>!>wW%|(syK=^q>9&b>pmV@_LDZM&cR`fRbloI7f5s=%Ye7`c^s^vp z%5>ReJJ8`?xge@!`d$$AWjb$)oj>D*>9HVc%k;G=cE=fSOfOBf(`NiVePODdGV6y$ z3=9_2Po~-_GfGc?n`)=d8sW;oaACUPH&Nl~I%#$SOd98=+ojp5v1<4-Ff>3;&Zvfnfqf_zXyR&-A+>VGBP72BqmApYaP%mr1u1V6wS4T`%2EjWsHQ zfx%;XWV)R)2~U@cPl|INYrB#p1vpDPJmUkih&^mVqiq8lmHXMtLfj;?bH}+ zr^{y8sq@Zx#lX!^ znZ7r}P78Jr7o(n{1hb)$(ewp3#WlAZX4+W`)_YnpFo0GwF)*+&PE%rF;3*VjU{Hac zA_`7{pkuFC*!OCJPSj#QB8oVJs}UpwJA>;wXwRW5=oBKMaF7m0j=h{99jvZe3=Av> zI2ah1#6SzCSe!sBtRQD_`6w{NAcFUh)U|`?`Eiq(ZW7!Wn+{qVo5|;>QUY;d!x@WbW0uN{xDfDcvlYu)^+D?~ASZ?~;YC9=Y zE>#8w78}N8phep3j0_ChK*#QYwzu&!aQVxDPvQc}aY;e~1I$jGZc}6D%;-41p~g;` zarN{iHFj~9;8Pz3jX@&>g3q-W7?=dPco-O%1@o0b2bO`Z-(zK9(GUln#MQ~fz#zoN z=5&jRfkF7)bn99>nfiQr1_m~lqo6aos^u9N*wyQp7#Kw6F*7hIuw%aI!k~*o+4Vte7GXiqL16}@ltK-(sbKx_eF0X_x>c4N>= zIuYR>1qKFo6A)WM7_F$n*aWnf^3oZ2NE3vz(H5a?tU29|?b3=HfJ6F`S{se!g{ zcY(|n0B_9TG>l_mU=Yj#rAon#S_~-+jDnwqK%w@O1r%za^qpRW3x8M`7&vc(G91gr=~?x5QaqgU z3=Eu;KoQ7tZTf_II~AF1(3U_0rgNZ`pM371v&js>9A*Zt=IIye?L-*2PJdc&XQlCp zn}LDTmI-7BBVQB9K07dniEjmH>ySMY=*nznz8lls8|>8TGZYyZI0L{6cojIqn4W>o zwTjbXVBidA0{M)AZ@L--17`$N04M|Sfn5;^wwQx&5@=I=6j(1e-+Lwo2F_?OhllSF z$oVl~4lmyg83qQ&@q!}1E&u z(^(ts)asvzFfeeYf(?@8O9c5W4a||_lLQ5RI+!ERzzs@^-`E%!ctH7%k%4OhCj$d# zCKC_nsICmoe5NRN1_r)spg1pJ0;yx*d&0rMz*z*gT7mC_7y|=m8Q8;0e4w?QoaIcJ zETFT*`07BeuK?SV%J&jvY$ceJ#=r$yO~_fp#Kg|Pz{|whzy#X+%NGPPs*wqlHW~Op zM+b5?fz>lIaDkS~ayB!ifljtE)L>xXT+FlxbTGyyb_NDcFab(G3~VeQ7xHp&o?)tg z33B&0K?VlSvtUyg_&P!EJ_qJ7LgMB;ByJeE?6?>hI4>~m0J(>g^FEU?=uj%KdmcdD z12*X)R5LhU9)aV9i7%Crfr0Ze*d%5KE*?;1K4JP=4|1vm$f;b+pajKL#>c?G$;}K( z8N3pl;>@7cub}(Z88{`F?Lospe4t@KPD$n*P)^_z2OaMw#rz7C<@lC>mZ(cJ3o$V; z@bJ9=ab%c59v0vOEfD0C1Dh(s_aBrDn8~L2U#Zr2#gI17egW*eEUrt{tE(s?B@?WD+x{88hgh9*9ZiP?JJHsm%iHQ${`~ zQ3i&3PAf2viGk}rNVhe!5a=8(9!@*vUeH-Rpu&&S9;zGca|ft97OF5Xa5{oDbMS$K z-3iR$WZ=>VGvKz4xQkrPfZaLoi2D;BJWU^*X6muj^G9ZCkWlRCZ09VY{q2Pic+unKV3GcfRSayGLrg`3-gY;G&ExoybiwnNNi;PM8= zKnH6&Hv4(M2CgtrWweA9RG)Dj00sOyNDQ)bZe;xoH+2(h0LcFge7hAG7&tex9_C?S zU}NA~4AQ)X^*qQKik#b7L6@OJ%FrFG;4+jynSpaB_-rsn{vrm>U0|jl16Kg3irLNj zAEeQXb02Fa=vXUoTG@~6{sYMFuRjR!00S3jp8)3}R?v0pyxyG0SU1CUA4k@G0$KM- zh-QfEPJvzL#lW>0lzvaMmV%DfV&^=^`WSA~d8kQSK&kx#D5gP&l5zEca`#2n{k#ke zq7j^zSqu3X7{u&Av2g{Q;Kjl~VR#jsNX6!8GB9vn11B@FouKOLIyj=lGC@_s4RDl; z-2=4@Zi0ha>;fooZ-GNm40P)_=WTGnh(&?Y?VWnCKgGZfx(jwG1J^H5INoD@4?1Gv zBFNOote|WNE(Yd;(%S=2{syra*jPYr<;n&LJY!uCI-TnXNCi0GgEBKGh+yCX-9XCu zj`ada!7I1|GbV<522N0Wj}siRT$?~8*jLtXAZ3go|3ieuK>HUt*g!^c$$;t)VF(+v z8H!T^%;sg|)MTsWXMmOmT5O>5fB{k-XoFQSLdpXjHc&Hxi4RoGa_X|xgA8TndjKj@ z_1Jhp&3!)5v^b|en8V7z#RSSz25hSQ3=F(1oF;6?L6&rYa5=#Q&5@b1m;LHa7_XQk2Bk4khv0^Zfwz@!>MFI zxyYRjRI)Je9R{U053n695R*K?nnf7ux!6F}t{0n@00RTB2&XR_=vI4(qx`@c82CYl zl5zTj-5~(6IsmL&2x3$qm?O-YK57h!NBz$6q*^}L#lW=IJ4N+fsTl}2{JMpoK6_{3_y{a1C{{ong!X( zr3*@{xolma1HCvn^V!&hVEMWLoL0qlf~I>p3&EiS$&h8>^d$z$dz|HLCzu%+B(hU0 z88|E1Ks&e@xITh%S{2&?(8)U6KnFq9vw_Z02Ioz4P&x!>8*ugmaT(ZHK$h|vaJI66 zPAulnEMnkng9ITsJnK2z!8`%}l#FZ!&JHj~fq|;tQ2;9AYbz`)thRtY)-=RYXsrm%s|J>WP5au6tkae`P3Y%CyCcojHj zvsr=8rkV&kl#Fu@n8Uz#7*uu7WdkilWZ}yL6;AWm+(75U@PQ7O;GECqBMfRKo(ILm z0=6JwP!2Hwg~md*2w?^W5k5;$bSzKL!?0k^J_JfltS3BsOnv-BQFBj)k zwwuBX4E&%&$vCfpQ#AvBZe|_>=XEfLi4Szs2ImbhhlNi7D5c$EYpMtN zkb%nDmk`W}xz$XSe*QW~1VdOhE{dJ$61Ebk=oqjvDdREY3 zT+Lu9K0eTr46YV1ho6C~24q<)BY2ZL$Q(0Kcn3`q+=b^7VGa{zU=VBrb$ta}Koj+X zTNObaWv=zo3=CY7;3hLyKFBGa%z2^=4C0`owh7c)0*6xtxJellnJ;vM zyIxtGfk7Cw$e+6bV&-Mg4&z1;n@M=1CIbU^lkD_>33jISU)2~GxZ6Pz0#b=-1q|FB zptBN%q>4f8&P)*o24UfepmP|yK}DE|untIl56E^=VbE+kcQ1%7CM*fs7TpIrK3rTl z3bX~j-$R6fK~DGwXlL~Vkl*Ene}i@_Pi$poU{DY~4RX+AcFAY z4BA~j9b{;|@Mm=f2JRUkc7w1IXyfxtke6G8pu=Le5wm8lUyH3@o5izquD&1C4S01zEDh6Lf4~ zB&ezd*ZClVfu$1U!DT5RsS=PBsGA6G6EFzbaIbt03UKh&npL21Vi0BqZ46%xD(M-8 z>p&5@2E=9;o(_u8wIC<*3Kz36)H86e0|h>xusmqj_j-^y0>Z8u3=G^G-ik9Yh)5MM zaBl>;Kti|_v^jbc$fuyA(dkIo+`B+*7Gco38g1^~APyS?%VN+b`@R1_r&(g)a$ofCoD`A93*cfZ~q>%;5x` zsRbH>v*L2nswVz6tCM z(_JRp3Dxfd9RUbB_l{c}Y`XLvMs7LA3MmE#zHOj*mj{b7@PTGkxm6fJ(apj)6BH%t zU{!bc{(#~{gRxGEf#Crkc!$3xBPeK}$OwQElnx^(d$Tagc!Huuml4!H;b4?u1?{5O zW2^^pc^G93L1{vtu|*1WDw+%*C|?lsPcSx-jziv44;TEvFKmEyOcFFk#}f!j zb}Yi6+thi2K(Wgvd~CYkR6FrZ2GFQ|7)Y9fQO=T;fq^F+#NlF;lK~yz5dq@xFv?xk zWMJTl1R2c7D0d1pa2*9orfQ6G>Y(A!Xb?x8Q4W-{cw#{bOM_8Ph?#+bCk`Z|$tY(& z{oGVLN$E>s3=BNEATb?AInW3WPXTBEN0(7fdOFiIJ2l3*>6+8*K2fFxps4}mxnK@v5>t)L@t zCxgTrgcpM}OaX~65Z(r2PXmcB5oQHBXgWyzi11Ao1_qv4An_Bzpd$l#W`o3E2p^GS zVBnbt8nAmK3_9tIXFf>$i*ORiu0?If& zcvgaB6d2_us4y__fXg}+M!D0VvryM}F)}b{G0K5jWjq@}tve$|x#x-u3_P1aorxqy zInYP}&puF3sEAPxG@!tLuhD7)JfqUI3?bE^0bsxvU~ zNHBhoXJDw2DFBU`N-}<71s#MY;}5ELr5HiO&FuU#o2H+gX(wI31msOQu>1M=Wn@8) zft26;{4(jX3=BMq;37_dUj|gC^Jsy2g8VX`pd6_U<_Yo3sDe_I4%ig%k!PS3z|9M~ zW*L-CL4)h^3|wg-!wndfL5Fw6g52WBcmy=t!t21Zn6XQNfq}0Zlw_BHz0bfG4JyZ$ zf;lXF&eQv6*%{ZDfKtgiuwp?zF+K(cp7mgkI;3SW3uc=r1J^H31_qvujG&d@ycs-O z8PgP@y+fXDjG&~?z^4bYU^|#2zz4byf@cSqqrj&K^7t+=$AE7-$Wgn&903P#=bL9Q zBdGHoz;|bQ;A}g|R8ZfZ=Kwe?V!(Z0o`YacEZ+%GY#ah};`rh~>Ep0^w1qKG*2A-3Q{}dS*_*P9nKif{y^bN>mXBa`v9CmPz zmgg)uA#(6ZiZC$nTm+lW$9EA_cw7Q=`1zEk%g(WrtOxZ(dG0cThA+hVo=7q<@Z19j ziUb3fA~ypA&jZFHMbHudpoo19)+%km$n%krRfU0pj{_8%pTKMeKG2vM&u2z%6$Sd=PTGFJbY~+UwvZ)ts58MV+D0$c)o*EsSF>u7Wx6^$bnlKJU_wS zPyo*q@%&;0m2PT$ZlF~1n{gH+1A``?6R58E19q4tp9v_V@PTJutoXt~P7nakyx8zf z0J&d~2~;=L@`0-+A@Ib7)>J-F1DQtw%$vps+Bd?Z2%gB9&L<2itkl4q8GQQFsiFN3KaQP zV9sK`PoO++4|ebpz9m`=3_K2C)0TnfuXr56^HN^>a#9(1e3?K=V~q^xOfnunCQ#c`hfziplo!LmhMO?ToC8GyWU>u> zv>7Oiu(9xfItHM!SrHVDp!~_iz;y^zdc`n_DKRkchVs~?Gqr+Z9yAuslgYFUbUFqf z=zvn5Y_NkI`Hq0RlmoWNiBANSXmgnkfsQugQ=YzWo}HpUXlDRd0Vw-G=Dv81cxEv1 zt1>X~flf8$nF(ey@cjX)n8gI@Cd=^|gUp!?4kr!19#A1a7tGP(n?7A{zMW(}xENZ< zG*N|t!GLcmC`&B@yT_1$8)Sk!NCfI3(55b)#Y~|61H2qO%b5H@R-Xk;_bmsr8Th_| z;%f!i3!nj+r=YHN6sVY5$)v3cx{3r8QAfb?(kd!EpP4p*T59~sY3U3+U%=tRz}E>1 z!kkFWXn>9}lL_HsVBle4 z2Cc^SVUcMA;jqHZ*}l zMjupONHBwX@JSppVW5O716EnYA!7%UlLhliIAp3pJY{AE1qOx+4tdZqW<2`LS;C-W z%w+gMrLz$;XrOJ4xJjrm#F}iRF+_eJ`tCBIz4`&oiwA_^y-Cn((a&5cszE@pw_`l zahbEA)&XSh?3K6-ICZ*$^}QCC0Vhv4W>E5cBQ66v5r)T|8MK?@kGRZ>>30{}N!R}c z1*{j?fh-a-%Rtt8gMFh7&IhgI6?96$1DWmNy!+2 zRQfZ63e6YFGN3cqcmkM}G#MD)D9a?sGcfQ3F@xGcACzT^K`Awu8C24JQvP=`GL=FSM*Ft2!cW~8Z5`7A`=YCS}|ZAuZqkrkPWe5l>#a<>p1Ee7RCXI8gLKB0u&RVJj}wtbstokB{Ao!g2v`RiARWoS2A9cfkAj9D+2?s z6o|>dz8~Yw9Y&VQ`V5Hb!m@V3|e5t#*z(U zR%?UONTW6bgW@aj#eZcW(TQNu=^#;%4Qwo+EeGNowHX*d7`E7JJ4hasfY?|Tfpmdv zVq-Z3VuF;hv77}l?}E*G3{ra=v}BfzciIdLO5Z`dG(iV2G5CN_Tnf-( zU{H1kt!^y=_e(&B-GP=?FqVR5t(YbTsDc*zR9P@EsDT!=IqNVms53?}8Zc;hfvyu~ zjAEJ?z`&px1KKdf23o_za2s^&)11q?3?>X(U7*b`Y~UslsI9F9S{=d2#&}tmfdQml z6|@|-&4PhJ8+0%5L<2Rs)|U1A`9e)I=$; ztWndrMhpxlEV2v?;M0;B7(lmbGtL1m>o+Z6NM;mb0*x@%f(8?kK_MgrZj>DW z9j^pV-6Bk&TGa4{3 z7#^M;xXMnXKFWZBK?^j%!DtA!QJjf^K^wGE-oTQ9!NCBe7aDeq#tf>a3=H5f)&ZT% zW)1cY=$tzS2FoVUrdvO-5uh*xEiq!8V>}(S%Rde-Dgq9t`38uz5zC+f+Ij&>Z3YYs z#ucE0Ac~m4BT5Vm450l7jB{>)oCx+bM5dXEfx!&4ERwMVtdcR3!FVp{Se#DC>L~^W z2FUT5+owCOwiEFIE&pTe1cwk~uoY+lAY&KUNsJ*@U}L+Owu2Vvhnkmz4jJlU0u4YP zW@2Da1)W?A$`#t6$N^>8hUp7e+nI^FTQV?AF$9H86jL!jgN`Qy14GdCH>>Sb+dzcv*Y~M}aw#H5mQrLi& z6NB7-WctHfR$|jR*4ha}BtQqjfh2xIB<$DP33G#ds{^`*exe1q1TtR02=XTU95|CH zpc4@Ofc@tWcF%TWi2we;{Fgj^=~_E^NO=ZI^dKvi7*B6}RU$V1keeX}5jvK29K{b!b9U@!*nV)TL=3_3cMan5#A z1_rYSpi?y4jHH#HI(Vw-aJ5vt(eAX69;PW>5vSzGSQz7*s*md1`ShDnW~+8RytpFfizY1MDOy{27D5RjC8WJbnfShM(FD z4B(~)*!iIAwn5>|;Cu?SSpNi5pauLqKE)W&@W2nyHPa`VGN*6cWG7w^YV5mi=VD+0 zVV?KQZjoXP3?R(v}GB5~wGr0x| zFff2HrzNMWjT8d|2y?1)x*r#2U;tsaRWb|=Aj}u+*2KZU0K#TMif*857C~4@#T8VQ zgRt-?Mpq_Q1_lro=3#O(=3!s}VUZVZ{#pzS{?ltW+sW2*f|eigGcd4wyM`+;Fo3Xd zC6lWN2k3%11_ohXCf6{~uz&^wgRnA_D+g$c0cbMj4x?+I76StabAIG-ZIxnR0AbEZ z4mZ$QRUj;y=w>R(zyQKx`mXKr3=AMF9LMDPNREL4goR(SGrBgaGB7kwSJ+}FAOBpF zfdPbhb}+l%m0(~1VZm8Uu2;Dj7(keN52Gt+G!%q|Wtm-F`572Mn0qRtE9fFh5Efj_ z=U;lUOM-|dfX+Ql=2&mi2M zaMw;JUJ`US6(gwNWnf^q$;Q9{V}GB%)W+W0&;eA(L8X0>*wIMr0wi|r^vDN=%BqKu zgw7+e?;x>XO^>v-S7wx)UTbSF&S)~du)JQJ(P#QvTYGoOMH~p1tVd$+oz81#uPpfn zNeFaL9L&+|(_OC_=`*@aue7sQt}h0in+J7!0}{IriM<$!y&j3Z8;N}!iG3M~{Q!ym z28qoHYF%hCfX^+i4DqHFfTkr5`T-t{)xn9onC5huP^BcI${s% zKR+aP%=EqX_R5moNJ2A^*vqE>w6~9E6r1jNtVo>EaC)JGy*Oj=blW;ramKvq3mxp0 zrysasB%unrNeAYtBcL`f)T*0E>}S*e-Y^n3hQtO9uE3lKx+fIIW(75?pzaYwVuO#>gNkcH#32Xdm_j(< zSaL*S`y#O;k=Uuz1;bRuJ?oH!z~}8j%|41G{u+tR1nLJt)$k#)rKa~f*;`8{BMB8C zvFoNkbh20GU5g~NYdY_3Bk}1P&h`@1J#HIG@XCWuu7etFGClXUk+NzGl2A7idj=AF z+4P0Z_Tu$dk%S&0u|FWOg+Q%Fs15Q+Y|z{pEa07x#Ql)iQAq4GBsTa2b1eooaKP73 ze|tJkynZ2){8l9PDJ1qaBsRD;3w75!Byo07dl)J%jKt1EVmBkP!KaGD+_HT7Qy2T- z=`-|nd2Dq-Z5gOR*+}eiBz7|rdlM3S|MW&zdvVoUNJ7t$*rK4O5Y%X;>3d!6#SLwd zgglYhpg~4hFoRoAP;FV$S>5cL>%j-%L4|lh$IC(4(nxFXQnO)`>r zHxhd~5_>U(4eF>fFsz4gz_ED-iG6>1?0uv7=^Ym`d8R+OZ=|By4r(4lT{szuJs*j^ zdb;cbBk}1gmL>9po<|bDjl_PA#Qu!L{*T1w2K6eTc8MdgO{On=U?d(Ig(Osq#O_35 zgO9X>8nF;b9JIOz7Faux#E(wD_`Xow^9zy?JE$iFH3EES9h5DPB(9Cbwm@P#Pe1#i zP@EThUL90h%5+Chdu7Qiv+!W02TcNbK1VwjbEy~JJ@G7=lK!j(}A zH0sH~z)+1O(T>EPjKrRg#9ocW-j2iut>=Y#<~)-4Z6x+{B=%>S>3qKSarL127?{2c z(4ZC6gOiZhOOecyGUwYBC){--9gP~1RYqX#gGP$Og;z)%m!WS z12ae$NgTA^7$)wDBp!&wjzwZ;BC$)S2m0Bct`7u_PeARDLt^J3v8#~S9Z2kHNbDs@ z>`h4Q14!(1NbEZhHfZpTfq@ZpI3CmyywlhE+l%w+BMI3|zvyqTELnggRExx(J)Jke z-kR~_blU)X@#zTx_6CwZpn*xKfssh;^yw=D?6Xy$APId$V*f{Cb5FMnwExYk3hH@7 zO){G97-XN#xMljnAbWAu+ek7mk=Wmn*h;k=Ra1>@XyD5)!)=i9HF4y#R^54#I}mwg>EhzXVdro zNEBCPQbTlg1d!NrNNkphT!!jRZ0NbDjcb^{W-4~e}BiM<1feGG|x1&RF# z!iF4J@d3gCd+i?*n+LSc8{&HgDI~TA659-k?SjM(LSiQ%vGb7FHR_;~eV`U}AxVIb zpo5ApLlWPD#0DQb2UP<;b`HwEhot5W68jet8+@W1NIl5^VxR-oKpfCa5fa-7iS2;I z_CsRFAhENM*cC`@@Ck8H^QRz*FVbLOsAq&qSb~Q5q3mEJb^#K*8i@_M`Us|XGLraw zB=%|~_I4!pVFcTY;XH!Fa2tsY8rOhX@EJ+`KN6c8bj}&n(c;tBzBdwA1#OvyX|qO> zc1L0dPrv)#NIVoY-wIP&jwIcT#O_C8&qiV|M`CYAV(*`B_`yir_BxW#VfguKD0hFB%5{Ie*A7Tcz zpd3lO3B-nqw}aSFy%Uhw%Rp>)Xv=Gn)I}&>q5_>Tcdnqd<2VJxhN{ni>IDT}E=U}zw;aTV zs;>dDA?ni^z-PNb6-@z2@Pd;8!wir?Q1)VwI8@C#5F2XHUJx6q<{}dN783gxm_7Yn zw7ocJ%NNLSDSgB_cB-H=&Y(scfY?x@Z9r_OxI2gq8Wd+>VDJX%g|fpy;!rh-AU0HQ z8i);5laIu%Zvk?vS1 z)6aq23!2bjU|?7eQVM170!c&7I|^b$-FphehKhrZZ-dnXPe9_JnKcFmh8G}npzO~e zaj5!#AU4z-X3(@PRJ>jgi6f81) zL&f_*Y^Yt+VeILSKf`rESE7I%bPg;!z3OMUK1_%ebPAdH^ld-G^+6}Lf>fDl4vhjFA1`Wf#EpFVkr9(NDNNndq2||HgE*iy0t^fc_9hGr!cevsNF1st6vT!)A_~NYs!2v-SAy73A2%VfyOG$_ zL2RhrH6S)@Twyzi1G*55fq`K+$PrNXF_1Xa5m!NMsQ5i3_7@NvYVltrHk&CTRCqva zs9t>}wx6jF0|O&eA{R-b42fNj#O?vHLF+LBn|b)T@V`@n2$hgsQ3pY_J1Tcml*>CEa~xs*ibVikl1=4HZ%%@L#D-d&0%AkPSs60S7#M`1>>7|b)S-K+2Vs|33Crw}5o-JO#1W9Nu68jJm`!o{!3KIJ+68i^;4fVl45F0dO4_cRD!N4F4 zW%F7f3U4V8TM0UKs0`tNLWMyGiEWC+wg<7H7K9_Q^O4xqNbLIQifQ)Z_1#E9laScc zkl1sP*b9-^E0Nf1k=R?2*gKKf2a(uEA#8|)&q6q0|6N34-$Y{Ho&FHy-e*WcZ;{v^ zk=Q?w*ng1N%$A7oWk+K3Be8{%*wRRBc?f%YdAhw|y%vN6cCR54+Z2gygT!_~VtXL5 zeUR9}NbGPVc03Y08N!B~Wt$D*fE|&K#4bl-S0k~Tk=X6ib^jWPGftkKm|-toKOaeE z84`OH5_=;Odn*!qFB1D868j_)`z#XsDiZr9gbir{J%n(;-g%0|ev8EZh{XPh#QuxK zX0<{@GA9yS5Q!~{#Fn)J-Q@#GhYX5H5}HVCT_maI!t<_|rxZRWkh|h-#RwIK|$danJNZ5OreuK@jz0y5LlM ze=eEL3=B4)`GuAd3R@W%CV&i`zER9ye)@w_FP7;sGwf9u zH%xDwVeii=u#JHM)R(KB9w_cFKRqDQmSy^%8TKknGTWvr&9wJp(%3e=Xr{d%cRA#AnM0-&PDd117ssX zl*{y$i|n--eWzbtWUtJsbC!W&#q__6?3Ec;PFGxPug-eFpMl}i^hVHmunCLp1sJbP zF9Zp13T0q;Fdcks>jseUo#_Wb!jr;4r^kYXr!BD;U~=G{F0{m6jWsEpf#L4-jSH28 zrw1&t7hs$*J#mS>I-7ke0|T%2^u8tbN{l|!H!iVPXKbJT@o0tk^ba6a`=>K5wO40y zk(;iy)LxCTetO_idv(T?>6IX=efmNWWi$OGh?+C~<5GM0L9ZJhD@(AL8<|>6Ul{A6 z&csu!}s+A0g^ItV67RnQ1kA?P4jDIEp|24)UcX(JHDK1~;V zQ0zi^5XEjR4LZh^nT0(`iGcxnj4LxEN47Ep0|)4yV@{Ac3~VerLB_3?WME*19N@|- z#K6ET3R)#T{l;y3aUMrS1_tO!u9ee&-?mo}e*wBFRt>ajj>S^|T5Ca3tNf4Wjd(ZTmJND8%HHr)jET_E~85sEYO<#P+UYGIo^ow`w zr5UZJzrABGEy=46KGO9+NI{?!0|SdIBbe-!vwgLA_ka}Yf+l1TBjDdl}1jM%Bwwdm7-(J7oMuUNY!wMwi!wotwfWsQZ z4&Y7^VqoB~d&$bc5W+1k!N9;_4`N4fJA>Tr0%FH-HyblBaJYil3EUN;3=ACZAa)9O zgdqb1hZl&Q!3{b(mBSn4ryOoS0|o{TUl6;1`y%MHG5@`;tPBh#+_OP}5CBSQ6%1@F z^FRk{aB+%sJjfy7z3%ch$@u-{k@+WE(& z{+Nk@LEM0afkA;ww-|Jy1smwp8a)t`fjb;@w2(fC&BEOZvc>>(5DEu(JLrTQLtW6h z3*6eW3=CXGAhrPaQIL9LaYj(=?9pUk;4%TRCAhsA7#O%rc^E;l^A5EA+KiELdiq0q z!TJJa1_my3(7nA}JX|*0K@ON}%D}({IbfH2s~Q6X7vz9lZqSJfT=pPCI2c$Kn=vqO zIdrixFtA(&ooms>$jHDT$^y!^JcbeM3=CqRok9#^lR?dMvG?MjoG#1;O2Yq)7#LW@ zK$DuRVp$%bb5z8785tPZ#XtufbBNv4XJFtI1062TCAJ)tq{SjZ+fv0YgAUjgQ_^N& z;1gq3VqoAG%VuU^5D?2YW?&E$OPFr|$X=H5>h#!0_EPmspdFk|AQ!QK&KcurodP;8 zbw23OsX9>Shy`?S15eK?kmxRuC`c*iMMhB8Rse08n*@p#X^3y;GQQoPE~iFG?Eg1i&J#K6EIw#5kKon&1G1}?Ey zeFg?@F?-M%17h{c3=F(ti$G_lh_R`HypzWT@=l>7$UEPsTRgVcte4kiV2~7>qRPM^ zB?h{NMp~=}v^`HOo1K9{R_u!*1B0Acgfs(#yx3Au0uoD>Vqj1dTV~3@pd{uX!@!^{ z7N*U>pdz+Woq<7BER~mmK}{@Ij)6g4%#WXeK||~h=x%ngli~~vT4Iw-7#Ot04jVHt z=!mtbF)-+g@yN(9Fz7MxgKkXVdB+F}BOx{(eI{8>1_t3H)BilSmlBTwZO}Dh0xgl0 zVdF7n^5$e_9TF-G>gV!=Gl3EvgD~j&1)d0|m7o)ag^z&t1x7M~&c@{s zcA5V1iM^zg1ZV?b4A=->VbB#}Jh4omZ8ChqE0jTJkATe-5dN>jz`zp^wp~Iv8RV2i zrt6^7gN37~`#iN*s|PI);YkIXBP$GAcE^(j=Ewi2OoFbFa8{AJSNVPFsj z`|TgpZ(yVTLv>e!vJwL`D2kaF_#c7x(=sxH&bi|MU<5jqgBg_c_{~5YkGYvaX-G(d zN1S;p$WTy;$RojQ0cws4KQd%s;E`lL3OajOxRMRze<@~XQ2rGL4RG>EGiQSWQ8*W5 zsthy8j{?G=t;;-eU}HsuL9@0z^31bAhYvIGYl0HKB69!_1A`C`j|wyBuu);KjjG5t zszGf8o1_6Yi34O(Jp+#>*eEUre$XALJlf0$K}Iq2m@(V%GB7}lGKU(q3A9n!0_;^r zVbEbnJXT;169fNN&}Lw3W^P`vJM5T2=LA4B+e0;jeeM8t2k4p`9!F-zdeE`U!r+j0 z0vpB2!2iIMfq}=F*@KsXK}LedmH7rQ1A{EsOKxDJWZglD*&Q6XvM)e+-2?1xStU?d zc!J$63)*JK;{|pG1OIeTka{zN4g=@E1KOD!!2E%ifq~;UuL1)D=Wozd4I2x{8va`# zqlH;{`4||aKrw1M{o@OJWx<=ER3*y_T1^WUjt2<~Pro0P#U|JfigQ)gY?zilkerMO z13zdFC66BKEKqe0I*Alq>LUmSem2myUkldVFr7C+I)&@OO-g>yZZsZuR*)n3L0cJk zLLlr_Aiv~6*x<7~%E4?QE}kmZ5Pk+|4y$Gb6Sphg6Ta6RZKfqGU@A<0?K!2bwjM*}Np%YhIlPc!R0xVbIJ=C&f6+lFjz zJH%WD{$|j*DIKh!i?xL!c)D3N1z;}hftmy^TzgqTg)5uzXC(%PdY(R3P|?IG3~KH0 z^s|DBJ|E%DpyGc5*ogtcYM_$=CW0*q6n+6J&L)95LBf)t!wn{b9TqGMJ_le5m=nUl zzZq1DOl4ig&%hw$#WRC74epki$Zn~hh2$8X*$}rd@Gl01*Bn+;0R{%40G|1*8{oPZ zAnRU;ta%Ycv#>F!C|(Tl2m?Q8w-C<~)*=B02L2DAfL{lRL3W;vtZxJu>Y-7%32N*u zP(iqvb&mk(Fk*gF&?ypISWkeQp~$nH6|{v1Qf%#D1sBO8$qYO@S@}WxM@5Plcy@uA zf(-oSpvJ~-)*m2^UOf9)LFczYO5^=di@-5)fVCbG6+8za9$?^C0Qvq9tDztRgOE4R zG1fJLuy{O^d(7{_CJJ)?oz1>H=+a|0aZvR+CI3_LeMLCqlh6%@F)z@aF67nH(ov(|$`Ms^Y?;obrJ zQx@!=yI_|x@T-G#++%$KIsmp9R4hDZZ4!c(7SllIi{1n^%Rwv#HWrXu`6YN675fB{k-XoFQS zLdpXjHX-491_mbKBcN=g3zlLQ76F|lp~uDs>ahwJf+|9NFo%_ae;%lsGGLPvW?&Fv z;W1%5APhD2zHIa0j`9O*U=RTvM$F?6c837O>Hx52A&8>_!5m=*{!5^i zU=UjZ$Rr7#P&Uvd@DO)|LEHf`DV(hy%47gE+Q+&|$>Fzd+?)JR7J&5MNiSFQ^nt0|$Yu8K_=K2YZ5n|1zjd z%3w1TWnd8E;K^cJ4m#)*bYCe?HaMLy2(Jg7ZIc6*0G)jUvXj3bE$P84jL& zw*Mf9ycK4sXW%ISCss%XE(C`TBtMpc)0Zsh)Lx!)wnJbY~JFaGeki9oOl+p z1%gf&75)fv-4eENanLCuw?GMK8C$G4g{A+Hu{+wp^TnK`a`y+)K~}O=Omad#Klv8m5ob+fk6axiZRbMaK>T~0i9yZ za~;fK61D^-;TvEMi!kW!8lIbA4x8|0P!hexwiy&M4E$d}2mjn=+b_<*z+VqKyYK;< z5@@`}26SjLI2C|g%?ZkHkdl~XsuTl*53eyOR#;j=$GUicnV{2Rc|*ZW&~826G!Ror zfVYB?PZBhDDbK*bTM6#9G6?HxFfi~|fjNxApQdMjws&AGpT6d^y;{9B=#;f)uoRzg zygma1Zwr{i&%nP%lYxP^l`%sC6v!Y4v9W*(Cti?6W|9mH0?=-s2BEJV`x_Sn178kET!R5@D`+qiY^xjtOFQTykzA1ZTsQdYnWY&RxYvW!H-KEqzzsTs zmah@SX5zLtWnkcI0=b=qyOfWCfv*|F=HS*~XPAEBi@l<)i6H|6Upq*#01xOKV!nCWAt(o2N9%z%M`uLl$kqTE-f>wUEsm%Ir&ucjXqi*nq) zAoc{1_vN`KPLKO)FK+7&I(lmg$d!)V$)KZWrh|0XbN3rDF!0R)u^YIfK%*fuL4IuE zJ`6fLXO_DJ1H%UH&gq-J+AG(CdV75HL7ly8kkAm8hQ@&{1B)!kbqlshg6`Y`9l^6i z6SUXX5_AGT==cP1mCeB73pxO2nF~lN1SAFO@j;}xZ1`3l2ZiA=P#CTPd6R*AqcQ^n z-)c}9&B(osM~{JlZw-jU&K);B;hVi|JxGH9w~;Xe1K)g6$<1=opfm(>4$Br@1_r*(AnUm}__m9K4xCj5ozb%c6#NX_pnD;kb_xYvS$d^d>A#=!CfbmGw7`g@?^bvMu-Lq z7$?WT@Icrainq{9fxlPru1_d$mc=`wkl8b?XKLEsL z;sy=N@dtv~EZi>)85sD3KuLp*`>7@a1Aj26ufoF(8qneo0Sz4SD}fGT;tvC<=U`M? z$i~3H9}ePhF)D$U{_#hEI6RC>rKSuF{E;A=`LY?6@|hSI_@h8cSdCE$G=9z>4dSRX zDuEIke=I1iX)r2jfHcK{WHcF--it6W@W+E>v>27FSs57k(?K%Yj7pZWphNgU934g_ z&~OcZ0jMpn%cvAMJ@1#jT0N+_%wGahV9luH0UF^dEoWk2uwjH0HqYdtg$)z90A^=k zSp@QIB`Dw&D;W7(LP5tvAJb)E;BN&n8MtFj7#R55qCwL_+=oD+-2qCv0^BD-`no_V zSA_d6KLZ1QH%L6zg!>anLoZ0ef*X97MIT5af_nmJxO)OfJcip{nSp_SB1pW3yBy@% z$sq9t?hBxf>lBdq0`4~;_B4?A67JP;l;lZ)POT$RI=4(VBp`xU(dwAki@728V%sz2kPw< zF)D!u4fywi20V%xl|Z{r`450%4}9KmC+I@5Y()kJ5C(@j=)7UjFh0vakk=1?1YIw{ z!+&KiDCj}A_wio^Wpf5@(10fYO;DO-VPN?Wvi(+#BIw$n68<}Hr+5Fcm&vjR^%Wn3 zMrb*>!RhG<$le0(B2ESd{^uZeAp;BOY7zdID->Z<8~ks?l^7VrQb9MkiE)EA%!|F{ zXJBArVA&zfz`*|zlzJ3J`1wDBb{la=8!<5Oe~Fte_}5<64pblW{{ba*HSQ2lu>A$G zHMn1JGcfS~1F^NZ+YA^O`2U00I>PTk5y!v?;^+xGPtW;luTT%N+(h`ZJ_7?kDj0lW3`!BaZxtCB{wqVXtvmz23dpMlj7p$%K1Gg!f!~o4)b$r~;9txLI>b}h z2-GND0`@+G@D|W{!Arp$7GXgh_fEd zQHPWnGgY9Li!$)f1?9SpjN&Q`3_=MVR=EMnan=0!dSsxE7;*WuSmcqbq0ScSrj7veTY~Vl1_*WG)01ryrr@#r0 zK^QzDdzul{Kw=YK0*ab5U=BODOUr*2tc*h#w1t=dBG@KA;V@+e2L4N64!uW z{NES_G(debMo>_E2PZ-q@XQnc4=_g#JS4~e6YORM@XQncFGf&#s3zbctKn;9LX8AGO@XLOKc z%$WX?(Ls$#Txz-?lY>M(Xrz?ioC#D?E&vax@>?*0O3H=8D?v4zC3qTXk+41}Qmw$8 z#ln&xzuJRsT_Rj=#=yYu0G=#a2A=5RcLYy#EfLQ8P|*`OGRVG>niU=RxBPiJZY#U5yonLm@MO^$(qLHGiww8~Zj zyU0=aCy18=Hrh$p3zRBynWUK*7@UP;rh76wDEjMYFfj0oi!(6rSAtau8S&3x;sYHK zx&zdNm$@7n8gI@$I1y8gUp!?4kry^UQhy`3+8AEcTV5Q?4VFTL4$$8K=?JN ztX%|lh#>F=>iGg1mR6;Ih0-cyC#KFIe33Mfk@Hq|!2L9z>HiNJ!sLWac zb`@xhMGTa}BtXT`N+vB$SWlgQHPZ}D1_rT2&_)=s1)x3sV&S6FpsxBg70?{>C(wcS zVoCy_uKGkha98~-sMT`>Y_Ob)3jb%O=Q<1wBA|1L`M-celtFkSsFwK&mIzZg2x@fv zVwydDJ&S`<{U1;&`N!nK13H&jVIPS1pXs{}1A_;P0wX9jurUACVPNoKQQ!j=Tdd5y zx}bB36+nw~`Psld-9Ib}@}Rfi=1`YYez>;ws3fiFNq&V2n1P+DSAS)!8K|T5;4u!=a zIT^6ZA`XS?AURnuuY^NE1XL&}GlR%fPTjTmf`9G`}fxJsShV4snI0Ag7rzgPIXH#1-a(G@65Xcf=K9LG`8u znD;V)lLG6a8;tI1tzPASRo{1|ogPd&x<~S z`T{lw>H349(DwrSf<;0BbXOw3H#lfiBowkig{BYKFf|E?D$gAZAdrf z!7&;Nw&JI<0_b!a{xC4_m$CwAf|5TR%=@jZzy*q@2(YjJC@b`Xij+t&@2|4LVNhWj z#SH3lF{mi41(j>jU^yNYg=SEOjREs`RTP*(?dDjpN&yuGG0+X2{0YqQy5Pf$c|mP; zP-=#jIBYDSV|;k!K*Kq@&>ESEffuyq43s3Gs(5vE85lqq%x7d^W9b7A!GVe{UQlrc z3L~%_I|DCB5EL#@KASDe93ch6yd~I>=T<1hjK~F=R}O0W>PW zz`!^Mw7E|;d3q^_gS^-Q&{-@yxIisF(DEVB@*>7LCDT`NIA}+f=rJ%rj@{D$rD?{! zU}f(Z85lG`$9ysF;{v7FASMO|4OY;JI{UdmDRCbY=-|Ez2F3$ipq44r``8?+hHfh_{GP=O!CsH(c1Zg4SzH4AAff z?a6Ru0}V60WoBT|ie+G62oGjp&}NKcG}LCS2c7E)>cE25km#%e9X_xbG;|3)(N#;I zfkF2_Xgl~;RuEegG`O4`%mC5>%Jh2oK;gR(=4{Xb^Ne#83>g^oAAtSavns9=m$QR8n z7bBQmzF@oZu-YYO1PSwZJPyLbm^R&#y$15JCV*Xl7aFjg^w zz}^9!stfYY9;g*Pybi)jU_Zn$FfcrY_yH893~VfSj2IXsyOd=9F- zP9_Wts@kB9hUXcbru*?ZNcb-VZQZ{B4u~)83=FE^16D48`*fll3=A5eMKg?-z(MH9 z0n0g;8NoRRv~3Awkum7hT#%1AOr|H!&Jvq`n$JOj59A}`GYkw2AA=bf45$C(bC8ay z)B`1)Xr>}oP<8|L=S*LNPGwPJf~5z@$)qPtU{+}`fvkc!Lldkjo`Zn_?nh(Lfz%+Y zx0*oW%V$CsZ#{!1=tN+U12kh87#Mzma<@q$Xa!*?*a%RuSOz|glhKTUK{W-G<3qvC zwk{3^232s*hVUgg85mT-SsTI!U7D@&6?C>rIJnIOx^4kdnnZvd3eLQI;6MSLtqXEl z>hwZSO|j{w0uI6^poC!T!N9=48p6QPWC{ul@HxYp)eH;_AW6;n&|=jXbORSi`!$I6 zNdgY)8iFAV44_?I+Kf?5B@CdcUFXTf0t3N6s$YQ{Oc&5(i~C3$rTItX|k2Avo75FWyp zz$Lz~IV=@D2FtwQghlNWNQi;TUvPjyk}Cs)hB+iEe+W7V*MlPwv==}&gn>a5baSu< zh;f2}fdMpS&S3HZbjY7AGc5fifYwIL0d0VRBy?M5P@)HIU56xXTV~Ku@nbFq2363Z z{)~3apdlzNZkQt-z$T?|Lmes2=*SF8fQSSKI-M32FR!4k+$H27%nx=y$dw=&MGJ`g zKMFYrtC@r_Fj!iEBbw1bn=zWvkU#csI=sCM-d0H=`V#H zgk6zypy^f6(K_}lu&{$v(TgpierI%KLG?N;ueF2B)2#OaxdoJ%BR~vL`I`~~N`99> zMM^!(T~J6dFff4jy)n)K@zg3R7#JH_Ks6|6Y+WNxh=GBziRG~+1A`c-m}FxC4WqHK zfW}))OF=t`XTePY6^)E@Y(YoGf<`nw+?W9Ea%Y@lp#eH3Ck`wEIX3zh$QVmrkk1mpD}R{526>n;Fld6- zK!TDngZVup1_s7jur|;JXvR4fQ$UTjey|AWphw0z;noZcW}sztjQy;jrVe8eq@0-u zZnZ%CJc$()b~2##xS*h&%*w;az|Ek~%fO%os%<7tmltyox7Gz6sw&Y5q` zz@Q2?em@Jy_%vQvtRDo&x)!MW^=5jZn1ft>rVRswx+o}fGq8ddeKJqHPz!MkBiJ$O zpk=#^OknRaO$^a+1D$Ed4Cc<|WnfST*C8z6H9|}iLqSo-018hlP_@BS#2{@0&K^t? zLl`tcsR%6B3EF#D#9(2=z)-Kv7zMJD!3xxrWh!FuhG__8Fn$6$$=Hg4As#AL%)p@e z3RXCnHh_wtli6p9F{Ob-340L%dVM#=yXMh7~kK$rz$mAyL7= zcor123^9BR491|XSQA4S7;f84KOpWP!lnf}+WO=4{o)Sd()FNteGiTmkbR)d7mRaa zY(e%-|0wPtCkjsTpTG)0T@TP~4g(~bykCPtEft>N!$3}-a|f&!loe9J(Im#tz@QE` zBnzBx7^4s+6DT-A<JFxSv zNjS(!fKBEBE7$;9*$rAv$jHm~csh@ygEZ@$5C(?i={k}QQmmjly=l5PhzSy1I6X_! zL5lI?^j1j+4aNi0*GW1k)q|D~GrnX8^%xjKHQs|x*m=bcvb$1%fdP_$UxWFeV?H%N z+Z7n!fceJ-7#MV|KpFTgyDI1~aL^9#r6CLq{`QcR!coFt3<@8REApXY<fkE{$=m1*~fBHEo2lkZvAWecCpwfmh1d?fl zI6%d!u_FTm!-fzB24x4Zrx?u`z)ko)pdx1~GzDuefVB(OGB7ZJVoLJ@tbySw1X6+3UPs!`+FRwKb)E+HeK(F2yeX>s2zVI1Y(yVs3tOCV9>cK&A`BT8+@wi zIdEz?>d3&L3ho}=W&=4>U66r6Ehn*nf$=UINUlSWfk6Y@guKTFs#%u_GJwys275)z z5n{XvgE6QwKVZ+mU<(zhH)b$SVPIgm62ia`2o{TBDrR6Xu3}(d0I5p>i$#G7-e#!h zjX~KJ6zxqAIc6>a0S4nG3=9mQBsT{v7!9gaV<0l1?#}%X28OL*nJ6YugvT%%Fld1q zq4gk3KwTSSP|MSpiGjhw*_eTWu@UTdesE)OixUHbO#w&@R3dT-F)(O=7B4e4gS(=- zLa?H&1>C6xofZ!cs8(=5fi5-B0M{*TY@pcA7Ghw~1Z7EZ+aLmTX9y^BW;;P*%T(4u zGN#%I9A2RAlJP=lK=eVx7_AsIK?5|P`r7y-RBjbQj+c>v0hIn2ENnngSP4#+pq?Y+ z906wr2D8c2SIIiatAi5QPpB?a25@l$4G5+paDD(?6k>XB`UhDD5j7PT1_sr6pxR;* z2PgzUQ%$Pi+IA8LsIoN`W?)b~H(g84K?OVo$QTAm&{M$)T0;?37f#~<^<$fa85qFj zJh+(ys*7HQFfiWr!e9zMuul|T6@tRZzDa z6v-!CAdx&#-a$$kR07{YxKT3`mVs-b8CcjAqWZDCgD~sY5C#V0>A&S2q?rVqr%Na} zC<%Q99r1Pz9Kl)Obh>i7kAj1W(<{(8$Tbd7b85B-1A`ejtzH9{M2w-3`uYY3YJGhZ z98>DxWO|DuZu%w#2Q5fj5!Ai`Io)8oqN0P?G(`tth&bqi8jyH8NL(`wRPi;q!2%o- zN8t7>xG{JWbVUiM{CdQ|0IuTgG8n;X!PPf|g(c_|Qf*LHfDQ-wyCZcd;NuO7qj zwApc*C-m3`#$p;E_8!aRvsBGayqTe9$66^-z#} z7g(NYVt}y~0|Nud_qRQfe85!30Lpk10~oYGE&ht>`&Art>qEU57*s)KGVb97Ey=7A zXJ9Z(2F*L{0WZ8`4Ax-hWME+22lm1?(Ecz`JHJ{NY%*Ih1J{4h9T}zzJ0 z-Z00#1v?IOjksCz^mVEZij39MFQ_^w%1-uSU{GZNt!VrJ4m!{^-)3MdKXC1s&Zp*} z%9uReM9smFRn3!uVfpkdH3tPq6$`q21{Cl2ydm+vPR&7B3gqHX-eA8m6$>yJgF1vD zjp9DjZ>u@T8-WIC4SXQ-rJ&N6(S*TxBLf2iNTUl>0;CaC$AdIxPS;U)P+$e=YnmRY z?jYg>QVA;DiUk-LEUtqF%*4Utt0|!CVdhl$Ln<(Fc2GiSl4M{|l>@aM#lej*&;i97 z$EGh=cQ6$MHN)zq7#JXBn+*Go>2K8?BNP-XgBaD>LB$(rwUh=AsAAFp`^-m%fdO z1_rgvtZW8G3vf%ZOoo9$!xhxhv;ZrdA_FRHL6^{gj&;(U{#e67Qw3BY+xdZ`fqCMF zdIrtAAVr{IRald%)DIG?)jz^`H5rWmGB7ZJ`aoUCnn3qCgNp!1Xlv`l^n}@2;?pN- zI!Hp&2xz<-ltwuHA*P+zbddD`HR$F1kt_#|wM&MAdM!*044~ej=0DKrJE$69V}`U4 zeIV)?%@~XwL4oScz>q%OM9V>0eHG|(8D{Xge4wQyjB_sf!xB9+7br)H%Yt&`^g1nY zqFi0Tc`$yuf{ud{q-p}S89?DX zcY1)1g8?MWLBq))vD<-=FkhkrYZUK;7X3m&5Sd3huyGp&XassfWh8YSgjrQW85r`W z8|peJaD!r53pC6PD{%{T9i;1b1~D*z$Fvm~TtN5Vu$*8z6U4y4_8$x+L6PsGrvTdB z&-4T&4hk0r2C%r19_UsO(_cZbxfn@Md(`MCsQqLn5R4+q3rhd0!BD$&8C=~!W4(lA^&33~r#T&!58#nl5tBLe0rvygM7V;4g&)S^Gsv+;51-h0AZdSb`Ne2 z1_lu331;_LF2uk9!U73Q9xEjn7(iGcp2_2qJOcv=3nVgm3UM+pfUx^hQ3eJO7O?Xu zZCBVQS_`;)ym4N|-1r9K} zGk^wK%orF1U%D?~W?%qeAu&%wNd^WGc3%eCtg=j)fq~20qg{i60fhNyGJCv}VqgGa zz8FT2ubd1FAk4dx#eKgL0|N*P7`U^UFff3yfV}%`V+IBg7TE7GUz&jdg!w`lJ!H%n z7(kd`lEov(gn4MDj!XZyhx2R2sFjXAvAk9RuU3uH1j+`jy_!v#KOV?&1N3FjQ7w@-cL zV4Nb^4q9*q$~_DW3{#NUo2EbXbF{YojU>bY%KcEKVn}RlB(?<-+iiNJzoRl^+4Nd} zM{(YXNHTM$FZ6d5pZ>?3XmAN(2H}9&2}taIB=!a*_AMm# zGbHvWB=$eP>5l>(^(3u8wL8?2?nvy=>6$@~%91TeLKBhL^QWfTB=%b*HWO$> z2&!If`ov&IaY@jE4484DNYcsE4+c9b*H1zcnvcX@i^M*J#6FM2zKg{Egv9=b#0Cu! zz^oSoHGiP4Q-ZKTBTx(sdJqmcMy-(8Zbq4r)*~l6W~18+_R#RLwpl@h3>^ z-$I~)cR{I(fM`r!1=P)FtZzeqw{ zpq>oWa0w)~E)v@ciS3TW4n<(4O2-G-!B(^yc+Zlr?b9$vg2a7{Fp#CV#mrIc}>_%c=L1I5gVt+&I`UQ z7i!bX>4q_m*7e4qYh<884oGZ2Bz6oEI}3?jfy8b@VoyP0FG6B(Kw^WhxbcOaz#CAqv z`$O2E9K*m64dH-GjC3S+F%lbehzHEFZY1&PNbJQ(?Da@&&?-)tUeI<482hrq^s0Er zxO!{Q`WL9DJdoH$NbFW5_CzH1JS6r;B=%k;_DLl6RV4O92pbXz?;sp-Ah3c)8K4g0 zMq&#hu_ch$I!J8L&I6bSU68~Bkk~Ou>jRK#)>tGq=wv{c*_BA* z?MUpYNbJQ(Y|tK1nBM(J;%AZAw;^oksr8^?T4*5fOt(#P6zA1L60)A2nB=G|nU5q? zgT$USeQuJYHRFfrXOkSor+-LtG?4TLjW0kAj6hYGEk+U^Gjd` zwt^Q~fYSlP#OXIv9fRw?APF&oM)#oFqu%qdmCZm;45gLo&g<^4-@AHjhR8kWwns% zb!{XGOC&bZe z`ydkgJQDjZf?dz>8o>eIQVnw{J7|qF)MuhdY-J?2ArjjjiS3KTjz(f`(w2}ddy$!^M8hQ}K2G3nGFdPM$17%+Ti9^-g2C<>$JOHtw;;%t$ zPXQFB|hI$4@C?^Ia0iJMSU;u62gk6#VI^+k&t^%onTF?q&L#{vpUpfQ35(j+g3{=g0 zkQ%5XmVnq$@%11!SiGKrVGD=@mDmqrgC!Ukj)2%u@ykf;dmuJc&0`Q7>WKd!HdH+u z=wN%$@o1n!Jwdm@K-r=oai|(a5W5~KVF=!1 zs|>nW9mIyJ0pCsoVuM!bvV-OkK^z7K1_3a8`o3I8aa(9x1$5C2=;~rno(u#@LjwnV z=?pY*5<%in^;ux{bgf0!a?^f<3)Vx07lMUBhA=R!LSlojpMe?)x^f0~PtRFH1_oj1 zojo@|>Y-{LgV<1OLFWp<)PDqtL)Ei`CikI1Rxg0W0pCjlm5>LCLp5k1u?>;ft{^tl z;s6jEdP`7<5d(uTlpPNehpNc}v7wI32eEw_K!?9FFw}xLPz`NJY|zGNMyU8wkT}$F z>yX&nk=T1dY^eHUVD|KR`HtfCpm=0pVE71f7nJ=6Bn@>JJ7_%=)LlFvHdI^+#D=O@ zMq-p-jgU(!L zgo<|{iBATxq2e<@Y^eIhAU0Hd1&9sn#exnBgc-C0A^}csM?h?-z={^$H=ejgZ)$CZKE#bzKNZ0yHHJS}+5;o(9SW-+u#DlMhk@WmkdNP~X&p z*iiKyNbGqaHq@cZk=PqxY)~<_4a9+J-jBpS31UMny8>c^)-*9NFx&t+4$6KE5{IgJ z2Vz4V^clp4ivI(#q2kP-6&X-*K2uOL4k{sxBq0Z4L&cRrY^VnCr8-cHEkNQ>wjYQM z^<_8`I{}HE24X|i=Ofti49y4*1Nh<{sG_N0@##i?!nNwJgW2FD!SE4@%>8`6>3c_22_ zph^%Mv@#ZSQ3A*jP<98BIQTXls5t1PZCD!xG+_;6Zw0A`hUgx%>EDVS`RhSDdl(oP zPJ@hvvaf-ZL9GVgp#$~XGbHg(AU0Gz=nfr5C|eM8p$yatDI~Ts5?d3*hN`bOLgH8> zv0aeZejql~L6IOfXsrjRWHD!85QefdK;lp}#UM7+(G?&zRJ<9)hKhH9*uD(z;DDbD z;y@*4fY?wCi$QFt_zDmkD!v88hFZKA%${C1u|ioA>hafLA+X5|U%>3?yCzm>)hmH+ zfPreWLSj23v6GS5IY{g#5F2Vf_@*2vdkT{HED#%N{$eEd8VDOyDljmBuf%~WIt`M5 z8gvDTeHV%S7{rFEe}lwkvP9gG#f`)kL1IgR*igONmMMqj z`vgcF8qwf8Vxa18fW@cRl{<>pLvNA--S#33WwU@TT7fF%2eF|>fG&@Kl@9Vq;`&Hz z6A&9}jva^%HOCXg2CbuIU|{gIf?PZW3Y_`~kOWjwGKdYeECa-bYG^=WcOtPTgV<2L zvp{Uno(~2FhIt?hpzNg}aj2R#AU0@04yeBeQlkXvnlbDKNkA2y0I{KpE+VmSgV<0t zk3ei?koy@Jo`DR4vfqNlp=!Q>*eVb;KR{}rY-Vdjf)TVvs#9f=Bs4&5Xh@hNv28$X zs6i1RHq^3Y5L*>uS-Ld?gD{j`1QLg;sRgm2W;TJ?AaPLc=>u_~8Ww=qAPEKrhUFkO zX!jEX1H)>Np-}cVkT_J$F(mdSB=$oj_8SlzYVk)98>$y{?@m4JA~#MO#HDUBNNiOk zwj~nV2Z^14#Lfb-p%#>a*y@l_skC8W5Qef_K;jTJ^$h(W4%Bs1Kx~Kv!vZAs4iFov zW-o{hHRui!`v-^()yr(lz`zJv#mT_Hz;4UHAPi*-fyAL|WI=3C&=zS11_m842jWsg z5F4t<2E>M1>Qj(7%}DG;NbG$eHq_9gAhtHh$qWo9?HCw@ zq3nAgaj0c)k=UO=Y^Yuadql3~2C+S%MTY>0163pqVnYp50I{Ls+8{Pm+yKOeirawL zP)7tHu?vvc6Oh;&kk|+9k&2EJAPLZ#Y6b>|GxiJ&!cg{gkT}$`M<6!T5zj$vsQ4!k z8!G-C#DNg z$#5CO25k;!U|_iJ$iN^BWxocAL!I&g#D=Q>4PryZ8JrL?%8$gB0Kc6^{n7q2ifH>~bV_vok0?LlyObB%qongV<09%|T-C zM`GVVVt+(pv$`-aFhcdJg4j^=4M1$rAr1@-3??oN48jn0J%c?+0;bgC%G8MPpBsLy(l z*ponPsOGsKHdM_b5F0AKVLD^8qj>!pB%xbK?57|$RNE^M8>;Oqhz%A01!6;;#q7qw zzzAhag4j@hDWU=W6~4}cUw*(Z_M_d#r^<6a=KKO(WegV<2LBJKp_dR85kJ8fZPIQ{|8A!?dS49 zR66`1HdKuS5?c|8Z4P2X?RP+8dm^#@L2Rfw^%+Q+q+#D=P$0b)bN=YrTEaZpoX1&9NcSPNo=wt?vS2(;F7=%H)+(1VJdLe2uIS?CaoHB?FHO>%;Z3ALM)i{FKP;LD`sr;RT2TRrD6bh8o1=jR*-&5Ze~w172?i24N^$0wfMK zR2jsEnxg??L&eRI*p47JRE?WAQj!S;NkBCufY?w)`AF;%5F4td8N`MK zhz-rb7m(ODVQi59?}Io{gFYj%B|z7j5ZfLSa`Sx{ z7=)qh%|4(83e=Z7K#HIm4ujZG@e?36RQxiC4HbWc#AfnElxyrDHdMV3hz(UQ4q`*a zl|XEWcs+wUhy#@{0iVRS|G=n%$i9Qe;s$nvS4HcgUVnf9@f!I*-y&yJJ{1Au@6+a7NL&YzF*q|H5 z7#J9yf!I*-*YzL{RKqtA8!GV!#D>NbX!kED&OloRMf?y!t%AhX0=fKp{~EVnYq;Mq*DvVy^p9Ha?=3GKzzW}kJdO!Ms zmN7s%zmO!j{23S+p_=89*cwP|LnO8p65AJvoq@!z1hJtZ-2h^PH*3~2FtqqHFbIP= z3=I7s38;>;hz&YegMoqJA;>N$`wd7O z6#t-L{|@3n4dMtulzL)FY!xK7K8OufZw+EYEpr30L5Bk|Ffe!pFfa&1*`XkDsG0;2 z8>+WH6~uu`6oA-JiBb?7D&CC5o`}Sr17btfF9fln>eqnSQ1Oi*HdOpHhz%9L1!05J zAH#hR2dd~T68kq2n>&z!ff4E(&^?hLpMf@GDucwKh8iQWEkSIk`UE6)CK9_o5LEs{ z6JQ5O0?M9<#GVIYLk(Jv#NG>HL)9NcVxLE1-vP0qdY>Y(e}mW{y&(Uy1R)wgyhvSMo`b~R z1!6;^=@JtA6%zX!hz(u1!GN?zng_%N9X$d%eG9~fn8Uvo4Z;CsNQN#X_9P_sG$i&sB=#aC_9`Uy zIwbZsB=#;O_Mu=!!aa@b4ct~Bcy-!L}F|Nmhe z(7B@_h%$%^i7kZ07DHmoA+eQ^*qTUeT_m3tJ$`MJz6^ZSO#12GaM`Wwf0TR0e!RBMAMsOJFr|V936tC|_5}Jg>o`%Gpi^N`t#9oHPUWLToh{WEC z#NLa7uTIN&sS7KwcoiG6eWTabI7APK!jV!uaXe?wybLSi$8A|jj(iOq+^ z7D8f6A+hBkY{+^kRR{;{Ud`>1QyjS`Fjh=YRdMp?JmAB~09xJfbh_i~X!+>{4e}Dx z74nS*7;j8xRdw=b{4hNfL|vJ_6hxU!|ElWb&pE}9kpXmc$kXW?c?#sG=cqYpFn*an zRn5tt$-sa5Gc_ka#tG9+)t&q~pZGH}fR5^XI$iKxwEXln>P{M*4FQaxDJh1h(-T2r z8{*1YrfE2-Fz%VIs^R3%_+xr0h)S7$6hu`_7u9s~XM8d}6-0fQzE#u7pGhQmI-8c0 zA7jAuP%S5a#+d0#K~%%^uOO;tx~sO6KjV_=Q$f_8=})zt{F!7zrkm+F`7t_7Z`E<~ zXN;JB6+|tVuBz+g&v<8gsV>Orq0^7)I{7g^nJ%j51~EieoQh^)31SOji~8rMoxZ=CeureoctLtOg{>uwoDf_cJgODFg?}S={Vzt>AEIP z<&0ORFEs%x`3j;urn{Ot`7=(KKGhUtXVUa%rcQoLEXmW&%$)p~7*eLUnK}6}{+WK& z%*mf|#&lJ4Cx6D4>7^j5XZlfdCx0e|?CD|_PJWDgrl(ps`7>$cOy36Lu9(hh33hfU zh&nQTDTw+q{VRydneJ)@vaMwLG%F`RCXtfq&#avM7&lBewFYZxwFZT5>GW&XPJWCj z(^YMp{25nFF9lH<(~p9vJ<~;Po%|Ucrl*3aJJYvAg{DfFLQMAW85+Q zs3SN=MV*}dnRq&;r#U(KF&T7B-v**tx~8)^JNYr*m>%lvEE24 zjxkzH-|OO}&1f+FrHhj?tHnG<29xQ6u1?CVPdXVGM5li=VHBS3D&U04b$&}gbiF689b&d zipvX6cbH+oGF`#LiJ#5Lz{t?lc>2KrE^$_4BMT#g=?~?&)S1>)Pv1!>Pg~ zK$C%i1zcFLFb2voFz`%eVPN2ZE_MKmgAQHXsKUU&BnTSyXJ%yEJKe_9Ng^~{m4SiD zhJ%5DNer}2otcS!73k{vx1hTPBy&MG*R!x@=9Mroae*!d1Z_lQU}j;z0=jg7gY|$C z0|PS$`$BmJ1|~Tn1_ovk&}2Ci-}IH9P6|A0#TXcvbxS}tM^C@%>7-x?x@?(64RpK= z(^qcL4O3e|k_>X7E7?HDo-s2r1%fVoXJL;MW?*1FqBuS7fUeYZ2QMcfrUa?!JqL89 z7%xrF_i~b!oFm1+z~aPM$jHFJx<-hBfyEWV{ylxMmyFLkCoRk@lP3QJ@@~j8l zImg4o%)+C_gIT)C#RT&sq9YANvFhzh4qVGBl^2`iQ1_pLd z&}qX=JEzC_I7ulz7GYpuZvsoQ@-Q&4x3)4fFz`-bW?mGzXqMdAY9G|x@R_$hk=1v7}P*z5nc%LobY#f1_n0a zXJQNt?7|Pgw}U$=Gca%p=YcL@68^2gz`!m12z0lnaDW5@1F!I3AqECMVep+G!l3(_ z1caZk2{JGU3Rg_G^mWp#*OF&okQD9!U6LsLRfd5377%7&&|~0aW7lV5Vr5|9 zlAr$3*GWn&j-P>n-G~VkDk5y`rc4H`3=E>~(-r-ktTalvK}#B#K*7w&6(-8Sz-|ZT zFmZjAVqjpmXJP^+ZLX8koBf>B>dR#r7}x{A3OE(m!5Ha?fUI0FNFB-2b#$a2~9GBB`5f%S58O=em_ z17`+%KGQFdx8guPDPRJrW8g{vsVD+lt-!S#lrqb}9#-PgW@KPsFJ}s2W?-mS;R0P? z$X)@qCzZ<%l%^}eoHPbj(C{~V4bvhv1_n+h_68;`cF<8SAfp5~Y2E`LMGblPaCD_H8 zLC3yufuC_lFXn2g@x-g3j+hY6f@|2p?VIkb08^c=DUmx3_M&y zAX8fFE zoIc@{u9A%>$a}J^^I+n8Ko_loB8Lw_fO0zns|hH#sIs1bseBDKLE4mo^#&*w^;o}y zY~}&oD2mVuVll8z1CczysP|x1Ln#RSzz{$zp%nCYC2x4vvvbn9u=C&c5+YT|8 zf%Oo`t`63{Ad@24yII?~VJ_@}nglNLdRak59vjyMQ2E!#8p6y_&%nuL5At?DE2!}C z;pzstcLLan0bGF~KTZT&63EpIQZ@<93F0~iDy1fa9Tv<5x_y{^3YZhZz`6sJyQZ>& zF3RKdVxPf!819yt$ZnYhc1u0fF|$FAVc=w7eF2K%Ijobo85lSN*ypqI^1ytu09p4! zux_a4MG(zg?w~?tF~lPbtj9qyxP^`$kqzn5p&bo1n(F$S^Rl zZ)TO`0bTdRs>aN~z`li5m4|_WQ;~f;YZFL=Hz)z`UnR6I6oiW(@^t^kUz~x*wzwoL2TjEds~H0jT@y!BKG#;sFNM#US4wV(kOz_GUlE z%E=4!{c&X7Cs>i<@gzhu7ua>Dz^?ORVD$o(Ag5VRgG^#)KgVhbH|adoB+%iB?DZGG zQO(A{S_bmmMOM%`P$CiRmsvsAh>I40+;at-;6;5wVR#jsNJS5*Ffg!R11B@l5K!8` z4vr|%kD%0Z103a|1)xNB6CBi{GeLoS3ml4~3qWdag9AqNVm&C~-U0hl6zrh8V3#tm z-T{T4qHB`;m75} zUeCb5t_zl8=IR6$w|Z>Jd<+aMTq2-mgg%(V%D}1v%2Nhx)qD&LoGk1nY_j|e3|#*} z0c;A^%)pfoDn!k|97e8OPzhwt1}bNmxF&##dIG~ zz@1Z)&A@KQ21?EhT>C*0YR~4$$iN`Lr4LF04s4)WR{~;*BiIrtE;&$@>ICLUGqA?U zGcd3_vuW}(FmOt+yRmHqxo`t03%Y}wH4I$eKt;3%*bWwmNuF${K@DRO23F8v1ngdH z4Itej?7nQj;g0eHYhd6`$t+`F_XoQ}0Ah6j*lHn&QGsBNFazsrP&5Ux?FE@6!5+%y zD!{CAwtxaE6>NiO6Q~qR0|$X<8c0z(*b@w_lR;%t23sG7jCh zo`C_9feXQ*BYF{(AIre$OSBeT?XlT0Gcbr}r&cnsSF&*lg6?F|0V%3t6BA@$V4W<; zz`$P5Rw4+^o4tYz41C~h1I~URE&~S($Wl%N_ExsTg5WS@U~hv2VLc>3+rc~m?v#vd z2KEjxM}dKL0;tC6Vgp$rV!+X)nvAuJ zoq>UU3L6LLiZBUK*9eqr`9LfN4i=CpoC@r-*(L}vFw}GH1|`cmU=9P904U?kWt#@- z0&_hDd2=2c=%O(Wt}UQ&p3k;O2-JWCl?dz$*j5OEa!4Ym+*!!BPKbd)gsTnYx+QE| zgcukkxROB5SjM(X2z2`x2TL3$s8u`(OoG}t94tIs^&lZoVZ_05nHR*)5CoBbKtX#8 zRA{bX0}Ta0dyw1MScDlEgs*{G<-#4H;|GO{r=99lm<*+{6k7_G{qmz`&iGna99>9n4|kx(zA_Z-6;0 zT;8C-xC!R4ajgU;(OYbwZXE{$>mpD(xy>d68f35rC5H!W^}-AcyfZ=k=AaMq+ENKP? zjw&#Rkt=ojjTk2fM*ZoMu}*6BvSJJj9L-=UKCZ_K3=AACU=BY6t1HOlR>q^k3=CjT zw}WapXwQmOf`NfU65J|gbp~1G$qYI@O$=0If^UQeyBkC>2H6XVBf!Qj@z{C&gN#uge7ren) z4;p(e5@8004FYdO85lU{fXv(?0O}xe&Sk1+WMH@=uvLVCfpZ>6^Hl*k zP;ku$b)>IBf+z))FhLPx%fRFS^2`EuQ3eL4AHoa_oJ*?27#MiF#26r>OW=x{fyn{X zSzR_2Bn7%ak`L77gGdS5aITaPXJ8Qc4hq;+Ul~FBm;{<67#KKLgNkNGfh17WtpTyw z1)fYl81E!o57rz`vDp}yQUw_p zIQQ1;i!(4VnKLsmaGn7L5z|SK&o6_Sppy_dZ-JRNLBjw)K{`2kI9V9)iZd{9iGyrm z1+y8rK*#NIvN3`Z9}CwjP(ZSS^8yD~A}ASgfH|BD94sKuvmOU2;AEUH4(bGOa&j|* z?!Vz`0>vN?BPfY5aD4^2l^4um1b0k0`4~ZZnYgS#q00|8kb{A>gMop8Q-JZkI0FOg zMo>}`2g^v_VdRu!Tq()Gz|{tde|fMd16MvL0|TcDBPiNgxc*Ck>{kaXyTf$^6ge7< z>m?Z&9&mjIY0_i_h5Zw$ogjzlFoH5M3!~IlP&U(L1oc@s7^QB5f>965<6)GN10@c9 z#;uYJ3<8W&QYs7#oJL@qMHr=mK|Lg6#$s^>22n;S(2>rZri}HVK|%>eDQQrMm@$G5 z@>5}y0^M%LY00PpItrdqsvnestieH%!YCyHDhlktyi`W1PEZcBXS9@HU`S(>G63Zb z2e5_dj8dU23=Eu(jG%M;G8m<9fzpfpAv6>k~P8MNcU;{-V z=v+PU01_tyYb3}mK8&ss3=B-Og%}vPbU~wrY@SRE44*(%9VpW|Fi5*Fa{1LON;5DB z2!PrY{-89*AW#h&2nqnPnFK&%X}5X7GB9w3fz)#_%7}u-{K7#TE=HL;MFs}02oQ&dQRa;b0|Qqi$YwrSMj6m` zm|Rhyw64Y|a}(5Uj0SPk8D*NLHzqqtGOA6Vo$Mqjy$Do6|j3lg^w0Cy4lK;jVs zvp{*%ZURUmMnFP>fq`oxNTNpIG^lql86@5ypbzRAP63H85O4yqr-8(m2po_D^&r+y zznJ1AUJsIfAz&)az`!*RG>rB}0CdL=*L;xp7l9ifdlrGT{gC+$I-X=PNL+$Z2Gq&q zS_+C68Ah3Fq6`dND?u^}j4~w(3=CZ0;!lN9W+$k1ygrnXfkBH=2Gp|R+6Zc)88OQ2 z0!84aMo{UU#3%#m?sM$}b!UngWk90>T>C*I8pVt9? z2!lhNiGhO!G&s&=3hEIYc9I5-%X3|M2MYS7%nS@%S3#MWK>*Z8=DG<=RV)lluAm^e zbykLfjX|)4>yF*@H>plC^%FpW^cXY<${_$Mr?{Sg>@5J-G+fU?>_P@6WsstmKSA>= zb3ifp5tL4(MfkZsOUpAb2rwu!FmQbVg$09vIw*nv1ce?8xE|*E4N8_O0-$=B>ko*n zCSVB)uD>9*#`N|yCtj&}p!EA6B%s5^0ZKXyj3AC4m*4btX-*3Dp0W%KCS0K7;ka1A zg{3K%G-$kz3tU=Qa|M8cfd^c|*>I(S;*1wu_Bn8E1Mog&F4 z0G9FL(gnFl5M0;=aDggZE)j4M8Nzj0kb%LMOOz4h(Go6D-OVKic3cG)sPg6#2Xm^p zUV}2Q1f!xn14E5e5fcLgmn7p9RtAPYd{S3Hg|!qTXbhO0U#fHZtaK;o`bi*f%7NX_ z$1jy71scHzmv8+1QlR5KxfH=X0e&e^HP595<_Ypktp_E1Z7@%WU&;iOqIAHf2=g;= zuz*qko1H8JgCVHv2+F4N46K_$h8r-3$b#m9K*`pTQAz_;$2o8|z# z0~bFi{VxS`Sh$`}kI8T{u2%$&bgTm_7UY@$;;aXA)FF+H(=gja8CXHLRB~-(^aPd4 z8C+W#L5Bo_J0x7&7$JRO(9P&v+rbnX*A6g8fy)>aQoFz$1Fi)iN9_i41RTH} zXs*4Cpbm5Zm;Q9QOeaYVP(PFF05~jS!2MUQgJ4c9*C$YH90GIVxMZitXF5r$NP~*u zV_<)!FtEmfe0iMlI>?y~TqhazK}m4J^f{SMlJ)MO06W77YW=Zufx4hvXThnCgNqwf z-d_Zp%g3b-ii%5M4nNmjQ0}?{RwlqD0Lp_m!7^gt-XzyuM$iz1IM)g>1_rKs;6RaJ zV4VRP^nAbwIy;ed0m!u1AU*XAk`|0y9~sR+$+ZNO&Od?K3|wNMkpIkRqYN6&FaVX4 zUl>6xDh{q`pmhEf>^UB;2#`;|F@mPI1h~Mp&v$Stl>txRaQy&t85p=6z@{w&PZV)E zf+vcWbL|2-$O)vUo?!)-JSeQ)K|F?)TyH_C-irxz_~a_?q?}X+E?*{43Roj$3<_dD zCQ#E;hfzuel)u8jhMO=-tp|XkHOi-UfjNlt6ioiGj5W6dy56 z?x4nAD3?t-(>73Kf(9nJGMPXp^D=NbfYNt1*g=k5(I8F^*diycZJ7klB0|R$*S~>&Q7jXD6aOHx^;h#(o)fpJVq@q9#gkMZ=rti#kQmS7HvhW|% zLUslQHx{Wf5br5*S1dmG$EE&fk1sb*E5(gWaz#+91WQ7ECwg>}55{FbaDB;S0RTgnbZ2`&2 zf_WtzQXfG)WoA%WUBMxnSdhuUrO$joh=HL;Txuq$$~9sZ*I-~+BQBLJ63oEBWx}kh z0XoWBN)r^zrp%yPc89o>D9CAM%%CKALtN@QNTWHJcSl@m6)4$RfO!wZr9eF`E=#aO zpNLBxny!=YB%SOHa-j_~sH%T1E~Nr$SK5MkFT|yei83&7*@1a4#ihQ3T1=2huvg+z z;3Vq`Hte;y6gbVgF@w_V8*!=WpgP!{d6EhP!yj>}g6XUBouuoPKr!J3b~THHR4piR zdV_;PMMA0uRPy_P4O5elvIjLHe3?NP`DsWyhMO~{YP1<2vj0Of_ZXa&Y- zMgs-L7-lXN6$VAn2^-3q3=E2(qY?Bq85rb2D|W0k85qt(bTFDQD1!E?xr5FeP-;1H^hN`ILyfXJBLjnyfEf6O8Wv5^s2X?)kg_L8LZyd^fq_v8!klhb}C(8VPU(*pvWb*Jl}w-wxerq#(sX?o9-cplzL(0#0+ zi^CWg7^Y9xT;XKx`2b1iEfV`T5?g?sfq@aKO%{o*jl?#ezIKI^xM4n$Pz@3rG~fy| zVj7b8qUm2(IJr+hBgf9e3!3tWsS%zYy3$Em(g}3G57cIVBzEldi7TDNCF_xddXU(& zrXO7Cq+EXzNeFc9AI$J4NaEldccC`0g05JDvIUXYvPf*u)pam)%#g&Lkl67Mb`&@n zOonj4?7c{A@QqDS%XmQ}wNSP>65APx?T^Hcp1yaLlfLA1B%vip>`l{IS34<7Jwy_E zhs6HFHQi~oQ=DfG=)7jAt(8dZb|m&3B=$-q_BJH;k?Aj2J1H}Mp3b|*N!*hUv~CG% zsuU6%)R~0^oDGt=7ZN)jiQPOsca4*{nQm%iGB=iS~%>}v^2I>lV zB(@F`+X{*8kHn5fVy7dqi;>u%lRO!Dpc|UIktC)gu@@t;*CVlaBe72)v9BPpe<87@ zL08Z~J>!VPj^G1b{s5IoL6Rt#es!&rHSbO&p<~m1MH|JZo2+w^kOW?KI-4M^-gNbD0x?5jxZS4iydNNjFF(545ds}(>u*g)Aj zNNfuvwhIzF7KxpS#6E(=zKO*Ch{XO2V^25T;N)Fj2D+aHYIQRb`ydkg783gb68jkv z`wbHN6B7Fe68j$#n^hQG6+o7{3PL#GqRjz`?K@p|qm#I829i(-5_=XBdnpoo0}^}p z^umo!&60tj`)8ouj6-7QOc$)r6t4%Z0EH#wJxJ0gkl0s{*bk7{f05V%pj%>~*2o~S zHIUdQNNfiP8#Fh~z~BSnfI}eyiJgMP?m%KsL1KeCA}|kthLd6J9Y|`9Ah9nXvG0f? zCB+v=5?_$m;5%=iJ_Fx*17%BquC{@)Rgl;QNNgJ6k!@HkR)7?*a6e`HfD+&W+DldAhGL_ z*j-5Msna{RI4MgWMiK&bc44+XnSOMOlQN_5^t)d|#Ci2VSLHxM(rP;IRwwKF79^pG zNbLDY?6pYj-AL?{NbKuK?59ZV&q!=W(4{v}>-iyUP_!^G$U->aWT}nBwnSpPBe6q~ z*vUxjLL_!Q61x|PJsXLAMiR6m3+kd9ND_aL*c_lsY@ljD3t3=6tAHe~gT%I&K69JX z{(5%MH8L=5NNms*t1u&cki;X9*eOWt0wi_~61xM5Jq3xq0K%UBzBiJ!ehq{J4p`9r ztT2m@AcR5}OxvT@4QdWJjA3gah`U9TGbjiJdT=akrEBbd}vs5|W@z8nCcghot7r^w8Z- z*1SrfTV_8-T8WOu0iQSIGo{YrahQvOM#J-5cz7Ju8?h|KVcnjfx z1K>9jn-g@q3e<7pNNiOkwlNahar#Ab5%Kz1B%y31b|n(K9f>^^iM<$!y%CAMABlY% ziTx6Z{T;%Fl+~YHN1fCeuT1}W)JdHcbZ(@;^h7;I;prB~oCFwuO!qwIq|T^3z3`ZmI+H;4 z^jXK8)L20meyp6{XrwMY{l+mT0Va=->GQPZ#05YL_Q2%>glL{Fc-%>yb$18@1IP4- z#!e#Brv`}gGZsuw1PLDwVPG(TShe6dcqidTknraa28KTn;RhEh1*bEfa8hS&2xnl3 zn$GxKRa87Tz93gGUta+N3{5Pd`vwaexWt((ET-R+0IgLV;u_I@!jvb_Rr!7?`BMTLn2-KNv7D zFmbT2(qUj=VqtwC2cp=kL0jHfm{{0B%LJJiIkqb?FtGfU0PQdY9m~XWcKYhuP6|A+ z3JeU)y49dviu0ylzwM+TzDbyYfkkZ-NW?$@w8QW+h&gLI-yJ7Ise?M8q0$o|5%xsT zg2|I0HXHj&jp>dpxl%l{L6>@;HezI8;66FM{*IF_I>_#p+Ezw^mC^(m)No z>F_y7#U@Gcrb95>Vfx=YPR@*Z(;e?RDVVy0MqaZSUxLDsAGGX_B?ru5+OTmtN#APvSK zCyTJJ1PwBqfY=hCTSFMwOuvBkF|t3M{^p*OgykM31_n0sNuUK4JZv`pAglL+?#s4a z1PTiFtEvnPY<3_v3;T4Cb@m|L91JX3({1lN$%jhnFfg!Nv4X;lk$<;30|UD?D@X+s zKND!G%!UvI)D1c`%Yr@ zPeCbLB+8V5flK%w%R@;1=-`U|`@8dCJ7Vz$*f}q>E1^T#r_?-2Ehfa3=BdbWehA1)B7GcN!1IfGca&Y0!6bJ3n&+H&SiYZ#=sy_2fD>Y zWEE&&Mr0po7q7@?0gx|2d6h-vi3Z4*g1QV0Y$B^b3uQ$zKs#7PCK-Z!nXJRWz$LO$ z59CWjRgf=FD}j8;DaF9RCt|4r^5uO_1_l9<1?&8@iH)|i5!q&U{Dv4=VxHh5aBmqV9*p16K7!15{WiuV9*w6F=AlQ z5dpP(bVWF{r9m4t`Pex1nS|IG82G<{mg5;P@q_mD^6zD4VBj4M4?n`7c zVP;^E5a zAGD%2lW7lVBV-0=J`)!w0|UPm$R`C%AaxA zD}`SHq`3*Ko{@q3G7|#>XET!+Cj$fb4^ZM<%oN1Qz#y2!$-p24CU%0hYx1&yT*$}4 zd4{QeCdkM=p!Jq#!KN_qyMo+(4$NVM#Lam~+%Rw-1i9`4QwGTVJs|VBm_f;adnIV; zAvZH9I{73x#hI137#R3LI}JG{n3r-gFfj0MH(+4klw@8DDp~m7gR-y`vo>f?90&hD zkd!oYFcSj<4}TEIR2gQFGX?k=85tNj<-o>@@N<^<&lXXdS33=HBDoUY8S+zbp7;6QW(8zo@_N<;48z?A?k+2iy8dt2f&C@eg| z?v~i3%fP_t1$G7l_dHN?@Miwc#lXM~x*?e}fH{_%fk7~Xn}IRodciX%0m0v(bRx^T6DD^ZBqu542g)g`tdC*B zY&_Eww`(O0 zCWyH$$mX^po7;wLZac(W2JR$KRCKW30GSlQ+0D9;7v{nqs7c^bwwD!D%Chk*gUYHt z))ZFIvS|J?khlB6HL?%CEGVcafSnk?9}8MVKM`z6ApaAPvPoc05PvRcZS-WY!-DzW zfx>4Bm=nUlU1G$*z&VvwiI;(a&x>;g>pi$zW+J;~7T7KIP{+&$Ifj9gfjbej9(xY! zT9EDl&iSmMg?W%LS%9p2Ay_w5^CF05{w<&qWHH1e4BTfx<@OTRSG=G?2^8?_ATh|! zxseq#(*-uQo^un_*yEs*eKUCbFB=25HfTxp7FN)%89qhM?W}Y87#R4$CEyNLa0w`o z%)q&m^*d;9ra%z`=Poc)kbyf7R9x(41#N2N^WxmcdJCjc7L-=@LoEWw!~v-L>%mcR z5aIy_?pL4`eTa1>XiK0s=P_0lepoynN7j7;svE5NBt$dBb*I3t^J3sO0u>jhS)YMS zV&^=^8Ui=zJk+E|pj=Xa0UXtA4BXE^ZoJ59z|X)S9>IB;^$|YJyu<`h z7+wV@QVGxz#hll`$xK24l=iQKBT8aADD~U`N4dlfMFs}Wo8X|9xC08@Ti{TXFaoK$ z4GtKI!g^4`y#w~A1lU1$!7gRs2CeGgyvLdV+N8G{q~kH`FMep=ReKt&0dVBnq%Dx==9I)W5{7V8M@WMrsk5CWC# zLZCLT5IADF6+va?SJrfpvLcW<5aDUs3=EtcY#{Tvzkn(dVF-IEsB)J8v-#LKHQC+? zFhI)#EjCbjzyK)^w81JEA?1M%TbBR>0~5bGXFUT0r!H8EnIE*Col}pk4%7?cPgZ4M z;M50mSQ)r;K-H50+cW_N20j)}6E@KFAb%hz7n_1LGw|DjY7;XshmpS$R05f^fyx;s ze$eGwoEBgXGXwW2P_xLA?H9--8BW`Jwthhd1_99COinvCP;zGAKLm;_d$#?c9f$m& zWpbPjY@jk)0%D0H*b*szLs0$c1m;LHa0luzFmO7vf#xdtBsksJ&ImFv@OOc-pgS9= z4a2}M1S&r~z;>`eO!8!V2^zc+Vc^aHndQYc8?>=cgwvNz47BSF>?l951_lAp-b_w^ zusZ}GRtJEs7J?WR2<8YgaGwE1QxMw?kVz7pp==34Fn5GO+yOBu9BdK`e?2(dBEY)Y zAWn<~+sMwq4O$Mu8O5dq+T1738N)UgEWN?s6d;n#elzMPLN$7zBDiv&lgfXav zmj(_32|tjcbg(BFxEFxRqzpDtqlb@!GmA}Ln1O-+Kgh^za5`b&ZvsVb4p@SPftLkj zC$|8|jk#>UK@Q>I%x5bXhUM!5ws!*c3=EJATnG*wi9%3*ECZ)62^&zcUe0!yg@Hi| zv^SHpl1){Zfq{X08EE@W6`P?j0|U2*1Oo$SJzKvpG;gi|Z5;z=8*ugmaT$17K$h|u zaJI7D6J}r#$Sh*uY=Z=0y#P2s+rc~mfs~AF2F?yJM}dL+BPhjmv8@wkU=TOp>|x^; zVPKGm24#$1ut8F(MGTyMVATxV&q2F|`q@AwDE9`?=AS8S$|4L5g2o~Y4B!Gl2*hIG zWdWJOr@%RzZM6skLp}dlP%$_M%wgac1ZAALY#T)w7+Cmcg2G}R+jbF9)%^-ouFq%N zD*|dQ`hj9%0o!5Fjy?VbpvLJ!wv!?Z3?lqepy*h_b{^zXep`?;ma$zG0qxD?WdSvI zcv;qRgSxuc!K6A*J%|G;jCff{|7T8h_2JQk-n!3%FEXu&ZJx`p0 zp`P;r8)#9b-~&+x22g>_AO!LvxJ?L-H3n|bSw@^X?4W{|1vCN3WejGPfmV5XfSFdH zHHe{LrZH&EY8r^iC%{#~xKE6Mf&VXPMPDU&K!<@}UY&t~s|w6vCF7VOGp0R&= zz(*&wdP~qM=w`4SA3x|CVXhW1ho6CarUnB8S1TiE&YKft`Yka;mn;LcU{n&^oaP4Y z3E}c&{v^i0APFjd*~DSq0%ZpVK|vUwflY@y!wa;#{v~+J_ZJ3+6wt{spzeGYNG%Jy zh8hC{cQ!~32Ro>r!JPvV*I)oUAW9tS067Mh^BfEe+_@m5*=}&xZvt({RRFcU8$hKt z1G|C{0|R#>h|R=qHa+r_leKNQ0RsbfJ4i@?BQdRjfxClAjDbOj1GMFnyOURpfkBx4 zAt()YgUU7$_6B_h2JRk^$3@wfO~3fbNxc51CIbU^KWJ}=9J>yPJptrjd3GOAjXhBu zG;+WW+6~P;8KljDJxhgwfqM$bagOZ2KrWgN60c{EHDqAmo&jPvu!Aw>a21LD1eDNahDQnL+vvBexu* zxC{dWKNBdb<-w{L_}B3;FmS6df?}A3{{|=))WNFm@cV-@kOrfy3vWx^97U+oEYy+pZm>8y8ezN149j?%n5M@25xsoO&QRBPMKU21_o{~M$it#8;mk< zLHWy@@st;v6(1P z%2Z>NV*!oiMuRx&jB=oq#S;rkSQ?CS4a^J-JaHfyO-8xd)8Bq~l9ZMMIW-p~ro$)) z8pGi!05$Y=8Rh(^EBj2Res+N9(e7+Bafr5G4^IzWj{fPEWCUl%B?iLf8zXJFvz28o-n z9|o!K1&Ld*%LpH`%q%7KOw zc=m&aL5dmWbU;2l0E)fn5>T4#Vr5|91f3rU!r*vdV&G)~4WqNH0x3PbL6(7mjfdw7 z_ym|uEDQ`hSHYbMc2Lin=O!qju`sZF1lfMe8Z=Q+!gFWMbh}?pGWEuwAb$)RCgorU zrH8L`w3@6FBgdMb>Q$`sy`5?sz z8YE`tm$^Ru&2J~^`gTx`kpsJ*k6-2=NC~9y=I58Wpu)hwqX;hF1o&k@bvTa}m?y|D z6ROO>z@rW33GvI6YceqK=zvWT=4aq#0mVP(8hHkW`Jl`LnuL*O;C2W3)PV7jJOcyw zb5OQ-WHi+P^=}<`7BgxpF);AQffDQzu=g4GpC~Xe@GJ#$SojsDulwUk)+NY;TB z3-bGe&RK4j8CjLVJ(_F=o^6bvgwMd= z0J2~^m?OZi0P^b&Fh_yk1jN||<{0p2fgH6P%n@(^ce;7@GJ-nY0sNlR3;sGuYJmEt zJO{vG5d-e?@*D(nV)>0gv2h5@iQ_*#edAvzNfprEex74sf2A;RgAVE7InL;+#K6GU zz;lvut}+7y|K92E{yIsTZUx208Aedkjvd@>+mr!@H}7?1l4mUpjdnj)+%km$n%kL zi7EpFzbZEa1J5Tgn}Po-D9ArEt^#d_;nx9`kzW`=Z6FSQ(2`l6uV9bx@Pk%O@_b|5 zpvu4?z+VhnZprf?s;us0OIlQ}%U7(oS@8vk}slK9Pd8?<+m zf3`FO1J56@!z}r$LA4tncyh#we?7@$}a>; z`wC#*H2y=NWT*(9Ynjf!2UISpfjKkyW2V>scT%fw1zDj57Mmvk+UUt+2G%+sJZQ>e z&IBqR7l6lBc`TSf#p6PLNlR$$Iz{0DhRxoRw^?vtP%ii^yKkn0ws+# zGM_;4;m34Ll7T^oQ6?Rf@xs7{n=r~GfRY7dKFkzUUW4)jFUxAs03WCrJ^)HjpzOiK zz|8|HkYbp&Dl;(fh4R>>GpVRCFn|Y~c`}(mr{ys4e*!7V20O@+UlWuIa=;cj@uz_j zR4x-U69a=Yf56nc&WiPCRAIeeo+73gH3kNe3eeTPB1b{{U_?Nh1eiqTYJxhhvp|Q1 zGH^$NDs;$97B35^*UD$aGlS^?$Q7qRmE%k>n}I(C)Pb7C1X3Z#4?510XEr!sHTXk8 zHNadjM~jI+YmL@GW>8{g2lM{2$ovMG z!ozGJ4?2xYrU+CW2{D7(i4|-z_dr#c2zXj6ghS>|Jt#s&nL%Y&7>5jK#E?e}EE&fk z0~#gd5eFNZz#;PkWQ7DXs9T=IAv4>6fq_Q`tg?thh8_8R?8PG089&fO(RU~9OKox`!*f2E-87WQ%1|DDL%UTQ!8WJ+r zp!oM=ehlJC$%KGZ`ZI&d)fdV#ppGI>0P|-p(6&#RI&}sHo*-sWL*j$7%mY0J2A*JM zP+|B@StbV@S)pJnek#kX1r^$1VBRlf8PJ3yPdJ$OTUo{m6a^7rU;j~-F$C3$kzn3m zWf?zEE{kFY^?MjpWEwz)R5VzQM@424C>O_odAuqzS3owzf>jEr$n=0tBjZV6{;37t z_Q?rqeuEM!ywMj38ZH9mCQuTEigJQBMuTD-#y_sbzyQKvKBz!q;{kPNK;;l8sB8j- z5m=6$ffFPM3KuA!x1L2r0CZ3jXxI;wj6s=}g@M~gi-CbBiP=t_fq})`n1O-U0n`L! z*{#dKzzZH_V&md%snG@<;|vjcR%uxl|gFz|MR*o^E6$_xy=;4u;=_9S%%2Hsv! z6OV;mOOSzqw-3Z-+;GG9bhbkOt$wdsj^J}J`WOJ5v2MyWqE&@pyvHufc zVBlT6k%fW5gnfo70|W08kY*PKmen9vEp69kU|@MF&%nUD9wg4P!i0f=cXy-?1A}1k zbX|65`TE76C1UYL3=F&{@<4~auLc=%ehNs%5*-ExNdFwfV&G)~xtaxZOcd`mkOG!! zke}`z0I9tIR||3%1IrW@1_s_IV8c(zGBEJI0u7F_$b#(o_z|RmQ5S4@Jp+T#UeFLH z3p1#%`V-^^?%4ti47}`&AcMKRxEL6C1sFlvxyw`;7w?B~K_>_CDl=Zy1&!$z$}uqTsxaOLWh{OdkRDaWhq?^)3$H+cKbQu`<*m#W?^Ys`Q_>X~nZwzkEF!1MthK^0Z97g_a)A=}^ zCF`9)k!ubXW8v=sg`owQ!^*%t9VBJND6YrAzydn!fsYHcY)t{g6b3I+;&(l#$G{+R z1+$P@<0(;Sx|kuj-P>nMZ^Yl9+!x|9B7TwB2e}a0WHPnU|`XdXJFv3 z_wUwYV1ODI%%#u3AR-D{=Oa=BTF)+$q6=CfS0xBCZVwm8xIID)46F<+8$ky=Mcve6 zU|_4@pT}pwz`)+X&A`AvAC%P?*g5nW82A@}*o^F4AbS>q*i7sWvJ4FTi$H8Fm-U_UoKmdjaOl39a+fqxB1h?{*IXkvdIh|R;k zW_mA|vv~bXQ02V|RL+U8F9M~l%^}*0v{ez?d1A}6>DrmTe|A!`MK^@qnpCHFFu!BZu_Il*Y72&@CS`fzwZbyspf0Jfl;AaMR4kh^SYk>lU zmC@6Lfx&|R$nCpwsvyVYgE@KppFx3C z0Ol0%gO)%DucSpbW|F4O$my&IpPfJ`R2x za9HzefpW1en9aan3v#O+m;;(s^#={Ff;Iy2+cQR+Ffj1(@cS~J2Wb!kMV%j5VLb!H z41X|>g`Wi!cL87raPWi9iQo?eb2u5etqd3#_=6ZHf{J4nP!-6_QmqH70wh4|6+lrB z@&vf~BG14HvWV9dHfG7d?F5RX#f%USfh3ftfEFLetY^#s^^+JF7(OyEFfh*HH)CK> zd2h_Xz=)7h`HJ9!jyqA!1#MS^$TNnh6{Qw4Fm41pQ;(5>K^=51?@vbthH29$3OI{# z+AuIMfVf+yZxC=64K zAdddRm@(Zz&{0l4|Gchn|DuR~UJ54tfaux>rav4LkAA$Cj8!~}Va8D&kt9al~^1_qr43=9kn77XAsR2V=>#B%x*A!nU> zUMB_y-5N#)21yWO2`CCcjEjs642B>E3ljr_Er?;r#K7PQx=N7~G(P|`3Y<^{8T3GY z(GLKH(K1kt&rlAIU1m!L1~pLFtN?q+gpGkg*N1_DA=HV1K^+tq2~G?Q&lxSIFRZH) zo1XvEke7!so~ej|K@)VdQPuSQ!p`FLoF)tmj7{KWISdR8MPP#?EEyOKFR+3nKvjM) z8v}!38R)2hCQt;mgSg<(Xae=dH?uJ?7=c{T0t(gpYzzzx2B0J77}vrKtpLY|tTh9J zAvi6r1sTf0&cI-}R~(f3)`CpU0P(?zaV;o57O^uh7za%+5^*-L0tLAt2LppKI7&8w zVk8j6-3gks-wd)fpM!xx7nCf(UI%3!kk=iprYo)v5S{)}#93WO(42uG)Cx3v6vb4` zz@S^pz`&3V3Ux_FXov+cGBAL&t%7Qc6m`~62PN;rU~SRhECcvxr-nH7vbLfYbX74h9BDE|g#d$uS0N z^?-7y6gb~q;$UFV1Z^V%xgV5+KrzJ25%JN19GmVZ?kvp*vi}t) z1B0dp0|P_(^m1`$C2=J!1_s6h;3N$(UEY>~L3Q=?4dTus!5|G!*AK;NHC2j@= zEl|6U@h6j{DFcHUH#E;P+cPkzi-I!069dCY9mvg~ zq^H3c&1lG=3o4+&X=oQ{F3^dA!P^d!TKOfNg`;OUF)(C7v@lN$U<2tf0G0Fx4C*S3 z3=E(&)(Mej;%ER>1ZCigz<@#B2P(Y?Ng5PX)-9lIO63g4r`Jk4E7mV@VqmxpRZ`5r zpgEV3fnftU5kxUh3}Mq?i~$uC4B(Oo+{Q@0KQ34(l0abOKU?;40U|_HX z6~Vh57#JW&JL!TtTYErx9CW5MD6n-w`$a$^>Yxf2l-a`^Afe7J?W`nw0;CpnOb}RY z5(5JRNJO&|977Ow@zT!9ydW#U0iw#Fw|aWNw6mn5pCbbU=rCV~D{iN!F2(ncJ_(F_cxn?PP)&kS0{1M;5&*nia^3qT$M zg|#lI`EUSqPqbYzXs6i;ranjb0a$vVxU`c2&%ZG(o1Q1*EN;Q6&A{NmV#vV2XnDdB z7Cw5?ObiSTI-u?6*7wjvAL%kMFgkvjzE{Rszn&Aca#a|#0G!cz3pWD;2n(7rI$vdF zU;tr39!6(F1qKEX78GZ6Hf3jE0AWEbMkgN7ASpKk1FMhIT~!7K5N1tqPM2k10AbF> z?2eHV3=AObJVBp<0fc$xGdqJ$P6lCqH6~}Lzgi3oAk06F$r*G69SHOMVRm*`U|;}Y zp4rUKj*<)vAk3-2?L19~fdPcMGZ~#$$}%vll%4)yQi#fQ{^tc#r&q_Cns1*g=Pas& za)8(Njb6^bSU`t$Wo%~)aK2{5Xtw=slk)<0Mzig8UCwN3k~N@Xsz8Mo0|P@R5_|dd zxf`6VB|&8`BUJh?k~H`9z!pjI=^PuKd3dcs1MN^X?$Z@FI*S|DBMJ2&v1cK%mm#q? zP0!ru>@LXxIzS3)k|+{edHTtX&dQ8I(|ubdWptnlnvfLqBeCZou~$tu-Q=uXe-laQ z84~*o5}T8ofdS@IQ6#n^5?dFEZHdHoLt+OZv8y0#Q08M`SO?*N5SrU9i71Th`l4qE&#HVlF>>SV7 zK7HX{9r5WLb2)jYTWoRWkvsxA1q!PEA`<)l^w=%V%8Y!|8@D)%duoE(B~VqSNNg`8 zHt5C;m~E*@;#ElOdD9XK11JY{j3!J`_jJ!~&eoDwkko>1JA_HUpI)e=E3PUih)BtD zNNjB+w&nDj+nkl_OOb?{kk}KD*h`Vvn~>Q1k=SRE*q~cOU@qbWo$3Vjh&U2k2g077 zzulQt)eXV{2XinI8?>DlW>E8V-|iIg`guswn~~W2k=Un^*w>NRkCE7*t3O~yvw|vK zs2hcl*lI{@YY00H>_&G82h0veV#gz~E0EYNNbLJa>@P@c9?(HiP)A5iU%10LxPBs% z&^#pe9VGTwB=&D4Hs~~BnE%*8CpAHh=0#!)Be5ls*a{Ffq|ma2aKL`GM`F7ovAvPl zfk_CqB0TO{@mBsMds_YXCiZ@TU-=jQq)NJ1Nt z*q|$rU_o&kN&GnyTM8+^sUfkAkl1!e>}Vu*9)t}kF{&UOaB#IDu_qz1L5rGU4qAmI zz72_e2#Ng+iTw$Q4Z3&>W)7ExH6qW8flh9M296RE8#Ma>(_n=p?lxU;vafi39FkBL z61xnE4Z6VuW<(#7_$(y$G9>n4B=$KZ_Ddu-52%f-0X^jqw6GCofeJ(d9GC`3Y#SuD z2ND~!ED@$R3rV~gi9HR8y$FfDPSPC_fV+?+jw7)zA+hfwv0osuKTmhv>#QuP2pW=s z#(^FZ+i7~^UT0<1LL{L&Bz6xHd&cyWd!4Q8KOqVIM`H7WPIiLYAdSS7V@Tqckl6Q-*sqY--;mf$pw17}d_D-<2^^SG5Du8FhQu~PV%s6Hy^z>p z(_?G%#ToOa_kyUl>8uBxvw43ZDPW(j$d@2q?*f`hgIXSd#EwN`7a+00GjCA!9Z2F+ zkk|{5*lUs4JCN9CAZ&<7Z$LO;k3KinDW$aLLf&f?PpjyWgT27``#f@(`ZVpk!tJCNAZkk|*Ozdhz` zoyY|`TM24}I1*bGiEW3(c0po$A+ZCH*kMTQ*y)|eorCK^heN>pe;G;oBNCepH0%a- ziZBve9f@s>#12DZgHLdR>II+R1Z9IyaDvr0pwm@gjsPFw1XTn+!U@U-9pMC113tkC zDh@uu3CaeYzYkOM9?21Zk=Wdz!FL90tfiig2V=GkA*qn29o#_B=#R9wg_l285&v&NNgP>wj~nV z1X(|?|EwyqBaO`t-JN{UqY4M^;5 z5H>jI81_IoprB(ogv369#6FM2eul(;gT(%X#QuTA{)fb7(MP0GZhfSpOAbi_v@aBv za?Fs#K}!Z;;-KxyFm@D@8qg{cn0OJAcpVbE3&sZde;SO#z`(EwiMg zpj$K;7)&7?u)6|~*r`bDA|!U(^q-fUmFu@62^~UWUqE8>nIghP0g0^*VuOx8Vqjp< zH$@!QXay37y4MxNRsp+;!3)HOiid*OD$rA4!AF`wB|sA)j8F{~AVp9MrcbX;ix#iH ziX`*}i7jA;aHBMc%?`0s-VC&F7sA#8i9@Y11+k&lSb^A3aStSR7!o@V#8!d!*^5CO zsD?Ta8){H9hz%9*1F@mvlR<2#gEk?tuOYF&BC&^LNLIug4L#D-ej3u5zu{La8I(Sm_N7|LD-5{Edbo?$hJ1C`i< z#6AUL^FlOVMq=MVV!r^fp?X;?5kBJsu|el+GB7X*Su!vPL)o$*aj4_eL2MOJ_%kpt z=zus-2{RBI;yMOv5F0A)3SvXWgOS*gAU0G@GKdYDgk)e~NC#OAWfy_Op=xSCY^XVn z^&k#Zq8r49N=yK;q2jYZY^eBr5F0AK62yjz?*_4<;zvPjsQ4)m8!CPU#DP= z8U&KP z8`5QG(6we@5QefXK;lp}&LB24ggiiOsCXC>I}yZ&s!0Q}q2|<|zesy++EhMH3dVv9o3 zA44g~Akb0~(CrK$38+C6Ky0Xn*&sGld;y3JRev1BhN?LSVv9i>bO~f8lzkT@4ps9S ziT&LM6#q~OCR+vuSVhSWVna2HA+Z%eY^Zv55L+B#nYJwhgD{kB1`>y=aY17HgV<0H zgn-x}HK6h*3C3YyV5kJKp^EB2Y>*<*#5#x#6`z5`UXH}xhQ!_tVng*F1F@lcPlMP{ z@oToA@*gU38%g2`hz<44A0)P@9RmX+R9p^;Z31FLvzaXt+YO2B17bt(h15_)ATBT^x> z21#NE68i{VJXQQ1O3AY-T5DP68D| z>@W@k0|OrtTL_6Qg~XOaVyhvswUF3GNNh7CwjC1N$q97E3Dk97ND_Y2Cq8f%ua80! zNW9UoPhyU=zx~;2~MB*L{xhE zfm$h+={906DvTb}6UAKo8AGOT1W`HD8O2@v8C#|Yio5u8ikx5oo$tetG(Glkf%x5dX$t0zjh9A}J}9w`YnbtQLLQ5HQwOZh7kX!3o5v% zGX_kz1X1&+Cn~t8vp&#fWLPr2@V|-h^aTno0*v<4H-dy)bQu|DOg{(`{s0m_Kb=w0 zMV(1Tf4Y{UiyG^ZVg`o&(?bzpZ3o=zt#R z4-&pJ{Ub=YZWRMV#Po+>MTMsuD7gqQu9)tqNaq${oHKnQ zNO;dd1_q<)3pcY1Prsn#BFqLo^#5Q0m&A5PWtaQR^;4O5gZ5lIf`|*uw-^~1xSxVf zX*mY+Fsm;}_&Hb!uK?>SW=|#t2EGI~1_svG%ojl__#QGcFtEM>b6CI~FxI!sAiW%X zpkvlq-+?(?eEzHq46N_L93H;=ObiUHAHb&8^D(gAVrF1q{m2YDfRC4r^)oYQBLc*z zFJKJ}5ZzzF943hFZ(!Xl46LBk%le%;l!<|Xmyh)q^LLO7r+^&w8?2sz4^&67{sD8C zK>a}m*1yc}Ku4|fO=n@KXJGvYHj0by4al$m!5nVBb0GIJuz@9c zbVxnOj|{9rEQdf53yL)c23BE~643TE0aj6#2l~tm3x>Ok$ zSeG*~Ffa*4f<-t$SE{oxu^PEEFtEDtgD#LT1-Wv&8R!BDbrAE48;C8X2U5?$s^Q4M zz{0`aX3fCB!otd<1)|s&tAMF3pwsSIHi8r~avarTU|{W10&NckEq-P#pPne=s=#wz z8+3^TXg37w@9DiVt_tGXGN4N&c7Uu>2c7YzaTCOhntnva)lhN=$et7DKt^)3g0?oF z1hLsTw5IdPx=QmzfUagZZ2`(*Gp3u$y6VcN88a}jSTcfkyKuc{U|;}cDBii?D?xbX zOs|)9m6lutQsTt;7Nn~Mbp5<5gzYQS>Wx{g8xbWD~Wh{?bKT2;fY4`Q=$6f;fVCGW~rF9O;d zYzVrEnumi6bW?;8h%LaOB*nnMZVYmP2#1zA0|UDWh%LbZ+JwMv3Ua0l2ZtsD1G^c> z{c;R!EZ;%5Rj|APx#g4|0|UD`NPwM(-DV5O9h=-hcTIrS%rkJf8#6Gl+kx0D^&DTc z7#P^?K?ZU#unK!HFt9tcvoJ8QvDC0IFtCDdN#p1OSs}~w{WJE%_K(|mZI)ZMYxUK@ag+ia5 zfk8p!oHFPZirsDu3`!zqY77j@BGQ(iTPQ&H-KdK22{SOLi5yc0-9iC6TvS8ki9P5R z3U&q1EfkAfK(|m#bq3u+!EVgJpeypsK^1-rg$QV4>PFD{#Rg2^-Rb-~pfhs~!5n4= z9?+5@P9r8zNQtv?nld@DGcZWFPd~2YYNY{M`N(O@1PXgb{ut1~$#!546F)yFtnHc9 zz?V`?ovx|us%G0_0lt$0q?!+OCk1F96~DJT_)ZE?%4FaNbw)WOn5Hv=j)w-jDH7}q z4*o6Edz4)zohr=07f^tV;N?FEIyO0$2~@4{@iXZ&FmT2(fy@-(KWN3kz!?v=U4ow( zq7-gTT|lGV%;upxn3ubmRdj ztuZq2JO&+}k;$|VcK-wq=pKj7pafsQ1X9Pqe;9O6M-kX+1%7W((kx>Fc}|HRv=frE zoGA@*|Aa2c@fBcuQu*ry85lS#!JIS(o-EMe95qZ^IH31W*nlhn-=fjT1j?5T{JtR1 zHi6YMGVm0E&f{%nk^r5Ta>$8+fpala2U;=bD4Feks$c2#mCuW0;Tm(Ag z_AJ;G27b_*bOxAPogZiiifp4A)JCvL z8eo$+ASP*oP2#F&;F$(G&t03@0Ca@}=>Cb-aHGtjMok1AFm3_%DkJ|_P=c`nbC?)- zK7%w{GgpB$^KjZRe}!wdhiV4<+yUwi2U`XPPDik24t`Lm*K<07d7KP9GNAPD%)A|T z|Aaf}{t0j(x`B<70GCOxaTnW(H6;2PZw8;>vOMCSnJc+mY5S)ltTKm-Gu9t+4C!D^5QDEb(97J^F76c%v2MuSqVFzaN{ z#S$Qa-P5JjU6lnNf|83Y>v5Ry)9L=|u98BFKqu#`vVMdKi||aBQFoO#Vc;pP=h1Ko?*1!HsPJ8C%Z)HMbSn+%{x$+acyM@Kk_`t`61!UIqrf2+nR+Nzi=@ zU>Ej)jACHm2bZF~te}#ejsFj5PkkRNs0iZZ?*Ro%Ke&xwo+H09_mby7@vBbOZ&s z?A^f%E_)$2U;G7aScTkt0b&X=@Z^B*k=f1q0;Cai^FB_*sc@3P*Bvyi|z3Z%?h?4LHl?^voK~XL-5tPVovVwwIA{G?7w^%`;D8UL+bDI?u zFcRQsC;M>U|DsJ3&`kT%K;L<0@Gn2r7}k zvfc*?fo`f70>>?nEvVhV!3NUC^9FRsi!g+352}SEz-;g>7ipmLSipH-iw%_b8Ti3@ zUmL7~5t8?H*q8)C&6rBiaqzle8D@TU(4qEvZ1vy3w_IEWHEQ+QKpa*E9?)PYrvV!u z=xA6NtYmJ5(O1Rz!ifOQK&j0yyEgc*2>LD3Y%767`M0(8p- z=!PPGusgya?ttBL0Wt~djtH=3Hi!%BBf&PZGw|F4m1j|Gvp`0HZn+SJ+|ZECz!?ix z!oc4Ly2c=m?GgBvi!-1yE}jik_zN=dfR+JrCa^sbg5GkG4!T?dbgBqvGC0g7j)JO( z6mU362!c-eO=SaFAW?4vYDcEAfr3EdI4B>bvw=Lpz!M9)$037FQ5bZ3B4-xcbkON5 zt3k;x8=OuU_*FoWn*)|$VPInc*~udga$_!AG3crY&@C75K@I`u;Q}^LT7~4*LU7=K z@?JdyXBitPeMx|>6yPjpJBoD6#az(bD$i8V4&o}dmBI`RJl7P#w_LD`Fff4gp#tbq z32?RnXEhL)fsF-ZDIe&Ti!c%JnXsT+F2Jb`cF6^Z1G(g)p0fiSx(WDUV&2O95xV}fq#twsED7-rYQNp=ChfC zPEF+h2dYLEuvvp{e&FW-l`#w196@(S@b?%qFmNtm106mr!M_BQy_d21ih^#rU}I_L zW?*1r*$pP2f=N)zhmGa307yIyO#T+G2XXpAzE}pzhbzEWZa~{3+t@(Y2#GufEg}*z z0_}SfnW_frl&-f2wSGiE_hyO&h=N)_p!Pf)1CJc2-LW5>zIoh0h4o1=8+>uaFOc)0 z7gvCC0|WTtih9oL;M~r{zZ6su-T-r0_FE`V7m$H1xxIyFBRWEA@i?)o1R3=AAo_!t*oEYGnF zbRO$O&`6L1$2pK&Ccg*GE;(?dgHF$%0&=e-hdSuui0L3h>p3nvf^MwAlKvA9M@Ed{77e z8Ur|%I3%I5RBy|`+5z(3g4LiS_T)jQ#4eGOWMB}~16@r48r2d45e%%;Kvx+ovjjM{a7K>*HlRx@Kx}r7f1tQq3vwba zM+!H?baqo${(6vZ0gks$pt~v#Nir~qaDwit0NE?Su^V(1!6uOZWEj|3ge5^)8ss+C zlh&ZSDnM>w=iuJXBgMeL5hM?~ssa?53>-!vU+o03nK-_J%-98Dvv9P7B5*f|&BnkA zI=`BGugqmh1_su>Yzz$CXFvhQx(Ia1$7L{6ZTd!2SIPQD(9vGbpr~PG1hEHyH7lSUd5C@ws_*0630a6x#`~$tm zA{KOy1^BpMd9W%5em&4dC@PGgNN3^q0A0$W&InRp>|-lMxiu zPh>#5CAf7MLD`vwQ6?XBk%XEqWbl|#MpcP{fm;vE<6)Fx1*Hsq#!SdP7G~4TT}5KV zr9hLqG6tZWV9E#@GnHVJ2?0fk86)V#5*0?7Fi^s^WIO@6xWW~bUaZ01Phpgq2D)m( z4$Mnslvx2X#h&pl+#t3wO zhYMJ)hEYZZbYF=(V?N~i3Qafg^%WLU3=B6IWwwKoo;M?C&-^V$1~wKCPEa!23%cEi zMF&)>g5s-Q2AXL&8F<9%l^GbgeHcM8z?uO%30rrX3^KS z<7)lE(Zrzw>M{j@*i0OtaXFqq5SxYLx&!D$T~MU6aRi%#&eH{TCwVwPBU(HmwxBcE zE>aS^K%1TY5}s1k5TS3=m7C3P!d*SlsgVO{yG}O zQD>9`r8=HiP@>adl$!=R1w0NUqsb_j2Rd#y9wej1D0i5hfq^F-B%{qJCjmO^Hy6aw zVUz=n74Z~+hKg8p8RgbY7q@g(W8630&eBz`{x#^xRnQG@9FS>}5 zXJFvCZ4J8U0>otCnCt?&=pq3$hrwYCI&QcFlo|y%Knrkrx2y|k2A4oic;~40C)%pn_i5QM9&}qaIK@v3_4?rigPX>uMaDb++d8UBG z7jP(pG*1JGFX7O!VqoBz4iZ1Y(G5C7dlpFi1V=L{6la6PUvNwVov1tyG@|#0!vr)V zGan@Wg#$Fk&9exk{)b#W=tyRs#UKd@MmbPVlxHa@4rLhSj)TrRUkQ>?V3ZTI1zmIj zifI)_xs{+Zq1S`vfwUOqKut29ji45p5u+RvD6%(!+GI(La-bmro_(NhP!XdXXykxr zKWNmWm{D#m$cG0&@m5~~O1(Xx;d{_-Ob`ag0}}%q3uvUC6?DT6&tcHEQg$AmD~mvp zkq?UKtDp*;fdkZ$=D7)S7YhUHMv(2d8bMPoB|LXNfz+M^9ngIjq86<09*E7t(FqF6 z$2_3Z-Z(foG^fW|yNauQ0iBWka;-cA1FIY8?DmhK^dk$p?&7>60|UooN6>W_$SxXg3l2W^+-;RDOK@NahpUuFR+ z4L$h52b>FlWqkPUK&}u3mvI67ph}iU1Y9(R@XLZutQKVid7^|LR9*9kfgMu852~+u z#6g^ThARFTkOw6guYxbL_zya^Uy^YdX`#UuFU* zjAg+*9)6i}P*#xxmxO%$G6kUH(jmnqe z4|Kytz7hiie>^CqE&+!L1OGzM-5X2692R~qP+Ttqb2tPFigTxLwslph2kn&SS;q*{ zE686As=d~OIqHyBNImEjXOP{Z3_L49ho*02{0qDA!W-$r3s44N;I{?Yx1ABh5#Zkq zI@Em!n4`e|5yaUA<{0p2gWR|q%&B((_rH1eGJ^Ww0sNr;H_twB$VPy>t~~p}oG5U= zm*)UDuwuYHVxEIwPAq>bC=w5WIdS~vb_@(Whryh9a7UQuDA>yh{98c9`!O&lg@Gp< zR2Cg)tnY^1i}4tA7OE8}6PyB9>J0pQKpno*jG)F68^1az;Lm_L?EIj$gGhTrXT-5{RxKE5AHUob>=wgY_j32<)XGDTZ z>Mx9-W*Gf(m$0#$jXmsK@}BIb&0UHcXfpcxDp( z0lJuw2QqQS2fFCu3&_+=P?0v13B+dL&jw|HSxlgQupGY=$eh{Wz|r6b9fHg=7tGP( z{{*V4=7Bjn{BuCH>wGXrj~`roEo3TFV_-1g2OZ(Zvk2tGdIm!VE|94#pkw7hg#{A> zj~%EkUCh)3yZgcfbT+RJ=n9JEOdvJ`|4~rHtpIxqGNml%kEuB%`WISx8GKqOrSGzM_Y05k?rtj@qt&m!_!3^WMv3N$m#02w^s+0JxM zoq<6loF6oq@mB^kalZg`*RIGlE|A7opfL{-(3t|PA}} zNI9sIX5e`QYP1~zJCsj>=K@nC=%8?WPz+rJd7q&kG84jc2|P>42r63{crJs(i~~I1 z!E*(yjti1kuQGx1Di1$6uU=yUX<0Aa{j;Hu%Es3IU}m27WGE1_qv=OdyFc8GTSY?-$dA z=?X5cO7&@=jQWphGvuz2Z=lTbpXrD;_^uGpARrG5GpJzlVUaljDsNbsZ)t4YjGKH#&=@|W&AhdGOeK2tvfR)iT@Foxj0?W%~iVo8YrQ9fqlUuA)^6u zn>RRUR3v1&K@AZfuwiNvGC82DfP9(Rbifyi7=hYRe#~MZo|H@=NTokBsCIdwEE5It zQvkD?4){WmX`lnAgP1|B&kxEnpzQ)Y!OWoQ;hVCIT|FoVhk~v6sVoD!?3O1C%=@J* z1DZkR2?z6jE6WIj;wb{`>p#je&q2j%B$)SCS*8zksY(6Aii`wka55IGQb0vUfFBg23Cy68Xc-j-E>JfIl$zm<>tJpM1};z$1xm+I zQ7$WW1_n@)fboB6GcbTKm=7w)ML_eJETH0>3sj_o!U!zK&cFo{1ceKf&sNU@x>o_* zzqA2e+5jpESr~YJf!cLR%!L{Z46G?GpbJGnl@Kdv8w@XaB#@npw`IK!0|N(WoRPN^ zB+I}d23o?{4PrBLT+jzyC<0&!rv6-Y>l!`=dP(FjPX3Mb^Ek@eHpc(}^Ce+J!|u?Qq##BmYSrCj`gnSsHCBgF%B z(FjPh3j^yTkZYIj(qUj=&C>>5Gy)Q5?Q{cOG}5EXz#zD6x`3yveEmx)1_o9KXV66> z1)%dbdqIYrKMqm>x=s}`fC6GMu(5!A!)gg?6JG-C4yu^IS5^L@NZjG%QmEc_2Z z5vj}wx~YPLe+%f^78OQ5P_vF-1azl|Dx-)#_@a^TAm6JoN`bD%;9ud+z`(1{sGtwJ zXk-}=1L&d=HGKvK8U6{Nl%>h2qYt`hWDh75v>1)_85mUf`#`t7Xfs;qGcaf{u(33P z*H113lN-S#=!63{mb+l~3or=^FE$oFJy+0BiX`Zg4HkPa84k*z3~bXav-F;19M183$U+%OG+SbR36Bv<;~3 za1XqwEgO7q2`C;}8CWlXhHj#G3>X;LEBNO*8Zt0&bb{_pm=DT!3>*{fKo^aG*o++M zAbS>q*r4-^K^KjH*vuTd;tUM@9E(957LIGv1$76s!cLMh=eO(;a+V#icUM zK=+J*gt$3^K+}fnKx`fkPVMQ1KCWW*$4nU*_&0&dKM{_tHVh2>n?Y;^4gqJ-MI#`# z4##D+`XtuAqxXK?ZurT0!0b4JPqF2id{ESpdFh1e6Jx zIDUX`DtHNEvv5K#8nM#{Uo^sc3}pHTA43KP#lJ?7i$-FM85qFJFZq9hP2vC*oczB) z(Z#~y3A)qZ4@5~A=;DaKAT|%j6Oilwm6?Jr8o2|ycLFjRAi}>AwB(Ty+~W}A2i@_+ z&kXLkOYqOP1g-gCWvnp;T{OZ0nzCYJG-PC8u;Jecx}Sj;oR)0)V?lRK@PRpY{P#hT z!w=@z^MlGCeqk`jf&VpVF|{ZosK{{PzXn?ACB|5$3%Yw`4ydy%4wjj~-w&E!mIRN1 z-l*r#(F9*U0`lh*eiIhZH9}ygKI7MxWMJTzW%STtV0ghF4ALaW7_7s<@RI*7$lLN@ z&MW>%&{{_&Mo@lv&2Q|)z`(D}2ue|3Wb|3VcaMMqJ%>>y26WqqD%k8iMj6oF6n-_v zdQkc)V3g4S-7BLG9#tr0lqmxRr3RQ+#3)k<>Z|I4{aDN>V+IOZ1F&2Pqs%02@ZBRI zE6NyUgh9OkGq4pEpz3UbAp?WbLmdXl-6No=;RmOWD6n=0ejZNH)gjT0pp3)9|6w|x zzpJFiYfykBFzzq~-9&O86emfHn@m9?IhR0LBpDoc7W@mQ`}@19ij{*dzsLYPE`h%X zl)y6?`OKzw`Mb)QUItBU<$|4)!_N$ITRxbR$Da%evjQ-ufL{uf1&Y8D+r^@0T@7-ft=t^LVh z??^GqID<0pRIr>3qm0k=%>k~O^`ISZ{PP(NKsReJ${2&X=nKFaJU~I7WDF`@L0OTf z6%@GUjG#yWUoip-MENwmBv9qY#sWG? zg^k40K}WajRAXeA9vS4yo%;>0W+zBZGRRuxP*(;9#?vsvK>JY`=YWooPysvdG)N(6 zABCz4J4hX<$;%kbpe6u1?c|CGhzl~s12k1SXRopp6piK?Z4qrqURrML~{G0y{$9f`LH??Dl9;kmDJHbQPwz1iQ*vo(3IV!Y&TV z_8{e;O}vbA(m*$QfKNSz$ed$jV9)_Omt7p>T*hF1hv~P2U6qXosmK1B0;v0|P_m^o3cjV$n*2mRAv&L&J*gY#SfO50+sm-m5B;<)#3ul7%MTtUAiRHRl6Q!F4(2g z3??A=XcvN_YCULy0RuZIZs)wQhK2BYuqzpZAZ}a__RSe41_ndWbtr$VVGcBNW?*1A z!oa{V)tZ4p-v*S-_pyUka4}5`FbV~2HQmd=UX{>DmePSfVw=%U8o(g&`gT^-ZBsz!B~$0tpAu zy3NeJ3=CJH${oU8Wt@LlfK6vAVgMOm3_6PpGy?|m05~K>8B9QaRx1G=wI~Hnil8`K z15R(}Z9s7}eSWyBEMxriz2UCX5}@uOqbyimBr^kpCO8SpiN2ctA>36;^1cl$ToB0x z>?}xfaR_%6pB@n5%2p3j2)18@!31QBnha?B_-AmL53*kgeD6vR=z0opru)p8s=>f; zg_(gtofWiQ`ZFWwo|&&8KKRu1&)_0XgoS}Y9ke!#@e8<&Hf3R8&;TcE2%j-b2Q)y= z_+|Rl2v<4ASJS^lxN11|g3em}1-9CPm4QJYoG5>T`Aic7!0|oD9_}yD7HCl70-Zg? z019qCJ4oylMY<}p*6w9s(3?Ih(p4JF^qam5#O&D1z>qurR-~&GB&M!FBX*_T^u)8S zV$&s~T*dt-?qy&&X$Og|5^ktQsGhCuzn<^Zv+Fxpinc+Or12BRJZ28I=TVW|zI7i^6Hg9*q$ zHPF3UjCVyraR`cSP|?CTr^11OK^-*6$aq&2G_q02%D`X@I+kL~^as(d25F$p*^m;X zm=#ol%wlC=PzNmwWGn`+YjtB|V9=3uVPIe^2JdTP4AI;VIxV9VEL+6Jz@Q0Qzsgt! zULiUOboUR)VsN;DiWyL3syIS?(jDWf0EsKmWhWq+XvgV-HcVpEFT}VC)$a#IGh-A} z2|QP+y$79^w;Eiog1iK&Yz{cW3cc0hASYjAV_?uKU|?J;4w4Z7T@(cB?3{ucSEQf^ zzF~!djRiD*p>_;Ze}#jq7Lb{sXknc5%aNfTT9Sr~fDH9wXJ9Y_)xFn10j~BKw86eX z3{>iZG=VmVG0s^8x>pG_cgWZv2AX@%W@li~0ZkJ#Hi&`778!%pK{E-Ajba~E85ov= zWFtW#*(e4YpkxfSD2PvGU~CoxnZp<+2U^O-@Nh2!Ly;3C!Ez`vm>M!LFn|iSiPQhZ zx=Pi*0edQ%sf+>C+5nB3sxg8Nuabg04YaL@an4I;1_pJo)1<&oyUPyCv{K-@h%s0P zv}&9YqK`2Il7*$kKxH6fs19hflo84cgLpy)K3bAxU?0DCLO8R{(s22;=;Mv%8^pkhUg;Jg2YJo0J1OHpyND)EfY8H8Tbs zR`7lLfp}L1&|dO*R}nRJSD3bHu(s_WZJ=Qu##*p8(A1@-!F1^aS7pYV)9n*n6(I?F z8q}F$uG2T3a21>0n&2u?{}1fuDDcHOYMh`0sMF!e4zx>`aZV!Kx^%F0pE(&AKr0U! znD>Fg3Uo0LgPI;SQ_MZ;OHQ3S$r?)!&AudY!K64-#EPbiwI5R4b{Ff$_c=NRuBI1A_(l z=DP=Cph#d0Hv?S>1=@^#f4X9ls|4e@=~hXu()Cgh?}M+L0y|rE9|MCaXd1_09|Hrs zJ1B6Xm`Xv3hN+AJRGynL7=v1!)?kfMV2x}nppLy&5$J&Id$62)7wm&g9t;dBpFn4i z-vcolxEL6$K~7Hf*C(pGLDhgX5_K-8@O7mjiJ7#NOug2E7-so-^{F=zub zG(d7wT?OhpK#k=%xUHZI;27u3@Pd_zabR0P_gX`2h42}JA;~zN5nOnOK-`cBc0(i& z0|U4q134kZ3*iJ?Xtiw|04)JPt$l7^}`Bx$s!xvI-$ zfzlVKNepTjIC;YzW(>Mwu4MYDG*@M|b08}trhiUzRfMD;Q1n5A%Ou@Z&&b_}fkFKz z=pgNN;4s_C1G>A(m4PAL2c7|7wK{T7WmUSX3NJ_vIKjyFc23`!;VR7q>i9|WGB9YKo_;R_=3~%FF;E}NXSy1x z_4~p4W*@+licKI5+t?Tw7(X$A3|Ii-pPpWx2`k`19ad1_`}s|G%yAW)u8`>}H2r+0 zD;p$4K^Ylp{?|-b*;pP>vgZdEyOY2rj<-JpgF#YCA_F5ocq1Yw9|Hp+CzY*)1?qd<_XDgy(fH5f~zwToP(d>I&QbLYyU=rW%NPT zf%c~M?qgtJuxAEkff?Wx@1Ot!-Rs6U=j8PNIj#hpdbc? zgfXa8IvE7FnZZU1R5HkdT@Nw?)Fxn@lM%wepl%Ji{0kzJA;Q3*BajU0oy)R=8zR9v zY!1^K@?E_cJExz{cQs@)3k3zmbfyAVeP?iDjs=GRV<@C^9>)$UC9aAwFgSvopc)E_ zE(XSAc2H!2R!$g!3Jh=<Ni`H-Hl9Xm4v1LI+EsDg@5#yO?o3=BGJRKTL(_znUW zFUP?;qnSAVgNisa1_s+{pdP|wu+BVi4*wsHl-x`?K_y6x4+F#L=?cZJMv$@}5yABn zI6zK;-`r@|1?u_#0~-g@$vDR)0+g&kk^YYhl*3Ml!wO3VZct=nD=fEy+zq;woq=I9 z*iC7XpvsGZ(UJ#b#7npl*7`hPGlKQOZ7Uld(3%3Ki2?ecC1Z@XJgJ~_WhRD!j;H{w z2xd4mU7^HPm+`@LzY;FUQ)sNm`W)jSNKfM%Sd6wAP%13Ddn zu}2s*@XZ*c4qERI<>l5(!D^L0VUTb8K>P~O4VnGIAg${_z6UKa1BJ0fEXY$)Y(yQ`^?Cb5VBI@V8#yPwR4A6m~O<>naNki*A*#ube3+|DE0~XdKzct;k z($xTx*g)k5D6t8~K@wYQrK_+qXedB64(t`saDdSPXp_VgHfk9YH+`WIlb9(NNDZt2 zG5yKFz;MiwfuR6ND`*iu*m5^U2Jl$va;QbpRj$IypaG2CNUA|y53p*`AzdJ6F~v_0 zta7!0xb-L02&Z_6Th~^($|z~XGBAY2gWLfci(@bX-EIvw0yLWdGNNz#>nc|*WzZ1I zBB;6|1_q;2Cg^x+FB8OJH{+*oEO!-~?pN(91Su*vf@C0dVMDd6NCYTM!A$^31`|-g z+kkd^Fv@_(5Sq28vC`JYb(AeSi1V|9T z2l-8N7#SEO_A@YiM3E_FU@&Ti4iy{EfCeb2!2{_9&Zu#fRR-1hPKhw{7(k1|Aj4a* zd|a6biGa5?uELD7rZd*UMoK{k41&V^B2DE~ zhyp0cz>y@#U~)H!fx-SRXb|%)J1pNQfyNN#T+9YV()0;+u4Z1KX@y8R*dW4tcF^!= z6^IWW{`|lW>N(7mgOviGz%8pCAU=5F<1@Hz^$^70G+m(HRi3e8xUK2Jq|y> zZPuIe3=Ep!Ifb8KzN`WRg9~`*^%s~AnNb3{337`vIPR}y!{Z**FkPO)z@P~}=sbc0 zRDRegFfbVDFfuTJ+e-e>CBLxZc$pl6^p<86c^zDUd)9ZgADK1(n&H zsgSrXXJ9am10Az&&cL7y6)Ob~Zbg z26209qpP6=NXBR@BLf4tFLV>Cq!+5>aigmt#Ct5D+`5;6;ZoZ4jh9`;rdu|-D%6AK zzTTukyjKkNN+|<_sV@@)Ll9_aEFC7pU>eKBzyO-J7C{m#WMW_dO;KwgiPb>W*&vC{ zgqjzCB(?&iuHKA+Aq7cr8`QuGB(bAR3=E*D>q&4iP<>Xyz+id>s(Kk*hQSoHm<*)) z09*{F`W4g>SKu-Xru9FdM!Y~0WMPI_$dm!|J z5;KLG8UYv6V~kd20{J75nSlW`fu94HVldys%)r1@#4sTPnrsAGT-hP<7{LN5kMCtb z5`lFKY?gNeR7NioBGcL8s-p~=m3PX7_@sn^!RRRqv|MLog_zR-RsFUFHuq)VSbniaS5oLYGH+%F%zm%E(>B~PphjevvU?gS}_3;_Gdt+rMh#%%0Ukhch0dQa5-4n?kX<`E}+~wL4}LD zA_IeZ{PdOWuJY#K%F2@yR4TS9GBD_XOGQskP^ri?5jra5%?WB6T~>t62K#Wnn*P7t zRlI(a1Oo%3A1A0?by^8l==p=~fE0Ql2Ot%Cr;Ff)9%yPPJ{MN#?F8!)Rc2r?y2K1E z^u94e15OB`y24 zg6IUbc1*$JuQm(}kEgqJx~em==S|P=bd`q~0IT4F^B_^Qsnb=%5mee`)w6qT{fJ|TP?{<}jMA1#C%;W-a8+H1BxC{?7 zBqv@jfJB~M4{S2T0V*S0INdPBRcv~FkE=B63MU4Jfa&vlT&T#>1mfx)N= zn(U0GFheV)wNUM+3n2z;_PT2Fft|Sonlgo^9|TpEWxcM-8lW7lQv~x9C|E${)?HY+ z1v(oAltw3jw1k24@{;K?eXhFfpf;xoZ^HC|K35Um3&o(eAZSW}OyAFQoxB8=WC?V1I!!9N5vYS)Jx$hijM)b?~`$kM=5Bc0W>+hK@>FeAE?a00GYer1m+ubD?{gMK`J3WgikgYfxHTC z9>Cf-nI#aXpX+y3QU-ep)P@2nX)A%a1=J00g*HPEmq6x0H7B?#It7BlXDb5(L(F~# zhNp1VpdlUu1|!g!!wc;h7>q!9`~s*Wah!pHAp@ibDtgGJ>^I6QBlYl|$_8oaCyZaTStk7>yVpi^%MpKqiM3M9wfA2 zNhYBJ;_@q#U4=D3;~A9|kkA5kz(6DNMk`_M92GR0LG+{Zcs*TP@~I@uW< zwxH9eLD~N|RCWFoS7Ccl(C}4)Enu`{Ftq`VBkpHlP=W}7Yb_r}1_qEaQ-~O&0fQ-M zNf2mW#DDt1DXyZ5pjA0ZP+3C;qaU!y;DQ#IGp9RRF^Ns*o$4yA2r_96RIL$%kq)f0 zYzI~Qc)H_MS4}&RvTtx@rU6V048EnHb85g&Wde67m>}+wtpbZN8Zel*fJXL;7#yds znChya1TrH8Drw1Jv=nC55vWx&svsf#f2ylOJ;*zoz=}a#2T(RDVPG)+$i%>K44k(> zLqw1g6(m;*y8WgZv>3({JgONE9_Ev+h9wAZ@R0RsRR#tlP;UU#?=^L0fVfw%8s=VI z(1azZi)_Ha%wTh4`od|hB95DDKuJ-Rfq}6DJau&sp31tw^GFhE42UHR;Bg>u!U8Q^ z1;y@?>gf+nn8c>@Om~&H2HCpBn4}Ra7^Dg-BoOQ&2(2` zrHlI+7-VX|js}@x1e!Skrzp^{7|6~jkYa;+P$n{UVPs$cEw-wGY5=cdVsvIO1ueA$ zm0VMy5}@Q94N6R)vFp4085mZ=B^ZoK85tN}fQGm1{)48&^TB}(>OnHj@u`IjiROa` zj(yZ%Gf#!8;InP=LBRu>ivYP0JTnds9$5R#WP0FCSF!1{XSgabo}a#FhO0{b^?K04 zKhR8Ej?jJ<1_sc+Qm1>M&U~H_NDeY0nGYV3T&%{x-~t*%VJr~>&#UQ&f~Jehg+OPA zfL3LKZ3eAm(1M02c#H$=1W;syLW`je9F(xOYOdQkGXSynAf&$Q}pMim4H>lK~ z4oxqrQ1u23=Ag=hsffX8`i7aVl8njIPt9~ysQt3255d>1s0D2)!v|Dmj|Rr1S)q7A*Tz=%>~e+m8Bll{c<); zoYRYDxk|Ev;$3$7gjud4+Mv8=099zfUN2Vf%g!<_lXS#~8fljJ# zte<{*rmK{!(RHYuMlWDZ+CNaskJm%;tm$l5Nj{K?knF?2#$q!)X11%Om|Y{R!ZQ;C zbsY|Z63G7P-LqYd~u*5n_Dv99NloQ2WTR z5o|nUl^>%agDz;REodwmv|s_eUeZ1dG$*=*8P>0wz{0@5IH#ozRy-_W1`Pu41RX~W z9`RWMK6N)-gMmRET!k$KS78+(KDY{73RXW&gTa^qQj0AG*J4{WV1?Fla4q&8#0Rfs zTmiP4SCfH3bLsTJxvt7Opuxd5O$G)>(85KLCU7msz`%G9yk~VOXz3>CR5$Rjq2BZb zb6rItRU4?^0}A8fCP*OMoC{k{&;Sjd4Nw`md9IR>8WS|_49+%(ph~_$m88srPSS8S zLqZVLRC)mm@4ryhj?IuEq;2zDg&>abfTo~|W=Ko??L1c@If(-d3=`qzfSNf545kyH zlWm)(%g%?cI=VF7ZoaE@fXV>|hBr{q`axxMTOq48W-oA+)Bz2oJGMfc3L3L2V20F7ArLV}BL>qdW=JD7 zclv_`uod82p=Paag}7Q`p{rCq*wq)A85r)?GccTh7y#~4{)8HO8zRPN$Y9FK!oXm2 zfPvvBLS0aT`qW?+=(ssJ!-RkjW@Ze5 zwD>~6Y8gXyz%9NI7B2DWDT`dySv?LgFsMwQu*g-K(RuosMXr_^FW}}EgY}4MF)-+W zO)Q3(7z{BHBFh*8F|n8h)P`gX)dXkWQm{+RwV=zZLJlx69Bl`O1gOdd?fYSHp6Q( zW7dzA(*r%3#HK%3?5a=?YJ5)W068L>2{b?iYJ8f4R`-G8X(?DD3e;!>HF-fTjhzr7 zP?yhi3j+fKsA9SV7XxK3Lk43|?+zpZD(XOng6b>=yN93)86Sf^^%>lha_nLdhWhF; z*jHUzph%oPX^E?P{hUr%k@X(zCnIeJ22;@VGsqS3ogf#3Iu{J4y`Y&!2L^@;s2DiU zGMX}&&R}3*0JYY7pc2Il491|DeUQ(fH45%PVrF>R3CRNiOI;P5K*7Y+1+o+=m_WNW zK!%BdC89tJl}$m*6+tz#7E}ymDQGP~!t_l`U6sWwx?%BH0A57nstsE0GyU~aS8a8W z9JJ;Fw=h7<;6cSLI9I^BreC@sxjcB8t42M@a`tYJtH5ytn$`u?@X`<=P#hV9)=T9a z04o8$Gy=9)848zfu{HbY34fx!smOi;0B1iFm_R5BZb zN^R)$zyAtXZE=vGQ4j-k2nRIV4GIgV=@VDDS}1|W1jBkEfezY`(*~=#)AuS@l5@z|57d8jwn_5GvEr2T8C`SGsC} zJCzIjU`~Kc${U@9Hn~he*Uf<3`vR)PXO*im#4smly`|9)F>LZGSDE^X0}KpK{RqQA zd4Rzbbb36)eg=jxxD11-EHeWGD6izh#UNIjx-5GLS_m&5CG&#riW0+xUP0ph6D>}%odz4ETFZ8-2{kxr>=H2hy%5VL1oXx00zjq zZaXnhA`%0y*7yQ0dqO8d(w!K1Ifj8QEMZCTf*O>iy0AqUlDwePx|t>hfYS{qUml&V zyv9|x{_zA@%SekCw8rN?XcP&&9tjlt-zUIAiveDma!mw_F;pp*d$ zLv@H8XpGBrDzpRV02hOVq4OuuHcC*JDvHr?`uR1kob}*~&?CU!It2;sv!hv-M!!jOGO$0M0zIpYeel18ncxE{k z94t%p85qn!D;Ys6`oB+Pm>#~?RUHx`8L+GXYDa@2EpXCw@Pzo9wXQlQpfWpc64?77 zI~Ytshcxg{Jbb9$Ytus^8K%$f{#3#ejagpM%OLWN8j%tb&W z48;u7AtI1A49JBHMn34xyDLzWoz}ZbvVz(O@24lMcNJp;)z|z}rq`@@m8u8Tgql;p z7J^Ix)sY4arl1)LLBxPvBTgGk~Rn&%B^gwI9T< zRAXRZ{K5+=ML{PcnQ<^cE&=>HJ$QqwrV7ZVTvMTbm{8Av=v#r-`-8&RV=A;Uz5&*{ z2QAG6=TX=Y)|{!32>P?ZRUKSatcRG$XvJU(O4}v-85oX(g&>2RpjIjysNKDff#D%U z9OM^BLNO9#WMBvc^`SxA`%CsRFmO$SyAM>9fO>17){JEsBLjm1M2^uy540_ALOnx@ zaUFCJ15{9eG8HJa8SFr}%QBjS_Ea%I3W}@KA%SZSUY%uY$iM)}A(mi%h9NAlt@uF4 z@iR~SPzMQXYd!{@>1>-^wHPl?H{1kUodp`40fm;tbVyLtZE{tV0tK$_bg1J$)G?TX zDs7OD{HE{RB+P*bF`9$D2QmUQBIwu!x;Ri{ zv#U}ls969`K_BWE7_<#QduJFxL%+C)P|G}I2G|RrwyY7T#|^3?!7VnB>h2j35C7lnD$EM<#k}d_ zTU;#}t)>TVaTTf8(qmv?j0Z15+XuHh5xNLXUl6o>EeR|OY7v0#vGt zB0K;Z%$;z6fx*ZNR(FF+Rgh0kP8Znf>HsPAKqG13Bn}F0kfg~hh&OAuy4pc1R1RqA zR1KB6ztvS4-0Ge(3uGJ8_#9|C1}J1KL4##G!LslHNi|TLt;B}Gw1km?Va@>th8s|M z&~i>tbqvZB1`Os`L0fu?7`{Pe!HsXGat6?-kQIZ`b7+ytW(+Fzpv{@N+guewKwD_- z%0U;z92W#FM%o3gP2A=&FsOs;gX4mrafm=;P%<%RU|@vsmw@=IL939DgCpmjF)Z1f z6lBnuF1X!QG_)SHPV%%Ms9-TPfwsoN=D{KZyx2Dy&INBf0o9*RXM+L<7_mo zqH6X|SEG7RP=Q;}vJ57m=l~OTOF;vY&p>N4q0Q*ii(oPJ47|oN+6301c>x~NY&T(G zfQ)y(1dn&RYy|BLeFHvVo<;ufSA2!0HIe&Vh6DVSKxyna^BEe}sC=x)?2uh!34B##!Xy7vp zF2P_5>PCUa-?I>6-~mps9iYAw*bb2WpfKDp9}+rpyImzAIZP9p!=BHFOys~12VF2BcB*bkHt_d#@kEMtXEL0p0e zfh_|aiv|kA*KjdN7#gL(5=;d&!6;2{*yE~c1`0#aeh5f~#$dVt+OqLn2=+5*cnWkD zDJWP?L92K`q1m?(;;1isTorXd5wi%Q80-Q?Xq$a2L<}^p47y_imaZWPGAnw48o+pQ~j34bVJdBe+EXniOH2 zW4MHYK^?s0w~-IDG$k9ZubB^2S@xJRFc^Who$m(~0?G^w3?POnXg(F>_I-;X(P7A7 z3hFX~bAP0k{p-n;cIY?*=SO`)y zfh544c~FgS3TmT)nq(K@Dj1AF)7+qpV+6Vy7F-^|=EaPsUpxrf1bxue6f!6PntB1N zkbq|Vc905NJy1_(`7)3@qL@l;KrK{I?Ht3z;lN-7TAvCs-V{{zgM4rgq(^Le&>>f0 z#$VIZ4!O#?%PfcJ1-Dh1CI;v+#;`I^0X2e5!GqJF&5>XwNOc~lL(20cY%r)kjMR3LL74Vh^sKTwVI5i zS_@YG*g(slSt}ufEc{1Zg(N_(T?_*2G+zVn1XgEfC{`N zt3hD|%8v|2pk@XrK#f4t>EOHs8&zOi!!Ui5GLy*kh~uuNkTy7IObx8&D0B=hY7Hc+ zcO7?CPXZP4d20|xe`jD|05utn6hTYhL4gUHvj)|(Goh+rTUbmhpk2>RXc9)CUNI)SHK+%rirjTD2Q!$0hUP#CtQ#(dl)y|u z*EfT_xCBMkl))5qKoQ8O9dHQ-W6%}9AfrGD3=|eIpfmrpD?!WZoxm%&A{ZDv7#Qbd zt!H4+VFk_5JBfn2po~G_z5z%WGH?so1m!6T8n`O3Kw2LGFZKi1L%az(C8!?UIt4k# zIE(?3TVRPBv=GiN!Ht1|F$=WwhQS@2xQ}gu)#_RNpjy2TboLcEsb}$ns;TuLei!H% z1qlBGJZb0fgKB-oP)*R0-;8_)U|;}cgbhfB+QWK5p!5$)3ePt{LNEG^tFW^cD0ntPoCTUti2)Q?5j2SpPTjDD^vTmVo^iD_1EubAh;mTDYznG~Kxw!eA!Y}Q0FNy7~O@X_)kz1!ZtxhqfVc7 z6{-gnwOKIL3=F2C%nS^mrHyqkF$D%w9cD-(nFA98E%#@H7OAG7!Cz2X+5nejFm{FN z03~d25P=dlWJ)C(w7FLfJia2w#=yeBIHzWM!Z}wJND`J40Hr5y&~aw+pyP!g{2VJ- zGe|*zL1+5fbFSj~T%hKYk^rczd<>G_4(gRF3xEV1&5-!_EOeEao^alk1ya0%ws?Vy zSJ03xNS*r@$lUs*^R6}!C7`8?U?sfJ7SF0J(;Z`(#HRl_?`j$k+OoQD3)}_ZZLXm5 z_BvP$sqx?h?Sz?jLJQts5EaZ5LtsbcY=$LT(6Qej#~5yfRMg8ZxC&*0#t%KWf^34e ze+?K+8K9k@7_fL0Xcn4>2{K1r4H1GEkEonM3x~mLm{6q+8B8Of&7O7B6)(a%KTDtq z?#)(6=tW+1l>)aI{zJ5bEW8A@PCGG!d#~4OEH3C0Ai_P<^x?Y$#~4kNFlzlj_Oz{7bGfT;`#W#s%kgPzy^T z3{)PgZwI*m)b;=s?G}*2(R3LLBpbM)$bzx~cy{v$wBZs3mu4{k12Ma9JE%P*HSMx1 zE4cGL5uyaN_)CZtveIA`M2M*rdPRtG0+~1Uk4Z%u0th2O94S! z4%iMdFuaC|u`!s&fUc%L$iN`I1L7I50Zh|9cewJ&=`qHEmS4p)8ZsC?gf)qNLYqWE z(>Gjp)eK0EWnf5y>IJoiWY{3yN6piqjbL^rpb{|`l%*K#z%xiIT@cQG)igLC;j zF;Fhw2{IKt0W%NMR}0p+2OYAqKn%LwS@R62h*$`A0;3JIYXmX{V!zoU1_lODEjxQB zXwyFEjD_uDpe}=i8|WArBR^Qp0-8Do<)=r}4X(OcLh6)R(DszlE=W@Bz3M6xehoUe z44zs8dtxSN=vESR1_J}AZ^bz0&MsI7Qxbe!6SO7=2}4{3pG`IeEuaHgyL#F+S0g>p zDR-xLfn$=n=m@B40k0fk;>chy25n%JI|!BojZH9^Jf5C#%~djO(r(yUBL?E2(SS%B zSTSl0wtO;({~WY&)&zX2)G|;Yf%ZaxG(wyMKi0u-H{5(9&{9iq#DPY#p(CYVuemBn zgN})^nFTsd!3S(0XgmSbCuW@UVY22K8jnCf+1*P-P)!%fO&hECW^v@+D)ijs?gGN#Y=tj3F)^ zAhjtVQ+QzhPZwvQxB(xI zsVz~EY`#lXOFl1ULH4)Oy716Z63RBzc#Uw6Y*T*r4W z%n2rHdl?wq%s`itx2Ll5L^Hedr&){TWPzDi#+dP+=GBAKJ?|&xu zWx@;$Ak1Fse#@PK;nwuEH(ed-8x0s3Kv+1~^DHj|0|*OVVDwzh&%gk}f{l!xprhA8 zSa1rX`%XRv1`rldbid}rzyQL66`mI@7#Kj9e*%-|ZX*T;5a#*C><$V65EhX1^i^bF z0AZfL%${3R85lsA=O1&uI|FDll_~>+V7I%Y9s>gi3pRT8^D;1iF#miePfpNn#~^%+ z)AObp0|N+imos{9P-b8NVg61gcPAqT1`uX1azDkvzyQMRzV6`;3=AO5p6hPo&cFb| zA}>8dR2djRm|ug*v%bWMfdPbhx|!V{i!m^Ou*eI~SNaSLAk44E{ zMt9H!pdc)mUhf&K&A1_lu3(Pi;$RApcQVU8e1&t8271`y^9;`EGAW?%qeE*>_|DRK-9Ak1}% z&9ha7fuU8Uo`FGd0i)*!a|Q+w7F^Hh*(A-t0K$SjjGkp;3=AO5)5YxRBh0`6!aP1^0VCa%5ltVV*{2_X(m53?R(jdz`hPcH=q1`y_mW%T^&#=ro=JWH58*NZSPfG}qym**~R1_lu3 znab=LD#yS8!aOgTr%(JSExP^S9oPG-c@k5~;!_e!6614H^QId_X^T#O8o(?x{k*8P z!1ik$Zj9`_#mR|z@kPZ2AQcSL6BXT6xBuyPtC~4IMax~3+0ejz`oZ<3!qdAn-36xB zhH$eO8XA~PZ?yFlWil|DUg#tt%wlL@VK%*RL#a5F1r;-e%bHAQY*7c`WQ_>3p@9)h$PA*K#n8ag z0u%xwOa_+I8)jOFF`1c9XWXI*a;LEw%qC+Kh)vAK1}58|=(zJJFj`Lk=;N-!WMME} z+}GWL$-;Dcps%|!lbO-<`TVY8(|df~c^NII|KI2)!xtZ)R+^U_AFl$k%y9YkhrdRv9M=@GX7o6uNIsLt#yQa6XfeAx=yj!TBbBL$EA6S>Mi7C2}sfh&x zlDTF^mgp)h4GpKS7jTuHUgz&F5M>536z&W&OgqdBKz1Nh7#X4)Xl7)DA!K5~F#Usw zyEKX)Els8i2Dm#hnHx+$Q{|>Gy)?jGk;%w#`h5Xc83QCon;M|{!4$+r@wmC6#dL)} zH?`?pf$qF2=IGX2n1O`gZniM9V3^)7=`J-rG|*im02Cr{IZHDXu7!~qa`0K0fV>7% zY-nHvG8fq;h6W~v)9(bj%LtkyYcw>lG@h>T+CgLbgsT$l?V3UE+ckqcR%=VvfesRR z1}@APKzCX)LfI>)zpeGKR{ew|{U3?V3mVviDpi{9TjwFpYl|f0IlZvXL)@?tNeFav zJIwGoNa8Dy*juLWtn+Y}f55c0Ac;>zV$VZj zubJLj@1b0O8%gK|68jqxn;X>1hI&^ViLH#p)<s@$wRrm4M}J+5_=&Mdo2?C5EA=568kO^ z`x6pdj341dZ6vk@gbkjUXK;mZz{w(bI%l(oa(xq$P(KoTE)sha5_>-q`z#Xs5fb|y z68jetn@s@WMj;3rl3YOpQ?MkY1(5)|(F}?0gv9nkVn-vf(~;P{NbGe;>?=s@*P#7V zFpIw6 zuh#-C0EHTEj>L9FVwWJX8*1vHhmsZTD!de}W|R5sCdDiLD5_ z`2=P(5<3BjorA=#Kw`Hbu@@q-w?NpCv~~c(0sHR^68i=c`w0^J0}}fW5}N}w_YQTa z4ieh}iS2^K4v;`fYcWU?8A$9BBsS<4I#{XDgCsr!iM<4gy#a~62Z?NS3XH?R z!0-Tx{RWB63F?(XeI|m$)<T z*e{USUy#@gprxBoNAn`FB@k>W24w_?0d%Gx%t4mZzjk>jOQs`9mmsk_rWTdjVls67>S*T#Lh=z*CMgIk=Qel*vpaFTannHi{lud zF@R#4fdO>q5zL48krcf}V*f^BbAravppF(tVyhytLC598%ydK&_eWwk$OI#5*d8Q_ z4M^-gNbD0x>?=rY(Dn5&%ic_9?e*ASzZ*2l3w7fOB=#F5HUsEjZKxU^B(?++TLp=2 zfW)>zVtXL5Lm+HOz$QRA;36akiCuxjZb4#CKw{59Vy{4AZ$V-oKw_UkV&9OPeyGnQ zuHFH3xenBWzDVqHBz6}Pdm0jZF%o+l68jJm`y3Mc783gzgbfLV&kznc5dI;tg+Sx4 zP{+w3v9*xcW=L!&B(@(CI|_-NhQuybm@YTLV^h5uXk-^^k24ZG5Q!a+#0Fhp21`uU zNaCGH?CD7CrAX|}NbG|UHl!*048j2i!l&tp6FtNkMW*LY^bnsuVWNkGBzS*3)Qw4? z0dFX~Vfw*|9@dQ4rhfz}6`AB=AZZA?D+elVhs5@o9y`e+TlFN8&^09X6D0PB>2D`_ z{AS`(oqlh!huE|!9tpNHL5oVDrY=KbA3$QCLt@`SVzW=5JH^9VH2|~$0%}Ao5<44- zT|WKq6p!HgTS!9Bk=U%DV+^21NFlM+k=WKq><}b&6cRfDiJgYT&VjI}pP%X>Ti*lW zfTLs*5_<*`dma*d2@-o15__P$}|sy zdVA2Wc4$cWAhDy6*x;S-P&J)M;?t1WOOV)`kk|*1*yoVgcOYy?&V2>pfF1V(iOmL@ zae-Pag2YxrVjCc_L06H(a+D8}coY&l1BqRxiPQpWL6Vq+#9oKQ-h;$Gg~Yyr#D0dv z{({720&NC@dPV@o2KiqO#sMA4h{U!+VtXL5K|6|JzDz+9FG6BBAhG+9*mIEBtF(|> zKs%5mK(~UzEVzOs{s@Wv0g3$&iOr*psA)lWX2Z+@-BAr=n<3QHGq@l)3_(cj1SB@- zMq!xd8YJ;9B=!s>_A(^4E$B#jXs~-Cu|vRYQ1~-2Frm#wpdtzlX$riNt0B%^gD>%8$gBLSmaDu^o`uK1l2cBzCSI!*uJ}9+{GlkObc& zvF)eto$X;=-vK&A3~KjOB=%w?_If1tE+qD8B=$ul_H`sS=t@^upgu+te+glOj-_W{ zcn{%#!ieE368kq2n+bFjEYzWrNNjl|wki@^8;NZ={q7tO@p?NXp+F>dED}2tiCv1s z2F-24{LzafJ`;((6p6hNiMe@NbEyM>~qs&=Xt!ZzX-Yl z6zax%NbEOA>|aQ14r7E9#gN!4NNgh{wgVE|4~d-&VNX9j-y@Ru41@y?@SD>O7kFH+ zKM&fh1$EaQB=##LHt1q!SlF?F&eVgd7eQhxA+ZgR*mg*4A0&1Zgbg|;i-92n!U4Oh z8Hqgui4B@_hdE;B^t}r`l`63rMGgrV#l zkT_It8HoJ|>?(#D5F0Aq24b^AJDXh~&Fm0GQ$Z3?Me{*ysOF_0HdK5)hz+{JgMooz zGe|F#y$>V~RdWKwhUz^BVnfAmfY{*86ATP@%u*N_grS`0APK0Vk03Tw^LG#%D$WSn zrU%|6%)r2E&cGlHWeb4Bp=zW+Y^Yv&5c}D5zr`Nn_26Z(3=B3PZBVv5SQ_H*AP^g> z4YV=?7Ec98;&n*uW)K@{WgmzQ)jI{mhKkPzvB6sp85rspgDi$})`29Tigtq7P|f>5 zY^eB25F09f9f^Gx#D=PQ0%C&??q^_l0Wu%T{tOa_s$m4(h#?G(X$24mDxnQxgVs?o zFfiy_Ffa&1*;XKNs2W!g8|nxz5F08Ufy7QnVi$qfpe;=d3=Cx;GokDr3sCbBYS2WG zBB(*LL2S^WQw$6Y3qWkBhLuR{-5@r2EfxdA5hV6mB=$8B8*0u^5F2VfizNdCBj{ud zP;t#+$-n@*ml_n~!XOE#A~_Hn>NsT(8!D~`VnfA^L2RhF9f%DTcLuSc;(j1DR6H2O zhKk2pf|`$@LvI)u7?MB|AQv$(Fk~aK8$oQSFT0S~labhSKy0Wv8$fKRIXjWq=Rs_! zIX4jOdWMGx4#O)D8*0!$5F2U`yA?FJ7#J8NL2Rf&N=R&NB(@2N4K*hY#D@Af6~vYY zg);*~rWFH&uskUIL8l;qB%q3#kl4K-HZ0DI`4lY<@zKf zA<&XZMyR%0kT}%JHY9dG5_=km4OKrMiM2WJO z#OswH0WWC7z#t4|%Yb&wLBmKL#D<2o6^IQL_dsHYA+ZxdY^eG)5F4t#5X6Rx*CVl` zT0k7AqCOD&6vRQGb&HHp2h9PAL)q&6U@^boHHtqlVm(**J# zlnq*k2rII=K)bV{?&1frp-zzkv7zGfAU0H73&e(s>x0-(aVroTD((wnL&fW(kvLgM z>{1XLs-X(RhH7X9v7zE!AU0HdDu@jgp9Nw=#g~HEQ1MkDHdK5kgbm3`he4d%kbpe_ zVnajXA`<&Khz$+c4@m5vNNgt19n(;A_(5!_Ir>O!e=vsRQ24N_B2S^;M=8!$8Cx`4!f24X`kevicd zfy8D6oxutdfK4|Oyr5?iPqiK7Z)LpAFmv0XrHsAgXz zb{G;n2E>NyEe5fnj;jN)^}#{S(B#O#APi;qg2bOOFn~*~86XbSXUmY-t3ho2>HpSx zi1UDson~NQxCSy~y5c$yiF&Apk03=*+20^G)Mhp(1_nmZJy@VS!krixgrRIvkT_J0 z0*DPYM-{||iW?)b?Lcg(8fOq2s-`|3#DN-GjKrRV#9j$vLp5vxu|bz4F)%Rf067TC zJ`56vsyPQ@LoIsBeDNN*pQUN4cb8lRU`&tLp4i-*idm(5F09P1!6+s}|0W;~RKgO(hH8!ju|bMJI}|`{ zE0Fsc7;-@tK-m=_aj2SR5F2Vv2Z#+7pA2F{#bwhAGl&fp-vMGn zExU!pevHKa31UM-j>#2KK64|n#X)SSIT|1~#1Zuj#vl%8n+5{|gSjgMgD{ls1QLfR zV(@6VnVTkxn5F2XfAtd$<5F6_Ihe+&KNbJubHq@M-AU4z-?RwCD8>s7yKy1*>*$fN} zW^N1&!cev&NF1uhABi1{#BK($p+1`iVng-Lf|>)mlzTBq9BR%w5c?4Wq!YLq#DQu! zkHmg}#D0my<^b)+fvT4Wv7v@)g4m$;Hv+Olk^!F7*arNs6n|%>}C)f8tgqt?5RlXc_22_oFyPO)SR_&c0B{bVGsvu z5O|*vlzkOR{2qu6HRuV54K?U35}OTlp*B>UABio2#MT3`q2`-|*!5731Be4H3=>4rp^E0|Ucd4+aKdDEkFS z9IEIuhz*UipCC3=oW+xYff01z2Ll5GhbIGrFqAC}5{Igh1F@lcb&%LbAoeqc>DpU8 zxavVCaxyS5ID*W8vV9=(;H(!8VnfYHMPg@z*id`QKy1+VDFz0HDv&u)b}L96s%8R+ z4K-&fhz%8wT8zY52Vz4NZ3eNS1|3IYUqE6%0WKXyHdOp968koY?FA`h7@j~lAkQ=W z0IM)SD&7ZTLp4lCVy^_Tp$^@I#NLg>J`Z9;&AA3*gKm&vU|_ffas-GCs^p)7B%q2u zfY?w+d3qC3=Awj3=E7Q%?u0-yhv<$5F6?s4J5W9659&IhME)W1FGbq z7G!`VK)WFs7#MPV7#M`1>~fGeR813z4Ru^Qhz%8=io{-w#NLm@K8wV@17btWuV+y7 zMWl8e5ZfOTPX@jW48l;hHAoz4nHz`=b%ZyF4HXXqv7zG8AU0Gy4aA0ummsk#L2Q3e z_%kptG=Vt~i>H9t&|sX4#9oHP-UVVqEjS8dgRXXDU|={2ax|2EA0!U7_z8#&RsSBu zhKhfw2XUYh|3Pf11g{?h10$3z1Y$!Cl}2J4g4j@pS|PEWk=XtqHdJo}5<3gT7Kc{y z#ZV5&|20VL2_QDqannKUK#&RshS`1$48l(gshz&Jo1rmE7hz-?y62uOMgjxMrki}5W z4Uhy>(PI!BYUm3P8!G+{#D=P84?yG*J`fvp4h91QgHQkigD{jW3lfLw)kb1lg4iL@ zf;Je$fhvjuu|d~$fVMz`41%&VLE=y~V9b^Y$he3kWDUg9d7|Qkqi9^*yfY?yS#e&!% zHPa{V^$@8C-CzTnZ2;+nvKv7vpgMa%Y^ctOAU0Hd4u}mEUxmcpfyCYmVnfxR0I{L! zuOYGPpCNHxgV<0F-#~1rhTkAIRGcjcQ4DZ{*r1y>7#J7?Ky0WQX%HK#R{_L^dQ2sV zfk8N&fdO>UwgpK15i}9lf;dn`?nrEJs0Pqh_;`>w)X-EA8>&7Nss?nlZ7oO~s-_vl zhN@|Ys=3U-z%Uym4pp--2$Tq*ik3nZfi48uiKJ*hhz(V93dDx`@+yc8x?+QYf#D`d zFO>ZRBo0;c9>j)P_65X-ivI_(LE@m&o+TJ5FM-&XAgM_h#D*HGj>I-VVmpD@(3I`2Qx4TL)o*C6fFg@K`v!rU|0oWL)B~sv!}-$ z@DQ($h8S@fWCWCb4=Ou^@HR2tJ4Hf@`#0Hfau-Zi;1Q8y}AU0I5F%sJX#DEm=8!8?FVnfA~L2RgaCWs9cF95MYN6mp|dO{c&grV$ukT_IL7l;kj z+Ye&HmORe_ai9|OL2RgoRUkH0d_9N_72k`*J^^Aw)tm*fp_%GFhz%8g0%AiQ^cIQz zKLnJ9p-F%v6j4nHBC*v#Y^Y{)5F6?UI}ke-5`9jg3=G0hb_7TqYH>OeI|syu>MaMc zL25v0xCX?5O0*ia7~M`B+E#D@C# z0}}fu5}P3ck?+|->_mtMxFZ-CgrRIPkT}$#iXb*@SV#@Tfl8Qw*ia3wAU0Io2gC-Q z=E=ao5CAe1%1!}^gHkeR>=ML=sxL=kw;{2og4j^KGb0%48HAG1i7gVz0G(T^XJC+pa~K%Zkk~pP zHq;={m0OHZwmV218XW;h>_{YbI*1MRKpu#l42h1SNCpOBD7y_L4x1L}263PoW+Abc zf!NRzZ5N0Q_2qsL8>;>khz%9L0AfQecnV@e)w}_*K}UWwFfe=oIReVAXNf|zNjO1l zs0K+SwhD+1wLlZZhHBQ0Vqg$XVPF8wDma3~p=tt=*x?{HRDCp5J*Xv^4-$v9Vd^0q za2U0M*ia39NbDsbHZ<7RBC)q2u@8aRP`x)mY^Y}*gV?EH;~AcV906s2iUO7YP(^=1 zil9DVibiB7UJx59E(Bsj)hmG5P=id6*nUXtbR>2Qhz-@-4Pt|qOoGav{%8gUVGxIb zfngR%0;*^Q5_>a<4Ryp05F4ug3=;b)68klX4Gpa?NbJ8zY~~mS23JO?K{7E63^2AT z65ATYh8pC8#P&sEM@<(z=^)9E z5_=I6dj*IMHD?bJ`zV54&u|;Wfg1D#iTxId{SCy11}}3w0|O(}P#z?<5{L~oM;nQ4 zg2Z+Pv7vgy!E8|YGcYhDfH{y9UJhbI4QfDQcOtR-L2Rf&i;>uCkl2SnY^XV>k=R#| z*tbkU9H>E$k=S2BY^dgcNNn~5P~1;{cg91!9&`~I0|SFm0t16Elx+)=hNejm5F46S zeL-xfcr+3_6Ny~{Vnfw8Be6R`Y^dJJAU0Hu)(j8_DzON}z6uGzz64@J&H0SP{)5C8N&*!%P=lnC5I$BxVrzle zP=f-H*d<8pS|s*l5F2Xd93=KqB=%|$8)PQP|NCJa1_p-DAT~7m{(;z_Q#L_Yxg;|% z2t(Pt$%rad0>p;Ky#^9n7sQ5|V*z4A)!2gAP;rlBP*DSw@I{h{0I{Lsu^={7Lk5Tq z70(5+q2d)FHdMS8#DIkAv7yLoXn)Zz8cDf!I(_egm=dpyS+JsSFH^PzzL$*t$q;XAm1|fe#Wp6p0-N zVnZ#+2C<=L_9L+uBe9RCf+n+}if$uGJV9dr0>;i?8A)h468j($`|9+$mp#NKnKKYJh$FGJ zr=Pv-AzmMeB$SK9o`}Srg~Z+fVncnt6N!BYiG3QxhDOVM5F6^*7f9@XAhtMk1eQG$ z5x)XRY)KFs8Ws8=Hq;Okx7>O+pVuQ>9l|wEt4g&*&FA_T$#D+R32Z>#Z#BKty zK?X4}Fmxla7lPPOy{nMen~~UivOx6!GNtLVnd7O=OA_=r1*ZF z&A=cGWq$*SL)9?mfV%CV@MmCP5Cn4|8pJ?ss3JuW8(PMzf!I)SLl7G(ZU$mQ#T`Lx zsJI)54HXXrv7zE&AU0Gy71VBoExj%PNkA2qg4j?+4InmDydQ}@1;mD`nGa$^)hq$A zq2e2n*tw!}s&S{9mc@P^~+uZ=Mp$0t$v7r{c0I{J#`Voo!3yCd| zi^v6%NNgn}wstP49)MbG50Zcynt;U4L}J&2*wD1nfyADO#GVCWLw&g%#D<|zesy7pfU5mtSLt^(Mv6q6_utiPlKpd!L zdy&}3Ky0XQo`Bd;%l;v;h4K*|P(xx{A+i0C*cnLd={IhA@bFGU5?M9<<4q6o`Wr|> zZ;;pw1qjPTkl3KPj(wks0b55$H>eF%sR^;j%~4at|qAP&@^8YFfr61xw? zh8i>l#D*F)7m2+Y#DlhMIGw08}qP4Y~`GfU-Y>*ieK1AhB5s5viRI z#D*Fq0%Ak;1|qS`kl6J|><$21ckk!bPBZ0cwygNCL_>Lt^`Y*ib`5k=Sua>~s(tns_II*idtpBC#)m z*w8ZO28dk(E{EzF?i4XF2tzmwpFk4O!iTjO(F@`Sv9E(QFo=NIQ1$9aYy%{=3liHG ziJc5$Lp_rNW`n|?fq|hE%z;=?2Vz4lYXPyLmd!w7uR&rTKw@75v7x@a3u2c;%zRkP zz#t4|zX6Fu)qJl9aiBi_17brZ*h@gQ7DO`-hz%7N1F^wZjWaMvgV<0*Rgl=aNNi^i z8|q^pBz82E4fcNuhyyh=3&e&RT8zYQM`F(fv7v@8Lt<}5V($a7p=KTdv7u(3MPffI z0o4moiT6knKakjrr3?&=P&EojY-1$0ABYVNp-2$B8WM7`r3?(hP<94L9IB=m#0H0Y zJp)4phy#^q2C=~s3=AD0HdK5PhdIPY@fbIS7dzjl@m_ zv7vgakl4*g?3o}o)SN{~?9~+v44JSg)r}wts6j`O*yoVgPe5#_L2r@R-;mgUKy0Wv z{FMw0j8L}n^u$LV;`ISYLdi(%93*xVhz+%-8;Lyyi9HL%h8n#ViM&FM!z4}U`hVh}?L61x_OJq?My3W>c1#D?vy*$v_}L4tjM4FiKPlzkZ_ z4h_;9AT~6pAA{IX@fRRARQ*RJ_Aey1KrO=el1OZgdL)i1hz&K!4vFmxVnZzs0kNAQ z4vnZ~U=W6~lR@H8HF+R5)N#ciHdGvJ7nI!v5{E6K=m&A25_6E)t3hn21zV8Vdy&}3 zkl1%XY-p4{MPh$JVuOkwMyQ!wb)e=3lmn__U=nI|3=A-~GZH%miCvDwZa`wsKw_^( zVsAlWABVH+85l0WISdTXKy0WF-XpPpAhB6NWd_vIa!71LB(@6@I}wT9gv9O!vFo7* zO#yMB>{TE()DfGJ*oTnVCqQhd`gCKCG*68i^;4YiE15t044kl4bFptC=rmPvvnpq3ed z+0*B}1g#AKJBuN>k%2+D1Hz62NkcuJ31UM7ClADiidTZzQ1Lnt8!FxjVnfCIKy0Y^ zOb{C?J`co(ir23Mai9|GKy0YQP7oU^z7NEPik}3rq2lL2Y^eB65F0A~0*U<%iTxYI zhBmWUn!x=%NDT3VI8e=^AT~54^pV&WNNhh48yfoINbCe8b_s|LHK!JdJsHG?>YW45 zF;LD@B#Dh6HdOO2B=%t>_Dv8Qs`n8R`y&$jJBST6hr5}9ff33Ufw4jU*8*{%1{ou< zZIIYbAU0I9HxfG$#D?n4LSh#qu`5ArsNP9P?9I)f8X78b8A;+T5}UCF$<;_~StPbG zhz)gw4HDZGiR}$yL+uJdub;D_ zzJtX60AhE5!k>YG;U|~_$$tE;i0mwZ#8yON>w(x%i=B|zp-AjJBz8FxyBEZUI&NA$ z5@$XVdku&UwO}g}`y>+k4iftp5}UUT5oKaXY?Fov#MS_@ zp_b`_*igM@NNjr~b|{DqO=xjQ>|7*veHDlUHE1#tdl?dY7ZUq268j~H4Rz=T5W5HJ zvknFZVJMrc6Uk#BHdMV7hz(ojC=cR5CA2_ns4w+FY^XuToe)Dos~BxS;!ySOAU0IJ z4~Pv_pMb=!L}K?MvFCPz8ZJ-`%aA12Be9Qy*wA1+hs3^%#C`>0L(O6CVqjo|vc-|u z+DL3C5F6wHQ2FBt;`Bm-&bNz!K^V$T28ly`mH}deG%zqQ)PvYi@d+R{RD2eQ4cd*u zz`!sc#D!AU4#YQ;^t;k=ScM zY^a%=Ky0X)*FkKE#SHgA?1`Z8XJBA>1ajR(h)chLB%s0j8^nfc;OYUlSip)zL2RfR zDG(c~Mis<{ife(`P;pZb8!B!EVnfAU>p>i-gcpbnl?VZ`kAm%Dhy<~rj*IPKU=W@N zSr}dj5{K$71F@lc8$oQScsqy}QeK z*O1uvL2Rg_zkt|KGyfv7*?Jim7@^`ay`b_RYN#qm0?IZ)V%vh)P(z(TY^dgNBz6K4 zy9~sJnp2O&?m%Ks1hK(p)-y0H1#zH;u0vuU0kNS5oke0_Lt@_tvB3s0FgyjZq2|0p zVt+?s^Y$Uy7GfYaY@$#V#DQ9-2Vz4FwFa@FhPoiJqd;t^`eY<_4idW*#D<#F31UOd zS%k!{UyZ~$2x3DGJ%z-+jKsbJVnYpm31UMH{e;Bk=tuZc5Q!~?#8w8ek3tuUXo5IU zgPf7r;YjQPBz7|rdo~h#2@-o3hz<43VI=k$B=*&QQ27t_%_EQm)Df?d*k6#?ToVvJ z6GmbyA+fbVY^a&`AU4#@P!JoM{bE4u$)K_vv@mu81A{P#1KJ@5l7QyjN)Q{Wp#{W- zig$w8Q1KZcHdOB%s5#6G3=A7U;!yQlL2Rh{10Xh3{MZCg`48263aS}Yyf@-)2 zVna1N0kNU#e;~2BCo(WFLd8Xp*cwP|M*nF1;45+^b+2t(O9AaRHy zhH?-a>WEe(b{B{ZRWlXDhN_tbVnfAOA+fiD*ibdQKy26u-BAz+Dsc+LhC1RL)Ip#d zg&u*#p=zFk*iZ{Tf!I*-A0ReVFXJQz21Y2G3yG}&VnY+AW<3(e0*M_2Vna2jBe5Hi z*b9-^hmhD;k=XZ;*k3?wsKtMwY;gU@HW`ts6+vvM#ac*g2M`;o*%OH!gv5>jv7vgi zk=S)e>={Vxg_A+$KUBkZkOb6%14!(XNbIX1HdOrwB(}g5L{MuXvF(xAK}hTr5E~qQ z^$ZNzAP(p(gnhz(V<8N`N)?*Or( z;)g+OsQ3vGyB=!U8K}h^pnHr!5>Q1?L2Rhz4OhN@2kv7zGGAU15Su^Pewo74tkLlrFp zv7v^pf?5D7IQN0Xp=u6;*iZ}3f!I*-Dsun1Rbvh!0NrKo= z&3Z^|ep}zS8 zVnfBbW-u@?Le&c+u{A+#sAr6j*w#pFM-UsTH*^N5YJqa%kR(b#Y^XuCNbEKwb`OXR z)jJ=Fy%)rWI`jyL4Z1^}fq~(~3Lx!VAPc08Wbx{vb9~ zJPO2y8Way=Lw!?>#I8YNw<57;gV@jzU4q13TaU!q24X`kJ_TY!Ex3%tzJtX61Y$!C z{f)%tnuSQn!XP%(Oj8gWYNj2O4fcNshyyh!7KxpP#Lfq?p$64}*ieI}BC+Qov3DV{ zZz8e3Be5A~gQ^y&K|-?;u9ik(t01v;L2Rfa96)Sn)VPD#vmsIDJ)40+7|IRl{RA@gcFrk=WWGHq;ywBz7v7zZ>E)shg5_>&}4fWYp5F2XobtLu!B=$ED8@2}hKZFDJKF3^y z&jdkiXsC#T*ib_ikl1D*Hq>$UNNf)zb_|FO)mx9m?wAWI|Dh5SktCLb*ib_^AhCBM zvCo3oP`w|K*uRk20`m}_kwjuE!Puburvc(X4N3&Dp=lxm#GVHZ6o#C63=G0hb~#8K zs-_9Vh9FfuTl0f|G^TnDkC zhTa9Sq3WL@vEL)HS?42s&xgd8MX>7`v_KrFLC#3*a3pp%61xP6U5mt?3}Qp0Yz`88 zH4=Lxhz+%C7nltSe+CAI3m^_u^Gzi7BP8|<5F4ubHxgTF0RsagR9qK{?TEwVpk)v`$24|nTwIw+ZKY#f2hQHB#9eH>~|nG)PnCwY=%V$ z->`w$P;-=!*xE>JM-Uroju)I=&%h82=P)otg4j@lYLM8iNbK1lHq@XcNbI#p?9CuH z)SNRQHY^8$*z-Z*%)oGa5oqxcl=BQE0af%7#D-?GZy+{QoMkZs10z(uD2NReR{*gW zKnzt`%)lTFW$S~)p=zu^Y^a&`AU0II-V4NmO8A4=&~eCE5F09<0%AioWP{kC6PG|8 zF_2|Yb`?k*s-_jhhU)DCv7zEqL2Rh_ED#$M{~&iShHyYkhBZj+{YdOfNbF}w?Dt4) z)+LBE!H2{aM`Fu@*ic6sEdiDPP}f<4B$j~Pz+k(Cfk7C`_5g`P)ubS?i;&p0AU4!z zO&~T@??NQ@HYD}|5F2DBDE}P?ah5_XJ`J)M%Dx5?2PtA;V0Z{(LoIj)VnfA0g4j^; zZy+{QoN*~)Mu!c=hKdV<*iiNIOF`v7l%oQYfGRRZV%ve(P&LjVHdKu-hgZ@Bb|Huj%_&t#>}CYJo}m-Ofoh(E#NLX;-iO4#gv7p$#D0Rr{sm$~EoNSZNE1Rx zY!eWBDJc9I7#M899Efk+kk~OGHq@Y0Bz6fBy930AdSC?-dm|G2IEW23=K>P@W<3(; zK8Ou9=r{Ru}eT~Q2c}ZTnpuZ*poqQsOC9H z?4?NT)gU(15xbGt=aAUXk=P%Q*la5hp5b2sD*vIDNgzq6g4j?C^pMz&NbEEuc0Llj z6~u;`*@wiQj>Mh|VuQ`EXJA+c=P)qr1+k%;k0G(oBe8FQ*wB>Ex{`qbl+{2XCyB&X zLSkEh*ibVak=R}!Hf(Ak0K@^ih=CymiJgnYZU(WT2K6AZry{XugV<1W)*-PkA+c{G zvFksAI8Z}>A+ecPA>xS>#D*HGh{QHUVn-selaSaIAU4$eMkIC@gbm4m6F?lO1v8P@ z+mYA@kl5EiY^b64k=QSg*zZ7WsF_Tw5z!o`j7#K8GGcX84*~UnU z>_BW-2?%0CHT!|sQ1M_88!8?LVnfA~L2Rga9*7MUF9xwe;voMw!Z-{J3_Tz=RMA8b z8|t8?NbGe;?CnVGvmiD!RIVYhpCYl@*Dx?JLd_Id11kTa97!YzeGnUJkOdOk9f=(c zVng-jBe5%x*o{c+SxD^72zEWg9t4Ns9uk{*EyATTNNiOkwl#s>PKSFKw{4Wv7rWSLSkP5Rno z0kNSL1cBI4gQAhx1t2!mapfTPDu{!s*E28(L)mR0aj2S!AU4=>^$ZNtKpd#VLJ%7) z!N9N##D#E6wg?V`6Nn8}<>t6wk^oz zKN3d{iR}SmLk$Wu18`|1+k&#%tK-?M`Eu9 zv7zQ1*aj+Upq!^j5?tF6KF~m7yCboqk=XS}>`6%M)ky3kNbDOhHpu^PU>pVp2ALfQ zi&c@>)*v?2XD&!=UnF)ghz<2jIug4H#D-?PP7r$?C`~ai^zL9_s27HE7J?+8IdvI` z4b`v(iM=1hhN?LNVnfxO1F`o)4806uL(RN{#C`{2Lp|^v!LDau*onw_oFF#TAQ=!F zYJoC{y#Zo@`c4K0VJO=OBo0+$3t~eZ=LBLy#RHJo@ks0}5F0ktm=EGWHB^Gwdmxt8 zf!I*XnxGahVqjpH1`>x_HV4Fps#%J}-VI_yeS8FoeHMv*tscaITJ{*kh8pw+iOsYN z5klNZY!M{3EQk#?M;XM1nqvuKLp|mIVsCQ34NbGbFdpAf0 z149mo4b@zV#O?;Mp}w4g#GZ@9UIt=A%~=CtL(Ms}3)Iwvavp&sppJM8VsC+1{1N0* zD4TsZVgQW?#D=OD2eF~iAp>GV#nnM48lot)$=16Q8B(^_@ z4b>cr#7+XSp$6rE*gGMPC;yX68kC=`yPl5b;NfN8|pazy@-&oMPhsI1(pBz!1gi(BT2*~v6GS5SxD?WBz7qh zyAp|Ahs16|Vt2yWApiHmI1CI7laScckl1sP*b9-^E0Nf1k=R?2*gKKf2awoD_A)St z!p>ScjU;h?`dtN2@%r0HLXVKx&yd(}k=P%R*gufie~{QL`w%g~fyCxVVhcmq(~A{7 z1tsMn9B>q=A+fcl&sFpkuQx>!vO!`yAhF$%*xpF&U?g@p5<4D=os7iJMq=kf*r4cR zU?_udz;3KUVmBeN+mP6ONbE^S>{&?cc}VP~NbHqJ><#;nj_=xnB(VpHeE^Al0*QSF ziG3M~eI1E?ABp{Vx~#INc>Q}Mp>Ig+Ur21m{fJ0rMPlB(^FNTNA>b zzFFB*P|_5_0SCAZ65C<=U632Sk%WSf*kMTQSR{5L5<3%#or}aSMPgSXu^W)sEf6;3 zN{$`~2kgcPNbDI%>^Vs6B}nWQNbC(r>@CyJs(6amA3zd1j>JBV#J+^YzJ|oUhs1t_ z#D0myev8EZip2g2VM7u<;{l{dMq=|Ku?3OXl1OY>B(^FNTN8|7*vAriY1#s>Mn7RF&4?ul?07>Eq68kg~`#ci+IuiRf68kX{`#BQ(Jresff*r>2 z8^K}tkHls_h)5IMNNiywwm1@79*M2oUa9W6y;9w4xfkP->54^O{)~I37lNo0(+?JT zl`~$MZdvT*&m_Y%y{p*Ek8#KJo5f!Kj4jhOOT7FUZ%nTQQCFs)1W_i_B}={h86&1= zf~X_YcY>%3(>cq${2A{|k1X@@XX0U-zN*a2kFjO?Pmt(@>7M0aV`hS=C(~boD2wTq z6<+>~CDS`WRLb<5AgW-xW~G-uW6ktR5Y;jLB#62&U9!r{pGksqdR7(K(4AFY{)`8v zb5?u#GjVWDkE-_aV-n$-zN*^Gk1=NY&uTA!#uL*$YrOm!O{UKTQ9jdOf~bh;mbG5~ zj0Mv>LDZe;H$l{k>6&#QC-Y3Ns`K(=OqhPM&dZ;%V!C9#mp|i~>6swv$Ml``pwQu) z&eh=M$5=Bxvcb!rv19s55cOsH&jv4lCIgC7iF+H-?%b(F@`brQrWBN}J^<}zeo0mW1oar+`l*ja!ASz+HWjojdo$a9DQJsFP z-OG=0&veZWaClULs43G=f~Y;yB|E+RnFKVaXLWk{G3HF)*$K9TvkM%8ks!)p`brSx zG5sfq+A!U-+smKPV){%FO;tZ8JTq&&!W7WctoNa42*3gTl&odQ?AH?aF>Hf5x8aKl{CoGya%< zaDtaV6N}w+p^098OagY(lR&hL-SkZ$TElKS(5u>gQ4!Nmf~c11k~6&g8COit z1W^IgcY-LN>6|mY{23djM}nxH=_^6hp6Ne9)SKy^v%o2G<}8rALZ-i(<>kltWV+>S zFMq~>>75|z#PpjW>cMo)IbQyZQ>Isfs0q_gf~cP9l5@TM8Lv#woC^x0$mzT0g2RGy zo|ivk$n;1MRWW@fh}tv#Cy4Ty?l~W9%*^>-{!9k3(_hU8<(|0dRtvoRKvpgQ2mMVD zl`>s(Ay{oCh}ts!B#8PjU2+jP?Ph|gg6TUKfucEmI@e+^KgN>jk&C_j8D~si38LOi z{|TZBrh6^{g9aIzgptu$GBv=e!bj@YpG+4O| z~ila=Dj35fnwHy?=i>7m}@bY7#(T9Jwo3fSj^s z`Y({^lq7tTCt^()WP7rlt`b`j3GhK7Fmp|i!>6NQNL2`Kd zsny`1kX!?fwoDLZGkqtBikQy17F<3>f~XzSSAwXR=|4f#jOm{1K(2cWmAfYl5hr>4Cev)R}ZnOt0GIrN($<`a+PX!}OCNYQpr7yS%j6 zj0}tnO^v5-e5@?7-Ez0rc6mnY?H_M>osr=UW;b}l&A)&7|9_&$+*xp*{Q^CyWxBXv@&lDEM zZQCa|`g~(yblKk3=JQUT$<4Zg;)U z&A`A?ygl=Uk03MSw(Zrgeb$IE>Q2{S^3~?CH$BP1zyQK*meUpQ`Fc!#@KAF50VdxA zRv`CoDivliG&D4wZnzG@GMQfJBmovPnap5mmD9jVrXb+WP-vqF+$~4o=|H5jd?XH8U9n%r=iWqQte-xhHXK1c##U|?Ycjdt;b@h~t1Gfel-mzAh@ zW@2DqW@6U`1wkfo|(!U}ofa%Lh`*D#ydXz%q%I zfq_X3bm0)oZ$1VFCMg}zIrto`i`f|%m^s)#voJ6)v#_4y0a5Hsd<+b%EX*wIGJFgS zY%I$_N*Oug*%=sE>NP+rML_q|v)lve6$M?v%aXv&z`(2s8q#Nx2Px1k0L5W}AOi!7 z;tmi~g^7WIMG17lJBtJh0|SflIgqF@h^e*~#QX$Opeew}z`)GNw1AC)ft`cpXbd9* z14kT4(J_!#2F{%6vKM{1CEM5-7+6k#gjhIOI2agMPJ-BM9P_3-Ui6jbIl{=mz;arg zk%56He0s)3Uq!~s>0K9nRqBO7YO@)^2T}5W;9_84$pLd1`TsIAFtFq@z6Uvl|2;ng z14|y5!@=JJGAtj=;o&#tWME(^0CNQR?Lh_K*`d>^846IhHAW24k5ncucR%=$!(nltK7eNLFRvT7`Bc^aMFtFN! zIUM{u*%%mD?Z6x!2A*bi1_oApR*=aoI=l=FY>BIw7#O%fChlTlVBnnqE?rnum>C$@ zCK)m@FbK1NqML0l<6CBidIpg-tPBhcA_9U842&XsSQr?XL=2f37??#EK`|_H3*;n` zUyKY4Y$CH685r0_c5^Z?aEN&EF)(n7II=M?aEWLMFfee7uyQdl@Q7SwWMJSG$>LyO z;1k)*!@$5VlF84&ARwa0$G{*c;>ORwASB|?#lRpeQYyf}AW|=4&&t3cDk96zz#t|v zhnayvT;vuf1A~MJ=sGh=5m^of1}Txnd<+cIA_hDR3^F1Um>3vjMHo048018_SQ!}P zMLIbd7!*Wa@Gvkaid^DjU{Dg7#?Qc@EaJe;z@Q?M%F4i?DsqRFfk91VDhmUHy2v(O z1_lk0c0mRPO_6$bZUzP|5l|Rui(Fu0V9*f(6~wwCyh02NdJH^g*ccet0>E*{r@$7* zbeV;Lf&U~o0|Q$)6DXP(_@4+cFt9~1l`%3fF!BH8Vqjp4WSRj=sr*@>5RU@u<>u$+ zVPIg326K4$=dv;|u*HBl^$fiH2RIlQ*kYM}F)%Rj@vjtQU|@>_+athV3o;>|iItIo zL4rRK6bFe+s!R+FlKe{S3=C{ZAQKp*_~(F}kPPNX^D8hgFtDXCy=7)#kl{}ODN6;* z$nq`7;;2PG4E1};!4d&~k&EsP92$3Py*Wcta>z`&Qmme1tQ%D}*X z0_26CQUr1`13MRc%Uf0k298u_1_t&{koOokjxjMXuy=#lj2w3b85r1m zKx`(C7A77B2KHW%wJaRHY}4~y1H>(j*clkuCxEPF_h6s4l8u3ZBbuOFoFXdw)F}1B1X#HU zdID1P1*8aM4p^Rn#gT)7f&D}<$gH=Z68Ah8I|GA&6g$im5Q~A01r#7GZ$S>a22#Kh z4zl;I8Az=gI|D;K*fc?qyBSzEf^2&NvW;am7Xt(Ps~C{7bdZrC*D9z6werZKo`V&G2&MU4rV!^mF@@~0`7!^AHIN-$>iU>-C7DiF^c z%wgfb2hwB#=CCsGgn?496=Nf)`dbD{-m##7Wyu82Un-mt*V!)c=e(k=|D;%vboz_FN%fq~Nw#Ae|DrB6IgmyMjuLJL25xzfFbhX98v_Hk z0*K84Zqslpf(+#0C}Uw@;8p@ToR7nTi-Cb#8RSNO1~!%tp!mvUXJFt~u?A(P5N`Er zARGKR85p=VKqfJ8Wb)QCFmP*v#925%#WlAUIN~5iX@iUkVqjwdmF6tXAk%f`f{g0m zHrN9S(#IeNnu9E7;ArJ#VBod`u^BlyL2L&Qn~5V6q{b2CSQd_Jpo-rK#Af5r19`}q zRTvaY9E>0d7mx-{j!lBo?|B7?)%Pu_5?XcgkvX2trsZ7B{(`+ z85p>|L2MNcOOU0$po+CM;^9yPc@><9p^;tz3K{{9 zX&~z=L2N;ei=ZH=0tJl-14|jmO*I}o3=HC1*tzR8c|kViWHWHrgP05)j3C1sKq08W zF`bWrfxGc0Xb4w>V-?7zraN2=3_2VyKuN6`lvWxzsu>v=xZ6M>(IW8=6baq_yr71J z#6gh9dg6H*7!24XxIsqsg3|d0b_T9VTnr2#E5I#GMg}fVUIqpbhVt21K+R7sP#A)= z*Mo(b8Mr{flFthba&88eL{M7j-@wDbAeq9#z`&>qN;aTIm=ps81LK^6KB*y^$}Ffc-et&rFrNbDjcb_EiA)9Bq zhiEX5WClAT^gul+SV;Cy4`lKyXOx^?dn{3W`kUwRJk#GW`57?opDxSnC(d|l`rl32 z;;J7x5V}P;5o`q{w$Ak4&Dr9HK1f0lNbD3OHYg#%98f#`=-0=1`@jjiQRz2o{Yp^ zhQ!{4#NLO*KE(x^_=39nE|LVOw+;)aKS<&npdJELy$BLp0g0`H#I`_UyCAV+U~Cx% z28Ik62Xy2T61!n~uf4c<{R||b4M^<6NbKuKY)~Z&b2|eMBFzXRvE`B2+DL2*Bz7!> z4T+&l2nQTPrAX{XBz7+ndnOWl84~*#68jPo`yLYe6%zX!&-6MrKe6dM{G@p5Wq1+3 zDL`UZBe6lv3P#X~0|Ns?CocnoFqAz7NzFVEn+xn0h9w|2G)6&{7pQ;%$*cqE1)a3S zz`(E*q=t<_3nb2P6T$(rA0e^dfY?xjSf(ek`-yvM@G&qjf@%#01_oUa8!Byx#5O}> zTOqL>k=U-=C$jtTGcnGYzL3)oG|}*p)9*Orjp;kN{6Hh=oZNo?(`!^!IHo6X`>8Pc zOh2e8Cp>)yx1Rv(6>SEF57XCj`zf5`8H z_!*B(SLE?iXXOxNV95@7r?y$~d9AjrTV0Tt%)6JRy4WMD9uuJ}|{csh?R zBggayJboOk9)b)EU#C0Da0yT2^%G!Bm@dfcr_O3C!oZ+3-Imu+nK6EPB1mMG8Ut)p zc>ze_rRf`a{nQzsOuq@D9!+QD^HXR2W68jfGyQBmm&)`&5PyaS1H*>tvJG4+(--pj z!3UN>L%FQx24*G}(;v!lsWUM!Z5QMB+a_GURRb}uDFhlOYX=PnfTImTF!>9B1~m;B zKm&nnizFBrn9M{#gPKlY5e_dg@StX(5Ca2~EeB{&Ga4kp#C{Ak{>j3cnODNV6d?v0 z;so8)0~*8xjcswThS!4zH#yj|*ccd?uCRi}yFdfYOmjfOqUNAmSN{rtMll0G%+nwR zx}aNuncO8oqnMy$rI?_*N$tzGiXoNG9ltCl0>vkdaIfhlkGxG{{^4Rwlrg4jS+*1am|fxI#cuMU2ZC z85sBlSXMH+F)=U*G=em*0hm)& zFpHIfoG%tXeXXjWT9z>j0|T2CE65~9zH(4A&6@Q9D6aT;B^emlY*;}aW8wS9&%nTD z3+8a}%?6DS*?~Dc3|xYs#=1T0Mg9@6i!v~9 zih-(iF0p;$3=G_2FBljYc*GX5F);9o1@kg6@QHN_F);9p-4$bC5D;?~Wnd5#TP()F zASAYopMgPGOhtl$K}76MJv#$~s92R41A~~@6BY&raj`Fa3=9%tmMjbml49?87#O6) zK8i9hNQ)&4F)+x8En{Y2kQI{zHFm{7L-q1v8~GR*6vVCxF)%2K>5DNiD2Z{2GcYKN zIdd^EsE7%0Ffgc!J>g(rP!oH@#=xL1HdBOwK|`!dl7T@}Y=J;M1A`W5K_!E>n5qy1 zgN~R0sLT{wEd?4S<+=#!L!^7tR8eNG2b9n3dHh_jkVwpfE4CYAlfl3ti z6sAQi3=A@SpnfHLDp*FA&kodkO9OM{_;f(_q%&;=_1@$eI6!G?2B>!gN*jy}TzVjn zWHPM-4V-4M=QI5Q`CEXMfq}h%38apJ&mQFJBCy*O_%4G6smj11qQti!BvZ~5!py*+ z!Z#lzQvtR#mG3>sp_O1x8Uxo4kh+?BrX{Ql48p=}3=AUR5anUC^aLnFFtBoQw1Cne+gi|oNGB-G zGqC+&W?d}4jLonSO{{NA=_z?`b8jdBesbk zGZ%X>GccI2%>xZ3Edg2S!oai$Gyt`9Ehs!fK|b7F0?JInpz$`5QbuTaf&*0qWGVww zJE(ttXeK)YgYZgrWO)WAEl{pL0qTu1@qN(I^W1Y{eNFlf;0l^_QLgRl%}OcLZe2Bs&%3=A9})j^`> zAW@LFL_i6Ffr}FqOYDpwgSk>b?vZ2!8N{o@p}_b8Gz9}nkQ|C&HUr-lQ3eJMCB}E) zF;c#DAbXV=zktR_`CLE&tit#UG)BtD28ujYM$iqD2};^iL3*?qRX9Ooq&zI30jzo+ z$Y>`ED0q2Twtz-HS+0V~2VfEuNIWcTAlI;fLV||{*<}3iQS=dCF85lT0EA$xH7?=b=rWgGHMFt0FNeveR zgXCI}`$|E^NoEQ%FmRTE?3P>#s)foyCP=PkWnkc}uK=YiNqYeX2F}W@phg3emN)|g zXSEF%0|V0xb_NE{TF~H*@ER@#1`$v)Man2kK)&Sw8MX&BfCwrHIT=`axNKg6JfR`V zz`$h-4iPq2eg+0EI}n?NjT01e_8?sx3{3SaK_jIOApJZnATcf*&=?RSxX5ENU}j+8 z@di1I>5Cu(0}t5YOm77k7$-uy412%~h(gv8z z&A=cH@?AI+1J?sK1_mBmMq_RU2AL!#9&g4o+zbo?pxT4Sml32=0BoZ_*b)Y=15ykO zJb{cWxfvL^yg^P02fLPwi-m!KCmPJ=t!LwjW7OkefI2oFq7~xU1Tcq*&xVzOfhUm> z6ay@L@=Od2JV{^qz*90b>0!Gk0tH3jmXd&47 z0y97!EC$;T357DSEpni8pQjwm7I*}Ty$Z%B+@MA*sJG8kSP)aC__$tzB5X344XFfq<}+r2%&-Fu z{)l~*1U1oagIe=qBA`aLSU$)MF;L0E#=tAXv$~#f1*rK2P6cbgsepm+Cdip*r@+;8_Reu<(IWJ8KKLOU9|Hrw49_XXC43AF0xvEHvC`sG} zX9h^r-vc`Vk|gef*$iA=+zbpn4;VM_F)-9~-2mx$1CByo37!v(8vG0ld<`HK9~osp zDTOZ>q~a4;FB9KgkUKwvqkx5h%LY^kd|~{~$H2fV!SjPL0;CxnWk12{8NmG@o?kHa zS|FeOW;Edkt7l-ES`X3y>MQXuGJ&EM8v9J(=9vg2_L;#PF$S(ukZu;H6n+K*__R$(#_U|$Y?ImSQ?K8Q#eRj4yrP?dQb>+9S6Bvo2de%ViH`%Yd!`B5jJiH z1`&`L0}l%*hPkGKf?S_z2}tb;klJ6M>H$=hAlfq`f*@U`pgMvp4rI15(-n~VcOdm( zM}peWA_}~ql_wxU1|AkriNbXZ6bj}{;HJz^kngORcmzQWAwdQP5x7O5oa@NcD9FIT zSIfh|z~cmFGw{6zr5a}@(3%bwK1)#Eb7ATQHA(m;gTmaEX)>s==i>$~QE_9MDagPe zP|pWyn(??Zf%+*Te8nJ59!yI?<0uR~EHgkQ0ShS1cvw`xY;Q0L@;46)1IRR%F9Hk< zT%biBJf2K4pd|ZB+SBgjgx_aR{_N4U<(IL z)blEWf`o@H1=Jl>0#$B&Y`&n>p$sbW`5AavmVz1}4?z=DD%(L;gz%~dfvf;!K3)xw zQ4DMsc^DXYH9^8GY@p5uuNJ5w!T~W!8)Q-t0}l(RDaiB|WVnu`5Ca2ieFv|Bg)jpH z+fI-R%|VtkunCDUF!0)e*o^#U~^B-l(qEjw=zTZOF>B<>4JGX`v+#R9zkAUB(^gC+ra13~R<3$`U7{|AAZ zfej2iEVDo%CIhlR7}OP(uVLj4%?A0C6Xc&rEl$w1)&tOqpS;l^aUBK@J7ETfYGKgq zB&hksz_bM9uozEJg~7v{v>BuslrMRcK@MkN1Jwn*DIhiz8>k7un+j@su`n>%f%K)d zf%I|k=G_PB1FHo$KWLRao0;GmDf!2AofkLfC0n|C*?fwonN8uqT@%ONcf+h?V6hJ2R zg0k-hb_NbUAqEDJ4cwq+RXrmE$43zc1`q}dFf#D4fCgSTKmiWY4;E!+-~fdRXdn#C z=VoBqC&s|Q+aDpqz@W&+#K6Gl(E=UAH3iQFf_O@xKxFg)l}!u`3=GOEL4&_uARmDy z4V4{47#IW?y+JBL*O9BpF)%R9o~~fwCs7ZwOz{(FN+BL34brU-Huj<@1A`hU4jAJ> zanJ%cHW6ejXoob|SjHrfHt-atq6w%cUIyZWjBx}T69gK10lTgY_L0*PT&L)a8 zFsOlDu>$0ZT1Ey2O;EmITmcG5#$ZiQ#;9jp0ZQhKArL370y%Lz$oHTz`E%+F44@vK zDq|F*1%nD`9`~j?G%!HP0JI>FaUaZ9kjok8T!7oU4`k~Dkga9R3=E9>zJOvEVk_f5 zkTQ^^^`L+`0J2qziGe|#hk=0s1Dud>Q$` zriijIFsLYjj&TBqUo;bFn2Lu5)ZO7>Im69R&!GPi6e_CV)*mSNAW3CC+)h=nou(`> zJ5?D$a*V-7;1E-1yf4APkk7)vV4TUor~x*m3ABu!hXvFRGU)_GG-$yP1A`JcUS>)& zFc^Y!uPvx~SkJ&1Wat4ZJZ!<^){MarpW1UYfPHGm2x_C;Vqsu__|5@rlL#vV zgDH4k(-GVeWS;n;$|x4p?{EV5n{rqg7<42U7#Ki7uMS>ptHHofA_a~sMnhG`=;_&B z>fF zKgoJQ4X~q_iokXhGpI7gf_%fkV769>fq}6IG@{6m1`fjIvJ4ESx*`k=j3wYkHS@#` z^`_u_TngqhO>{9m3z|)b^#5Q{RSu4-W1t`dCy)wo0$~hQH)LR7@R8MEV33jlyMcM) zmU@s!Ihs@%V;CJ6)FT-f7&J5(7%X7&8$j}qbr%de84L^zCK?P3>b0Q792yJ^snh@3 z`N>243OZL66h4b&AmQU+?uD0LkdcPLH?uQ*l>e zWMBZf%10K}RgF+rnK3djM1ZUV%SSVT!Yqc-m_f&t5fb4lDWDl1NM5sX@RLggEp}o& z0S-yf5fzMc=EyNH7;FVqNhd&wk>MsQ1A`&BlsLf%l7j`^DR9vJVuhsg)8MqH%*Mc= z11h$`v8@S>Q!_b;Kd(6WNkT#(1}akwl@WCGlVn}5&cHBfy1t{IRDB94!|||yS}yva zg~5#9z)2UB6=Ol=+8hIU1_lFgsr`)+RDgmO9-7MYGcYjz0CyspCOSZ3AJX4qniykr z03`bhY|akQ90JIhpu%5D9vqa=L^d%-l`+PVsfdF?#gl=7p#Yo$qe0mshH0V$1B00< zC|`<$x)2PYb#sh!5)~L248cwjX978eF~~qwayqAzpNv=~XkuNQ2~p70{g}pc))f0WvU{go8?GP)W|f-~i4g8yPEpuQGksHp>J7XV`n)Tc)N)61Ow^aVkq zfQ)fqBl$TP7>vG8-{$ORq~0aUz~HF}b}3sC1K0omQVcqvL;?08sKo*D`xHfp-&I`v z)LB9Cx_x?pi=P}Mq0E5>!#l<4jtkAircZY96O!!EU|?WU0vpRz#K55bih+Rvq)~PH zKDb6cP%_tGV2Duyn?B9ePgoLE{}e#=l`t@<>oP+0^-tGv^^>v&8v$>@7=m(?p(1_Mwnz&ID2G^IEh z7!1HgH)Pi%Xm~7V;PMY)IrChEYM(JcnOs*V}L~@NETGhyb)ty;8cY; z3?vIJB|-75!p6wJ019SM7Aga+6z+xkj2qM|kY=y~1)jeCJ5V8T0qlQJxPtl?jC0E1 z;d%iauAr$MQ16_fW4fS+pG3GSC^GJ$X*vVfbPufQFed{8B=GM+0zVjH1SEJZZ|d-@62!!jwTVvA-p z0O>IR#k>IngY{<6o}d#xQVa|r%u~c{3$hc0`6TUAB^ek%n5SNv#s0c50|N;2n6ucQWoBRiVV?6$ z_CmZ23?R(&jmdrvHv1Pl5S=T>85_*rs{)@y`2eoyfM(853jgi=vNNjr~wks0b8;KnS zVMCU)r9n90q*R2&u0vvXA+Z-Dv9}?y4 z3zQAo!2uHwLJ|k9vw(?bA&K`Ru~#9nw<58x!PubE{UMCQz`*baiOmjLZ3=Y+Xk#4A zG7BVem+423_?1hZLlU};#MYi3deqOFv1IzhqkiJ`{h$S+Py@jWO`&Y?LQ^OkG|COL z=qi%>he+&qNNh$>?;5I?7l|#2#0D=k)ntII)-^(saGjoL!7FYXjU<$Y#4bc)*CMe& zGqf-_9-XfHmq*+ayjm3Mj8{lXew#M|g$Na=Sy^(|>kk~~? zY|w~0%(!_-;#-i|2d4A>=Mm?_ne<9H+$K}##4t^iFK!;EvCzV^7E z`1CdQ2|SFIQv-R$>!%^9T!X~kfy6$7#J+>Xeu>0p0(C>6HgX`b`HUIaZd{*Ay*`JFcLchi4EF%1hb|ANxWxzFEg)r z{Zb^M-AHWEDj=A)2T0;?kl2i%wlLInd`N6*B(^3J+YX8C4PiqvS0sc3j+MOWhOE5e zi5*BnppCLHx2#4I-;TsSjKn^V#J+>X{)oi>H~sD@KXG13(AW^v3#!w5*?7ebbCHB* zBC$^*vA-g*8K--m_H*Y=2aRe%O)8oG@L9BY{Q)GQGf3<>unKS*qTP#*zm zv=S0q4~cDs#CC(QA!qVMLO9^C%>lEgztYu>nm$9^$&mwUsLu4Av6myUw;-{PBe5?dv7aHaSwX`!nxNHd4501T3=FWymW4=w-L8qmHbr7P zBC-9D*r25cFmtMq#M_YAlaSc+M5Z&H^AoGzjwE&ji7f$YDnkQD8Hue6VndgQ8;T;9 zio1ctLA^Bw1_o~s8>%-H#D_aTT4nmJ%#V0a3$7|Q+t z64wNUKLZ29FAxW6=zkC!s+mUukvqjeY^WM(5F4sS6~u;$8zHgnk=QOEHdMVIhz(UA zYyjdwB@#hwsOwTC7#Ki%Px=@b7%D*GPz`m{?>1$MGcKE+xYbF#{vb#Ov}AyRf#DPq z`!W*y8Hf$F;UkF63yJ~;hOZzSpls0MZdl>L4VpKA+9m*EL-oobv2`G9NPEK^#DQwC z0kNTmMuON-%_$%@XwnF@b4QYa0kn%3L5oXb~uO)jkp9Pb|wJ>y{tAp53H3mp*OC+{Eh|Lcztvw(daFEA=*ig;s zNbCY6b`6LPwRjeY4Gpw~AU0^wkAZ<ISFDzL+%`i4HdtG#C{H9L)6qWd_`~=eu3Cf3z+2?7#N{!Ne~?oon!;? z>|T&G)Ke!wY=}n~&Vtxb@jFQD*GTMdAU0I}Zx9=5zO+2(#1n}5h9EZ7oO%lo2Q*%ei9HjO&zVuR*yL2fz* z;eeP7=aJaAL2RhzCrIpHAT~6_nH3Pl1rHKi2*if!H9=x~Ah81#K)DmDC>u5@$-S$P;ogVwk{IeND-7fp}zD2NkG}bNbF1y z8yeI_NbG7P_EZoXs&@wx`ydkgI*1K5=K+FU&+rn#VR#Q>Lk(h90_~6j1v&$R8WLL{ ziR}tvLk;yqVuvHKV?k`FnT1H~31BuT{23S+Hi9_NAl(6CLv!sOB?bmzDEl}_9IECL zhz$+iryw>|`~!#$75@riL&ceu5m6(E#Fm#p;^>0dP|F;rUv%XbudhH7>IAW&=1l>y zLB|>}FfhzeW?%r-@t~ku3=)T`SqEZ6-Le_PhKlb4v7zFJL2Rh_MI`ne5F6Ihc?jY_ z6}p*O%nsy}i1SIxM5F6^awIDXsoHI!5S4eCwRj3C*XW$utI8a|&gV>;zGoXu& zR6&bMLEdFx@B)cL)r5lB&=86Ov1O*q-Src%2hF^IE@lI1gR&=rq@mj8fY?xN3qfqC z_<9f92XUYhtZEDlj8F~AAU0H7 z55$&-_{m6(fk7C`wgrhp)p&r|P(yt|Y^Znyhz%8w1+k%e3nA?3?lVmU>nDIX(Ab)Z z#9oBNUIAi5HE%>>9|y6adM_ZcZz8epgV<2LKato>>I@8w^3b-R1c(DQND+yxg~T=h zv7rV9fY?x9W+1T}kk~ySHne#*5yXb7pM%6+pze++1(qX8tVUvQKw@t}V(&y^@14Hz zzMr_~2_&KONbJi<>|03edr0i3NbHx>86WtG*MCJ4`h&y_8-TBoaFoiJgkX&O~AtYJkcb zXrz@QNz@{-8~KrQrO?0am(~h5OrYs zO%OF>x~7Of_`Gcqe}5*1$(QOr9hH%mXL_cnKj?_=ogiw-bWSmU(7E4{ zASz}0N)S~r{U?a3neHj>f1Fok8UsTJ0|NtSsjJ>}L1lI6=@t_H8jKaw6D9mXM|N+N z@b_m@m_D6J(%+AmT%is|5!buY;K3$SuJFfe3H|M-kwc=``{e*w@* zy%9w9OkWA29!|dqqFSc^RPa}4{T9x^aC&;+1R>$+7K;7?%m<4Yru%PZ7oDD<=r6$d zXL_NczdEZ)F$2Sj>EHu*H-Lnoqy}K)at= z^1&P)zW<~24N@AHhkfApb1`KQP4pK!l0cz%)+2E z2v~$4F)}c)3TuNLC;X0qfq`APo5hcTfkRk{nSp^*I2E)DQ@9Lt#+WcSXxE?cQ_%JS z;V)ba41B_%^8)yV=Yh`V6s`vyB`Ms)%D^BbY{Cud-%n&>U=U$oN}V2L4EM4 z?*}Q10n706fsSz34)e_Gq7@Tw#)z>8T*-ufq@gcTfZH|hVItiJpH|`zkz}a zXb15GkUmxq&S@c_qbFrq7#KLAoAU2Zx3}}x*9M(f!3o`be-L!UA$0S-3_k+{C(`D7 z&iON@&$RQGtq1K_<6Hzb&8DD`?2A?-bnF=E)CG+r|;Q%d>WBdlP zk?%X`{5~~C&{_`>zM~*L>WoaFgGl+fKnDkMYA|wuP9o(C25Hh{G5?+!?lHlq~yBvKxhc+ehG7EtK(uz-S>hXr&%8V?I-yAcn|HLxrwjCff7fZ3ps z;9&vzoQK7doq>Vt8pv>6Mpw{j1-xvWMvN_>;{-sn+?=po_GX~1j~1f^M>32eKcw$zFp$fq{Xm=p6^>BvP)D zBG5^s|3SN$OF`y|d4aZggLm1B9R?W<-jgM^l$n8ns{)j=#N0rIEOe87C?5j@SG5r* z0|OH$3j+gJZ3pNe(nZq+ocv8xL3fkZ31|4-h9kja=x2P|}p;49G1VdxgY4A6c`q%DFx&@F;mAT^LJf^4A8$~>N+ zEG)tXI+cjW3sl|KOR((%?dtRfaa7nqOB{HhTLgE3j*svMIU2G>kS7q7VJ+A!K;l85 zGz{7zH~|!5zd&vb2CXg#Lq9pv{&1<)iXn=nW|8YHa4z~RWvzyLaZ8oWle zo|A#;C&-mCKHLlptUNqP+d!H@tKWH`TLce-JPq9<_yV+VITe&}SQwbnK%BHrP=K=3 zaxyTmD)1D8Rtti6{qaC|{efey^dP7%WCLBlzysa&7X=FLa?oW^41AENgKqoF1X%~& z_O}3ZYDN_(Xhay8{6K+RbDSG|PAE^^3Q*evwCj(j9>io|+X`|>18B{V0$VA_^Uz&? zyu1tyJWZfwSUPN(ps;QRrJV*g(3TpW`ZiEdv`E|sNpyp531DE8C;)k^2XsuF0h>e! zNPF)(P6mbz>Oq2_o(=;K3nbiSrNSmi!YlUlAHv?7NQyl~YWtnDo?1A{zR86z{u z9>yRA&@vk?MFs{%(0&S0MFu8@`_moW{9Won%Y0<7fmShpWd`MhI}8jAvY-Ub_>~!y zqW>~5FsOpf`VKWqMg`=6A7IsTj0_AilAx7|Kbb+*kRgZ_5p*Uhg92y`v4SE4 zgBob(jE*8`i&PX-kpu&S+&$1Tp37hl`++^&#LvJWD-CK7Uj{o1bVjsn*z`tse=%@C zGX^PwW|2WQfX?VrVvK_ALQn)b&Rmg!!I>XoK`{e^BIwX|Cq)K^Sg2T$iV`DeZ8(EE zXsZHKF+(9(BAS_tiIG7Kbe9Ck1SQ5OCeT7`xpN@rm4kZR3}v7#*o#c534A``HgJ%IgM!Ru4wE1(%(j8U%$JFQ zK_0YGnsFOA;u(V>(Y^x`?IDP01l3odXxuto(9>Vv78I(WrBPs4GcYKEx_haL3=DUn z?g4F303FQ0RK)NREELVm#mLB@2HKa{G`-f-U$%Za+$|HqZpi~(o)80C1~-uz)QSR~ zfCF*OWQc1J@fjxw4ib2L+AuIMfU->yL>#;=1hlz;shFV+ECjVZkb!{#lx#q*b}nLI zV2}eH?!uS=4k8eragMPNEQAuku6hJ_RRY*m%*?Q?k;LpgJ;uvl$^sM?|H0Nk(lBUm zVIe5nfi^4EfFeW)>|CZI256E}16?}OGJTzwzbyL?AqEC{X`bnqy!@3_z!^705j1BC zG8J_E8py3h3=E1!3=9k%iVO^Urb~MJ>(x(DWMBXtm*)W?ZP zJ_e-^xlB;GAqMs^sDsToXA@}OHK>`wD8>wG6)*p5VIknTh67#7{h4Bpa4qoU`K(DGXgoPa{9!lX=2mkef{~S|M&4{ zNqQOOeHVXrT8fe7+%=9=ve+`dJP~lq*D!D;M2!Voe&MgTB z25rzaB#hPOObiTlEDQ|Vkn#ppCd;rgFld9<6jy@^cx%uuP(hyQ=luMo>cM%g29)J$ zLBgQ+2xBeCIHrjVI!>SrSqrj?X(EdbsFB223o?*tB8Lv>>I23)P>Y6XB99)}y$v9L zF$U`=XQnVPHiEP*XJuee0F8ozg9MaQK|%5xwACEBHYoP@7gh(wzhW2z0|O{tWyK-! zTFL;4QAJQhf~}I(`5tw zWmw-TGBBK+ZWrh;Ru8fQYCHoE3#f5uuoJX8oDsY!6BO&9U}BsD+Or}HYThzJWOjjW zlmW*CGb1D_K&R_~k3I*jRstDW#K52cnz;gd50r^OVU;Nfb`_|0j%H#-)@P7!;0xI#i$*$z5C_c0TC(3R!p1Mu}9$6`)2nXj3IPg3`g>mo7?XV9Wp;qQ=g^pa5#y zfMP~14avIm!Tz%KFF~7JdccN)Y=oSm09x|{iGPR;s8cMv9TYh|j3Bu*b_NDWX!n7w zn*`#6+iv~f&_2e_zyNM0fkOAXG)m~I!I~$a04tiF9pW!9c1s2n#h{e95$uwi>NwDvs2^P{0`3Md|#xO{7{R9p`(6tFhpzKsE3-hodcvx^J z=(s^p;(>S=mV&!wQ9P^w%7Cg$3=EEnE}%xY5(5KhFFUBAY|Nkt3NKIsJ_ymoR3r*2 zxljr_(BU4S4E#eDk}?az{Dtd5fgmIYwuq@r0;H#ifk6$FfMH=$CIQ+(4a%c7;9Z}f zFaaIN$v9^VI7~n>43W7G3Jh=+VZ#KfBN&4r>B)`>RK9>t_=BgPW{8z+_0ZkEil8bB z?RpumVF3G(&Bm1QG+a?Lifb0Rw}9J;<;oaFYWR5TLV? z8Rw`fz^rWoI|y_e2_zk~fGuJSh8L}65L-a)PEgUx4`~g7j(h<{&F1M3KctCGSB>zO zgfuN`z*(Dt;Uh#MDZ*ch8=U7MkqL>&IT8M<^+j+u%m=#xbZ8dD4GSS|h*AUfaX^_D zsei*@zz6csHn0|uhd})u#yR`phCyV0aKW0gJ8&3Q58AWMV0?lXbcr3)B?b7-N)yn| zN@LK8X)Gt1UV+3x)-W)D#Z8$(r~5qqr2ylD4qoAz1nMxGfll87VOAfri<}G$Ak3Oz zp2ESv0K%M~7|pixGBAKJTdvts(0O@FK|{s9X35+P3?R&wXD-RhzyQJ=OuXj%xfvKh zm@|XX{5~fG0|;|IWi-=gV_?vq{x{NJt6o!pfdPa$Z!(${@h~ueFu$0^aef8{5H<&m zoq{muRz`~$P6h@LHV@@yU;tsx7)JA0Mg|5D=6J+o{+fe<0faf{Gny%JGBAKJTfW&B zMg|5DW~(=AWoKXjVYWiE3jz!b7kEGypw*dif<_lvw{ME_pP9b1wl(us;`P;IiY@eLWxLjm=MyLN7FGz{5<3HlU4q1JKw{5CVy{7B?|`sD6M+m27a$yP z;&_3?{({7205xWz4wXP+8z8Z5kk}qbZ1A-lP`wFA;;n3;#Y0dD&>fAifLe{D=*;xO zr)A=X;Qf|RrGJs6K__X$wCRB=aHtxq=^wB9mrEW&61s@QR-E2=&EJ|aYx>@6{^Iqm zpso~D<3uF(93=LBB=%_}_H`sS==5utW4tsIb2*4l;B}zgRYE%v5TkodP#}buSe1W+Mf=SK93}R8;SiKiTxRg{U3=9nuvs% z1Kw~6^#bU0SeUpisKhs6nEw2;zMv{-_82CS50L2 z(HEb7=ZiiM?{g%jpQj(Z5-wiP4H~P1S}l&m)<_8+o_&yD&IQTjZD7$p}+nfI4^?gW6LBr`V zd)_07|3YH3f~r~QMkCPuS+I*P(mgB}vw7{rEJX$N9M)p&u}CJd0g9tz?> zH~B>JGBAMh4=9dOK;lr%pv#FEp_)sO#Opz9s5tl*4ygJbkT`T_%LI^_P&RniB~;By z(7j@?JvEzwDA_Iltq|%YEA-#4N6E13}qk= zG#%C>u{)61paXjup_*5M#G!1^nSU?~c7ep9YokHOkP1WDCqd#+M_&Q4p^m#L3|ess zmH31t@g2m5it~eZ_d+#@fY?xRc@P^at^#61EptX<`yjECKy0WdvtewI|4U#T1_lQ3 z7G$VF%^-0o8+3sQEO#yfi9-!qjl|vvVnfyMLSkP4v7zd3BC#KdfHD$P;srGsnxG8( zK#HKjdlJf|MS zff`f@Vna26#i8t8B=Olu?3GCD10XikoTDH%)HCOh*iS%gXf%QMHiIq_1r-M0kR<+q z*ig-^pdGzXwj2`M7Kshsw+vMig(MEzs|-u9l^}7b#Z5@;4$#5Hj8M%hKoU^)9whcr zB=&6(8*0!KB=%b*_D>KSY7Q@G-!7ExjKubVv+Wrel0Y1&q1j065+rsNhz&KU4~e~g z`dWEA@p|wXsnFPZ1Cj>K=z&f!1??4vvVVibp=#JbduE}r1>QFd6_*5wL)GgdvCWX! zJ|H&KxuFm?BoW6!IG_k+$O5sU27&hqL)k4Laj0eeAht4CIm2Yo24E+Pa;X21F@kR?jW(BgV<2bZ$NCQn(rVsRQwN!4HahxZOny= z^MKe;hpNEXApe7R3_~TrJBFd`XqX}f28Mhjb~6&Y2Z=oui9HXAy#d6A2K!DV_8}<- z1|~+%>2=Tj#p_idp?P15fdO=s9f6_8YB+Y>W-b*d<8p4kY#*7<+o))?lbJSV3&4xB!R^6&D4uq2dZ4HdI^{#D?{)jUgPcZH`E6&_S@UiYO2y4h@Sa z5F2V}Du@j=Gz-LrI%J; z#0D7zS|WnPUV_Bl3SvXeIRIjVrmGnk7>>w+P6mN;&VwYNif+jJ>v`%OkPXKy0XI3_)yda9U?DH3e;zhH@N05>Q3nAT~540zho2cpQkW zJ>BoEzjzF2;t;g{1!M%2-3yY2DxCphLyedVVnfAOgV<2@2S9A7_zfiXhv{eE`it9g zgLW4~rTLNAVn}Q$B(@?FTXnkbJAd(dLnI*!B(@C_+Zl=Nj>PsuVh16yqmbBfNbEEu zb{2#UiC^$GY^XoVAQIs4uSH@vBC$J>*u6+>@V0HJIWv*O7b3BjBC*$kTI{g=zY$3S zyyqKg&>kdl@cwV8_)#SBvq|03eM=&<15AzJhVPIf*hs6Fg{qB2zamjy3 zLad-2*iid9r}KXB7xxrF5|Tz@%OkPDyUn56w2;INk=Ul&4L|rhTXCjzFo3RJW@wro zxZ78L`hkry64N)#l@wqsn0{0%z@M|GgMk6GjHYS2<0Aq2=>fAuSf)E@2dFUan4YQ~ z;Ljw{IenXU0B9E1e!_%q2&pT5j2z>l$H`d5(Xp6RaUAkkUVrk~^rIkZ%XCqz0MOpSR1oDeeJhA6n9gb);LkW^dZ=}P zHlywIM(Y4&)*WjY7`{wjX&s=<#Aq@7oOOU2tDH3hgVFSdUqywd^VkFkFs_*{YZIW( z8sNsj@B*?eFUBT7fJx=S^gNpYHC79E(6z{npi7nih$;v$E||U-tlWcv!31&*^B<5Y z3#Rkh2B@>PgfTGOo^ELy0J;e|79=t&9efjVB(KQyxwZlPte4V3N5~r%TZv5fZ1Cb| z{4@QkZGbxCqUnEa1JrpwoF)%RHPdC)fl3^)jU=RcE0OaMUWnj3#&cM*j zz`zhZ{o*rzX~rAV=h_9pZ%W?ySXqL_+!VC)Z;`adc0v1qY)0`LplM-nF~P!E23o}4 z!NkBYgL%4tzN`dqJ7{wn6T3EO_g%#F9S#9<^)a9=dQ7avpgVU#*B~;988a|2usi_m zIgkRCx6B-@E#OUk?4S#UnORs9n80`Mf@Tg`S(sVaLCd|_SeAiCC>c3YL3`=0fNnn) z0j-5$xdF0K6tpmx#Se6mvSKR8bkODrW?j&FOAi)l(0#aypc95!ZZR`3uqYh{sQ}G0 zvM8SeF+o?1v8b&DF+q3gvSo3DzT%RgmE$ZYz$S2j zmaej#1hLsTf~KE!43Oqc1=)349JFUbfMt5-MPCJ`k1W%>FZwFigEo?|WHW;AVc`eu zePPJ~a~SzSC&shnGQI~nfZrQ*=W-sH!@&3QXIil2DS1N?zoG?AlH9*3m1tdS=66khh5B6#IL3=bobDZqcLCP37ltI@k z&j5uY6DR1dM)sK?aTboq>HAy*#Opz87})24q!l;sc8X1o%PQ_&^B;94-(7WGVy8HBbN@k^=4Z(*h|1nFE$* zU@-%2ayfAjboY8cXw&O?2aqbz?ZjXOf*=+H8w)5rSb9NfuYnY>yat(gHwUD)2DIxC zq8Q|E2A0>L(0u~3jl~?~(pR9HC(rfFCcnB5z4^B3(Aq~ zj39$~EJ18ZMvy^#I_wIJpv!Rii$Q{lU^W9k=oVUbCB}TvIn*rtp!;swl^IJx+Xwjz zK@L=51nrFG;V%KXNR_b>w0)3Y2oz*$jP0Oni1~km;#-}umz{w@f}a)SKMlsopcRSy zCqOcq;2VM!_&0;1ON((nI|G9Xzdk4_XfrNl2i?)j#`21lfuWv_1r+*hETG_JV=)Eg z29_`|nFuC9fyBnr4rYTwf{g{_b2gSEpq*%{pu$|2@d6tI10Nf^5hFhb0|P(kS{-&{ za52olpAU)}6EKI7e>*5pO~D){{^KBySv{D?%r6V_wK!fy)VSb#aK3_PGsR_s=c z+d;)K=)iD}SWv*SfG!~8NHzp*A9UnkV1UF0xL9WQ;z-W}?XVRAZLP`xr5Oee(49ma znc#wo19agOM;0j8a?~@hq=0Tn&IXym&cTtp38XO_l!@{n8l6Dwd=Q(715{gZ6oA+) z9H6xk9EBh@8w1N+&<5k8O7QMMj*`C|3=CqRZPy&7AmhYpL7RWeKz56Pu3qLS2k8<6 ztx4giuK=YiF%D4FS3=VK6p*W{_kzm&_sk3o9JRur?Ss0U3=D#xWGV>K0P!tobv6S# z52sBOXshu}&>mo0a0qZ{f|f|xf!Hh@6G8h??Lk&@Ft98FZ7p>G8OGBFT8&%J2ri@8 z1-NAofed-c&A`Ad2hzyE;ljwkz%36FX5j$sgXdNNu{k(igSJa6f(+#0Sk1}6z^w#w zI3LF&4h9BpWsn>B8Q56VKptRbVqoA_DFmhB5N>rIP<^!#q+0`I5(9@HV?6@{wXU;GjU`vGca&Ff*i}j5f5^p6Nt^m!3%PkGb?Db1P6yDh~om%z{&Ar`dzO8 z@%jdkT6d6IAr5hnCp|%~5#i7Q1&S9az$G|9=i_sGgV-vd2xQ>)1=TJF98n;*_=B8i z!kL_w&cGcADupaKK!cRrL7+_1z`({L4GN%{pl$iVvRn)d;x(+?p{k&`f5gJTP|qE? z8ngg}<0m@<19vn?T!(=Rw9L?yn}LCM0s{jBCj*Nj$f6i#P^rYjos3JRJU@;032)Xq;Dof<}O2Iw(3SL2N+|FIENy?kZ5wh%m4ygEZ8D zb`y$kVdt)k2W>hAZBOK`2Qe8qBtc=_kk7-wpuq8*fq{X$@g}G*t-&!L2w4u7Wr{pu52g*d!i++|UbZ+iqZI-~u(P zKvsamj*)?@o`-<}grR&kmH^OhUQif!L$l=o&@Cb52YqX1_nh5Pyu|B=@3X9q>zCDEDoMc;GP5uBbD!53=H3=FZ3*M znx1gaciwcHf>g2X2L1tS*-+MLPJbA~EV=z_Xn;R6%8JbG&XEBNMJ3fiD=L9`utD4N7#N}< z9B?>*dSQ%E&7k%SjNOf-26SQqOnmqBTKNWX#>>-VIYPx%Un8jk-5Cv2r45R8sHtYt zeSJj4ZIh6MYLVC-NbGq??43yLqth1_1e7!SPrsX&BtHGdB~_m3HiZEO(>dNc^GvTO z4B(l*r!`E1QGI&sWmWy@C*C^qs5WsR&J*oJV$VWiFPpwsu|Zt*7?RLMB=#L7_VejK zFRLoobAq}zFn=MjLEQqF-$6S8VC-llHEBrfDkOFr5_=L7dma*d6@(2LRNV&QfTIt5 z^99sFcaX$iOg|eKCN9YU${tW@&=J!xcd1QR3v+2IUVdA{JpjD7iM@mj#8yqG+{Z4Qg4`b+b#*i>^ zUeNY-m<^Ms7oJHJuV0O%V>=T2FcSMb68jDk`wtQubg~Z2Xc5r5NT@3mkk~p%Yzqi` z`u&ms)_U+7O{j(-hy*xFmLah>BC&Ua*wDq6`*{#Y#h(I+L(RDYVnfU1he+&aAU0Gl zJ7`IwAaqs^vSf)`stIpEctP(_s>&7i{x7#J8pyEtH{w|9WVp=u_9*igMQKy0Y^ z1|&9k(I!;CSwK4*?g-XKHIT`{4SZ`>9hR$Rg z0+bmuraLwSsI$5WGB8|*4B9m`1PCy$m_89C47#1#0wR0?B>ZFgLy&Nw5Cek-L|CCQ zK!7o2x?y90I%}m61H;wn;A6lFK*C3+H-d!y#26SBPJeh=L3sKBknsEI7eT^W%HZ)l zJx1Z_0!;w|j7ifKn*!7s_e}Q$QB~6mLDYlkGeK0^^n)PEW%^4HWinl`88KE@*uW*R zJ+e8V>na=c;4aYUT{~lBU^`=E(00bi;6;uw8L--evx1cb8MkeJvO2gZgwbefVTduK z+4P6n)#5DXW+oO}mxVlIV>UBlnBMR|SaSLb_7DL^i|ISrL)51CvWIX@f5{#q%Wh=A zke*mlGW~#Eq{wzfj*v&OC{`$@h2-lnPMtn+Qiw9+>g`)6g#;N*chrzQx&6Y?kO?eI z#wOd7PKBr@AZZfczCE zsTO54ozB>zCd_PUU^2aNrUi&$JbmFRo2S#?-3%3&?Dt<_Iv;9tN09Mf|* zm5M{cV#AZD7EUH(lj*+Oqa>#Ly^G>zvM`(;P@^s-fb1*_Gjogf)^}0cTi->`Qa zneVdrcE^9wQ#=^AZNKIgbIFf!>hzUUV}9~7ak`pvFff2HU*zG-thTGr_Wk-SpV-_?c-Oy74!#bNra z`y5W&O|~VAbMspu0^Hol)Sx};VDk2;gDF>S;8vW|&5~d;FrI#4ZkQ(H-0fBWQj`?L zZv`MuowL$lVBirFWnlQI4jz53_cjEbCdb|@$-uyJ%z%M`Nf31IDl;S70+5J5Xyi`_ zv_YJikt3QLq?GlCAp-*o=!#?LsC2Fx0|S#JXiWo4Ifw}xpx&&@z`)GGzC{x>GR;~m z3!>P=BpDdM1JpVS3=GVS9D=fn3=AxwD;Jm{W7Cb(qvcZ-c<#zEFfi+a+O{kX)7#}! z6~sa7HCfa^ZCDo2`f3)9%b>B}m(%yjry5F~)?{E{IdK9c!d?iz#SX+~W1pio-LWNC ziU)K8H_K@wQ0J~`y1qiHE|Z?h^mTWfq?qiqr=MG^B_)}q!oa}d#P}Sfq(_2*fyEWV zem|XYotE_U6AGysj55085r1X!5j{LD@6tdHajqfhk<(n9|HrMJ!?5=JpZZ?0|R>($S{^T(D;bwUQp2G zPw!Jol~MvNh~a1gOM(u_;b>K4VPFu{VPRkp;szbt!J;_*lv1jctF0;n1IHu-(9kLy zhdxsoXlT`2o`HeGfQcV;Q~`epXneyE%wcBWJ}u0^z+uD`#KOQJ%En>Jw1kC$LG1Q) zP32T84bWx*4qGOWos9gvG7JnHc3=(@|6vsd1`c~B1<>>Y|MltJ%BgC$Md}O;906bj zdfI$67&ubF=E(Bb@iH)Qq=7kd{3nDM7&y|w9C-##Q0#Dl#?)qmdX)^^_MmQeCX)ha z_#Si)T^{Ht!}Hn<3>*baAaxA;-(&nfX6gXUJsnLaQxFx0E? zbAcRR0k$WVAAH(SC76@Ozztey%~8W71{%L(;%Hz3bsqRDq!<`D8kwGg4z}P2ow>o$ z1Xj<;z`X`Ekk!mo1sb$ir^mp+v6u;T4WA%rW4RER*a^D-n3o0QLOu?TGfefMZD9O& zL>L%2&Vo&0;NJ@xXF3PwFhb(tJR}|%xWzz8?E=#okooN(^SPKoG0qKIgU-Rt42n8F z2@Y}QHg*OEe$dtd4hd#XQ1gqwK$n4mLy~zdXaM{ChwN#tO_~V&Dz~X|`qto%_be!(qn^noEPY!yc*`>~jaGJ3eYLFmO16HFJPN zy`IAf%;RL>eq_kNz~Rgc8f+1j;BaML2^ysYyTc7^l$Zi24Y`8@R}6Fy1&0UN+hVUl zVc`jOw^$#@0xz&L7`U52$-$dB88mz&CJD-N%m+b3v7kfmgg^uXuOJOoFo=VqSe$cu;&v_R>2lk(*aZtk85lTZS(Q1Vl8)0?tEWl| zwSY2=DyuI{xB#q2mUjmzFYB?^fJR6sPSZ#gsRy0$%wfSg7p8JICj)~JD9(`xP<_O} ztqJmiJGj*376WCQ5D0rJNIVb1{vyc0z)=on^Ko%hv6^u)Fz`PF`L~)CRDdw>2ZCHs z!+IPvv&FwasU9?H%L>{*%g$c{D%9#&LF1Mj{BCj#3>@{Wpwfbqf%_cDjs{lHtOFk> zM>8wvs(FaHEy(7!!p&u1;AlfOwjE+D1GfVxhB{cCKqq=eaCFzRf_CFUjOu|J1uo-y zSwZD48-J$)0|Q4NE2x0r;Hgdq9ry;+Vk-nlyp9WhSy)W+A&}HpDFq z+FW!L6yrA))3IZ zXFn+5*Rg_98Xr5yM%HuOuqfOFHFg)Myx+_U+Gfbcz%2(F&)>od+Gxn9$g!Q3ori$| zQZVjd1s9A0$qXDjS-*phJ`gBk;MfIb3Nmnaf=ZG4-K@8`85sDyIQFr+fOLWr%YLX$ z;Fvgo?16)<;Fw_G{sIcgL#&`{n)tjqj41DYy=UDf_-Ekgj6sSh$xB!l7HU{o3pi=)L>nt7y2GIzP%dDXL9L3&( z+;at-;KhtUL3ouFlt{%s8Za<$Tmz>vv7?|m={h)~#Fm3n&kfdkP?U>tf)d$Ha8Qe# z2Zin}a4?FwffU^a2aK3MDB<1#`%?_;p1WX&GH?fjG~8nab?muMgETy51#Nx=mlYMD z>v_Rh8pLAYWdXUBI}22IJY((RWnfSioDWh0&hVfp7XlFs-1(rg>mBQAUIqriqto?u zQYGt|K#u>)3fj^rcn72h9J$=PG#D5-IM_hixC>c9N9jV?=Rg&_1endo#-Yg;!N&m2 z{90_F%+J8T094s(gH

^1cq+7tk5V{7j%~PZuo1%zpsXg3)8Ee*s$e!M|6Tfq_Gx z4a8w(;PwJlQ3h-bd<+bHEF30mi$Ioa2L+}nST_UzJy7{*2IesG%YZbSvw_MKCjLpF zHjV|D!_2@P4r&HjvZa7blHssr12xtJa!RrpIPBO!NtdCXe=8`Q?b$%90R;H#LDB8N z1}di|AeK0SEs^4X2`b>6z#M4??l4fJ$C+&%$Xp2yH#ReV1_pj>Pw}toY@pI#kb(O> zC~G9JUE^n95S8IbVv7`DU=UjgN-N3WFc+H%3ceI@IEit9!YLJOfml6g28$yN90Xz? zKxr`@>ZnvUv!C z!;pca4HATq@N5Tj1O!qtvKi_*I>0;y2JWk%%D0P6LXd$$)PSRhtyGYKL2N51ZTEr= zl1MFL;OGOZX5elDO_%nwg$Ob*aHoLs)fBc~K?VlFxgZCDa;*@E#lXt~GKEipV>X+p z5Ca4M3Q($?17fD(l`mv77Ghu!;ST}D@DeslAOkQnB2b=85lVBgVQN@n=AtZ z$4M}okBj3f+ZK>BauX{UIIe+HHG@EIW*!5_bufpC-yM{OZh$!~{Gem+IBtSDZ2Tuc zmE$e8Sda%9xEnxCn%ivknL-Q<+{Zy}%m-{|gcukEp9#TQN}z!_aFY#Eda|rgWnkb` z2X*EoKQc2gC~)d#2{SOTgD%44)B`aY*pGtF0M-YwS=jACr!*TBfU0wLKRE^lPD4@9 zLMrxqQVa~7Mj*BTyK2240|TcqsK^jupQFaWz-aH)Et*lSf87`S>tMzgTr0G&|W2V%2v$U|{p$ng;3(vCkG~VBq4M4pP9t<Yhh*7FleTo_b1J_)Tm=e3CIs*gOJW#Q& z!U0-|rW#1wAO-gqu{Mvxo0PjNCZa0xJi zc3g5_0O^xt1UZ0Dhf9HRg;+fU1Aipwglt8|6`)=+KWIrLmlESTF;Hod0tx|T#x0e+L8;sV%wc8VE(J+h zF@iQq3TBDJ3J-9!a)U0?7Coxc}V_pan+6Gb%j~yX!Y;uDx zIp^BW4B9ZsC&RUySxSO|fu9$YZ1;fK4E&%zKG$Am(0QsX{3;;l?qgPyU|`_j&sJh! z;M&g&$|pSh3w0S7xDJB5Es7`VAWyCS7POkoz#f?6KeZV3hkkxJ0!3z5g5+nPi`(|t@Lm-RqPG~Gd0 zM~GyJF)*--{E=Z`U=ul}0a~J23~J~xuz>dX@c4U3)H5(ZjSD^wGVUj6xI{z_w5LVH zK?^j%ry&3`&IYvBR|ItBH7f&452)abng$wkoTbUYz%vKbQf8~*nRiW+fr0%U=s@oI zpy*;?pDMz@z_S3vW@KL@%fP?`E*qHG#bp>6cow~6U=UznW`7DgVR)d8%eOD3%1+x2Q5O@N5E= zxgzX!S_}+4n?Y;^_BVPA3_M#vY#nwHIR*xvZJ-V87VIpB3=BNmLF@u&wyFO?Q^&gND4)#_>1_qwLAT|&C36NX=flL$N z-v_GR85lvfiSR2bFfj1cGlF?y{70l17*%-AM z85nH%L5l!*c)>ZrmS0tcfq{n)%(3I=&;b<&V2(XMs08K_26G(vvq8g9qKtP$7#Ljm z?Lh;6VvNs47#Mo^Ka1BhFz|?jr6%xS0v*{c$p{L{8~h(ZUXWr0`SS_Cj1mI_k2Kh& z&-g)ST=2*;?i6NVc)?!-(j&)sM3{l$CI3E<9(ge56~7tC-%8-@{+d4$6iLdApw#n4 zMgVjphzi)WoO(tXCS?W&9#t?mk5OhSNTnLs%3=BNcjG+9&0*RSeaLjOk$M1OJz(#5CXMoas0;8`S1A`8~ z3@D8!F}lk!FqrV`fr2F&tj7X8;K-B02x_@U@Ed|Wp9XeyoIqyE^#4|=T%!9y@tpw{ zOyCF2Q1fImE}kxDoho0y9%O7T*uotCmmrVigE@Kp7NAHe0CNiXlR(M12<-eK{z`cU z2A&cyrKSDe+ejX%NbY7F)-Bd2Z3ZN8Ba4ZFf{P1i8C

5{cKPOH#4r6V_=xTF9%9SZH%D3cT;4vK?b#hT_VCL0~*!j z>0$(rYBI{a2AwS5!wBlbh(lwd7pzi(QRWXQ`%DHqO^Q**#fX7{XDV1uhEYZgwebpEkcmly3P6lpfT?Pi8AjU{Jkdr_S2woNo2@w0c zC<6m0D4Bpf!2=q5muKJvS#%YYXhD1?25whSo?Xlc@{nABD9>`n%?b<*{AcSy2ji~* zTfxAe1v-L%B{+zf_^*Sq|7tLYh2IWTw5$Ph*!Yj>GcfS11*ZlM{<)y@{MUmyoct?6 zDQF|uXdW47P{Q2A2)cXp1G5ZhG=pa|<7EW~h70^M@t{PwmC;>JiGiU&P$m%+H`~BL zP$DRE4^(>Z0K2I|P^MwJfL*F)y&ot=?**r=20GBS#lJ!>&7#Mh)z`o$&zb(ta zz}pN~$H(ul&A`Ch0_N~DaQCP&Fz~iAf=+Pd1lbBY!x!vkMh0%seYL!j;0XZkm!RzE z$tM^@4mV#{L^Lan&cm%)lVdeomc%fv+F5i&T#NyBY%n-vp2^<=J^b zqf`??Rk;HD8IV&ZzXUBVbzs-gV_@K$0&=b+ySESn1K)Izq4n(6An_R>b_4rV2?hqf znIO-$u(OIXF!0R+ZAaa}4%!sXHwR?s7WN8|_veBvyTT5-?VN8ONbgnl?)+N(Z_B_k7v#MKm7x3Hbfg#<_?Cd~ZWa8a%)lT7>a&6g1{NWG2GE65 zDxi*;3Il@>sO<}pVzc2}*`>n3zz#Z7kZ%cWQOR$H^GcfRN0{IU#m;t(C zmX`(OHkM183=Djm#Z?#>*f{vM-vT+{6DVAEfFhHDJssq$ogg+7JLsf!zFi;tULYdu0}aCe-y=7#R4@fC7x=m?Q%O-(@iK*7SPkRLOdORR#wBbWqf= zGJ@C){Gl?Sjte6=LGs6lfX24L`GAAp3zVcdz#LA{XbWhPsR^WjlTlEWfq{>ckDGBm z$UIQnf{zDWaxm~O2DytD%wgmQH81)2z~vMZ{|63+>EbS_LiLHN3=G`;f(#6N;$YL| z?lAJnF-og5Fz{ahMVvfXlz|^K+0UoK2#RDDesv`V20nGLsyqA!+6)YQ8jPUJOds%r z4u{~=1ed-~WJF{c82EG;L0OiCQRWJ0#zYs~9^hb<*#!zEJ;r*_hzJj(4Cn|zK7B@Y zbp{3jMwywQG-m|1S%guBk(Ysi&zSM43Il^EqYUVxR6bL1%Ta<+rWO<KTm9GDw0&1VjJO_0#-5GV&85n9AWg-kg(;)+ zWnf@Q2XzQ_L(~}hgIWWk(F!KAcO$PP5>ZX5mO%;~}P5JW&f|4Bzdzmf+ z1Ah=GKd`YMov!GXDxP@<6p3LVX%0q(K2`<>{%{b7i&4Qshk=1V0>t5AR7f@i4F-VB zDqHAaQSprQF_5J#O+0hF-#V?mirgHZw0vgD5g$!IbvbWdOCmMSUz zMv8%fKNlpX!>9minDG~Y+GVR1*0rr(3eO;hz zEW%y@a%(q8+=P8GNPRCz+=3lEXx;}Bk6^E4U|`^{p8%4GVFy)y{1ZVEHSC7M3=I5} zLE;VUt)Nl%DIoC$>>>y|JPX~z~VfP0G<}8r-33gLZh|LCxzhHl_!oa{k z540xW4Lj)a3jX;Z@h|KXK@F-!AoV{K>TiQwu^1#F!KeV5E#qGbnzoc-RB(}HVBlW~ zl2Kq(c%a3=zz;6qR2UUh#26U(*Ml0&T8s*yVPpP{py6jDMun}QNZtgR?nq)(0L@$S z?*mQM6fr7*rZ@TbgJx!n85JZ!K0E-5z4{VRniK==rqR=4U;troJTNivvVhjOuuK9e zJ-kJOfq{*O|4M=u0|WbX(9)KxpsdQk4k||YZ-NpU3j>Ru1_J~CEqg5n2DTFZI~zc1 z*+7dI?n2ap_1y!pS=b+f!t!w*8))_zJnG5+1mv6oa0SEv9KUv2A z2L6wr^dv9B&;Pkshk=2eUyp%-{|hLD7}yVi78?8n1u6@;LgxPsO3*6c3Yq^8h^@xn zD$l^c{};s8V808R*Z%iKo`Hcui#-vP1O9^~bohlpNe$9d*5mh>zQr?Dfql0YsB5)z z`fblt$@;yZ5a9ura5ns)%?$j!;Ihwwzd(e6fu9d7%Zp9)F}0$>>* zel1X33WAHi0De&A$}a*gB18DAK%phd2=ZJBKd74K7X!D6D)>S5G`~2Aqsvgme-D(s zB^W2`Ffi1}d;=vpNk$G<28KU;GAE@O82F_aL5o}1`DOB^FYrp0uFnAZNe*1v@$t)8 zfE)uU$@%$Z{FNCP_!Ys0odCZKs7~kC0`mmF^H11}3G zF>r!n8C0==Q;j?WcO%Gf1IA-o3=G_$dja?z8Ru(&ifjk|#f-WjcmEebI;3S`3+mp0N(@m3?$@BH?Tw7P zK{Zvl#!2tIVlX>-$712&KT{O>_AcLvO1=Lb#F@t*}Nn`fPsO9Ul}C*g%Q-O;@}63O!9vPdya?yJ;FH%s_`g1w;tUaH3bixE^Fs`0M_CG6jfw;352H2E_? zwaXu{!z}qh$GGwHftQ0>@pploAOKztX2UN4%Bq4)pxUgKA6%IUftO-UXZK6xmk|b) z!;0WFWz+c=f(kV?FlPoom%wx*zf{%CFi`cP1s0qqP@HSRz;6cDKOejdgx{PARJbkx zuNL9AU;-7c3;F+n46+34S;T)Fl;EwvoW=a_K_!Ac*quxGXMqC50c_eb{_WEb_@%1V zvx5o-FQ&D63=FFTl5$cR_+YU5?KD|E5p$PgV54V8Fn@?JfhVu)(VMjQD3T zZ33CP7*s0F1hX0VOF^EU#RQtqljCOvCG*+fV9?;#02S+V!5l4q=jn_Asgm{JGH4-_ zi6H}n0slr&=2--Gk0Apm$b>_np%kcxu7j*z%;W%SadGf3WBLTLdI_i$T@Ge5@TY?+ z=M`Ybu`uwm901J$mV(Ntl}zUh85p?FgLE7L%gd>#@PB3sRx@Q_5J*l-XW;(=4j=~p zo1l34$rNnLzz`<05Y){0#S}Mve?Y2I{aR3R`^O~8&cNWtB2x(B{bx!xWnl1NkqHK^ zLSbRfG-Y7$VUbY*6;-Uvm8J{~PgrEMLBY%h?yUY{k(mH0irB%tzbrE6L8kC9n}Bxj zu*!h$uH+YD2DK0?*kss2CAkQApg)8|=1)B+LPeQD1yvY_3}{IMzZh6Djzb2tjDcSq zY-j?94Cs6#ehFq!uRMuECIpl&Wxy(nIAn4`89^4zE8&n?1>z|)g9`Nu4n@$&G`~Kx zs}KW2kGRY$P=##7+-b_dutr>Fp%iH5$b@;mDFee6aha{4STi&kf4CriQeseJIj<^g9C?{Bec@M;8LO==2670|?;xb*J=zaZnIw=4y}<#bA^{$B zu}$QBwwn zH_9?ILH)BJW>C}VgR;ydP%;l@1{HPRlx588LG9O2uoXX*WmbTSqb&0jR8B;Kd4H8pl;$;EiCxdLu(?a*IC$gEWeSA%iOD zI;8pj3=H~Ei4q0|4bULaYJac^jK&NMn*N|8E)zg;1d0)m_ZjEZTf+RB0P?H72qOc7 z)_ENU2F3(XD;#udiq_2Ozrs?rlEFcc3%nOsXqpxz2k zl~R6g3ic9naYG#ggJ!5A0|R3}%u}FC+ZgBEm@XcXs-zBf@I;V*W2j{5vd}4VEaHffr0GPo_-)ARc!iNY0OjaA@G1F{gDm*g1qZcNXKOqF1Bw`O3_dN{o+GF7%7 z?8Jj0Co)EX8t34Uf+R>tGH1}73_5u65-2i2u?E^g%{b>H$cQ^)3=E8yK(SWH%)p=n z>e@420(I>fgCWWF3dr2m%nS_LpmltVS3zd%1KoZJ%2Xh)Z&$Vk2PHUdMza<(aQv5I z0FCv4le7jXhZXumLOw1kRjmH0E&~I&smB1?j?6fx)`o$>5VU!p@g>L^-bf*}Dkrn957DjNfqXydfJ|}0oP;{zMy_g{b10xf-pvhrjU{HPnN+1w^FNmKe z1D9XN!oXkxb}$Pg*u^0xZ$am|u`+@xQpRv_qCW4>z@TUgad0sMgF5J%S#V+jrC(6| zS3@Kj4b>Qhm{bjk&;ASyqIMv+L^GN&sDftXK?dkeUl@}r0?9I< z;tr%G)eaJIH)B$TAu^z~L?D?tP#J;PRAJ@+{tOHoz$Qj9m2fbq&trs^XP|}GAl1L2 zs-t65)m1>{sFXd(e$Yj!YK-yl(o~g)iGhJDfPukf`m)$mRWnez6An?yXuzPM!oDerz*Zw-0o0-c#e$*3bj6rd5gkhg1_n?_ zdO;P!qXJY{fukY{S^_jWK*IHFT&gfQKBj=Rfa3#{>p`ZhovsiMi;o#leNUkJZpNhY z)vJPbZh#Wj53pwN4aBOqKqsRFFfhnCB0JVVjWHISKjT3e1$62HC>%{7Y8XvGrGz1a zI_UaFaBT-F)j`=L5TXE75UGL+M^H_a1r;mShE_!yTA<^&p!E~z`Zl9EpjvM|I8%X= zH{+aw=>iFTp{jINJ*7svI+nzt7ouu1No^5+*t(GT8BW%YL34LEXbO`K?XW+0g`1~m_P;Y zE=~ppE6_PojIB%{wJM;g3C1>XNZjCLU{C=~PB6BE`QJDh7)&fcHDCv18`s1DlY5}D zyOZhV^cyLu(kh_r)#wHe2~ew%K^@c(0jC|%VS^yI?{I^-T_-hFI4CH9f#C*3In%@d zHO6R=CP<4-6?C3pbN~axYlu9fA%iODthe+41_oAluniC`OcTQxR6z&bfwHLV^ogmd z!e+$*3=9SkMW76Phk=0s)J}7O2!SpfRDTUkUaFv5+d&Sic856ZeQK&OYkdId%4qhq zR2yZG#tTRqF=B(=1ER4yEmc?^8X;z(*hV6xI95FhbRXn`bD5s zVMa}$7RVRSE=~r}f#8gDtU(R~P2e+r0jG<%psS#a0*x3L7(r*FF)+LWC%xy>FQlg` z1;&GV7yRJv<1%gr21xNDzziy0zJT~gK}+HU!Sb>^3=Asg5PSy^UmDbc76QwIj{Z?u zKixSa)fkd9K_}&aBG1ta5(l#~QuQD*t&EVyV=GkVO-8B$L}n9I<}g&oATw2pYh3^X zgT@U|G))i5OjT!8pI(!h>Zc1X3hTjcb>L%ww3$E!UbZ(ppj1Hx-p&99hDFoAXTnMh z&_(kgcir@cxXU*yRao_C00YBkxJEU`XeJJ826a$f1D41emwm|R;r2;s5yPh2iBYhty%}S8dX8r3}oL9ABcYC>{OZhi;%h>l&7FGXdtcN zhOs1r9>{bfQ0tNL1h{PuXAz2gX$}=r$KE1SabJpcB+a7NH^Gt>I`}y z$C&;VU|?VbodCzcFblL_cFsLN1_tFj(>-%i^*O+y^O*VZ^oE>N2?fMlVa4NxWk zHAHNuZ^(hQ3_#b#f&!|=4-!x>a#EEgK$W;U=+1YLlT^#V@xZ`v7OKP|H&v!y-3ROe zP|*Q#mvyBPXq!3HH$MgjHptmYdUF{W7_9fnGBB{5Wa9H@U|<6k!wd{yahpe=sXjiY z{|XEYHsZ_-4E#CFpw7K5=!AO^=HJR}XDi9T0Kx*nwoF0{3?M9ci^+C6=sfZ1ptU@i zOt$5k3=AO5m&s^XFU7zB!mK`apm}-_W=*j3VP;?eVIeWwo$?F}AS`%+$@a7&0|N;2 zs4>}o(qUi#VIEZ`+f7Og3?R&x#b|3F!@vN-{Og!)BN-VOK$s_=$+liVoPhy^`TsK8 zdJ8ZxfH03TlkI6G1_lu37iY0GlV)H5VV+zjJ0{Q;b|VG`;g`0cwQ3;DKb6_G&5(fs zg!y(c+Jf#%2VuU2jJBX82*Nz-Otxzz85lsA$AZarDl-EE2v5J5m#UhXs>i?p!hEM0 zZGWgTFo3Y&X(qe4p{+5==&>5Zcga`a?CteUcbJN8oC$cdxz=Y-_u~$#el}!^je2gUY0g3$&iOmJ- zG(v3_o4!>x&3*cg%nAv{_UWQ>Y08q@kfaYIu`f;!luHwr{EQ^T0IDXTCh<*gluJ`K zv_%pEU84jnhGkuhZ7Nmpo8ETwLy2HF)%P(L6Uedy;eR=Us48i;1g6I=v)n$dFIoP%BLwy zrXfieBe5H&Gb*ITPY+m_&SMKYwiTw02XuTB)Hu)yf-rH=I$0Ro8cB`k^py%}%8V7$ z&nl#e8%{=&nUBQYg2X?KHS@ZnHU<3I;O!JH311PUtt07?BDB=!#^HVZE}Hl|3>pf8 z845o52`UcSaSam(ANB+l2i?{Q69?bK2^C)eu>f55A46i_MPk2%upt%1*XdK0(yS%z z_`nVW>+?opM^1mKl%_1%fh05)iM@Ebs&bn0^gT<`dFtOFiG%NyggS{I)H8sxWsumK zNNjT?b{Z197>V78#GZ!4-T+~P7TYl}?1gZ^{y2@qev8EZg~a9nRq#;9$s(~qw@<^u z*Az+I5s3}H5E8043be-#rXe3mQ4JD%0up;E5_=;OdoL3EBog}(68jwz+fxu4aiCif z;$R#G28J>ucGL8?Drv!nzmbGEgrNEu7#Q4;*g;6_xaozeY2x*>kc5^av9}_z4Lh4S<}>TEpI_lRfl@Ge7= zJUIQWc$T>28ziA0NNkqrtQu+MynUeVHPqjlJ zblppt;*!}&Ler4g+o$ttrdiiBfChu1I=~mfLD{-U;+9Bk7bJEl5<41+oruH+EzyJJ zxm+aiVh9^jB2+>+;IOMlVz(l(LFX*N3|fpNz7mPO9*MmbiM<<%eGrL#LINp3E+a`i zo32}4AzuFvNr(&7ON9mw=ztTLTa=K*^^n+BNNhJGb`TOf4v7uEj1Fpk8AKcsI86`^ zIB@!q*t3w>%aGWckl6c>*r$-#*OAz-kl0M1t~AsU(o#r)qlP45Jl(gVLR``tNhlnN zojiS~cG`PM@NH^Pql!UeZcujPblb`banHF(Lg0(hpwc^$#E&DfuOhJ@Be8!>SJX|5 z=S>97A3%-Bo8GINcD+6YG(`gyDnw$}Be8pt*t3z?E0NgSk=RF(*q4#m;Jdn@cD;v) zLoROq3*mqxPXaV<0ac`n#I{0W`%RbBPg7Q{MH1>lV$VQgUz?t&pB7vXy3`7m7TrPD zLqTl_MPh^Rv4V;hB8k@{v3rr&vys>HCSGKZO?3lpDiXqZ-Ae;CGPU|_g_#J-2b{)NP50}YBot$xA!S4`%OSBr zhik%&GeZ)0LSp+Nv7?aKX-Mp%=?Cj8#Ou3|gr*^}7a_6NA+dKMv9BYsA0e^-BC!=z z5Z=&1VuO}^GHQd)3SwYja6ys?Kw`%ru``g^bx7>#NbFTe>}^QwLr84UAu_P=yRCv$ z-abQ8^l`duV}&>)`*cT>G-XLsRfHd$kl10G)WWZU4SIBX8KW+H0%0r zNJ7kN2tx#s*z!nhT_m zLt?K&V(&v@pF(0^Lt=wQ_h2#o4oUnM5}QpEVHaqfHKR7e^yZcd!9*=22{R-%=$uEG zp?*l>QAq4GBz6%JyAFxnHJ#BSExZ07k`T8R!Y!sqY!4)M2ogIHiCu!kZa`x9AhBm4 zv6n#DkWR!#2nU=(_8_q@AhGWtv0osuzaX(0KqqBFi&!2cw#4*6%e2$=Uyy_tK`U#Z zO8Jr4vPf*uibPmYTOx_OBe6q~*vUw2@Nz1s`SlQSA+Z0JKsaFbhUsgq(!_Z$Aqm}| ze$gsTnO7Jzy#m#)Fnw)%h4^#{>ofz#DbsDO)5NDISf?3CzDH8?2Z_x!eWi6;wkqfV zMVRZS=pkZu5fXddbW5AG-@GS43&)_gU7hY|o0iQOK7FBWnmA+K^un$RWyYh^U)rWw ztMY+XbU@WfBe6A+*rwAx?b3qlXCMiI&KH5X1hk3}#=e21<|z{UClZ?#G=T)QQUi%? zio|wCVuL4~V8wbol0+^NyBdkziNv0c#9oTT-i*XPh{QgR#J-Efer+_J=}5YmB)c&p z*hP`p%F}a?q>I=4A_+w!u``j_t?A1u@ok;BCNbIXf z?8iv#k4WtQFgD2lyru|WN+Yo~k=W))Y*!@q9VGS(B=&m{n-v_O44+LAr_}!gi9?ez zrx^o7JtOqyUOqE~BP2m=sJI-64b`9tVnfCCKy0YEC5R0bw*#@E;+`NjRNN25hKfgm z*bwo0hBy!h>e31%b|Vsd0}}fd68kX{`wtRZ*c{;*Sr8j^NDl)8gQ7VDgD{k>0}|H; zg+BuWgBgeeaS?+xhz)hAD~Jsh_X4q@nuC$pF-Ytp5F2zDECT~WH4?i8iQNTaL(N%S zkHlGn#6ARKLk&8O#J+;Weh6Yi4SI#dX0~8pV1$axAh8XQ*bX4JHUk6bQbh(Y5C?Rq z3v7u^qgV<2<10Xiki8qnhpODzUk=TNk3=E9W@RNeDAyKUi;efoy zU;tu64YfpK`-9j}%@IiKL?m_|hz-@-0AfQO-34NUmK`uKF!Wh6Fo3S>09iKE5~-+J z3{nL3*$NOFs(BNL4He%GVnf9bg4j^;V<0wE`~rv#zWj!P;VOs?wfG$p`#X#c@;|Q? zB3Q(b*z!nh9S|F8kSP+|8^nf&N(d4=7Kxn(VnZEN3}Qpgsj&hTHBinZkOb7A*+}dq zNbI#BHq@XKAU0I*I}jV{`yU`S=*}eu28KUY3=E(nOF==+ZjH$Of*>{|)9I5_>Ze`wSBMDvS+E z7Oz1Zs0Ck;*ng4O%ytY6j8F^2kl6Z2Yzri|ABYV#GaQMXfW%I-17%C7q4^*QD7zKJ zhHCCZVoyh6&jqoe>Ng^>cOkJafY?xTZX&TCA=vc{e?T0lLDKdJU%Dc(Baqm+AT~5E zOF(SUA)yQm3>Eea44}hGL1jQQNF1uB55$J1gM}bARD2DHtqux*1_p+WAP!Vw4~Pxb za1g|Xil0Yf-$i1-Mq+;hv7vf@gV<2Vi8wGYFhbczNNn$VBu)qtI}5~y23;`{y9SBf z1Y$!Cor=U>hs55F#6AmRL(RMfWrO{HAIbp*-BS=7YUocSwyYz<2c}4DJ0x}x5<44- zT?1l6L$Mje2JN>16^4!s^$fyL&LofoRM7$?_8uhmDJ1p{B=$2T_E!)aY9^l(;{Gs4 zBz7T)4YsSEfuRD#f%J?SYMdAtgrV$qkT_To1H&W`8yc_EL2Rh_A`lxYz8u7cif;n3 zq2k*?Y^a$Bkl5Ei?0RT?+y`->>=#JvcOW)YGm|p|10$5pjl@<2v7vgkkl4mZY#Y^WM$7X}7cH--bmhKdV=*igL^AU0H78N`N) z8@YhWe<;TsBmq_A1Y$$Q-9c=qco2vU6%Ploq2fs(HdH(v#Dr8JsKxV;*vpaFn?Y=--kTsc)MrmXY|s)%1_p)~t_%#qQ1)k#I8@C)5F6xs28MbD zW;dkz7{rE1FbIR#Pz~}(Y%LHQszx8ghN`gwv7zGjAU0Io4~ZR%#LfV*VdZ}=hy!(L z6B4@{iMzyoBUFuCJrc(diS3HS_CsQ)fY?w+ zNbHM9>|0PaDE%>f0CAv({zPIkc_8`=93VE-P$eX`0}?w7#D)fY zB8Uw-x0Zo{A=QI{K^V#|0Et7@RC_Sg!}D$flEe%U8yc5$L2RhzWk~E@NbJK%?3*Aq z)H9Ee*sqb;-$87!nV{Q$JsB7n!5jt#Q4kyIIvEgK98@PVFerF3FbG50+8}YL8Z!_Z z>QEaH8!GM$VuLoQFfcHy8$fKR_-+szDqep8#DPkj2C<@x0U>pVp1`i~5Fo+G+906iOEzUt=FGgaoL1G^Qv7x>{ zjl{l!#J=SXD*vH|egR29*?*DP{60wWhs0JyVrzidP@n08*iw*OW9-AgAPi;OfyAL| zd=TtdRClb{2>Y)ldRrD?tpc1hJupHX*TRfY?wUFGOOmLSk~c zoPj~r4^;j`U1SH6fU@0@*s&ls)c0vf?0h741&9qbv=zjLn$w5Go{q#`3u1%KtY=`@ z2Inv^>_=js0I{Klo&&L=hCTtYp}zTp#1`>KG-MQz*g8mT10=Quh#dem$OgoLvYnCG z?nrEZBz7ukk~Vj*b9)@OCW4e zsm8#t2EqZy^#&yN4kY#-B=!*`_6a2R1tj(rB=#L7_5&pL3x80l4h_sVND^O=*gufi z44}QDQ1vWGY;GhrKN4FUi7k!9R)(=b{#S=_7#JAzk=VvaY-=R8Jrdg;iS3QV4n|^! zBe7$U*a-okQXT4>3?zvhBz6fBy8?;bfW&S=V)r1iCm^w>Be7>A*m(?#5gdl)NbL1U z?9E8*T}bSGNbF-s>{CeWOGxZ%+b71PeYWEic+J2N!oa{#FkMj4Uw(SPED@IJ8)m1e zFs4kuIy=puN#)ISwK-{ij4P&>&Pns<40y}H02=Bon9iu%AV2-hoHPy2n70fJppA0{ z(;MGJ%TNEX*Oz6w!`w8L=?Ya5EYmaQrulGQdCR~6+6!ASy>PaO{B(y>FP7;K=BBAI z8N8p)HZRSO(PDb&yflBtnCVOBrTKHpd}LtQ0&&z<8Tsil^V2jKFHCoxpXSf_Vfs`M z6*K+m{51b*H4!Y+Ef%Eta0+~3U;rI|Q!stuHW~TpYZjzwFix3%bwQdx01}2`7;JgXI-4;&sZ}(ba9$Llfs|r%ND2kF}h6u3KG3C z-E~QtKcmm|sUWIi`cn{fVY=y3P_VE}Z(Ew?$M|FVRS;K)W4hY1G(RR8&go^#()<|L zOh39T&7ZMly6EyWf5sKlQ$f_3>03e6o9V18()<}OOb-Q7In$S}NPEw?XZqBYY1)kU zrXO6Hrp#I)$;cov{pHFuWk#jxysOgGS=W|;HYFMwsS8h^&=w)UIAMA$NZ7xHfnf*a z+T}T`(gYYEOkWEUW^ZL+SOF1!&=$cm{lls>9>z1%|AOS!w=ys^Pha?qUwFFB>NEky zHPd}pr>V0VO#_)!xjIdm@zwOXAQ9D*@Y|U0tWFbPjXlZ0umECcN28Yj4{5}WLU0(_T3tO6IJGQxy!)tfSrM%5VU4%`o(Ab z(o8B(r{7zXrU|>@c01qNw5uA7ho(Qdnx++Tk_~hTEcoV}fTx2Ii8`=Z0x&>qd4 zzCD^bV+te8e$f5C;@f#yGeo=?w{2JQ&k)|gXt~|&f5vl8M$75-Gjr6Y7x;;>PruL{ z&f6ZrnYlfJGb>*OuKS#BmK3Aq^uT{9>Wpi)3+iR1%h#KRFff3wRb^mcVSEfaFFW0g zfgwtV0kn)8T)cw_CKh&2a|Q+`CiY%w&_%kenRz7)EM8`?3wxOu*+56nvUGxOJOy9a z%f!f$%>&ZG`oNrlfrW#cfq_X3bl@3_G3X`=Nn_BBueMqYkqk^ypvw}OI9R`eHt=z< zd+ISTFtMtVZ|~SkORfgp$LqxSpOJxqKSc_B!!MYKAb6Ud8z`)%+T`(|9hOv0MUSO7f{S8qD26pNF%nS@-EA$x{ zYB&@MSQ!|&r|U2PG{W10+b_Dk?(A{n>Aa)FQ zp9up4hbxGkzzw=mhr=DjPT{VYzBVXJT+#(}rK&H;I|baJ?Nl88Aa)7&z3F#@vZPe? z`572EB|yoUfm_s^fq_#JlpvY7Z3P$@IHf@1EZnZsWrDK~GS*MO7n~)=D+jv$NACq_ z3mA9ubjFY@an)0xYm*FhK^I4GbAYZIG6Jy$xYr7SZtVf39}(`P>9!$R;z9f67#O(B zKq*g-fsG}f4U`>I*ccdCyg@hon1ckkc(`nI*clkOL5E>+L9WW;4p3)c;DTJ0#l00| zojvG;8V&}QqUp;*vgGSu>oPEKTd{%+W)xbh$-uyE%?eV%BowR4z`$+83UURDki01a z1Gg=h!y%Nc!oa|72j=iF@M{S$FmT(mnzMs)73emCE|6g&pffiacnu9W7#KtsfQlZ` zB+xnn(YNBD^b1NF%%V$->p=-vSDt}^RWw4Jfq_jFbQTu7Xc;2|1Bd8p0|o|8(HPM6 zP@>O4=~;9$=q3hHc4h_!UePz&3=Djt4?$76jhL6U=R{5Wd@Cq z%5pI60=t%uUHx32{UXU~O!Z;Wh1ZFcZFgP%<%mkgp-vkn7IVixu zz}uPwx;d~Mbov`e83W6e=^sP0q(oO}Ffi~=@?d6Q5M<-kXF3SF0M~lDLRglRco^tz zCL<=$4pS*MUQ;H}CAiXz%F_eGvc&6`gPdW(be4mGL6Do*nkg7`b?p;w1_oXmCXlTR zLi0d(4cLM?j6!Ol8!ha>93~+ake&8S7ND!Jg_deDFz`BnWmtqXco-OX9lH|5ql^oeoS# zK}W}4GG<`lUChJ?x?WI_n}LB7On~Yb1~wLu3k5lN&oF`SRTb(MV_@Jt3pRy8XbBes z1MfL7hY=D{=OGcrz;6snNf($vSLyOk1DVgo3`#)!X2J{%yxh#7xD}M(6=%N4&AdW^2`jNdW3-=bY?ZLB6AKm1A`zBuL`p?56nhYWE<6>HiAvk z0Gq@CF-a3_5?4I~e>&*OE^X$!AfuRh&6p$LMwvs6+APVyz-s~aDx**@D8X2PIZO=v z+d-PGnbmo~?yzHC1lMd2)eQEz1JoV!^+A~iteFEG>h-)%U>+v}|0z%gab`~8VPKGw z;B{sG!o$D-I+KKf*9~lxv;im$xq|~&dI~6$dVswxT?ER#o?v%NJAo|l0y~3&e>W&O zcr&j9osjw*=u9?+$f;=BwDoFIaMO_>E`4F_mXGAAhd82CYZoOp#qQ2eX1PJ#(<1?!RJ{RYbBdaMUQ zmR_5#7@Z{|xENG8Sg<~VDP@@c@rAwc^vLKe?s|7{eZa2+${ryQ_C1gn@*wO&kS*n4 zwjdX86>Bvg1B1{$&>bYzte}#FL8t>{Ukxh{9|HrM&>2v^s%2H-V_;wx`VY#?b*vJ6 z3=AAXhd|{(Ju9eC<7D6$0~In2tOk7b3=D#tyv?jf;pVm=o7;+PZX2?>?GSSr_$PwO zj}F#$J_ZKC2;Oei0DhPYd!QzP%er1xP+7+&v`LwPfwzwpR1R2HvTx z7eQ|E;+?_T3wO&*WVg&hxTT(fcQ(W^4E#4i;WdXfhM$2!Fo1VH>vg#91<1M=B6KtG zE`n$l5(X7~iyyt}|m zK?Z&+P-U^3RbGIBLC}kLA1mkpZHP_#k==g)+5PngAs%4hPXYP<5NiZTw>R%G*2^Gk z!71%HvhEYex=%thLtJ+X>^d*Vo$kD+S*L!(4@zV=!9guO6;y%W0*9jXTTlwS4GtLT1)y|$rylH2X|RLtf?dkM z&jZqNkCh*EK70|#)W@tV1)-ULFX*aO(4EqpAQl4~3&^efQ$TgZGuHE<>tLUNRDjBI zPEbh#CK&jYK}FO%)(;>BTtW;CoL~hE%nZ|G;7*-8Ks@2ejBgQG$1@AE@S3oJw!I5I00pcm zST}=^DySYX19KRK)Iplf*+AtBlh70kP~`#UFf;IHf{H&&ww0iZab~ohY`8Afv>2W7vE|7#M^zi?SJbW5G%o zgkFQvK^zlt{QI=+Z7Q81_pjTpH9gsb{kjh33g{ zQ3eK1aJB*GDiD`}jRj<>paE|yTdycM3>kRaAVCNT&vr0JKsY5Mo1vb!1I$xk;I{&K zxQi`Tlz~CYfVYQj7s%<~Kxw-dY>-T95d&`@STzHGC#Y-F&o&cumc2Kq1v!Q766j9( zM<54*axEu_#lXe_GDT2qgV4CIS#pnSN3?S&`< zgDj+1xsC0d7z2ao1km;dQSi|zqD3;GZsl=9(69*TST`2YZhla&(hk&9X5a_i6UDn9 zoWA+D$}=$Vo&>W6xp=R#8HzJ72!losd9Q(U1A{PV^st`yI+({Kv;~xeZ-6;0LRO%_ zxC!R434!}=x7cohLWY4KbaOTDZMJ8ibKw_)?vH!G<|)p=z>zEtD_cRX2Dk1YB`^!< zJVrhTP^7SUgKh)!05Q3^_*zbhGcYr7Kbih8B}-iL3h0Kf9*`6hw=n2Fre07f#KK)R zT`)CELg6{+F0u)gpwR^nzG-a|3=G^MpzF4#gH$namrVCe&9bfs-NM2*7bK*_?G5TV z&jXc;Dmxg29`<_1_r(pvY_FyWgt_}e*&pul7y)Ou|UZMbW!eU(2Y^oKnhs6KtXd? zPLhFv19Vmc#6*xo8CaY^_ryH`S;n$Nj)8&il?zCfzoa!ZG8kAu8+Z9WMuCJuhc!Sn zgNDQyShjL9F!22ZJ0~4v&c6nbs;Sc-q-BZJvw$uPV`l`}%D<9}fq_qe5o9*MAm~~x zNk)*Bf;xN(j6qTi3__q=iTD)3Yz86FnT>o(j1iy#NTF>YFDo;~Nr76z{-8_QR2V@+ zlRQG_KsSu3GG;4=ktn1p_Tt`{={bC`v!%o!N?%)uNMp|79|{4Bs6 zRtElJkdzhU0#N9PNJHa{6BM=l4E+B=7m%%BR*+_3;IN1R+yXaZ;>hUhNPj$KiG&~Uvd zp9!ce1Kk|OBKk-iRF;X$gGR{mbr~4gMJqw0oeV7Q3JeSa{-31l85p3(1s8&hQwB9* zL}!6cL=gP~8qya%CI~VPbS4;!sHZSw#2D1FiE@x(U|`V)-6S*zG(yHzAuz8&mVtp= zhKGScU_Ph>VBoe9V_* zY%cB>nhXpAYd~ynZcx1;unxrL;Z6XVvjG&xeB5g|85rsXHiDvAfV&%{VH0Q=RD|0| zpMgPOGl;Fg4LampU<-(?!#x4ygKb~f7#J+Lnavp(1h#|N5ezKv85kG@F1LfOsW%aL zb_5g(pmA4$=O9ZNcnXSh83bN{EM?+8qQSr*@Djvk;YlpWtY;8-KLwOl8Ccpurhn*` zWnhq3QwQCbC-4I_o5Bq?=_lAEZc|wX27zCoh-cyE1C2ob0V(0&?pI-85cmsX^Kd7E zT>o#YBB&6M1O*iXBgi@tA$Mg41_4GeM@(p&3Wvu~1e6&;sqc$IH)u##1#Dan zqXMrQ1A~Ann3u<>uoI+E4eam&Mum2eoI2PQg^UXPpkUJg^NJW1BBjz87zA{|N{bm4 zwhA*a2pE7ROBfa0L1AkGHnfaU;hHo9gMb;BSHZ}@#&TYkfkClZiGjg~Q6Q2L6c0k+ zD2xJYXAr6ZU7Qom2+D3OLffWm=4L4nRf2sKme^Py*%@3yFauxD;e*Jwu6*ju``k zKpA)@szT@{CL7<56k(0vI827v}fP~Peg`UoD={!kQ7{7;-450x!l(cmI~3@0WCRZ$GAihR zN`@XrP`^PO8Uejvr4oz^qM)K>GT3}6Mukud1_pttU^y8^h4$&^^0K7sL2WUC8DK#r zMg`E-eFF0tLC2}6Fe-owTu_O{$iUzMip_2rGN^LHDC^#kRB+i*MidrhtOO$1_pukU=F9yRZyDR2sW8V z;T|X}Zeq+;VPN>ctZ)YuX`2~qRq8=kRxA7jCHAdgPZtO(JOr7z4a_SMREP#8iydG$ zRR}6bfl}~JumzQZ3g;2zCUI5V(%{1m^HD@NWUd>SxBSpj&1 zN);}l<7NyDf=yt1d4$3h7#IYb!CLu*K=;%OwtzYO4E#Y_3=D#;jIOGnECi|+!Lxbb zS^^YEj12tWl^GZWCBb9*{7fJRc`~c2F)&D4Ffv#$SgOHVl%U=@1DB3aMv)o=1GhJ5 zR4@}{9s~DWEd~amERZ}4_hNO>aA(o<{l!^gE}$D*!C@@Nz>>IKDv825R01_q%% z1JGUB+~ztA3_|^qstgQr+($uPm;kDt<++!G2976!sv!k#(24`0$&5~n3=9t3LBiD6Osj$hc)&qq%fO-m^1y;#(3%EL(A4Y_2GFFvfCd8tC+OxCFu}kAIzB>Z znKVdB8zcp4j6J9E`pnzQk3JC`8LQs*n8k9pBxohh685o4tfH>^jpFvJp z3-U5AwD0Vqg&31PUM- z1~!(j>Y$VbawSW;9s`5WW{|76IE1!?4*TJ@6lY)%+5s||f%}t)D+7bjP7sHQ`v(gH zgU~Jzn}vHmD7JQk*lY|e?<5!)g!Y0m1Iv1lnlqq)WmyC2gj@zQ6Q}2wWl7d2Ycenh z9RfuID5LyjNJ{({UCj%P`C;<31K?*n-RW(6# zC_>zfn?dG*+ATsn;QYoQ^bq7MUNDCdJQ6R&2QCPhgpPAEOlL385~?o+UAxBva)db8 zbfr6tLUN4y+6)Xrzd%ta4;Ez*0`*yhR2V_A%_3wAO1kP`Rd<9QgQ7%((Nvp(;epUj zSq26nO>hDJL_tBGfk8-z5tLO~7!{a6({#GvW(WtP0_gHjAw9-=P$uDFRQLo+*7}Ur z+MxEXLNh3<8G&sUVN`Ge%?%kd{?q{7i>+V+a+)c)RVu-#zyV5eW{murpnI_uxIh+K zGJ+0x(qL4m10@`5u1{Mz~1_oi>4A5BTCeSurm@)?jWfw+azvVg%4BYb5A68_EOM>S7 zg#$rJk%jv@=#=&#P-0=@?w&4KnI)d-s>8q_90ro+U{vX2V_*;t2XVL6fs(EoqY7x%i*PiEqt2)TN^Qcipe(4tsB#9h4kHdE zqsgeEFnwZWmZYsJzyvOA*cn(r$5{zif(EjbD;R}abU@d-R_ZY@ z2)BZm4BUr7XSTE%fmV}op9O_q2PlaOaOZ0=FbH>nGQS8nmjDBUa5qTYgj>vvfkC(z zByPc-A;`cW+y@em;BIDMU=XgK0FsE|R#IVL5S|E?{77O{0ZnKM?*mQT6fvrR<~@b? zgXV0D8C5z#K0E-5UeImYY%GZ!plgWq7#N&D?KDt2Wny4s0j-*0kp+!%A3mYOz`(^L ze5C{w87iy{48m7I8JvL|H2o%g6BMT`3@rOVw%-cYV_@Ja5x#Q-r1lm&1B38gh+43| zdmuIocReU9AMfOHW?1B*OJ)ysNNRM$&0FbIDHr6gq$ ze&Npx4Hy`>O^q2Cguj?h_pHg1wFA}D!hb-?T#b9L5(9(qUl3b^n;Vn_|AE+A-2I@e z@E^q15!wxkK}dgGPw3!}x(7G(@P81GKV< z5#)&yAy9=aECy~bRS1D;@E-yhZoqg8bPwkT zkYgMfpJ)g&FbFybFJ^QERZwoAWV!_Ge+D6KP?RhMb6A8LrU%t!8P^*LF)#?P11lC3 zItt>f2XoXREs#J^I~`=3C5Ib z1B37}Fein9UsjocLHIahY^))u4J~|t!5K400s3K zFozvHHz#}+tc*iwrX&M{@I|nVd_snxGVBtV!!I;p`h)r`$$HS7n($pl&_t}b(0Wi1 z-2;c61OtCG9|ME%14d0F1_u6FAg!;#T9qsqg+DUxF=1d3TF=eEAp8l;W)K2hTqFFM z@sJ5=`px(mbZxd!v{`BZ^+`8wgiQ@B6#)KbRj)Z>7@qd%n({JU9mAs zEz=xiuohTso-pXvY+*C7_W9s-Aj0NMph9#3c)5tM1rw+cT_|)AWR4|R&mtjCP%^Lr za~2CFfC9%J?93%XfuQh!tn*tY^ke#l#w^KtK2XTJgH^8-nghzRUQD2K>sASauFw|t zWdfy#H3}}E9O1_VYOU%pD)53bWf<65CX5O?pooVo?K1^6J3x7bjpZuy)Z%tK?Pbi*g=j$pFo@(utiQn zM?py@mr0t5fx%g5&h*BnEJgn(CJYSxo^lKf!jQ#vf=0qKn2v!AeFLifW`fxaLf=3+ zZ59(~YEDiFbTy&yY;c%p2>k>F_gpYXOX%G6k4;$$^&X}S3b#zPd!TT@Ge52t|Xc;uT=GgGPO9LH8GL1LdBT zOpi=qbC1HSnF7oh7(|^x2Z4$9fsS|;4QG@FO+Ic@1&y$Gg02G+%@hC)*r)4*7td@5 zwVRHB4OUW75&q0HA9R3Ka#}ir@E0Z<(AsXHc2E`l6D$#?kPd2${9-Da{=7L$sa^q; zR{t?2aD(pLR`>`?AOD%wTQV?suqf1mS_v%7TP;C%ZY!98$~ji%qn4mMw-wAm^%Wbq z1N?_YVHv0#V+Zs8vM2gG#wD4h7IM2w^d>WE_VAXz7EnIM~nx4uuL(s*qp?4FM!^D1efounbsb5r;xM zNKO{aE8$SM4B{y>gKC5d4%NhhOa@_n<}NV?h8}T+4p6mi#0)xiYmKE#1$?mFfa&P zf*txqT)}yIRBM)W{ZvpjV8aY*Iy@Iw&;l843+BBLSFi`wxOQOPOL2uzkkO7{?XScY zz-inS%zG`a08Zp?%%DX6MqFVzsH%5o1|^X{;tFh_DDVKQ{41`&2FmoF%%JwpKXHZC zGN4r91@;Szgu*|N3%$Vsq#~hUHeH}COQimzCFquIh0UN`?#Ik%#lWB;rN9KLiv5{E zh3pGug&I&^4qz6vVqkcqtdOF~z#tq1w&H`bLJufI1T%w5#&60B7x@_&ghRoO`Khe% z6jY3afqB1_6+jCsg~P$T-^vOnLD3VzY*Ek1!0<;|VJfI7i3EqmUu6Y5P(F%c22B7k zs3^36%C2az9FK|uBdDH^0rPlO6bwO85DQi*prY^^l*kg8#jU`XZ1aMe?w~{rZn%RQ zj0~XV1E35GO1==$dInw|Gsp>S5CI0>r8r30WMix*Ukfx-wZ$IieD z5(I?{l+VU;Sdf8%7t~c!w}SQ?SQz-lK<&;X<`^>u2DMYX3=E8`SU@QPw6CRJm5G6Y zan4a|1_pJ|Yz*TnmR=Q*1OtP5E$AwrRV<)^anMbN8Z$u$1+HNMH4md17#K8EKnKOI z1@l3>W;EPDM~FiB7eMmQLAM;OV*#1{j)8$e6LjRAL=Xdm))WQ?2IU|IhKp7V(-k_h zM65xaH&zS`+Kf?5#SGev(ac;7iVRwfj1YC8Q`wND7!?_`CP1Z>rssELiSg@!jJ?Ci zz+f4~z))&Ez0g5WbozuBVZ76&=Vb{_Ki-ig$PH4XqsRnOgDx-DnZ;j!+M0nu;yp71 zgYGrZLAw^PAaVm={I}hffk6*cDKlDt#>+q%QXd>(R-o{zVq{>@2L&6WHHf>8k%7UW zqJn|Z2DA$aRIccUgHF%11)2Gkk%0lUp@6|9h=IY!2IA`?hCpq`XhuT@Ezl10fFK5j zEVv9v!a$ob1|)09z`zg_#K6#uB5TW_3A)!929OUK7t{?^mQQPV9 zU0ISTAagWrAr1$b1BzXcIkr%-Vg?4SKTvZ5p<*C)f{YNyXTillUbAP=1P!Z!9d8DW z!iBaF$A9d~60QgN7v#JWP|9GmW?(Q}13GaSWEum*eenHxp!2)bL93q`1;IlU@=Od2 zMxbstqab)9hA~(j)FfjRWCRU_MKUoksDoB^G75rQPV<-;7>tuM85o7ZL&r=L12n)< zD*_sVXOP{)#K52-3f|cP9`*kX;)A9%8O0bsPG8WSB?C!+pbMQr>2Izb#PJWhvlQH? z1~D+~v4e!w!~ku^Xr>|tP+XcZXn`)G1f_wiP-&0^C<$n$FfcHHg9CJJAIL-=dx(kr zufq65G(ojJSb76As-2XGoQI&1l{kHMPnKl;yda3(Aj4yrCI&DtnCu57??7<( z1(alGfYbLhM+OFU(9(6rKyV8*l$n7+9klF_5i+OK&&(%nI@t7)!v0 zU14Eh(8*$8V1T$jn$cLB5#o4LQ2GR22rAr%!2jEfmT zS@#zU1A_%!*S973o!s%?m3=HvL#n5t(36uqkK$j^8GcXjxWf-)27#SGkf*Bav zAYzP$3_8;o85lqYfbx(b1B32qP(y7hsDuG|=%X37jPu4H+~+S9O8|3KWQ-G=J0y5>TQOvV387#OrbSL~VvGcXu{#iE!>!G(qqgVt6C1_q~K1_l?X1gJnd3p%wnn1LaA z`kDz@QmlT#3=BQfPfy5FsgDX~U|0ZEIWd4i3v?-KS}+3x=yWnrSp+KLgcunZih>y! zjziQj8ZcrXaJk9q3d{A7**_*WST4T~&gC{BJ~&0(0B6i7HU4Vg8!}c10bCUk|$FWGYyGIf%a$!9NA! z{{ZQq2A1dNU|`S)o8C4#%a{+GT0!@vgVN-R>57UDV$<(V&eDTOBtmPlHxLQ^DOn1T zRNM!Z&~k^Q;^HY;QuUw$NM{Q)szLEs%mK>QMxdI)h=IZIKPYcQu7C{$H`qY88bbn* zof#B>k(>++W}tG51Kh$b=VV~8Sq!>Hgo`t{Xo3#u1A7V-^dL{Ybf3Nvl)V8{zv`31T<8npir)QHvhWMD7?&ABt?fIAtCK@282ptJbvz+nPP^`K*080VCF zGBBuvZ_TS?{;tZvz{$nHVB`#{73-M4Pd_j%OTKzrL5A$-OVNNqWVxp%t4^ejnZP^tIc6XJeQWelq6 zL6>AO>}fG$dm{=Iekq^?@=GEHN>0R4_1@OaNuhbKpJ0*wPH>?YA4s7r$E(Qjh zC)^Ao42&0;LCb$Z%_4A7aFO}rbeS1hGA^K0s|B*+LNMfXD{aOo=HeTS3|fv13=Fq} z85lsvS%CzLZh(qmPatm~f#GcfG-28ClZ6R2X@q-n}-@!#aBeX#N2`=abco`Tptfptr%2KP3_JuaixWHxgZe9ik9Z(Y$QVv5J zXN(3645pxKzg-y^7~cCbFlbb=GB7a8F@e^6o#SO-Fa@1@06H3WCCoG}uxSrLrrkhm z>VZtNTf)G=z*NkzThbToGe#o@&CRg1a}<$wrrXWV5`mN>pw1Df+|r$%Fgwej{vW7< z>;mlw4Q62Q@&lU!F1kP|gDZrA0dzVPC}%h`XmKzyFo=aPFccyw(_my^PzqsSXaS2w zGdeS989|lJ01JU4he0a|T5NBGi9w2PhUxrsvRE}i*$SS9V6{4fp^X6p1EUsbaX*72 zIDuc8ZaXI{&>UPt>a&7!_GLZ>1})IY8K|iVI%1%@h%eWJeHqQq0BInCd}$L1b~`AmX@VLkU|)ic)B(AmG7w_&;dxn-^`KUKFI06A z1A|r)0|SF@2m`}Huo$GZ52__Ve%cQfi(-QGA3+T-Mgs<&ItB&?kSU;0Edp(hueM-d zU^&6`IFJE$`MJba(CQH@(5W6LnSO)BLD`3aL1HUt*vPS4mw`cmj|p`6gCnS_5YAx+ zjk-9=OEWNlFh{V{2W|!i5EhYgn#Rq*0K%+3P7&%13?R&!;QUU7fdPaC)R>%K3NkQ& zuz)g?(=%fR1`rmhaL$!tU;trZHWp{l;t>#b6wqRFQe|df0AZ1Qr$_+?1`rl~;j)68 zfdPb_Eu(mC5<55Ca1U3p6u1ducK-fUxjPW@l#^1_lroaAk5%;$>g}Vc|c_&iRTA z3?M8#mDyQYgn5ccZq*?PybK{ezGkS%KZvS^JOPCq+7WM6_ zx3Xf;E>Pco{eITM7Dnyqx%Z>R8N;SeOv$!ZozKOS542> z=S@Ts%A3ynSzdg4MS8Xb=@b%G9b`p{r z@a@r1aq#WYP<9tY&2;X}Y}xvq5Dqvvjv=u@i-=&3c!?zb4T%lfGXzs33Az#*YJn;e z+YpIui^K+BH?6<`I{J=*0W=i>Gbj;BQ7#g@5{cc4#GZu2o`=Lfg2aA`#O4NF9u0M< zk`Snu1?A`=Nmxy{&C0fBY@YtHE?9heN1_PN^f_7C5|U?;)Z9X1znFeDD_c2N1$3)3 z)Hp*VwmlL%1c{x9#Lh!v*C4T1Be8cNv5!p;%+40C|B58U1iIWAYP|pw+X#tmkHq#x zVkaT7^N`q8NbEKw_9O@!5`Xg{9B?Aqg2Xn`nDcX(1K0bYFPIhp;1L#U>s8U}fHn;}|6<>lRz6y!G0g1g0iMo?X%?i3z8mfjHi7kl47Dr;sLfDWPQHF59F`|jY)<-VJ3hg6N%|T#_9*eT7Xh52M8N zlO@^L4f#Mru~0?QNNi0cwmA~pb^2NzRq^^nBq2~&1QtNGNaEc{?3qaHY`K%MPx8f+X}2iTxjm4cdkS zvr`(WqSHiTn_jAXK7fQVuLpB!_@mB ziG!A)!o<^%#G8@W(;#d}oGpTIz;U(?iMwmmHIxm$;u^|c1v3Za zf6&S`n2SKmZDH(lFh!t4_>tJ(kl2EtORS-WnjoB%x(U>@7&_1JgZgvaRd6Kvz^lEfPm!t0J*MXYRs+-w{dNABi1{#Lh-y zS0b_7k=URUq!?kH!o^4u;QO|r4%&|-ein&+8;SiAiTxdk%?g_Gftn+X#8yON2WbZ* zN~bs^i6$g=9};^O5_=gEdlM3S-}I}s+578zL9-lC`)47sLHh(?feF4`8>;3WlA2dY z>~BbHCeTgVQ1yIBY$+tR8iWnXLJSN>5DvHqu|r~eA+f`d*hxt2JS27%61xqFJqd{o zI`nC?py>dp z8KOvRWhAyC65Ae$?Tf^YMq+0ou|X^EVS(9-Bt99!2F?63FzkSEz=3dNx?xkcIODVF zwoTdM(-WGqB_!2BQ>jolnjo=*rcZ3jwq{&0{UAu`lcsC~NoLSWK&VmyB(~gi-RA6U z)!9fwE0EaRkl2T&?`_Wh&3I?}+Lmnb=@(kE6Ku0VH(x_dtw3T=LSipKVy{DD-<+P? znr*GB1X_g$H9{YWZHvVAoPM@7JGg!glF&{h_H`uo8zlBmBsQ-ZqRdc3VuMa3fJK85 zlDGvD8+;2ktkiQsk^mis4$~ZnBwm8V2H$)Q^ zV%p-_vZk=U9@Y;zO(N-8R);y#6AR(0wHKTO{^xBsM2#K_ApsaU`}X65AMw?TEzoM`Fi9*pPB08^Qr+ zp-Ln+=tOg{w-^{0z;{_gEnbYIW+M`NKN9;a68kn1`y~?ly9H8wv4XB`hFTzu#8yON z>m#vkk=Wiy>_{YbIug4SiQNoigZw`c#sRJV1>LX=b%Y5L+aAP*41X~=gKl1ivi(5f zQ1y`@HuPSjI1n2uo(W<@#q&UHsCXs#ifE`r9g;*Rhz%9*1F@kRW`fvI@p&LNRD30f z4HaJpVnZFb9f^GjiTxJAHe%qgW?*21YEVXE>mae6Ky2`QChn%4EI5IG(*|1K;lp}UqEcA|9*nluyTeObjLAN zf&;{cY7hdkq2dZiY*i2&szx8ghN>|Ev7r|GBC)fP*eyuxUK>!lg=$y~l7RYn4HA1R z5_>m@4OM?0iTxOf{T+!d2D%0rs$L6;Z3kn6)+PqQI1CI7*+}dXFnjvES{=FiIUqLF zaf?7~sG&PRY-mXA2eCn`+!+`c4%;#?2t(QDK;lp}H$iM@Xx#&`q2h0l*xx~HsG2_@ zHY}Rh?HCvsp%PLcHdM1Jhz%9j0|F)%QgBC+j|*e)P8RBsXzyAs5P`o0Ck2JQD}U|{F~T?h?jPqs(u?#%-! zf(FrI5F4s_9f%DT-wa|y#rJ{OQ1QbcHdOo^hz%9L3}QpY?}6A*@y8%GM7*Bi9f$*! z_zYr0BpCjI*idn1(4EUrSF<}XFbH!oFo2d=OM%3pYUDv|s2Wowwk1?OXo0m8NE~Xu zFNh5qp9K{yK_CuPb2<{c0Eyj##GZk~UIb!8W?dP!g4j?8?EL9AV!MIZP`wFA>=Gn)I}&?3h^+v<>TV&313F@!fq`ME zBk1H3P?#_;xCZc;M=F6;{QS7Q1vWMpsVhn z65wm8p%TJQ3=E({_d(7O2i-o+&A=Q`rJ4o!`NNh>aHONr&!FM`C+4W&a67fjvVkCAahz*UVDIhlJ zhA;*Oh8Zpl48l8_yiAIfP*l2{C4Lk(I5 zV)KELA_K!ZkY!NzVURe~&`U_{>mW8%?;{W!s^&R}4Hf?cVuQp%<^OjO2P(k?x)T{B z0lKaU#Da%2eF~P zOh96nf!NU0UXR4?Kw_^1v7vf5A+b+@*igL}5$t+~TL=!rTM!$n`5O|O2Xy~3RI?}& zTMmh>4Pry}njo?LL2Rh+!$54%E*Ay{hA4N?`3<1(2VKStl7K2I0I{J#1ipzH%5DLP zL)A<{VlP2rZw9fU7VJS{UjnhA9=MIfegd`tD)9;=0oD8ui7n*8z`zI(qbW1EqJ(TSQ5{DWZ z3SvW}EDFSiif16P%i!#K28LP?2QpH`&R9z#C8U;p%#0A z*wDM#{k%cvu7Hhahy;m4)uecX%73WqGLa-oKy0XZC5R2x&;nvZ#U~@NXMosHHQ?K) zp=wru#G#JZgT%f7V}la>O&EuPf#K2gi!-yu>jgm9Dns?DAh9iw*x(DJp=v^r#N&|I zMM&%(B=!O%_7)`eUI-f!D>pzKsHg6O*wFjnANwF~u73v-hpPF5#AXNGfD8=;9uOO< zMjXV3imM^9wLxsC`TD-~5DP$CDx5$PPz~-NHdIjz5*u_cw6GWh!wd!nhD?w+)Upx~ z8>+Vw#D?mv1>N~9#=rntx<3IV4plQ1#0IGW`F|CR!@$6>2Z?<=I|$WR6bhM!1mem@2VMyOs1B(|a-s8)tb=z%1ln$3~e-bm~?Bz6%JyA_E&6N$YE ziG3EthKAM^5L+CaN$MGH_%Semwn&1wZ$J{zAo>VmLpA&Xv7zGJpqqoCYyl7(szw^b zhKhsle};-{BZ-6We};-%gT+DN4_dko;y_%)5Q4;xMPe6&*wE0bL1MQevAaQRs5x_x z*t?L}*OAy?>XA5qk=VkZ3wEKF$sn;+k=PC(Hq1p3Q)8!0a3(b_o)@V!GjiZ1MUQB%y93c0Uq(8WMXJ5_>)pdodDwH4=M0 z5_>xmdpCqV{rG}x!TMtm4%oeCk=PfJ*f)^acaYeRk=W0X*zb|ppOM(Vk=XwsY)Hmu zN1B@EMq&#ivBiVx|?UZ zBagZ8^bH@g4LA+{GcbTgBIBns@)pQX=lGPZ!FXf3;iqhW#y!&;LDY%q7eUmI>58AT z{dol#85uy^;Xvj{PInB^lAb=}bG8O!!SsWlv;7$prVD<__GfgNp7g&yUxIjZrd$5Z_Gf%Dy%R+Jn0^yPHB8t1 zmF>^CWO^ltS}^@2h?+26@^`j2uO;Z<15oIKHp)#8$G+Th7FLL$_qfk z6Q(zUgxxwA7(%B%^r#h{egGs~F#RG(c=lWdhF#PD{>fHm44tm{H(Q-`!ZrBK=Lvta z1sG3EFZ`RW&NyfKOb`_?{ovnhb+(L+j0`RU)9qFmDltx(F8D87owMOB149El14F`e z$6Q%?R)(((3`Nr)u1OQ0Uh^-TAAVW5-yvo3?JNIfzffY_wtbRf&Zo^5 zUMS4io--v!kd?{MczgZK9F5s9UE9~0M%)rFKzDpK#5jZ<&^(8Y4_{MQ2CibHO z3=Axbl|UDd`+#psTgjHi1NvKsS$T zfbNZF@t^*!IoD9~BIvlb6DL5D>@z@@k)H&y+1Tx;JGA6V^E!d9@;(jP*~)!IetN?l zC&}r&UEJ)99n(8oa-}uzfo|}&VZ6=Az`*$uw4e@jl{4rF8h!@uNs>F!KKZ?W4?P{10*m|0Zb$&}HHv4hR3Y>1wUH>Wn?p z{aSOy8ShO`Yt7Y*5&|8BB>Wt-L|OQ}G6MsX@LEm=24>+NkZ**y3oJ>C@k}=8D(v6k%Xs zGZY2+hFw~Sfq~5k#1>%B<7QxBGX^5*!2tNbeqa!Q;y5&^(B51Hx_z`G% zys(x$0|Te>Lob7c8l zIT;u@(!d-!{v;j-299(vN1lNb6zrEkcgBNU&B(xA!OpTR{$uTf+dVrX0T%0Zcrss6#%1Anbu664H2{N&}Nii^R z_JV9;VLv~8VP~#{!b~v+2F?j@Z5u`dI$=YfJzRk|Uz##B- z`t+_``FaM>eJ%o^tI0ts1VID?ONAl>1Lp}RHUsu{FCL~t$W1O^s; zP`G~V0}0QAYkm(pxrW7)je&vlC)hcl!(lo9Z2_q|IlZ7eSEPOm7Xt$)J0r+e?kOOJ z0*oNDxwRx27&s*vL00nVa4ImiaWXLQr?P^sX9Tku_*a8eD>3$PGBB|4_kz5v%s2^@ ztoeU{oT$P$gOh=QhyRc$0|Tcj<2+6V1_AyzAZ2QdOE?)AMEHx985rt0)frcDg0jq4 zkl7lH8#oylWcWQnnlu@=aWXI{@VkQ&fEME(P6h@QenU;C&0+&4-N7U%FnL*W!R%%*c@j*5ZnUZA7G-8&;M8S&3%V7Kjnjxx zhl_!MzZn!2#^73pf!~UUfq~Nm%wgoe2nrWdFo%g>4^+ySfjP|lS3xP?9L!mAYY$2k>zP4! zVhBu`Zrz(JU2g%pGEatcH}emW`(A-uu?Ng%;12@TqkEbEfof^~_n^Dd_c618?oH

=#*NZYR)N^rxwuOs<*r2kWfq~mK6LeN_Cup6K@CDEgHQ~pgc8jo@BB)N?1xgme z$$Sh9tipFeb(^pTsJ;lVVPN3)R|8!y!2)X0a0f31nFcz&gh6-)Xve0o zpd6^;xWNT7?P@wGGYKE(23OIb8#uV5N?fY>_heIT2+wK6j>Sg>zbVqoCj4q`_zuz-#q1hVHPh|R(QI{KCS{RvQBt7l+o1)2U~KMwh0SW$kUXVIg#`gjY3>N&A(`_c?O4b)hGB9xS zfs?)+KWGaVH$RwT&krhMxrM!vBbcfq`3$@hCe3Ll6Ideg+0^ zaj?t;{{NuZlw<@2g2(kSN!im=|u^g$zSt7RA6A>R%QgHnlBQd79Y0?*ti@<2}jU{psHYA z9-{>4d<$+hu)_-&CFX}g=o$qb{`s5?4BSbKpbhgT{OO=zNd{}O;J-8d z*Th`a`Yuoo$pE`Ifj^vsfq^@du~CqLA%&kC#K{7in!&%Hje&tX8|;!Sej`v|=YnN& z_}M_-$Om)s_z!}@x&X{6;MWEv*&?u>BK~cn3=G^QU`{drWkv=D?oyDY^$aEatssw; zfm`tv{BJ;kTh7=n$iPs;?*o#lWZVzBRE=L1lq?z;L3LUO|5K20jbMv<_}79`bQ8!p zhCY4+P>?q>_6jmEOyIu?N>^=+lLZ+VrbtACjBW?(5n+@N0J*Nqk#PbO1A`c xqa zdl*}o7#PH%anlP{D#0ir1S%~igUy#>l;~1sVBnq#mXl$W(3&1MIajlu31sVh#>Il5 z%Tpv~2!M(mum%rM)LsQ$f6D^O-`sCNZZ&5FMK&J?w+%RE_)miTX$xjE@XPZtFmT&} zIV_;M4P+K*gFUxBBO~YzRUU3%#!}FQ=Af&kx&6Qj>lq+s_=9;Y{9>S(4gfoVgI^ky zYXZR>P6lp6P@)fFGzXpP%K~aD@Un=3?u=%+$^ojV1sNDXo&YzQojhz14YHgFJ>2uj=pIb#RdO%;L?{L|H@=4#eEfRg)OaPn#p zlmOl6z`YNgAzB0_;y@95fbpO(1H%$Q2}yYd2JVAkx2_PB097{JN5H&Qf)aN@v3(5e z+BJd_mqEO9jK_sRSENbY2W5dvV3h`<67N6-?`5z`BT|*C{V70HQ0$ttOSM14KU9^RAMtI&EEv`oJ1v*Kw0e;*f1AS3DEIe+;z`(ngaWf+WLjb?>^bgZ>B{lAXoP7YC z_+t3Q6&M(J4}v+d{0BjtLtsuE|KI6`Gjb(Wj)KfP2KHA91Gk760|W1IMo?|R*T8#{ z(Nv6qfq(w=ycxNYrk1R>s`ifHUNDJI|o+k>rhl1A(tYAJr7sw!UCQxs90YB*UPhJbANHzwB zh5QVl3*0TidKU4o0>!5ln6sE4bU7ujJ=j@G_(2DV@j8G_TLvBx;B{mIjR-8~Zvcg{ z6G%@z!wUW(EgH3n{BP!z>5flerqX3+u7dho7h z0^M#cJPS0lDXaxLpGdfn1Jw9_#SChEuNMN1+Nd#un)1`+KzB3nvVcsK0UamDSilWx zT!4l^jlieQxl1uH$b#CEj0N1F0tO@_2db(Vi@+);GcYj7<${KWin&zs=(D96$JQx^2 z7lkQ-PmE_!1f9_g(#tA^uuuVXMjgmG%1TTO3?Q487^4^sl^CNz=S)spm&-o=$(&p{ zvFD)Uw2Wci2X#*v=LkzrmzbNY$Rr>&-Fj}Wqy#vO%s^^Dr|T+$rY!b(Ffg2$o-;RB zn)SE`1H+5yJ#%xV>o0gPFetQwj=uykK&L)G_h4X91|4Sj*#qo0(BX!f(V&A?zJSaF z1vw}*8Rs-fGcc%5;$UE4`~vE7K4fHIPy;o57{7p;J&eKXpz~e7fsUmH-Nc{)cG7o{ z5mrnL49cL6**^~ruocWDHyD%{L8ss;F~)#yQPf%uI;bffWEW_roN>;T>3;Ka1Q-#V9?n&eZst45nj+4BeH9h7(j=lADq5%UalN(gA6S3 zI5HlberH~8a6P9dSUaN;1A{>c$cy!$l9~auV2g3iW*G(sL$HnY;Ch=e$Z!Wl4X8iI z7|dYs1msH4(f$k!;KOR?td)gXF#)V)3o`?Q>?F_`IupR<(K}`a219+&;a(F!WzF<; z^K+FLmrTDnKUZH5TNVZeMNI|<29Pf$ z<)-gkkSosxvIBHfC_~%yk85+qroVZa#;3*@4?2XB!2on}E8_uh_<)A;8Ru}yGcd@4 zGur`1)#*A5bG58MLA**1{0}sRSWXZPdSKx z^@I z90i1DV?n3JL+l5g&Z)!*@p3TebS_=c02@OaxZrD6goU*(6R1cO=U`xvwE>+Pt;+-& z@eAZ&V31R1V_;y^X99I%ia`7&)3+?nRWt=f3g`e5km1G*ilqz;44_c4Q3S568#q!rgcum)z=u#n_;Z997>qnYC!aw0sqzI3jNh3+#nvv6 z(%|XqmgX8mq6u^=E66?R$`JRkF3VMf$V4$fisgAw8Lwrz!s-g13=E*j2qnfSwo)ms z|No^J6l!4M2}-XZv))2=%v_c$tPd)E`BXrGAH_V;gAG*h6*DL?#xRvIF(~9PLbFC4 zBg8V->5AXd#HN2-21~)9VJwiDoe&9)<+%#s@Sp-21GS7l(3&&IdR6(|{*PrtJwR|*m-une82262sjus^REgEA-(Fx+G^ z4RmnNEwGz}!N~}88V00Tyv2NQdhE*FU_~L2ntR|-U=wFxkh24w+x?aqGzST~z)J4_ z^ouKVg*ENfVNPda0XaP!R8c7?!(!e7npSGmA(?6`r)wIM2E(3p1$t%bLs)px*rupZr z(1b;yAPXoFm5MVk$ofqWTAiye2a2)V$o7J208kABim{*5=daF{gv6L1G-wPoAwhFz zb*?Z(22?bG9Fz-{5nhuk$!g{ay5+!dO|FzLnhQaR9aMT4JOzyqn}gj6x%~!oQ8Xl4 z&B5;cBo0gL<}A>}?l*nLnp{^#^Xd22TF7<4v+`UII^<3R~66kM%jcl+w(BX4(>7cV< zbHMz|(hLj=prQlp3{aW_Im1d9;*1CDVJQ!E%@atb94aHbAy-lo%vlR@{F>Lh|Hyf!va#DGE$)W~O?b3zZ6McddwS@f?o1A`&B zz0$@88ZBWAhIEiR!1_SfzBB0ffojG@Y@m^LkU<9Eye_2Az@Q77C16|x*61a}z#vx- zYP&9}2P@5%VPKF4wegpN3_Pqm}2Ra)MV&4a_%7-xPKC*d&Jn{u>-w}{eouGRX7(hp-GtQAT zfaQ%&c2LM@gPP>vmQp7>sHNm1%fO%r(h91EuTQVulq(I%44|SGni;lj%9X2k0;R8Y zV3R?o?=#Ms2{(Bi*yLQe$?L!-FPCLtkOTJ@Hn4+2{sf4B9n?SC$PRMwZDgDK4Zx{` zx#$e2=fYIX0csk1FeorFGBD(WV%Nq%8FV-*BY5Ao5jcdH3>g>-F^h&AHOP)!;@nv`z*U{R{@+bNoOU*oZE&B46+rV;_xZQ(&_nIa>cU28ef3b>BuuMFzE1r8r_VXps5#-Mv(Uz=a?A5 zoWjfrc8WZ#Z_mOB@_mpzr~+nSWaR_}ZUIQP98_Pifz4SCGT3bY^bcEdMcAB-85m^$ zP3PL0D=V=Yv_eM@tmZjL57;pVoCl}dZ_O3=)&L#gY{bdT#K6EbF+lDuh-(ZUQrxJ( zz@P{!V?bTb%SPbX16LKGiz^gBegzjkcF@9>%Xs?2t+^U};L00xf!t(I(Bib~TXPla zK|O2+g9uPoiU;rU2DKU(=VXFh2^vRbj0ZdK2x!fwK_RF^R}5CR3>;%!CJYR+*`P*A zF(;@2`&0oIPNm>*vQUJDQyDm%azK30yc}aWn7<7)hYHTO6`*TQ8LlWYFeqSD7ThL~ z!gJ%cTuDcemsLzqy{rg2=YGB?1A{GCBASUq5tM`turzB*pk^s-&lP5zKiy<|u973@ zeo#oiVH4O@pFplW3QF-?!0{=p#K54y$H2g_+LM7n0aUbsgBR3u1eJ?yrV!_?*`6y2 z$-X_HfCp8YV$+{)&y}k`4JsT3*+I2EC{2}sn|sz~u);wQoQ2($7#JXVND!Qb8H43y zLAMABvxCy&EF}g8xu2lspa__M5yYPd3VBg5pF^2}LGBiaF9zn@gZL_-XccD{23ee` z%)p=sy88iC)_gFXK4EjNXuaZJ1_lO@fPfh!L_v8!nz?8OBPjel7!(B<85p*EGB9XC z<-yHgQ1(>@-Ms{geo$2fY9#2ig7Vc}aB2a05;7JfVh*bT?t&A<6lDemS_-P_bfQh=2x_BIr^;P#e(#s<4QGK@oJj z2`C--K*dTxB@`nA1Gw2^02*Rti~%Q^XW%6BzzP=eF+j7~VB9)AU~jGp<5dtP zF}-(hE_*#Fc`z_&DS+~86)3mFgNp<;8wLh7a6nc;lA8v&hOGgmuyj=h22)U@5tJ*U ztr-|Jz(XwiK_e`n{cBdHHe}jBoCFHg?+gqK zK3)tA^$N_OCC6S23<{t-v2KILg8dj77{E1^PA+KBXBG#jNCbr&IQ-}Qw}q85v%od^ zYE=dXIU!JMYz_yg>^lSED}%ZUb2&h2zk&EHpq|V;uso+41A`oB`6J_ej+c@Q3=Ae9 z0nma;#swUp8a-Z(fkFTL^qBp*vI*uOa~E@fW)c{~<`bCV^rB zw4*N1i-F-M)Qg}L35q&UBS!&r+glaLhoG)GIA4H@Dp0-%u!ZD{cl&b{CEL6h7*cE@ zK?F*)p!+E&c`-1wPS-e)D+4J}K(P(dxCg2+<3O&k8z>cCfNBIKV$j`9bG;ZC9z(807E=?4$wiiiu^!vfa;9JotBLni`K)88D(Rbf0h zUGQM87VAnc28OxQ9S-KofCurxQyg2p7#MchK^$Moz@PxyX$kT(c+d~DmG==u5_H=R z$a(`%!ZBb_1g#YUIgG&`sux}kF~au zP@(`u=}oA?t%q}kHPFTz7#MUCK$%twKKBH=tebI;<@5uGbCuP>g@`Ozt_Rcy)#(Ja z9vRqR`6d=zSRI+pbtG4%9;}!dTy$U2WMEJPos0o;|7=Ha48ZOvR0NGif-0PKU~y1| z1MWeCA`289&*N`Fgk<64?Oz-y5AO*q$Ht2;MoT= z1_jXU6*&LH8U_K*ki_)oXs&QQ=xRIANiCqz1?7KGyAl+PbzoCKB{^uo7L>t3Z2?dU znE{r8&R&7qX^Kl37#PlaF)*wF%YgJSC~sk4U;wFxWjoNg0E59gQ0wwMxVsD*$zq%n zddvmp>+|4>K17#+K@L1JdlB3%F4bjVFa@3R0-6-+abaMP`vDsEzrqGu_qtk_fdN#( zL1tHA^?r~G#D71Id2G#b^u5kA8Trul9 zP`_#=I6Z*YgEG$f=?Zh?N*++u>;pM+H)s@YH4i9RY3VUA7=yC3^7K8&bJZBVrawNO ztEK{)VvTnN+s#}A8t(v&eu1L`G!zQTesf(RPIWqwDh1DrBJX@3E@Vz>8zrF{+_P|f~850=!qcvPo9JCUmmp3+TsgSe*{ zG^Gn_(SoLBYhZ$)7AE>FF!wDc#~>*N1`y_+&g4+b z4_XDnz`!Ny@SBN&0fhO*98SqGFn}%!CL_Gt;P6-AEwj#%JJ_ZI5=3c<$_)Cz1 z0fYs$nH(Q;GBAKJ_bDdFN74)oAk009$#E|S0|N+iTw{0KCC9)3!rWV#9Dm9(Fn}=c z7G_6L5e5bj=03yZ;H1pJ0Kx(<9aSV47(kd;oQ2JyM-(&yKkH1cY<-110|N;2+OatJ zC@?U9Fk7xe4GRMU2($S*Itwu{fH3!7CWrkZ3=AO5rR@-}z`y{)Tt1GVn-)QscRI5} zxe@~d2y-boh_f;+1wkiA(A9Gw%sZ3W(OH0j0fdEl*c^4)7#Kj9`wEleS5XEA5au|*K^7C^hKiniT-S<`&_xAN>c`uoGijx!b;){w4K#I0cx6E@qEx7{J^aa(* z3=9lgk=U1~e`LwGu9pE7;!tT#B(^yc+YgBiy4jc!sy+=#ya$Or1BtyDiMuviQR(4o{z*{ zg~UFE#J+~ael(qzJ-=Ks2Q=aVbxS1@`{eYw?D^KVLZH<>P-)N}IGC4pk;FZb*d<8p zsnbO{@~!LdAql-kVsnE=w4p|eBe9i`*v3d~OC+{E65ADt?Ty3^gs>rLDICH9r=?gV zb}|w>3yIx`#BN7o_ad<;Be7>9vF9VPmvMtGAb|REBa#I8?m(#c1+e(^w%zsCp!s`{ zBPBp>UZ}JR65C)puZ^d8J*e!4MMVgbbOI7P2Z>#Q#BM=iPe5YNL1M2!VsAxapMbDI zOAi?F3@ks1k zBz83tyAz2$9f`dZi4C6RgIa$ON&FgwJzbwCKa$rT)Q5p8@|ixBC;xiA6Q~af74k=7 z$0D(_k=T_;>~H+@N+blr4e8)|sxz zm#?fEjU<$T#4bZ(Z<(ISmmgd&0UF4Knxu-vHb!DQBC-9E*s)0LY$SFi61yFVJr#+) z7{Z2R*^Lkm*qi&2*x-8up^m$aB>obK{T+$T3L3_TsuxCLDh-@a=(6voB3wDUff?s{!hoK!r@Fe-y~KmTX26nt;TfH{De*Kbui{`bNQg zab7dfszInmr|DM(^MCWkfTri6LYdR=3gu@rzMgI?oG)Gv9(RMvfX01c{?G%Bn?c1R zk=R8@>z&teD%oP5@S*x+t01H&c>1_og$doM^F>Yx)K zHmLgv>MeuVQ1KfeHdGvZhaOZMe1{%X{2P)Q7D-U@fl7cc*MnLH9#Md@H9(^a;FS#w z42DQ-@I`x2aR-n%R6S@dJnVGzI3)2B5F4t#7RCmxfarm77#J89fY?xjwj!}lO%J@2 zBVPXzNr(;9X@)B0M`A02*id`4kl4mZY!46{8aSX%31qIAfgwzafk7BNZ_L1uh@>VP z#C8R3rDtGZC;)MwnyWx;XaLrO*iiAQAU0Hd7KjZMUjkx7#aDvZP|Hptv0oywKOwPy zOMzkws(}SGvJ7R5fY?wAi=pfpAaSUgrATbhxe&0-wjU%8Reu%4 zhN^!6VuMC(7#J9yNHZ`<2}3#WK@w0!zd&r)>2~7z;`QKx76t}>8N@NXQlJ@fs8UrB z8{`qt`Qb?HP!JocCI`fZswo7qp=LIM*ibbcAT}>JyE62E?1HlEr-LM*ik2d=!8aE| z#dm|mLG!Z=3=I20nxX7dAaSUgs~|Si5uod>VFC3NN&FRv4OPzsy7v#3J_R8hu=B(~ zY^Wj?B(^??4Yj})iR}bpLmiZe#LhxuH-OmC4AzOno+JxOpHPVzAPJ~J>p*O%BX)w= zp!F>b3=Df^K?lx)-N|qQBo0+`8N`M*idt%K!fTaHYiytgE`ap zZA_P|cL%Yd4hjLWp$0{R*wB+wK_l|QP<9qb9IB=i#D-c1Ix+zk1+7TplabgnKy0Wv z;FS`B(Bk4SlEfJ#_9GA*>bTcP>@P^{Um!NrP%hAbC)9C*AU0^_0Rsbrs5}FMFqEwT z5{IhMmIp-#)CUGg64oF#RNMi?hHCHzv7zDtAU0Gy8pMW*XCkrlKy0YRZAk2X7#mbv zECq3(z61~1LfPAq#P@>OP=n5b*iehFfY{LET5o`S31vS9i9^-A1F@lw`wU`3#sA5J z&hCOrFoOoWp%Q{fY#9(6szwpShN{s4v7zEtNNjr$8|sKOBz8U$yA{NSc(R_M55ZxW zj>Mh|VnYqu3}Qnq-UVVqk9yswz`!63WuF9zL)BaXv7wH;31UOVpMcm<@s}XBCukWy z0|Ubs5CTLnB zp>}nH*q}8)3=9nYiiopkXMx0_YL_Ac-Byl4U8>$|B$0yW5o=Wu$ z42+yH$ZHt_&X3AD*hS7 zhKm0Kv7zG3pmRfDr6eC{CmB>i7{rEZkOQ%y;>sX4G_-V(*r0(_Sg?D8#G%mpzB1TYzZW`9*7Oq zYmUUOcR=E}f!I*Z;44g_>{O6ARC68@yBvw#1!6*R7ITLItL^URkIw# z1~~|n3D$r(P>Eeg>=Q`r%OEyL0|NuYLnQVy5ZfJ;Zy6YVf!I(r3~CGvj8I2NBC#!y z*p6zTY6q$)93%ntaRL%M6N#MqdLoNe}U5Lc41+k%eCm^wB zdLVJugV<1mb|A42BC(Hy*ieHmAhB;w_kEcoUjH9SNCh-P3RS9$#C8U;q1J%!l7+HE zk;J1xY^dHs5E~kR6(F`0B)NgEl@*4v+d<;6+zh^B78;n-ArfF6i$H9s_;L^%YAE>b zS*ZA7kT}%PJ4kHs9kWnzX3%A@P_`t94fTMMCP)L6qm3kC2x3DuSb^EoZ)F?G)hB`2 zQ1y8rHdIY75_=_x4Rz=S5L+7T7Y5Lcw4epEAl`nEI8@Ck5F6^5^B^`<{4Nsv1&9sn z0lfurpo)Hg*ig-EpetdaY%wIZG>8p#guE65cyH_x1_lNrkT_Jm1&9q*6Nto)LSh$a zfyzFp@4=VdLfK6qMNoDJhz&Jp9*7Nf=u!|Hw7i~yfng=c5m5FPkT_Hg_zqmCgN`7H zp9ir);-Hlq_hB4RuNlOK8uS*4&8!VNYkhiOY_wdxCWsAHV}!(Z0kNTu_C;ccA+eJ| zY^dY1Ky1+RI|c@ZJZ%OBVJN#2Bo0;60%C(4%D})d1;U0D7c)T|sD?#I>>VIB)DZ`f z*r$-#7eH*N-kV75*B~}j?-wNYUnI5=XsK>7|PZFi9>y0 z3}QolU;$!7#hpQHsJI7+4b>Zn#7+mXp$;m5u|fW?gmFNteL!re=E+FxB_KA`vh^S~ zXq`T28#2hDP&W8JVW^suAT>}2-9%!8?-qutd8q@cuAqwEffPX{euCIg@qZvT)B<+U z9lubvEQk&D4fvvAC|e&%+#1A&s&_$RM}gQ7_4N$N2o6II61xJ#hHCCXVy{7BpFv_j zL}GtKVsnA+@P(Qqi^Mhpv!{pcPZz2W1hF9wVu(UwCnK@TKy0Wv4Inl&u)0BP(3S&G z=SGi#K^V%O1rmpE^`Aj(sQP~(HdLHfpMe3^9S{bwp=zW+Y|#D`1_lN>ebD_9P>v=@0;&jngE5rt z3=#+Jw_spkaMx#G05$7DC3P%F9BNq-hz(Vr3t~gXYmnGYAU0G@Cx{K&q5#SSy&ywD z9MDBtAPK0V#UM7+pcNoCRD3gt4He%3Vng-bKw>{cVt)p)p;7z?iOp&N$^=jeDbUr( zPzw}6Y|wr~1_lOI0|o|RDBA!e4pn0fVnZF_0AfSMy+LfKcmRkE6$jtj3>8m6h}Sb@ zgE&x$0uUQ&*#so^ED#%N&_WO!v@(~0fnh1gaZvUKkT_J$J|y-T5F4uI4HBCfbip&M z&Bg`dsDomafq~DEfk7C`RtAYf9j5_eLoF}{v7zD?AU0IJCx{JI69Qs`#`zf-7$QJs zLfOe6aj2TSdJqR{P%RR>3B-mf>IJc(Y9@o&Q1N*nHfY%>0|Ub%kOffoT97zY%?=P7 zs`nTY`!tB{30Y#va1F$PD!Kz=Lp47Ku_3n?FuVp?0A+szi9^+Z4#I$CGd9re)=+Ul z5F2WyJQ7<4#D=QTHv--I1XW~;B;f#JgVvQYFfh0nF))Cxt_MYqKS&&^ISRyv>Wv4n zq2jqn>@(46%LiOp&ZYJPyc!oa`{V%I|r5&?0bY)d4zGl&g!kQayz+Ev5Az~E=hz#t4| zM}owmYEnRKs6(?rY^Zo4hz)8aF)%Qcg7iY!^$j2isG@EV8>)E%hz%8=4PryZ7l7DM z@zo$URD1)74He%FVnfAGA+gVc*iegaK-i%2kAdMGhyx9-??`M0(Ea96aUKvGs#z6@ zZHL5mM`Fi<*igM`NbGzhcBu)d-3m3d8zces0r%xK>&#jzSbS;8*Pv{ zlx+fLPrqlFFJ2GY6bmYAOc@wJ6&@&+C4;1)?#ctPq3$XMv7zFPNbDXE8>(g^hz(UU z2gHVoF9fln;@~Ufq2f^+ktFtj*ieasAU0IP84w#Pei6imI{G6LTM%^XI#gU6%$|PE zC||rDv^to9fx+91fk7C`4g*O;jZOryp+={H*ii985F09924X|S!8gf6#oLg?CxX~e z@o6A7)UNtxhZ@ub5{Fvcjl^Dw#6AvU zL-n2mu|XS&85kHYnMW`%2tzq{K@w0!UqNiB1;0RSs5q+yqWvX;#FhlHq2?%o+0)CW zlquIk6LbJr2<#<>WF&Su61y9TJr9Y!35mTMiG2~ohMIp1iTxOfUH=}$fx3&&l7RtK zv4NZ+4`M_8qy}PxHa&wjaal4j2t(PXAaSS~2M`+?9ihdp#0+ zhc&1cf@%O?cn@ViMN;$*iOmGM{vE1@8;LD~#Fj;3tAp53hZ=#{kTq%yW;P5A!XP%N z7Ip+lKo$9b*ihdDg4j^;7!VsOo(N(?#dAPxsCXfW4Hd5ev7zFPAU0II2gHVoPqYE` zLZA|JkR%p@*iiBHNbFr8HdOO|5F4uIEE4+$hz(V97sLknl7WHY84~*!f?dzR47!9K zs)z@PEsDg}2C<>VhzSzg7Kt4QVnfYIMPj!hvHOwOOF?W_Q1~-2FsuV}!0C@+I}&>@ zhz&LLA`<%v5}VBqu^Lkl#5RYRBWlOMAPi+IfW)Dpr43?3L&%^W#DPj!gV<0BFC?}< zhz(T}1!6%4# z#Dlql%!Z{2K*O1t6Kx}BD`-;T=hs0(9 z-6Ib*R0_m~Is&x8lM%Gt9n_C^U|rAU0Gy0K|rh$04yZ zL2Rg+awK*Qhz+%DF%o+X68jK{4fR<4X(Y}SB=#*38*0!85F6@<-yk;V@F39XRUn^1 z*<7GI<)LasL2RhwRFK%3AU0Hu35X3FJ+}gJpc1YiwlydzGB9{LGB5~3*&!ftsG4{X z8)`uchz%9b2eF~zB_K9bydK1cinoB+P&4N^g35m=XFZa{Q4kxd`2vV-198w5kb|J? z`yg?snpYq;)PnaQHdOoTF~Z4Y9D3||VGtW4 z!Eh0YeFwybs(FRPeh*?p4P|l$opc3>CMhJgG7{So#D=DPComhjBE}ocfoKk#{?a~Q zxqc={2x|6PB=%tt8|ubWAhtb3+c{?j24N`sCP*Br<_U-mb^A*Y8!G+<#DD^ zUV_BlJKfMZU%dV`lF)x7wy-+`10&RI86>t5hz$)JYb3S{659*JhU$$$VizE>yC7^( zdSPIg2jPIijA1(x`wSBMDiZrOhz)hb7bNyyBsQ}L!ULj6Y)vG#g9p-b{|Jx-G{g(0 z_qybZOEw@0wIi{+r|)&i7q^{;Bs3R^y%34L0*So_iM@HcpliN({eC2&!$|BCNbEC6 z?2Ab3t4QoSNbCnl>=#JvH%RO+5H@60{Ez8tUGv2~nLQCnlnaT?hr|{|VoM^i6_MDg z(|O%Mqfbae=16R7B(@V0+YO2Bi^L8@Vn-seW0BY?NbC#<8e z*d0jh9whb@B=!s>_5vjK5+wE-&_oGrws-@Q#116(9whb=B=!j;_IV`sWhC}(B=&tI z_A?k8 zkg;d_Nv;Ba#)#>X+y(xOJEmuXs0-6~f~Y&wIe7{|*V0Dv6!o34bV-2%f5w98nIP)O^qm3){!A*F)42o-{1{uNM+z4BGv1iK z5=32@{u4w!nC>Z5;LrGG`b-dIGW{ip@|kWaT;R``GQAT-bxgkrqNYsO6e;j$Trj;7 zM6H>AQl!A2Ng`*ulxTq;lSR09`M<5=3p7 z{u4x{O!pKAIV*qqEb#(AMw{s`#S8oy|4g@(DDY=IF}+iwz@JH@aQZEY0zbx%>6(%S z{)~5~SAwV)(@#nk_%rboO_!1?@MDrFnw}*EHesh!fj{G!>73F9p!MV5@xt_%AnL|+OW6X@{lT3eDrWjk5S1}qQx0r%C5U=3{UnGwGF?(09L$*@ z%3}IX5cOs{rvf+#B0-eR^pzlL#`K>c>d16YMX=mV5M?v{r6MRCTBlnn75Fh$Oz%`G z0NpWsQ>nn8$)IbxmU4j~=*nT`0)IxE=_f(dpXrh+1^$d5re~@Y_%rEDoW4t?po}qQ zx}hpK1RFtA!SstDDq*^!T7f^~mg$9RAWNo9KcoguFM{e|rHSeV{!A=Wr*Bd(@MH9t z&Ztq~&sZ@%5Jdf$z7Rxxnf?((ZJ6$;S>VrDGku~a$XRoyKhgxJFheb{IgKD{%JhpM z%4E8tHdwF_MD3V<5Jcrn7t{fzzLnFHbPD_!U8Zl;Dez}}Fr85s6osp%2k930F}|3- z5X4njGyRipfgh91+UZVu1%6Bl>!(lBEAV67F#Vxkfi~mQ>Ad;{%B&#=7#UKgn}V1- z`xqFGO@F8(Cn6xg06Gx`TzY_r`st1O1?r4DrmqB1^QT_~Q4^;B1X1nN6%7j1nRt?> zdl?j{G47vU2;$mgOrK>?pvD^ej)CFZbjBzx;psOF3Iv#gg&3#%Z)O*rW>_G=*f(9! zut1&lm=Ghwj_HghjKb3cK*CF=CmI&0GuBP-G%Qf(wOGN#P@~Mi06O3B*Yw0~Lei|i z%o!P;Pha?qUzzdAbVj2BbykxIMuza|j{l2lZD~-=$(ba>>x(Lfx_xZC~7!@i`du0%$Uq~S!}xwQ}Jann3{ztx)R%E zC5!7qU?O0XcjOjt-VGB0sbMxUHJiR6T1$g5Vf$9i68S*SeGQ14o?G=97V42DT zy3iRk^v}|*!@$5K30iW&vI4{e-{;KC!76LYz`)GGu5QS{z|6wBTp2{Mua#q9U}a%u zVdqt2U|?qCkXL75V2P1sU|<#jjlZx+iGr?m1|6@?@&I&Iiz4XI8y0_d(6!D5pi7Z2 zaH}vdFzZ%>*xJ+gSC=SgRf{t)ut4s0W)fy#V1eB044S`W(bQ%HS;NH2#K6FI-*`IX zX+x>$$~7fIOkP^k^-mj0F%=t4|G%MJOYMLb_?G4lMg|797ogjdT^Ye_B^?F^7Ei_* zAaP0I>HZtbrKaz#DbZkTp8l++M455QbgtTxI7>Zq1_lNJ@Z7(EycGijlYoj40|T=_ zoB;y^ivZ|!BvuBNnTnu`nA@2c7zEkaoNh2NFbJKQzOc4LhVkR{eYGWGxeGw!R08&( zP4)~dtU3$~9O^Yp3=G1ttPBha9J-*JkA;jt_vGqv z85lT(EL9j7I3U+H3++~5VBmmU+bncYl!1W*a&5EFr|FJ$CF1qpl^7T}ptm%0vWSDO z4rSqCW?*1ZQDl&T%?}&gElyV#dJ0nGI&XS7%`0ECn(7S#&^iR-85Rp!;XngOZSdFKC^- zz>Mkd>PlqmQ$SO=0v(|JY674Y1WW>pK#7xqB?ELfY!}E379AM|2F}f3W{f2R1LqDf zvjudI>0vOl19U^{B@k1Pjq~bt76t~PO~#-rYQKVx{Sw-s!N9qR|(@>(!S7pk;!1*DCiGe{;NKj{bY(t5-$SRQUzWISvYjFO23{l+yQVm)w!uc1h znt^5G^qmbQ{*s_um^e8YL4Fhq0)+r4qckf6gV>hoij5@_jPIsfHI_KlM}R~17ib<& zpaOIQyFfB1e+k?KT|_S6rOd#&T1HXU{C^iL(%@`O21rEtGFbE0ogRamP$meEY z5Mf}M{=2b+JEC2afq^U026P=VD2RPPcQ=Eshjw59UpCCu1QKO26lP%HYE1%NhMUXI zz`zGm#=rtPq?xM+bc-}^2S^m8lrM@AR3xmJ9@kVNUT+B65+`s1v`b!~T^y7h&kBRG zV?IcYfSoSLi=eeqYyyI+ATMqO-2^SL1rz}SpjBX80-z;2+ybB_);t2n>L4%r$br20 zL<8i-P23C&0s>01ATK7!fV>F0O;}hUoS%U~L}2&yFCa(c7%(tM3WRAgFh~ik(q&+f z7TB!Az#t>g1G+{<;F}2pgPg!NIR*xKfk&YHE$~a0fk9E=7wFJdfkpBR49Wt}^cWaa z1VHEas|wWdgKj!Hpvb_WF7QH-fk8vS*o1*WQ@~A{fk8_k+nj+xTL5%^u8sh+76XH> zK!Sig1A`s|7aNy8(|ypLcO}zjHJ3<NPrkuIL!S|ssa6dO@VBm^iG6G#b&RwF)z`zyBbOuyTafeUuZz+*C;DX*n z&Yh#dz`zB)iJUt|oq>TX4s50Xw~qk>0~hora&BIbQxcg#XJ$!q^QugL-BO}jzg?Dr zfeU&SIX7reDi`!Ba&FKiQe3dB$k{h1`9i#$!6*;%QA_D^#^eS@hNsJ5(T;)uL>S_-1~T%BBm)E2S+FS# z+@L$2xz2$(jF5;p4~Yl{wgVv7U0?zo=*M=?l!1YZ3w#+1+dMG_1}<*!B_v!DT;j~2 zo0qwxL5`PTE&`3>az8O)VBnHu2A$H%!o7-}fq_ek`2`~bLp=vKXh{*5G&ATj0Uqvr zkf}1vAZH42gAS19k^>tn!aWZZd-BXCpgT$#*ft0SeAvR&7281`cjRP!&|q3aV8(8Q3D2L05SkYWMEy(7!BAeTWY;HTm zTn0AKO%z-mtg}ESMR0YqCWEdj1-q~ZY7)2z>tzKMVQkz5Y77iqeXNG;4D}40+}lCk z?q>y+FFxEaL1pX&uoDBg7l5K{BG{5ZZeLJbP6Bg+xIw3AaZLt0ESUQjD14@XIUx*e zb3xgDD(e%FTfDetur7eRWhSy)W`W&O4|U9JkYgA)8Q5Gw_RnF>=LZ$gT=Q99!F4Y{ z*1Zs{8>)E`L^JmSP##ze@dyJO=oVY9C9I%(&Lmhsi$%GXv4U=@6sQ6XlnOitofjie z-)#n}V!wkL`~sjOxL5>|*g*H1v&{y@)jCL|vvX}^jR0N!3l7pvP=_e$GB9v$2Aj#o zz?Q_yz`(VI)kFYPEO2dSod{A7E-81gf=f!CWCpICtSdlgZSoW`aP0y!>jfFuE`iFG z-K;4fonBn~SkHlUf^FIlwFw+~2avsd5aMM9w#}d{aENs-NV7NBF;>vAO59-0$B{Lk zK-PQ`qM7@vJVQML*D0{`ycpO5I2jnYPP5(u8O6?Zj@1Kn!!6jT^H8HiKq=({IB~Es zutg~_FmPRDRS{%h5RKrv%z90bfkCVRjjnkH^8Yx>?^3Ay$KF#F*8u;-U0`sm;^}8ZE(Pdfi5WJx&!v77}z~`!473$ z18uY6y2lylv$v5Ca3R z=JX3aB_g~RK*iTPR#T9W|MZVNC6e``pd#}tYcxnG4P+2FI@v%Q2)H=dz$M2aP<t&$)yXHVde(4 z+`07F>We^EesVtowL10LKpa*EwrQYR%7Cp4)aqg3GGWsJ-HHur*K?VIbu(~-8unaf zU=AZUsAbP(&IT%Yn7BbrdoBwwhnay5wC#nGM5aOEgR^3D4v{>Yz8hnHc(<^ zsOP=~a=blT0wV*10JknEf*rs|>qj!DB7vb_{1D!$zag`rf z0|QS=W*GyQKiC}t5UT^gx`iM{1%f%k3~cfscLcGW0U0I170MO@x{)31jxdNjASQ)_ zO@g{30<4)0;==k!u#M~tY?HYd7`UR?K&N1FiF3uUO$1$MoLQ93z!eKt!ocmy0c!fO zX)u98>I0}CjAsMY5P}SBk3g9rfh_@aey9vr65C@D1_rVJS_}+a$>1;-V*~j)1sqOd zFG00WD%b+C`e0BqE)5(6Vn(2-NC$g@fz67Ifq^T7ZLSCd0~ZHZ7Mn2W%HXM>=CZv9IfR2NpDkMymTe2bX%&(^3&DW{%5C)wTxH<& zCALKr)M{k&XJKHF%ucOj;HqSk6lGvwV3PtB8C7hmq6`dd)iMkWT=i_AL%YBg`5aLO z20n1M0X3=kKwJh+7LcV}23)OdmqZyDcruF^xY{5=$O8_~b}&bPCnY1Bp`NP)%u`@s zivm?aU2Ka$S4A6e^|1X1IsFzWWAuUzl1wdP;OYabW?)+bD$e@Z?tvUN7u2+x!X^&7 z%voKGfq@T{YxzJd22K``DO?I%v)Sf@F8>ClO|Cg$HUoFK2B?aj%eGXEfq{kF7}U&} z$F^DwRF~_5+W+&}Hi|JY@Nn+|d3picb}>-A&j8hY3)%LHF))a57l2}T3EN>Y1_lXk zP_vb58QV!Q1_l`hP8Mrk1_n-+d@wl^Ouht@pu_4oSsn?3WXnbCK@_(b0|Q$*s7PGF zrVBC)Qlo8S1DygOuohgSZ3T^O3jC1=RcN4VWSIr*m_S1~R|P?R#wqL!3~UT+VxYGE zen|S>pv=I)brQ_x;^Ml>RwmBCz>}L;!N7G5oEsQ;ax?Q7>bb6ic}(0jpn~uQn8U(t z35xTZU=AC12Plc&Vv`qVVBlb2dk0D zNQZ%eyOr^ZI0FOt>Ko7jZLkj3QZ)t!Zb@+Cm<@EPJ+~(_=$JNfP$_z7dfwy`SyeVk z1_q%m!k{D!@(qI!uMqn6v*@`wu*&}StW z7zA(d)aOYtFbI9-W?N8X^SKxq7_LELqYgA+25)`z2GP7#Mh$Ob?h^BI>*z#NIE(z`zIU;PEX2jSCCf@T>&&j)cT{7#Mg~fdYm> zC{>+-foC$ zB!ucz85nprf&2ip8xAmslYx^3D2?MtPNEa`d!w7Cm^6)W&v@&t?ax+Z-KCMKk zo>PW_flUxp_KAZ{m%78qBgc4HmVtqLtpWoBk33kEfqNMr0|So=BPb$SxE(YY7C&(0g z#$YWO28J|7={%5Y9KaT)GfG>sGcfQtGJ-A;%wUvG0Hp~h#u?KMXOu|SgU-XNVU%VC zMY22NRapjxT1M$T77PqLUX1Ic85nLbO1}Z+B5%ev2?mB+j0~JCpi}QSSwN$NoGhRN z=Gj3J1v(fFTt0C!uuTQo?!y=_!@$6D9duK@?jKnO2KLnq3=BMS(89)nLB@rV*N@E_ zG?>{n{o;%gaY@iP7jGaa*|7+{GGSog4FW|jn~=_Q#+fDJnQZzD47_0=X%0r&x1jOM za1e)!QFak%Ffjte;bD}$V!^<`8woO(k5Tp|69WTp6eyLdG0L6?HI$=49Cb!nP{QJk z1*IzuM%f4!1_s_Zkc=jyY|HeS#3mvHI`oyd8zgQbbPc4w7bI>W1UloLw+|#9 zAtbNHz`$ES0VEM4bP2?n2$HA~(vVI4J5uq=nE(~ zr-Q_g2!(?}a~4Sagir@4$Yz7YUkEj5GcfSZ0}X_|5n9N=z`#2nB>qLH0%X@Bkoq68 z^~I7547`g$5)zEEpdKObQc!PRhEX<0nSp_KB}hhrQC5bLfq@rXsHrf@g3g8HT@Sh= zS&LB?)KKEx2x@Q{G0L9RV_@Lj1ZvTQ9`GEbJ0s{jGgX4jTfs+L^z|Arl6c~qNwXZoC70zJV25B_&S#} zXm$vknx251Qvj|-c%OsVg$yhmpb&p4tjNH?0=j0M_ai7l$%ydtel}HRU=WHmWnkd_ za&o%moDx|(Q1#0D2b7G}g!Y4y%U=*%Luf8&xac2!> zDP50y!t^O~N)$Mf6&V;zxJ8Vo@0n8~Q4eYs@bZAmG8^s*pa|pzmvRo=x}Zqo1IxH@ zpEqM*;N=I)cyPbg0*%arWqi0dgPb7tVNLf zIEb?z%u$E57M?0Y3kXpLwtPMY2HuT~$)FZ)2JcqJjVhovT2VFw?>0tIqG#a#tir&+ zyB*9C;7-$EVBp;W<|uIA2XS_RIR@OGO$Dj~7&KUO*9K3=G_VK_%KLaK+5Ptu4U7zw_Ffj0bV+2i_2yl1RgFOBn9E>vD;EL)8m?H;n zhw%Oc`$GXdA;bHN5mf%Eac>8uso#t>j0_B#+)w2h7HnYrR|HQPP3H~+6=G^&&J6Ct>4FPO z)as9c4AugR&EqM~HDTa218biT9t-6)X9AU_3%Ef;ro0wRpt5u!_iKDv~T2-FvY3Jou& zP*nzoRXj;KsSLcnOrVspM%o(`^nOgBhNupsG!rP3hJj5qVU(T>3hyW|&lFUmgK`Zg zOSm!v13Rd|%>m7wgPPn-3~Zo-rFmnRK*zRmh4Q8|fsV-nj~(-7GJOP{l*7Qy1GNxG|tIu&VFz_x1vl+OT zf@Q{TZ<2a;2 z!*{&mU_%o)q_sdz4+&;aKRby-`UI$%C<9hm#33C5l9L7VN;srJR|@hfGlNR}3J$r% zf=mWpedhCG3=BQu(t)7L+lbjvhk;>@xU{>1D+2?s3A4Kn1H%?^>D8cUHf07iZ+3`F z-v>F(j2V;$Z-`6xgEX3hd3VI6Q$ZD{1(^3hT-ts*%hD1}#ud}`mX=7n$AIG0jv3Sr zcquMD6%^c#U{Aafmj)+DS1|9jxHLFLx-o-N4fPMmX=7@ zi-Mxp3+yBo3F%l+67~lBQ$<4B3sfumfDKcVkQM^XYWgz!>M$^9NJuXSMY$hyEQlv1 zt*FVs!0XQpDiU8POWT3UiU8(Z9R`Ls%F>TOO}!vyP&?>@vh*7x1_s_>W>7iyO<6h! z96h06D}E|Vy9{IUW^hPEg8;0rPlOq(PS~@Wz5w3aCg|@zgUg@Fp-9gQogb7}!A# zZcx$$*W;jOo*XX&13M@`ff6NDlzjo{l0eXUA4s9W?x@4S0K#B-PyurSJf;OISJ**i z4JeGja_kK3AVE;LK>3{YEF4169!xXLNEQaRqo4vTiFt*9HUk6S5hPVNTS11TgVyc{NQ15v5dhtxz$DP8 z3epv91sbg55C+XY33Bi~T&BywAT)Kl=ZX?JPLM`<4!&m}rx&a!5e)}PDa=y?jbnnE zs0yHoFTPixtfK%Lqvd-I8lq)jF|c4@;Cr)Cmw`d*1QQ=C<6c7sNVUwz24*vGzm#TR z;A00jHCedbr{7soBAE#)Px-hQLBXocy^fcGfsY&9z|-Ll1(^pKB+%vN1aWx5jSM~R zsUUM8g9Q5E`2{|HupU$H9v)B_GJ5JVFqm=cn=vr(34$wUbMCLx<5rePYJl#sbl-Kp`#)R$v2eMe&I-g4QP4a{rw^e`SfWG-xV2v9C&JspwOGoDE(-9@v0I{{;!%0418LQpk-D;Owy&(SFb9ORsnUA_;eXT>#ahW zq^C-P5+&HjVNBAylo%NJ3>f>TzgktIR6hk|gE3<@3j;$Gle8r$(oDd-XeQ}Eken&l zyD?1Co}l4TGjOvgfk}F)DFXwaIoRzfOwyvDxho5>$`U5&%a#lbe3oEdDUHT~v3=DiWU~UDI^yTR@SC_c(g9?5=XK9kmUk@Ivo0y!#z-R$d29j4f2s)X;80H)` z&?Nx8^$ZMw#taPVjG#Lr)fuB1jTk_SY9Q_e?aBnXbD}ZCH74syWFT$?EemCWy0Ktg zi6VH613ZB9+8Eku5oFN3ZOp)+#|t{bI~^1xVxTKk=kS}u!YUmUR&y8`7?kgV!ZRHd z&U+ad7(h$q7#K5C*ccd?Ctj#C$N}A$kOf-x=fuRo0QLr`;fWloe4ti6a=9AmDL$zKz1^yf-dz1 z>jh2Kf=u->g_xTEutq=vbb+F3A|nGNoJzql#=y`FRieM4M3@h(`5;v0;PikEB?dN6 zjTjhif$fT7Dq#Qxw*`Y59}@!u=p^oUUVjg;4CG{3thuN&#xNQ%s4jr%I|$V`%?#pdlZ_>c?w0io3|mn2IYacRePCi>0GWCT zMb--zPAUi8hRzTNzTEXNJihOO z;yaWH7T9DPd$24k>WMHnHDH3nx05k`<}q0X}h zwFJ=05zxtWAeTs5f?T3Iy=!9kVAIGYdo$vY6%Lh>0fV`Xrj8r1jQvFBfu`~LYmWVo^hg)ldVyz9bwID^fJiOBylFKiAEs+3+ zeHP4adzjten!_jGAtY#HQD8DPe`D zKUzCFuFxc6F5`PrLu}sAb>Wnc=69X7j17M|UF0?YNgX&b=St0|eCYL~E_SsEm zd|)g#J!xl&v^=OLxZ5zY@}fEFuC$%i&Bdj7$1VYoXrfa;6d8Zy$m|W66ECx_7E?FQ~QEL zB`l1((*t&uh=+peAEP8t@%kR@0?-L?jC1rIU@mwMbpfP!eGhg4w0H$6g4zdK#tsT% z4M=eUv8!QEiFiFU-oJtNiuf^s;vG~0G0u^5gxTQ71S!BFe)MAk72sVUKNc`B1~7qI zVMmx57$A`x2p)`Kniv31kRUT44gjABv(ABm!8|i7n}IQg3A9J!Ju?G?D1#~}tAO05 z28;f84xj=@M@kKJ&QN1L0|S#IH2N7BG(eYbgCj`19$e-NfzH`Y13Nq!ly>LvI>8*C zhT`xvu)}#-7#Pe87#K6a4tHmPIXn}^;UF`h4hOkzt|QFh#bAdQv4Bpo5e7-2IQ*_7 zJYZ!+K@R_j-QnOWA`8^2twM76AGpJ-P#j(bcK8IS!)w3}KLvMqEsDcIW-} zFo(B;9sU)E!_PROh4=#}Y$2WncK9Dq<98+4;icdZf9(tl@s%hJUkP@&Fe@a)SA!ky z%L)teH7E}M?F=i9EkKQ(>gkI6N+coeO<1znJ$>UtW3lNCdrBaId)^s~8^!9uMKj1a zaM3Kspb2uGkq78rq61(@L$0cS6jp)LoR33jtL5lvO$9TCfMb{Y_Qc zX?e3NBDlR^r6knRAmhM}R%FlwInQVZs9W?A>}V-)HR9_It42P89X*!~R*ifFJ9{70 z*`LAA{sDLP7nrk6!HwImOrX|nD?7AA^>sIZ`9lp<#DN;PS#D5wsxqj8PNN3rP|$uj zkk?kZA-u*3I>86jeKt zz?Fv^tUh`Jt&cPq!F?o%UGEQ;NE(6@A^3JeZE%AZQjsuvz@k!{8M%4h(9bj038UK}TyK+-?G?j@24K39X)i;U7dFQxQ14VU_hX zkSwUO7S9IP1v;QEHz%l!V~7BI=_lMvoGi%U%gF-rk`M<2gDGf=jggxLG%#q)0Zmq* z0~(-yg11dzUfSdd_L32}a+*=kz;N0V>?Nqv3>efvHPn)N28MeO2}TnJjWDo7=N&1L zst1`3jt71QO_1}9mVp|3vS3FifgR204T}d^sG}iuyDZqzjKSu~xhV{c@+_c*&u$#B zSWy6b0TwGDGoU_z*HYl@4LaX%ofp^(;7*?0hI$5u<6clNK-+?9pnbC-iKo-MkCsR> zLh9Q{aOp1(N;XDd=Yk@Yan205bB$1(YXo&JxFrBm1a%K6pMnz!q$$F{(C!U#j&41u zw%-G5l`_B@Us<5q#tv*BC}0`qMEbyj#}36lJE(o8g-i?#j1J)7D1--(BbW~ho=hKj zwgMgF4|Wb{gA{l`#nuPx9#$uCq;1?&0xje~n!qu~!=MRrgpn2K_D659(;UEs+%;dA z)4ZWhgS45v!A@%hB{#6+e8G-c26vnvm=ALt$P{Q;K^@1#pavS40~KK6zS9G*7>iBc za=b(dQp7#-0XY~s(RYN9^3#65S_tSo5T{4i7|>12rl#8XqDG7SFHC!Q>E$N^_>@U3d8;Nr6n z?3{Q0uu3HrTw?Ka!YY+iaG7Pt3CkVnC}q|^e|Yr6a|h_aDUd7I`$JqAbgD$A{-k$F=&F^Y7_&y%6T6+KtaQP zjC1&cVF9`i8laFAvk#nNlH)-h0FBc#9)Kkg(;uKt=0PyGfs=v33bgi{@em7W7J_MF z2&ip)7_9j}C$uz^3&!*HVf0l6mzQUuKw7{%X`>4xV@jO0M00DFVMK4LV2 zjs&QIDg@AS-)qww&y|SOGY5d>;Z+S}G}bUDmVaPM#%xEwMFgQcpUP&YwR)laaS z(zqZk#NXgGs_k5`JOWv#!89=d($xCP2x@Bm=7OdogD?ht=%7EmsZ|;Rbq}_t*47YE zF{(2?|9lCnE~ssF5~>>1wrXKuU;wqP?n1>tZ7WbK1XLXTnZEFRiIno!dIko8P^bkA z45}Qk*p-FGVL&J(L3}=6A_FeR@l1_0|P@dLbsX+Xh=Sofng3@4Aew2 zU{DKUWMBYUwE-@{pjrmA3UqPP2QI-{!(lNc#tLbmKnhebR!{?lF&NUTmS6?vJ!r2Qqz9Uq5M5AkYxE!e^4vr2E=8IMht4O@!OA3A!}GN0}Z2q!hkg#?h92=FA1FgU@k$1QwK)%(j_eC0+hGiZ|5e(7|&cKoknjq_p&ZsjmFj|450CZh3 zIUv~p6$IURrT`joN(37Y9srz^6A25cL=>|V!Dg#M2Yf)PpeX|* zsG=jmK@|lm`H}4cPc;}_0o_KE3$_q+dg9?0W>&M1vXXy9OK4OFn?5`7+VE3Rs*zh02D^xDis_)1`G^F|3Cx#onUkPz~=mc zo70J6PNyc+AaK$FslpW=Tc$f+EiuwlZD3$H5d{x=HBd94$BKdBAzTa+;ToVOvF`MR zS4+gA!0G5GXoUYX*hwa!LSW8=7+7QEG}uXe+zbqm%zPTzO(12s+|)8%@LGwHpJ4+7 z!;ENzn?PM83u^|3jc_rDo76HG7#Ki#{0KyX(TYJ8RIq}x?Hp)5{(JhwYbBcXA1oOd zL}FlOLiO*0>Q{$IFj_IF9c5r(0NHO15dzIdsa;`UU;x=40vCho2Mv~jBy!OuK0pm_ zfJiV}*)phsy2Kz?%!G)+3kNk$Mu;!gKqNrE0F4=de4znpG=K}9X-`V{>mfrTv0Mxc zjO?IoRt%HDVV@We3ww4pP%&x?4|{etADpg36p)u9X#f`l9shayzRHU6K$p3IoD&uY zc8=#msB`k+ilEN<1C6RChy}-?Ghufo8Y#>;|)@eg7kyyQB?*_ zkcCE|g9I2Gz|H_2|IIkZFbU?21{7yBAUne`3B?)UpoF=CNi+!*{<_mI+$mu}cZ>=o zbRdoanF4l<3WFxdTBG}N3=E7D!HxknnHlGNg*#>%n;$G>!stK5Gg%sZQU2uY|SU4dOjW;lgOZ03A2~2I{dc z28S%D+sioT5Zo(^p&<+DTPy~LYzPmeZ?TjOG%r-j1MNJ3G(r4=Ila6w1>`dD6nj0W zLIagNkbs4`p_P?^fpHty4N2hQJ~|y1oZC>`unp{npDwG*s)w z$iNWVz`&pblLot-mAQorbdyvBRMuQKz&AcRYINvcn?s17EBqTxW zKEWZG0U1J=^SDIF7Boh|kqOfXj$;Nj(0O^HDh6gEcQ zpvmB8;OqbzS7w~!kOj*Q&!E`>QUN>zX9s8n08+#X9y>#X7wCd6kh5QBf)f}w=uRnc z%ID3RzTruU3^?iQPrvx2L^cBy4Df6Ts+NsxK&9MQusa|VQx4fMcYKAq15z}61-qk_ z7g`tuWaEyx6Io!FfQP2Rw!fI(^Rz^oEwO=tK`eXv+NUKN^&gBG81%DI!&M`bfq@|x zsS5>8av+<)L8r{1338l~G^n1?W(Uo3gNho)IjT7f3^w59hT80)5{og&SQj)NuMOUR z&KPV9UiqNQ4r)|_OJ&s@8My1=a|58Yl%Q~YlnqH-tOl>N-(Y8g)^vd~s2PJA zD1%luFfj1vz}(NEkp{2uqZu7Rr2uIB5Zo=Z3jlR8-Pu8nFOZu-r559ypj-w9d$60` z!ERm#3s{f@B#KQ}s@5|wFnWP?{^Vs~umJ6Ydy>PzVAc;huFszx+^~iX^#rhkhI*{| z7#P$785kHqvuNuP4pajjoeA>I3Ah-#8?>GS9=F}Z2dk3ifd_eEegNr%_yJMfgL87fq?-$!4{s&z~F$agwcROV-_e?PT#nvL_8B554@oJ^gvmJ zf#Dd~A5RKk@eqYF$QT74WV{UW#Y|9Ii(v#E7sE8s0i1t8xuKw3HsTB!i?#joiN zuSzW0{u(kcNEA$8_@PAD20mtGSOD>%87P&3Mhig+6*Ok*1(h&|Nu)q)@2u&3uS=v^ z=Qc1f^i9`$T_O)DszH5TkY(ozKqZZ?IOvY~0(k6#(jTbpb9?%N*CnFT>k46hYyeL% zz}jsM%-^S9cwHhT0#X3+4(OI`1~Jf`m(%~fhSdwOrtOSEuw~$JDlC>6GcXv<1(oW( z-~t*l*YdImW_K@&-M!$cjbMIAL#rQrHeMq?1A`ejv?nlwjtqi@HpmR9^FU*Kpq1tf zhDERz{4z{6cnrr7T&y{$GsZF+GH8H?J~2Z9Jma(&)XU2T=XTJ53*(&S z#S9FPLO2(k+rf!wdoeuw!b=%QUB<$|5MK-mYn|yAzLl^_t!!XmC@zLMoB=$%1M@LVFfK@D3~7ju0%8yWGJ|@&}PsC*=l5=#K6GV2zHAbIK>y1z+$8k>=szb(+Dkj zz-|L6f&@8cJ!@M6b{dx&Xp9ZyjOgi%?@J`>F#`iUUYZCBjFn&qfP##1jzAgA0V`1) zuoCJ3GjP$j8l~t1>4CThJjfwh1`j%T$p>HfAzBJ{-}DVHN?4V*HZU+~mcoM$v)Icl zg`|+TFG|F@)L^w($8_Bfum&b*mJXDbPC!*=e<+cW1Vzamgt_2l7ND^BHGRQ{63KdL zP+kOu1!UaE8FYQ|esF+5V&oJ&K=z{q$bM*mfMW!t2oeIAF*3Uh>_Jd+js~ll zcBe$P9=u!uTD5i5 zV1EUqX^#knyA{Zx09!Z$3x#jf7k(}gVFUG=#44xn{#+sjt`V%K-}+plP><;ga4B?+ zkAZ>F1{@2ZjfsqNDyv|=uz{Avkf^i)m&LGY8awzTGpLOL(gXDcJg0$1Nx5AkDPEhKzl0~7<8*49=hYu@8G`R!RxR=0|TJ3Z;&sSPIvuLBA<;J!Qee2BA}lBIdJI>s{a`01l7Sj za}K5SK8IX-gB0O%yJH==K$;F(FCC9O@dU0e9E3r8I8QKT)iE%z{Rab0&Jya942m^!T48vh`=`VAZGQ{5l2( z_Vb1e3=iv|yTh0noNj;yXZ1fJR9&oNU~tyqWnchdRv%{@Ed~YQ)XZQVcxCG zu6Dc(3?S?*t;oOt!t7cutUL@1Ak0_K=(1RZfnl)-!}Q-EM?6$xU;trW4HlOQB?bl% z<|$=#F;HM&0AZdIMwh+H3=AO5cc0NYi-my!g!#o>>a-XbK$!16qsv_>1_lu3Yh-kZ zGhtu=VV+7x7cn*l1`y`E#^~}^oPhy^`C1uWdt?|GKse1sm4|@=g!w)*y8PE*U;tsh zZ;UQ)%o!L!nC~H@i=7n%0|@iIVRR`{XJ7zffdCel9t#Er5azqi=)wy+{Xm9+f$uw` zi!Lhz0|@i|V00!3W$`JAC5iDlsd)_38RwP?Z@=VT zs=+qBUBV=D`oH^C*3%E$%Lq;XFwKo+`*Och-?-_GTr48Y7M3Q{6Sbq;f3KXj51Wi+4OxVBV;$-)e53$ulV8CWy3g(*yn3D^uK z3uCZW77Gg_n2aG*#sI8^$=niRmbp2|X`+l~(*@U;iZYr`H(XaL!e~Cd!PZxV*}~ie zs>&E5Z45Sq*&J%>^sDPj^}s?*W|q?%ZGDBAEzB%n40Es>rblcj<)5xQ(}J7X!VF?O zlbI=4)AacpO2rwC!B$T9DOcy4Uh5>m!Du#p<6ct{W(zX|s7a=ffMB*TH3x-*2&3tA z#d39!V?SQk69N04aZ{-%qY2m~CR1ZbsGAzWR5z?G6`g*0W2qREi7{Ag`b!YU)Bx-Z zCKF4D1`|st-vY|Ffbz}3d`6RLEo!1nCT3vX^rM?f#iwm56=gOtG270yx%96zqviDZ zMJ1xsWzUy#GZ`CC*E(M+UvI_`AD>p5mmD9jVqs!th{7{R=9#1LER2xlEKuYuQRFO< z}AGs3o#S z3j<`|TNom1v@k+;wuK3boGD1oE!59B#M9po6vY;1C?=U9hg_}LyB-rWo}kgew~$Ia42fMbT`|AR zT6Hgy&?zML4J7v4>5chi;;J0n3=E7=lSGi%_DF1>>3j3b#3j>_go=^a_0!+xm$^$` zMG|_1#Qredx1dbfQy#R_3TlxK5*u{S0?YyaNa8U_>`Wwf`ShIyWy*1|G<$r2=?MkIFs^uL8=%98t#gia%|Z%(%?DvOu&1g&6(S`>!FPMN;3 zs7ze44M}J+5_{qFhec(|^%szY?jo^YBe7XP=lnu#;6h@9?>2*qiy?{2AhDH@*qTUe zI|v)JvWkJh8^QsHZ6p#q4~ac#`r6_$amg)6LI;u9=cnH-E>o@t9o7y@VcehDuz zBC++5*w#pFPb7965<3ft4La=uW_}ZrcprofS|!K8Fbl!~duJIEdlM3S9}@c%68kz5 z`!N!m6Esi;^^6u0I{=BDE(E%e7OJQiNuqwbXla?Xz5%3ZAM}rL}GtHV*f>AbAv7)g4(Qr#I{0WyCbnf zk=W%BHYDU*ARKVWPeNiZM`CYAV(&*{pGIO|M`AxgV*f;9vw=n&ppKRT9hwbG7y3vN z)<|r3Bz7~~1)Ur20mNpJ-U zNo!gV4%nM!NNgu0wjUBZ3W=SD#4bW&*CDYNA+gsXv3G$+DPZw`3`yb=68jz!`xO%V z8xordG#vvCMLs096cSqvi4D3<4{R^U|8__cUP$aPBsO?UH`D^~zCb9u3rWpVB=!j; z_7x=d10?nvDF%jmuqzlC7=9p0uz*gRfm$Gd#8yLM+as}qkl1lZ>?|a984|l0!B%7F zLvR>oBC(esvDZ((T3x0rbr(tK6%zZO^mL(`G9^`A&~OUW-Qe9;P__q>c*yj~nlkJ9 zc}PO5k=Q$t*vFCBSCQC{k=P%R*#D8(yr9biq1HwBP~iY9%B#=+-J&La{;;cSB+a zO@CTjw!dBxv~wD2gdP$*2#KAB#4bW&*CDaHkl53Z*q|HgU`|~BbHCeRK-s0a9v*iuMrH6*qX65CE;`l9->xO&i0XfQ`^Mv}ja#QuQ9 z2JexF+Q|u8DGp`JAh9)&*d|D92PC!+gbfLVNC*cU2q{SH3M6(55_5)PXE_XwyAy&XmSVYk(Eg7?MUpSNbJigps8L41|J9q90(E99h=I;8LOuIHkFA_FK8;0klc+VeFBO7Z2H2cGHXVg=@&st zzciH@NKOZBq=R~A2@-qLblc{#Y*l?#gllY&*j`BNu<2);%YHK!OyAp5CO-W^OId>L zf6xXosHr@ly(Un$8WP(CiS2~M&YfP{T4t@f4N2%Q68j<&`|k9+t!2UWphNs&QRb_G zaBwyfy8(&ai^N`t#9oWUzJSEOi^P77#Qq6kL((NX=-4T!H${=y%1CTOB(^;g+ZTx) zjl|AGVwWSaTann4H9?Dj>HBX&k1u7 z=<*mC`y!H>`$+7!U^XcH85kH^KpP;T@iYO6y&Q?X7KshIJ{4xcP9*XDNbI9X?9)i> zi%9J2^+=q%NbJW*?3YOF_ekuoNbKK8Y(~%?L8xcgk=VRQY!N6M?0;=22UH{)BC*Yp z*tSS)XC$^45<3xzosPuLMPe5tu`6{Mvfx8z^+*zZNbFfi?Bz)8T}bQ;NbK84>}N>q zPum5%%c2?Ui}ewSwE>CUhs2(P#9oEO-hsqEhQz*t#D0Xt{(!{(2VsK)oPh_lTMimU zQb=qKB(@n6+Xaaogv3rjV&@^TYmnGoNbDH~NCn<9B#A9Z>_bTG3rOsHNNiC;f_DF1B7#rmOXc&iqfgux#U5>%TntZ z!Rw7dH<2?i2t(Pzpk+bO=#T}mL5F!TFfb^A*idmD5F09P2x3FUtwC(4xC4j{754(M zuY~0Vn zYR(K08*0u%FnjtlSs}UllOQ(KobwCvz?6Xj#+F24>x0-(y%tDpMa_fv9}_z4}sWFy|5F2C;=;W2HFb)F) z!(}A)9WZOoDZ1F3+rXM)&JTNi-X!Vp`R zSTHaML)q&=;!rhvk=Un^*jGVp(B@MH28LT8HdJr@Vg z2K9p2P?t^tu_Ymnn_Bq!^)` zw;&0qOTU5H)8mBV#OtB@_^cTiU`j1PY^a?MAhtBbT`txP48l;hKS&&^CKidEjl?bm zv2Q{2R)N@1z0FAM`k5dO)Ln~^*sGD)TR?26LAyX~s6kgjY^WpdfY_izqZt?&9)KJQ zWxocAL)H95Vzb+TQvmqva|S^W2edMkfq_8`#D;2?M`D|T*sRmt*61tOLzRYsgrG_r zL2Rf!9U!(m#N$0S3=G0h_H>XqRLxQ(_GSn{U9Nz(z{6Pe;_tA zKv?Y=7#KmvNir}naN0942t(N-AaSS~B_y^khz$)`TO_siG2>l zh6ea`B=!R&_Dc{OYQcLD8)^=-BLf2?l&u0{zlG*wZ4d{to`XT(k%2)N%C-WDLw(?Z z#100rp$<(%VyA)FQ1zuq?0OIzv~L|W8U|uRJv_q^l#ihX%>zk5Enbeq-V0(weS8dw zeIAK@1H^_}a1X?Wn)3;XE$jp??!iGV1!99PuK-ofa!w2k!XOUlR7a2m)CcBBY$p&K z>d*irb|{DqRiA>y&I7T}g6(1`2C<<&ZU?cU=JYy&hDf0nPXkFn*=s;-sE@ZIvG*ad zkAv7y3(kVrP`wY4*i6m{A9I4(pz{|%S6MkTFbG4~^$Zdq38)X$kl2PGHq@o|NNg7n z8>&7Si5&}KpN9B23B-o_xD3RGno|Q}Lo8-!1+%C3X_+b4L;bo9Bm^~L4~Pv_dI5>e z=z{PQ2Z#;Yo(a0e)`fvV7|Iq0i9?;Jio`Ymv7t_}Lt@uEgE&wPK}hTv5F2#nJOcwm zB8Uz3Qz?iIHK-cIhFaW$#GVCWLp`<_iMD9cqijb^@`X>H|T0uwZ?uXpqE7kdX`w2_QDq zvP>j)J%|nUSqBn(A`*KRhz&Jo0f-GXXA2VhDTobn1Sk`}0dYW^T|nbUt_%#qQ1)+- zI7kr#0|T2I0|RW-gd4<$ii?5RP+zJbu{A+#s2U3-wljzgRqx>j%7jowK_Cgxz9j|* zhHwxY>WFM4b_o)@3&e(o#AGD)93=Kq5F2XdY7iT0<|zcbp5Y#X!|(}-E$Gg`zzEeK zg~ZkYv7r{5BC+j|*zO=U)Z$gV<2@3qkDT5JQ)N*iZ}BBe9Qy*ic8GLt3lfLA!WxO~24X{9?G0i>)kGn&Q$Xzf5Lee{f;dn^i;&nIAU4$5 z6Oq`nkl2esY^XsiL2RfwhmqJ1k=Xx{*b1ItPeLL=9mE0cKVo2D(Dr0t0BsTixz7wF z4)uWx65AidhWauD#D=Pg2eF~zDIhjfJP*X)2Qra?p%}!5+EwETs)?bTNgxTRk7pyX zmmsm%g4j@lHiOtuy=Rcv_mSBAUSMB>Z59KuLEGXO7#O6y7#M^>Y>@v|K@w1x8Y8iN zKy0XQ0zqu3ngk?v7KjZxh?0SUAs@sB8Op%GP=Unm1F@kVn~ua@-~}oKpb{%V5>SKI zgV<1mP9U+LA+g!L5kBJsu|b%@FiJcB&LmgUx#I8hQH-Xqtb2>n5s5$dMY^Woag4m$*85kHCR)QSr01AHw28Jyl z38$?A;L0`~$I}ma+SQj=zS8%YxWYWSarBYc z79cj%AUhBnYEV9i4Yjxo#0DLR&A`A=<-@=LYU+WkXa$Kw)l5cW&jYcc9#{-w!^ZB{ zfjCf!%^)^Z^C2Ym84w$EP6Go2!$lAqYVj>3_6HCf>a(9nY$jhsFN7P!hMFVc%TUk2 z2sKC%BmrfcgV<1m9FW+aNbDdG8){HIhz-?Si^QIT#NLg>z5`-|Jz3Ad@EF7a9lyoE z!0_Ccfk7C`{sa;SD`H?^@Iy-NNNiOQ8ya$2AU0IJ35dND6d4Q*mLN9NOeZ9E1c(i5 z1SWzwP#)8&5_=;O`v`~))q56+UH=%wfogt(#QuuJ zX7p!Z0JT6t{*eK(p}tfGvE4wT3=Hc23=G0hwh>4is>T+?hK7(6hz%9@1+ia38-YO} z4pbr$iJc8%AB9*@0AfQes6=A-gV<0H%s^rDp=>FTIMmS^NNi&e8|q^V5F4t-9f=(TVuRFx%Ab4~2Xvww zhz-?H2V!rB_`Vs$hFaW%#9jnqLw&y*iM<7hy%)rWnsW-ohMIFZ095`%IWIvHP=h`p zv411683P#@K-W}&oWzC1RsgY~dNq;QMo4T65F2V&1cF`9kci+gl!Mq%gBp<7ok;9{ z5F2XH3?%kC5F4s@I}-Z<68jj44b^)d%m#%&0|UcT5C^LH9TNLH68kTR4b{vRga`>4 z5F4sj6^X5f#5Mu3p?ZCh*kScZoE#7vYEUT>yAFxn0%AiA>P2EN2C<=f*C4UCBC&Ua z*igMkplq=JZ-F>a&5x1TZ;;rZKy0XH6{Ll&+90+!C`B+Z=m#?}2t(OcAaQ6y_CR8X zA+ZyJLFNB_h~`v~1XOb#61xS&hB~eni9HR8Js-q|nzIzdhMKbviG3Z3{RzYdJFcFA z;U|a#IzyC!f#EO62T(Rg2%-!SLt-m}*r2=%nmI&bn}FD0Lm3#Hk=TA9HdK8uhz(T} z3u4EBPOf8MU`PUSpca=QvFnl8Q$cKKNX$cGFGpf;0I{KFZkxV$vZHwYJ&+L8=)Xv8 z!B7SUMyR+H659a8hFW8Z#CAerdxO|eYXU)Rs5u2l>=p=H863THAsjG!BNBTTm_42C zsJ>kNBM=*E@e2?eYAAac!lBYgY%>rW8kn{qHs~A;1_lPlFa`!;DBA}l4pkF{#Lhrs zmqXa#tiaF+;($)?Wnf@v1F@k7^&_#Dg4j@pu0vvPM`9lUv7zQ11F@mz+(cr3LSnOp zgQ_B^BK~j&22iC73NBR;8)}&z65AY!Z3|*U^~NBv3y|2|AT~54CV|+X!@3w47^a0Y zFbIR#Apb7}NkA2?M`G_qVjl;wL3b`OFfg0}u|b*{7#OZ1v0sDOP)C13V*f>Avqdm4 zFhb4Yi2zkaP=m}t5>Q9jf!M*IaA06?ieO+6hO&J@;!riwNbF1y8>*%r#D=PA1F=D; z#xgK4bb-u)vZsQ?A!_Ow79%(e8$oQSqEkrh+aNYX1H&T_8+2h60|Ub|kfBiaN02yF z&3_~|ZzQ5b5eKnBX9qGcFvx(|p`h>wU1102KzwWsVnc(`1&Qs8#0~?op$5f(*ic6l zf!I(-RD#&y5Ho8d85o42><*APRL!({B+e2L8>(n668kWS4Rz2NB=%J#_H7Uws`m|u z4YlAihz&Yx5p*9H$PrLBQxqgr!2TD2azJjC1F@lsOh9a?LDnF4BuE7VgMAbOgD{ls z1rmphQwYEVnYqu3SvX`o|IFg%P=;`|DRwS z1_lP!I0gnrsAd%;wgnP99En|k#BN4nPe)>JLt>vtV!w+6mH$x7z9UKS#v_If#E{tX zNNiOQ8>&|iiR}PlLqp3Gi5-N*js~$IpVnfY54rYVGpMinlE{Fql^)n>)dnEP` z5F2XHKM)&gkVFCl10$5Jh{QGrv7u%*#7k(4peg<61yCU-3wwv4Vs3;o{z*{ z3SvXeIgG@93}Qn=O1A}l1bQ$SSkOWi_dm^I96h&gogV<{!IYkA; zh8m=c#C8U;p$_#yVuvEJ<3MbvIVp*t@*ir@RFDMJ5pzIn&^d|>3=9hr85o42?A0J~ zsG6Nf?Bhu6iy$`W?i~gOhHD@;RPTKx_E!)a>`>5+if|4C1A7u8U&o-LVyK^V#r1W7;@$s@6~ zKx}9>vp{0og4j^?K1l2^5c>?oW6>ZsbS^U=#DjsTs;*b9WIrAHq@NwNNlzgQ2QS$p_qb5`5GWL=rA`11_qrJ z1_og$+Z-eg^|31wI{?InIyw%CoeW|_)#rlPt019L1Y(2C1eHJ4Fb)F)!$c4p>a$r$ z?8QjzH6S+BpiLk)$RGv=h7%w*)Uxv+b{@pC%ODRx+4n%=P&IEr`5!hL`yC_!^}!zy z8>)ycm4ShACBz_Z5F08k24X|iOM}=@3*=K77=-f}7(k6<4Ujlgy*Y>tRTGI|*E3Wj zI1K$r>~%=&?MUpiAT~6Ft|77SBe9=?*ig%u(ij*Rp=@p>wjziPx&##DH!Uy+#A0AD zMq=B5*ihd)f!I)kl9AXsNbDvM8|t`jB=!^}_AC$^YR=AjB+elu_6-mlYS2R@_A4az z2M`--5Pv$tm+BxkRIe_G4OQa`VnfBfLF_ze`Cks=K;x+n#0FjH$H2hQl+M5)3}yF% z#Gz_tfY{Kup9^9`#aAP-w}RN4AR)R7#DRu|9aR29UGxYf0cF2NVt)a#p$7c| zv7rVrXD~1@LfMiaHdLY^$ZLFAP!V>BoaFbiJbvrLp8S}v1cQ( zcOtP5A+c|O*iiEyBC%hA*s!UH4Kh7Kh56eRXM5F2!yJ_7^8 zVh|gucMTHz5Qq)+%xNU{m26P^A1ZMdBmp((F^CN{=noQGAcuj05h|_?VnZEg24aKG zKWAWIu*zXz5Qee?K;qCS2nDgB>f=G|rC<-&Go*kxP>FmH8>*oM#D+E;YC&wMnjR$f zbPyY=eh!EYwRi&(`y>+kDH8h~m<sa~T+fq3k@6I8;qdJrbu2i9HjEy%@v>T~Wipz_0?uhHBmfVlRYP zupPvPT5te~eGSBhM)7?l_6sN*?EjA-4%CA0AU4z>?mPwtMkreZiLC`-HxPa5{M0r*<}DKY8xs3Jhz&J}HJ^cj5o(Y;5?cd_ z?TExq0ZXZ~(#qna^+%#D+TJJctc-#48XR>idr%Ht5c21_p+&1q=+rP&Pv$ zq6yE3#FhlHp`oab#MUVUmH$vf%|H^MOE4H17_32TsG;_S5DP%pq6CA)p$0{Q*ibb| zNbCv_8|uqOBz6}PdoqX(vJ2$@nII0-pe-Oa)IqyJY|u593=9nWL5_g3Pl3dtYHlF0 zAA{IX$9+U%e*>|h>RF2rA;ez{ zV~xZP1hJt$jzVH5Be8QpY^YsDAU4FDdWH!I4#Nf{_7x=ddk`DygKr=<=qg?Y28LfC zheFw`#R#7XBC(}GY|v#K3=9kkAU0IJCYTKhe+C8ydk_ce0}mv2AQC$Y#D*G_0AfQ8 zDnVjTLSpX)v7wGW0%C)%Sp#*`iWwM$q3p}`APK0Vhe+)ANbH{=_F_mh{R6R~n%PSj z7#N{!Sr8lQ0W~DHJ`&pk#DKn%o&nxlopHb!E5g4kd)>lqk=;2Z{qXe4$Dhz)gI7KjZsv=fOv35mS|#0DG6 zz_1aCy$gwb7{rE}c@o5~hZ=ep#DTJZBeA8+5UE-T#O{TJmRcDDgD{kB2oi?|sXY?g z7l|DXVuQ}$XJBB60kNTa>r;_9)gU(12Q5hKUL^K35F2XH91t67&{ib&1rQtRpz9!Z zKg7|uL5_y9pMk_-n?k-oIAB#w

`OBC(}G>}y~p3<@AN)F4eHwmpaq^?(NwI}nK- z1!6M_hz+`Ui-Cb*IfxB0h+zW~`xuA~_1JkN_6;QVLlFBIDEvW7 z5J4QMK_8IVY*k3{hs2gZVk?5!PzR}l*ids^k=Sua?0OIz>ftspXDTFEx~do$grV%I zNQxFCvDbmv(CT;(68j*C4K?&MhQNYUUNF`Jjf(3y}CrX!-vR#DOaMj>P7z zM)+O~i7k)B)&Q}gmg#}mP;)#%Y^Z|*KIPz%;VEdwp9J_r(rnt2Sw2AfmQz;F@7fl6Elv7wqD zAhExJ*w6&^ABoLTg9sr(5F6?UaS$77jwup56p38|V%I|z%>Z$r?9CuH*mVpHyFl!j z5TEUX3vFAecGSx9KFhccmBe4}hY^Z0nkl4m`pzu8B^}hXfiz#M6H>=5<~?| z{|Ta&O!tf}_h%B=K7CefxgTT7^p~;a{){`OTgH|9Gx6-0-W6Bw$CxnvW?Z>H0Ltna-J5?$4yM zdwNu2xgTT8^p%O_{)|ti{{&Gk(>;^Q{TY``pP5wd&&0BK`m3aJKgKoFEtAXrnHcs> z?@BKBW2~5dGa0N!Go{?0F<^Qnh*~oJB#8PkT{5-YpK;3c%+zv!CWC|1ccqs5G0vIJ znO5%4=rcVMMD3Wq5=7mY{u4y?O!rJL_h)=CeI|%{GyP>c$mV0ytuo5}7$c^4W|aFg zE|`83M6H>wnOW}7ByoItRc5&#qs8=-ndSbB9n&SV%KaHVre}hvIn#H7s1MUQv%!vw z1W|jYugnGo=9%fgvcbXTnN#l1*f4!2hqC5TFyZkb!|&v<8gCy2_KeiKCfnXZ{v z?$1~N>Dm`J)Ntn z+>i0e^vEi3vRDbCJf{ByQ8%W0R+sxTo|rxpL@k*95=2!@x2ypr#ZS|_YRdf>mrTD| zQ|`}LFY2V1MEOkTY$^9=w3!|Wq7F=738J=4{|TZzrhB%Q z`!lvop9!KYroU_jB~S6`R&C{eObim!yV}bA7-vks*;ek)xMsR$d$~X3ndy}v%4hmX z5cOiZWCu96WP+$A(|3X>hv}T1pkPv(9@Say$GBnoN)T5x)#+Yc;M6~} z3!Khgc7YUYOtWrGxe}bqL(-miytFs#MGBOlS_nld; z%(!@ZAxPw&J0pX|^h7;I;prP@mJ6_oc`!0~K#aLDvs{2lg?sv|ndNGXanl87m8&yO zm~J_%T%A=fkCCBZdf=ZF;pq#~xdj*(Oz(uqZk$!F#b#t+WN2zK{i3j@IIFptrGd%x zhjLu%OdN9C)n=DRiHLhTFff2`f@WZ0oTb3Pz_VD4fx$*$x_`c`M7^Op0|PS?JFh4M z1Isxz1_mZU(B<{ajBE-Z5d%gB1|}iUQdee1jy_J1Qq}|N3=Av|peq)|j6t(Gm2wOW zOp>5GeOa18OexTb15)Jv#|aY2T|-dMHm=ZS(sVacStfYFf(!p zE|g+mVA&?jz`!g5+G)yiZMyx2as{4~5)2H?x}a$cmbB^F8_E^5+W8q6Skyps(=4ES zYFIQt$EdKFC@?UvXlgTp3}ft~{Obw4v1W^Bc;An3l;**FSA2#rS^uzYXQu zs&8c&7+9PbJ3#6{SAVj&LfEEq3=Axuj59#u_0#<}mOC@%OrNx|T$#~h`nHYbarGjg zlSc$3Kqos3C~Gh~iXJTMrVUc5CU{kMQ zVqg#~WM*JcVAFMHW?&HN5oBOs(*rRXgrxWw7})edY!)HVP3vq1zRU~^96}`$3=C|B zqKpg-JVKx=CfJNb88sOg1cZV>8jSxlFffP+EeDxz0%A)Dfp*}tnSKGSvKGpkzGqXp zMAR}V1_n0sb4;K^3fXMBK~@*5Gcd5(g6ExtCde=_u-SpwEJE=h>+C_gIT%>}ffPB! zF*7i*^vN+Wusee~H!KfS85r2J!OZ{D^){C)8dQP~91{2fx-LXuk}@bbR6xmyfu)3> zfq}gXtn|7N0|WbJFmvPd`pxB{y4hk34D6RcBEoF!SMymI7=%_TGcd4UTLZdkQfR$2 z0|Wc@?aT}ej6wne(+_Sg7mF(tXJBBz#lgbBz#WK;+HYjaix2BAOG3$~Oi^Zrv|U||1{!oq7#P^O7@spUFo=0@F)*-m zGlHyPU=sj^2oK{nRt5$x5q1GaH#P3L6n{Vr5}q zOPYRSYq=w%^>nUn6~t`tz1;*h!O(>N6&dS1_s{yYzz#1AUQtp zCF(3orzdVJ7nYHiWMJShU^)ZpEOE<#(w!lg!_2@IGkwCgauLSt=}WhjTWS8|W?+{M)%w%&3=A9rU=>^n9AQk8I2ahX zud6dKaD+2~(ij8xdu0X&jtC|rP{G0tc19%FW)5z4J_ZJkD6n2`?(<9x3>?v54i9&v z90LPK44A{q-5|}tz!A&D#mKfbSq9Vvw@n9!OaO;8Gm&jDW#K0iQ z?J@o6_Hwm)Wf2Ajj#RKgvfTb4ucd)Ga@^_s3=ACUV2(TkJ1Ao<;(*?-$;iMK%*nvO zk;$}!oq>TXgCn1bjgx_ay9nfy0w$0;2JUW<>LRe!3f#t^7%2mLSczMNk%57uoT-D2 zfuUZ7+Z5#b3a~w?+$TZCR)RTc3~ZpI1vqM$)^RW}a4~T-FqwfY0VM{GMy6WO@vYn! zLB4GQt7l|jGXVurGm{V}0|Q%Mq?liT`rjPf>p@b| z%mPdd3_RSQK^z(Ib-x1Kpo641dP2zxoNdfsGPdB*DPI;SLU5u}Dz9^8kBW>?$ZM zJi+c33k6x=1$G7l+gDIJ^Jf0d#lXO}3FPbm=16V^2Hq5I1_nM5!N4iO0DKp8}p^$JY#fjjpAWo;NZ>y1zkNWsAS?~U~>am(ZE{7Q_sM_#mUjk%FYWjw*}eUR%CPA zkj-s}n9IPX4GQ}X){{I83|tW$-K>+~CiOr~0vBk#te|q0jawR&UHe!;IiHhTgR!20 zfuo-lRJ8bT_XsdBa7+L@F@XCFD7GeoEeYgq1V!T{FeixnG#dj0$7Ha>g1Om1F)#(p z31MJc2g;FCSwZ*Yad~mfU_B3a%S>dq%tE-Oo`GXF#4!wPpFw8LVV%dzz`zy2F`reE z4;Cg1kaaIa=w{$p1kudx%>gQFARb|0(*{)@OIUC7GBB_$2L=2(NDQ)bY-A0Eo4SeB z2;_eT?$@BAd^4*ms4c_5RtD0%h1HOcfq_erV>@dfNCUXY+rbJh@_3RNICiqGU<4gF zT*Sb!3(OQ`V7m({A9k}Qf;4(@>|+Jp!3Rkz`;py$0NMTZ2O%C{U<2K`$8m^t7D%@@ z$1zq>ewgo%BkMkatotNHGq`r_6>idbs7auc4LB}< zV!EDzje+ejC_P_fRpe)25RKrt%zBxhfkCVX6dPB-30^D$6oyy9iB#;n8Uq8zHE=Q$ z%K+6j*TE4bCIiZ&H^5OYHU(7Y-2?}<7z3#Gy#)?Mv4x-%b{iZpVpgDZdnXv|Pcg8A z?t)#)z?K1uj(e&XRLw( z3=F(#0@E+{lnB?mfy$wGtVSR)9|7TD2C79RAeK0SEs^3@ z1C^*wV2(5cTR$jxoY_Ft2bTng8{1xx3zWtPTKc7J`@*2<8Yguz{`$;s|0p zDagRUCBYHO7AVBPzzudsSUtoc5TnAuMnT;X0oKjN{RC9xM}lo+XJC5;$}~}I!a@uT zT;d!tY<(a{Wfo;KaKwU@FmM;Lf|_+~8cd*&dIO51cs5WKAjrUW8FmO)-nV1buCk)(^K^ZFtEWyIS$?`ymfr0HSD6QtQy#d)T%E6J( zmLUww$_3!W3dypC;J|@o!7_0A5(9MyILg^T-2sX0)Jg`9N;WajQOs=1L3yi+O-Y!6 zf$ayVtx?a`APlWTX9_bg@PV@ps8z=Y;xcfufb8U|H{fVxJ1@+@z>`_Tz|jT?LmqH| zwu3nWJSiF33>+O`jsgSQG*BJW#Wr77 z+-E?pTf%lggn>bVyBg$-Wo*Yp7#L(2I9ckmxEUBYS>}Ps6JSz;2P6V2i#S>C^MlwW z!XT1Egn@xg5)_*&*t9@w&{cFC`yt7c50tb{g4tYL99P*u7e(^qCRQ+TTmvU+2Ad|twdJPE%2F_-%93MA>G6Mr=3z);t zz&0IZbSvXbP=6C-0k|UxnulX#;A8=HWZ43w7#KJu!EIJH&=r!Lp3IeE3=HC+0i4>fGcX7o1dR#^a4;}1FbXJhf*i3! z8Z>^RrVJVyW7#Cjz`%6`N!v}(EtmqKObiSR0`oaQx}lsk3eQH2(_^>FmOEvg^Mu@1ItWi1_rJtAQL4|FmbUm7DzKNaNh$p zz1YBP2JYpcqKBO^7&P$0T`=AHc)4Vzt{4LY7Z)Qa5Vg4_L0uniMo_rxaKBOm^@G41 zUG9S*4lg69sMO;Q2ARXh2r4S|!SxdtKUkS5w>hX+DZmH{3^Q&Ckar;?4CdVJ)At@P zm(;M)0F6N~f)b$>H|UyEE>Ungu>scuTw;u%!4zBW%IW`(mm5oisxmHVMo_($&+Q5F ztqkJ+@9(T3|tCe&VBA((;H5dtLw}Ixm$(tHVXrT zJfl>rGy?;dDwr3~CtwmK z3aIVOrOWt1STmfRR#twbFkx6n4}s&5n%yVS;8ds z5#%vTFt3zJDg(r`0`tn4q~gUH7`Uv#ymBU~9iYO6%LdG?V3N8t{m0327gDLFEKXnKbAmT<(m6(hLkj??L^lOi)BK2+dVuVBpRI zB~%unr!ou-+}R){973$1ahn{FxCR3|C{14k72u$2j-jeHGBi7D!M)Br&akfxDwwlz~A=q!`5R>=R{R z5EjY;weY$@DOp5lfieRFcMr&BQK1?&1_th45L-;>DJug5cOR&55*OMl&%nUl4=P3F zgfu|x384HTFT@V=;6zYnQV>!EIcD-p(8*~ILM$L3P60XCQAh~XQlAbov|fl?m4ShK z28i7t6bq`mW`exiB9sDZYs~`P|GPox_4I@@<>K|AT**BTr1Yv#2FSSipn<4skU+8o zwHanJFfiCMuz)Vp=3a0|nt_2OL=;pV`pYsf@W#tBFhJVGpoTF6iz#TpZ&?;dstP0p z8ZrUPGYH#ouY4=Zz##Mq6tt^Ap~4`vPeO`;fqOM5e=`cjf#Plrh|MmfIi2rpxoka1 zgMd&O$U7T8%Q7&Ch!ikzZv+*=PC_GW2k zW?4ftfo%arhIYlZ%I&g>jP{0|PgxL&VJrW;1Ymh%+#7 zvoV5_9}BlA$Sv&PWX-{y2}(vBU=Ak(Ckx2)Z0A4@mNJ3+6C#+fDaBSFTup1T=)+3rZg1VDlvJFmlT=)+vCT339ePSd@VqbV56~ z3L_|PS-7J>MYlRw)g5lo<&xYQj4cWb3=g<_K((?axCnnDwGd>v4r8Ji0|N`A)PGQB z(gl|%9E?(+>nXYQ80$gB3lF2zUr=D^Gj=I3FbFV8DT0!^5!hxCMyVg5iqDwQLymz# zlu>Fv$Xlk2pwWB@Mkz^T0f=sbzIst0yI)E)qXOt>qVPN2PWZWUgz>vWx#Q;iRPK?2F z3=AcVQi7m#=nRgO3PveV-;LV^ELX!QwG|Zo?u-)@7#M09rR>xh7`VL{GvycLAaHsS`XS70u9gdgnVISVBnWkpWbkxT+);i)Rc|@>EmIP4O3@e z;E4p;!^bH53^Xef1xmzfjIzc&3=BNcAdWhtY}WL1Agw9_3=BN+pkhdiQI?&Bfq^F- zq(GZd_M0dJ15Yl9qr)gWTb6-=rvTJJ)@78nn=W&)T&;d79|HqV2}pr8qihui0|QT~ z3=;!`4I`v%;Q_TaL1haQ2Z&^6U|G(~z`#=p3K5wKMxK^xWd;VJ4~h&7Jgp!mgHWs* z0|QT6BdCQVGy@cj9iWsdAaoMs{Vq^JAR?p;@kYxgOo)?3}B^YHvgK9iW zLD40{D7#Obfq`cwNJfEC7PJ762V4ZIFv{Kq=~y@a=EM>sNUuI14_1PLZ(U#3_O29Yz-j} zP6h^^e;~G&&<14&2A=;Qwhnh7D6KGn8y|YyjnjW$E?20RQ(<5*;f?{RVg)xNO}WKD zNs$X&d{}e)f&9$_F7j+ZCv`LM@PZ3N2kt!}89uO#3-@VITb&;)WugGT6sX4M(E{@X`K7*q5~((rC&Vvx z3#3v9Y>Y5J11Ae8A+Uq)=wJhl+=23`JOdjGD6<X5Qw0n9d0 z2DUdKUvFfT1GR)Rc(yX;fXXk>SOCv9a2u9^`wl1ywu3nW+*Q&H3_Lr)90l%sAkHo@ z$AJ3?$W^<+903RL*cH!SaN9J1+j4sLwQ@-f(9jsq0dQEvfQOEF4uUzc+?PRdbO_9e z<90t&Hv;DC}~U}NNFVBmScSOJ;|e+n}0HCT_N1tZT#Ms6(z z2JQ`@4DkufhIHe2J~M)@>}BB&1=;b15!Bw|;GPc35MROm<>B5dRL{V`^Nmql3pBC; zuCTs?)1nMFxR&|>=E#AEuz7xh-K+qf9p(AO2rBs0xMztmF!20ltYKte(Bv)$RVIJH z4zuLe0EHSKc(&1syA@Q13xH=EZMXwL@hQjzs=R8aJKZRkW;{PV?nb#JW7PDD8|7+@ zM$_ltD3`1UO)T)3Gl5FP1>pGy9t$Q=iMWtE7*vB1hsuh^Cn41-3k3HDZ zCEQOyY0LpUiMR|r@51Nuz`zp*Hr#|!N&ytzkV#@wP#FzM`kX96Y7CG` zTXijHGlGeM?Et70i(!%hb!V~2%wQ7LW?jdGG{h8oHV$PfMRMcn4`sg4^-LA19Nn^Pl6g2^T8ZFZg7dSkZHOW z1A_r~2*?+UKu)Y@Fl1l{nX0Od@MH(5Kv~SRSc`#yi-TtwQz*zeMk#__vFR7x!^OhUa#}hA&lhl*F>n`x zN{pZUV3{zfIUv)2F&&)FcDr1uek&*;{9{_n$-v;oB9#N;{bxF+$H3shB4rDTa2Dn> zdJGIcEK;7JdWeafAr)N@iVjg`P@g%BLkiTN<`Dx+#&Jl22GV)N!GY4A;An9Jxk({Dh4HH8L-MC4ypejIax5TghR>(l;4xul(q~}UA}*B)ig{CJP!nc{xRe{nX=coz7Qqd1 zsS1!rb1?6YxYPnrTC)K29*9d-P0zklu2~-pa+3`+sOo<%E+q%5ux!D+7vfUuK=Et` z=Die``Uz?lKxUR-iA#YKt}ED|uf?UnDc6k|lycvQgH|Ln@VGOlYcnwX5tnKKB_`LmqEpqCo`y-@=si!5 zq0hjeAt5CTN*#X85+I(G)MHSN_h$x`lrNN}W`MG50JDZZ1H&6-DNy&6CkSle2W2TY zkYj?GLB-oQWvPb(`3wv^p-2fbF#1sFfi1EyES(D&>YRez{Un@E+#P-Ycnv&ZRBNOU^E1+ln32= z#5iZ6J_CdNL^TG6jrt4>papsiyX+YlI`kPB6d9wKiWn3bqZthp8Dp5aPB1Yjfy%hU z_6!W51#1lF?ZJu|EucLqkO>^K8FCpII2cqw=Bn;xVqjnl12r%~7D|D}O6T0yXJAlE zXGNA^Q2n9Gz`&RZN~R!%pc~T|=M)(*FsOlq7&Ae`o1lA4m4rYSR@yT#D1e58pV~7p z*iCP^U#`i03*;uy!J|*@r!$%+i%mauznnkGUWkE#u?f6V8I&Yowu5wmY-gH& zQ6*Vydf@b3PXa&ea zpaa_>9$JO)&}x{6K!<;vFk)bUcnIvjvv4lLf1HjC3=AMQ8BAAHOBS16|FB$!734wB z=?fl~i>QNqlw<^QVicpfA|uGd3`(GlV_*+~&Rhd&UIfwn@nN}4y&%*>ZZHpl6Di0k z;IzxnpaSv-m{64yV_;ys2#R@7VweU_HT#WWzPt$Xr57Uu1H_k?!M+saVqjpr0`;X9 zI1;ad44BKvz@Q|>z#zZ?b{S|r6v$Kt(VlU`(N|Q=Ojhq}%}F zV$dmcAfLyWLR`G%2{f=kcPYaP2XJ6@!tw>kSs*QIpjud-mJ2IuI503AFa>!MRGu&> zfsWw-2MOr5ERgE&P}TlV%Z2&CGCYisx)rBsRtHHpi@;q zS~i$Z7vxG7oA$h18XQPR%t2m+1QO^{8E{a5R-Sz5C*7oKMFE1FwO%z z*99EO?$b42mP?01UCO|~xCj=%CfcCdZ!x30H3I`^g)rFRpbKds4mUXkDqlB)JKr~$ z8ITHm(3V?JEF?@nsFy4@ef`UF8CH;UDyLs~SuO%ew6Kz5Cqxa$t8y8L#5-sxe1J%J zyeb!F18L^8o}T!sTo_!iYE7?vRW8HC>M(u!t8&G9kek49qQIcyYt6u5$|S+S!1x60 zGEgA{x~7+L4zmpdgC1zQpYaKJ5S59Afk8i039J%S7BU9wcgQm^Fg^v#GKT0&vVnPE zxlnxvP{2K71ewAZW&$oWUxIB==44@DPzK$Q>@eNob-6*}e>DaM#vkAyRsjd`D_c;C z5Cw~Z%3~*x%_{}Ke6Z=k2H;Bd7b7SZz`^{>7M`s@CWF%lEL+W(e(`m=kvgcT+h_wy z8K6u6N~2~BN}vbcZ+PGT>|jy1EvU(HN9KXU%{WgDNACVpm&u zwvmQpSkUFPAekQ9>5az8V$-j_DOZBX2tiAo%eIizD*d)x85AQ9Z_7pNLCy!qhy;TQ z$oHl-+zbqiDxh8zC_)%Mfvc%ldjLwp<3{R#58!m9W2cAVb*u3Qo1p>^-drRqVpf<2_ppaOEXnK)<)`UF#}Jp%*Ve=tz7V`N}3 zla^p$U^&S&7bFh$Dg#*DydAV=HHr~55oo>*)LYGA1~ob@B!w9mK-jWLiGcxxxh^nT zwF@&afH1GU6=-IzPt=Tofz`)qh71D(2(u(CS2-YHZOsXDz%vs!BUBl8L=M$_quTGbLvrl!*$YFA4#nm{PS z>4xh{g;^|34b7(~-bxi`HZ?Sy&X_K6Y;wR~x#@LwiUQlaEGv3gGYt(H;^Wgw^OED^ zRY0m4;^W;y{hUKQ{rw;!7U&`-M(84@m?DpJiXcr_ER~{q4MTamK~d z4`x+ZtG?l2U|`gS#LG`4HajOmTxPmrc7?dAIg*ew5<3rxT|GTEyF#3C+H_O-H09|$ z3(|R}FUhVjkYoWhu%Om}8(UDe{Pefk70RA|NYc?r>`Wwf9TK}6i9G{}y=;19PK7e# z)#-*z0pj%^kYrdv*$rx`AQD>^iLHsmHbr7PA+i0C*x5+z`AF=O5H@Irmx192gaZy? zNghO?IwP?`yN6(r5RD|BK0P$ILSJ$*lF$Yu_P*(Jb1Rg2-y#Y9nto6-Kz#a>+=>uM zQ2!ogYAdMXf_i`Q^uW9damlSnLWhvp7p6DnRVdg0M-t-UL%18XNeE`D8j`p*659ib z9fritMq>9Pv6mpRH$vE;o*DzgJ_rXKcxR@Y=2s|t{zekw;77Pi42i9c#I`_UyCJco zr%zN)6R$5u5~@dHcO$WFk;Hc+v5zCMuOP7>AhFp%m7O*Np2Ma2cCHX=1Gc?XY>vLhw)|&peph8(S4N1Bf ziQS0Ao;LmLvUG974M;-!kl1gL*uRk29Mc;ME5sSir~9g=iPr~#T18NIlpwJik=Xr6 z>?KI-4M^-gNbD0x>?=s@he+&i5H=(wF@ri-P)CSQ|Eij%KmCNBE{{=u2pbZ+mJkj&c4Lv)nMmwX zBz7YbyBCQ)6N$YPiMFFq}qWKSW~xlARv6 zJX(xVa(eIbXmMUcIfSe1rZeiNiA#nc3B@C^v!*Ysu27bofh4pPiM@0B-RcTu#uw8W zYbwNfnL+(yXh`u-SFNeAu8%|#N<(6oAhDZ}*b|W0^N`qUkl4GB*e8(K*O1sxAZ$pB z;uC}ePC5(<2)~2Yoxnm<21#6NdTc|!c)c5vPzVw`35i{R#9oNRUW>%Oh{V2&#D0my z{))tAR0KN_w561Rfp_}G+KT=4cOYV5FT6xz^MVE_ph2#P#MVV(TOzStk=TJq>{ui= zc+dlCW+_A*k_8(f9IzvLk=Qel*q~iRurS?-B)%7keG-X%6^RX6um{uo7D@c4()7Ig zin#hjWpKcN?axDE&p=|YMq+PAVjn?bUq@m;Mq-2ZKEv$)jU>*l0=5@&<%tM{19pTw z65AMwZI8tEMq-B}v6GS5`AF>Q=^Gm=PS=B$<-y#N0vbbvMo1A7y8(&ahs2(P#9oEO z-hsqEhQz*t#C`-}LlPhRbY9am@#zvx6+FDApkXVhBb=riHdQDymQBw!O%rEaI6b$i z!kY2>^tnwH;?oZ_RTxMHse?ld97ypq6_aL!nOkder5nTTp zNr*!mp-l~mZH>hCKw`%ru``g^-AL>iNbF@u>@5&BBv&1RaKK@80f~JNiTwtN{R@fB zp@VR=7!q3riEV_$c0gkL=^#~XF-Q_wNbCwEb{i6V3KDw*5_=yK`wSBM783gfj1BVt zHy8(WREaLaH$q5k1thi}659re?S;gSKw_sMu}hHHO}Y#Wy08p30ZC#W5_=62d)M?t z>ooDuYe+&*kl3G)*bI6IfAAr(WsulfNNkJgXRXu3>qC%)l91R1NbEW!b`KJJ77}{} z65C!M;S_Hqb|8q&3Qltjq52FA!mQBSClWvs&|H}bVnY>mBC#hSvA2WRQ1u5vY)Hw$ za1>-Hlzjmt4pnmt#8!t``~bv;ioenarAE*WAkc+eAk9$rPb5Xm1`G_0P|X}5HdKuu z5?dX_W`|f{fW)>$V%vk*P`w^7HYhblfjCgj$w=%RBz7@~4Rv)bhz;66#lXPOXu!ZA z3}yF##Gz`Yf!I(-&jzuf;>(cOTMQT&!eFU!A4meUwuXU$;V_5|HS`P;`w@r@b?9p( z_7^1fUl3b)`n#?Qx#>B{^%C`Ah71ghP)+ej>g!z~wl*|@9ffefx-TQK?}FH%#rzBm439u;s6lT)Y|wfI z&=rUvHq^3TNNfQkgvTV2*h)xjZ6gN;21cj_h9C*3L0(AgWF&SD61xe+W}j}C@2Ff4 zb<1Lq5Y&jvAU4#!cR_4Eu=f}q8Zj^kL)mXY;!ri;Kx}B>{06b1;%vr<+$w^^mIJY& z>g$z39H^l>NNgt%8ydUbNbC?Kb`*#W)mx0ju0di?0qbs8WE zsAfkbb`%o37>V5pVnZD<0mK%7ICP2$1A{P>Js%_vRkI4jhB|Z?j1BVteh>$$=qwWZ zCKCGvhz&LLBNCh46yY-gB(@|HTMfj9>eWYLyPARyDTVsp49$4b?jjiMv7zE?kl4GC*hfKZ&|)nH28L50wji`9yA0ugZF>n~Lp}2eiTxXi&0@~Lzz8)+ z5X6Q$P6~-_0AfSUu|#4!A+f#9L74z*Py|QZK@!5#@42LD)dzssP(`sIHdIX+5_=jFdn1Sqb;J%3 z8#JTOz`(G_l7T@O%03PfhpM>*VnaQ49mIx;KZdYD4%DDWNbJ{0?2jNeR5O<~0|O(Jt&PM^ z2C<=`k_TdoLqe;_nt?$W%I*M(Lqn_A8dN?*HOvM{K-nvi*xQlVN0HbUKy0W%S3zv3 z1za|WC=&#+B_NIvwP9cohO!kv;t;#)8MHwhs6hrGHbjEK4vFoB#0~+mLCcI77#Jc! zY^b40NbCv_8ycdGNbD{o_GA!S78L#r3=A_t9H>E?kl4GC*cU-;sG+xz*pHFeZ$NCQ z<354dP&3(V85kI$YTcdp#0+HxhflJ<`O>ILGJWH&3V&Xal?)6O3=9lW44{#0L7f2U=^DE$G#GoP2kx!_ojAM@L>-v^5ky%` zcid9}I#7Dzo(g{^mbKF#?WyqNeACM?5$v#9<#S%4&#>TKlfJn zGjXh+?zOL?j7ewx^h5h9{8(i+Ffc5ce(_Jb@bsK-MFP_;_E%^y9+;lEzrvp}W%@=C zHD@~GfeL?CnQaUVJktgLr3+8bI8b51q_K1Qq5~CvyfS+j7%Uhe4mY0u&?P~7y2QZ> z4aSh^jt471XDv?zQ6bYG9<13p<9EgXDhQx>w+luTbc|EOg^BaX+%KBFf%z#zbIU#z;jg&bcS*X z0|Nt-`SicSRSE`9p!1j1rhr7MK&PQ;Yy~lYf(~@no9E>jSUFX|$0`?sRxQ7mWME)%WdyV5 ztAdYJ1|4b0I&u1Qkt%1#UDLHitCSh_ru&Olc?yYwHgmBsv#{=w1)mPBqcDBfL0u^| z&}burfCgwFTHrk>gar2UgO2NI(*zy7lOYW{c!w!?`YX{YDRFl-1_m}~kdv5-^%xk~ zvcb&C>C$3ViuFDkpc8y5Btf0RE83tFd^UqZj)6%ZbQn_?Sg9fC1mw+NCTJLrZ3mb+ zfrWvA?J$_>1UfGH5{N0t#ϐj|ssXy@Fum!R{3gd&s}7}&0V0j*va0fq{YT{ynh%onj0OY!9r!XBD3Z zne~tfoKXH4Ffgz^0%;ee({@`fkCi??R5$G*yHK3;#JDL9l8t* zY#)5VXB8Jt?-j3-5IF$y*f(Vs1_nV5wx2s7ig$`vDf7jGoc|ZBn1LyO`YZ7&{}6Xj zh;T51yeAsP%)r3L$@qbpfkE^T=&&;`Mimfy3h0zaZbp#346HY#85r1j7(pvzIYrn6 z7@I+-7=u;-un97P0*is`{`6jnDoOr>iVO^FBH$#!!oYfM`c{c5$9f^qamk4nSQ!|= z$>{+rG&wmiFd2akY;FP>!8BWdfq}jC8!H0?FC!ZR10P5k1Je~P1_t&X9?<#5G9Xcq zQa;co3I?W6pd*_nfezm0WMkK7@@8XT;EIxGU|=_3+6r0{%~izAz`$KpnU=9!0VbIyzF<=fa7iiBcdo0r%1_lN`E`3D?2KG3xH3D2E znxM0@;=wMG;PL`FFOew{bo4QopxpG$QdO$;`y?3{*i*qK$#N-xyp{&$$Z;u&Ffg#E zgE{gHY!4Y281Az}V}p@_H5PQhY9`ZH(0Lsh?D6@x4Rr6u-8rd^;J0xoZm<|eRuMh4cYObiU{%}o9r3=FKdbr~4g7c+rQVCJ38 z!N9-=Ccw#og9YS5P7d}nO!b#QMuL`kv!4Z0Hm_f;aH3oG2H#ajVJ~<`W#hIf)$3cOP?PZr>z6Toc=i&sZmSi>uoqf!e z20B4PiuoewWGoIYO^}o{^H0!TU#?mZM}`^XOaU&?z7cjgu(2XsFF>&;&kQ;mSB!ym zDk!EDnZI!`FmUp)t1vHx+o+0cqZ-skut^$VlQIl}%!37HSdUhu;kCTBl43sIHncs0TFo;O7yE22;8jFIBaswMBIuCUAygN8> zML{cH*ge4B7Oew?g(ukEqWK^Tyui+2U=0H$2XAHzE(QkH2#~V_n5S_uFz_zqVqo9{ z5eys>EFf!Gr9jD3m~}H31A`bSMsIUXpKwZ7$$A0kAR1ZL=P+^53T8e~9ulIpkt9i99GbtANCMdFdKBN1$!QZJso6UIhf7K#a_kw3v{yDdyprqSwTe!0~e?= zVy|KC=4N1E;{w%2?6s_mL3xr3R2{L`u}%jaxX1qQ4 z3Cs!NIs`iWe=^u%!CV_b;WGuy31MK>*JEH{pUN5la*G%H3|7!NHW0VWM0U$8gj?zv z*k?l=!@&9yR1(f%y$#YGz&@Wf40PNY*e45+buUEdW?)|g(ad!TRGKV?c!Ytq5me1A zVU^%zU|?MgO3v#bG04uo5qzF6#7&!6r9u8@;93GYz+f|L5~zM;@m}%<09xkCg*- zE-~2s`;py$0NMTZ2O%C{VD$s}{t)YRkhR|I$5=rZPC(pw99j1XWZfqrnz_KPI|X)~ z7X#~4Q2lY5RfLa$fs>v69BUKY9p|AYfleW2zW|D9(6Pv@-JtsoF0#h)F))ZkuwP~s z0G*EvYLT#C0VjA-O;8wK1t(I`9(~ZI5#VGd+NTY=Gy)t^qNbocd;=Wiq8y+^b`u=b zqB}u>dkY+jq6a`J>^3-HM7cr5$(?$zKSjX~x(jwG1M4MFINk#vq|E99GW9X52I!z> zQ0BDZXJFu~2jy=Ni-Cg$fXb_Ptoa}X zop1%RObqo5d^t=E41C~-W!(x=_7z;}^DY1>g9yuLGBB`nfLlteb)ZT`7{X2j)fEz8 zHYXdqCYucCU>R_Epv49%4;Ucjfi_qLBcwdgVcWsaz`(>cnUjHmU6-vM`4A4A_o<&rxMJVM_y90&2msn}W?{-~u&a*&+P`MlMhr zmff5URL(GQff}*w7GMrD18Xs;1hiz+5MW^7lwr4J+Y8zO&kZ^xnca>Jl$;s3j6tQS zJ)0-!kYuhWpuFwC2C8l)AeK0SZIt3F2Pty`bEFwq7lDGunXL$9t^~Uq+b@s{vp`wU z9o(K_-~ydM%<$5l)d67LLJ*?@!5m=*Rx^-0g4oyu85lSv*hAU+Kqoqa-4OaDTNiO52)Tq z0|$ZV0#M#c2YZ5nRT0!c&tSU_at{Z47Mm~VsL>-JBeTKjgn=sp6uCKI2^Izp7Lc8+ z%Rp&0mrYZMfkA|WJ)dnU$RXf-T>wt2qJ7%+3=Hgr;Lw3&$TD#H0(U#u%h^EP4sp<~ zN%l%M(CMZOtnr}Qriv|Ih=GB%LV|&Ty`F8a5VSVGCd9zNw*ZuFz}XMPW#C`|S;}d^ z-pa-UI_xg9h=IKg5`^5K@T_NV2lE8DL5C!>cYrwx46LU?HBJ}X9gx!v*n8M4L8m1L zf-*)g*dX!LA_n$8uxbWYA5d)dvq=auFtC0E<*O-dfx-+7yosPwn?V_j55!{NU;&xJ zslYy)?WQmT0~hEtfqM2iU=9Pq%6*a2F>p@GYIm|$DD96CTvK8c77LcQu6hJ4l zn}Y-dc{pr}Kz8dHfNskH73T~>-O8ZLazJbrAp?+o_8_-&FfiQ$DROWXWnf^E1)Z;K z3^JRkPYra=Gnjcol!1XW6wF-AF@3v66>t4>Q3eKZ9m~lM>syO3FmQ5!IgDJvpw1a5 zBgg_KE>L%ylMB|})(~f4;N)gpDaydW!2&XdQ-HIAaX#p9VLQ+npp{@F7`S*sv77l=^_=-S<*k%KxavB zVq;(sWMB$W1f3;~i=D^e*Ws!Mna2a>=yHKp3v%%?f~qw=t_+Yle2k!K zO&{Er;Nk}>Gv(R`>VFC_f}+HX%LEkWkWnXda5mu*0;f+4a37yb7{t+Lu;k(}1Rrt@ z$|qJ_vqA0=1xYd3fa`HCF-FiRoGsV4>05NFjQv4P5iV&)P`f0b3v}Tfmki@dP*1MiB>e?zGzp5}wuz=3J zmeo@NpL-4B#WTu+!&nVG)Ha_{_RRDS-6~D~9A)sa*P!vmAST(?=?8SHq*XwDBQ9M= z&_H7-lk8qS1_mxYaKMBy$r^!_}FVu;g`T9yLoz)UX`@vA&?g=!AeS*WR*cYD=@E&NmdASjJP$J zSI#86MUH`i%LdG=V3Mt#zD}>oMHbY6<8lTUBx{&t8$qRx3nQp)w~k46`gDH%Dora; zbCJsf?D&05vPPg(wU83|!t|-a#f=F0tuF`c)eBTO}A6 zSTC_KFmMGjPLTnXa+*qU^!4i7u4a-crU}iAY=$`Q-M+g zgV0*g>2O(~#Lptc2s$n}8>ECos2p?#Zw^RY12R(iA2fmhD%0c`n8G+2G#R*ax5+Rt z2;ShX4+ou{47xUpy8&Y8GSIoWjUYCYQ2ul$gDUI#sXCy8ut7os!jOZoCxdDZVaP$) z^S}pTcY@9z?gr%m5urz*1KoN+#fhj8=$J9?UJzSMXe#J9-agO}uDDQ>I_MzmT2TfD zIiZK36D22r@|C>M2GAMT6G53!L1-SxDU(lwN>c}+1E7?th4BT@-hHep3=VV~uo(r<Hvfr%A#p7N4fP?6RPI@2Fi zU4pwq3`{zpQ_Bm|3KUKZLKcdkld(Ys1*1>} zC@$B4*z7{CptxKMaw4w~BL~CuUxrou^&s5>LhnJo-JmGXz#t+FIwu=sxr9)@Jm{Qk zkpE;DI9Q56H8%^$ZA?EjLFZ(H+#<-qy*(S`fJdNk*#U}72BDvzhR{wBn@I??YlwRn zh|MCT1d8z8AT}EVlf4831NYu~BY6e}CeXor+-E=m#&j2StoLOwGZz$Rx4_H{P!#_J z>Er~Rll=g6oc$S46PA?`#Ae{S1F9F;7(t1Xg-Z|Q7D(%WgX=uVQb_B7lYxT;6cntW z%AcE)agjWO8UrWjoNNP7VE}60a6`&o2ChhuHePVu8jPD185kaLC4=0o z39cEQ$fkhOk`5!NnZUv*`x10SxGp280ODYjeGJm2$5;>I@-WIC0tJRXBk15(0Y=&7 zdZ0V!z&498%5DHv>c)&^@}P6FWm7=8!ITlyAd_H})d3|oGsYfy&^g(%;UEhw8P(-M z=VZ$shMbcPN*pPSvb#YiYTJQ5pUNn^2xN*qqfNa6=$vfXI8bhI09%;OD9Zvmw%w8O znLOy6Y*{IgOPv@S{)&A zIoZ?YLFZ)4UI3*=Z${Am;aiLh94z&qJ49GyK<8w0up9@?5rN|C9H=P{%1E3HtaCta z@?rDr~=mdeDy@D--afk7U0PPPi@gyLAx*?9h-^u!g$j0&J7@;s3sd-xa?+(9RdM1c~q8l!?L=pfW+5J#O+L3a8Y(<(_bbI<{%@t}a$ zVpM1WophKEQlQPKun%;8U@nNG!>9ln3g;;RjfCqmDzM8<|7}{O%IGp((X2|Y-U`&& z0fht;cp8$Ofk^~({9+}@>++xju~(`vFbHvJfeyq5F&Ts&gATTA1KmK#B4h_TL$Cvs zBn5<;K>q9k<#-XHC!kX~yFub6LWZCQS1(B1LdXwvm}4JEJVMA0bV6VK1dv3G&_@tw zB1ob}=n&|9&&eS11|dO^hAANN1wx>kwRon1#Fq$hYl0R8fW(goDS=MXoCOj;A@mM3 zD=-@*{z3@kM4ow|2@BW>*&y*RLeoKZEdr_kp-?XkIuLd-NJ4^90W`qMvlJ9lGK>n1 zpaX|jf@BmJ6+kD<@PNxg6-EUSPzqQd3O*uR0o0e}*$C;Du9|AJo`aI$i<8bppFmE0Z_cvmw*!KYta1Neia4=5C+Es69WeeXsV70 zbU6jjVOM1a20JmS zxX`oVas%}=dBMe@1J_lM3?Ep=g)0t}Ci%fK9$c}Y<0=KfGCo|+AXf;2OTz#zP^HTw z0xmT}xOhN$U6c{zw-PQ;_01y&c1Q&msQ%^=2XX2ds<_-h{+3`=QDvm#_9@AD zmko4MwrmUNJWnY`&@>x6zig@;_@r!*&$#$yYe1)a%7P4G;Nh1&4f3cQxK!lhmj&&9 z>n zHZuCCGca(1&dr_$I*=MPKE$()5tJ<$xZZ#wWILE6zy;bD%d-Q_QQ&F^oq)Ov%rW5l z4RYgdFsI%DJe)rHi8>8rpU7&%!vYbKX?v+11knRz{qnD%!%cS z1x4Z^Fei?y2{Zt77|e<10*x#390hwhfomx!XCDJ|QW#jjfr92ZWBo0VZ$QUu8)Pwk(5N8KUB)&1^$ZN+To*tAdyf$mo)QeKmq6A&U|gob zz`z<0GVV24lMMKHZA)zi2Ch0#j{C$2Vl!}oI+Z-18SOz`Yc4U6C0`gp%`^_KZJ=EA z73^UiE)`Hs^o`L~8#E*auI9dj0yd37h6`M|{Q&V8X zpv#4LelwgOk2V1y=YpVeR1CIlEj(Qn*UZ2MiJg>i;s}*Fs6Ijm*E@@D(x`R0@ zxpYAZ)r-ka6LhpTH}q(2PzqQhn-0nYeoUaos}7^A5~$D*0~>C_D7z9Ah>%4Hrl7JN zlshdT362>rjX@Ul-c+#16f+7wyug8@)0u0|^lf%kiuH-0QIIPjJ&+{t%opl%(xOzZM ziJ43wHUn1(D3#A*0*yJ!adCkX`D}1FX>etM()L_1M~mwUs2-jN=IC%qf()1s=IC*O z%czA+N3|Ik47jSa85npLft*;+V8{R-$qWXKi-SrdCI(h-P&K-k=^|)^i-TtwQ!~gp zd7#6nmxI|1Tz;VXdj;5Apb>A--DIqw?b|#nnc{UA7+9S_k#__vF9SYW`w6JU2R&LF z6lM%ulR@27}InW@Y9w03EF@D{lxsS{qae{$Y`Q4GJc9@Z9@f7THRWnLNx# zRX}Hw%GQDo=oVrIH7YCEWIaGRS_HgyAcRA&3 zh=UDH;E?qMwM!(JL4%4(9I|ggi9-ggvWP>r7$heP=9O^BZUFI=nL&kq1&18;Xl+gr z28JGS*$z-GZp18Q06JP*wn7?mv^HpqE;JH%ykKu$Ab1|`cI;?)F1repm^{EL|BB0s zf^xSfGpKphNQB1M#F}w}MpqGlNRT7s|4FpmHgI8MK(meL4C+@gsL1XH6IUW^RJy0Tx0rPlOWPL$4#DY}{sK~D2VyI`}NnnmK z0H3tY25Pv2QZckJ;b7?kU0Dsvd7$(Q6=mzxVPF6y1sGq;fPn#o!F*8hWCB{$zyd0j z*gz!}D2%{z>!0T3Fz`*c{|vNEw}OFB0mNVsu4Ld-eCA}pz@Q*p#lWWo5_Di-D`jF}_+|iIWW~zo3GFK^;^^tgc{Scx5G|B80TDsyCRqa;tDNseFpG0 zR>+~Qpfj@>z?Op+&Vo$e1~q-FYn4p>whB$x z)({^&hxq{HWQdDlG3j6eadD)mGjAk=CdkbwZenx*ITz$49q``yPH>I}rH{>E7jS@% zs0OE^PH-yP$H2g#yB2hIVJA2x-DhB6(3>@VoqLsnjs)n?P;d&=s{+k^%mACk7=&;Y zEF1+)A+F;0sFGm?g`wee0~j-6dZ0&@5?HiydId~$0Z3G2`dW`FKGxF}3=F5IAMmJB z;{qid&5fXBIsIcumDuz?zbf%8$bbmQHQ>-yX3z%tLh%47bpL@v*9+`7&@N0!4*7=^ zy8pnT8_Nhw9t_OTk}4KQeWpvOKU zq!r~sC&5^NL#hqz5)KPkJX?T6nK4MefPvA1dBb!zuPRkV&{7*lJ7&=0VWx>8YM`Aw zAdiEt7XatSsHqc;#HJ^CRS8Qyu3%uuHwQT*ih1IOdIoh+M-&ubv#0laRjKoV^?{BK z2f6%9gb~7^*}}lU5NZfE5+cPk5p=Y95NNX^Xc~iop$Y5> zdrO!nBv>H1O^*?Dw3rkNsI+39_@GV?G^N5Q%>tTIVVdXw&Tsyfp!^2%5(6TDL3ba3 z95~AYR1WEKT0yhg?&-U{t7KT;S1>T#o_^cAN*bI@{!ahxT_p=Ie zN~#`YHaH20GiZZcXAl8OxS)K=0GiQboYQZ~z+hOwz~}=SP-P4<>I5C*>;n>I3^vS3 z&0}En0kx?ZLl`(%rdl#EXoGkL4?(6Rf$|8%l&ervl8{YF>bC@)Mguh_38axRgu!^G z2YP^$!_KLxa&YmVP^M&Bx7FGW?85kZz z%(?Z~kazlfzbbw^)=CBjCL4$jPyrmxXaGvR91aZXQlM$mN(KfQuyiyy7lJ~GL0yfJ zfkCp8fx&jVjenJlr%EMEKXgPD6e8f%Bfy~TXT!i?;0}uSJD?ys1Wxc>whRnL;Ii=! zB)yvyFfiWvJbj^ml?-G2^nLzS>T)18(25R}#=#y2omLJC4oO>Z>Yi>8P{qOu@`Cwv z%YZ7G`cPZ2OBjto^+}N`$R`sc7}PgGOBB%7K~QA~DY+vUG!H-}G{854Afy5qAP%<$ zT@b^_30e%#a0cvhaeG)+|WI(3i@|%Gjq=eTGtdfB=9zZ7wf_$A0mB|mR67~d@{q1&O?=nqv(O`^bF6v?h zRq_rD>Rk*B44?{dAygjR1OSyiYO`PoVgocmJcOG0Ah1d%8C1V9*h9<&>tTc!WuPk! zWWj|rv_%0j4jM?{V>z3V0_ms&ERdR^fusZuq-Mqq)8m7xL^+lyF)%Q8Fdm&=6I7)S zDWrR#0Th8Kqz$2Nyfr}m{Qmi$O3=DqL{b9^p zkfXG=#C8;1_lNtxU4x?_6%4SbOb(VKe_{4)(R{O+S$Nh1v<%IjDdk6ZhAs^ zl_Vso!0OAXE|74T8(t->4+@8^E|72ll_Jqh69d5E5XPY92@8i9XgIuq>iiO3B@8hW zRH=jVtFkNHOg?r^P+81cIo%uACsDdd3H>hrbi8d)U_&MH0Adn2o)Abtb47%LbU4nq~4j;s=verCkLaMumV zMo{6Pc>{Dc(e$5@Rmvin9x(6uLcOPJJl!Cw${OOcVB9{NW*X& zs?RP!q(Fk8^1qmYK|K_75N8Dg!=LFNqN>y(UV!=2*aKv=*mRrdDj@|>kr3p8WHh4a z18o7co1Pb4rR>b%3G>H%s6QaNeLfRt;RItaxNw*7glBajSYpwDCYD!VJ4L7SdsK-} zi>YF*2Sq%*_F*o15ANrH&J_grb3jIcD^d{#ZIIoH?w|v>lEJ;i3UCX^z?*>q)HO@y z_$xDo`Dn;Z-q8KdAtzHK-mD49ONNlAZ6?N+KK7Z!NE6V7LR3foNn<1Kooq3o6SX z=}H51c6~Ug?Fp*?85rk);sa8%g@gN5otz8|pq^DYGsGo`9tW(y9O47YPNLIe;;V!` zK{jUlfZYPK5p-n^*haK0jT-z>qdQDgjn5 z6hQOnGT-SRJ*sqU)oY=x!=n(LkS-j&Tu=w4WKiGrCRjR}X`%~*`T}T*|2h38S?<%|i`4{Q8Do}I3`IzVvxl0;~3Jq{L(VlMg*suh@uSs2toJqS=- z-GfL$0+d0mih+Rv6j$n?+lxT?i^(5kUKDdtJ0rMgWnoaC%fP?@(kcm&f@xg_(+aAo zL0WA=^4W}0%tifhy(gi1LqKwjQ82w1VR}J35I}k>Ao9#b(_vaQK?|iooqkB63C&ob zpa5qqMF#E8=^K-(M9obCU_t5#E(#ZOLCZIn0C=!rWFO&x=?}ZA4C_Ju(h2~38Rj;4 zh5;AMAVa_wN;7DKY_h!y8khhT7z_-Mto#;kzYe$+cZ3VpG}Hlg6&RqE#b0c$0Uh%P zDsImNAkr~-&EvdRXdIh27x9dySKDE$0_AnpWpn?dVl8Ja5@7}RYT z7#R9Noq-^*gW;J|4K(yQ8>9j>TD!cGfnf?vg(|pzHH(!&9dvyjsBBydlLBQWMgs;l z&?Q;mx)M|@fGmFkQNd`a!5GcT%rISVbpXfoH>p*^;MDaSA`44hE1@YL+M`+k8Vp_o z?r4A(Au`Sp41tBt8gS^i!b4{bO6Y6=hfW$d1JaNXtblF}2K$$By87w>{^`AGRl*7& zPcDE6Gl3hr%tati+JTO(w`XA3IsHIdl?bHO1nOsjy!9a%5~e@Ws)Un3>5)AIY%I(t zph6Q=bTHU9fCiPffE&3W0~zPc41pE%TToh0TcE8c%sQni1Y%iJdX+GGQ|Ugasl;5g zgO!277Ib+t<63Zm3dw!8p|J2;3ocMw;Ni6vT7iMvIv`~bha>EUC32Ziu)kpO$1weU zSCuk2?u;Qa5RJ%HDL7^Kfcmz_z;4+EuGANW!MuG8>=wo#NTcx>%q5^fB#(4uC+RVXZoQG*w6sz7;I3iFo!_`iYc>7#uZd@s)m7G4=wANi%u|uIxrjx z4C!8YhdO}te3wSs)YkFoDbcDQTdRG>7kaNrQHCa{4&{5DUSyf7mho*ne zs*+RYih%a=1sSwKZnhNzT^)4@>=VdUfeWTvWLJ4GDo$_AuJRNC&BQE-ggFYdQkCJ( z^n2M=vW&l`|H-bBWs-=TE}c^)qiGfi>&1R#0rg_pco`TN)Iei|;KBmjd9Pq#D2oJz zw+@>oXz1ef^hr5Ys^*x~DuOb*2&V%Horr*!4;)a+6s=z_%h%Fjo5no=FFxVv1>1ugZ zS`bB`AyAN_oM@2e#imCURPpgyLYvi^KA>jx^oe;@TJ<2WfNKvq25pf4ZQp<{ujm1X z3aGWtIHxrh7Aig9P$}YNV9=cj>Sgz^fOHXJV{r$PXAIb< zjE2)!)K#fYcgU?`g}6Hp+Q@2%fq1SXAL_Yv(--7dX@Z04FhnzR(R)S)bY;> z zUt3Tm$+%(q@q#KVQAN-^jWH`I83d^07N;{XnzC+~E>>7&;-(Od)I-1(vY5 z;vqo-%8Z<#!N${-3=C$|wTfVkY|w}+$eU$Qg%1L&#QD|!LffyJp#B(mFiULu#-b{z zdXN*re)WgejE_M_;{OB3{9$nEs-6fdVg7+*9#*>kXMuE7z)fY4B1q|K1xn+fOD63S z7#Q?G8*>@?zySuj6&W;N0~!c`v@JClqo;cnSMfvQ2iB&jO8~`>E~g6v1H-IX28I>W z=M`6}vVoYF5~eTAuac4kb>kV-WHwH6Ni!pV+?cA0~Q7b z?ZZqA49+#6VLKu4R$x%?5Y*RXobzFNWJ#40qwVyXk}5C8kJFErRC&9C<6IKF$IuiK z=Q3;`k{KA7Cr+qWElMq6V3Y+L16o%LuJZ&^;IR&B34sRFLZ^q9R>|5HC&41$mJJm7 zVW6Wwt#TL`K)YQSCcDSAvWNkmEz}(#dcK16_zrku10|NtSo<=YgCOa1_%LqDR zR2}3sP(5ri-LRrc4w8gGJyB5FFG+=X5Ht`4^5DYhQ!1)7ARYwus-PJFnBi9*mo(M^;v8#`%H{z2C_ilfl5iG%-N00F;7uLAil? zwxC(BeXO97d8Ua$dLKboH5_6EEud$b7zXxpP6jMpsDZlb;3xqNpMhNbEe-5q-9*p@ zK`9Ij0_otQ5z=%94fd&lRx*IKfUZmiX$eS&q;~(RDj8OtLgX4x0?r0|y67_VoGH zRkn=xrr)iua#sdt3>J1!Vdx0S80_qzBa}eXsbCMYWKVamsd8j&pWazhCCj*U`tq78 zS=+;zu;|oc2W0}#Mji$$P*h1UFfcrX%W8vVXM<{TD^QakR6hQn&RAO|%P2ct9zUpd?TaE&0?zmnp6TpW+W1 zWni2$DF;^Ptz!d?7O{yjFhIsl*0F)gK6Nn$2EBWr{hu4y4uVd}n&_aC$iTRP4WyB2 zqO(d8g5w1akxe=9Bmhd{;P}+yfEHidr!T0hGV*&|$-rY%jpzLJ6ADO7Bt z189H%G&TpC$Nyc)!0;a?;|!AlB`fwS1_sHT=?e8#BCLfOph0=d`YH!V{DanKKr_M2 z`YMt7MLE#?%?8QeAa{b(gFJ&aNX}LmbRWt|aM(Nt*9wpGV70@Hz7;xBuY=l%X zi18>rXwWUr1rIBP3Rf{O?8^m*9mq;paDb{;P(a;)NP!o^fNpGOP!D8aU;qWwXNU~* z#9j3;O`zdcP`Fu67jCR_gcL9{q4pKzLGoTjV-;isf5P+$jaAYRMWA7MP~JNZRdl|w zN>~!5I)V;y#V{~vFPQ$ju}V^8dI1B2aybLzM|MzSsvVTj=1tdVs*+^|HH4>6_iC!r z5CLa6F7RM7B)@TU9G%|QRHbLTIUkm%m^nasDg|_!t`%qu4s>ArMYt>aHpY5j9Xn49>K$#!5*MD4=vi)If{%z%pT=;Hh9>SX~6MXme|oFu22Xdiv?s zDrr{G)YseTuUo5RA*lsa)PPcpN-;#eP8)2N>jc!KXsAqbTa~b~Srr3Aelgg|OvS1U zYA;}oAW#brWX^i1>UC{ZGORE17#OZhKi^iR0I|#p8VVvM(+{o=5SuR2UL_4yWI5fW zy-ER6IFy1EAtG29QY5sMK#K@X2JN!x^V+KfEV7avbR;8eolWhujw%ZgVbGAwF=*rl*n?(4y{7wgz>+2`#JfsC zA+D~p{7;#@Iz$*4K$xqQ(d!I90|N+ioo4j83*ut*fA_0uJQ*#gPt*ckhi(SG7Mv|%L#?uQol!`N3npjRZ zw5X6^GO++%lrF(!Vm`GnM4ZXeWV(Sxg(Q=S!F0oJX$eN->4`in5=@rH(;IAkML@^h zLhezYo_9l!Z@R5T1rL)E)FdMdh!&&i2J1>im@SP=z*aLFO;^03C&_GRX*ykTpQ#9= z5yWCcgXxVkErh2RXje;4U#L?p!enF&zO0?u(!c`7Fo(L<)DmnKv#F&i=o)tkM)T>7 zw!Xs5mPV%2886p~Fc}$w&0sWyy4P&_#zY=bCId6D^mOqpf+wf{kE&&xUJ%JEHT~6n z4uS3KbgT0P87-#=ysi?TZfal6&tz#j{WMRN2<%WRHrYruhwHSH=KUa zzFJiqbO$`_j(7ue6rKe#&(O$hx}rn1I+KOz^z)ai#HJ@WR0}YgPcL++&S$io{?MUX z)!fh+>B4y)VCpWNC(Gn6arLlI6z6=4kRJ2Iyv(m|&P;0rCK{JtiP~(&ABs%ni_uwlG2y zF*O7E1?DqTV^BaNn_+5-Zjq^_;r2eK>a-fkt)R+n2BbU$?Ga~$vL8(6-Cu33s>#8? z024ApV!I%*Bd6!?uNLP8ZPkV;ZJ0iBf3>*b4kT4ak=U1!*!PjxuczPKU+pgG2xDoQ?oiw0k=VLOY$qhP z9}+tXiJgYT1|5wG3yXRr@opsc3J4o?^g08>9S8>;51?r-m}XPZaWqiJg(0yUkl3Iz z$6)GbAc-%TzVKkRzSILGp|?ov-`vw*9jsQ8)B<%Pp;nk9v0bOD9;%L)+=?W02#I}R z`rJd+;*y_`g#IJ3d8eN}RISWtGyUVCYH`nS&|*)h9mz=S3M6(b5_>Wddj%5v%=Ey+ z)#8%xkc56Cu{ozV9q{UUaL_g)vHOwO8E9@2wa2HH^%OJtjn)bI*} z1}>qBK7ixqU5*u`qHB3z)l6c(owa2T) z>no9jT9MeRk=Wai*oTnV=aAU9kl4?V*q@Nt|B%>RqF|pv!d(o)0f)O165ASy?T5sU zLSm;Ov5S$|bx3T`;X$x4n1UoeUv&DR6V*zRXOYBiA+cXf|9hgkxxN)Ns0t0*Nl0wa z0m(39_aKR%Kw`f@V*f{Cvm)haZX~uK5?dU?hJ=wUgaZyEWhAyH5?ddMZHmOUMq)c6 zvE7l_zDVp~BzB}Y=;AY|@8gjqQjyp>NbF`Lb|(_MABjB`i9H*My$FfD6UGMle?N@F zz`y`H*$x)$r;)@jBC)R{vF{?WA0x3}BC+2ivA-g*e~W`|mxB5pboUX=Vs_AUHdI^+ ziLHRd28|HH)axLL8zHeRkl5}>>|g}jjv)cTVJJpogLmUV9Wez-d_EF;^>)iM)zOUg zI-s3KP_>pwYV)H)t{#>H$e4wmK5q6p8JO#1523PQ*wOxk&74Bz7kfdpZ*P91{Bu z68jYr`v(%64ZO_{bVMU)dJV<_Eo?_(8z8amkk~#*>?kC51`@j#iQS3B-jBpSErXPZ zuOmr3Mq)F7W)PskD~!aJM`CLuvCWa#&PZ&3Bz81{UC)q?;4pL}vB5`ILM>j5B)%Sr zy&H*r9Ep7yiG3f5{Thk=9n6NLKL%#d)H&2Lek8Uu5?dXKZH&aWM`C*;u``g^#YpTv zB=*L7B+gzW_DLl6RV4O9B=%b*_D>`>KWMBH>KP3rwlxyl9m)pn>tG0mazObn9*LcU z#4bl-HzBcmk=Qe)-@I6@EO`t`=rR)f`E=1s)yk@33g9XpWEq1p659}oZ96^oQnht` zJCe{8B=#aCHt3uLSh=tdN&E~F`xX-W1rqxk5}QR4;VdBt8T-EM=# z_CjJuAhFYs*d<8pCM5O*B=$Tc_Ibr%go|z?N&H7*bAtw8p>Zva#8yUP>m#wPr@y>h zy}zCdsbMLO#I{Ca`y;WVk=W@->|!K#JrWyqqAx7WrXz_jhOi+4yB@*;2j*@hHt1|- znC8n!;`fo*uaVf_k=V?jML*E+;74LhBeB(0rZ2l%9arCvBsK?$eGG|x6N&v4i4D3u z2j)grRYW`qBC%zW*qTUeQwSThc#na>3Bmyff-e#~5s96P#I8hQw<578BC+Qpu~$xi zd9C_%eJf~+6dEp*kk|{5*z1tkdyv?tkk~hn*w2vIUy#^LpbfZCy96L?&}uyf22%(J z>{mx5b{G;nd3xZDYVqkMH>xEhmmrC6L}H(xzVt@5HLogY5i!&rqv>yNR9j0nAPMy% zv1d^e4Bf6Kr2-A>#8Z5}RKe zAufx=)<$B7O>ewiZOu4;`rg~s;=H?%WR6XLc)L2dUK6w|7HYQ{5<3Kmor%OQLt=L! zv8N%iK}WX065}x>@heE|M-Vn7=Y4>1z!C8eiOmCAL;`i36cSqliEW0&c0pnXA+ZyX z*m+3o8r^zC5OyI+%s^r?ug>MM&%odPwc9eMk~#kl447*e{US-;mfWpnY3V zp9vwc6_D6^NNgJfyPm-d!C{C%Vy7XoOOV)2NbCtn?0HD+HAw7TNbD0x>}y~)DEt{1 z7;-^t`Jq0jL}K?Ku|el~!Q%TnlDM29A`O`!vAvPlVMy#)5F5NWgn=Qk9&}y|l#>IJ zfI6ZX#0G8kV_;xdh{Rrx#NGm8L-p=OVqXTaK_?n8FfiOfVn0PO-|#8v{ap%%M<*ic7%gV^B7R|W=uBL)UxC_4%y4pozZ#4a*osApgV ztuY2|zyV1>H8dcxr-9f|2hB%fuRvmN1hJv!YzMKS<~#?np%%XbvAIEBWMKFNavYdl z&%p542oZlG#taOM&|ud9v7wrcKy1+THv6$}hlj2Re&q3ru0aj2SaAU4#|TqX<*j8HYg zNNi0I8|pYCBzCWFp_8!A2t z#Dp|=(&|7=AfH+WzeIPbyt0n^j!(k8`Dt-~fhFW|JiTwe@hWhL$5}U~s zk&wATY^a%nAU4z-Bhv`bk^2yzMIuR5A+Z-CvCkl}uOhLZgV<0WegQgkcf_f8>IMlD+AT~76;z4Yv`V1s?9f%FJvK@&%0f}8d4a9+J zUWLRy24X`kI}2ii77j8nFkA#V2+F<#5{If`Ge>wp6p5_@VnfyIBC(x8Y*uLO`an3~ zP!2_6M}yc<%>_v8IY{iKNbKDpHq^&Qkl1ID*q1?UsF|P4LA5)S!)bx=fdGgNTJ!}P z?66>f-`6e=5{LR&7m00)#P&gAhk@9j(=8Yn7@|RJsF^7+HmG)~0&$?OZboAFAhD-{ z*ieIJgV<1m_8_tEAhG`;u~jV@7(mwpf`T^`#D;nx+7eW|gO&s{FfhbhA}$3lMN%{y ziM|_vo1}OYNwL6FdRa69G zLk+4!Vt0VpP&K_EHdM`Y5F50jmVtp`4u}o)9TGbQ#0E!SJp)4)hyz;G z&%nTtXT!iC3}sh>#KDRf82UhLXt2*gVy_3Wp=yqS*ibd6L2Rh_RS>%!6t)Zuw?J&D z`Hw+t&}bS+>L-W;^)ZtzQoV%476GxL21$X~P=hRx*kMTQd?fY+5F6^C=^(ZO$W{i1 z`q{P&48l;(GLQsR(H123eh?e#vm+ojRLx~1_9G;QTD*P{NC;}gY9#hS z5F2X5DJ1q~B=#K;8|sutAU4z-MtcSZMkrer#D<2A3WyE5Hi3bGLBpPbL0Ab|*BOH( zpo$!k*l|egMi3hs;B6o_RQ*&W_7V^qYQb70_F)hk>X|c0?5p;mx(+IF8zceM`~itA z?ZCjm2o+aBVq1aOP`%DbY#$_c5Qq)cTZqJ-0Aqv7+6^!c0|Ub~5F6^VyCAkQH~}y` zbYNfr%_D<&Z$RQuHQzyOXsG-Fv7zEzj);m|5yXb7Q3J7|Y787fbzLLKNCpN|kOb5+ zJ0x}hhz<2+BoaFbiJc8%L(QoLv7r{UfY_kZ0vQ+>Ivg1ogrV%oAaRJAdWLx*4%Bsv zL2QTw!$u_b2@o5q<}8Q}HRu`=`vr&%b?8SV_AewhqZ1-jI6!PQQ22w+s&`^w0PQ~j zg@rgs0_q4Q5F2W-Arjje#D=N~LSiR^*lHkC7#OmU*bN{y)N!3i>`C=VoEacCRPzob z_CX}}br2hB&;um)OC!T!&KazO6x0XJA>-FX%GwkgCw8^vAQrYFhVT@ zZPEi-4BD|Q3lfK_Q3kQ0YSdjIjsqPXWepOCs&NFdp=w;AYCs1_MS{e^YU&vn;z1m! zq6{Q<9f%DL>UJdd1SIw}5F4s@8xngz68kEM4K?Q;68kxbT@RIb3*tZx`i8{jaRpZi z;2;u3V#^`1RX}X0UV9K58q{teHfVJ=0|SGXD+7ZtlpP8ZhpMU10dc@V!NAY}VnZeR zk=XMC3a2uK2I&^;vfR}dQ-Dt|z1$S^nqgF6F* zFqF;hjwo0pk=QCAHZ*kIKy0Wvp)fWm|D}L9P=j)j*v%j|)YUym?5RlX*&sGl?=~d% zMI`oLBsQA|0|O&ey^IH_{D)eg3X*`b^^n*mAU0G(FcLcp#D@B&5X9C7#~wqe2LppJ zl-&RlhpOpAV$VUa>lv1TIK2?ft3hn2<}FC5olFc24Ba3$)Z!^f>{az34%BCxk=T2X*hfKZs6m%NY^Xuckk~(w*t}j042)1U z3P@~YB(@ur4fcN&lmm){VkCAO5_=XBdmR#cI}-ae68j1g`z{juGl&iK@EKiu@8ydVmAU0@+4g&*2fHwn!Fq9n)5{Ifu1+k$~lLcZ!#mnLB zdIp9@5T_sHcLs(w5F2VxKN5Q>hz)hf;D$p|&a8YB*7rz5cod_m_CgRFYQb_48>;sh68jbs`xg>h)DIDrG9WhSkaLj#75o?&gh3nz z(AH>#A~TR8XfV1Uu{}X-Xpn{@u@gb;Zb%wR1F@lI<|DCNL2Rfe`}`OfrWdR#6RBSS z5{2qq3t~fcozz7u=0kNU#r9f<`xH1yk4#EZn0t16T zhy&FS3SvVw#38XOk=XM=Y-lhn1F=E7m>C!tR{1k92t(OhLE=y~2S99Sa2^G*q2lNL zL5Tpg<(+|n;R;9ss`)Mw`!k3Q4Yxl?Y}NpzR0(23%@F~yq2{Q9*iesYgV<1UFAy8# z2$25+K^%KXFbG502_SKhA_fMAY!Dmjg8~p6Dqe@g?f|htXJ9ZeF!X}hP;;gs zvDbjuP|s`)Kxzc+Ly|ZSVnYo&3t~eJx(8xIee(pwhKe%>B2q3Fi0ugR3|}AvgD{jW z2@;1oS_Q<0c*dMT6U2c^m?Nfi9^-g1+gKHW_Sc*&w#dIKR`HO zm;MH^p^6xSkU|B-2AwMlI&cTXhFTzj#MT3`p`I~EVmlzQJwa@!IsQSQ#0xbj0we)t z7b3B%kl0g^*z1tk+mYC3L2Rfat|77SBe9=?*dV(=iT4|b0}b9kAT~&Xfq{V=Y3-8` zi0ujvAO^8u1_og$8+m<{4oD3&8o^=s2x3DGWeP#G!#F@}sJIY_4fUBM zhz&YBfPsNQHiUse7|PZFi9^+xA+cRRY^WMvFdG#9pi@;r9H{GZkl3Y2>}n7js(BWO z4Ygn)i0uxEnx!B|K-n8W;!riaL2PKS9{{nT;^*p-I5$9SsDti;*ieI>A+i5}*ieVE zh9Z@oNNjNs8)}X$hz&JI55$J1GZPTo9Xc294B|jt(#P)`ymCa!c48rwL&OVR?RM8nE_8lbl8zlB`BsOa}0|O)I&_M;vhD7 zg)IYvbOZx~FqEwi5{J#j+d??taPdZBry{YlKy0X?(~;QgL2PK&+5%!j)$9YYL8rKa z=JY{q=t$Xh5F4ugZUm_Ohq~w?)ODaMKE5I;`VC@3)%=I50ZlRpMh%gjM+s2T?t8$1%H9JKhpIUaVnZEtCK6QsLnW>wN!$Ukq2kX#Y|zP`3=9mfL2Rg@Uy#^bQHX*_ z7>O-|#8w5dq2_3V*bsB-8B7oy1}_jB8WO=s>=-0=5{M1a%rFs&y$p$c0f~JRiTxhL zhMNBa%m#%&=(wC{gb&z3Y^VihNNjr~b|{DqH7E{=osPuL1+k&#lp(P@Ky0YqiSTV3VnbbRgv7Q+V!MFYP;?s zVna2rM`9mAV!uUVOUE)WFhbRG$vky*idcaafmjqK8OufV*+AB z)!2jBP;nO!8!GMxVuKFmVqjnh2C<=5hQ~py2c2n{4HAbHw1prJR8c8Z5vWPi2@;1| z&<|om)l7z}0p0Yl93&1^vlhgLs@Vut1G+ixC`cTt<}`>6RdXc{v;h{%c?FVSo$j== zOt~KFcY^XWh31D;T z89;|Iihv}b1}THsP(`34b{L^-42G61x(_hFV+?VnfYYiNwB~0IL3= z5_ga!K7rU!3w|T9SrQS&Bo~Mc)eAZm54KFz0wf*@@v%)J0|Tg<1n~ku;?SfK3Sxsi z3@UyTKpdzUfvP{K zBF!X3E;I(QL8+O6fx!aAhWRE5;u{;#m?=mcsy7V8hN_8zssUYClm`-rswn}np=v6i zYH~ouZx2WUs%R334OKJ^stB}ja}`J&s%8U-4OO!Rsslf;$9KN29lLSlP^*igp>g4j@V zW+1T_BC)rpgUWxXp$9+`Q1(eA_9YM-YUm9R8)~RR2Ew75NNj5m8)}XV65AJv9R^~9 z%mkG`MIa6|ZfZen(7|$`xsnV924N_BDo7lf!j~YiHzTnRBC(Hw*ibVsg4j^K50KcP zvlHuK3-9?d5oLfj65ABSE`sC^D-auMXex*eH8cyvhB`Da6XIylEL9Uo9IB=R#D=Qr zfvWKZl|KtW5>Q3UKy0X@RZvBsO9%FW#Gz`AfY?wqC!lIT4W2t7aj2R{AU0IZGpHKS zy2f81ai|)GECvQfQ2h_`8%q|%)yo(d7$iUvP(^YeHq;;`sG7YD3=C!p>i7VrfERcO$W;xf*BYXDzX{e7#N|JHG(9d?CBsj)CUWY*ej9Pn?P)+K|7|m z3fJh@OXV=Yjf+QOXCSewKy0Yd%}DGXB=!yv8|wD`AT}rsf<{qt7#M`1>~kP-sG2(v zHYhJMFgyowpn>oP#D*%8$VCLQ5r_>{;|5|w)r2Ck<3a3VaM&}XfY?xrbCKB1AU4!9 zJ-J9_*;FKnc_22_AkgKbj8KF2gT$fin@H?0NNlS-1_qdVXC!tchz+$k3C5modqD)mVbq`H(Po2eF~*V?b=EnkEn%D&7uaL&c|o*lExT zZB{e3xhHJ}mGGazxOnoA%yRLwQ08qi6&uR!8ZH6K81sG6Th zZ2khIL?BUs=&UFrv9&;Ks4opbY^XueNbD3Ob{U8bji!1eb_WuBB8Uw#6O;+&f;iA% zSpi~$u1scNU|3VYz#t4|ZwHA()f@t`p*}kfVnf9*f!I*->mW8%{5cZ)I})3*5Y(Xo z-DkzXz`$0B$Zv`uHq;ehN{T{v7ve!Kx~Nm zdWJR-2kOgyB=!s>_Bs$78l>Bi*awi<|ze>bO`Wb{Y~pAH;^5Qwm~3&8e$L;!FXtp$5%G zVlP8tuK}^4n$IAy-yyNTBe8jl5s6w1i7gLhgZ-}x;y?}6Lt?vt*iZ-gBC*4e*fAhB zRBr(iyAp}r4`M^jnSsP!SPbgWKqXdzB%ndG0mOzHdIH3Ts<{ecL&fhQvA=-WP&I#% z*lZ;T-}8gmQ1eAWY_K`?3=Fy;4pg%hhz*utU~ooahl1EpHE~GnbR>2Ghz+%%2gHV^ z{OKSz=n^aj28P)s3=G0h_A-z-Y(>&W5C@Va7!D$_kAc`wgD!&DP&L;;Y^eBCB=&m{ z8#G45z`*bY#D=Q*4`M_0@|7Zr{CZg=juMCs)nEu>L-VUEhz-^34Prxm5Q4#^NbD3Ob}onwHKz*1hMF@G#0KdF z<-fTg4pd?p5_=Db4N?R;s0)dG4vBpo#D-dM7sQ5|^996)>SZivU|@ubb0M)6%0cBn zRFNh~0?IZ*Vq1gQPzxMEY^XtANbDF88>%-IiJgbUE(fup<}`!YkaSkh&;{avZcJfd zVCXAnU=W6~XM)5biWruF*w6&H62yjzZw9eJcMCBvFzf)ap?VJ@v9E*JP{%z$V!s5l z)4^$u;S-1hHRuP34K;|f0w(x%N4O!e^N`qeNbIiZhVnJy^$U@NmLjp& zAh9u{Dv{21slZB(@C_+X0E~fyDMfVuv8HBOq*0 z{$gNAfN;QGPC;VlAh8RO*cC|Z8YFfL61xM5JpqY51&KYU5>&oG)5!uPi4{ofHAw6& zNbDU*>;p*bBS`EsNbCzp>>DsP$p3d>9MC3MB=!p=_6H>P7bNx{BsN18BGx&O*gQyV z5hS)m6$3*OY?xmGNkRpQt&POiM`D{Jv8|EV&PZ%`Fnc8T*<$@Hxt%3?a}@*00epXs3>%4Ygf5OrhvR}fV)-E{@nl&K)9X8KbQl`!3O zWsN`Mjp?l*s$u$75EU_9bybZ&6 z>8_h<{242zPu*1G&&08I`m;?nevEsjn{KZ0XH1#i3ZiaIzY3!6Ojq4f7rt9to*?3`k-R>Gc#s$;Q?gsg4yX>Bt4DGqg{RLsR3pGxFn#Tz8g*8g zTcB&!7`F(COn-Z*hM!5HX8J#n@*}qy7zCy}%5Vu!w>exRz<6i6@8KGC)+=`z7$#4j zxP@JKdJjmrX8K%^aQaUM2J7i357#I&E}CwbtSdg9s>8I28-#5dW^!;b&k{s zFo|kUw>wg!#<*pA>X90C#;MbLkJPC1ep$=J@Ijh^fsK)Yfq8o4Gk$5-Ru4vojnh9? z_$c#QL^Cop2r@9RGcquooqq8dzck~H>AFX2wAhRcj0{apre74+6yIKQw8qO3ba1~o zv$-+kOn*l6>Gd-$L|M#D3{0m_+>$KJWMT-u2Y}h!*lc=WM$_?W(Y378!Kd`g-3b+# z&Q&LFv^|2Owv3s{&}8}r?pg(AkksAH^23{F6z`(}{((Det@Q#5`Lz01k-2-e#JqyGrPq1zg2CjJm3=HgE zY(GG{Mc94WirHa~@&jvN;7`dcV_^3OyF&nCbpTki5X7WFFh`hy%b$&bfjx-LlpXAj zP`15rcZ5OQ0Wztcfjt~-6x1CNVBKsGCq{y8WM|+yDa63Q9>rDA z4D7LBB@BF%*clkug&{O5Ik%%%p$(?2|~OLVjV zXZhsZl=!65%$$_?#N-mROCwASkZ-UsH3MB50r#DS(ez0#>Rh4>(XW~?GX&jq0aIs& za;1iu3Gy`*W~Rv3ZJ3#XOoHn(H<@ntvQA3Q0!4=>P$Tor{9|-FSh-`qJ}SQ;`f9Z7{Hf`GO#d$?pos6%gMkH$S~bM zUsgiXpNWBinTcIajDdlfk?p-G0|QIAAOi!F5NNR^Gb6_$evmvXv%qwnRSlB$KZO|> zn4~~A`!aK|{^w#~VCH~aJjlYDD!{KrO0~-tIo=|qs zeOoMX+zbrNqM&^SES?~<6+!n#up9>|)=34eQV?WiU|`k-bwF9BiZC#+NPupE;$Q*U z$?77_!N|bCDG9oPl5->ImIltt+zbp%3=nxXDbNkOoc};aUvY|nr3Kg+7??PNKyKrl zz{SA8!a09B$La=IdC)00jGQW>AnElW+ZkAPa5FHl*|{(>FtGGZcUj$_!wbH9n6nOK z1?TMPwW}Ls>(_ve0OEYW$iTqJ*~tRZUC+zFz|46P0J^z?nG1yCo>BJgCM6fCj)~JC+G@A5l%K{ z1_n{iA3O{UVw|^l7#PGk8H5=aBsjDA7#JiuMR^$*q&U5J85pEF&kHdy$Z$U6U|^8t zloDrP_z!bq#Ceb#H*hjAFmP6}g8XU^4umUa;vmmX<^&}vmP?|b;vD21NcgiS{s(E3 z2Q3NX)D{4F&0GK!=9bgXt!a?0KgJF+PZ@Ms1ZM&>NV*!7?ig4W@i8#47jc2^q*7on zUChkDz?%=MAIm^6I z!waen*&9LPBD`jx%DD;TE{W+`Ya0~n-9QF+1cPz}?^#d)cY@fAynJE|4D4MXHWTkQ zka#!fGzAvkMW9-(2gK&!oeZ+17sTe_Z3RVdAIMPxyqO^N{ZT9o3?jTcK;};XiA(Ud zfYeU}iOcYUF0N;vv=`LRQ{a^aRrHfV5-PlNL3R0*O`yX+7?>HE!Z|=02E=9I1^I94 zI%as%S<%A6z`$9{1PaD9(82l)ET$ketFu|)YSwK5sky-mQu6|IDGnzuIO=YLaw`Li zg(JvKd-_=z7grA^7fPsNO2~?P||KkL;k-!rFArb;kY#<#hj4Esl41!=8 zRz|2)wFm=420Irc+d+_A>2&rD4Qh<@rt58JkgQJw`BQ)q6#Ei_h9Hj$GJ=%J2!dl! z2rLsLI1v;y!eCBuc5gZ;}= zb_NEK51;`1b)A)gL3A}JqcAXn!cp`ys7b}f2nssUQy?W`j4JhP3=E=DpoA{N2y(Zm z5GWxjf!!;r0`jK@*nOh$prFwMJBUH72-LjP2RlJ52$WRK7(p#eHkQNe3=HCz*%=rl zK`7}M`8>N9Ezau;kwDrzyP|okb44X0GbtAJaNjaaxgG(9swQ9$O*pD zfb%7|oR8xJB_z-d8Z4X@pn?=q@o}nw%z%_pTz;(}y$PTbCpmAifr_@xVxaW38dUFa zy77S$;S@GdG0q|aDui`FS(S6Xm^`Qy-U!NDoQkZVLfC_ufq|QW{{k-q0|&R*x#=F8 z8XW6A#2Fa4Wk6OytmBsZ0kW-o1 z0Ju`wE)H@{g8;}i`k>m0^Es$Z%h|*Za*PEts7h$#139LWALJO0dT>3-BfbJ;YAfgl zQqF6jOJF!{K$SY@S3ywt$bjoX&?OzLoLdAze%uer=$!LF1u3VqFv!$>Tp&~Hg&7#Q zIp=XOFz_(&dxHg^D{7T@Hlu)f3dkiwth1^0|Oh6YcfcgD-#0)j~l3*XJFu;11jHmJZnG_&H@Y! zJYJykn}LC!SAc;*k;iu`NFrE-fq};##AIOL0<}SwazS&Q0t5eT0gy#Or$7oVSQ!|2 zf*3giI>7Grh>2A*h; zGbLj|7ja461COLKFo2G_VVrZAn}I`8WNzyByY&Tz%W&qfx(yuY!gTlVwWsq3{x=!gAB-L^B~S( zp17c1mNA-nI^XsN_GHjX4>lH1l9Qax%fP^B3v-hnXq(5J*C0265+9>2h`Ar`CVNyj zIbga8bc_ecO~{Mxx5+psW%|Kw4U%f8=7wUJ zD+6k>f($cO+`G|6mL|i=h7#O5LxrDI@#H?e4 zX)OV11%(MDa7!^Plm{6F@`%dxjXN5IxtKT<7-Y;C7#Ki~kekl5qd{769v{rOR*-Qh zE&<*13U-Npf+0TxgB0kb3C77F=0&(8rh;@K95D^IBS4K8S;i=o7-qCXa*zxg3n;fs zmVmCFSpo}U(Do;Uy~80Xvt*#Rn>7*B%Arc-b`PNUj!25tw;b26YsHekos?+3N0Z@~-(tqf+I zQ!mKCATAG803u@7#Ow)GcZI$ z#1PTOAmhLSO+)gbRiJAJ--7}RRIq^N;TY!x3BgJOutYdB1B1c>(1l&^K~*?outFZl z^h!O>8+6z}T^Fg;>FRqLl+orb*#6?Zci1#fT(f`0c#xPuLk4R0Fvg7&uNcRe{7oVZ^`y z7FY8WWnchdR&_N&Q3eJO=9N^B7h_-mVKvYtQy|Q3rKZQvz@Rrhb8mx;*c3hn1`y^< z(D*FEzyQMhk6EWH-t+a?{&;Ugi#T&)O4;;R7aOFf_XVrTZJ&0v!IhtPHV3Gtg=!N; zVk;xD4UpKNhA-@B%|ImaSR{5PgbnHuF))-uIN%^_L}K?Mv1cN&mm#q?A+c{Eu^B;q zY^bBzk=VRQY+(-2%pX*dB$9+Y5?c+4ZHvTqMq+y+vHg+Qp-Aj#Bz7W<4f20Fi~~Ag z7KvSq#I8hQ*CVmpkl5#u*r0AbEDGKriGM<3vvM*pWWp42gEBWXBm|Mz;z(>z#}%et z8A)6diLH;sHbr7vPru6%D9-DSBosBhkvmJAF>N~I$8_=O9@98^rb~QG=i#kGQqwY> zmoreDcLI{owCRQ))5Q%JAqlNSVsAxaA3|cEo9@XOs4vL?Y8pZP$&196oX-2GSbVy~ zo=l#4J0x*$Bz8CwI|YedfW)pvVs|33mm#q?A+bSiZCIF|hKNs}{xU>%`ixKMJoU_= zN(Jg#J|wmz5?cj{4eBSrOtV4~cST|cAhDy7*q|{AnBF3Ycsw{q)2t(P^K;lq`E&#D5z{(kxg4j?s>yX$-Kx~=m`xtY@>V-kwF$M;PyI?VhzULq| z)C?|A*9fXc7>R9y#Et~9q4p<(*w7|!Iu8SbFqB;c5{Ig(0kI+G*E7rqaiEG;AhAy% zvB6iwLN)&ZiE}_4%D{`boq!wEG=-`GjkJNT&jYEl0Et7@J0h`DL2MaN5x~H}kPqU3 zYH0=rhGLMRP<9WJ_*5kJRuCI%*?th43uF}o!(otKDEk~p9I6I1C3=9lwL3*L= z9UyVgMQtE=9|Cb8@xkyE#D*$*hs5UNXJBB2id%r#Pz#(uY|xMw0|SE_KLdj>lpP2X zhpLGNv7zQCfY?y+Zhp|>MyQ47Jz|);T1?6 z%KnVR{tse9^>Tn(|4=sg!ds|%b&$9qXl#jrfx!U60Xy3a#D;1B&1ArQ77G%G-hq%P zgt%}a2P6*lKpBV)^;tED4HaJjVng+AL}FhM0&V$#D!L7l05#AV7#Qw@EP%3KfyAL| zzJl0L3x0vvP;m`V(-x}U5Q!ZCVnfwrOusA9C@$H8B-D+>?w>9z7%0v-Yx>!niQw!c^HpO_Z18j=RJ=keQmnpEs(TapuzMBb|I$IWoI{O zPq)}+VlaJ;YD2>IB~pz`Bv}uHGcZU@pU9~oJUzjr(Sr3xI0J*h^oJn+1`wYkf`LJ0 zx*?Z>@HEp#3nrb2>2+KRV$%am8!cE}B0zdCaw!N;UjX9AfYmB;D+o{j0OB`*C))`>=gCPC{5PuJtFUX@HJpBQP{{YNS1n~{b8!cE_B0=VF1o0a{e3?j)+ZcHj zgr{Es@qHp07!sxjg7^v+jTTI6BB#&eRS=tAV9{v7cwzcVi^k)OU#1sYHu^JqOg{*s z&P*4yYV>Ecn4Sot8m4aqQ75J|S~vPLX~awqvTg(|q*-X)2wKYX5hQ95JKf2q(T{P$ z^ocf&pjAH)Z5qp2W8xSX&P-n@q#!)Kz_!tXNh5yxD%(as#wpW(+BW*LG9)lCOqf1V z7!;^>jUtSXrhk;?5}w{+*C@a`A(??;#`L*%jmoTi(hLkrkd-AjKvD*>3=FfUe>7nf zo@U=Dz@$+=UC6#sjrFu5$TaZUkpPgmMg8<7ka)Bb149F3P00fLMghh((>K~TscUz}PiC(4kSC^{6ugY-P#> zknrE>3qisOT?`CcrVEOJ;szvKI{l+VqdJpF_jD=8Mm5H_(;Xcf)ftaW&je8+(pjz!SWi~%uqZD3@^FnwZblfv|$-y3wM%dTnUnSRf=iEaA7q$bYoYx0_A GgaH7a#WGm{ delta 1048195 zcmcbzxrgOQS2xQ9>3TyWQ!`5g69okW1rR_c6%n!HXHq z_Aroy>q*r>W%czWxt7Y7Gn(zGCn~tuw=7|x4X&q^!9kr2M8!=Q+Sm4rVqpkVzo3`&IXk|zvG2wacMA)2kMzJ!4!oc@AA8HNv; zFet$|6w2+ZhZdcEC*Qi+b|G~>q$^-{ndhj+PEHU21;<`?>P*_;CggL(fgng(cnJ#z3|x;*kd9*Y3DGhP1BmMf z(sG7`=z7AwPueKKKr>uV1;bPR$uN+M>(Mo)t@*+L!Wk@g7%0J6x?32C!1Z_)W&f*S zz=w0~jxbP$>nSyWLjCnb_@KaS1p`&_R1t;(D6WSw@Y3gAFcd&>p`#816>&X7QP2&7 zxR~(|L$Smg1kUYXD5eUohZt0%8No0hxPG84hT2O1j~C{Fc=mbz!LW5y6lDuVJVq7uOTeSpR$h13GRn+Q87@`T!Fz%3)|A5!b^s zG&-(epayQ@ieVrDi(pf{xkkQOce180|7K5Ljh4+t7wzq`??I{aS;%-1H3znjDi4Ty~v)(^`&yvceUE=>?7IEXqu>9~jIW85S}yG%_$e z;6NdHBpVqRW^zo|7w{IFTzh5J^!cw8*e0i5wRgIc!NYr#@goC+Oy5BUhK&pe{jwj- z96^Sx;DDIN!wEJ6VoM_fLkCBigh`r_*<`tEs`Xhs8j1`IolHC+S12uHmi?f#5X58v zvl$pbE`#XNkWDj^U&{nB^Uf*=%_9NV4b}kB3}(XhYH-MYV1R=q3=9lYpu7eKaR!DQ z1_lNf1_p*01_lNl1_lNZkmTgM*OaF>7)wh`-{34MFUUbZt#dt%K49pzt(?PmeSU)o{Ffg;QKV@KGU}a%uVUJ~FU|?fe#=yY9&dkVB#LB>+!tx%Z zL(~yu(i4y_#V8Q71LPi^R1k9=%jA7GrRx7MF)*-Xfo)s|ViulfU|`^4VW|^iWMJUV zEv;Z+sRuC`731TXj`c07f<7^=H-x)#bl|cc?#|8=y z29{0^1_myjEsP8d{4?1Y7&z*=!Z?{27z6^D85p?27l5KupaH~=kOhSXgCHnmKuk_G zMg|7Xogf8lEFdi`_dv=bpMZ?I$il$D!Dti=Gl|g{VG^SWNIMGyOFlaT1EZ-P69WVP zWF`g%14h^1Obqo50-+#rHxXtA1_pu63=9m6?yAfT3@ic$AlG|<4B`;D3{v9>V)F>p zure?(dV$yi0zW|F-uBE43?c#&Ahu5=GXsN!Kp;r3Z!t3igN%R`$V|UFW(EcYftw(< z|72zc1{HxhAT^Q!AdZH>W{{zQE0{s~N6?9pfk9-l;T_TX-%Jb)93ba#f})IpjYW!? zfk6-y!yr33K`8=EFtD*`gJeLl3~~V{NC}u=U}JHG$$;Dg7KG`EXJ%j!0x4xfsLiU1ttn|88`|U*jQ#VGcX9BW@2DqTn=&oC`#Bt{+e?I6b^czU|0!}5M>2% zHiA^BgH>3tFffR9gS2i0S<4tCt^i7Sn<2^>7$kTY7#NmuFfholFfd3m)<>~|qJ@D$ zN{E4hVI4CAgOmgV1H(oR1_mim!q~&Xz`!6J2ePCEu@?Aa+)WK@5ylAafEy=GZbY zFxstV3}S91_mZh28Mb`Mrc%l4HJC`a#fr-fJ;$Amfk6h86Zts7(F#p145D{I zArk|tryvRoKngc7Ffd4>DwHz>SvwM11KyHfV8WCY@d_M z&cGm}#K6Gd3ef@az9eHbj1j}k#UKEVe@VtTMh{8Gc&H3hApjAKh^zt`(iz9ZzyQ&sx`%;*0fZSfRY8FV z!i-v~?4XJllufl&Js21mK$x>ft&)j>0fgCBFsa>QWnchdwwKImJDC_5K$uODO$`*T zAj~$ERV{>-fguD`{;(;tskX2)Fn}=2IaM_l1_lsjIj=f_fq?;p8O>ESm>3v9n9)L& znT>$~gc&W>jM*6&K$x|PQEdV%0|N-N&Sg@yWMNN^Go1`uY{<5pe5!N35*+`pz5E|XQ5E)ZEPF@3|AEc5Al?M*zBC7#H$2s1MCO~3y^ zRaDY~n}I=4lu=#MQ}q0UV3L^VB*DNS)!D?z0Fq!}kY;6I=71Q+ zBtCtib)hILx2G_Z_;ka63YL?-pQ=qasB@8+{&$DGg0h+(gT17UWF8;bdQf`@6v?0} zg^9snK8O~de!f*tb~=BpqR{jM!5l2p7qThKPELO2#F#UE!8|<$0Z`%94@yl8K_F`4 z^g=#9h3SqGjiJ-eRR$z#l{>sBzX8MMO1stxRsuPqzL4_wMXMrjN zSQP`SAYes0tiT4j7o;9mRxX(={!&>HRBV7u0;N?D4a(3U8e}Jk=9=!%;3DpcZlNZ$ zSr2N>f-H=LHuXW4fp9GY0|UsyiO_xlsDuNRy_+UWzmzv7Xer2MC|=9Lz`(?iGriEE zHh6QvtB;Igsl^5H#g)Y+skwR?46Fzf%&GZ?4euUD4l zp34YQ2r`Rz`h*QOqSGU8aq$TrfQd4*fHg`@pIGfCF}=CpO_1p#j!(0<~Ki;SOzM0yzt0C#V6#I9-vGQD%BN zC!@gR5Ay7ax%nxn@g)rLxuqqk74gYMsfi`244}{`N=;0O&rM98{P4TnWF-Zm$p=2M zbEG7eBr-S#cuuaDSFnuF%quC5&(C8>DoM$W&o9o5Pb1>K!Ecg*exbe$A&JG=9*KD=Ibe5W=9Q!t6_pm0#HVBy zCnn{jGUVjvr7M7m%)AnY_~O*uf{dd0lEmy(29V$SO zFkm_eWVS{8Wd3hTBFK6?U3^?YVKe>U6It=e4nJ5Xt0{<07W^VRebOIUA^U=|fW)H2 zT!a(iOBm8~@{Vk!2CTE9K7J$N`BCs^IG}Rd#9loHbnauw~ydL3}qSWG& z{32-JfWpNou{af~7aSeQ`FSNp`8heMMe)VS8L26yIjImoC#R*y=Oz|sGe82#BEE#7 zq9i^8905fPU~A#Ak(XbRnN}H}kzZUAU!0mZ`PVld6_A&G9i8LDJ>5LxgZ9t=okPF7S9 zX3osZoF3SnD>*&4O_npQAit=@H#8zXBr?Di;Q&w|mSrSoLVTN?n3I!~n4HZ3ifnK~ zg7^fQLojT03SlVD$S*2U02u>z-}Hk&xkM&&eCC_nB`-RCW1q5|CfJXl1ji6xl31J_ zUzwSjlLAU$#zyfa5YM`#=A@RSPFLh$lu(NYXTj98(&AK5Mr4S0%FoY%`x6rWA&%1* zI;)6HpTxl^GCAp+!sLVBjagGtK_1?C)=z{V6kD)F?d0P+d7ixHWc~M?lbgQDO_um3 zYz9iRVCSNH43av)4ofPDM@mf~mrqXkEY1Q-MAHKw%SsBxgHkY9X?$^NNqlB;(d3#> zDk3mHxmIMBz~XQEM<*^jL6CZAE{7!K$&Oz|6ku5!S_na$1nRagirij<2> z5=%;p<4eE=RY68&d{J6F*wYY^)S{yJ=?euFo2DCh$#YEieOt^io&UQj$Fx<<0@EE< zGjmK|v6@+6x&UJdn9DLfW;X}Nv}J-k(|a~Bt4t3N=jNHdU?Vfn^b6}1d8W_V!yz$U zVM~F*^n}(}k?979nFXdVn64qnp#d3z5}o|!r+Xr(%?_#e$%wXcMS`?%nRJp;#L6sce^o`Lx%F{21x{FNz<1246y+NE?WxBy^4W8)* z2RT@#cWh!-nBH)XS!Mc#vm88=<^S+Zw-Kr5nLblFjc2;9ZKK5W99wsu>1!PuMW%mH zj24)F;03eI^q$UGp6RphR*FpLwQCfZzJa-fXL`eCL5}G}x zVh#4moc}FYGm8>)4JY^hmjb2g&6)qx8K*vGd^`OdBV!aJ`*cPoEm3_*1{sjU85kH0 zz|9Rk1~n)jG>pc`V8j6Gnu3Ht4FIO;jv~Us^#LG0wCBdeAk6^k!onIMAbuINZ2)SN zfcTxzp+FcP)Ng_{PC)XT7$C!ikYJW(0CfNn!7j}J>P~>HggD7Sis1{iQ32|efD8Z) zBtgPGkV#8?dI67)9kU99#Po&CjQafg(4Gp2Vq`F$zS}x5e!3kCqrvolPb-DCPdKJ- zz{u!0J+RVHe)^w@6#~=OTn-nQuJBMyVHz8wz;q2meF4V%(wB3 zq+=+=Aj{wi<%3)ZN>~|CK8P*EAkWY=eIgs9I48)hLJW!wd!`qfIf{FNT0lY!Dh!}; zLy%4o2I=4iHA5K~KqIIOLJVpQDo{R5-T=x6HPeI`G#EUmGcJ*nR|E~?fRunR$e1pu zGEgf{h(U{C$@IV_a`J-bpu(U|kPw3o!|Um>$@cP${L?S8Gm1_Y_#rl(iv#3m4o21O zQ5=lcjN2D*GNv<54|*&sv0aUuQIv7|3>jfwMwRL3SenGA&)m$%Gu_iEP*@0*iWouN zPEZ#al#-OD=k3-IpFUHvM0omx_z>3VmNv55(|ep9d8Rw;Rpptkvea5|Iw!vt4-2Sm zJl*lTgb1%P$n^{ip#CnS7D-+c^HGH z_x+Vsp6>Zwg2y%tVgOiKID`!%8KK%io)^&ri7+rofrg~@Afv^gfk_d)>3oS|;sSaQ z`$2Bt2K5T2clw1%*Mr82KsrIG9K`0fgO~yu!w}JD0B54*AQSZ&7(kYR#=bz}AXOkX zw>^l(zyQ(<5(lMZ5Sts+KVV>BFo)^|xg5mi1~sc07#RE^;`QJ#0dZgwNe~GJP+Wu9 z+)fY+K;tVQ3qTG9vALZg;_XoNprJAln;X<-XJBBM1r=9-vbkL$>Q_Ol&5Kw&Ql6$kkbBqt)pzyL~KpmYXO1M(k;&FzQeEKpYoG-3BJOcx$-vzc`o`C_BltEfW%ph(DvALmn034X|3=E(!0Yy4U4af`- zn;V)pz;S6lJ#K-oIAhdwzI0LL>7I*xd8Xf75GgU8*WHC@`riB^;pqY0Vyx45iYW_KSLH>R&%?;T z08#;}Mg(E(>506-3e#03j8&#D*OWuLtF7nC|sR(z}q@N0HbUkl1gK z*x!-ZGN3Uqs1J0J*cM1^&{P?tE<-)o&wfY}(MaqZBz6%Jy8?+_hr|X=(ZM`39Z7sH z5_>TcdlhKt5T@ZElEiT&_E{wMWhC}3B=%Dz_D3Z4UnI5)Xsi$#D*7-s$p6+b4g&*& zI}$qti5-u`&PHOFBe9#2*!@WC*+}f=NbJo_3=H)!-|t6~08iRLU3wi!{4o;yJra98 zXdn}+ekX_xswEj181{l@fS~LXAaSUgs|a>I!)*`;R3S1jFx&@efU;kK#Gx8MvxqQ< zGJ-~NKt&z{Xw;j5ff1@+93-v?PEHK6AU0GSG!6<=qmLvG8rx*l1%*EY1A{Y20#t^A zqJRaG?LkJxfW)DeC4$&cHRT{S)Nzd5dyKH;$o~2&wxr-MUXgDjW&p_ z$pFcJ1|SYp!WP7aYK{Z3q2d`JHdH(ZYAC2^22aR9#oIw@pz0@r*iiAQQ1zgKdI3lr zs%8~v=$aAgoApQ%dq8Zc=F1>9RKr~m8!G+~YAC3L{{|9=n)4gPhN|ZP&09d#%Y)cZ zaa9l-EMCvRpveXaB2YzO0+(Q5a0IbI4GhruJctd|><40lH8U^-LG^;F2+;ICBUC&K zqz03{^)Lei1E?`1To2`RAxTUDv7s7ff!NS-*m)q!pzM_(aj2TZAU0I| z9*7MUe*$8IDt873h8G~cQ1)k#I8;qN187hYDj@@6LnV|zY*34sfq_Adoq<6Z$~Ht2 zw*#@E*~}fp1~t(b7#I>kY-r0p55$I=Sps5%nrI9R3>6?VWgzK~p&3b{7sQ5Ym=0ot z2E7>=7-oYsK-tSc;!rgkKx}B-??+-E0kNU#&mys}A+evc*E2A{3YL!`2~Z21fq~&G z$TBD!)Wv|Q;Q~#QHwO8`P*~U|{g(U|5 zC=SF1&0;YyFeHQ6Q1N^a8`Mr@U|=W#v7zD(AT~6pTS087_(TvJngFMP*ii9BAU3p= zT+YG35D4?xYLEm}(IzA|XjuqM&0Zw&gGlTXNbEDyd(YG>^WH}idOUsanR?~=??^(w zk=V?fh&W(JV)G-hg^}2xIaipA9yrG z;*xDhIzSWbFzJcY1x1y_B|%+Um=I`T5sbZQx}&I)IOB=wf}NG(^_P(h0S(nKLNnq^ zkT{eLS}6t-2Q|iF?0-mVm_Y3(sCrH$HZKxe9ElB@h-H*z05z2v7?hACz%%ergTO0x zpllN)HP%RM`{`>{8LjK{K|-Jq2F*(&v8#~S;07pEO$U;A4-$Ja5*yqwg{ohOB)$}h zy#~StjY2RmY?wY%u2|XeC`1gLbWb9&LG#^=Q1k91i9bVPzXGwRH_k8=p3b7dXgXc; zp)>dN37_S7r)Rpl@H2``cRVK`&ZslJu}nmq(PjF@sgmN1G1CSAN{AbRk_f1S42x(` ze-zX!0@b?_ps0eTC{SYnBtB*OMlK)F>O93B}MrccO0;pvQt(Cy7TBrjP zKn+T0bz2K!L#xawAU3oHTn%DFYdUa?6KxV91~t?Cplr}sTL?1)Lp{g>P#Y`)Dgi2`vO#QU zd>2C5px`QnvN;(T7&<^~Q1CD?F!Vs#AT{$rY*6?!Ffc5JvO(h8Kx}CG*aKyQ>}NOt z<$y*}FN4_7gmV+h25G(vWrN0qK7iQJ1oaKd2C4Z2WrL!biG_gyH02Lc4_b%{VuPZU z4=N6_LIljNhYT@FfjJBepz$RIC>u0x1nL5TG=m0ybfDta3=9lLP&Q})3$)}8qy{vA zWd{`pjWszz*`UfJ6vPIlLxllGJ7K)*4P^eZy z*`Sd%m|jrA1a+T4=73sQ-B2~45v_?(Hpl~0p={8Y=n4>90kU3>^J1g0zpLt)w zGkwY##mMP*b3zR~LGET?VAudEJ)!J9NbD0JHZ=8IL1I5ZV!r{gC8l?2$SHF`6OPPu zLp5RX>1Q=j)#^1 zpj^%lLpNcz}TRC24jQr7Nf#+uI)0)iqOVk1*pV>HXuREI~k#k z%n8iX<=zUoO+S;NuEP1o7_xN9bNazHDf#IimWr@UzY?k>GF^aGMS#=9gn^-jfq}tu z`p0g0`DyP2Sf(#oDk3ud!Omg<&K)L@QFYJhiS1JI(*xoPpt3b)i~?LoV6qI;<4*I- zP48GIDKXu_(Nuu*0!(JQ;lnWb=>Z^9RaS_IOqVfd6yUsL!oXkyw$jv`QJ!(mbjEiA z;?r|LQWB<+OyW8HB1ogcYBQGUQ{D@ROy6V9D8OrD3f0KKz`#HKB2TmQ^a<|;Sf+2N z3lN$9;4h~DZv{+0XqIdG#iL%*(^YijB&Nq$FbZ(aF@^c&;G;14=?6fD`$#$SOuxX$ z$T5A51*5=p4=HB>2zSE1VwUMQEEstZVvOsiZ(MCAJl&*5T4cINoVWlhXwjtlbU{l- z;pq!z6bXV{UjgzMXmKKVX%NK1x6>DPN(nP=0;`mK!3Y`k1!ZVZEu>(^zyNAyc~0MI z$tceXO2@olmDAr?G74}Cm@_bdvZLp8Rx3t%#skv@*NKQvx3OXr;MIUhF)%R5Pv6Mb zEIoa}CM%ZdC2N#LruSGe3UE5WR7_uL#VF4TO7pza3m1wBPrqZuC@}p4NcA5UE|KXK zp9BOrBg`2X5sE^EywKV9IE3=5<9^oMEjBGYRFc=0hlG`8g+8KxPX)r}Nq{%1{4rScZj> z3!>e{hEag?j|C*OJg3LnFv>HYn10bFN__f>?==FP9F~yvah}uHf~0;-KiDfJKK+Re zqX6R{2%EiQdt4r8I}wT zpw*b343JTG&>Rn_wg)#YKpLR<3JU|n)ai;UO2W2>L5s>6Ad?CpSqVD^hAUhQ3?L&w zBf~HwK#Qo6t`V%=A_b4(j1b|&UeaUGr0p0__3=FV*=Q4fb{a|6x;$N^KJW31JWw zLDeNQ2Rl~;0|V3dPzDAT5l|(|Gzm1(CJL%QnfSvQ7+4fR&3mTx(;uH^G-KR3UFr;D zJY&T4sxyq9jMm$aoMDV$WSll#_8emvqy6-fbBv};e^aNgKF8?7xN`c3bBxN25z|G^ zGX^tSPR}^cSj_lv`knKPCQRR>rVCwQRA%~>INkgLqcJ1T^y~|a%EEI(85r2awx=;L zu#2r$V_@JATQz;*1x9O0p(F+dVX-}lpfwpxeL)NiT%Pkm%e&`I|9XMZf{|sq-bF@t z!yRD^47_3$S_}+)V!h!E4E$o25ey6hVv)fN41!|H;tUKzVrj7;lQ^On7(~QwPhWPC zQJHbx^ivlZHEs1%7#Nhqii{Z;l*Ni185mT=(&HHzRK@x<85q>WKN@w~FGB$%NmkG2!TyU=o0|Qqc6G$C{AR8+K16KhPs9&rg zsIAPvz*WL@je&tdN$`0R0|Qqn({a$YBEb`B3=CXlOrRy(se+p33=CZ5U``qX*WMTg z2Cgcm>m2nA4E#)7bxiS`3=D!cG7Jn{^-Q3FR|dg!knRSs21W)hNdX21u0|%%Xo(~X zBUdZaD!7I=u-y!TiGBmCI$vB2Chm?1_rJ! zrfg0I1|Ak~kdOE|xK1&>1sNy<^80D9r3`}S?HCxi&VV_Lf)#=c3|wa+rZaHekziop zI>)q!lYv2k1=R82Vq{jG?s=6_x&9W&-5ksyU-L_Fi84>)Vqg&5!_UCLCC01@YMBeJ zuxDW45@((UswV}{gKU&w=3ruA;1IkGl96OKU}9k45$q6RVBnHsUc|`2ARwr!!@$5L z!wd>#5y9_z3=CYd%uAUV7{nO3bUhguxa64)xfmGudARD8m>*3BUZ4tNJJhm(QpkOu<;mm{+# zs5>da<;=X3n}LB3><$;ONqn2b7#O%*!C}j10dlk(*w=j58LSx?xZJ@G=Sxs$VBqoq zJA;91MLZ}sGZ%A%VjW~2*C&vOAnSE*1_mimZ2jk+u5z7GokyCLn+GbSIlb{Zqww^s z>x|qy%B-d^;RukhoS<4XC@ff0V8TrxVPXDUP{9mM6_%`LreC_ws8pX9%D})X=4%Wp zcxJnU3Z8>Ppn^v(jDdlZfoqu=$Um$gXKfMTMJHJF!y zfj@$)lNGeR1d=W5yP!t-MKLgNb+dvxBy57oAYb>ef=UZc!3bLh2CiOKP-)~N_zF}K z^nqO%AXp{Kz`)fHwj@wcQHp_qYXX=PBzPB;RPd>1FZi5}lz@=`) zz`%8f^){&Ze&Ef(!1a)|Q~+8ybP6yqh@9bJU=RVZ7SvxZ@aIvw0bNEYL1_mxc2>UlkTnx&85p?q*iH#B zFz~Z*8L{PnELq0Fz`$h;*3BR&3`(XZU=E|;4^U-e$_6SQm;@O?)v6ho!_2_dqs_p; zWzME2$iToa!)48OSdf81Ag3gofy;&s)cax(+?T+>z-7y}0$gp`iZC#6*|A*%Rgn@9 zOYFgxNC`@S3JV7?N1B0aFUT>DY@k|}UxLepjX{WkLGTZ#0(NBs6$uQ2J3uPjz?QH; zOmYWn7GdBz11{*<&Vw8!!sX58B?NPn4_G~eKz&MP83UIu8>s#ifLQGZ)-41v${)-T zX5hLGikbj69w7z>ehIE%wkdFTgh1RO05&NUY!cKRVPMT{5Eq7nZDeQQDguRD1X~!$ zB=LH#D7K3rS7jDuGjK(N)i4Nla4|4&#jwo;Z3Pyb1WGuuY@m`{kbz4aRFB26Ef8X0 z;FaM@U{e-mVBkBU!oa|l2o7_;gRTq=TuI|*Ks9c?7^uNGm+hknsAcB_YJtyV z`wsGq;3H6^&S(1zvPUqK5mZ~SF^e)VNC>V1l{!n`XAZT^Pjn26;jQ)O1+JmMa2kqJrAl3|w2-f~RLcU^L<03r?{zEZp()rmuRy zsAW1&lz~A`P?3RwJLNTKH8cmv$LmC)odRYC@ui^FGIu6Ol5LYO0|R%~YtiYP4;hu} zS;Rn#7H8is${K>$9Bd`73=G`Wpp4JMR;a_kz+J;A&cGnR zW|+vpz+DRx_hA$AVqoB|6P(WTh*389RWt(wcN56k5;l2|;msg+1p^ODGRUjFObiTy z;?R&`V&DLopa|phF);CgLZ>xPjDdlbgS#VAoPmL@dwR_yMp-own+2jF6Q+TYfoXvu z0|R%DjyMAYs{)U-UO0@xr1K~6IU2HuHa?Tmt*2@DLplfbG#1pvrvTt77#7Suz5K{4Six`!sdp~7V zh%AH3=F*6z!D(a=SqRvY(WeRyxSR9f^_Nd?qr-K&A=cyKb3)jcNe2AXl01tRVfAr z-rZmc7QrGHIm`0|W0~#(C19JnCs2!oa}0k8z1KsQbmM$H2h5AFNJ9 zkjb2Zf%gDdMnX`4lYxQvAXt-(ptJ`A1MeZmRniO$3W5*37#MgDGj5o^<{6`&iLw+Z z$u>xW$j@N%Fqpgy7Eb`VJqKjeamM=~w{!5`V3eB9_ngs4&q{)UfmP7mnSp`#E~Bdi zsBOPcl!1Zw9%GCI0|Pq)*9Kk&2HyLOhd||B`}Dl$jP8uy)3-fmbg%CQ#dHn07tAlj zTgT)l%fKLb)DBc2G9`gV{RQ8%gHjJuo(!lxG0T{Nfwz&VN(NMZ34lVQiK$HnWZ@o= zUz))jc0n&w1_s_1rb#lOK(kb1VBl?Kng=TF1kHIE74}@UCK-BFn(Q*Dl7uz`Gjka=s2w zOsrvg2wI{o0WxMS(*@9Q8CN1GN33H?lVxDwSK!^ibPwdcEKvMz1hebGd-xf6H!*=S zEsNkIHUNa=bN)aPaa+0A7F^50gb1t4QNc(*fw_G}9Z zfU?03uqzn^+rk+bcy}^^swfr)E&*`zV)_PBFTlHpsZfrAL2#291A{p4Ua$`sAiDQ~ zbu$T0nLhC)qaK%<9H_(2dyHxK^ph_c-f~u7#Mgjf}O+n#fgD|_Y&ADK4VJ;2Hwj|uR!5;KAC}m_X>o452W`h({9iN z7uPQZ1_s`1OvmLwLpPvSg&eaas7~Sp1+D_KtvmyRu!lSYgOmt}WZ+>@1=ZgtQy3U{ zEy3M#uBFo#y<#-hm?zJ`AOi9^m|);41jTtU^D22z%H9An<^V{A+VsD#7!4Vdrt80E z6cv9F%D}*P1vFs6q$S3{!1n@FiZP{3kABT4tK_M`z#!%Un&%S>O=4hR6w3vrMh1R1 zJ^{vD(8QYG^jWVN6G8D}dnFz|soGkg+^peljyy8#0OpCni@1J^<>1_nMU z#!3ayuo#~#!wUdSVeYH(_AlQwE#H%E0vu)UZ)!Tn^Hv z!KcaCrO3b_m=eUmz^4T*Zx*C5F!1R!?&bhx4^Alt20lZuDjq>lcb3lxtV}>~#qxy@^ykWLCRCUF2?K1u=13zoAK`So9`I)(kzrf z=?xTqJS<u2Nv4Si%pGcfQ?Wc;nnz#z<~!oVN`N~8>2 zLZCt1$zWlw`=I=sG?3J);8Stm%F48CBD?R6r4*Aj!bMw~0|m z1y(BaZDy2H0Tq&zH2qflYa^QjyQZDkzBbAGM3QT`g zVC5p8B3O$I0}l(xY%XbI1_nMQrYMkk9DFKF=RoFxN<=xAkr~u@%hp<5fAfE$MK4|M8*IhjZ z20llo>gh6{75zfHCSH$#Jje$XunUSxQ2{e8P9=_r$2ao$Q z2>MO0|HPTI%pd_`53Dkk*GGJj~;9JcE>W^}L zl3-xqTf+qEP;zl4Ffj0~WdijGd1d(4GqGtvdv|;rm@3p682Fq(U6qYYEg&|icgMGh zX$6Q4>fP}fZf2SQ;()q$d|R02fY|du8G0*N5d+s&cLoN&ZA@F#85sBt`1UY4O^^G` zXv8Qqed1?EWv(uH1_u8Bd>5FeP2cyKQH`re15^+3U1hpF{oQ9q2{q6N0vot5$ajMY z)Jf!E;QH>yz`%EtX^{p4gQO@U-yNpZ={jE+Lm8(`Z~DS$$bBCq&dkX7ifQBYeP0+= z!%oXHF#MMX4KeY(X9AUu42%q1>y;Q7_&zcfYBDhJv-5pndZ-BmRc3tv#Ud}sPA z4<7xBOJ!i-`^mHyq@I)S50mzE%dd=bG2Jl?41E8=vk&Zoejpu;%pe^c3|x2FL79a4 zEl3AD9~*PD7R&~AW>7`JAP5?C=7WsRvoUa0fYJmfv$+;%7J`q5xqJHNuZ(Jr>7Y*O zj5tu8!VDUN;R0=f;8SM?jh=FOcr!5Y*)W5~RV4)&`Rth;wPBVxLM`!|F7=Jk#%i$^ z0|O_cJZQv{&z%{><6@Kt4O#MeFi+QFVBlty2aQ?sd4lD57#X-4K{bpQ^X};rzA=ip z)WQu8hZ+nT9psB(_SFW54`@{kUnFy+HUons2P0n$^GUddIH(4{=`X%9>dSV5lrS;! zr82YYz#N+nS7P#=QL+B2HUk4cBVR7F7DxqXK|Nm{Gc;#tfFdrRSy+dGK~aK{uZWpf zmw|!r0}}%SUokT%C-Eh@GBEI!FoSXoUk9lAC}mF71Qk-Ca6DwwrFc?C43z*k?%+zsM@hV=NVz+nm=S>US%`wBc-$5#V(KA)#H0|Q?z*rDLz zJ-#|-P*CxKZLbGMIv*Fvum@P^B$1WYamr%JHV=Pb)DgLSPrN{TE+Ybr0hFf8In0Qpu%J;c*2M4 z4k*9ugs?rPhyMi6OIH76RIh)m2kjg19b*O=!yx!Vhk=3bI5V>ztZ%?~f|(z*HB}JQ zH{d(TEUgEs_CS3DzEfZhq;J4?nps^B)BphW4fxJ58-u2+zfk81HSn4%-(w7zCjcydM_}CgLKJCGcfSo28SHK1m6SZDf+PF`w*6VqZklwIiS%Z=;^KU(Ha{tV{9c1EqaRvsy zFJNmJ7`T!^3HvMa0)241>Id@|kP>in^C#5O?G_9Se80fz*#yCPz`)1Eat*Xnicwwx)MjB} z0kyAL809yB@(n8sC=qcm$~%HmC>smtU@;y>c?VFcW(Ug&Fv?5vGBEIQfc1$m%7dN6 z#R5tL5{wL78iEWAeB3My2K5XKk|K#``agXgtCZFZI@P;-jOs-A&? z&wwQj#8Cv50ER3@AofjA>1D)H2V#TPyz*JHfU+7FXqOkC1EeR^X$7j5S+0O=y$`Y# zl1Dp0tvMH#*C1hjBL)U=)`g50f{YLW4WWQLN?^CuGjO$oda)iX(xBt~3_uz{Z9j-E zP;@bHO#&64J}jV?Dp$Wf0|Q?Wiw8(?Fi0_oVBlfd1Day;2lYTgSW-cfogm2ukh6L~ z#0(Iz1Vn5A5fFpToEXd*`05~Dt72nd;NxKh4P0?O0C`OcJSznr_uFU0z@P+L3=q!5 zz$(gbdf#Ze%0EUWEs!|Vf@B5;{w$E+nDSB?82G1vnLj~e7Sq&ZK!aZVTXd!u{9{zE z=Qd_wU^4e(VBkLi3IZD3=Hg57IdtqBv^ux zfdk|gP|uRP9u$O}3|uDu3=I5Ij7%mB42msG{4$Jbpnj()sMRIQ2vW%hTCmSA$EX9^ zht8F60&27~I)f+=ekI0JAp43zCxI$6f`SpUOoCqp>~tnUa0sa~f`W)y5F7+*j394I z3fBJ-W?ZS|~f?%t3kgd{1 zwn`7#Dt)lwl7e8H48R;c2Ci06lp8YEgVsUvv+x@;hQrM@K{nSEVlD&MWgP|veltd6 zQ_!d-zXfAET)ic-dMlXv8Y2b$G8vZ|o?w+FkGiGl0969WUk z1LI_n1~z^t#xHOU&QJ}Yr6>F@5DNryOG+8|UBNOe3|!`*g)nZ6he4Y8_&pdS%wWmK z6RaK@WL{wPOpvtX4LZ=Hmyt=r8&ocFLrnAotKeba`eeqy!0*op+GNeo#~;YJ9&Ta~ zvWdZ9^-vQ-7#XI2U}Tb%G&cq&ofrcYsFQWMiN2er-l3mKct z85kg5DPm-peu0Tesy@z~fkANz6Mq?_BdGcVhgdn-y?o9x3=I60;CSQv0BU?!f#ZZv zNtuCxzZ#t3_;!M_at%22_;!QlplZSX=KBv?>{`bNT2jkb0vbZA2d6{6b@mJl{0-o= z!*^Yufgyswkx|Ki0)`fF-10pIb$wbHgFx%cxITks z!P^-7%t0dtAh(Nxm+S}_{k3FZP>!B{keSKA0d&wYJEQVGIne36%BtR=rn|BcXe|$; za;pufv9A0tl!1YVQ8`wcfq|D%`9~N710SQZ2PhsGmCsH$WMPtKd_CQlg-J25ClRR(S>n8Aj!l={+n=28>Il?`2`?W^9=5$;u?76kx@`pll6V z-OQv68pmd2QeJDvz`(?$d_EX-IJC0k^mbMzU6Vp91_t(wlp+R!rJ!9w3~ZBv85jhX zfrL3gb)_x?15<4r1B1YFkclcxi~_5cOn<@3q+H)*#lXPIC$QlQ+=Pt~6MA_V7z8#w zmuFz$VA~0r8QJ^^R1dO&dd&h`K&3kmTY5SJgTPi0o0owp+Kz!iVB2~t1_o$2?vS%) zU=aHZTE!{m1Dnt^F;A_IfKUXV6c78QX5ZPWYMn8YGL<8d5ppk|N2VNk0_ zgzdB|1B1YkHfsh33ARtX3=9HCK_<$uiH0#S2pk9Lmt_M@H3*z|D9^y402-V$WME*r z0&>VHO=|`QRuh4^V)`|Z=`!H$P69VT#lHdrQ@=0+gTT${AUk9P?!-*5VP{fejF~>4ok?5p7ATEc%A17N_eE$W<76VhRI|GBjKV48B5D;Kwted`> zgGoo|Lo5S>04t*}NLWaKgYl~E^p6}&Dn_7gCLeeOfdCKVdQdkPyn;Z0ml4z*6=2|+ ztHi({z{l7H(r6$c$fz;hos-GQSvrA%K|q}Gp)CW0qza>e6k{YPticISni1?0aI;rH zh7r^h2Qo*N(Zmj-L4mPr`Wa3p2??mQ9VlTbGp5=xFz|B;s59=G{)dxEje8n| zugmz#Zn`cPlPcFSkbs1MF=Ny87%nCWJzoe7wOIb4E2L8-+8 zJX*>v7(0Ct7n29~H;@@30?v##?Wcd`Vp3rYo-W1Bq|Vg`Do_Lj{20Zidvi0XN`cx; zd<1v#5U65I1sQH2P|L{R#K0ghU5A%RQ57^CB>-L;AkfH|qYgUfn=8qIfkB{|@eoM4 zfIusw*YqM@CI>DaQ1K@s(91Yw`W{{;2ktNsUqE0A<3*?G?0ifr^?smsHUrli76t}^ z8H@`c(z6-)oMB#>1NF)tPX-2oxr|X7pq}F{kn87xRe|Pv(=-?uxH3f<7zE}s-US&U zCa{RH0&c`&s1fR*l5Yvvn;e4rpptRv^i_OJB8<7y_wz9+$|!)Ec>)4!7`MW;u7zox z{)dlAk-G(?f=ggC<5TD98vIPEng>AwG6FjpJzZc9-UZbHYBUP$1~(cx1S6)G@iQs7 z=u0p#hzR~nVPFv0&j^|+kznAO?8d+#aDee6#H2%v$KfU&MmFgP+@xFlObUTelR_96 z1Wtexm8f8{2LpouWE5EpV#g_%9gVsS3<9SaLtQ{ac>?DdSwJN!IHg>G+7U6`TYyQC z>oQ1%h`=?*=;>twOh%cYGK@#C0#v@=W{d{uV&Gu`^-H)K^%)oh?l20tGBEH92;5_w z2a*IEc^_&dsPYwf01fWHps;@kZe;K=aA^fGFbF(i%!O!v#(3Lxx}YGF5!Wh+z*|Pu z>Ar$YMiQVIJ01qE4H66t0-qS4gJdNHzA|o@K3$N>qW&ky_rDlH>tlEYLF4WMzrn-v zeBjwofj{8cP=3Kfpq%%Y5oDHtU;`-H|1oZG1FhlaVF8WxbL|FAI{arebYo!P7ZKoO z0v&+_$wypFkiraH195{TI0WyjGcXA7FnyWsC&a{~!UigE8F*OSbwSOCS)k#3Z2?fB z$#e*0o`8S=ljrn0AtqG`kV+l~uKURh3<4rd67FEz#F!RL-z~&sq%%hmGz|ipITVm) zS^zclF=%cgnuCEsK!zz4q=8F7j_I2FbV*?*Rjy4S0TBUZCWYx9!c3~#AWb}ieW?r# z0_sc(pv1ty!}1yHpGR;eD4Oe;)_@Fygl+>kv_u$qa=Cztybh*)ARQV4T};K(OT?K}>p^bd6pXN7U=ZkI z0*z^M3C@mTU=ZjBPkhM;sPg3X->Hdlp#hXphq%k>kKASN;K`7kgj zIxq@MV+!$SV2}oOiH#44B+Lf0&AH-jY7WEa0Ui}bxd_2@l-Vi27&cVS8YLer0_&CFbHg5(g2M^ zP64&bHZg%3Z+wqH&EPFeT_ADLaGk(5rd=SmeiQ?Pzz(KYAhuI91B1XWrY6v^lP;*m zvxn&>i2WHPzK=-^GywS!)Z{wAlmv3z1yH;nVu}QL?3^a35ns==4aC_BDmjibf!Y*& z2SCZ}1e2E&0|Q?iNb^aiDIoS+Qw9csQ%n~@Y!Oh_In5*jnl1nx)FW_)2~@rFJ+xdCQwDprwSS>KFnph80sm4!Xs}TKjsB={AU625LCpXW{`( z$;|}yhaNC_g4ph$lI$VVG7wt|RGL0wx&~r{+vQJ~7(5vm_^kLC7zCbz3s1g7pcMTK zT!8UiRAFEccn&W7_*SwqFbKS0QuJbA;0rZp@MaKr$rKLaG=a+NH%tpb>_ABd27$NW za)N;iG@l^wo~aeIs9FZpQuz)k`%42s!|&ihZGH&>4rcA?_oSFq`4T`I-~>5A&gEg2 zn=UBLBx#!C&%nSfXbY-P_?bbiQXawEpyET2IT%#%3u=Rk0AXfO3tLdoI2lwQGIvgo zmu4~%s{oCLtr1XQ&In*&5Znh!xr)pg(^pC}DJW?NFfddEK-83 zfs_{r*fJLdGB60*f|8CKn9U&AIDL`~lWTnwOcN6W*J)6R<;N@)2N1NCeN;oDoc! zUL(sS$vAWRG+8EN4se#tV4gGmqAZiGiUFwgl?!&BAd5V>yPgN;39-nRfeOle=AP+B za!huNjMEF{n3R}4s!g9N$D~-#14;n3%%F42LRjQMTf+qEm_aLCN?7DKf*Ps~%xi)f z7;0GL!Li*2j%^uM`3g{J(hkWjQXG-(~RhIFL^0lCXcsbaP z1V(vqqkSbaXrwoVQ64S&B@e zY^h-kprr_{icF4zwxEvx6|gFPW`Uc`3#VUKWHL%A3_TaQjBv}g)=bdgQl$*SMY*&On{DR1{<`Rmv{OHB_@T4X3#OB z3~>w$42*NKA{ZF7BV8F77@Gw^PGtw z3BX)s2(lM6q$NK+LzziN+8_et$Y`+pj6r9|?mNxEU;;W%=H&E7Una5X2}@lCB*6E< zm==dHFfhjPgZ6nn0z0R1`dwuv_j=Gg3+OZuGf+>QF_9lsGCl*HGLp%_n8XiqC&&@z zpv`Nb**=g97}NMwA{iJg&V?~B1T!))SR4ssV3@?nz+eeeVRa*nfdO=n83TjyUIqpR zkh=^)8}m<|W?;yO1i3nj(NK>unss`N9uwE}wJJaFi?q17omuYZwCq<3iyukX(p9Xpoq3p)e>$ zL8nt{gBo0ni-c7q7#JAC42nw_7?%ixLXC}yfx#GbrZ3ocpmPF2uGkj^^4;`MJto2F zUsaicq&4Fi7#Jt=vVc$5fE>KbI7cg*fx+y>^dvPVWtl6WK(=}7&%nUAg%iXE#S!TE z2gW(-(-*2Si7@(2-=@ao7XwQMW^c6^7#Mee)h=RUU@(6d25K^cHdZn)Fz(^}7R|t5 z!5YrM@Pvth!Qyuq0|P%Z1A`@K*Ei@a4lDj}1_sc<6$}i9pre-`oCaNamY~jL$vA!b zEOjQ8dao1)hUKxai+JonaSz+T&Zxw@Cg8-i>D1*S;s^gul((dn@oOfvl7 zUzC`=R8ehV9*Ec>11RSSSG;0 z06Lx0A*ntk5u_AUlI&(-V9*Ekml+uaK>I*aSQ!``!3m040FA4 zQ1Sqsp=bw+OVGY~PyxiKAP^Y`jmz_F(6|KMn`jS`1;?W*JNPI{ur|=4ETH}SjJg8- zFm2B4P;H>&1nohxU~MzOoBF}JR2U&gkuX{d9EIuH4%79Boq@p~RI-3|@q&^N16UX6 zVkywE6pRi6zw2Szv^k)bg>f)2*n_0O+8PnsKFbe*?gF;Qy^U+S+K6J z2wk89yuep6`3ivcorBXh=wLf=+P32iW?--fNrSb4&W>Y%xbX)g0 zfdP~RO%ouAvq76lDiM^4Jrf{_s+fVna3uo+11MvqK*X3Q9;?-3jA7#V!QgZPv^&3u zp%x;;=m4u>4Bs*^Fo4XN2$2C@$!7Q$YR;PJzqOeprH?|S7#(4noIDvB7?_F}?j=mu z*I^Q`{|;5)3{zk{m63q~R00|p7-VJc<-Nfk{$s>8(Z3GzfUT!O*SfeB*sJct-lU>K$_F)*mdFfeR_ zNP+zfIu6X{3d5<%C3=DUZz+nt7bfCAzfl41k24m3WY~Yd% zRKkOjk;wD_Jtj?7P+~EiUZ=;TXS6knfq`)u+`o@Nr;E%1^|v5J&oVC122OKsSV^;t zt8@B2Jtld$x6QiU7#J8=ae)?qJ>-UF2GE6L;E=n;^*R|E3XmB<^!OOs4uffQ`0M^9_IwT8X*8wI51_zL? zdI9dkFl`EaP|Lje7#Qq9(qL_62yGh73=E(f>lh`uK||l*GG!`E*8z|&kSti&Pp~e~ z@F1ii13F|26mw>&;7EovWSAMI$LTR~Om8w^l4K1z13GejfdP{uq{!%i78$crAw|Yh z112e{_%jR)>mWvelRfCbZx2wiPn|Al2&?ZvjsV%ko;Ka^x~tgq^{ZWZxETy*Li4i5 z^g=@>8AFgZuQaf0AUP3og&s7?DKJ4>U?xnElB*HPu;~vBnb^RoZxP5WaaE^2CUA+e z2Wnm^IA>2hP|IKlssyvnFfhDKo33ueqz<;0I~|v`pfi5JDP4^jVy#m;iXTA73W8F7 z^7J)EO!E3Q5Q7+PKm`fdx<+OOhSD<(3=<$S;6MVMIS6V2ZC+93nMAliE-<+Rasi}CoNCOZu4|hK%RFy6LCs4Eeg+0JaC7rLCrGY^ zp8;A^f8gYuzSEdVz8;jB_ynMt3Dkrs0HwKaoZB*>*&of*k;lf}DItp;>X*mW4?o4n{3_=oCFr1<8;Ft{^!<^XDK3C{E8ZWs+evIK#l;IKA7H zNlrW}3+!4(V_3|XfO>Q4(+`+3DT;~az+C7Db|JSAxbXgN%H#wu#awJNKuvWnkXjdT zn=2SxB-%P?Gcai9z+0!F1{3H&;02)gh~=`&hI(YD5Y!`2gcum?L9$?v@Pj)BhA@xB zXM>#y>QR82rv`e{52P@0Og~`8#KH>lSi|&_W=t|*=KSfe%$TIWe%wEu)0|08;RZxA z!jIr{?Q z*_p#&4(Sl+3PZyrLYRTU9wZG8lV)(37=up90y*9gbUG=h(D|MNDXyF>n54i#AUHkI zf=Luorh(c{AVnUz5Jj^rn1mrRcR+qW&A`x~JDm~K3%z8)qy&-q1C==s)gxiaB%=v# zoPcgP02KzGbD{CE4AMCH&R`hA$iM)K3gPLomQ031Aa8>MP@F*n6jU0T(-&AWiPqQU z!}4?__fc*JhK0fm3}#C~y{c$#ker$bw5MbOx^Vk>P~`qjM?08VLI1Ab=EW71ZjmS0c&Le?pQSkLr@*weTIRdBp)20 zj2;Zepm>=E>Ll>6fJV!;euH|{po@uNz0#}s3=G;6LqWZ6@D^dlAV>hdiZL)4 zf~rE0v8SQNS}_=dGT*c_pq-gKET9p2t*M~%z`uigfuQa&;~c%|e%4HqR#QV67!*K; zfErdHLsSaDZe!+hU}P``ZFm8@PU~eH0|VnKaDVwXD4yn|OcU!GxLa4rUEhz50zW0<+VFftf| zawkY%7+5BX(U8FebQ##)Gt>9lF-bEK~P$*3JGVPMb> zvS46f{4M&MXbDP>^L z0j-T?j1mD2?=nqvFa(|C#&8yN&I8E*QA`tE^cbU=INCvtB?kr*P#2kddVvFzn(o_j z1_sDzkT|0>D+9xQNd^WT(EcDsNk-7xeddW1>dgW{LwHh*h0_l^FzIQ7_GmCqTv87% zk^h#%3TR`{0j6MIgKl*KMeO@hh#xYxxQb1GP|w6UJ;0HPJ(;Zx>?lSraAm~c1S*M{ ziWp>}!k{5DPz;0G1fXiz79tMmWnYd%feE?5=I8YZ43+yAeqHTGE5w)42Gb{Qaa1Pumda+1@bwAA?WOJy|WAqw_$>l z>%o=%lzKhJ7*HrM7_x#!1j85m}qWnkEVDi3P#fYPAx97af^*<>9f0|Rt8)y|noq#hKj z;QB|HK?9URv_Mz*F=m5P9q3*^#yRd43=G2@+bjYq zSwXWK;C2B>CnN~L4S_=p3=E*H=Zq&sE>%Elo^B~<&9hC4fx#Xm3$8jIf|4nuR~5;~ zzyLZFmGP+vM39Ld-H&hqe?9T^Jb{Ky}GKsM-<+1{08vK;<4N1#)pRfs!cK3uXprD{Pf0 z0|TQXxatI5QpPwZ7Zm>B@dd?tQP2QGsWbxvcmN(WvKUhZ@=7%GXT~5M(R=y4USXj{YsDca0hKqJmec|bA?r5PBEL8DOXL8%jz z5O$wsU^oV{M;$s3!3wSt84N*HEhy}6f+QKE7_AsUyOkKGO}BSrlHomB&A^}!E3@g#U5V6+T!)dP#ElIa`Vm^8(Yf$|vW&b3P*H-O4+P=GC%{=tn& zl=a?O28ONEx!joy*_7)U81&VrJGwLFC`5tg6)y0C250o;85ndx(^HI>zlnMy!iR&a61#PNZ_7*w%?Z2?`o z0Ma-Cs_~HrlduKjIR*y9yPyNw&oMCU1e*}eG|>S(T9>cK7|S%#g~6BsS{fLNfJ%eY z3=AKjMmTvg2}^=nrz~|KhsJ<%vtbt_0|U=F1_qVsd7eztkQyD-*aq1hT?cXWT2EMW z*$mn%pM;R%7Y3ac4|X%?M0k+ClTcY{FPOeBpiV6)-0MLmicJspViFPtImP%83#7$t zqRGm@AThndi%GWrDk#q0n1SY;Ik#~#Fq~FkV9@^xN`DNTpyd5ifq?L`dXFfg)kf+jv0gIpwy7#J8?IYG@CaLEE1LzV!Ii?eg?tcR8nQlJB3K}CeCA_Idx zNETc~)PYVGV1UG-%5-^eCZ+m5aHiPWz`&pncGg~gkhA70!ko32ALK01etn3u4#1~= zAkI3-4{;XQDWHT5I)Re$2!DJ7)G2RZP7zmPV6X?tf}Iio8W3bK7RH!An$`dcN73mo zyqWm9K#5J|90P-O!*oU;CM`yv={i14CcdD~Cg|{gPz#nZgw?VUYL}KWv_SPzW?-;{ zsQ}xT1zI7G)ZBx$VhS1|)*bR;64nL{;Pf_vQV?Ra5H#LloB~VqpnG6J>EOsTUsxk? z0kj468)}lTFO#sM!8ry7p(cW_8Pr<}WME+I0*`pq zDl;(XfO|_loFF;IU~ssCuD$dCMe%&jZB0&bnlfl|fC)Av2l5z_KS6;2a`2ZX zh(GQ9n505LT|B;Kkn5tsjTZ2TxFKlH+2$MrgDO}C?rxCZJwUk=G;#nc@SGv?%v>sr z42CnH^+EFVwSG*}s-WUtk1+}qXbe0opw&ZK>p%x{M1smxhF{>s<}m%OACpBI=onV! zi5F_kj2#&m7-Kj=6EjIF3=H5&PEa=lR68>!af-J-pp%^YRTvmR8$=mED!`Ln zpV52`(hl-p?|KMhnQ-QA{Na42Gba8$cn^2@zwSc&ipvZGeg`aE)fz z20GckiGg7rOu>a(2E%Ef>$J`=Fzf;gBGL(?A%ijKGD1)k8-n5*WdBF7BFH4`^x4;3 zd8WGrFbP45B2Z%vq(-lGI-`)A*!1cECW#0iNSXnK3j>2zr5XbR;}KA2j{(vJo7%>} zpbs7)JHiLbr=ZPB+5$QZ42(zlKyr-1+NVJiq{kq<5VHp$6Hf45oBlcgHkRoKO|S1- zr#IR&iA~oDWK!n?yBZYJAQ!1lPYh(zWDPmTz+gYUKafdO6~v5cg9IID1}~bK%TSQP z7__?-q|*e{83QM2vFY~%nI!5#i!Zb|^cff!K}V1=FjRpfUZov2-oy#6%d1rx80jqT;C(Aa*a3Yx_NrEk!5wiGC889+yZFeIE~U@!)a^@Cb9CZOsl z`y9xL(M;3Jf|wK-w@jZN#H3XZYLykMF))BT14lYxodIyh>SAJGr~p~4z_G3!nz7o{ zpoPdrH3kNIkSw?WxdXP?5H#ux$^?hoK~_aEb2-Q}fD$mIp9|_JfI{#WL>4qAJv~Z~ ziD$Y`Fq1GOkXxa_?>PNqFq7Ey=3pje@SslW^wq&k^6H?PqpkyNHl+GvbYU=Vht+$a z`*uL)9|dW)WGg?%!0^6fxB&Y%eMW!LBqybry-8o&cgGp@qz7Qs%dXS$RAo?M##5GLN39X&bX{E&w zSy+Mcox$WJ6QunIDiA;gCwSxy6a(Ofy9k5EmQDr+t$$9S8GZ0H<6=-$%sJA-z@QI0 z&XF;U1629^R%2k8?jOp;!8mn#L@1Mtz?B|YB)Wkv%SoEv63V1j4;u9Z*#z=kG}FXD zP}5;z0CcpelL53sje&u&kYi34G@>Kbp%GoF&cI*^Qvr_bnV>ENqzRtI#K5otAz;s?$XJD`g$y)KtfDU#7Re%h}pbLD#Aql!778H__(;tR0iA|3VV^W4B0&o>@ znt>q?BC#lp$q*s|>ZyTrYz0YJ+Joxllii?5jRqB2#;uGD3=XXf42Clp85lsb_fH{` zpu*=QERlSGHja#YrZ>KD6`P(P&ZNl-N*+Pe=Y}&$)z5BYU@!*F@__QAp&JvV*S!RhkU<4KC|JyTA?0~T1e0+6 z3{a{C%?+RIWMD9if_7zMdlCLH&SQY2KnAVVwhRo65}>vc=$vN;#yL-VVf_FJc1S+} zTtI+?Az1^nCv^*AG$>a`vocSQ)nnqEE|<$BUJp7&hT$e?DiSi7904kkl|j7+&_+!L z#yQjb7#OrCfVv{eB2n_70d;M4(D0m!2xvz+W3YA=1Bm<(e36-;AFb35N zpwt3c{Q+~CuvhmnDS`8)#ygXud^E$hn! z>VJdop=O-ZGu<$TNy5={B5VRHh6!cL2h=Ki04h{snT#hwi=%s*(BgY0tYBKJH~*9lR!}oT6R+nkp=r4G!V=`{b3A~tn7{{FrQ~Lfr2YY z3pQYw%d}&10&>c{To`)N^;*6ScIENq%$xuP6eNs!=%l?prd8Vz`(c` zeC7_*#4vCj3Yx9|0rE>RQ|Kh9Uv#vgehJrRV6X?tf{WEz+MpnE6JTaw_%(@v!61_% zg|QyIc<_iev?%}@Q?md~wKp&=0+|L{-S!A%8fbN!q7DOtJxCVZ=nDmfB7-3)K0rO? zZIi$u1PTLVQ27cffla=GYFo$zkaZlBN`1s+u(gb{!M4`xKyCG5WMC)&**b^GeKNEG zGFJ!M0J#UU6(kF`RR}at%wV#Ok%0kZE2zc+)iU6Aj35&O!vv5q>zMjr#@OgWjVaJ& zU@*1^NrTN<0yf7GM1l(P<&$Bq2aP!zF&Kj8^gt2^rVGY1i9ni+puhp;I`%1$T<00j zq|C~Ho`FGedSN`1s3VAJH3ec2IOQ@LG8o2y&KNk)zz~cgVZ>m32UcN#ZhQtAJ9)}< z!DX&u)9=PJN!NpN&2p%gA_fK%C(!gYJXe6$h=MjHfU9uRTalm@Z{YO*3|!8vnhHyJ zd%y|rkS;9Y?PCJTJqGbX_ZKkk2QLg|(PLmRdkmWLH~{8b=~*){=$ry&tAk9Sg|SQ% z10d_|4uMyk7l71@g9^99VE#Tm1_r~KpkdSV3=H|xHzhDBL8hFaAmaZ^0+WO>Xj6r$ z8_1%MVCRAc5*X(=Oouu5BiOmD`V0(aLE@mohsj~OeIk>DFQ}Ocx<3xojb!}AWH1ey zO4{_H(R);%fx!}{0vy9XL3h$2b;Uq^6i_gyPlLqX&O|0*Wl$7XPlH5RF$06~8dy&g zl&nFjH$hdiBryq_gHqfvgla?3ToNe%-$IBPgRbfTrF}!tMU)^D1gAq9`YB0FLad;& zM1Oj95|d;-KXmmSsCUW30$S~F8Uq?emj@4UZ30JR)C^e2$TNdV5D5bY1~bqWAx1@J zkenrm586t~s06+VBEkS#hUCwHl_B1sYzkUtBQ^t)_td~Enk%LYCo{=}!MgG*K-orv znPmpF1X*kVEkVv1fL4exL%X-2RnQC!CW{zQa~}hIS%?Y9HfUF5b~2MfJ$NG%Xl)_L zMc~>+ltCkY1_OgB52$Q&0DBfRi^@3Xz)YBD9l)MdHDq8g11}qNVg}W|pv|w4m4nXU zbF4tq)sU5gF3g~ngEfZGg$bY=f53Mn1uz>h%!K-AmLb$fM-3Sm>_O7tGVvd1E`q@j zvY0$lQpCUj9)bgP7^XqQ zm|@G?zC$ttXhqkmX{k&`yeYF_J}YFNI^8~%NnRROA0e7Kutt{c^hP!}vFZJ(Ov0@8 z=Rp@)El*|A&y=6dz@QCoJ9L9XhcQU!x;X;_V=s73Iw*rq2c@1qX3#Oefkx0-O7HUw z47+DRoD5o#2O2d6Ir$1y3{*_TFxoJH7n_EkXJGg_Yr1_JlRRVi^!PL;MY%N*3=E8~ z!I1Ok;FZa%n*o&cI<1>HQzzyMkv z%{b>eTs0pHC}lGSnSoBoXB1!ooz*teh=IWbv<|U)x=uQitcJ!MnCF$Cstt-#iy0VI zSU?G52S_!@XYJDq)0s4#o#(=Wdlgvqbt47_1JGF-jB8my<95u(&|DHc7nVzmLG!2J zYzw;o?d0j{3Y>0|)4!!NDc6H1LO|oelg~3S7-mA-xwqy(0=1NZ!3oriVk%bGo3?OwzV6kYXA_dTBx(kB| zXgv00J+xm3Y5;*-^B_lqGZH_82FRzT5uiJLZ-Zx=LAPWw&bbHo|821U6^$7fbU?em z81I75aAKMm0B$;f28AAgGX4XW!*ik8B-$97P1=k>%^+q5A;?;@eW0Oz24m1n^1SJq znM~@ux8}j(M2mIm^w>-$S#V$fk1;eCf(HG6fJ`@FjhF{Do!ZSDj~IXaNhxLOKTw#!0Y(8nzI1_dJH_L3&Ig(|NO) zgu(sg3t$}}V;C8XLDzeNo4TeGKr^KpF-h5bcDQ5*G#TFA-U#JqyUuwd@ z09kln#R?k~Mr2!9wGuub>}W{u1hSxiCCDYYNaCOpi@_MQ+#B|YbkZIFf?3sk8`(-l; zF`k^Bn9U?+F&(aX16cD-kas~_co;Xaf(Da+njm-mVBRZQ0I4;PWHSk8f>LnX0df>zsE@D@d>{uX=P=H(T?ljWJ~mJo^O!=jpzlI>7KD#QgSzpc znv-WC#7vNct(?KSH^MeqB2FM!I382p0HL&HN+hiH% za4v$S)N5eN8H2zbE08cGIYAb9JOE4Tnj(82=9H@lr^wX5S_t+!cpjIjh=aipRN;W) z?>|HW5`VF<&M(AO_MV{j4A@m&;AFRB5iCePgDrM|1qnz3;x0s-f-(pwNSYThFia2D zV-lWzCYMR3e#RnHmw-pgK|Ns;*t`|EECNsSbqF&+hI~x-fJVIaz@2eOq5c{kKzi(; z*kKF;FS`ScOEH+L`hn)nz^SjB6|{wC(Fz9W@_yx$;1rZ-%D`YYFPMRW@eC{I=>FLt zK6n`YEbG+iU3pA;ilAfjnI}%Dgv(8ENU@!rVaNPu}gl^to zF5bZgE#W{LA2dKt=wn+2a{{PN1~1iRvH&gBg*ibNG|2}U(eh?xU~mBGTFLeRrpw0y z>hN-qE|9Dhzic=I!y>RYV^FRKS59G|_Vj562JxkkoRL|;B%Jc}JOhK)QjllBol;QD ze>~5?-~|=}%>{tcfH5cyOq@{3V7QBcf#L6Y28Lv?JZNAGRNWXb7&0GukmBp}_mMCg>^MW{2RieO{& zpjI%*f%3~C4vZ>d(ozIvY~wRfbBsZg+$mAwAeRmOTeV-!>WTo#8 zs40xaOfpI!Z=PNb_hu~%WMPHj45(tJ6%Z>!ikXBVQ~f7dAo~SWSAcavMjb#?{f0ML zAj4{wP?<6Y24e|U1_n@mHB@C~U;u?%Bt#MxZhEYcAj*RXgTu`@hZQ=AT*(TtYa&>7 z`my8!B4Z8B+;+7vWY6QxqV7?%O21td*j_LX(OroY*D`ADM zBYK$v-uwg#R^gQpuW_g_n1F_Uwob1s0iAdS*BXjbYc@=)2~_K8kWujYG!q5}(_Nqr zMkctJ1Fg+qoU;LLZYH|945pJnE!}F6>Uz);4+h3L_u$H_k(GnOg~8Oq8noUGq#RtP zFwW6j1@rF`sA?n7YGJWeAa_MEnt?K*0c4$^=miD_V^E1M18O;HDS{SynS&Z*44^Y6 z8JXw&TQz-dDU*~Is4V_%!N3464*#u!6^Dq%D##E}B3w89VJVZ5FDOh8Lo9?uFsSkc zxfi^C8swk*5Lr;(E`+vZzd(c_8bH${APo!}w$l^Jm_*~>tbrBw7T~s|q$RA-wqgNY z{m3*i0MfL!1vjmOEur-~NFOBaf%}HwMl`4`0nR(F&|+-)>ggBx+{C88Dq~X0%PC}F z*s~fOTFhJwObmvg#w@5^d<`rJk6IN5Lr{`byuiTl5-bBQH$bDm;MT!XsJGbGfQw<&_bjiCkW zU|kde)-U=D46rT=X!Qa^1gN%@V69mPt>$N0LTk&TmJAH`AX#u%9&{)mbOmPgS_X#x z>CY;ebo3N9z!GpLc+6VH3Ywn`Ho)?eA*kgUc!7c8^SbE{RZJ4BAhzK2*eWJTiP#Ga z3@Yovz5xXjXhkJx7}{}qUlo%?0B9gO4kioE;gGu2*o}dK0knn*++hO6kuhk3Bm)!+ zpea-E8YB27s9tEQJh>hc>)h2$%Jrb>)w>X*L1U_hpw(cYg-CzkVlexdI8HDao?~EO z07;8&0J#-5S=1rSU<}%ETml-A1@|67z6KZ9d<+_(pfL>vwdwl71sP~f2;-ch4WJYS znoncwhn8gU)}RS!bo<`Q=_jk1q_dK*My5x43zy%hoXY*MkQ#g zrU2T133jw3&mxd6&}elhNEc|d`b51g1A`?@33y2G4@4_y&U;vL^dh+;yw1M0zY!4m146E3q9YKvh^67#4sm%;sr=>D&O* z`NSTyuLEQuXnI}()KY}(-FwSo#{jy@fPt}_XAejl$cJVQP#=alFfdrYWr3&w`>+hG z)etnL0UGkUy9uQw9nc7$$6hif$Vcqf^5sYuz9*-J(GxX&jkjCCkSa{&};zMIiOvdAm^xTfjB3( zo=HY$2B;hat%hE5fq}ts3&Iy$Km+Zk85j)jKv$%7K((E!XHsKaIQ?Tilc)q}(AOAr zRU_Df9%zH|=^K^M7$ToJz&GOfRRT|*X`a5Pkx4^&&jkjC$zT&f zbvJ`CXlNK5Ua%!F7q&qnM5c*JQuzcZ`jAwEib=3)P~`#&IK}M{)wxYfl7?3I z2e}q(wjpTw0BFsp2UrZ;A^Kg7xE)mD zfrc!!`9V!C#vt&>c@ZLuFwU8~3l=Tcz=kjefsK&4$iUFP z3+g$LvltB+OhB#zNr2jMMPNZ|1_skjHlQs*U?V}bAmf}5a3f#Aj080#G%hkQ+yWUX z$QZ>0(Qd$C0vcb|nC{TVBv$_iYzBy6oTIuM=Bz(ZGfY6K%;X}>Nem386F|!uxIlr( z0MQf-*Tf|V3S`D0V~{2XQ0vz8IA|6?6090BxYGewEeTd#&lqF^D&>8U?brZ1he;c( z3o_Ne4X#TYtcx)S+>Va`+wm3@6t-a1kkR}naMiXj)u7S)6tL=vE}#_`VAUWZopFxP z9+HUm`5fijT8^ulefV$&yeFbUUpfPHorv=46)*cecJG0v%g z8?y*z45%oX0#=;_TEDjutQu4VGR}$J2MdRdVATdru=%mgf}m-TEGKBo7Nii;)G`Dm zZ6bOll%_`@kW|Qp{kW$6x{)R$p*&df#Lw ziF(KYrX6US;VjrapxH9UIn(yR0^uy!J&Zvnpcd5{aJq_RG-qHi1d1F)VYa6dc}1RW=H)QJJoN8WLffx!4FVvg*oUBiaBv?paYnY%=rg5#|doC z66boDi(J449fcY60>vOJ&}3jF*dWkwC*z!!1F#T^1RM0k8Jaw%9Dp^w!5bOBTx4Ky zKLCz<&|o%rCnGomfTm+W33+;pFKE2En@P4Fq!rwIkYdmPnQtlxDs8gBwnCEh@dL0# zkp;GuF~}H{q!})O7V3C_hLS75szHPJjB`{D!cV1q%0A(#OwAXGqBfsQdUxWvGq3mR_)?W;4^V~k}qWMDA$3IZ*_sYkL|>=4Wg zYf)@o54L$W+~y5nn=hi+49Z7fn?ZwLHdt*of!VAGno2tbwm1Z|&6ROZKiuY1C^nw~ z+x#1D^I5RXhOW?|0I-E{KZ8m+50K5E=0DiapfMwmpN(KPzX2^T2?g(t4gq)8Rq_tQ zl2)iNDARzBABIF+IQYb<8dnAe*Cfz^KoP>AOKO-WE~wXe0oq&?CCn$uz`#6lS-p;> z4+8^Zv@qyK6y}LL>J35b!9p%EFmN3Pr$vw&24j%(5~dgQF-awqfnAUdcER<-3=9t7 zbHd7mK^N|Aa%Eu91|LyX205ZCSR1@>pd9QR#t^fcpe22k!k{Z#K*y>XgZvLlibtue2Pzp}w2JP_zTL@Yp!#GF%D9nS3Q2Xj3 z7OH?P?1NjVieVw&QG^dc`?^~|7J|mGU>2G&FqobOogrlnwh%OW!Z>F-+(K)pg%JB} z!S)?-W2lD)sU3!ebx0P1Cj2LWECfX%%tB)Z2Gif5B6S_;oFjG|=A7GL=eW8WL912rBPKpBN`j@t=XnzRFN>xAV22k}_ya(g=Owg?d8==zb(?3pO z5}RH$g-I$Eymtb$00gpYGK!h&|9{ZpKG0P)T8f}i(nwIb$Y2I)|IBGP1=~*_Df-oj zfkDs%mXabxeJvOmKqrKQy#aO($m5{ou^VKcK4gJAxQld}f#DNKOl-Q#R3>3lP|&cQ z0*4}KTm`&((;$a|!T1FO0|Uri#-RNrU?V{X7J-cPKLv@`g;SY?rEXkeV90>!X9cA$ zGX@hAMg|7=>F1_0N!3q2#lXP!9}G0w7#SG+Ed?1Em`*aS28n~l@)#Jv;sMEt3=AC0 zK+W(#XVAIw0nDH?VL3qCT&|yj%{?&$Jpj$?EPQba){4nX?gQqZr$E66 zI%qTSJ?JWehs^cdr$Iss!x$I>B|!(f3bDw7MJ6aRFa$mU9WN}#0y^?EP#JU>yBy2x zPzHv;DlyOrwk)7SJ_BC!Ffa%{4mu5WC-_u|^wS6jy;BA);;lFhcTo6g28N*jpf<{} zzSEI#VSZ5t$n_FSPDAhM`p?V|#K6bEz<7HyTz9arIs*d;huB6kFn}I%(n5%<5pT-!cfn^?i=c@#lQfRzUTo@QYm}@^z=xTokhUq1-zhMqNGU;tsRubiPB4h#$+ z%(a#yR6LS_0ff2sbA*Db1`y^t#}O)?%)lT%efw-CIo4Gv3=FHL-R8NY5 z0ff0)r}NKY5|8=K7h0#ozyQKrGW?-B;S3BQ%%#mA8mY;^0K#1M9HIT(3=AO5<-#87 zEzQ6H!dxqPLqUyC5aw-W4h=D7U;ts>0_ITd7zPII=}mK(v{?@)Ffbh6zG)59>wBSumz-7e2}qsLt58UH2=~Z>H@D@0rf9 z!g%ce+(4bIAJZAj1rxVV_`&prnX!3$>mMc^My6Nt(-oiAiA`4!u4bEl{x6d_`yzEl zW=2l_=@0LwicXK_XXf6{`;TcMBV*(A_5Ydd8E;QlWMmc*UMI!L&cMjR#C$Oo%wS|b zGPQtNWU3akoW_<^P9_FM=6X&x29Qxq42&#{%$OQ3PAy=z&{#%DF)LX6{izq2MQj%m zr}&8!Co=;hvlAyD10%CN$T2KT%yTdu4l(-WbPq;m4aOKtqrNi6LaWJ1|VZ5<@7B90EBjfAo zSNWKgm^NxcVq`*7Dcf{We&z(RDKTI#FfzYU1~ZtLr^aw{PJgJwEY9^-8SGUSPSNQN zF14c55Arh`iT#S^x}pHHFyq4QrUJ}QSf(2&F^h|{Ffq?e z<75GAc`ganGAnKR230;u#uw8QMVaNM3*1j-+dfg0S%X=rQwtQW%;4yM8qLWI);Akw z)w5_$w&{ldnM9|5kYMIunxitk(2QAhJHI4zG7IDK?ZvXp1(Lig6rn~iGjj?~7gS=F zX52rW$DCQ6{Tf7O`Wl{08OB%B!_AqMB>q6e7#KNuK?m0|u!46PFn3L#XwEDqF;fX@ z7AI(L0V7Oy_4NJb%wkM?m8Ks^v=E#A)|^>f;u2gbsCI@ceK1|df?1vYixML@>mw>gM1Jy4!5_$E|pdS7@V$Mgv+ zg;=KBS~6=h{+XU>$*jjTS!H^bC9^KmYAAgOLNnf+u4=`s&h$zJV&;$ODOSu5jFYA> zwPJQ-U8~B-%rgDs9Btw0cCi+0(>bk~H5pHVcrXMKcV3{6o!>r2KJpH{5v-tEmHq5e& z3#ae0VK!mh4H7b8-KNgS%r;%nj9Ga4f>I8)>5jI{`i!@y7uqtrvHpR{Nlw2C65cnR z)s9(%>5Jy{f-N>;(_QVD1(`N$O;@;ACo(<9j@g{)rq=We%$Xw71vdL}OfRd>6PTV` zQOdFXrXBO$;OR!TJVM*APGaUaWptc=j8k8Edbg*j%Jc)rnR&KboM7JK!)$74GX3Cl z3vm`hQ!{fgi`mfFboxc6GGP`&5bGl&m}O`_J&~nMnAy$ z&SGe2Xf{33PXeUD&}_QmbZK#rnCW!E7ZxJShDHWpNmfHcBO`<9jiM}~Oa>4;nGKDM zVKy09f>p5?8X6c+fB4fznAOnGz`z*fA_-M(-msnC7BG( zrwhEW5M#15gPLSu3Afl{x?@ANIIE$dv4z=mMMWv$?Ox(6%8c6!Bv>>+Mf6NrmUT)@ z7G~1}nwe#%r#Z0HFk6^1OppG=EH(YV1B-y5fjL8bd|GKX}pL2+(zaQAihNzYq zni(<($H${6F)}t|nEvq>voIf$S3!ZO=*nW~X@G2>u_=ZH#-?TrXa<^^fjo#}hpDB> z_Svp1q1B9q(?1?y33df7BNh>7WB`pCf!N$T!J8r(GC+su1u-yymQs~N*$oT~3?M8L z#J~VrlmuE)1!iyWJjf#6EqR86fq@aUFOGqM;UN8^gP%AOCAguWrMK|K&y@Cbm0s-R&Zhr~8UVmnOV=*OyDpMfM) zi^T3kVoyb4FGOOmMPlzlVxK``Gw>h+N(+e{31Ncxh0nJfE1L`J{#8V{pMTN1Qi8R`l>B)0YRy@9Oal3_?f*+}e)>2CvBmFpKE32jAU zA3|bZKw>{dVt+(p|3zYR3Luh=C=y!{iLDD^Lz0jsgab}Ou1M@aBsS=bU04#zLK2^V z#9ofX-i*Ws&8x%oUO^InC@`HbnAJ*BSrFl13naGd^u%CRWyxG5p?)Oxoau9eS(Ouy zAPL<>Vn0J-e@0?6f;PKDBg_DaZHvVAMq(#S*9~D6uWv^Znu^5Uj>JBK#J+^YevZWc zjKuzr#O4Og?LnO-j>J}hu%R&p;ecbx4T&9v#Lh=zS0l08k=T=w*lUp3JCNAIpcAN| z4$=?-%?m?04oDI{NbGVXcFXkCP}bmj0nqddRGTIeTOWySio~`?Vml(S-I3V7NbC?K zb_WuBGK38YwDk}UIM8+@v5zCMFC($Jgf~kt9-( z*yTvihdpQz&GZK4068kia4f6kW7>9v@;V}~XJrY|9)HQ)dlPMD05sB@K z#Lhxu*CMeyk=Rqk85rtexqcy%#9Aaa=mu$+nxjbK7m?U^k=QSh*k6&@jG$Qss0Vlv z>?8&$1cyNtiEV(ywnk#RA+ZCI*s)0LA|!VG^r;c7&8qy8h?urRVh1C!6Qw0O>@pn*Xt0S?E zk=XV~Y;PoXI1)PU*e{XTUy<01pyO*`E<$2UA+gnv*hWZf ze+U~?6frPFLpb0NPe)=GBeCm|*z=Lt2a(ukkl5Fe*e{USpOM)A9v@VGa^|BNBVxbl!MYYe@!0L>d!C zVk=EgjAxBEoQNa@I=2y)LeC(HKSW}`oBlDLRXmpybgdWE=h{eYOC+`*5<3HlU53Q& zMq|_A4azM4Rrnr)OFTKY>(-g$*jut1xP}zNbHG7?72wnl}PNZNbG}1>~l!$TS)9@ zNbFA#HfW-rfq`8eDRUsPwUO8s(@j%YmFp9cgmRJCpyS_QnWhy}(LfqZ z*f~8hl~r8w3X=RQB=+~|6H{5mL*+py>O-BRi^R4@VtXR7!;#o&NbDLUcIWiJsjSL& zn~;Q#BeAa_u^%C^zaz0(w5G?Uu`1Q;fUe(zI?oY_?T5sUL1GsovFni7JxJ^sNbDs@ z>8$Cj%Jsh?V&GWi)JCL8aU`}X5*u{M9xTZ@A&L7Tv6GS51xV~V zB=!^t8{(FQ)7OIBata~_cFO}K_FE+OFC;bxXmvL<9A%N%+DL3iB(^USI}(YV3SmQ% zc_D-Yc0?@_yAz2$6^XqNiM^3C!Mi?99|LZUg0|UbkBsS=nE0_fWdI$%}Ah9)&*d|D92PC!+ z5<3xzou|jZF#Sv>Yli9*B+(B@Y|zP8Fc%0-kIZ5%ub+z4onM8--hsqEi^RT##D0#% z{))urHb8g|bYv9FN>wCrV+b1*UJMM55DqxK_#?4nk=WTt>`Ekd2NHW85_>fgdj}Hx zI1>A=0aAK-i6rqAi49tK3-bZ5A;M=;NNhDEwg(bB1c_aW#BPMKLH_TBaTpjFW+Jhd zBC$6jvG*dePa?4&Ah88N$Am+(wILGQ7Kt5Ygw!wZLXwz<#9oBNK90n`jKqF`#D0y$ z{)WV6G)9D+0)k!7po`!zSRk>(kl4vc>@p;F6B4^0iMhHIUf0NNg`8b_5bT7s7^wP8Ea$4xJ7p_FN?PDkSy}B=%V( z_AMm#S0pwU=s%ug2dj9#6EfW*Fz#J-1M*E2jt za2Vbou|FfRe<86MEfJ*#2NIhfi7kf2mPKN#AhET>Wt#BS`EENbLGM zNSqf)>@P@c(7sJru=9epib5T#gT%H#Vh13xlabg>NbEic8=U?aW+DiG2)- zeHn@U35op=iOmJt4G49d7!q3s;dHxl~<68jnw z`v($R+76KmG+}Iz|9xN_1_p*GBz7$lyBmoOI+FtCxVuQ=uaVfi_6W5Ubv`t>J}gq|a@IYC#SK;vH=iEW9*2JN?pg}N>q&q!=W(8UZ;$0;MR4UpKjNNjH;b}kaT$_Xjawj)VQMPhG9VqZdH ze?ek1IwN986p3w)#CAbq2g2B(RsA+b4J zklcdARzhOyBe88DY{+Dj7lZ?ji5w($B@(+0i9LDx-zrclLK1p~#Qu)NW_3llOC5=A zg2Z-2V*4SnlaSagNbHFaHY63zhj74dKZwLWhs3^v#QulG<_7I2f~F`5B(@q7+XIOm zio{NGL+T6UPdBY$wN~AZB!3f${S1lydHTW{R`Gg$cSN|@AhErW*f~h-N+fn05_>Wd zdpQ#OBog~N68k5F4GB9o&|XWZ|Amp*>PT!)Bz71QI~j>xh{T?Z#9n~JUW>%u>`O@OFGy@gZ$zTtLt;xKu{FG>Yt^%I z8JZ!9MIf5}Jd=UV+5kg2X<6#6E+>zJbJkg2euS#QuZC=I{lFAS8-JARKTMDIl?Rkk}ST zY!@VU01`U}iJgJOECkl0s{*bk7{Z;;qOkk~As z;{-sF1@gZDjKjddAcMr#Kw_I9u^o`uK1l2cBz6iCy8ww@gT(IeL+TYzL6TU2#9o8M z-hsqEg2cXn#J+>Xeu2dPg2ZM3ohAbEJp)5M0}q13Ac4eIL1G&qv2Bpp9!Ts^Bz7Va zI~R%Fgv9O#v%#C285rh(IpFliuyVR&Gi!Oh4(MDNh$9&sk=TAn>}Vu*B@(+2iM5_=sIdk+%(6cYOe68jkv`wJ4ADHxpf!JZO; zutC{?fk6(!0ZZs0v8|BU9!TskBz6iCy9kNhfW+=YV(&#_Uk*lEE${$I;w=*U*YwIZ z*7*A55QO6kk=XS}>|P}HY$WzdB=&YB_E9AEWhC}PB=&m<8xl}|Aslc(af9w8fySI9 z5?dXKZHmNpMq&pdvEz~0xk&74B=($8r1EkjlEgkF_Gu*cOC&ZE=x}qWLphMxd`N5& zB(@3?+YrVE`QHx4VPIhJMq)=GvD1*)?MUoJNbD_0?Dt4)Y0!CUP=_jk*x=JX85q>U z85rt?p&Uby1XPhd65AidhN?*dv7u@*L2U3@l?)8I;S3DIP<91K9IB=n#Qq45RfY}_ z8!A2n#D=J^XIKs5KqWST*r02a7#J9~feeMR4}!#@YR)6EZ-LlQ3tl0y--Fmt_5VR^ zs5uItlZBydLogc@{tOHZR$vaqr9L1wCxjh}#EwH^XM@;K3yMH&@X0z13}q1v48l-$ zBS;*orXPtt7m2;19>jtAU@eFZ)vyD^hKlb6v7zE8Ky0Y^Sr8j4egnjYia$eQzX!3Q z4*Cpr9O$?uX3$A8A3^mM=tNs62jpi#5F4sNG!o()kOn!BIMf1F5F4sS4~gvpVnajD z7l|E)#LfhzXh?udO`6II>;Al0Xv8dIslDx zAU0HQ28az6&jqpTp%#>ZI8b&Ehz<3@R3!F1B=&v~8>;>}hz+&i6Nn8yoQr|s8^{At zHY4bYD5x495F6?UCqWPgDj@@6LnRbJY^Y{!5F4t-48(@EGOVH*7=(qVf9qjYhK+_M zfTW>Dq=MK`ZN*6JMkIDW5_>KZdo2=s2Z#+d^B{-~wf-pBdIkp2<%#uIK@w0!_mJ3+ zL2Rgo=SUhpfW)Edzk}FNHA0{>VxVjd5F6?NeGnUb00;wvaSQ{4FqCZv5{J!(d4f1l zL;XN(sOCrz8!8?LVnf9XemhiGeo=<#D?naLt;+`v7u__#DMBC zsG`Ln38+DPkl0s|*!PgwUqEbVa{G(KW{U;gS_^RmKZp%=s3?dHHD3|I zEfU)eiR}+!Lk$WAv7rWKBC*?%*lR&-XlU&Ku|XUE7#JA##4<1lL)ph;k=p&2K#HIt z@d%0i9K?ni^a;d8>*%g#D=Pw0%A*m!k>YGVFri;RkQ-c zhAP^K#NGyCL)GjDv7u^Cf!I(7oddCSpv46xf1TlbiTY&t`2)bVjsz@Bf zhUN$bB(^3J+YH2ps`o--r%sKhz%9jLt@(?u>(MCs0AS)HZ-16Ky0Wvxk&6H5F4tdIti(mYy(L^4eCmQ zxEi!ecos+;YS3aN_6iUis(uZU`mG>wsQNu1HdM`J5L*$HA{ZF%f!H8%P%?cE!FGmK?kQnEe7Ad2^ALwi9^}i zAU4!u6C}1R65AQXhN@3NV%H+ECnB+@|CzzcQ-2&u(he22v%k93%l%v;oA1D%uTVLk-#w_02>E28Qz> zaj2RbNbI{HHdOsXB=xUA;!yP;L2Qs3P$9&V2|D`|Qah+4v0XrHsL%XCY|ydM3=9mx znG6iVP<9+h9I7T0#D-ds2Vz6TYmnIOAU0G@PbR1mfGU~=l7O<;f!I(BHi6jCP&ou* zLp7g9VqXBUp=xe|*ibbOKy0Wvj9Cl}j8L``f?dzxgy1klBe8QpY^a0EL2S_Jl?)6F z)maP-pq);j@M;5zL)Ahz$)DMGzb62rVSGem#f-Rb&BTLlxPB*ieHK zkl2k#>;*{d14!(fNbE;Q>@OfTG#megvcdjm%R%I6eh?e#8_-=(u>5KP5?2QWIs=1E z4g>foL=ev%Bn}O^FeG*w61xDz2HkvJ{EE3dDx0*$iSs)$9VXq2?S$V&4R@p}v0vXV)_@yoPfa7=D1*P|ZTQ3=E7= zwlosk5X6QWWQD|bMq+z{*igMeNbC#{8>+Vu#IA>Osz4klyBWlW2G;}-8*0!@B=&j` z8>)T>68j($`xJ-`4c!YMHq@M(NbLGANF0$ogpXZ7Y-l`rgV^9(>KPdP^B5R}q3kG- zI8;q4hz*T`ED#$iUJ7DE#p^(9sNN=sIrR*nqx&a;B%q3BBe55N*ia2iAR55x*Mh{M z>UV(HP&Ip?YN8n!7|wvip=z!ov2TIcQ1$on>LI=XX?PBjfNJ;zVnY>ugBm)Yfq{W7 zAJOXMM`DYB*iiKn`4BTf>J>raP&0KvY^WLosG2>X{O16YfGYAtV*7#EPz^ya4WLFn zNF1s@3B-n~DMezpg4oa~=mD|yAh~P;$Q&qpc0N-1zY?Sfs$mO=4Ygn=hz-?n28n$K z#D=PW3}S=MduCu@cn-1v%KiirhpJ&HKK_%kpt)Pp!si53tWs-Yjm zhKf%Cv7zGgL2Rh_5)d0Iz8=Jeif;k2p$y(=sRd%!LlwDzI8b&t z5<4Blh8mg&VuLPGVPIe=DrR61hO%ox;!rgmAU4!N(~;P7Ky0X*yHY zR|RpP8gxKx&}{?^3=9UP3=G0hwlzo`s>Th(h6cMghz%8wMq;Od*ibduAU0G@7ZQ6` zDN^~r1SIhslr9++Vi#D>m+SAp12@oo?snmi|h*bdME&RGx+IAm9Y*w89rBZv*vybFna z7>Ruq#D)g=JtX#XBsOyeqGII&v7NzIG4NG@+BQ&*BuE091k{n(Mj$pcnV5svQ1u=l zHdMVohz+_G0MzxYU|8O52qn4pgEJ#0E()Ffeq2*ii94 z5F08!1H^s;@xek68*1575F6Us-wI+w_3lGr9|p0ZYR*)E(l%7lb&v$qpxYoeRMBe? z8>;3D68k5J4OPQbiD>b0g4j@Vgpk-8AT~6b3=!;l1}g-I!41TQYK}r;=OeKzkl1}7 zHq_ARNbChj?3ExkG_IEj6veiD6<2xp`qvuVnfx()+2H9Ky0XnQV<(-)g1!^LnX*iD7ytD z4plP=i9Hv@hFY))#D=P0jl@0(VncJ&aS+=J+P1j`<$zrM3dDw5@DaoY-IocPr~o+v z%4VoW_?{cYhFUC%#FhiGq2_3U*ibckAU0IovKrL3flAncB%l_!Be7#aY-k*(A+ht3 z*rgygRBs&;yB&$W5Q)7F&aP)*I0fQBU33w|_5+0j1H;v71_og$`vFKCs^&F_4R!Pf z5F0A~8^nf+^VT3jNCL!$ipzr7Q1u!hc0E)=7sP=|Sb*42aa#}@D((SdL&beTY^Zny zhz%8w1+k&xIY{hs5F4td2E>M{sc#2ypb|YGHZ)H!0I{Ls%Rp>sNbEvlA4X!|1hJvf z^azRl8j1Z8#D===m#zTc_AEdxGRI$P=j=k*rrHqYY-c1P!tk78Hrs9VnfYo zLSlC#u_xAo+BQ&wW`QK2>|IFg!$|C#AU4#{M@a0~NbHXwHq;!}I%rKd z^2Y_lfg0+I#12DZ$AH*SLsOC1)gU%hZwnH;7l}O?#D?mfgT&rc2P*%ens{B2%RP$vd_Dc{Os{Rua`!^Ds5h--Jkl4Zqc0Gd%hyzWH+8}lSIJ6k_K~*!9Z3PmC zs&NIep$XFq#DL2RfvOCtjVBh*ZeMh39?It&a95+HG?8bvs}o`FFP#DQwiLegLi5{GKA z0+Vn#0K5_$H2hQ2V#Sk4TIAAbPxxsXf22hHFO&i zdp{EUD2NSJe-4TL1jL5weT&5YhQ$5@Vng-T^ENRsFh+u$z`!63VnZclkl1=4Hq=ma zB(?(*+ZV)!Mn?#U4fSP269a=Vl${I`hpNc~v0-yt#UKt;q7}r3YUl*9p(%MLhz*U7 zMM&)BAU0IZ1`r#nW;=)tHRk{l`x=N1_00VyP&R{dULZ+)1+k%;`I{LS7@=$h5E~j= zY9KaLTpx+;g2YZiVpoIMP)|02*dTL2*r6acL~lJqCW6Dzg~XnZ#NGg6LxXxZhz-%qa0H2c z3&e(6{1}P-28sO%#D?nq4Q7MFpMilvuoW@8BZb6PMq=xO*ig-mAT~7EJwR;8seBAR ztqcspP#D<1kI*1JwFRe%7G$XP5Ky0Xn$sjgV!#ofhD!v%RhFZ1;iG2vf zhK9sxB=!{~_InUJ3flhv0p);70lqdwNQfh`6_D6!AU4!u2PAeh5<3NnT?S%99aN9R z?q~zG|Dh6dKoU@2E(WndxBf9OFf4ClU=W6~H-W^VYW9NI(2zI=VnfxO0P&F$+Y^a*`AU4#T`Xfl3vqD- z8>&|siLHagHU+WoK->RLAP!V>8WOu6iQR$3o(Ez>Em)4k-hjm331UM-?ih#-HU9$= zo4*rO{zE0yIvE%kp|dzTAU0Io6p3wz#0~+mp^k_}Vy7Xob3kmUIgLo{E*KkB{w#rU z7#J8%f!NTvzX)O{LgM~vCj)~pl>GoC4ps9S#D>P}2M`-7{u{)GiZgT}I-}emHdI`o z3sn9?HAsOZ?m{e+2eF|EM+3x$sxe1myMfqH2c;viv%4S;?F21D0Et5_Ye8ang4htf z^$fj88m56Hpc)o}*bqewOF?X?gSLX$P&NCI*oQ%EsG2h%HdM`J5F2XF9VGTA5StSe z{tOHZzrh@c?^(JLB_J<|4Gk435F2WcG7{So#D=B=CnUBv5<3LMhMJQPVnfZTs7K=T zf!I)krX#TzAhB11*ieJEf!I)kP9d=`Be9<$vEL)HS$iO!1pA*4$^rRb9Eq&}VnZ!6 z0kNT$1tYOzkl3k6>?$PoEF|_8B=)TyQ27r{Tn|AKDIg~>Fg)#HU=W6~KY+xcYJP** z(0FC&Wnf^0s^LUp%Y)d^P}D$T8zQmIL2R(zdIkmuIER736Nw#%#LfV*p^nH0vC|+9 zE$(Gt5QehrK;lp}JxJ_nAoewg`q>~hRQ(bVyB^Bf1>!(meHe*-28n$Y#D*Gl8^ng{ zeFb7eE&d2%gYK>e4cUPl2W2z#A<6(gBzCR9)!dW2eF|RCxO^d zHR&KW)Zzjp_6!gks(v1boeeGj7xghP2!rm&W?*1g3zC2;+74nv4c!A`L&cAQ*iiA) zAU0I|CKCHGhz+_2mVtrc1&9qb|05Ecy&qKmLxWwQACe_NF(rw_Rsyl125ErUP=g$h z*kK?xbZ9jO#D=QLM`HJZ*ieT~1+jBMlj@*@8~Yg;gh3nz28Jad38pI0+B^xYk=5L4Z0vU z)F2BG8!B!KVnf9}Ky0YEFNh5lj{vcu;;|q$#BucuX$THO0}{IviM<$!y#|TB6^Xqc z#D-dS48+cdgv6-{3=G0h_EnHLRLuhr8@9IXDTo8DJl=uWP(@4=85kI$n%O{Xs2VX4 z8|oW*B(@5O4OOEHVnfxKfY?xTypY%#^+=o=Bz7-|4Ryp65W4{4n;8=s7=)qh#UOF0 znsp#H)UwSWHdK5chz%7#3}QpYFG1Ph^8YS~16A}0#D*$*3t~gXKY`d#@joE;BZz|- zCn3@e4~Pv_F9>2o)vJKmP)BQk*w7HNm;@^Sp&A@P5>U1qhz(Wb4`M^b!$54Pcm{|K z6)yy_p%#>a*ibdCAU0G@9};^qhz(X#&%iJT#DOYW3}QnK+K$9NfW*E8VnfS}+eqvu zNbI*DHZ+8OgVdI3lJNs#u3DZs__7^ zp^lD4Vkd&wQ1yi%HdK8T61%=0#DOa60I{Kp`ax`{p(~Ks2a(vPkk}7EY-p&wL}GtJ zV*duQp`pStg@J*w09yVlK{%j*V6aAFhajj?4K-*95_>HYdozd)HRm`I`!*8$2@?BP zJ%|G}lzBR$0m6gC76P%Mh8iHT-9c<<@cMz+C6Fi!n$Ex=3}wfH#Gz_3Kx}Ae<$~B> zq2oUlAP!Wb7Q}{X=m4>y;=Ld?RD3#!4Z7PNbOi~B4Yh0m)MC(Z`zDY$RPS~W8>(hE zl9~h4LFGTx(91}Qu7lXnLg_h(4K?Tk68kHN4OR0G#D=P2ox#As2(?TciLHRdHUhE1 zp@rADH_TvQ5Qeh5LE=y~(?D#fgJy%+Q1N9T zHdK5yhz%S6*$v`A6&(Yyp^DCf*iZ{DgV<0XKL)X(YTh8RKZ4j$HNQY?s2awZ3=E7= zb5xMn_3lWV3?z095_>uldo>dKAczfh^a&8V91<#LW->4cL)q6s;!rh@Ky0Xko`cx1 zec+!!9H_*15F4t2eHH@)Bh(-PB(@re4URts27M&91rpm1#D?k(LSm;?3h+P9Q^D)RwDEl2q9HOS4 zfqf35%;y2Ip^7v?Y=|NT0}#6wVvxxk1_og$+a4qiRpSL>Lmd=_#Eu8Cp=vTg?0XP% z@<43R{6C0W4(5PZ3=F*>HZ*ZfLt@WIVy^(Pp$2UQv7rvyhr~XP#J-Kh{)EJ4tDnoj zzzEeWg~T>SVn>45P#+|K*q}tiz`&3)mw^E^l@4-tK1dv@rV7M{h6LDrsQ4t1I8^U6 z5F0lCy9~sEYFLlN-U4Dn3zNMdHdM_K5F2XHStRy-5F2XQGY}hen=k_d!z++Oq3o|9 zai|*Rc}V3y-#kP*5C*ZKisV3SsKx3aHq;<(5F6?^YY-c%#s!J(31UOl1cBI4HIX1T z*qnL>hCDcjfuSD6hAy;k1+l@37#RAH*h@fcX!=--#NLL)-UDJo^?L2RhF4TufZ?25#W2C<=zOF?4iBC(4>Y^dILB=!st8{`O3E}9SGv_M?C z801nYdmTs|q=b-`^6ua;ubP62t(PKAaSUgawK*mh5r_?%{{bm` z1L8m>K7-iZAW;T}?;y=kHq&CHtOa62eJ=!JL-opn*idmL5F0A43t~gXjX-Ruxb0$4 z`45$FLXz+Wv7zFLAU0G(4u}mEF9fln;*Ch`iAd}@AU0I}LJ%9Oej}V+&%m%7#JLUe z@c|GUs^}DmeG4Lf8N`N$#B~rGTB$q-v7r`xKw^Idv7u`If!I(rtVWD+mV?)=Lq+U``~q5E5Gg#D+RT8;R|W#7;qCmm{$!A+cwJ*Y`mU+J+=?28n$Y ziTxVHhUVQbNbJ8zY_??#42;n9Bn)Ch%~wNW>%-Wf^2Y(hfi5g@1F@kRqLJ98NbE^S z?Ab`{jUYDEal4S%hmqK4Kx}BDzO)Qf{zEOh4U&MeKZ4j$gMJ~gnU^D?h6luk8l(VX zL-lGRv5k<})=2C?5F28CJwp_N!;p-`&H=HZ7F2@RPz#!n*fT(Eh(Qbsk=Uz{*qcFY zs5v`9Y^XVBz-&$gDcK8U05tzcjfhO%FR#Gz`wgV<1UhLsEqj8L`+ zlnwU3Hi!e&U<6|KLku-r$-p2CWjlhzp=$g=Y^Zny5<3Tp-3($w)pvo|6Ch^xfy{)m zXRZX5|4>ECkrZtNv7zESKy1)i5};GeK$@ZK;~;UUnyVl-RQx`O4HbU|Vo!ot{0gKO z%Ki!x2dk-PU|?RwzyO-X04WnkVk;oAwLomJ1_lO05PLF6H3Ng`Dh38&DBA%f4prj~ zVna*101z809t~nc#S=hm*!WKth;tueXg-JyHM9bW-3MYr6XtXz_5vjKN)Q`r&Uz3V zYR(ZP_E{u${R1SEd>&X`b-tXhWbnk#DhXfR_IeAP&^fL?m_=61xG!hWfq}i9HF4JsZS+0CDIF5F2XdUL^K)B=)P- zp!Pph(PtzH_B9L)j8Jg_B(@re4RwS*659fa?FeE+9pMgQL(PdsV&}uyp#0Yc;y@RW z_k-BbIGYM$Lp9GsVs8Plp^n&##6E_^J`Z9;9dQT5hMMyU#D+$}&o!X(AG-DT?-~XM zVJKU4Edv81lr4wEHUY7r7TY4R-H_NmAU0HQ42TW2EE&X}35lBYwG0fx5OzI75l8~6 zr~!%H4PrwR&IAw}qJd#15_=I6dn*$A6cYO~68jDk`y-eQ3V#L$hF@R~#C81Z7#Kjq zr68UJ5?cwxhB{Oe#GVCG!N8!qj)6fK%C-QBL)CbL*idnQ5F6SGiU+Zw9?Pgl;^czZ zP(@`RHdIk9hz&Jp0up;6hz+%D1&BQd;-EDk2SM4}LE=y~hd^wona4qF*!cfN5a%&O z^ED6~s`(2NTWCE410z&i6^ZSH#EwT|XCSc)k=Rv8?B?~L@*iqw50bu zAhGv?*ic8G0y(6ZS|}m4pc$_#D;1R1+k&x z@*wtAP?#_XhsG2S$c0Y&>RX-U?{Tz@uRQ+-g8>(hCRLurP28P`mLFGSG z(Gid$DElOc4b^ZKNy9aeI8@C;5F4uIDTodA@mCNVs^%XOn|Tuh10z%o4~Pv?11f*S zK^&+-(wiVYW@ct!&<2Tv6frO`m>{t&L2RgcTO{>vAaSVrKoA?MCKSYmTAT`EL)GMM z0+s(zPBBOVs;CCUhKjd?*ieJIp_aX6VPKdI5{If;g2Y}4VnfxhMN+>FBo0--7sQ6B zsb{!{;4pkgVsme1U;vGHf|8dA5?c$zhL#P+NNgJ=7Ply+ZEr!IF2eF~KMis<{I!F(R?NpD%@kU}Ng4j@B zW+AbQk=QjLHq?Sn5F2X2A|&=|B=#00_9+mX6FUEU8Oj0q{|*xSDToct-=9Eis0Er^ z5m94=#P$HOp^gqjVn-pd6F_XJIhk7-l;Ck(gd|ao#O|N|^Es<>{X-<7uSo2FNNn+K z2zMDEvAsZSXqgoVVlM*ulz}018v}zdl$`()hpNd2v7u?T0K|sPQ&xjGP>BW*8>)E< z5_>KZdozd)4Uj!Z?4wBRiy$`CoTo_acSvlO?VxfBY7p;sMA{QWVk?2zP=m~n*q%u2 zAS8AQhz&I}7l~bl#BKqxL7@U#&Djm&EQSPK|8@ojVJLeRNF1byfq`KKhz%9r1Y$$Q zcY@eUAbR(L^g`JuK;lp}*Ffwg)9<}x6|Y|kQTh?26w3Ysl7=ef-ht?y2!YtkAnL_- zFff3|TtGZUkT_Jm4u}nnI4dN!Gl&h<>kicmTCQIo4w8UsNI+tzg4j?EnMfLnK;lsK zl^`}$O%oD(28ay}@P$b1RY>d&Aoen7wYU?)0eObuJctd|d;^L75Q+U9#D-e@0g27F z6Om&0k=PPQY&j4cs@H5MD7is7o*;=j$N?c?AT~5eV?pfYV7DQ2lKy0Y^Z6x+b5F4uI z2Z+5IY!JgAkU3B``))+85e2cK;%Xo^RIe_Gy#^Hi3=9m0yBQdS*FX%i0ZBj=d4bqa z@emLjDjp4DuZ5_O2kC{fvq0idH5DK>RJ;?!hKf%BvDZQLPN@fJhH~bEB%q4cg4j^; z?I1Q(d>@Ft9-{dWNH3Iq79yAPJ}<&OHna zj8H|wAU0H73dG(B(JZ%zfk7C`)&z+|)tG?T&;)1+VnfyVBC*4e*cp33-6CkBD+EbE z*;PpFMi3inK?jJv3F3$zkRzb%=^$~anoS@!RD3rQ`z(kJHUAo%UC+R9AI@Q5cm`ra z4SEY=Z-!X*5o8&Z{RbotRl~KHfq@Y!E{w$11hJu(86mN)k=TwPc0E+HH;4l@Gzi4r z0H1=HdOOEB=&X?8=`?>ABepNV%Z^(Wl;86kT_J$4G_ZUOtvtxUAPi-10f|G^971BB1+k%yxCCND)!YTKq2iA~ zY^XV}k=S2A?0TrgUl0e%W;?{dzzAiFgV<0*IiQT8>%J@#DAdZ_2avYSs3?vR! zvk}CGTD%R!hIKa&f;do#YaljM!!soIHxL_YDEDCo21Y1b1c|K*Vng-nfY?VN4l+2* zz#t4|yMe@^c6o!3v4Luc1W7>I=}7D%5F4tY9K?ni)PTgE24X|A?tCQn3MBR+5F4uZ z28a!^3snB!2XT%;T>2Q~QYiZ!NF1byfq~%<5}W-9qK@DJv7u_DL2RgAeI&L8659jB zhN|~J0xJKHLo5zH!oVO5Wyc{Y%0Xh6gV@lJr~$E|26cnjP`&e!*ej6OJ3wrx`u!mG z39!BO42MA$LpTiQKoU?zcaYf6L2RhSZ$NCQn%^KcR4@Ng1_nkbTLOu#0b)bd>x0-Q z!4@+ZA7x+=J_!nc1_lN@kOWkb4-z{Z#D-cN17btfWP{jHgX)pk9Z2jMAU0I}d=UE- z#Nx#ui=pgwV9iiPJ3)$|mYqOip9Qg@YHlI1UxL_BgFYd#IgTNkS%OGxDI~T6h~fGeR813z4fV`KB=$5A z8>(jUF;M#-%Gm^xfEu(LiG2~ohGwl>NbJW*?3W-mRPSFTHrsIq21cm3IEW3kOAf?7 z1M)yU1B23W1_og;hk-#CBmq@q0b)aa;Eu%h0kNTKB9Yh`AU4#TLL_!Ohz<3?1SIxM z5F2*n`+N`ws(CXK`#2K&E{F}a_z8%87UTm4h8G|YK-r%`;!ri9+yFZSjOPTR%n$^z zq3Y|EKpfDZ7wAw&5F0At4q`(M@&mEYK`aY8!N4F4WygZVp=z>0Y^ZoChz%950kO|R z^frL>LfPFQaaj4k8N`7~>_K8*0ZQ1d06$#D?nqjKtlR)Cm9%oq3n2&I8;p*hz(6E`5-n_yb8pIir0hKP`w>6 zHmLlW2jW0|xg3eT0g1f_#D;1CK7uif?dzB2f<;ufy90SVmCsDbHT|Q1M+z?EOgW!$|B?NbGa<>unA4u#!NNkof zh>+uevcdirfO0@-Tm*?NgTz)qVyhytHIdkcNNiIiwk;Cd5sB@2hCz%0RzmqANrX;a z%O-A{fFzQF#Lh-y=OeMpkl0nz85!BcJzJ54dXU%?kl53a*t3z?i;&pMrYAD8iHB}N z6555t-iO3KhQvOF#J+^YzJ|oUH~lOln|S>zB%yam?5{}dpGa)RvxvxKMPlJSbn9Wdx4v5k?~R!D3+B(@t8+Y5;ugv1U*V#gt|lg@G@e3Lc( zEfbr#WEqlt6%xB?x-2uBczrLD&_pEmOeFSPB=!;{_6j8S1|;?tB=#O8_5mdJaR?i7 zDA;KT2OM6Pk=WOf*!PjxkCE7~k=XB%*x#q~vapHQGo3?(2pbZc7l|#1#Fj*2%ObH= zk=U9@Y(pfrDH7Wj!k)gEg-uY>6T$)e&liauI{hpQn|N*_l29rVI|qqffW)pqV%H$C zn~~VkhBbvkOC50V|pz}+5}0+0*UP~eJx1Z z2T3RZi5)ThE=W2BNhkw}T`--OolRV_21%#^iQO^XmYq$!ehQM%3?%k^B=%w?_G%>d zdL;ICB=&A3_F*LUaU}LR2pf`2EpM#OpJWgmRJC zrAX{bBz7YbyA_Gui^QIY#GZ-7o{Pj@3Sm!g=42C;+z8=-!*(kYd++qMoNVHfCy|8C zBC)SdzYCInh$QqBiT!puFBhA*>9!zg!HbB%7e!*rPR|8NYa$8hBC$=U z&jm?4A_=)7v3;kX1xZID3B@9@Q>Xt0Nf#msl_Ifgr|WXFiA#1O3H2her%sOrNiRea zT8hM8JG~bqy%R}jFB1Fc^t~YIi%3FOk=S>qzXeIZL=t+7#Qr*6mWNGTlJOEE)L4<& zywiO_(vnC*vPf*z>9rtfLnI+nB)0AJwIFFvBq3iUcIfoGAn8OTp;RPx?sQ&WHgU;H zB%xX)cI$Lokn}_(p{Yphxzlq&(kqdK)*`XDPM-^sK8PfA6p4Ly`dMB!alV^KLU%81 zkK<#Ln_J&6i#P^3Ob&5^?MDzBy8GaeJOcwGq@ZDFP(Yk^`5(jvErS4E5vIhz0J;|$ zlub6OAdXz)Qe|LZgdRX<31UM#%XuI+>|C##AP)4@s&61RT9(fNu!9Z-UsL!C}h4zzE%9VF+SF zw@ie9*wCF0+YGh7C7ple80*)cFMLf3v= z0$d z4WRI6U|@Iz;y|a{xf~c67@;%ZIv_T5jyW2{hRzumf!NTQ)uSLbbawO(hz*^{)OTcH zV1&*y#(~(-X~13(8#+t3ryj(CPQkqfv7xhE!cGhfjQb%z(*m)f^FrAmHgu|H6Nn9+ z==cd@L+2G7oDswOy&yJp)cg~O4ISY2c41&(JkG$73bLXB#DR|eZUwQSL$j|yZ0G={ zxhrBUunxqAj<%f!v7v)rUqEc=AeO8f0|RVmC~N!8^=!*E>*E<17_wy<7=(ft7(fT# z6++pC3=9nAP&Ozt)dg zL3e-dmSw1C5DH;n03AAW5Gnz>KIk}<4Z6JdT0j3v}4cgP}2W5lyv?YSr^%0=RW?;wxaUvKPK*3cE zWrKpN63PaJ5a>c>p$G=>4Uw%-aTf*#hHfYubcxDDC>!Ma=}s=7H=%6Mez^NkHfSr!Qz#o0 ziZ7vTP|5NK#Et}oKLY~;yF3GfP$b0nf>1Wd_u^1C=m2wBC|i$#fk7F{2BiZ{C>wP1 zm_C#ZN)x6~HYkMbplnYD1_l=>+na%b!Arg#VzDm+1495*0u)?fP&Vk$)EFom6m&^Y zb`I#=DJUD1JMy6HI?%uylnn}%DkvKi60K17Y|xz*Q1%i~qMHQe>|<>zC+m{AOD52K}`f^1qKF?dQdsR31x%Q4L_6(%37jOHppWNP&Vj1 zVRa}Qlszqq3k3E1_mxg1_mKek;lNmAOK~9JRk;TgQmh{pzL~4 zQ0WHcC@?TE=t9|`V%P-A206kG$_ABJ9#D2N0|SE}l-01H%C*JCKoq;TV)1 z&d9)U2Fi|QWMH@kW#=$5Fg$>=K?D4+pzMW=3=ChO>>Z2@4F90)Q;ZA@97+rfLiKSB z4Cfgc82CV(I0lAGj0_ASQ1*RB1_mi8`xPStg94QOj*)>u3(Ee<$iQF%WwSFeFjzs^ z0!$1H4p6ob69a=Alr6=?zz_&!YcMe|)JH%$222bL@ldu069YpUlpV&zz>ouFr!z4y z6hYZJObiSaP<9m)14A8@-N3}a&<)o7#LvJ$BLPh?;KUEKZ~Dxtx^z`&@?z#x>!z@Q7NoSz)%cj^D;6pR6^Opj0_C*P__&s14Ap6t;)#2(5(zA z|3SWFWMG&Gl`vprV3-bNn=vvl%!RUD7#SEAL)oA$T`QsNP(}uZ^-wk_M{I?%6G2Xk3>gdz45A=5bl^e($_6<|9m)ndNEgZmWn)7q8&tcxfY_i`45-}) zWwU|Wp8-$~s9q0)vO)EF43sU)z`&3MWy^zVFen>TuUCTDpym(*14BKO4RTNyl+6vg z76{4~VPIgG4rPOmDVqyo*Jm>@fP!l=h?C90V9CJ1uoB7!U3R%1$_8yQ-wI`e>igYL zHmHer5XuIH)^R8s)IdE8WrN!J7oqGD1_p*FAU1Slr~Va`19J5{C>ylqnNf{_K?pkJ z!wzMG)bK*tAfE|C+2Wwm5XuIHkUW$PYVD{(*`U%>8_EWy149VAo&nS*H-~T-K)n`Q zC>vCaJ44y&3=9mOP&TNM=?`UtO3zRz8`Q9jhO(zHFfb%S*`SU`I+P6>ipYhsL8A%9 zYM}BzkAVTy+^&R5fSTL&P&TO1*a~HX`fS}$HmDgs5z2lCidQHb)bySUW&dMfU|0-g zb22h8EQhj%K+fX*BPxuhZ1~u27 zL)oC9{s3izg8Cbj4Z8dG7nBXEw0PA)%>x0_=$xsd`<>x`!pxdZx zplnbsXoa#tWk4U44NAaMplnblbrzHjs)83l*`NbcmO3=E)-$3Z9?lyHti*`U_yStuJc#B>A72Bn+(P&O#tJcY7BYbRbq*=&pq3}2ya z4$%4v4M<3Xs%iFmD2Jbsfq@swmS$vN5Qeg485tNPp=?mgRUXP#VPs%Xg|amn85p#o zY;8sc1~VvImyvvCL&w#Sq7#SGmLD?OQ3=B)4>>fr2hE*D%^1pzA zp`Vd~VKY=>3L^uDY1H(}$dle%C!)Yjc8zTe5RVW+O#C`x}?_p$M zcn)RnV`N}>3uPZ?WMKFKWuFDL|Cu!*@o|ljfq@Ik{>aF{AP8lDV`N|uhq8Y#GBC(O z*}oVW7?h!GCME_39Vi>rZZLwf1(_HaETC*TCI$vOC|iMvfx!jD2Av_V&&0ss3*ro!ELr2&Pplnc?Q3hp$isTw78&rNYLD`@#UI&y7DysXS zY)}@hp91B8TEMfQY|z-;0w^0)$Si}h%|X3gC>zuQ-UMZbgL=DAHmKM>3}u5V##2x> zsIa>LWrHfAYY=ul188*r4ur!18eDu1WrM~8UPIZSF@S#{HfXegfq{Wji-AF?7*bdX zK-r)|Nes#cc|Z=z28|o4K-u7P$DwS{XqkZ)sQfQxU;s_3m_a2#<3Bb~HfVIz3Cadl zuU=3#s2~b~va=W%7~-L9P_>%|WrHfJ94H%9%ojn~pi#66D7zgb(G2B)y2o8mHfV@! z0+bCZWTrvcpv8Q1pls0K;&Lb(be`=xDEk=$1H%?58&nDHfU>zjxdy}rg+FNUK?_v= zmq3E?4pahE=D&inK?4P!p=?k(_z7i$MlP7N85o307#Kjo%ME3Nf>#8}236})P&TOX zq5x%wF)%QwLD>u1LQ4MC-GcbS#lKMa#P=qlsFie56L0M}Sl+D4wz_0+y24$Po zP&O!3HbL2-X50=a8x$%Bp=?kEb_&V{h00|p8#IJ-vmVL;wSezK*`Vz76v_rA%y&?B zECU0>7brUcbnp$74Q|xxFfa&}L5A?zplr~D8V{5WnjaH_vOysy0cF>N#_i>x98k|x z3CacqohgV7J%-x>$_9msJCqH|a=uVDsQn)SWrKRn@lZA>R8paAP^e@=*`R(wjSi^% z2RW00fuRW`Q2|Me9Z)u?zupIBgG#h1P_`myvH{B01Vs&$tp~b=2g-J0U|`q|VuQwK z85kJ$LfIe>9EP$vK<)pNP!7nlvrsn3vIihGsB{7~nW1cu=I#n8`P5Kg|b1pNdd$LwN^m60K~4Zf%sSl#HoR3HiEK2n$4hWkY-O18x)ZY z3=IBIHpt>AC>x|E5y}R&8PlO`P-`j|$_BLoi=k{#Vyv%)azIlj?NBx-q4h%9psY9< z$_AC~Gofryr(!;o4GN^CP&UYOtD$Vr{OLw08#LFs9m)n}(Y+9MJp-tmKMdh8fSOz< zp={7xgZm{TqhTR~u zF1&i6^1mJu1!7PM(8^$WC>vCzszTYImaaCG4QlBcLfN45zzWI+wR9bzY*0(r4ax>h zVE91Upp+j3Wjlb%{|G1t6a{fmHmD3pg0ewFxuqaBsCool%?D+J;=TpS1~t!np=?mL zoCals67?J?8`KV11Z7Ku&U?@UmH!P444@wFMyLcRYi)vDL9fq<&3F;)2 z4Z2?Z3X~1%nBIr7LB;t~C>vDYyoRztx$z^E4Z6de;SZDp@*J~11A|Zl0|RJAo)gLj z4W02r*;7Gd08ln)8buPy1~uDtKx|OspMinF9LffTkR6l_3KbV98{{!BFuR_CK?^kZ z1Li<#voI(dRDi@l*`U#iBq$p+SCj!|gGR&iplnc1DS@&m2|tIY|sG0ekdDM#9jiiLBR$Z`Gm4TWvxbg8>7BP%{IA6$1l>s9p=?lh zdMA_(nhDttWrHj}3T1;Dlc%9AO%iC`UX5u|c<_f{M>CAP#8W z1XQm>*&qio7&0&jbulo23L+LLTabZ)K^(*e4S6syFvvpLAoa>nHmDHOgt9@N(TB1@ z&3scR8&qZ2J3u+0cyfobLGk1ZWrNyl!B94+UWkOULB2_WvO$$$Hk1vjp9-ODkblad zY*3kB3uS|{Ycqsh4?5VCp%cPk0L|k~fwDnEFSDU+(5Ux9C>wOn`En>5H1x6-$_8yo z*$ibfGcqvjfwDo}??X_wBqIaE2`F2hk%8fyA*lTCW?)ccWMH@sl>m)^--WV`85tNJ zL)jjT3=A)!>|jO)hWAi*B&dH6WydozF#LwHL32WkMhpx>-3$yBj0_CiP<8`o@EOYP zt_KZ1Lpc*bgU?VlsOPH=WrKRYx={8!Mg|6BC>u2DZ3$(AM!oH!?467Z46ac2MMee& ze<=G3BLhPulnt6&iZ=q4|J@7>PZ${(GNBUBK@$m3_E*qE0+js^G?4&hGk^w}p==%| z28M}Hwm1_5!*nQHmWhF3E|d+LXj%bfgF3S7p=>86hI)prP)-UH1H*188+0=EK`0wE zT74YKZen6!I16P@Vq##p3}tU;VqmxlWrOB~?nBvom>3wILfMCz7#Lnd*=Lv-7(Rm8 z^$ZL*m>3wogEU}j+G zhjMl@GcZhrvUf8xFwBOs4=^(@EQGSpFf%YLhq5m+Gcas|vTrgoFzke~A2Bm9?1!>B zSQr?NLfJwr3=F5CY*7{lhHJ*4^1qvbL6(Jq;Vx7{jfH{XF_i7d!octn%JyVoV0aH@ z2eL3Qe1)<@SQr?7L)ob;3=C{0kSNPzVPN2evddW*7{s9L87vG8@=*3HmU;#T4Jc<0 z3j>25l)aRNfx!gIUd_V5UqK~q*oKl2I;i{ zu|Wg93=9lTP&P=f2b2xc>jPzj^v0Wl%70L|mw|yH6(lhc(g4YZvOya1p=^+bCJ-Cc zm0@6D=zy|87W6^cpl0|KC>x}H7L*O@FD!tvL4AZJP_{Ox{l6W=fv*4D3uS{0JppBd z`gP}_Y*4@MDwGXsnB0c4L7j?+P&TMx@*K)`V_;x-3uS{EDW9Qi&`iruQ&9OonSlW` znD8Ge0UFt2HDh29n#{le>f>=k*`T2pK`0y4h8KmhK_1Wmu|X9)XpR8N26?~)$_9DB z9?AxFLfoKiInek|0F(n7CW(Tw{TUb-5}<5QuP6=526ZrUplnccy9mk#4ZBr9*`PVA zIw%{|+-`xgK})l`plnb>c?y_a&%n^bz`!sM%wb>vtlqjr6rgNS6sSYlpf;c`lnol5 zF^011L47$(CC>xYM8lY@Ywrqp4K@-vwp={9luo+M`D2vX6 zvU@?pbP#quILobqa2P;Ay#dMwt?J$eWrO+!d!TI4;_3rXHfT-QWe^+GqhMfQxCv#0 ze0(3u21U(NC>vBHzl5?uCFvgvQ27sCCC_BZz#udqQvP#5*`U#IJ}4X1r4oU%L7JtY zY*2Sv0m=qtEj1_`)JfHWvO$xZMo>1W=W79F`+|G?WeM zQYAszpah!%WrK2Q9+V9Vj1njtG+I^CE7M9`x65L!+t0mv=r|sl>LW+f#Eci&BVySa1qL8 z0j>YJ1?7OIMjt@g+>8ti&!B8UMh1pAP_`7PWQ4LoE0}&j*&3jd5y}R2-&m|5QE392 zRfV!av!23GHfRBpB$!>#z!1d9z#tFiFff4nZ>mr>Xa$otl%2}Rz+ebvXD~7_SV7sj zpea@;JD-t(!3)X;&5VXZ*`NhXF;F&WqB9A~26gK)>Y*G^zpfC<1}z#ahq6H@UDra{ zTR~H=Q1)&{28K>38??!P5|j^98hK z3(5w~XdZ&HxtSOkPC(h9zT8D9+lGmO;TDwb%*4R(7|M2KVqka)W&1EOFuaGdgP0f? zzCzg{ObiVFtU%@ed~Jl1H_rnz@Wj*z%UQWwqa&qSOR6cGBYr&hO)yz-7Y9Qj+udB2b7({%)oFM%1&cu zU^oqBgZhM*pzKM^3=B7*>?zC)4E2wooTbbR3~!)pP@nKSlzoz!fq}^e5;dT{A19Q3 zies6p93m>C!hpzMFl3=C!vc0B_N3j>1%8?!JlBtzMteq#=l?Zv{tPy}WB zurM%GK-qpQ3=DNP(DFZ$g@K_HDiO!Rz%T*IPG@0Ym!9ofEDQ`=pzJj)3=F%V?5!*e3BlRo{49B1xP{;8Mlnv@QUWKyn zvM?~*hO(csFfcrXvO!0=KZmkEvoJ8cg|fe~Ffe?Bvj4C!F#LhC|FbYKFxf()l7p3j zfx{MB{tK`&Fz`VoK%GtrC|in^fk6h!)?j5|&vDwuL7|_iv}1N7}i1AAn}7BHfUlAw4f2phR*$*26Gq~*cliY?t$2#`F92e zhL=z_Nb?6M8`PBk24#clenvY62BBpP44~n84k#Pcf)a$XK`kY5C>t~$EDL3WT1U$D zP!6cIstIL-mU!qx*`Saxg|b1dSUV^i)SK~uvOzN^K~OemULgj`2K8&xp={8Kr#vVd z)ZQt9vO#xPF;qc0pzRf{P&TN^)dOXN+60rJY|ui38Bq2cP|pd<26bQ-LD`_i$Xh{d z&^$Y6brqBi3dLhkHmH?+$_`ZiFK1u?br|k~B%pf>A4Az74ey|A(8`rhP&TNq&uY)W zAOxBiWME+6hO$BG1)*%vG^{9;Ee1LX3dDx)QPhL7nL+J;6DS9y!2-$#xy~EJ1_cRd zx)sU>S&#%`gW6S~wV+ToNW2on26YY@7#M1yY>@Z_5F5JLaSD_T5?>Bt*F$$ct_5+{ zLmHo(p=?m&b0?Gy%4YkaY)}F`3}u75*4IF6P~#5NxrDMo7Q6+qp&KYaL)jqle^54P zP@lqjrvLNhw@Q$}y5C^obj)8%p8OjD3+6iTYeBTdcgWB-3plr|*+=Wm! zX!2?~lnt7qTMK1_TGgAOY)~1q6Uqh+dh7+wzY1-IEH1tPl7Q|Ry#i%}9Pu2)hVCDI z3uS}EKSSA|X!;3dgBzvO zR)(@c6O`&uHmKWd1!6-tu{uE6AP2cY*&xe&plnbS1VP!LTo49jgW^8Z5mf$zdIAg# z4EZ35U62G=3T1-~s)n*b1~o$2AcI<=Y>+`SKy1*y9Z-1yWrG~F1j+`PvkJ-vnX>`P z76X<4Tc8|}LB~OCP;UgZgAK|C8FU%S1{rh{$_5#9AIb(f=rNQHGUpqJ4JyGv$4o-m zAamHA7#M{1GJwY%xxwsu1_qD@IS>cBwO0ws25B$_u|Ye^7#J9=p=^-28sZ>~bwpcOE; zp=?RehBPP}l#ic7*&xf_LfIh8K0?_b%UGNl7=)mkpZTF|kX>R>HppW#&Y<%DFara~ zXG%~Bkk2%rY)~%HgR()RAtq2ZXd$8nlnol7@CLC#i#`|_7y_YekY(XeHpsGAC>t~Y znG9u1fy)0(CvBB ztb(#Zp4MZrsJIn{ zvO!r+8p;Nxa78E^l!MfvY*1CM3uS`_n2e!p(5Sa1lnt6|wui9m89>7%&JYfR8EBvp z#0D+eVPIg0fwDnynFM8n9G3xQgB+I!WrL!r1j^QDU|^_#vO!I;ZV($ZngQC50cC^C zobCc@|DRxB02w+LDgiQdF_aDR!Ad9_~G@jRW3;vXw#Q|05^|)J*;gVuQw7Kns*y85o34L868o$_5$A3uS|bR)wK#knbg- zY>;JZp=^+4o1tt_uGtA?gBF|ahq6JI9fq<&KE4KGLk~u{17<_p|Bt{NNIG}{WrGTe zH&8Zcyzf7V4H|J|U|?W%V_*vBc2}0Q*y`oSysIjU6VuRN1GB7Y0L)jn? zTh&83ARoIz*`OYe50niW?+b#mK~1>`C>vC3$3fYkdMgRa28C)Vhz;5_$iTqR0A+(3 zDeX`;$f3PZc0H)_m;vR0)_u%}vO)2;6v_rQl~zO9pu;IPLfN2IEZd=MkfZlP*`RLP zVJI84M&%@w4RX_YC>ylv`l=g)JA=>#1_sc8;sdAzXg}|BDEl*L_6o`tU}RwU3}u7X zar}g`)fgEV{<>|yCCwh@#mF<=Fpb@xQDS-{h*Ft;5kyr?S4?O3=RF|F3@%4F*T{)`RN6EoQTnU+XR-;}}b#~3l4F_Yb& z(PMgGCc8h=0h#HGGQpxBL82Yg9kbZ|d5_33Gk^waL8i-2pJ*O0J$*+Oy9T4j^oLns zgAKFU{TWN9H-f01=@+v><||BB%3=3oG?`wQ!|u;?L~;5d5Z7k9U@piWrRhnz?0$?K z(>La_`!iZhXUt>wXJnWj2%;pWF9cB{(?5bJi|LN}U}sMRQ3BH+=Ck`V-O!kBRKV`X z^g&~KQvtglqs#P*1?>KeCesxQ+5MSbXiYCFWcTAepv}wx>UDwK?LEEFE?#>2i$Zn{ z#*FELMeP2(8+4c%N*Ea!K+^ux8KwQCr*{;wYcQ%z-&n-%&$UFKnE|wZ*OqCz+$15n z=?R-fSf=X~v#T)5Ob;w(_h+n`z7RxBnf?((NlbSvVfSY=m_89iO_=_$1msV{=|-jO ze!M4)m>ED-7|5#R=^OW#OHW@>%C5mEGyP&I$ic?bmCD%t7(J#Jma+RY&Y6C&jNPC2 zg9$Tel^WQ6xzi`!;g_CnQO>Txs4zXToZX*MXZl7EWig$xg596dWqKfp3YfkSLv`rYC}^1=Bayu=_LZu$j(O%kIZ?!Df0;ExR8h!}Nu`oubr<@VDbfw(-=4ePFD zW%pxjm@e4H?$6jWJrP9Bn7*+Ml#bn}Gqtn(F>P?49t5KIxKCdMqEEO_|J2Uz$0#%1 zv4h>8QDgc<5al!dA&BajZrBORHy+FkpgBlTtUsPU@hT|RJJ~fD8Kz(C1m|SME_Q#$ zgz1GKs%84YE|B9qrwetn`!SvIoSp=tKX^{x)Xnb47&D!*huxoPkJt2|94wkrs6LPfeWtJKV=rS=n6B8*?$30^cY0AjyB}lD z^n)Po6aVQ#6Tl`XP5_x4Fntq<>oc8kA~;J1f~cP93qh30^p7AaXS(Aga70f8Q5@4B zf+(NqhLb^QIAMCzWN@mwI2oLV6{mm$vv3N#KhufS>4&DU`!TXi7o5uO&*(5caVon% z)0yGPFQwBjfw&6O6=$;hGcK53IFntQv2VJdC8O~44KvvV7x8>a2S_85n*;gg=0UbEY%SW>;t3;l;pE1rc_b%`U(gF+C6@Y~szpaC-Vd zmlzQN2?hoh&_+T~3y6V%!DISDkOBrj28PAcCwk;yDCn5}5u{*A00Tn-#9)It>;jA| z(;erqtFwv(GB8*}gd0G@4AUoqgaZN@7|bBT7eK-jrauG;cLXvp)J$)DtRx~RiRz3S zQ>GiuWmjWm31VOnhiELA%Pzq5X6p1Nkhn|`1B2dl$9w$3(+|vL7XX!7bJ^8deS#Sn z!Xe59=79op`gEmv>}sq_f*BZGrXQRsBs@J~9=iZ2ch6&2XMGXM!0>Fk;zm|*4Cz63dYWl;pc#-L$f4%q_6Q(Z&neii%fq{Fv;UxnMCrz0C z5u|`6ih)5MVzEs+WLINViDF=oo6cC8B_fDs`HjWXCxKMBL@_Yjhv>Yp z5L}HvT*$7@suIn>kOL7`Si~;CSTo&l5xY9;glGnaWf0*4kTApaMv$;Y3(gvIOvj4IO$LBck%3=BaK<2Ed2 z7hpQGa{8gg>}sqNVi_3X!Q#`FunREuOcz|juFm=)mVu!QEIK^^B%Crm5hPp_2MS8C z*$Y6zbEa4DxcA_8dU=}cb;Qs7X)zz{b*@M$@Q0-Na{K?)WWFfb%R>@!#m zih~Q&omPX2qe2D-6>t_oH`!(S#MSKTtQv(33<}c~--(I{$fJ6tVfsUm0*^ul27&1x zCklyxPToQ;dG}nLZnTD7jWq(S0-P2L*02jOUAZ{D2_&9T2uh=%vH@M^n~T#gfmE~< z!V61*wcs*YaV@(#>zqP(eop`i%S3GXRnU=W1(aRW%$Wcopn@P$GK2Ak=P-$g|P z6i|KOGhJ{UyE-dR5d(u7L|?!DJV^?D}DPmwSfru|y$1cEVFnuFPc}5W; z>Oji3T%OLfo?VT#qKJW^45Hj&Jt*H^o*o1e|4;;qJh1mCfW-G)nZ5`l&QZ+3U<^_J z03?3p%Jfelahqb0?;0BmML>ryAqS|ybjJZ~zf1z-akHn0mY`b?h)60QLYZ#-Cz zp|4~5Ly&?wUxqq6Wl~tJ94(va7M~DP~|Whd8NVBf9`2!}P|D?CPvvis3#! z01}=s{US)1r392w!R`>)1S)o~O;_5)uEy$7!oUy#F(qLWxP~a)#IDY|03o~qr2NhG z>4!kdf0V$g2tg%OXRWz0U1&4A8mmt!NX18ac@Y6L6*A%STbF4JG(k-PZcOfJ6_=z5mZ6- z@`^{(i?*|?v976t7w;QD8c$3=xSd^{@y>L?9qi)McCZUDegHAmSy`$WmiCH|}5;pS}PjGbT)D+{rFJ{R2p-1jJTn>;NeipYE`eU4U`H^uV2< zGQJvAmVnKh01`eieIZErPBjCA2*iI6K*ArUe*_70)G#oJLWB)=feTB=UF_}D5Wt*8Z6@nH7~>|qyR+%a8o54$>J#&pj;?CNYMIvE(A zT$*0Chh2%agpq|oVEWuW?8=O5rXK_;vYh^M54$>3%bDpyd)d`kH>_l2keDv`fnRuf zz+P~5l(?5&o%O_8Murp9Cl+%HPhS8Mc9^~qBs^goBLma)yL;J{*%&fd8D11lXWPfF z#5(COBSYPE-F@uJi~`dG_pz(9dZ#flSWG`?!6-a^!ajBZ#^&h@_pz%py|_93)IN4K z#_H)GLEJm{r%UZ;S7R)m?zo>_ooUUr=~?^P)mYE`Wn!?K{_wQ1@bnLwT zGc+cqfJZ?r|*2st{{FyjDdkk4K%6E^i7a~fk^{2dB`L-{ljB+Ln$3& z1_q`Rps8LKwg6EE2BwoBHXGYw{prEk1?opMSz`&zmjDz`(SM z5wzl$uV%XRQ+8{~Wm*gjOzRolKr5O2c^Md(zJPCR;<`FL|0%ntU<>H<2^MA+)=$a| z49qO-ebY}qWmi%=1)5F~2kk&$6z{NMU|z?N=}0m#uM+7#P^albIM8IK*ha1=u7Kl;qVBI1NT&qE5d9a0p zbc=9$vt5Ea$_K2TK_DfwjDgb^><$5l)qY^jLJ*Vu!5m=*E@hBA0@$X2Op>VQ3}%yI zXJ8NnyCVeR4v0~qV56Y!2m|Y8gSappY$H1Z*B(v=2F?h!dmy94IiuJj*%=rFGK;bq zIHSQz7zD-H85lTY*h)bw4+S?_Ffee&vQ>djgJIxuQe$A?tdC>UU}s?9mElZaTg}eE z!1qaqfq^p-9OisqO&J(ClfVJR=LHI90|OUmnHOgo zTPiyP0}l(xI4N+p;oQRZm7Re>+=3Of)$~Mf{WiC@ToE zF)*+(aQ)I`VBp+4{lzPGJ)Yer3=CY!4jc>&vLVxzUbCyK8kjRMaAoy^*0`{NPFCW| z21P#$+iztC2Cf_sn~m-0^t{*Xs`XYn3=CZ9lQ|d|m_R25aODMXFfd5;h%+#Va25RI zU|?Vi1Q}KcVluE@R%Kw|D*DgCz`(+$Xvx69RSZfQ9Blhd85p=qKq1G&z{9eU1LVOy zAT!Oi85p=qK}^;fuJXB@3=C{v^%)qrDnR-e*sg#MpX90paah=lB^emFsz7Qu*wTd= z7`UoIF6CkC6l7rFs#(m*z#zZ|n!Dqw1&RBxIcPC3aMf+*WMJ@PGo2pwhFzI)`t-Ut z>_&|2(>K0h7iZiu{Uk`xa{Ajh?BY_VtQi=%=GbvDFmTF)QUcdp5PK%0eAINgx9oED z{z?oCT=UOyGBB_za7+K^VqjpC&|_fWmI1AxVqk01Wnkcz1+f{~l35rSxaB}>CN|JX z_}ua!HZvP2IdLn1*eq;bIt&cliXb*C+gT+B25u!#1;)lUjfH`MTNzYGaj=2T`Q=uL zWM*LCVw=AEEjy3o5pf0vZZ$n-P$@h`jDdk$9b|$8+qLNr-m)vXsS7bM@PIA>V_-^? zU|`@01(gC^+Ug7pJm!p`P~;cjsbIXz&A=cCI&_k!5?mEA2%geqVBo0&a~K7=r+d6( zcVK)yz4INrn#?Q}1_qvHuoRyly9omWPYamC&%iZ#`ssJ61UOt4V>Ph*yFU zl(hMrCV3SbVCAiFLD1Fs?@XbC*C zVEc5LkL;mhBB1IimNAi!fq|ccH-YgW9|MD6^{DQ1l0XJ8O~3-U|}*lq^Fc~T4vyrp0X76u*` zJ$?oTuFb{_47_EGR{RVM{4%^1j0-`!KnFVVRx*MDltCaTHIIQ8l1fAb!B$p-t(2%| z;BwVwVBoD`EC87VI#h$Vjxmgffr0BN$fkNmH68{AejVOM#tH!j2Ehy=1_s_H#um_d z6oPxj85nq*!4fQj2dx+wcv~3j1Q-}N1kac;Fz~iAwg@mV@Ca@K#c&&AmjI~JnrXnm zz}pU1CL*ZHGM)P~yM!qt$f_>J2?7iZ3WAOb3=F*8jMD@d7*qrc)fpIgdl*5nt|6!h z3Y}hXKxheiO^^7@Zdf0s!@$7X&v+E%`pY2qOk~_5z`!7~Ux0x@^b=@0maEi~fq{22 zSeT37hJk^1CZi}fsJ$r0z`#3)Q31rB28!&(V57O1lo=R!SA*I79K7oog9RBF1f@Wc zw;t>e20=HFt2Tf*(>cDd%hnfxB7ZaEbpZwjHbGGFz`KRK1BK9e2-{tifr0lvV*@DEeL-seK*axmLV_8bA-VJ|7#Mg(!E9au zUU8+W~Tk z4ih-(3hGX;|H>}K*gt*NS9U!au#_oO3N-V~YX;_UFmS0(fAW=Gp&qn?o7aXZREU9r z&jGZX*OqAwh;0K3MLQ-{5PO*@0|T!;gbg|sjMstb8)%^oR|_cDJ2EkWY7IUn1_oYd za2RmyR%Bq{b%C(IfxMXuX7e-h7BI~gW?&Fx2RXTr=@SpAhr+-G+A7Rj#MC0pz@W&? z$Xm+v9Ha3C71B%j0raz#QXO-S+GBEH~F@Z8X6C(o`GY10$ zZ#C0$kegHQTthfwZh*>R@9qVBk6ga?5HaP}7Mk36x0JFoD`W zTx%s57g=85k5r8F}w8y@6}L3)RjuJ^Kf{IzQNyhhR4fFe*h&U-*OFB58&^0|W0f zrZkXtW=7suOcr7=*S>~n2l?j>#I=G2px}PX^p}T$;lC2Nbbk+yJO)MvuG^sC|H$-1 zl!1Yto%ah<2H2?S)<4GTUf*+uHbL79mcEXW{u48-9Fa~K)84uEPI z0p@pN3=CY4Kn0E@^BqlhZ^;%HL7r}f&9NavO1672P%vZ!27!)}ed1IJeBw%ih zgK7Y~H6F>W;k*e@$Etx6aw62R3|tRDMkg_|NH8!cGBNU|GB?2uOGh>=1IaMnOo&+w zT#u(0{AL&7Hv@%n9y7SCXW*JRee!R1U0%@Hdc38~pajTwdivSl?BexvK_*y{4RvkE? z_*Q{ZKt1y#keQD`MOyL`8~(7XN~(bZW*Ru0xE6w{sd?ZS;`%WC-5+)>#!1s9|FWwx z-kWa!mtBEz+w_FL?Ba}0(<}b6E7!AuoOh5JR3&g}fC|q;5Usl;85npEgT?uUc#ks2 zNi#4A7J&qhF&BYW{t0dZCHUjaby5rrOo9hMT2C-{fhOz(SAmqBWS%Aks^1(y+3pmW z!!8KAg@gAr^CBrwt-p|kfkB-24D&iE1_my{1)ys5ESSS1Xgb~SAG?|tBPbkigB`># z!TW%jAJlmV=c$Lt@%;!I-=ZL^9)lAzr{H5&1_s`zU=EjH`t*hW*d-Y^OyB*FU9J8% zC{*7tgZk3KkXFK5upJ@{T#lgF{lHu%&A`CV$orYu2xMag$lNbrB@7H)OF`|%uguai z;HKLT=6sM6u%muL9d!m|$S<&ZHbHQD`wdQS>y^N6;$i{i0SQJ1t`DFzz|B$(a+3%nFCU8| z+)ez*ZW4gH30#s2f*aqU!t=Qb0|T!R3!f|lgNh6zuNcb|Sq26^A5f7h&H{=uzKI|e z5-gy=Kd2&-0^7%@4Qh8uvw(t=fh!!8n`BvhWf>T_R)f-(0t@Im zA(1_@3=E=K(hLluAQl4;*e9 z)q}jN%d!Pjma>D&KYf-SP+Q6b)Lt-PnE_&hPIcimWLW}Y-v^aKMl2gZ><^%#(UJw! zRp0`hpTg_FQUVhH4DyH*i@zKLgGiJd1B2)b(CTTf0FYJ}mNbxX7fg7186$^6y$8!Q zkmzcVXt^L%2h@q{L1lms3#etv^%_)81hE_jDLw~M3?dkKSj^=Z7`QkU|<5B)5bR~i3c`< z$8U5|fq_BwEof&Hqv}0V1_nk(RnX8c6QimcKLZ0Zqv{J|&}gyh3| zM%4o<3=Hgys^yvt3>=KAGFl7_oQ$ffHVh10jH;T-3=G_is-@s+rC!w<)I4WYT?Q&t z8C601H~AS=|AGeT7*$nt85jf^RhNKvjWVi&j$RRFRP9h?U=U$c?crl!5M@+N6k}iz zV^qB^!N4HSs0upISb|Y?zcd4bB%|tYaRvq{M%5cq3=GnYsxv_iRYujjObiUNjH>Ik z85rakRqG=R7#QRkRj&y#Feosp`YVD?gHmN-WnfTZR86vGU{GdMJ*~&Upu(sMI;35d z5i~N*pvI^gF2KN`&Zyd=%D|w(sLCe9z@W*fS|!84pv9;PN-o-rs=q847<3p_bGaB8 zbQx9e$uKbJF{*y$V_?u{R0W+;ZNR81STD`MV92QYTAG2uh*7m)je)_KQFSsi1A_^p zs;v+MgDIoxL^cKnGe*^Ste~?VR1L%#7%Ui7HB=ZFEE!cn6Vz6W(BW48DJqH#462|* z!x)%UQB|K3RFl!w5*0`DFqdfYe1zK2LqFgJOcy&+Au{1239`)4JSZ1z(5plgeZ03=HBwLE9_Dop?b*XU)UJAuA6uR)oz{jDdmw5~yhE@fiO zXJm+hR(t%+;4u{rL9m@H;9(Lz1}=3C1_pjs#?#6S42lkn{9%lHRAAb}LE2%uBOtm3 zQj!_?BSE7z419v$6sJ3~bBJrCsWUL}$AC@L5Cruh_+!C6Wlg~XQw9e9I7T^f1_mv` z<S`BPhY@DhY#IL|789|qE3QU*a;83gw zF+n4zhd>qIHBgKdGID_OfCPUD<1|%R5R^jA1t+UAMo|Jc3Q2V6R{V z)qn!vE*yU)*m^+*9+q<;!>55#WEG<~$Z!MxTE=G}!y~})QwKF2)TrUF2W#UHyaUQc z4UC{ZrvM}{8yPlNz(;5In?Vx_o(rAGkyXo z6yfh>tb!}-gDC{1`hKXD;1n?d9DjU*puPbAMDW@0RI%m?QoN( zBAYY~Vv;~nYB2-@P~BbAA98XC*MlTL(eW14 zYgPm)pU-$0M2Yb)VvJLVd2=yTS1u?3;~q|%fK7~!3m($ zw;aq75_}CRSyzBLA`D#X^%xlVS22QG<@{XyIhz?l_Z~oU%@(L7+dz46D>zg*7`Tc- zUfIT&1xo5N{5u&x!5y^=svb0U&A*!wR04Ad`hmLkd%&T{BiL;PDjC5X0YUlc_qjL} zV?p;R@XPQYVl2>r`R*{XK}V1cIttbcHRu?aBOoXbN_oc_xwsh^L>>YmCR?R$PZ#Q45Ox8xX$62MsYDP z@ZW~$2hE^>nnEcco9-~yfXWR4{(Fp|GyNd}cOPoFIjB+pfUzE2#0i3q;O2h_Hl2@w zs~e>I5#vpW?q`hdnlRr#hw26m>GQu}1kDg}2%ZO3MK8e-&B?$uQGtPh{}rQ{Cb*<~ z%Qz9P`5jaJPpr{rC50`KVf^`Wq6={Li7jP+q60QhS3rMpFzZesb zHcYcPvStaW=HTgXcsUgOz^WK{SmuBRNTopOSBB{z$OtZeIVLB#5%S1JC_s#0;8Fk; zL9^Y^~1J12Thwhh+uGf@hoz4E!2Qeh>{hOm{$% z;385NYQX_(1_pjT$Oxt&2PpOGgNIb1<{3cEBd z(sV!>Pfm$}f!~@5)D4kf;9&uEK6qH1;K0By!*9oQ7i0$5 zZ}w0JfitoLQ@kLkvkope9HD*#7aUGtj(}j{^u7EXlJ#HA`{=IO+FRlIam#cNJ8(4JZ*+GxdXGGab~7tznui2wFh^ zn$YC0Wl8{zPYZ&sMBuLj>*o>N4l2s)nO=Yl6O@~NN039Z-U(ESHZs+MY!cybX0p(S z`M3qyrdDurOD`s|jG!6d?9a1ly~^z{8>q zvNsS^cuZmfod?dP&cMLH{~c@tSGf%X13v?J@P=Q4pM$x_fPq0!5mY^Jf`)hM85jgX zx3=+ffyc(!1ZRVi1vm3SeNZj|9e={l!`#6O3Rh5*o}U*w0tK2>;pbyMtIxo|E!YDp zvG|!m?KvJnHjssa%%GWn0l^!fY%9zR>dOlXf)3H=7XfpG1QR(J82Ck*>p_ijVZnW% z#)UZ82_le$B*6@t;1pxvItnUtrI>H(GcfS4;a6Zj3HAUe$t!}{41)5Yq^1P+;tD}? z7SIKGV9rVg4v=qe8bF)2Yz$n}BpDd^)tG01`YHwdw#>Hmh71gX!Jw|48?!BFftcV0 zP|vv z8O01LVYdiA1GR~xnL#OdhoCITaWTxG6uU?8E2s*OWd;7$Yw^clg2CJfWxi*Tsa3xN_(D%fXV1j|85Ee*{1DmYn)fq_3A%=sqx zAJnVO06YJO66l~v{!H*7EeDHI6SxlmHkXG*sRUFrWrKNqEJ|#k`P>|^83HUyCqXrI zF4)_GEK1-`a84eWE5xE?39>t%IYEhmL4-vq6%;51U}G#;lhE?ewDE+lFgW^_!m4O2kzaVwsIA&wu z$OK&&Y79+i>AiqC>>bGIA0-Xl~@&N-6i?<>JgSm}40|R3c%*~)PSQzJ6P8X2m5SIe!)Hef% z5TgZy708)jo#tiJ9VI!0)j=o1Li|!I2|8trk%7SqH2J(4WHo5X~v5%0G$oY!vY%j zv$ob?U|<9vf&n_OgK>_$1p|XEXiSgsC}>QNF~}A)sKL zWeWxdi+z?142(}e%3lra<@CM^)_m^f4z zOh6}FfKusVkXSuq6jLc8(}3hb1CF3fa|k34l12m>qcwvW=$sOeYe4~43R-K+;>icf zIG_^Su2Bp$t`52!5PTLE;~XVR1_pa@G%+)R(iZ6AIk>ANEEzNzph*axDD65yK`#zA z19Wl-TgA9jCJ;alcB1i(~KA1XBTaALxWKSv=9{>?e;7T3`Q^|U?+lCYa_z( zAHs#8TVud3w0m#Bz`zK){E-2C!VBY^sc^Tof!zi=LJ{Jc4n~mNDwu0vp;6D+!w5R8 z5gcH9S)c*-0^}N)60mE8!Id&Rb9CFl!wb|Z1-pia1vENtcOF#8f=*gxU;v#A!Z@eG z78YLfz-}^PWnj<+4K^~)V`Ktd&A}L~3mWxioCh9YVGPj)je9df6vHymLPn4=jA7uQ z1hxA?u47!vXlx4&%3xNg+v`{v7(mks3?LO?x37e_9kk#b6xZ&yV7D`IC@`3KfQmOz zl1zsRmI;80U{IkG!&Jh+U|nuj2^>7P;lXnWk|&|b=?WuA~ffD$}BIq|T7CJpRB)dAy6a1jSOZj5ox zQ+t>TUxHoO!p6W*uLD|0!Uz#q%ErK;^G%U~0m?rH;)8mLjIS6$wZL;W1_s?Ubp{5; zR}e3S>44@37+-@UoP(W#K^HVd!1x+GMZh$XK^HUy0F`E%$O0)t-!Xz5!Wa%t0`;JM z9N_Hqh0)0#>V0)~sP}`|85oRUD!^%=7BscWU;;W`2$TlG?ZMt>=5k z5J9GLc$EW@2c6IlN+Z)?@`9#}G0{vVpn96ofx!fHWI0IxR+zjlyq(AKlfeYkOaMt= zfk-o#FJpqqGkP$XfzFtNr7+MnfIKW`roU6-kgTt9fCalGc*JWCJFK>nW&+7wV}~RK z2GC*d;IdDVDc%7Z6klLLAO`gBBEEph+{1*08<73e%GkW(0VSpKLO zGBDV2foe?94XKcpFXJ3ICL1VOxIQ6(63K)g!W7985~v#fZB=RaTZWZ9~51T zb3musLHYnmU`u;A85s1qL9O5vCXgIslo_ab^&lDS5hl>do;)m|uC;>#GXn!-DHE*S z=?ZQut2r?+=q!@~%cwaqgfJZAWMI&d2H9N3q`dM8yU;-*l z-Xt?Hh&aJ)0TmR*3=C$VcJL2~-OOB|Q`UG`1g7h&a)|PFJ25cmg64@Br!ZMg4^-ul zt_KO#fXoBA7?cu0=h1;$84e6qpmVUG!Edk1z+m@Oje&u20~079ASG#?Gb}}H00%@r z7XyRtT1~JjkQ`&ME;wIpU;<4QF@`|$%@(E>XHW$S$~Pelpurb#zS+$r?F>yU8@QnP z<~A1tgAq&xII*yCgRF-)KJ=X-zUMGNG(P;M+pBR%v4V0)?({e{4k-hWCqM-zqy+|= z!{T89O?cVe*I{5_ybSgc=)hLSIbkj!A5CAO#$i+sVl#$f=)?;1SvSbgYurM3&h=^f*sQJVRT?H1GV7bZUr6Q z#KU4RJzkwdR7}Ga-t6zPa6{U^jxj4p_<6nCATXu%;|Zw5MS3+^;ZLuC2_O%4{uiPN8JaLBT)as!3obS_N}l{gR^-EtG= z3^%Cdph^PV3^L|L4>Qn87o>Wt+6}|*nQjQX;mt|VK1LoE&^)Ex1yJWC032qJY*g*e zz@Q5rQwRWu8Do&Hrz8UdV<32dhA~+81gMmP@w6sYSCaitrB2`Hh0QlR&ATP+Sra4yN39<9Y81$Qc>(2rARV6X$Njb;Sh zBEUN923^qHCgTKV(7GkYAc(Uj zFoT^H3~|;(2rooeetMubhf+P*S>YzIjM?S^2^JqnMGOj-B@iK`Iv3<%I>*W{4X=E&_GZw?Mcdy7C|+wlISxN*P0S zzJv1i7Vx;%JdoCX(`9uyl1Lc$?Zv>L3!0u}yaq{7LAs#r3NYUE{W=`tk|0Hlp;n*<9(ZU1 z6i1*z4yozybvVoo%i*XAnka=g!oD+ubTEcnfzD9` zyAIU00J$#S8!~X>rN^NF8BzgV6a$jk1eNL2gvJ*66$>;`N3Cb9x%OTHD z&%o#gUM32&(;dZ5PZp3iX=FP;V6_u8H)nqggPYKZcT49;83Wy(FcVqijj?AZ#W_wc>$Y|fpQECjPt=p zf<|r_=QQ~-FzAA&W*O&$mQ8}<2{bp$xB$Wn)&)(@GA@MhLUcj1v-OONSU|H6jG;Q9 z`B}!rETH+>5IzP5-Q%hZ42(-yKvT4g;kuydFvg`UpgCHmiO_MM-DxcA%3?lfktwXveT!8E6#qIM}(6VLy3)1_m8S$#R?pG;<3p7Ei$97+hLI zc_F%m(=QluNP{PD8Bc>pFUT?%9T7Mg4 z5NPt3@gK}X;Bfm7F&5evWn=}Z+XXTfHY{}!>RJZ|E6_+g)Kt*KvRyqWr-80KU|;~{ z8pb&e0WjA}u!5q4F-R9QNz5q8S`V5_h7F)dvw{?!1=#{~Jg7eoY1$#TmO+hPyAIG+ zcJN+a2GAL-jB~z&YymBCVYGlu2LwT?Yb#ce3}dhrsLup0!axTRg9@sx0n;ZLbLcsM zg6Tv6B$QkjOh8E!R7O362r(7I`-hA!3}&#QZctqX8KXTr&4feLyFQSCLAMK3>4dXB z1Pz)7=?Zf&FffL*f|fbK+GSC!Aa#r(@D_GJAjDn=1{2UQ2gu&M=?NwrlJNEdq?-Pv z20D|4k%576F?e`G9Nf1N2!b_j7K5it7=s|av&ATrB}-5yOO`-FCsY?ahP4ztS;81* z1_~Wn=xhdPNP7AY6At-c4p3&_1GW*=BVwG>3Ab?%ij8|vY}|`t<6fwZW}u`lJN>N* zhoV2D0Rw}bwjcuo;|;LspbLu`=cENQFzA3smv69whL<0JvNd@6=LU-TH=yQ2V)!=e z&FQyHIiw^(5&1U=9H5|i6cbQB0)?o|bY3%Pm&JOzjv0qk45*d~4Th*JRRImagC=4? zQ#7EI42oM&EoxT`8lVJqJz?Xiej%VnE~qiV%?4_Ji|{ir=z>-YFmkhj=9L(ObycP> zGUG6a1*wD%UVsK1Kwf7QXX6QhHi1p~q3!Pkeg+03m;7KxQNnyYSl3B%% z)YhI2wFq@k6tqOnZWGAIeqdukhg~zynHS2y5TOfNbHwP!23m8(7zCM^^JfE1^D+kO zf|fKf2C#vaG{JhN!E7LHjG@lpiMSAOfXN^xcR)=HP`0$4E^oo132yfUghKr8!(akx zmxAIlZ+e0SwB6G?z0LxuVGW8g9+nDFi@=bJfq}6E$-SLn3=F!U^-_!_;4=&ugCLGC zfjA!4ux10PV+?^fumbEr2}HR8Y7>GSs1XKn6=dRU`X3z*&glx49KzuAXAPC~KolgA zVW1w1@bq{~4%To`%Bz5=VJZQSK7z`Z7)A>QGtiO1u;d5H^`JFhcFdrL%yh74K!-{* z&M6Fsd1gAyGr`k$TXHCwfLk}vIfyxIAa#sk5YNm7dqxD&%7hhy`qKriI5ffSG^cQg zzmUqn1c(rF^VfyJ3^s5C$|sQKuMntBBm){g+5vVbXnvJ(4r>I=p*x@sg;Z0!*g!IS z`572sfy>Qc0y;Dq6uK`!4icMw%Zfu1?5f`oCoozuSb?r61O*TS4-05Dn%zrKO>-S= zVG5{doU<{Kfk6kf7KiaV8)z-g1%3tw9nks)#v5#)%%*2po(ja00RT0$hpt9aeALMhX$nO zYsSF90CM_=2uPdwmNkbW*zGKl;1C53EyJ6>%1|*-Aq(!Afk&QAK$o9@(uOls8ayfq zo(_uv4_$*!*apdmL*+{t7_5GPZcGKui-L~a0ZEo1Bg={ANPRIKWQ=ZV3UH>`J58wCmLd|M7laK@V$1qo{oeFhWI$RDV% z*f4#eEwtc2KmC9$hZGwqK;A`7e_+cY=?Y3ppd<{b#z6zvJS(-@r*#n>i@5OU+f znZXRXUkP#5VO<6WyA#F?42+Aw?g_+1GOSZP=WWH5mh2#GNe*9Y4}Ghj&!#P!~Y5^WMh2%J12X_(QQ z!3=c&Ei6nSg|QtdG{1v}Zcl?<4=KMU#=bKpbl!t1l^0+aYYBnU18BVA1=Pimg6$PMNTs(Bbfg|+JGkP1$Ic%I zb#0sw)U};L3=Bpv74_hne+!6<7%)_dgE-fL!3t^82DJ3r?i{G)#0MVPPXnh2wRl)d zkdFftri?+5_8lJwXfX_9Fl1bsj{~$Sjxj_Rw1I(9&0bNeUIOj9SJK(-aP%y*?LAsy?_>4i|?JkVLx>}%7ieL`tl7i=;Wd|V~pe6j^ z=wV=B4C4TIV~}D8RuXPZfcS2)Gl!%RD0YrO919v~hK&|If(RkUjthfX45-69{hc$1 zEMx9;9v2P?NOcApF9ua-0f`WUJzO}16F>$hCxSx(G|vet7ePK}urmiuNPrJPVt{zo zGKqmfX9Z|XrWYJ{&xByLWk zkpy-KQ!yt>asvAYGBv{lDLz3v4eTUA-LWO$=l~VbjB`4ZkQNo0LA(p`YJ)3>V*R}& z1_r%{p!v%!9H2vfm?j2*hgw-u7#I#gZJrnaS(YS_!oXk!>bc2)7@!uS1}IUxxbTC{ z%VYYO#K6Gz9}KiW6ZbAPC{ZAAhFw!*prdi3y|3BAZ$>L#=x)#!U07m!zm>84J7t6B=#31 zHn`%0I$9F6S_{fnn{FG#DPHe{Bou+fPC;T9AhBzZ*d0jhsYvXFNbJK%?DI(M4-hu^ zz!ru-5DwUX9H2ows2fF)*r5F%u!zt>61PBNyCAWnk=Wfx>@`U29dh-cq7Q5@!&M{+ zR#1fnbp+_3WSGUWNa7|)Y-=R86B64Ki5-B%4u`Qp{*Qxk7#J8*k=Qv%>|!K#6%xA< ziQR$3?nh!zLt@WGVlRwg)gG)P>BBz_i&{T_+^7l{ozxC)l$bU-sYP`ezE*hxt2{OL<0 zIh7^nA_?tBVxO7*Fp^VT@;QclcxW|}&|D<; z4kY$1B=&P8_HQIMXzvZoZ(7sWMseyJ#)I0KP{%YPvHOwO8Pvn`5)uXV z7NABbO%ILcbeAkd5}J&}UNC)YG^cX?IV7PENbJ8zY;I7y9%`yC659%i?SaJ3LSlnX zD1rI21xb7ogbnWIGHiixz=`VM^voE}U{z(%;2YFVS0r{25<7nS+Zax9!`VneE0EaR zkk~hn*iWZx#&Rkf3WGZBP#a8<*v?4oR3vuM^x9ZXammR@LR*p8ho-NM9%p4*7f(0gcv|AeyCDDB(?z(+ZKuKjl|AHVpk!t z`;gchkl05cY|veq3=Gd89B_1eMq)F72E$+uLSh>rv2CYY#&haR79j~uL1HhQ-Wbnm zJ^e&HCy%WlXn+c8oE#Ec8;Na?#7;zF=S^o#;IuZ}h9qsBvvE@M9XrM|}L2U4RAOnM@ z2?GOU89HQd6)fuPL25uNyBHW4TtIB7-XJ7)0unn9!iEG$C5QvnTnA!9HBSezq2dcb zY^WoaKpg>^ecA#NhpO3ARKL)9NcQhy#K4pn~*G=RVeRrJbay4>m%v3h0DZVjlI z1BeZEj2DOv9(`nB@H1s#5QefNLE=y~$sjh=@C*!5lkg2bWhp+oPS&iRfdQt$03-p`0NRlOGt>nn4q6NVy0Z*qD3l!x5{LRY7Q}`cngn7) z)np^F8$oRFs!;}pE*Kk>A|}H)3=9l2L2RhzHAw7jAU4#pJs>vdv^WL^h65l6LD{E4 z;!rhLL2RglZh_cPHII?lKg~d0JE)78KM}L48l;hGe{h&#uvnfIw%OlhKNTq#Dh3c4JAnIDM;+qAT~q;!$uGrJUh+6uoYw( zlzjjs4pnm&%${DC&Z$-Z55$IA%nTY+hpHDtVyl7JP`x@JHt3RU1_lNL3kC*ZDBBt& z4prj{VnfaJ0L4}{8>&Xq5|qH99A%IMRD%|X4QT=~=vgu_2t(PHAaSS~7Z4k2 zs3(XG6%R*Zry{Y7k=U&uHponn|2v@;fCf2df+V1ZE<$222eCmK7#J8(Dm&M3=E)CJ%yocQ7c4wpa5b+El>rqp_+}6*q}2b zVa0(zl6WGB4K*{>ih%)SK4@ba=-6{ch?(^abs$9$4ns4D4b{+&q+tR`9I6I%a|$C= z&1#T1lzj?`eH+AvI`k2U4VvL$U|@I#G84-F2oetig+BuW!yga_Y5^l?*&tLi4~PvF z7X`7QnkB6n7=%R_z#E!0LE=y~phNtiK4UNki9^*}BdK=*i9^+U*Mm4vMR7>%JP;e| zh*A(6wDyOAfuRy)5R}~l5{Ihk2eF}sP64r@;){^jYe8(Nnr$GqC}=-90|Ub@sG*?c zt*1Z|P(_!K*f&6IsKs}X)ISA@L)E_lv7u`IBe6Mc5a~$(#0ITXVqjnpv0o=7U(di$ z1d@Pis06X0ih7XPb3kmUBNl_$ptW5L3=GRb20_`IK;lp}dqHfdnTJ4ZsQ3jW_B{|A zHg@p_#DOaM2Vz4FWwHg`(89m~n!XUS1d%ANk`NDE z2AK&ug%QNP2a>D69RLxxw8>;3F z68kq2o7Wyx{zF|YXwSePECt!*t7wl1UM(cHK8OufZ;Yhg1|$x(*crrzs);~iS0J&c zBiQu}+YlUvt4QoOAU4zo-$86p&B4IH@Ec??l+EUVC|CqRY^Wo|Ky0X9MGzY*t_5O4 z_3Ak=FbGT6Gl2K%*?}aWirkUdJ|H$!LjYI zy$lQteIRq7?3wi-38T>}z_s%ZzYq2}~}*ii9V zAU0I}Mi3h+zQ+-?_#U)e8q`z=846{eMpASQ#D*Gr8^nfceg4O(%{z`!sUWEW`e0%X|=kOWlGW)K@{=nfDYDt-)!eFcgA z48(>S`U+&I0t0wY;V+Ol)Es8eenTjm1H^`^ujg@QU=W6C5Cus<70H0uP(=nvY=0zn z9um77#D+R_5{M02a?ZfOFb!lrl)Vrn4pp-T#14XXa5sWDP>KCW?6XMh`ye*dpvO={ zL38<^LE=zH|3P9ix-c++CRRY9%j&|wAgss$-o(fU5{If6bpf^ip@wRJB%o|JBz7!_ z4Ru@!hz;7n!oa|g0WuWIE(VE1)zpF5Pz#ztY^eA|B=&q58&v*p1aY7SZG{>N>I)nN zi9-!Khs3@NVnfwmM^gU)Bo0;o9K?pI`Gv%maAja%go^9Cg35oW>&!qB%AmkvV6bv! zU=W6~T|wedH31+t)PhhD8!DcR#4ZJ~p?WK!=72oY2@;3uorGZ5GfW3@pc-Z)X;=ah zhiX_2VnfyJLt@`SV!s8kp$_^2VuNgDU|{$GG84*Xc0-hgd?0oZDEt{17!*MqsAgjj z8>+$Fje$W}g@FOYbq9$<9Tb4X4h6A63K$p|B9YW5fyANeGeK;qni?ebta>EQMi3k7 zh#ep{=maAM28KN#L!s>BAaSUgt4Qp}NbHYD?Egq?UU!7=r9o^}X!)-P<$z+}2Z^1H z#BKtyp%!<7*q~)P3=9mt?hFjVQ1%RvI8@CtB=#00_8|}(s{X1wsQia=J|jtRc_3UW z2x5aaKr=8fhp?i6^vB?X#Lh-yH-Xqt$900(pp}E5 z1n9-U06MH1qaz`h!?2*he}*Rl6Zi`ehp$n4f+6LL)HIB zV)J<;qE80IhB{6aiERyHLw)Z8V}r^cUl@mhfgu6JhHB14V%LM%P|Y1k?1@P1%^)^Z z?=d9y6C^f^4+8@uRE@L`1H<$gZv4EUlYl|Nr{=@J0GfOQu?;~Ap+2=oV*4VoqmkHY zAT~6VvO#QZkSPodbx7hXbKWL z55$I=Sqfr<7KDO^aX=PB*)6_EiEt7~5mdthB=$Na_D&ERYVkf08*0!+B=&6(8*0uY z5L+MO<7Xg?q3n+!agZ8NBK!~IFfcIi`XPc#8i}om#5Mu3p^mTwu|WngFfh0yvBQwq zi6AyqeHw@jbws5fs1X9?bb=(H22B95L7T1^7#ODbF)#>2+4Di-P&I3j*t?O~Cz06K zk=Rd>*q;&XdWL@>4%Btb{tOJDt#6s03_$@548kVRMo2730;(t*iCqa|Lp3xZv1fqT&=PSW5_=UA zdmD%i)q4_&{Tzw?F96gCfm+NO$iTn|TF4K&-#3tfK^V#w0f|G^C?T;8kl1!0HdK8e z5<4G>-3DSq&FKZP!E1Nw85kylECX{G80LT^po&%@v3DS`k0G(IAh92T*idr>gAh?B z0b+wTN-!`m$OJJk2t(QGAaPhD#1zDVTI`I(4n$(dgV<2bT_848{X`HOw4afIfnh4h z0w{X{NF1tWHHZyOD;q#;sCfN8B+eNm_EQiWs^Jxg4K?&15?eNyfq@Y!ZiB=QLt>|c z*ig&zKy1(fK@1EGMZpXV!j{nTzZN6`Rn!4uLoMzFv7zF#k=QGd*xQlVN0HdqL2RgH zw;`5+j}dtd5{H`qB^XrxLpeV|5>O3)ku^g&#(r>0WBb4U|`q~%D^BDW$y-wLliNbL}Fh@Vt)d$q3VAlu?52r ztz9W3wlWf16U4Rwg+BuWgAJGi@;d`V6cW1oC!cevnNF3@oT@V}UAR`bPDsBs6L&cpy zY^b;|hz%7F0IFCeksM}f+Js0JR; zzFMfOg+Xk{!aoM_Xa)vhC|e064pn1-#P$ZUp=v^q*jXSp)X~LA>>3ywZe`xJ-`wfG{4?F&L;!rj3kl25a*jzD)C{T?7mH$x9dLRiX+Xcji zy4n|s9frhC0WO!5F45R zwx0ChYHX3%-bn07BzAo|5~mczh8k3d#GV3TLwz$BiMOG3YevHKa0%AiQ_Z!6agtq_xgM8o#iVp?`u0%vW76q}PsaguehN@9UVq1dP zP{%nTvAvPlfgm9fl+xkHjtnv7rvCN&=PtP);+FL>Gt+wO}HM4LW!M)VTy%0A()#i9^+_2eF~z zhmqK4kl0s|*!Mwfh~9dJ?+6Y9e=;KOr9o`aK5Ed;RS+AZfx!^OhOWXj1F@mvj!0}@ zBz6iCyA+9C31)-BpMim)0nC8}V+#_y6N%l6#GZu2o`%Gpi^N`t#9o2KUW3HmVt~Zi zfyCaA#6FC~J~cgeBByx$RV1OCNbHA5?59ZVw@B=dNbH|T?7v8C))YiUa3Zkz^iNw|gv!}nCD3P}P!6Z(H3`T+JioZGi86BnH>sInx>ca{4oFnI8C;)1UW=H6wVTkq#pRgW&XwJk8S64L%64Oh5CN zQ-$e|_4H4FIsF(FraS)Q^k;OLJ`qI4On(TXN~RnB=k#anncfJZHcY<=qE1XzOn4$lLQ&L{23#rCxWPy=^H^*$8<&}E`P=a(*r@&h3N~Kxcr&E*iQe% z#O22*G2M}w%b(F^`a}?wF#REjnlRmvg$v~DMiwrA-Wzs|;OR_|v+buJToEWd{R0b^ z0n;D5=}N3zevBE@3t74Rd4Jd=eCImdQBq!d`U_Sr4Mu_Kf^1y=j2hDuL6pPvjUXyw zIwL!mKV!%AKoGTH`a%%3WBNxBbz!PfoLv5l71J9*RLk^>AnL$$MJ_IXrYDZmi@3P_nEp6UKg0!gp&&PxKjW3@ zi6F{k`bH4dF`bbI?DIenwPpH35G6AGBZw-Q?#RpK&p2cHL=d%M`a=*UGu@C6?B+&3 zE`O#MZqqOEarrUYOjqRR@@HHzy^tSdv-|Wz{9MNvMW%NOaQQQyn0^yPt(mSV$W_kt z!gKl}K`uYWmgye_x%@#fEyU%|STcPgh}tmyA&8QhZYT_n!A1~uWco!AWiwq-gv+0C z!t_EBkR86$4~cO3F+l*^y#jogv<(;Gol#q^63AUlGmD@k(sF$PR8l;rYf z+%x?kh!U7CD8=Q^m@+*PMD3Wq5kyUx&L|D`Y9NSWnZ6K2IZXcuqH3l)%5eEJ?wCFi zMDa|22%S4h+>#-s06YkX?l|q*piD%V1FnobNMq~m|h5?RHh$P=JIFykUCvRh0Bj|&-6qU zE`P>?=^H^5&vZsrE`O#Q8PkJQ!9l-J6&&;*LDY%qj%uKsm^pot8kZKM>GZv7T*|Bq zDj6B}On(Yu+O{(={GNWXlS_EIf;yJ~qs4SXbuM+rnCX!q%6@tyi0YZX5=7-szo^co z&h+5h^k3>+YK;BU6*aij88xPRYH+EuI__p**f_mZgG-s|)A#9qMciW3H)wDPFzQY} z2$D|y!N4FfJ<*O)c$y}c0ON$|f|^|FthK)w7+y?27{e<(Jpd%UWqKk=IF+A~L3R4Z zSYF}j3qZm>(>H>IZHyQhu1voe$t67fgC>_So1u}ZnT5slkAcGC+ZD99WH=bNOt&@S zGG{z6z0`<$L7#LV?PXBJiwTH28`xav^Zw;6$ z9KRV#ZkLPUn$9E{#M%j3gg%dffq^v#!rsorz`$C%{ahT^LmilogE`{jET)!5Mw1IJ zYcRdJxBXW)*Ex2Re|8KE;G;JgSQw`oFfj0d_Wme?I$I!jLow513kC)z&=u|s%#3UY zr~jGEB@uegih+R%H2%RP209OonTdUg90LQBupR>glO*UeEEX2l%)Al?CRvb(6sV?V zW??^V$-uzO!76SBqS$$j7#Ns-OEWMqi-1;XFg=`}IfYAs=bH)x1G6sZkT@oe=~Jh0 zDTwQdF)*;GO<`bQV7eyAz`&xh6~vUDer5`np{$A#0|U#6RiMyf`!B-4z;Y7AW@8J{ zV_;yJUU!C3QgkQi0`53f1_qYXpwq;-f=xhDIZxPSSvP8fn0-&!#Wl@9*V5ZCg02q& zpImc=5qg+EKLZ!&j9L~aupHN&>8qx4Iq;s9U|?Wb1-@04@6`0~Q@N}qr)x4Wu&ifv zV*)jVc^Md3zJPCq;CepYdm5K#_7rsn1|b$^7FGjg1_ovp_6=$b48pIO7#KuACkZl$ zf^JY@V3n6)W?&ElZ8c#K3kU5b6U(<|U|*xzy_= zLEAUP7K4r&6>|{-+3-mSWW!QWNQ(98F)*--X&W&xu!*IrGBB`Pum*OwbIFi46eXfZHIiT&4OV2~Em&|_eb5i{dpV2~C2V9LNC zC-y~_fk9rZft7(lL2QEz1B0Siv=sw`l9;7D1B0^I8GQx@6){&G1_o6zNj?S!HL=%< z3=HaG69pI;G{k0`FfeF}IZ84xXo-bcFfeF~C7ClY=!i9IGcf3ieFI%i_PrNF?z z&JVulfvZlRfq^{$%;r~M4`XU(Wnd5l?S)_uhuq~L7;VD9z#aj%LnP@_FSg#Ajcih zVPIg-V*;sT5d6c5PU2mzYM!I+XOZS27#QCYzB54Hc+l&5RBAgU|_dpo5KjYes zs~sEYY@d1w!NU>^4D9w`%~FEqrVI@14q%Qn1J@By=sB{vf-WnRV0U3V%f`SU$j-vR z!0yThI=h`gkPqZKH?Sov5R=@&nnf76mV%7(V4DNdEW+;12D+9R;wT@mdIo`%%(8k0 zc3-eV1Rz%XfprT(jPeI_gc-OrK<)@&y9qK%f<2fmksaoa5QsZKMlrC5f=ziw8W+ix?)kBJ&LV<9yISlefhkbC zo`HcQ{RRgE15>6B0|Q4MNToEpI0J(SM}ZwD0|OgqXC+4=h{?cqSA~IrqsRqRE3>&+ zFfecwgAy4B8>j%_C;`O*=n~*>9H5|L3=ABtp&*BP=rS;Hsy|?2V37XL!oZ-wsXLvEfq`v<1Oo%79*D`n#w5bPz^M;n zv#@zHGB9u&%;jQW;9zrAVPN1itp5%=N}NqWfq{Y32*eg(>j7yn2DwNCT=#OCfY=gj z6G2M?OhF!zVVkSOz`$t+iflOs9u_$+P{@Hc(=shrXJFto2MMq$a7hPqGcd4$4i4aw z0o7OxY@pkqxnx0XMm7^rxx^s{;xMr(Pv19>OT0c&n}LB#5hTRQ7O2F)z@-FgEU>Yq zgVZX6+5;SHvhoZJTq;4#3=CXse>fNzxKu&v1=vEw85p?K)R`F=MA-g`GB9wdgTy7+ zCW$aGaA|FJkt&l1_qwxP*?2bJ)=0BcS&WMJTV4`#-IwEY7y z`MKG61Q->085lry?CS+w3iW?^7#Mijc*Gg~c^Me^K=H{V!3fHRe5+&`7o&-j1K5)W#zK~17 zqnjJlAm>^u#lXOm!uSiKB%Lvu4`gC$9s^GX*r5!9etHZHJelA-%vcz>WTY7wc(NGH zLD&Cs@Z>PgnC`!bORgTQC?BTimka{~PXS{(L{Ty036Q<^polAh8u~zzfq|zKECEWL zGx!)7xNaITFz}QyE&=J1;i+Kc=4W6K{H@Huz*ETxifIM`(23VPRbV4TAnvLLTPab` zz~!aIz`#?(cnf5bD=3oc7=M70H9N?I^^7M#XVfq|!$@f|4j2_}Imsy4;yJ)f+0|QSFIHoiNL2WUf zUa-fs1VKd%Pal}0&A`I~iV+?bP}K3Th=W|hq6{X_f$!)91rk>wXn814KchZB0|Qqw z$U74mj%E;y0{LJAm{ZRr_z@I58yS5CKuLHO zC=YC6GzHbtf=!@QxS7#WfPsMx;<+u1kpc`1>V7eBO#(SVnn_TQfq`FvN0zBmkbyx^%Zh=4 zM~+DVoQKmum4`eNC<(F%{s*~6f$6OP1A~O1E-0NVGIa{pGcd?7@UVbv zfgC(4O#49w-T`G?Rj~UQ1ov_>Fz~2>ugGFy;3@;TQXPEHJ-+~tCX<*D1B2jg(9OkK zV5c((f;DS{H8Tn7fxN8)(JZJA3MXBrYtx@CoA4t08Pd6n1MMQ3|uEcX~lv`Nr-`gSAoZhX`c`S1K%@HE!cg00id|IV*;HH&KD!fz`$b7?J4c{`n}LC+g6RPxD2>U35?m$IA5dFD?oho30|QSLxSztr$iTH6)QGBP z5)@`&-~!!u%(Dz^Hfu(-FA(Yf$ygAk(iiS+bddf;Smd_T6Cm!wzZ!bD4rN#7(BjA`A?&qKrIu zn8HM1*4>3_m!E!m1(!NM*p!E0HwrMyot@6OlFOo=8x+&em@a^{Gc)qMVp;^({u-to z$uaKXU=MNL;=zT~?{e@}(C&YhXH?s+PfHK2>a7tnq z1RKT33^Iy?f$I&ZmSJYT2eF!s*+&c(2<+f1>lp;!foeBM|CWt`YaS@IaWZSvi!m_p zGx6{+*MKx6gDO{Ea3hOBkQY?A@Pj#w3|!`*_KW~?gct(@*IZCBEy*m(#=yW81d2R$ zWh&VxZ=u9O$kr9#60w z4aO>{lQogTWr+XXgoH&J$-~sD}i1IMjJ@pteQ?vz<6Neq=!9bR@Hv zI0J($2P01m^Del5;-DJ9{)tEUhk+*n>YYiT+>{9Q4g=RVkjY8RRUosN7XkUgP5cC6ZdO zL;040O6xjsfb(4drNeq~0_AgNtY={0X2KoFooF#q&g0yS_eebgQ{=vpd_@J@)uOVO#??87dNO3oCnd)2ddx~GB<&=F9hk# z0uii&3=AUIK-PjHK?Gzj16LTR7+A)<7NqnzNEO%)uqu!Os6}r<2Cgz;z6??Zx;a4v ztPIJVR!|6T1z+&S1!@WK?1ZqTr$1TCrCcus3eN1X;yKEE zMT&tz@Dr%EIK~XJhe6N-RFNKM{vrt)?9Kv(%L!)CC5SA70wBF7nR%o@5T0Ll>k>?FFXrNIT(yDz6wnT)1s}z)IKQMzz zN`6M3&&(@8R{jC`@e5c90|VC@Q1|RB^F(O|27V5nAIwidO2DrA33U|%sA2XCtey>$ z|9*q>A3FmV3pXfG{xENmW?+z&VdVMGTpS0xIy>$ zphg~}oGqvzWdUD0$HFML0b~y=xYx|VCmgk%5aDRCjT+fHJbI2qO<4%XYY%_>tWt0Cf|%dJ_b9Y(X^|A1F43 zSXyKl7!+g}dBj+_K*Qbwpad??0*W)fDp0W?!2$|QzBT5c>@3Lw@;6^8C@D#S?c?(U zH4LR$K*7nt^&3=3$g&)kVPN121tmTO7A08*24T<@#3B!*7#KuAECwF1U0gMwI!~De zG=Rg!1*&e)5kT8QB0|PkoPk*$LOSB#o_zYaipk(U7!XpRTSPoL~5Y!n0X@mXiP2`WW+SV6;MT$&)SOMyqOnYQRMFz`+T4R=6hWB80fCod~b z1dSguDpr9`y<=2-4w}+pRNT(Tz`)F?2s(R^g;8-KF9QQBqhc330|OhQ;&WvN26je8 zYtRrUqvB5u28Mc0MnySm1_mxh#dS)cN?Gv(C@L5gn`Ianco`MV#2Fa)7!}>DKy{fS zs1qo_s3@hwz#zz|c*Bx`L5NW?$C!aZm{Czdk%2*kQPGc&fkBi}5!AR5V^mC+U|38WcD)RvA`deIgDj)sK`jObIYvc2 zeFg@3M#c3)3=9g4ikB4_7!(;5&$2QwC^0IQSurpuGb&EeWnfTYRNSe;z@Q2_89RGh}gz@X2lcu0+b!GKW_bUUjdqoSQO1A`Hx;$~F_24hA=(0!LCjEb^CpqmgB z9oZQe%or87voSE3Gb*kYV_>jgR0JLWYssisDa*iM#mK9`RiIO>A$nFr^qi7rVBlK=Dv3B4 znEK@y82Hw4mW=zL~Vir0|Vct-Jo$=w&#)z41Al9fpP|0sR{!F-xg54 z#lz+YYHe%z&^-?mACfq|*al!1Y7FGzw_h3`PtbiS=zV)dYrDh@VK3CMRC zQ~-*AM_&1kWGON*NU-fSWMJSs%B0A^Aj7twhk=3bI7quJ+b=c-2EG$pc|cbZ^00`3 z<~o0Yl%C>MWME)5;XC^QGz|m}nR5`Ag9>lH^Ps{PYTE^nZ36WW>n?(<6Ja|h%D}*P z2{cM5!M06@fr0Nbs7#TBSbY^_wG_naYapv-*gzd}z8j$axB>&y1bqeuzMIt`2gvZ< zaZrLq&0Qo1+=DovkCTCc?>E+CcNkOF%OkkA8#95#W1T2RG*# zk~z;I=78P!0^~+M2BvTF3=DiPK|{f;0(@__!S%gG()SKY-+QP&d(g>^d>=ZM7#LU; z_&&3NvN1U1z94D*3ei|Dz`(%w4HQ6pZ1y1bcTk}4vsr<W1u;}p9ewa zaq#_7gPZpkY#syCS}g_!zJG$s3=I4Ne2k1q%JmEk0$>}N7{N-wO>sVE@Hi)jAlOb8 z@c1Mj1DCft0|Or`qajGQ5FZEQPGy*8PGrqoP|emR3=DkSjG#UNpI`wfWO*1DfVw(@ zN}$4rml4#HP!nL_Vg$+YG3J5HHQ*Cu$G|n6nSp^% zobjkK1B0vzBcBwbEnJ^8R3E4!=96IrRhS$MT(d#RRF+Xf1)@QLF%Pam5m|#0Oaq%D z0|TEjqo)c313wp^Iuql(=`}mJB`0_dl*39Trr+7YCE>x$25PT?+U|U2;9)CH!Iv@&41DHb4ws-i9|HrQ1=w5M;4UJcC0K?B z5*b$D@Z=S2oo=&}OR^rE@az~tquOE&Twb6;!-4S@$Vw4DXU4s%u&{H5dI_BS+`wjV zfX7t$+!;ZWYkY!SpwhwvJa#7_*b3r!g6$Pz;CchfP~MD1s^Em;$M_3wY`s6SxdBjf zxvdx&_yQS06(b)5R|g{l178s1NmT|0SqDbGFveYKFjs{m>yCiv7D!2E;EQAg^+)*x z*Mq`5ig5>MwVpspE(2dQBdD}c5$sT7VBm{ktOw-)4MEU20$(iHxtfCDlokh0XdJx6>gG!VyG)Hy4s^=~UozM@J4OcZ{NO3j zv`Pje1A{mN*9*`UE-8#`Y77i!{Cs@rjG#M2A^9c)*+ZES4>52Z;Rbb@7_X^;!!MW7 zd^*Q&F4cN-P)m@3hs6TaqIhP;z`$3?$fnM~z%Rj9!U$Tg0Wq@_Y9=_U%NRk01&82E zP(CjQtKty^orBL;!3b)A2|!XwCD>{~1|Aj{kl~=~WcaEWJwb*W@YOOtQDgh%j(ffJ%&2j4Ys~Dgu0K7-z!ms9%e0 z$vUVdIiSd14^Fpy3|tdIR&Hd>0O{u9+st?pu6qkqGg$pruzC&#E)$TewlOXRsh8o~ z$*8LZ^U*G-deCeq-)_cvat!qh9D>V0)%zaE45HwEOHfk*%n=X--Os?ck1>v$fk8y@ zJ*b@8&j^~ulVISg0`U$oUWHh4h;cRClEcWB906GZv*Re(SRRNS$G{vzZE~*C?QCv)r#t1kHxWO_Uf-^ylULGdU;x!(@ zE1;5um+2Kq52!!|b#z%k(^Fh(pavcv(=w2;0(=5Yy1K9+6NH)yx<-Oe2t1z40WnAz zY!D9v*Zq1>fg-~62c%nsPmHMru3H>gw**vo5UA{s1dj%D3f=(OEXA}RG{gd)-{F&n z=x5+zVFUTt1C+I7m@IX{?Fl)iU2wzYVTQ|rYB>dn=?q+;Tc`LGnWlj>i0~;hu}nX4 zkV~~5ma+;nOO8dEk7O>A&?Dbpk%7SbPS?FhY7SQ5t1Txp*GwA)zo^BxgWu5 zP~z7IPl!RyGk}`MwF6WS8#0OMF);AU@EJ2*0$Br&9FuyeQFA~>nL^wu_yW{8Gy`)u z1=oZ6Lgru&m*5jnW7Ps|0FU5IkTOfA8z9pJO+f8@E2evTpwi_!$UR$3hI){T?3hCJVG(N&br86;a$q_s04nRjg_R^6ZOI6K`_&QsBH{z`z#`mH>5ALCr_53Q$8N2E62!Uw|)>sTHm(391X+R7eI-hj0jr z)Pv$M1)S*l1i@{TRPbyHKLb}ZsJu#NayI~{@GPdSaHF!JMuDbG_;Q#g$$=-1c7qyg zc}x>Q>c#l-nIsKi4laPI2U}eTwK@*eY%byePl@sgu9*J*2$x>{L6Bw%zDlMpxaKOT z=2TERtY-QNP7v{+Xs=-c4Ht6?R)CUTEz>E`tfb%qP{CXW*3Tm-07_@|OcOwcK@vm* zIEp~!7HDdehowxCfq`oxsAO+sQZ=jx7hlax4?r5g8Kec-_EvB%;1HY+DjeFts(2vA zwu6loVBlc^4N!A|4m{`UU|M9zz`(D;*TocW1Ph98Wb=BU=7BxX%XCVpo`Hc=u#Aa; zfv=AVG|bE;CGzEyg6T$YXFz~Q|#?ZMyXPom*V)|srz@Xs3 z$TyA2!jyqQ8SIf6V2i=i7ko3Bsz7nO8OrWkXUonWimI>62QyU&oXLik)j9Kdom1^*{OI>p_NYU;=d-`L==_v55)P z5#);m)eu{lKz%&$04d)#rg@-R$VHQZfo})XIS^YK6e+uy(m*BYBv8@0hY8ey;$s0h zXde@(*8?6m;t8S<4jLL5{e)vo?rqslliuR z9Cwll)Dq?cZ3W~z#RO{K^4$jw;htvtp~1kw#|d)u875G(laC2B$a9wI1t>vkfQWNU zpvD`YAS(j{-+3lb8;h?R!yNASG?IpPKr=z0}CRZz&?WSRyFgg}tqTTIVD z?4_Vi;T>=u<&y;Y{w`CKHbXrF-wu$E?=kHMx#$JRmitT}KvXxVpZ@?{1M`J})I4PB z0yTtxfg~S+t3SRyAVZ%pJpnnW31rz*aKX-(3`#K1z(pvZ6)0GrgUesOHy{IEFtLIH zN*dIHsDH_14dQ@j)ZTy#FFtFKFW-Vo9|kVa>QBD+OrTPq3v_-U-*<2p;sTxH&c^_r zM&Os=<6!1DV_*=J2DQpKp%V>RpxEOA&*HENYJ)t(&Fo?dDttkw=f-xW`3NwRx%z}c; zK>;EH<_HPC1QqO}VAF&J4}#)R9P9)UL2y|s!3^#CgKoy+lVYxqF=b%jU&E)s>;v+^ zA$A4^K1DE_L2x1{CY8WmTp@TAWW5TQvyy=Wlr~2P(hXicH}w1Xf_50H@;+Muv-PQLA{(5@KodnL0wS$ zEfws|FM`KFg-{xp^HnfMh=GAG9nASA2rfM`Kz`YCnoEK4(Db{fxuh-Uf%1AT*b+e& zIq*nr9+)S@A~zpoRz5SRkQ8B&QvpR`0oZL8EOJYx8=m2kW|W=odxlH8-U1ZT<=`1P zHx@b2RX2PU%%C|}PZl}Qr-H5;HU@19!Md0)h`=l6)+cQ z$tP%}gq?xw7%1^}GT#Bk=n_W03Cy5dYXy&jY@fso>Pj&PP5?DGCW9qd1i_=vQ*YmDM8TcX}(!t zPb&yM1jX@e@a(;!91ExfodfoW45M5+C?@BE6{NX z!-Y}q87Mt10P|cK<)%M9%O&Fg9;;pq7K>$+%LWyNOTfH1MmcaET?$?j63-|n1*#X8 zgFT+WC2VzGiV)c0i#^q^f~9aq&fINj^4z)c>4ZxTw?X#K{Ht_py?(a7EpE0 zT7Uv%3yP#vE1ie7z(O$6qEP}D1z}g2^#R1tCVrC63 zDwr6!UVy63{mfsj7#JYS_4y7lXIL{Zh_QptbQE*r25poV>jrJN5-SsBU|?oovI1RS zqf-o;M`Wo4T}uJF6hj0Q;Lv?Yj1xe&Pl#OsT?rue6?EC0*lEzzf|wR)!_KTf?!J1nPG$OclJ>deE4F7981_o`= z;ho>?7#McgOrN+uRc!jg3tTGkcR?4u1~7tjgYF7qobwLd9wP<@bu|G72F672kOW9& zCHPkQep{G5iH!Vg3=E*-@^lk~7#J9n89_nE7^0avUF9N|BE)*oraF-IO}5h)Zc7!L zo^_E+Q*x0l1MCWIL(mo42B(xk8`zk3Oi< zVqky@fNxk-1*HXu00$`A`Ro`NOhDP+l99pqDCoXaeR(^W7Q?@`3=CjpCU(#iB*b9c z#KgeBxY`w=3UmuZJ$TqP0j7)-T*NRj7+W(lFfg7iL@4&MV_-1u1KmP-w;fHC7v$pi zb5TW2FLE(3FfuZ3K^5iz1=~rOb<7MFrt+XWzQq`CBh>A*V_-15WzN6=!u)s5%y}3X zK$z9XY_T>20|>JwOkY^1XEEJBMsUJ(?)gl1+nKL$?G!`YwmtpA0uJ`=PhN3dF_?ay zkx_p7JTq~l=^rkM=S{cEQWBV6wOUDNdc$W~x#@X4Iu6tQ_7oUQ&)TbyFg@?9tibeN zdli(n?~vtAke>eMg#ZulN>&C2Mo=zcU|`rb-O!TTn(@c2 z1y*bb#W6_i%;^U$xs@d+A_*-+VsD=Q*OFUY@*I-TUnDlybX%@0aYo(gg3@f_h9T?- zJ3z~$VRpA5iBCjg&!2iwSDf*{)Q`I2Qa6yqpCGY6vQN)*$`E4|o1QpVM4VA+dM=34 zn?BJgL)_4s17Tr461xhCJq?MyXnNvjNAc-0c0xR!py~9 z*lN>bzc`BXdLs$NO*ga`5;rVE5^6$XgK99C&9jiimrduDXA@`KH{DjAO}zdZk_;y( z)k0%h1c@z=#MVY)n}Vu*Iug4W!UnC_1r3QK0-$?(p$@xv;&zBUs5oLc zjKn^V#J-KhevZWcjKuzr#O4MSno$3VPZvCxCLXGfBxH@mc1L1|AhF|-*jY&IQY3c6 z^n=bW;`J+#gtj8FPa?5FH47|`UL%SBL}Ih@AOc4miLH#p)<iTxRg&CZK(y9g3n3Brb)M`{k?fZgbf z#124Wry{Y7rYG8STQhE%KG&XGobmm1#d~4m)8FJq@Jzp9&&^}2!-udFw1xy0zA;GR zg-GmfB=*edycQ+mlDmncnHhZC$?)N$3<3`x+Aa5fb|y68jetn@tcA zP|`?jbtJYi659d7hGf}L2nQT#Nz+4}xRq@uAPFr+VsAoXA3$PXMPfgizSW6aUs4>@ zynu$34iejP`d=q*W!^+2p|a_@-U;IMeMmyHkl4$R*qe~p`;pkEk=WOf*pHFeKakjL zpuOZ!*U3QGpzWdz44TtVI&&-62SLQZVG@VL&O&0BA+ei~*r0W=u=FwuNqjvLdp8pM zI1>9Zgbg}_fPvvYgadZOYb5p$B(@2tT?zGw0}|T@i5-E&&P8H_+oVvv9Z2GHML>;k zsKhEHiS0;i(CjJ9m$#9`Um&r+BC!QP?IWm}a!70)B(@cd4Z7*T1IA%sU9y|M;`Kj~g!m*7&XYl68zHgnkl0>G z>@XyD5)wNPiCu-nZiBEPX?_xf19sy)B=#yK_BJH;Atd%WB=#*NHmDm83op<*Y8d-J zk{WJF(5cMO^r@Z!oL{+>#21zIjiCu}r?nh$JL1M2&V(&m= zpF?8bLSjEdVt<0LA!+X)gadXLw=BXV;z(>uBsOT5C@d|3_IJS8MM!Gukl0;F>}g2s zMY2fc?K&ihT}bSUNNms@XE4i@4vBpgw2KMmgF8qPkCE7~kk}uQ z*gufi|B={ipwS#?^zkCGMUdFiP&U~AN>C2S|C&f_10=RN659@m?TW<6hNoLLS1?sNdmOO92P3~k;Gpkv40@3nH3RPQ3;8yhs3r*V!OfF^$ZL_a1H}Q z91^<_i9G>{JqL-s0*So^iG2WxeFlkr1Bv|v#IA?>{v(J3WeX@Fd;{7@2MY-kByo2n zb{Z192#H;f#GZ%5UWLT2-;Tt&hQxk^#D0gw{)NP5S4KEg9f|FM#12JbCnK?2A#8B^ zW0(ZtfYKksd?fZ7B=#;O_8lbleAe5akA=Qd%(tNA+ha{ z*a=ANTqJfC61yG3h9rd95DwVTy-4g+NbKuK?59X7 zIU7l$5{W$88iu`n^v6>>=I z9whcGB=#O8_9-Ox8zlBmBsLppq6V5+g^}0_5H@5$Ne{vS$3y@UI~IwZg~TqOzBd$< zijaiPA+c{Gv0oywxwR4DB7wwKMPeHvvE7i^8A$9>2pf`$KnJ(M0)8n(0_=}XNbCbh z>_)j?ugBC*|ckcJ$Cr+*FOwpN{uB)=DleF}+veR^Uzw|KoU zXfg{LFA7L(JtTGj5<3=&orT0MM`Cv)vDYH8cO$XyLfDY7dj;Wu!|OW|n_Caze_bTD z6%yMWi5-f>E=OXwAh9PRvFGVc&x+vIGkl69#;%XBQv`{vh{V>Lelmhvxjqa@r~--I zhQwZh#NLX;K8(bEip2he#AY)Xz}O)Fe}Qp8{x?Cy91jv(0*S4H#5O=;+aR$$kk}ze>;xos z4(J{_SV>xeB+-Jzo`A%jgT!8e#NL9$K7hnNgT%gp#D0Qc*E4)Ta2Wm|u{lf;At8dq zRzPCwAh9ix*se(IKqPh=61y1876yem149Ft17Y`0zZuJ2o+x03uphLp0Txh3NaFTL z>{ujr5fZx|iQR+5o;iJE9Jey##p!S3xWy&EAjvR-7I;8&0N-@hc<#;hmym=WAhF*e zvHu{kxhxQlmq22xA+b%6*iK0703>!Cgbhli3=BCC4mgymkk}na>}g2sB}nW|NbCbh z>~l!$J4kG9ON0j$LB~bHf?p3w!WxO~G5ux&cYOUuBq7j3b(prZNaDAV*e{XT-;vm? zRtWn+m&d`(QA85gM`GJT*pPtohH$_E6^X=7M`D*Ev73?D6Oq{Sk=SdI*t?O~Cz05% ztdNQ`&*qKP|i7+@zpCYkeBe6dsvA-j+|01!OZ4jZz zg~XOYuP9QckgZqNm>=5;VAoWmo3`iWRCLP2UfvCv= zv7zGSAU0II2E=9ug+BuWLo1jA(J&jthRk~~EJ0$gMPly+v7r{91hJtOTmZ2_2PiNw zFkAsS4$8idB>o=6hN}Nn58`k_EdB@50A+L9B7#l?#D=qhuY=go(7gjkQyp|>FSg4kg3dIpA>AP)3$;l&^}Sb~9J1BeY;%ErLJa0$GZ4?%3G z_){eI8zlAzB=&bC_HPh-``t9|?JS%!3m6zcEB;KTJ4X8{Pd|{&t-`6XfPn#YPm#&= zL~mjF=?=?8B&OdvA0WV409V{t94bG3!ZHz-=?OX9DvUMLTXVRNGu>G*-7lBBjOojQ z>Bn-p{TOqmi{^2IZeK_RQ5Ms;=5fDg%$UA3pWC0&XZlwV#WLNsfLoi9X?kG+w=yfk zat4Mu(`OcND>Hp^o4&7rTa6WTz5Cqh2Q3(dr~fJ77GRolYdT*cw;F4N7XyRE^hU2@ z@#z7D+&qji(_;&{)mbNaF)(OAl+P*T7GOGYd-^(%@*Q3b48GF^Kky4re^baUz^F0( zFGxA7KLbPmbj>1eWyUGfeT%r&SzWy||bhN&QECU0J z2xxUI%UjS%|DvF4i&zR+7#LU-Q$fepSA*_W&?x{hpK_})FtF%WgV?X9|DVFGAg&_KO~ zFo+d^nv`OtwhRnRVmAdrLD>Mhr9cd{!-tiDjy)Z8mWUCEEx=v~Qg8g9fq_AUUD1Gnf!zeemSFDy9UyP| zg@M72L55vXg@J+H4CFI823{7>>GQlSpp%4IrhyL0HwOu@fJW0e@<3`>!a!$kH-edo z(^Y108|1ctZs8Vl1C@kgpmS}Q#QNAl0dXI^0(p`OXa(|jNzgq7>p^Z7JHZHAf&9%B zv;sLv4RlYzAJA#YVxK`rNr`O*FF@XE2)d`h0KCC`9}8#!vW6vS0rHIL2WN0=)qfXc zU|VvLEQ0D|)jqu4FbTtBKc1~WbfDLpt!aG^e)d>DJ zpsNuo6hK!a+%N=Pji9Xux*Fjl_-X`eWzf|Kd4iy;5uTWVu0{xz0$q(@Wd*t#A-y#fP+9s~D8MFs{=ekM?aaMv0#FmMKd*_@!5mIR&UG#j)Snt}Tw$nzY` zV0Dv0M|=jcg4xTN85lToAnah!L4~Cdwh#wsmmC{NjercNHQNF<1_nXU6#<+!Y_CD< zvFnA@3>X+VZP_-14pI@C1k!8A2FgGZLeC@_7&z_0nx%x4%o!Ls9l#uE2JSb;3=Eu( zY@uun3<46IE^K$%7#M`!urM%iy0U@X%pjBpa-AF45*CO_?qJO#4BQJqMtQJ-j#3k- z7vc0~QwJUF4|bIgSObG#N@f`Yr!UwY0uZbHz`BJXM)`v|!VKJgAa?|?y@a?Un5~c< z=8h1EJ0K>7f=ztNtEP-kG^jAN^1XJFuy;Y?s-;9y|j2W?U3 zOazBH|1C2H2F@gKIPq74!YLVS0e^i4F9QQ-3OES(O+boL!Jc5?p2Wt$z?sIji=Bai zmjz^=1Pf@J0p}JrFVGbMFF?&iu^!MuIE`GWggI;C^iP} z4O$EgoO{8(hMIAJtqEktPZ`kNf?_j3?Pjq=b5QBWqXf!Q| zE++#6yEn+NLJ*UI{T8UKDtZi3&8}g^z`#`uO0OL3OF&L20YxVd124-|PEe>X0IAZ@ zVPN1Y1u@xbxXK$rH%aU;U|`^?0O@03KkETH>b?@hVPU@o+96v7Qp3Tn2Rf#<8st(Q zc6HEp+nRPR1_lB4LeN>}wIFdH_P<&T3|w`f)BpY0Ur$e)$F0n`WO~;;Zln5hpd)%) zzku#GP~esh2VFO^M~{JlTLx7BFtEpg*s>rtBRgo}JGUH&&BQLG#lXNV4`MU3gOV$^ z0*KAR?hZPUUJ=A*Wd}_Iaw~!AXEye5HUN95q zg$*wY$j1U4JkuDDaWgOog-zcwpIevl&Gbj}xvl*lfsVOj1Q&U{ETA*Qx%ojyKFTqN zb2Bh-uL70tmXJd4CFtx}Yi5v<+>1fGeQY4?GSC(qTL{}|dd>oFdB(=+Jqx%M>)90< z7f zq~J2>>YW#0&3(oU47~5bOfL}z2Ht-lrT`nS0HZ1|1B1{>kV-+u@1XKkXu8fqZe=M@ z*z!s+f|3{iOF0GxUP-W025znCnG3lUH8u+}F!0KQTPBP`-O8X7slgm3p|7B$@)Q{r z7#SFtg&d}DTF4zLCZWl|z#GeW9&`Xc2X6wSJ|8$lWfyU)Grpegx`*!>A_gHR2?hqEV z&I<{HBEOrF1$64XP_70818)zwb*Lem?-p|#)`x?_x}VXQpMilp z0_28?j7p%BeJlDN~X7#MgbgN3<&+b}Tj&ScC5rBPvV1_s_aj1?fZ3Ft)e z#bBekxm6e#cvpkj0vx>S7!QK>UM}jrr%u3 zt*2QEvQ~!)oDPMAKVai=7`Pjz8!Y42V=SE>zl>Xo@$B@fW!wt& zVYUnmyf#dSLC%}W%D}*D%OoYlz`!pB3NkyU$sqAWF$M-+dkA~K76SvX15*lUsUEjB zC>J|26@V@eS;xe{!0Qb5F!vfI1_oXi2>THz26Mq|0Y=^eCQe}n2BA|53=F)5Ofz`c zKs_?<#Odn) z%ndr_j&~&!sOiNGx`K;$6%(kr#9a>xn$=98#t-*BQ1V&B1Zuu;`$#e{@UCS7wLkb| zc-J%i1|5U`VET#W-1<_W76R`UrimaS(5?yItxR)4!{Xe5(*;*>TdV%kV_@Jtz{D=X zz`$(;%4bI*Zde8qKMi3=PcK}-Eg}Q<&_$?+z<#&{_5&LO_pa#+S8$8?fK^lSH zaGl8$bnB2%k|6^F?+qrxSjjC4vF$ZXJt$1yK-?o_1B$V?OpC$Co`Vb5_u!ys zU}WG1oh`)sktt0SRJHPcVY&vkdiuqc-1^dB7yN~q2#(c%V5`}Ltfxz_;+Cq{0-XuU z%=`$VnT4CZcjW=KQ}f{H^(dz+1c`v=G&oXk363=9HHygbYeAoc4(hVX)GCkCM? zP=??Ka~K)8lR&kH0CNoJbns44p&-eu3aW5@K!u$;vzZ}?69P)iHq5q=gUfmCnL$UC zLPF0G>I$%*otUA?ZThQK+*154pz_I;8B{NDFv_)07hcV+Szids44%w0z(<}ka964_ zFz|XYZvff<4x~O9>@op%-Z17OahPAjp|)s)s*DI`C-C{>+-0CjD3aL^bY?gQBX11z zKDdTBs0OgJ;$hCxWMHW0O<;y(gB74VWD>#EF$*ID_hOLINz8R1!V9#R)m&y#>x}f?qf4bEgZVlc_ zP^nkS3`&Ijcc$mB;TEsA14T;(vjXT8Mt=~y5*&B@!l1gP3LN76a%Kz+ywzZD@*f2S zRt?yd{Gc;ed27Lz@;89ustz1>{GUx27P6G!W_g_$a z&I3mp_aBSt6W4NUGP+LRy_Q>*@#*x3Yq=F9LqN%DD>JA_<>usNVBp;eWlxt{$E~af zI+%m^AVlaA$YF;dhM9mW$-`iA0U_R_%r`(c2eM7iUdJt|kq9a{PcXAcF)*+Qflk@x zJ;^KpI+R=JFQ~*i1?I2|-I~5;9k(RkK2QaBmRSSTf)mo4et8|YTFN9)Y}^LhBp|{2 zfVoo|mew93$Mz#=Y+nKy`xu;*Ifa@*{hg;^4wsM>?Q%Io4`e@APcAk3@S}Of(i^FmJY~~+q_~de6kD-{Qp6P zu{aAT7WsF8a*qTHC@}dqSk{AD2`nIg^LK($loZ%Lej`vLNty)|oDAHcoeI3NEXP6j zY59PXmI8|!=-g^E(CN`nKu2zaSPZ;iySSS`RX*g%ZSJ3-dPR*T1f)6>q#6`hB3D6| zWP$w4!0iCK-h@||d$=!RHC`CJOBx^fX=}N2~U^U z#I3;L!6E=U9b0v}!zON#`W{f4^lqmMrg88vFo=SO3;2z~L1#@*1a+ht6%T`Et{D}t7%(s}F)Ci-2aWkEN|`b+urMn2 z@PSX(Ucdo9S$j9=&O=5;EznhajEa{)BM6L&g0|p;wT)E32Wx)>ou$sGco38#7!^S! z86Tsf6=+t8pHZ=%2UJ)qGU$O%*4| zONlcoK82jDZ6gCdS$nYr_+;%=X$A&qM#ThS1_l{M#cPm*wL$lB$}uYH8iEhj2DO3| z7!{?J>cJ;#A7cZbtes^8K3O{xba^SG;x;wpleIzn4%HbIr>lWa*1jYJK3Q8v7JRZc zHy`+9ZAL5b$=X-B85ndK729ON2WwB}2Oq3GM+1DYHt0MULq^368Suf{wdxG@pp&%^ zi83&lFe-`*gHP5D-~gYjJ)a$Xvi3r8@X6Z#stgR4jEXztz$a_7@$fGJjV5w{&Y$96 z3Ob~Kfn5W1Ce1RiFerOSGBB{XgN`v=4vJDGCPw~Ms}(?p45Sn>@UMnw`62^4mTL{D zz~NwE0j;a&U)!m`z`(}Gzu`Ar@kWT^DkBC4{!O4Wt~uB>q!}3aH=hEXtj!*w#=yY8 z1(Y#(*kdIb82Gn>*t`rZXF#@Z16|F)QfSV=z`qwH&ZfeDAWsqIj)T+vwsNcRf&?Vk zpBghT@E>KHUcZ%FK2!=ctDt1Uz`%b>P?3Rw&4mB#7r3@_5Ep?8PyX|uvXg@yR9y03 z0F{;k;9+w9iy%Wq*jIrn@k^j~j|BUi>7Tc98`LiVogH=))ShOO;lBea<00XA7s=Fn z5K}=%E%Dz6DG}hvNzG&6e*h|TMIbgj1lb_Lz{}Dl$H2g{3p9rJ=s(D<0{l;#KsP~x zW9J!?sn0>C)^o7W0iBii0#r2dF|gPwGBEJJ3{_%aU=!efvkR{AEt1A}AdOIc@1gqC zEf^U1KlFn1De!;h0^Pd_w(tv*zON8{ZlJEuH&7t(v8&dDINw2W!OyM%YH9oc&4~yw zu&ifbVBr6G6l5R={~s;5fq%gUGO(-xo%Z-oRGEQ6K!Bf-F-@6)K@e;s6C+p!xE0FJ z3?8=N5CYrD0v?IrW8k&{oqx*8XsXP>P%j|F&%wACuA38CHy2cQ3n(#jGxmTEcoAv? z1uYNb5>QkMiAyjr@bfZ)8m$5h+@O(8em=$`kfRLv1sMfYV2%<(HdYv7tY9(&zsPj? z9o$0oVCRW}ou|jZ9Spj=SDf)A*qbJx#AqMUrpgil%SOz*^TY%q>@gLk=e`Iq5pyvL!W?N@`o|*Q-g&~II`~Pp}V+6>N!CNtVc1P2MyH=mgF+B$o z6&0Z*4F(4O7;uu&5CZj0`D4M((-Z=y);Mr#)e>?AjXA`Fm1zs*fNp3^0CRM}U4Q;W zMo@99D|Zrf9&QrYDQb*zpbc02$spq_80;7sI6>L-9O#A+&`gdv1NSD-Y0)W+T%Z%e z`S{Zr|G|Bb0rSChh27jDT%ZAK0RjG8M(gQzySY{Ct-)t$^Rn20+7R18MMfbb=zKQ; z3H}ns8S1cbD218=j?FSgP!Yo+1lrWhUk+BqBUB4IJH3Jt)UpzQq>V~&U<)$vvVf+5 zxr;!BS`{N`PFBExzm^en)Tto&EN%WesOjLiuLo=65PA(tunml$@d^P*a5gd~g3r?C zo+ib>z~9Wc3UnH`0Dmi^kp|42Z7`FjTkYXiHvsL(;_qhs0#Yc#-^*A7SJ($rsKCI$ z-w(CYZTiGL+)~Py1sE9kCo$S-fJ?F|j631FrowbhKevZls{WxU0|WmI#tw+W*^J-d z3g=u9PWsks;N4-wG^BM_=M^YgG#(*V4i?bH>gNl4(136d4M=8z#I_L%mHcU;@`}87OpvA3sg5)!&a~c z4hC*ZkgK*at^{e2;or$IX z=sMIP!k}by0}=v4py7A^n-I-HpgDQ|Ta2K#0FMyp3Ss`+VEqCNyez763=G_$`!@OS zF#Z4;F2H|}u?=+oHKgLa4>kP=s5$ij8aop})$BvC>3j^_4ItkhnP5@k_7{P6lp2P!r-6<0Ocpw~V}?8*0Fb>>bpGrJxk@9&9KFcnq2U1DL}l zGzaAOkBlOq>xCG&OF@mfPmJe5CQ0yrWt;&w=^L_1oZrE^IfPWE=N#aclm>_SFGkQ@ zC$G?EP=x;m4|MYh6;5ApfLoFSbSD7+KgJo;4<6ta=9UDVM=iq7$@D^J`uzjk;`N~8 zFgb*dfU-Rg(;@~21|A_3ke_&&-hq@d@Uqx|hB;Y4x8a@T4rWo4yRE4 z3D7B-=3pL|5a>JS_pj8i8T|bhYM;AgSxxC zEPFxyJQh%onA-qUz}YaRfON|6+c8Dz!{W;x>L76bbznLxAkVgHEh-WBLLzo`>IqsS|FzC)9YbdM~hg4hHTop#0^{lnOdH zT7ch|>Dcs>hq>kI!HNRFig*~fL7SEN1DU2m6a_Oe8^GKgf^29gSUrbOEU4rU1FHg+ z{Dz=>e+86G!Q}e>7Nvqn?46#Sf${0#rxGFo}YWgcjgW zWa@-#OM+?x*P_YbfocvRR#3F0FoE0lkhWMV6R7s)XW(80%0cN&-XN2>__LUH!cEGC znsgD=?9E}CCda_wz`?-19Mp2jW10%mAjY51Bx?xsbOBTY*y=*4)vH0HJw@R889t%y z(^Zdh>%|@g>6PHGWa@+Kt%B;U10}6$roW(5riEsMdUiEToPrDtoI;@KY5rQKbD(K& zq4}WbsRQfh5jqVj*z1|5fDVloGMv8QD7R!i=sGL@MkY;=mV9*`xnsVUL8!!K;~)icQHj9!F=6~Y+eu4yn3)}d%>>d z6k=j#VBqg#0u6|A34vA)^Y=4>ic%S&*Py~|0@ySKh`kfR_Np-OvMdGJ8w4svCNX`3 zoG8sdjmZXfqBQ>uu*Lk(c^Me^XEN1+>Yjz5v+8FvtyTc_*uy}z|6C?e7oC3x$ocb` zK#fIyaAH`<1Zo`eyMhY3#Y~|4gZcYG4dA6rpbj+u6i{|q&IIb9@+W|LF)NuseNO%` z(D~r2nLzzWe$XXa{A-y&T|oXXpfs|M3Dn!;7nf#WsOMkL1nRu;zXln)feF;(;-3j} z#3m+CuZe#>$hljXKpi6R_#gi^CQx68-vTrou!9NIkKvaDManKFP#=YV2R8!){~jh# zPk~NjSdjk!6X?WEeqkF12L3}#j_M%$L8n6VA7PpYDmXzWa_}E#0<|^y z?|>4^2_{fuk-rcWFDIEm?LmG|P`~yR6R4HP4?10e|1{GdPz3=xB%A*X6R1VT&j%XZ zILq_~)F>ALrNDDcpk@vKMNnv+X9BfM_@96Z)(iDao*<88fP(8H6R4%dpAEA364O~w zRul!brYMez54O4fT!hd~ZH1~U0R6S#Ei2lbI3 zfGb9RS&*8COnspA1G-Ou{}H&p;y(d0`3chtkT%e%Z~RZe1vCF_P)GF{(=kwkK^x?w z=im~Re zNst-T;}j4AU5dpo%na%#3JUdtLP7-05fTC|rQsI^n_;$I+9uF257)S5zJ-~`Ur|uC9oG)2yF#fuL9<*WZ(q(HV1Uu zI;fY&#=tEADl^oWwapk91i1J$nGeB3Lkkibf|)7P_n+eCsy_;Hk`CA$cA+Ftl<6`v zvw&*PVo(y+1G}7)fmkc+ID&w*T2z;DZ(X3oGMbO}6c=mzF62u%X@COnv#nHU%ngigpXFz|bV zImtrnK%Vsi+mi-~R3ET6(uKg0`s6d*ilL04 zmRmO1Kt2|^WuWna9I!$G7P)#*+~tD3D99oQ9!$*x^MqLBD)<=~`16@T<+%upoH8gd z3c#jVu*e;s&UuzwT3Zp+DJTXD+Of!iE<4~a0|&SRi<}N9F3Q1EXl^WW+SC2da!WI| zOwT^cEnR;Ol+EjyIoZJHT(1Eohz8~bmf&-)!I`HGoOxte<-nInv@?SuOo5ew6BKD6 zbv&Td!p6V}ni$#uy1N#{XJ_C(1}XtMnVUchIaol|n*cNaW9CnwRlS)h4E#^Q{$^kj zIy#;G9Jiv_Axj1Z0T%u@%t}@a3__+L-@Ie4n{IcGTZ-!+NY0D@Gjsg(q;uS=_3>5= z3``81AeEr~R$v!!fJsIMZVpg9{bts)Vqg$p462C?OgF&`P*jr`>X~jbfdthu z8JKP}se+b%@UnccVqj1QjofI6a5FG4y#b3et6D?!z5#1cO#(^4w7vr?VbJ^lI#Xj8 zNGr%B8PMw8Ieyj*3|gT4#0ZyQ(B2O^V9SGFfi!v1GyTsTpVOvAoB}r1_pzx zRtyXa7#J7~PFpcBfG$up1Qp<*T{}kitr!@-fn3P|y7HRgcrXLQZ)?!}MHHh8gQ+6} z1H+|Y2GDXyP=&5t1=@9=06r%KDNb47Y8jGd|@Oo&N3u zw*o&{<_H4=14u^R79wMGky{}RqcjUB#ub<1D(|HjR_PxG*y?7_eD0Ff=nWFc`vA7)e<(Fl+~hy(wty7vwDC z4Pa+6FwC)oIBn}CZYfA8MKVG{=>b&c^CfPDsL#RRsAVbwM=2;DX_tUj;A??aD>9UU z+%c!qo`FI43uuR@79)tw7^L$WbX1Ercnk)#bHUUc8Y;$tQ0t5BA=Wot=2o%(53z*3 zn88$~hygU`&H^e~EX_b$?m?-R;V{@DHwOj=D@cHW=5`r_tR_u=c$r%%5EL$;4GEyl zSB&3z9iYJix(o#zED0-Sm(v z+=}(dpko4OfYgANzcS9zb7Wx90^2_WWdCy(1_ry23=9l*j<9pQ?Lo&mb}=w8d~{%7 zaL8m}oC7kLG1vy=!f*x#kmnc}=bnPOP=^&7aoMa442CcTU>DA3o&Mztw=~mtyXk^g zxrMnwv1b7?{zWh(=v=OH%hrRe2A6sw4C)}~S%R)uV7vr!^FDBxaXP`=dI$gnQeq5)ENsxatJf%T&Z*!WhjoF@V7Wv~NxkY+^L? zXT~4~1}8UA;@t{2s0Lha9d}`1&`|&t3R{_uPq(1_nLQ)rgF{ z!CCnhJ2YwBb%7-faA^s0LWeV&6O2LSy>18t!yLE_gDGfVASlX>LA@7H;dKil$!KW8 z7!5vFe!9R@Zno*4uX9UDScWh#m`;S{u@%rfrtAVqC{{PPWt?0?7#M6^AU017GGUBi zv|=!R#=yV;@_QIqA{rbjF-#MK7)(_eA;p-n1+-M?1sf(deccUiAxK)x1Ty7;|g{w*ryB(79hn*(icmHHq9?@T{*lUp5> zNnYRNRHwFeB2hfIbM@A5P6$b-@1rGxQL*Ddxx44zrPPu`K?divFamzC*PJe!j zTe;rCoq<7j59nm}U=~n9VGPpQ%EG|F7!0l#PIE9YI6nfV&QNe0gK1)bF(`F5x-l>) zx`Vw5Dqk&J7#J8T!6`8c924O5$>8=JwBLdWY%a*b(co--&>fVnL1r?stQBBnU;rJ{ zt_OAk3(N88GjDUt*MrI&aae7^&H}C}+Bl(^^(ZF;gCR^7oLPT@7JV=?TO%&GXs9Hl;4EceFrEfl!R*Aq&@_GWJ#HmP8v?W$17!9EsM$B~acfC~%zg&Z&N6XF zJsX2@0BHZ269WV1bh-Q7a(v)&u8JAb{BW4wc%NHrdcu8fVTi;os6-t|!oUGkb4>9D zyAQ3;ofI1euETHZ%xJUz~25^xk#Go$Z!@%HP0xHrzgBw?%#tq|~4L%GE zy6Zs)_kU*I11dd&z-7_=|hFfcGeE?qeWx=Lh@OCSS- z4!DjBU<3^<)Cn*!cx9%56oCrQ`2q|KI-p?)#sF|-eHO%zn*R79w?jQBb2EnP34=l- zf)Uh$_$&ym5J9Fw!ULQ+^ckU!O%} z!5DPmJgDkTou2lX+Xxb2Kfo0y1H&Ask$WC<3qxeIm>`MtGF0X>T&4pmBOU;8hSn2q zg%D7CSUUjWj0a2%44^KGJwnVBG)fC<9vJ^+VqgF@GGdS)E8kjJ~G8!O#l3pTUi+tjo%@npiE+# z0V^U~p)Dx8AV_HYJ>yoEbarH52nvFD3zVgHfU^$+L&5Y5&$va5j6vJtKwfWwssTm+ zRR#tIP%O=Wih=Y!gzDP{(kBUyL{PpjVPJqX;oZQef>yJD)^dW%b5H}7agJp$1B0Fi z==|vhu#Afc1A{53#-0cYPEe5#@~j2u*a%n$A?P``Y`sq~{4yi;xr_`9-t$x$7?@5n zrGUgi#xpR0#eJrMc9ky!b z&dklSG8oj~2W|KCI}Tc0#>)cg!1_%zVPIh47h~Bl{nK-9Rnbme1_lsjO$fNm&cFb| zoNK4+yx^9o=K|fuE(@v;_yU&8F))BIXB}UFqbUOe2y?b_1}sr#U;tsxh3tWh+zbpL z9M~(vzyQMjppqDbIbH{7Ff%ZKFlQd0|4UW|1`y_W5^$7(fdPa$!?^4U$tp}2h%AnnH+y$!oS=>XKzVqjpHkHlV!#6EhrDE&Viq{7r2_+!0^N`rJNbJc->;*{dwMcBx zUIs>}&6kkG?;){YLD-N}S-wFy;Ka%#%fJBB%#XyDMq=9{u|1L4SxD?MBz6-LyAO#y z3w&5P)TPUiBsL+j_aU*bBC%QJ5DryCVjCf`{gK$9(Mg!cx?$oV|4)Z;7#J89Be8cO zu@54#Pav_+BeAa`vF{?WpCGYcBe6e$4=acI{wIc_*w2yJ?~vGE zk=TEb*vz1Q8q`cKB(@+DTLQ`k`(GZ)0r_7IiLHyoHbG)rBe9*3*q%u203>z}5*u{B z1uV+ugAXf*x^xYaqSHw1>qzX!NbL7W>_13s(DrVa1!{_jENX>_tfI`gKU0-AL?PNbF}wY|y>Qu#otNB+d<*-+($)8;R|M#EwK_ zr$gAFHXH*(Cxin^e+<*6GoI#AuHT0w^Z<#?3>vzF+9Qa>HbG)LA+b}D*u_Zf#YpU< zNbJiHHn=On06G*2=2<4y>Dx~8#7Sm@4he@kpcjcfYr5_k9_7$ONJ3AL*r1(MFr)q> zi7SByH=xE@Be6q}*oo7Zp5bv%+<+u>9*O-CiTxjmtq3~F8)~#3659!hor1(JobG#; zN4b7JlF&gU_BkZ>Z6x+fBsRAOBEv}_u~m`S#z^c?BsOUAHKQ}b^yB|E1Vd|)B<3Tr zcOkLwAhBN}vHv2m2XhQ#IqO^-nxuY<&PfUu*$F^~k|fZ6#->>4C?7ZQ67 z5_=aC`wkNO<#fl(Jo=Jypl%}6eg`DB@AS^gJl2x4k%aalu}@9EdznXE@->nWFX)hH zs7X@Od9UzT*C!zffesskB_Gha6EOB1BsD9L*jtd;2awojkk~hn*iVqyA0TXS%ZK3) zgaZyd4$x7~P&bMou@#WmI!J5_B(@6@I{=9tgT&52VwV_$PJ4w~20B{~=HnhDMKh4t zOOV(bkl1^W*e8(Kpsma>Gan#{gAVEfi-Y|C14)7fG-(2LkN^@}28peK#5O@h-f zL2wutKnMOo9mIpgmOx^wOb_JI6t}fS67oc1ha#~Pk=SKO?B?m7*LnIS70eJti767> zY5K?OJmRXkNJ33W?Ab`{71MQZ@QB-jH}FE;eFI7QDH59*G+zQ$BZ0(Lo!)qZ$6B%+ zNvIczJ!|^a8$74$D?ro!P~B}v>?ug>MM&%oNbG$`>@!I0TS)8|NbGM&Y!=W6yEEuK zG6n_)AqWSYO%;&X-~*+hj8Dh3?%kaB=+X%y0>}6>%Sohfo`madBFfQ zaR@!5*aUQ&Jd|w@5{J6T6U4R$ha7`Hhz%779}^8dHaH5T7s^gWQd0n8+e71^6vTmQ zZbo8*&yR+R&qoqp1!6-j-V9k}X%>|GeDElgi4OM^Bx}JeSn4N(E zq~Q@r0;=dGhz(Wr2Z_xCn&*Hz2(+x2kqhE`anPB@P_`118eI?@YNj<3+Y`nH6_tJ< z4%E;{5F4r?3B-mPng+E1w1}w;Bo0*r+5*oAWw(IDq3S!3)K3J7L)FXxv7u@f+JFwm zhH|!pBtS#L3=9khkl5g3pP}M+K;lsKPm$Q5!>JgdYFI$0dP3Q}NNfcV8>-hB!LDa; z263Ri2Or%Gnk{EwUI77v&LE=#LElBKXAU4!N^O4x# z)15g%;m^RpuoWZ$HFOV%%?F8B(6P_LP&WA3XQ-N+AT?0-6A&Bfh?gKXRQwBw4Hahs z9fAyH3m~x->XA5_AU4!8T{{K_kj0>>BwLU;RI?ir+Z)7&s`p1y9|01Fs*eY;p=vUa z*mWQ_C-h+Kb|?qr=Ltycxga)F^D-p%9uONEq(_n1=aAUoBcq{ue}KfHq4FQZ22V9J zFffDizc7@;XOAcjWsunFAU4!DIv_Swy(tpg8^ne>CtqNF1vEI*1Kb^Ao~`lyF>5h}|_ud>WB;w8){~=6H;fS4*8^ngH4*;>D>Z3tysCa@isD_0~WPv0sKuL>%As@sBxsHK>p%aNc7m2+LiMQEIB8)~TS^xCI9;`Iqg zLS-N})Lr#R><%P$ABYV#VmcCgC5R2xy9tTC8;SiG#D<37OAs40tPcvpw=N6}pl#J4 z_78{zh{^B=Dh?_{1zZ^z7@c0pfx#5SP6KOYa09WS;^81RX!4wa zfgu*ehKlFAg3>dzWmpE1fV!>*#8!eB)Zog%APi-9BZ>Dz#X+mG7J$T|4q6IgLmj#a z#DG>;+!@$76>V`<${2(@Hi7f*IgRmO|gD{jW2NH)mR0G6@TA&MJ zLoK!fv7zFQAU0IJ4~Pv~8_mGL5a7nZP%jMSM1v%tiqb%AsOD@C8>*%W#D=Qr1hGNO zc^DWNdO?nZvS)zAp=!2(*iiA)AU0I|5{Rt^4&8c&Yaq=K4#Pu`1XR&`B=#>58|t9{ zAU0GDAE?s>)vJWWM(&KcfW$!+9RmY{hdTplqlffH+Wz{UA12f`Q=( zhz%7#4`M^buYlN4@%tb)RQw5u4HbV6VnfBhfY?y+{~$J0oW+xYfe|*X2ilnm3q}!; z1XP0@h;0dqBnAd`5E~lb+MWyy!kP@=yH>10;!s0fkl3CeHdMVYlKL=^I8=RoB8UT3 zlnPY@T7+5(5{D|PLt;0B*iiNDNa`nm#G&eEgV<0t^Py@$t5es5#Gz_-K-iG{w->~L zYB-3b;S@+5s^KDt4OR0TiTweI&E|!u5BZVU5=d-S5F2War59-R5R~IIec~G)@%m;Y z`5q+pA`lx|!L3GOZ$V=31+k&AbrHmd8vPuJ&E?I&zz7u=Mq+D%*qqQI6e9=+9Pidh zY)23qs@V&Pod9A(9hZs3E<$40gV<2LQ<2ykk=VPuK@}oY(FKqM)X_?$QUbLCftJ7#NIw7#M`1Y&(!RG;RAJvBN-Y(CxRN1Q8A5KsBTwv8zCAsDql3 z*gZ(>sUSAUAO;48*&sI5oNXXB)Z)D$HfVVqX!#w;aZvUdAEXA}V~`?f+IsgT!{M2XUYpT#+>RfyAL2B0+4Z znpmhB&;s9FkT_IL84|l1#D=N|nGXt4kopdgI8=Qmacmkl3C`>{ujr8WOuE08|J;Eo%iyK-qmr?CBsjG?C2(v7r_pKw_UnV&4a` zq2|0mVt+(p{{pc=W`Z+8AR=Bwkl02@Y-=R87l;i_CxIX~sMEs0zz`b9z#t4|CxFDE zYO+CWXj&=&v7zEsfuKSNw2=UG1v!#LFA{qOhz->|7sQ5IundX42gHW@_$U(l91{CF zhz+&t35X3br=H;lg2MpX3C9SLU=R;N#J2(xTN8XA6QNNg(*8)`ui5<3ftU5dnR1hJw0(KZkps&^6+dma*d1C$N!#O;A{ zK>j>|#6E+>zKq1aj>Nt<-S#Vwxa3PDp|?ovFVl0s@`%?ngdi$x79=(|5}O~1Er!IF zLSic+vDJ{+dPr;|B(@cV4T)tt2nXa#1~(+O7ZTeai5-l@jzD6^AhDB?*y%{@d?a>p z2&f{5Mo1NsL>&^l4T;@_#GZu2o(5)5k6WKsH{BpG)OY$>4`KH0cfRuo1W&iQn#3{v zix;m4qsDYwZ(e`KHPd^&dHtEbuus3|&FjZFVY;plum5zN+esYLTYPvum_Be!Kj*{i z#~3hO)|c0xv1EEKi0YZX7ewuu&g;kP&v;~dEQm6gz7|B~O#cg_DyIAT^ZHMJ^EioP z`VxO$55_su-}>|VGai_38^G(&cxHMpi1L|!7ep2E`L{h9uVPqz!@ z^(BHi2Fosx?d!(A7jS!xshN+Z$VVZblWJfLwZ5f zn(cR^c$AXdJg%<-u3j+f~;dIBkENRwDC7_!k z!S^|?iQyGs%$vS9hF6{GOVjjcF}!N57ke2P9zd>v{IS_bfU#$~X)LcgAvApW6s*4#IrcP&!<5gzb^bzp)~^rX zS3;(M___}n7!E)T?}_6TV7hQ*`n)(^HP*Ke85kO-PyEC$JpB$x{KL`d??B?YpFnp~ zCMwG-GtQW98_%oGdV-0O!3}a7ywe^tnoUnss~2H3p02=DCc>E6`~(cmk+vWhn;B0(H-}Gy$;@PWy$hdMJKtQs?R<0j ze}=-Xl93eOuJV~*Uz~Bv_7E0G$pnh?G?Ew!?>lL<(9~HmRq8eHDJ=) z=P`+C@-lAOeu7_YzcZ7$8OWPr+vf+1rL!@an{DTa60;A4EB0G0_MVk-%XYhsVyYo9 z(dmAx#U!>jv5F^w-2RkDd{HP&YI|RjxGoorH@z=OJbk-nt~er64P%ugw)2*YS2Hng z+1^bl_6J@lR{_v-b$n@WS5Hta!3@Ek3UL;5 zGtfpJMJeI!qMs!GGP@X=G9;BG#uuj)#22NeGsMTch59*%c>4Rr$E%o|85?1USfGoT zm`tANBECKMn?#)&ijz2GC7*&K^PRlpL0J@;Gq#f9B22bCh`mYMV}m5~a!?e#*e5A2 z!nkGIWyw5YMwjXN&mvL6aK zw{KV~rEH6$>*FJ-MP5iE;@daqO0#kr1+gw=U|`_5#LU3JmIGmf&KF`Ug|M$Og6{le z1F7L=i38oYx@G%wGwChfFrygns)}#l(IlNA!en9$ifeI3!|4I`b`H}&^cQkYFDTP4 z9{pB^pBco+`5+@Nh@xf%qimNEqX}YX+4Oa5g9N7EyDz4&-OE(=G7F>0b~!8ASbG#* zGb&|ovNGCjFRGUfg%_aUuz9jrR$l_9c4C9N#CF3yvM%h?HC^QdwznRZwPfJ|oz%y` z{F#M;fxU41spGOI7$w3MfOc{JVqjq43kRL>!N9qim4SgTV*09+vTBTx+b^D!En{PJ z+wO5e)`^)hZF=`**@=v~+hwoFrphuJP5;PPCd^`DW@#|pP)1Rh$=qbRqP?9klZn~% z3w{zJEGFg#X4~(4ls(JNWMDRZ^-tLZCL@#SyuV~y84afIeJm?Jebp~nDP}WE^XbQb z$tp7%Zh!qtmd6g}i;scA;@d?m$YpT$~|L;dI7Wzmc4MhjIW$CKcoBhgc!M_ z>`FHFrx+O+Kv=}io*Q)EFX%iZFZ*B~1_lroF`Mq5BIm>yKfNnO&WurO`oR=AM@Iea z%&BrSO{Oo(*MXudk3(lrsk#2hI9~_HcmF4@8MI^T`nkRqSipkV$d;U%NRcuVA zX44x_$?I@0;2#- zL~wWo{adrnnYKl#9Amgy6uYX!D*OjEeT$koWe@PLCs_5%aM^gGiP zZcLY1Z7wl=LzIog^ao1b64Misg?Yq^I1qPR%W^X?@Z4Z$V2GVAH&elqmyex+fr*LL z4RoFK$LT3E6?7Q+rca!yAm#-+VS{A`7Xt&cD5w|30xEKt6+sK2S(b4yFfi+a@1ZW> z0$oYH7<66m4bT;hO6x#OYgPsZ7Ui7`pgT^Oo=yKaQ$dAy5hnu!%L%YF=fUYpvlRU5 zIY8Y+{+*yRKKMC#7#NuNKd>+`F!L*du1w^=z`?-4%E02p%D}*?77Y@*1uBRldO$Yp z>nb@Fq>RM@B(Rg4fq_f%3g}{85R;ANKIjDcSBwk{ zLa!L7zn`Tbrd9#ExklNi9_VI&`1>xcMWMp9AbTmf(NK z#K0iUKY@vXL59DRk%2*$|2Q`TgB-sNXhe~}fs=tjfxm-=fkBa9lZ}BviC>n7fkByn zIRgWO3cmyk1A{7m85aYC8vhH>MrwXr9tH*t{%uSQ44V8wtn~~GTKqd$7#OtqLC2iv z@b`c&Y2nvr23@Bt3O>z?cMDqu=%`aR&{+%o=1dF>jQqzzDURO?l!W;2gOUvYHZBGR zR{p;%3=C`xV%I=Nlbi&_2I%Y$#yNbf3=HC+baIxRfk7N}T{S56N~nNNs(U0Fi$~j`oFmf!u9V!6VhT2I2afhAAn2*>1Lc`1~c&&$V5>5v2rjl zFi2&CoL6QHQpmu-unK%IL@pZxgLHBd17q0^@YyX43^Ils3=FkwunqI#prv(!91IMg zD>N9uE&-h~1aiq%kV}ljWk8akV`#vVkx*y;14)Wae?Lz_Mp>N$bUr8Oww)*@&i@SJ zpk3==#h}9}KqdvTO`kYVL3FzFd^ zK~{mL0Kky|N;B~sps@x;7f>X92Zao6*`~Y?a1`y^+)>_WazyQLmK3b0$85lsAH9`9i2Ll5L^Kmh1onc^L z0AZdK?KRvC3?R(M&8TI>%D@1^{O`3^axyT0Fi)aZ9tQ&h2y-cGtz=4pmx z~*-xn(sF|L}PwM4-jLMgNVW(8$~{^<*Qn_{Q0YFGHR-C;w64dZkH8NR^n z8~OA$OkX57Lw*rtMHzG2P2KQ)K#s?pT583d;pWwm;aRV8z5_YO!5r zw?YRqWYvuR-LK%zWNI;e+J1%OeEG$h@!-IU&&GKXL zC^K4YKXgc8HIoQb7wF)95gEw*@}lXPM-@yMji%2#svs^2Eorns%_3O_2GF`o5S!a% z`njVD`i!R2{~cAZW&tfYnqDZDn=!r8PF!XC$zux59EK^N{0FLi7#J9uL2T%ciW`8$MInwc1+k%e{gK!SAU0He1rmD>hz%;R zK;!;vKpd!|9UwL+m>3us_JY_@@sl97HpH@XAU0I|5)%6+68rA-UhXXG=^YBWJkw>0 zw0I=hK;;os6BiO&Xu4yOmN>60l91wb!PqSE=`}@KJdDQEWqGp18SSPoEYcE}^h8qS zi^L9@ez8bPoH1d#Z)}!0Z#I%l{`Q9#6{MN!=YR@F@X3A*47WjSP?ZEaG7!Xu#&jbq z0|O&8M!|=>K;!B%NE{lt%UK|G2`D5sLfN3THM^l~P(%DElnq*pbRNR4X8`4j%McC& zs4jg5VnZGA2FeB*1ZtrPaWF7|s$^zRqXg9gW3{8Tnyma$`&dCswthJ>{tc{245&Un}LBL9Lffrz!VE*gDT5pC>wMJ zYbKOEiGhJ3AIb(*mZeZOC}UPa*(*S`8mRRo1P$IvAPHUu29S?uK-r+=I1kDO)mBTO zY*78Q3d#nh%neXBr~udkWrHfw;~+LP%1%SsAoK6BGB8*QLF4ZUNP-{K5@KL@1!aSR z`U8{=YHoakvO!vYZCAafkj%uSqcgqhhJqjCjOjOTC}=bKOc%6d6rOJ2Rwux@L5G3i z2?GOz$#lg#Qu5OUOj22}$caoB$dwgfd@=nbNOXgm zG|TjY8U>N*1$U(c7{5%HyrrN%eS>8b%XF7p3M!0OrYmlelmHc4phN=l2Pny1nSPLw zQGEJ}TM7cKR~Q%=9!)P?C?-7p!Yu^>#vRii-cnF!;?bMVbz4D=m4S(YK@j3hkJ}0Y zj5nr7-d0ebE+A0J!ng`7KJB-<04s++1H*~wYi}zkGai_J@wS3GeB=KgjpENrcW&97M||Y(jdrU%)k&cz4xwyGGo&8jdvB)S-0>p zFmyr&n?KxD5Ma%*Wng$RU9gZ_czVw{evau1_Y^o-ZTT4(JRpi3?kNbc2G}t$%$c4D zQj`JWxAMbBuqWJ85SYF|N1A2&l6wj&tb6$x82(QWv}Y8a{s5%1#-4$}Vfxp53d*c| zL>U+oryq>s5}s~wUqOITcKXEq#p2T=?kfneMkv7zYyinkm_G5of;!`#={rHxf$0zL zE2uNEI8EnzprFQBFx~Khf;#6HH3kOInNX(F7s^P=v$kk4Ff5(^u!Bo@`iut(@X;5+ z6n5w`r*e4N{R|;r8zlV;4;Kj zK|?h~Q$e-ZNT1F9b^b(U+>0>-sq8CAYZvLASu zpmt-La^bAPrUlFpQ#2Wwrq6h#ux9#_*9s=nKfG2jn4WM}Qeygs&stp5^Oln!Y`1Jjt8*jYe*Sr*pJyb=Z`Mz)8b-t-hk1_mb3Nqr1Vj2xFi941!KQNApe%nS@n z;06r~sO!cg1zM}h#KCF{Qp3Ui6-0%wu*QOD7WTEE<+&_OEbQW-&M^yU+>wcqqXg6! zWM+hqH@pQgb-?2dJWTNMhCYxx6hUP-6C=}7rs?nBDj3v*`nL=`2B4~v=LHi30~1dp zNHb3*$VeVdW(LqW!civBI0ERDZ5CT51_rh)Q2UDo)Nf!b1RXoZQq91?z+MLG@Uwu< zaOIE!i+V6IFmOnNh6i}(GBGglaLCVOWMBXn;~a_}pe7}MeR2{5hf*BKWqfNvCw?h| z4B=p4Sq;*wk_j4p*Z}GS>463!KmiR}O2s$_#1qV9U^D=^1SBjJ%f!F{8k}HYV*%-6 z2L%m?&jIS(NizuF0-ffq12PI!Z8CuLG0rJ7Wny3uJp&d6IS5n-iGlmtb|4!-hi8L( zsSco?o*V-MgEt2QLnITVOL=^*0$)Ao+z5s+4hDu?CU6G~baJW`sFDUT1h#=XY>PmF z0dga#f@GXC6Le4@s9s6}mHyJ8x)-t(4|IwL)w2?L`)C^SIbO$AW63bMeugW{mrTfzwKvpaC` zGB8MhnkS%enZOJV7e91xRiKqiT$F|e_K5)L>@K~4cjDKCRCBMSqA>{pP>!3h!+ z#7&?8pYxW5fk6};jai^jdCS1S0QLuHoCIQ_IH)lPj#bbqe30vVr*E9AAjTL1vQpd# zv^b-ggMncK3&`=&jHWPGgPb16#F4@v4(dUHOpplyrwe2k=Q4oZ3bGFDRz3z{kdtKR zg95z{l=MJuodtGl2xuq@?AAJvTR}r_a(19-s{=(2V=&m^AVpAzgIX~lYb6xH)-o`( zfrmq&4mSh!c|Zp^a5lo2kKQLm{&i8T^G%0j2TBTpUOadiX2DvkT?R_2aY2F24Rq! zWUqqK(@Id-gW?Eu+BM^xD$r;bD9eKGumD{;!~kZ1IsqUCgKQe81X%~u1R6SHoU@o6 zmI&8@n9o4v9UIF^b_NDvP-?E1l>lkl2Gay;4l>Sp&(6T0SYpV)2o`5&Vqj1zF@o|K zgXKY&DKPE?RRWAb49Y4jpkZMqCeWSN|G_{QbikuBs7b(bl1U0A4)O#816Z6LR4(ds zFff4qnO4jU1`y`F z$f6d;$iM)?s@$L(?im>v*jX4=ML{Jh69WT#EDQS3%&$KRi>7aU%`HA%$y{ETlh2CV zn%h&DNql@_|6gH7$ zl3-v^WMyFHfSJO;poGMgm|kb2A}`9#z@VzfU@vJSna2k$neBvTD0MWN~c6VgSdeGK849>T0B zpa`laKn?)81w@02JP-{kPC#_r^tsH6%F|;$hVYQ0fjtR4AhvIMp+jx#bon|(we1Oo za>p2_uV7OQo36~RsKux^-Jf02dHVZ+29D|f*cDBt&)HzZHT`+Lvhehr=Q14AE$Wr| zgwHTAGP7_pGcYoPM#RAE>FYK(NKSXSr^3R_%*itS1E->l7>ET|15wG$$uwE}D-~pvpz6io>ZQRd5hlq_ z&#jPCW1q|jawGF}kR}e8Ca~1xnQwWfYx5`y%B^DrjqWisFmi&5WccXbHbzEfCQjz* z2kxheOwZ#{yd_vr7Lu8pTI8Nu0;WA(rl<2N8c*M)s>n56T1}B_`hH%;mg#|fipspD zdBvIOd8sK1$r*`7)0groW=u_x5}mHcujnwnieIs6x8pNRFGr(hb4j> z)8lrjaZKmncNYLj@=TX+QRbL_U=Ih+^ni?5o@w6lJkuT4G4o8Hm&C_2oo78W&-9uw z9+l}I*2?ls-w?qgF+E;b(PsJqF?WgSGp_paOqUl?^qBs>Rapfj%fqNSec~x*@#!zV zXiH3A^Fmu>x=%^0#`Ki-Sc&O-QnPuc%OqrTOc$7`Au#Jwl&?O3 z3QGn<23Y8{CoX&VmUDi;AAs-?JZXGi+K$q%6#h4k?7(mr5hzn{NGBW5+zyG^Yf4bcb zHHGO>=Fvve&*bsQP51lLs4(4*S0`Zlxg&xLrvE!2Xu#~k&^`U_)M9x-&_xI!13*{+ zGy*u?)*wur9poD!2D$0^&nhK3K}CuXg95|n>AKU3#W_JGix7hn1OIeKQ%7-kPyr*v zpu%7Ts>wk6)j&s`FsLy&L;0YRP>4Z;ArQ(3Rf9qdS`0Z*KFC%f2JPvGl@$%9^Qb7Q zn8Od01xEui4{2K2#LN_F%Gt!s%osAs{8mL#j|(*3%#fR!Tbw$5uBxJrNCi0exu@o( z7G)+o=jY}o=A}%I_66Mu!oa{NJAGe-g7WmGu`2SQ@ihiU=mKF-m@vvt_hW7npT2W~ zEYEb!NCk=Mk|``a(=At|OE8*DuM^M`pKiI>gohW>lLwFaF`7<)S0N$}Qmrz5r-mvh zjn8um6z71dQJ8KSr64o?=ZPSL>81UZ!qXf6E3!`C87sy!T{Napg3)}s-#im>n28`w zjHc7?om9s(5vB&zSYM#jgW{|V44_sMs4odp z1FE|~4M!2ssU)DCoFFyokg07@%`XC)%>+&TLd8MqL8Fn}AV)Dk4*dt|1(^ZbYRYZO z0I?0Ul@ufaidzty8#G$Sz`y|NNP!GBoPIE*QKTLk&LCq&pc{2S4R8<}G`$I8b3?Z* zfs7Z?f;bJdIUB?V#Sh4I5F2C$sDA}wgPa5EIDpt7b9_P02U*R)09sbe01^keOc(4& zJ_ZJmW)KERfKC7avAID3$pD!|5CL7BFx}8IOr##_b5MYRRD(t>L2PbN&wzn}0n~{E ziGyMU#O4Og#4$jc1RzsD?E%otB}fgZod{yXLK9R3g2X}N#vnG#Oi(b0XhXbS4~|mk zs61#U03-o&E~wi9VuSn(YTkm_pzr}r`GVM>Fadj4fPn#IG01lyaZosb*f2+cj_3x7 zgMtCXhB*RMmWgOH)Ppa20CBiM$D)JwHG=|IfPo*V22h@X ziGxONKzc!`1H|T@UMN!}tOZICA`;LMDNv~>2MIQiGGRH$N=GRjRqC&Z}FE5`sj zWD<-S<)-&>%7KMI0SLm3a?|<#N`Qqxkqp9&a?@9(%Y%hLaSFnWa?|~eD}aSSu?E77 za?|I@1n9HKF)%EdzEQzRWctqKJSrgD_AoFofH0%n^g8JXu!<|w7Zw(YOg}0e0agLJ zMFoUGPTZ9VHkJi6mcYSX3R=)L=AbqVC|@uzFo0VUP&O#A!1rP> zFff27@)$wO4;UbI2qP#tGk^xK85m${K;;6A4JsaBY*2>?#`cHU1)3gWU;y>MVG`gQ zgP<0J_NBnYiy<0736Y@+iQS0A2HhJ6QxCde3dWv?qz1I23MRe|RFJ?pphZ%Gicp90Be6j@*1*(ABZ-67UctmQVB#SE8^buD%h{0Fpmj?y4IxP4 z@kng&HHA<|lp%@tBC%&7v6mvT*E52)ae+#G1_p-Bj0_CIQ1&s9B2WW?fq~&Phz+#> zw44g&pl={?P!?ohVE6^n3uS{AIKb5Kg9b~W=7@mUP;=x!Y>0S0gEEK%)vSZWb^@_M zRT^j%3W*(p#Et^7p?dR>*ySKL)Urkp8(IQ@t_Ko^vOz=JjNG8`XJBBM1yTgnumHpc zHPRUv7?v<0rux?-iSGfip+}6I1F@lcK`ZrO6a9BUdO`Ix0|UczBsCvFY>4j}zSV;` zP|eJs@jobA0EsOHVna2^gV<0tCLlIc95hb=3wH3}EvQ8TT3P{819e0o5<3dY2K&DN z#DNBNB@(*{iQNriLk*n>VnYqx31UN|U_Xcr6+eN*z6D}K&3}x4W5vIs<8s8hlYYZhz%9@1hGMN5a^gC5F4sD z9EqI^Vsn5B0R{$!G6)A;z|XN=GN6?RP@k!R*iav9gV<1U3nVsZZ6_nB;l{wg z;0_Xpni+t^P6M$)4h6M5Koj|lAPxfq18CtUj168I0X3+7`rqRz;k1j6Vb%l@huGW$;(#hO1_p+S(=Wbv6tCX^5`wyA zCldP*68kiW4b^rL#D?1W1&RF^iOmmMAp2G$5a!7(EAYqd8 z!II#DhhgJ%-d&>Nyx?{n)UE^51FwmTGhUt^dre%N?H*Y1^k33)W}a-IN*G!kaUrn< zk=Wqo2vm(clDIMwTWfl*jGTBqXm$yfv0XsYkSxLgn#zTV`y+{i?%;)qgJz&%>=Yz5 zpqq+e;zdZ};KmBn{91_k^!XiPto5J?W|#)hybmKZXMt9v!`PrH1{fQ(JRQbf12PDz z9y~7$Wp76k-;KmRio`w%VNZX5REl-_86yJ;UeKHjBQ*cKn*P>NT-@m^ND)*BH2uN| z%_7{OY8=WILSl;{u|fR_M)~P^MGDr_&+r#Tz?v5EVQx452`z%6|gsm z4JkhuGC*u-Go}v2hNh;UAT~5T1c0g}Xe5BvvBAQT2UKE1OBziO8|q~T5L*IT5`d<{ zgrJVN&BVX}VuQL{520*OX$QK`4I~cI{|zb*DtSQrT0r8Ujs&RL17d?}A$DenIiOJ* zNe~~;!L4#IDp=?k;={%GT>N{SAvO$yIw?WhTAkCm5B+zZuAU3F< z^c<=PbS)g{j!BSs7U*tgs5oeHkOj2d5E}P29jNIEWrGG{qCsqs*BKZXQlV^+#raS+C~uTP z*`V|RYJUkq2WdK?;-E2selWWp(qo(n=0FAy7DL&fvKX{59HbdE<-8s$4jL=j3}u5B z)*J(|p{2tGC>!LUTTnL0K@Xs8kb_=9*`NyO3)poc4B%_+e?cWcU04Rt@ga=4Z9=mXc-5vDWc{NeNR1c+gDYqaA&3piCZO>%C>!J;Zx9<=vIIierXUIMN=*q! zEblz^n(M5rQALIqVRjF6#N29D`-|0#+yN=z?|EEJ#K@hY8X`kM*`9#zl~3?nEd zf@bPLbqjPz1vFyF2|!SWi`>1R`A*%?))_nr?EHv^5jFhWNm!RkR- z3_7|BGZU0(8KGu^(jcS$^mo^#;-_oAZSY{^p5AvxQF;2$N(GhaTbH@0Oy{*P=9ykN zMay7%q=uZtblwz214e=Ac@rzer*p=sCrn?tz|3HJ?lu`7(AX2mWk*0oAuJ-N$KGiW z7XmF*VuS`a=mvX6@##tn&6Gi7IUpS>paKvYq6X6q&lrlEd4PnVt+@~o8`{bQl?t$C zI_Ta=Mra?U0;EQE^2W=0(*yR(Sa1qxLq?U{ryIr<$WPy}SB7Q!l=lK6(>G)&3UJD3 zLk5K1rz@UOm7o4$sffh%4Zk@BI3p0+-U-N07wD0fm>x4nOn@^*8#4CjKD`knkZ=H%k&w^%8>P>yr2OnP&k9`o93QA@x7?@ z^Z?L0)CGGCM5bSuoFKrPqr<=e+QI@-!8<+CB}aO?fvFA4^e3W{BGcd0DhTj`hU#Eu z@K4_eQjxI6jAeStCjpV^7OTw!cpG#fX6AUz0w}CkeaU8 zAtXJ$;G8N8BQHdahk2?1tB)Q7gT!>l=SsrU&wLaWm~POc%fcuOQSfGApa5%%9s`5Q z^od{vz8M_TUzn!yFy=uN%;?b-VC?`6FHV05Qefj4Bftt84``bHF_&9pda7d#KkEd2 z28J8c4PPh;PtW0N7GQN?W?+~F(LYD3L4Y^IfPn$jG6H!|W%|W){L<3{E~v6F#!YW* zEEJhO*FcV+_ktkdN%OvQY8q z3X8Q^K%2L~#k^^}JJch#n$ygwVfcBI4 zPgh(kEi44OPZbo{pm_w4RDkSs&J*6 zt`f{E!1~66fuUl$;aer)>2vaw1z17j2evqdqLNx%r{)DRP6W3%lC zw<#*gBN->Y?V4hGAd-N@_EvQzMsdiUsU}7i=Gzy>SBf)k-(s&ckx9S;**qglerPA*bn8?8#aq;ao@01odp@{q`Q0`>r$pSS-SU>~v zEQQ-AmMBlMK~f~aVr*b)2HMliln^jIZ=-VB^aYNLGLu=Z3Qw2cq^z|)bd$0(n10~^qr`N9Ey_0a5BMOdnSp_Y@hu+%1CN*h14A`vy%;F!p_qx0 z?G0!R@ETBgAOy-MOpF{FT;R>l37}2Q9iaWjVxXBCCMI@UUIqph$XaLSXCMhFP%oN^ zg}oZY;b6T7TDZ)?o(x)tTyM??TB8hVLojavt&vs)HH?_QbA#3>gF59*EUd3Ui;!8^ zi$UuEK?|KDK+BRCIUIRF+k-*QR|GXZnL#@^S(HGFXPJ+Hwyr8qVPIfje#XVXz@iDd zG?YBWqziQJkz7MDobe=ffU;?nt&Fr?PXwK0Ck8t zmN76e@H4Re0xkG<0?V=KO`o?_S(-6^`mU|Y(o)xX7#LW-FoHC&?EsnZ3&K9fKmGky zWij`;pnS-619a6mS0Nh%0}~f$sXH^*1<=&T0kDl(cO*xq9Gt=~i+mxm2B{>)vxTHY-V&FT)$-uxR{SRau-#h^Z1}+(p zW)22sGcE=OE;&#@^Rs~BfO{_Eab^Yvu5M66kt+{$$|x78GGOB3WMyDr=CTL5p6fg} z0|P79ZaxMEHm(L<1_pMn4$u-ouH~SON?f3`Nx8V{*|-=OxVbt3U=ZTs1P#)0C37+`h;UhOGBAj8UF2Y35aa6N zWMB~IiUqBv=BfiN+vNJr%)lVU1?pW(b6K)5FvxIKF)=X6a^2%+V36Yitr?Z)`d!b% zz@WgT!^Xg%$R*6lz@WtSfRlkinF};oqr$a`m4QK(OO%g+L5&MEE27S|6jbhWbuln7 zXmZWuW?<0b+Rnznpv?tps_Ssg<7Z&d~DC``-9BBqNP#1~Yk?l1z1A~ABw+mY_sCSVCQsT;X8I%EqPJ(Q91KYs@ zG0D9itXqVEEdyk*2b&WM1A~AFw>R5fxTAc)8W;pqGRqjaeZlS!fLQGZ)+_`u${)-T zW?+j4ZJ!Td19fx+B)Egw*g>5NuscE^?tqvS3O1=8>X0z7ZZ?P$!@)MPGqA~k92LQK z667dx?kF}FRt5&a%%W@t?r5+Q1|ef!1_tgJwhnMe<$@NA#iRXF%s^7RKF@rLwGN}CF0*(B$aHaBrvV%2f zdo%+xXf%Y!XfJ3ug!vr{0|QSEC_ONP0*&ViXh#Q|Hy;B7Pc9QkSb&kIfJudofkEg8 zBLf3ZArr_p1_riB9tH-UA|_tYI&Wr1o>Ha)keXrv1_qvTCQv9a2yNnJVBo1>3ILrP zBeWN^zoe20v}%e|3^Z8EQ^myu8WUt-r0zx!eOxHEawF0{?j~Fx`P0 zc@b(P*py3PQ`i{TezG$#@LXov0aDMybCpRFluN-*xCT`}ot1%s=Q`7UW(Ec}p(~uA zlP;JRv4W=9+4gfYF!0=D0&Q^>6=meP!?d~{uKg}lJJ`B=5bK1(LE7(w-TYrXJGGL5 z=K&LFK9qq`3~bFqXn2Wz1Uc&wSfL=J7%v9{1J7fyoDicJD9!LZVFINYVMZ}oPzXI` zS^(O_!N{P>_MMA?f#(?$XwR%DGb7I{rtfeky@okyy38JBNybgn&GslO*MmL#6)IKA z&%nU*oe8uVkd1+@0A%)0CT0!>1_4ff$b3}5Sf{cK_;>DurV)$n^e!v42fzfP+)Q}gAxoI0~=^Oh=-H87NmiR zhld$dN(x;AnZgTJ!XT6gN=y7;4kH5_X#AE(fO#!wWw$mcok%i+ig-3wP>8EDUuI@t z5EWqLv1hL4WMB{i`@s=xaVRvAIWZ$8GG}H;BI5+P$%PqI{ID>J1%QIXl^K-cI2gsc zK#p-^ehI1#7{$~;a_(Rr7o%9r^fh~xW$HnF2OclxuOLUIgK|kQ*tr7iJYme+;qC|r zyMsY!56FlJ=63M#9$O?R1w=AW2GtQ9j65;S%%HumV28&+HGnfmJhHnJpzam`X-?#V zI-G%R`t-nk%A$~{PDj?Afvh_dqML!O0+e^NnEAOF7z7x3a+y;=R)cC(o;+q~-UW?f z^5ir7axpMSNHFpgF}rg!Fo=LQPxBNrgYvpaE+{FLFoW{6h!7~Jm)0|{W@lg!SqR$k zRK^TSmm;8%c%E`*&|wuKY#>KhFoP1A$UjhMRf1z(szo7(^C>qP!ODP?2jOb{#l?MU>eX7d5Sa*y*+ynib{F{% zvY?514d?`vH6TYcGlT0fHXo1;EzF?fXn0vb9^?c!A9y9|KqtWXf(FXCy7(Cw7`e89 z+Hzcr*g%6@P(|`9L5j3NJqs>la1)~*v>t_ts|ei2*akYehJo3YnSp^<6=a^IE@*ZJ z)MtS#b)9pUn}I8u#M4- zh71gn(Y&x@NaaAr&*=s=IY496tN0igz^g?;27ubM(u`4zh73}mfg)rB#6T4aXjHqN z0kl++an3E6&0F~x7`8)fhV0>CkO$cgGVc^bn9+zq3N#uEGtYp5K{5su;vly$fR$vrX7P6KY(nM3kC&xFx*5L-g<~1jTk@|r89tx)aL~Wf&3{Cav;cJ zC$LZyqcMXNXaN~Wl{6zr1%u>i(3~G=uo}D`i*e3mUIqpQP)HmEg#>6I4rD+x!T^vX zVFrK>ua=t&nsflI1_rMcWSpbN$H1VJTb$0o=n2|Q2I}A_3vx3s*n#R=&`2kP0%$mH z3pWD;=+k!SfB7^FZWu{XeR7sY5O%@_>{RcXc;R%R9k zhUt5Zy}9b88RMbCOoa@fy?6}lpv`z7E5U7iQ3e%|vsCRtU5XP-VW9Recni&c6;NM6 z6*Oeba*`WKWIZbo-;qXQnTemKERx1(BBInZR; zLCs4hhUL>4%LU`N#|x`iFiuan!R0ai!Ar&b>Hk<|Jf{bAYp_grIII~sU7%K+XZp00 z${VLU9~2jy9&w9{k5O{^M|%O$01NOw3kF6`Q3eJ^_#TSGkUbka;vn10=gS%mi_cz*|I%Lx;w;Pj2P-a6B>Pb)u|K5-?7`1bNM z$~#%6D?Q{An!ezexXSeEi^{X7$E;USnI7ORz`x!5lCmz-^!k(H+S|8WQJ%m){qAaQ z?&)`34cVtB-%(yZ-GI+s0JO70V0yoY7{~PY9%2I1cPtU)nVz$OSp>X|;sa9(QOJkuM*xmBh+q${aRU!dqNGCe@XU0}L^y1U5q30Ii~ zrausOH<*4w)SYL0(>>)3=O`<)=41tK^t|U|~AP^gZj81g7W2*K%-z z=52%+lo?c}@10m7Km9?t3hVU9XUdJDMrLLVNhQhPQ(NMb6LWHs5|gv13qM!(nl8}9 zAu?GF-`DiyJ~`I6!rPh!R8^ z#O8)-0~N&}anP7Gh|R4xJ?)jUGNZxtE)bj_8Rw618vp{Ta zz3F_fmBnGwpt%r`G{_ndn_F+X-D_p>=_dmld8Q}6R+fM%1Z74MRZt@vG8@3HH+|A; zk!iS{G|Foy|-+d;8lr%J+HduY(GH&_FK(1H(NK8&nQ6FfhCTv7sY+ zZ@3|sk%Gb#G|IvVRl~@`zyMo31iBFuCN2pQ2bJ{<3=E+2%s`!OkX{WWacc-0G)2n5 z;0@wH4Gjdbp<_v*JPZuNP<8^6cqS6N28rDRVnfZD1Y(22j)8$;8ps?ddm)neCLYl7 z{Gj#C3=9lAkR(ncv2TOeP(vSr*iiLPL54!vA3)+zHGh%VT%h&Bh@0FWar#q;#N!YH2h=39i z!+Iq4HYD~gB=#XB_Oa=;>TK5APyAJW!&na*FJuID-5D4dPJvoJ&?FA-$U~FtH;_0q z)d_Q&0;Q$_8nX1+k%yQ--oZdexz9(1;yq zGz@mMjXeu!MFjM08&{Abe#o+QZzvm78u~-opyp>Hhz(7FpgtLB`W|FKHdGvBcO8fg z^?eJJ4N}tuWrLb}6QFDn`O0!%ih)0J3N)TS@E zEyXgOV}78>^aPNwhw1bpu<%k5mgx~7;SH=R0=x;Pkm*WLBawYN?|DV(=@XWTuuKnm zCm=H2;k=>%Z;L5pUIe6qbNa`oLh0!N`(#+AzhPAonI6EVBEY)^Nd@=xjdn58(-Z#4 zuuM|xMcdnDT?CL1r(|TSS83O~)^gu-=>FEMZxg3lKraN+|s531wo1Vp?qBh;&g8&Po9Ay6O&pu-T)+=V9 zGj;ZIs3=cQ=#*k%RD#GQOid7Ak};po#i^nOna4HZR8e87F`pg<5?Nps#WLMMz)xhl zK^D6J(--sUt2kBE7)z#KCQN zRRq{ntQi=N@J$!vR#9TzBgnvD3ZB!O9>A?4!1_^`fx!tf`()4{Ex`1`b9xuIiW;Nw z^o`sq>Z~4K3=C(c3#uv!PyYZ?-Yo+1y5SjPk?E2=D*UV>-V6)}rYC~r9e7j(STBn( zFdUo?K78MzS4x2GiZ=tp6~^gxJSs}8QzRJ}&P~6#GEjK>4jvT&rX(%!JlXUIAdPdi z;Kv4W@Tv%~UeyAfHUyd|oNmCYBEY-Cmw_RH0kRmte7d2qpYZeqUKI{jQEdi>2#9|g zKq#3 ziFt|Xsd^{}?puNm+!x;-z^C$B25G`be0zkpiaiUm2&G$oNfPWTorS7m%|oL>Xg1Cyat7YA;TAw^UJMbeW!KsiJK09duqTsA{;&&cGlB zTFvqjR0%3y5366BhGU{|ulb{{8|t9;Yt&N@p> z=c-TSVdR-^c)>_~`hi0nBGVIkty!kW-Hcb6{$Qqt%JdI4u_Dt2ltF!@56t%46@pX* zn6~SOsB|(hrflCCrc%r*3W^I69tH-`>?6qOAa=}j#~2mmdQcSwT3;n13u&2y*xb+t zGH8_`NF3D42eDyY2~Z$|i~wa?&`c*t4XADevAIEY7y|0u^lmJG@+K@y*c z#GVIYgPIHs3=GRbY-ke*yi^^O>=_ssE`Y?L=7Y}whPG92fz0QJHeH^A6hS54A+dje z*ig-&0aaMHKm#-k1Qj;{v7we(g4j@TR}fneCgGf4#A+b*(vB3vbLQTDf zBz|xDU2S1;-d9LM@3!}5sQ5G2gPJW~pymk==)`3P2GBZL(C{rNbB001LGc~~WrHqp zN`kUM=_~`v2BnESC>u1pSOR5((i3Qk8e}GDg?Tqf92(UVSs1oQ=ct@zVpN%~nXlr{ zm@~Z+M9rCgGGE1idO(aH%XFCn6(2^0>6ry8@27u=@#C1DP^jWD-67VGW%`;z6^-dC z{FNfpUlghcFxE`}S*W5u{eg89%XF0@6%|H<>7GR@>eCHwE3iy20SU~RKC?(gol#-> zK@jz1`b&`Xg&ake=_17{D$~KNBfU~0(*ufC1Q;u(Cl;%yGX_lWELMS>6!>lW#YisU z=_f$49n)`uWWP;kEKyNs<>O^wm;tGl9ZFO{=N|@wgqQKcYsCp5;SbXnf`p&(GB6lG zR6hU-mrVZ%5*FiQU^oe>j15Xv1Q_2;cPv#=XT2}P!0-)ndS3%b`0DhDAYlOocny33 zBWnVaBOz2{nTk4RfeHh|0cHjUqS8tzUv+bN}s-LzYxkzHWARc z^&wdfQVc;$DX`SQ~z?2u)d9;2_OGM(kIxWM!Y`f3u>W88{4rf<+!QZ_?U{+q67pr$^(fk~WYdQO)v&-4fbkcLtvf$0q(R*HbU!1NU$ z)|N&`?dC(O|lzp_=-1n|2|N=^2J<3XDF}J3->1 z(>H>|1$N7_Ouu8OroxysozX~5efpOJLITq*jMOBiO;;3{o?xV=!&p1L@Q{%5^bH{P zT1YDUV5A0FNCb^$Rtr-@Gn2`Mmo*qow)+{Ytzi{P;jw6POyh}Ya!l7` zp}Q<+nfEeH|2|DYb-KX}M)vLej%p`ar}yNia!vmxrolJ;gPYoo=?145xu)OCPvzVG zz+Fv*QEWDJ^Er4O5@;@)M}UDLYWg_~U&(qjsV9 zHApisFbjo)MgbW)awQlTn3-5_NH8$4Oa^tc#XyZLmQ;BL24*QxualXBRYZ`1ftiCH zG{eZu!rCjzz`)GH&LPXdz{ki^L04Km?6XdRJAsuk#tgib*Q1{P6JNzXDH zHf$2Zv4bWU1Z&FGk z0}}%ic%KjhTelSWI*BJBy|+N;|8p>b^zyTS0*O^Vkcojopck}2RDeU8fq_v#j+=pj zN#Knr0|T=FXfq;i25D1(A#esk}XjPQJT`2|zR)GR} z1_m~PX_5>K>;m4(3=A9sn(Pb=oC0sy85p<(PJ)(dFtGT@GBB`37cns~Kpeqt7z^`V6_6uRKu4Vk%%}%juu%qN0qBf!c7dIoAPe4tE`|^g6$e=` z2ed{+;Gh@-1CPKZaRvrnfieyT20npU83qP^0VdFFuRxnH1B0MII4=W(kbtHHXn^hq z3uwPTi?s>^1G^_ES_Q#j!#4}`Gl2|Ikh>1bf;=7~406|0MFs|Lfy1EGE&w_plvkiw2;{DKNszl#6c`u; z1Po+B?z$`wa#xfX$X(AA85l$ajJZG)`?KZi85qO_Kr^!90;@zB7$gL`q!}0_1w@4y z7^DQwfTqL*{(xqL1S(k=7-R)D3o|gt2}FVB?F0-(85k4n4krVHx`3P<1A~S@i5LTerobO*1_mvG=?o0f4B7&I z91ILP0zJwM47vg~ilF8bTOMfLSO7RlL4$1z+ZE7qpk<)6D8M8JN>k@JK+y?md@~Dx zW|>(8j;nw|ZJHQpq@S&L`YB&Ese15veAB@xn}Kf?8v_H!495SU8Ckwq76t~6nT(*V z7Ay>$ETF8x_E4OGfnyfqGthjwAje!r&_UM_UGu=Y82I}585lU`GlF;EGq8cSRB$X{ z1nqcY`w5C6MzEvVZV59ma0D|KvQAI-Q}TW!b)lOW85lSxGX4RrC}QVeU=VHxIi0N*hW#$5jeG(gNJ z3G(Q3W>B)=;RCIY;Cu^3@Vs}_&$SN`-T~G`hqaXZw#Do z!OBD!*yeFDFmQfg2A%K7!^ruW`8LRvT_C4_0V`o(V55{%Rvd56`Zd*7)8O}Vq*b$i-%D( z5fp&zU^xLs(QhC}aDX+6Fp7em#Ki(~k_00ITZl9R11C3&3TW-A2qPyS%PY8>_>tWt z0Cf}SP8iO5K^AbLXJlZ@1BJ8@3uxhzm<%JQ7>g}vaVDry%_+_Tif3-n&O=TK7Eow% zYl7BANwR?a&3yzEP*Py~xGkg@7&xU_K%vRNb_-;rEDOllZ0kW13M`?ZwMMC23=G1; z91IM?3Lqu}C)h5w2oVMbP9GLf`V+q>!oa}6C3awXU$B~Ey@Cp8xoTq>Z;!vwyAHfIY|2!o{8fa~moBA_~TA*eMY5DTtSqXa=! z>MGD(O9G%pHXH&kK=(lj*olFvE_(?EP@bu0IRLksTdItkfkD6$G%6tAF9b5Xf*(}C zSAkks0`mnJ7+3^02!VDSvUH0xFmNlnf-YtPSE}4r3qX3mDT8zcDuQ(N%7WGuu^bWv zt)guNjc0+Ebh;$L8wlLtx9dT=JVC=c0>PlA1Oh7sL3)*Bz78481ZzfPKgft`URU5N9qN)VG61p9I>$-ZKHU@&wdDZD0nL7)FMA2A-lRJPZty3OuE{ zybKIdRSFCYJY}GkCxetXXkA?uh|MGgsylef4hq(B8RPcMkgBXwJpfq|zF z<$-~bG@`VVvn&lAy zAHgEQ_YM^Lf?%U%z%?e15LhOL4^%hu2!lBZ4D6s3Wg@`9z%ccaL8yeE`UpEL#1R=c)oB5GBC)p z3o$V8{0iY`VBp>b3V$93Moc2l<-P(6Z4q!Va)XXKAc>4ue7Yb5gFpai6^lTw3@C}DN`q4fs6ZB&1}YZ??ka-{SZi>PEeG5) z@&=vkFW>~KECnuu_OA%k$$@%C{h$=cAkGOoWsO&BgCGNg6lf1OuQsUEVPFt%1ND9c zc=b+#WbO$uF!1Vwav}qR_%=}Ikk{xDNCLD_nb#Q917~0me=W(tpulVX8zj-e#lXO8 z0V*~b7{tXvyH|K^Kxgbp-2`18XbZ}O3=HDJ5)2F+ybhphO$yX@7#P@iU4uZ~u2rC=t!`jd4C1k%!h_c{8zhm=&cMLy1u7327{tp!=X&${ zwtyt!6c`wI{Xt9y26oU*rBj5UiA;e({D>6D0YN)K3PCHPiU)21Zv zuvT|Qj_IngYVzKoCJocX5UqG+28N{~uzL=)K_hF6br={xjWHd@D5i-aI*ifG6F=1H zfG%N3(E**O&!7uh-L+1Kfk6*+h{Mk56O+}9Z9#^BiwrpiMUd^PyFoK7kVA7JZps&h zxycB{O(u*S)BmHpsa_PrO-7;&45YaUWC++zk_?I<+f^5VLK1XZ3j;KqJjGycDnfBn z2_wh!n{jC26bWiIfo9(r;Niq0MxvYQL56_cB*vf!vR(Bc=;)QdNO7ku4s+9A6gT~6 z1QkM{$j~TCEdd?#eVmDb0kj)e6THfpkqJ3cjm0qn5Y+0^ASndvL8gFRE6$(@a+fOT z7EZ>qVAq1qz-OGZUXp=9ADlwZGJ+cQput16v!E48XBk1wd&Xc$$~zBtJ;b#a7-6op zV`5;~F9~z4LAEgD&_&RAegxx9#tY&M42Dg@4B*2N4MFXB&>hpD87l_k9$^Ls(7+)B zgEnaE-w_=KhS%cY7-62+Qx8tFb_}|pZS$bystwvKxl@OM!AN5I!9%>F(`^#f zStXFENTz&*sRNx?2~x)=32}=?k{Z7-X!khS4h2StTU?>C@kwg@LRySampVdad!{!e zshQS;&QJtpTAWb}DQ`hx430}-21QV;sTPB#!$AY9u-q_Rih)5*P?mv#aV29UNHPdg zhOA@+jZ(s5ay2|AA?a|sNwS&{N`bOm3KpC2j1naUjusLM6p$fc=Snarf*hs_T2jsk zI_Zgl!5Li06-vW0iabh2QDo$p&X|Ihc^jqSZUU`j0)>}}G(IAPo zCQ$}OknJWL_+clOfm*SQb9!VL7)+B&(-;_4K}^OVaBJW!$bXzHpeYm+F3_Su@Pc8` z4m-v<_hcCu%<2>w7#Q_IOvWH{&_YMh<_KO2dRlwhdWI|mg6dkQql z#qxxmfkE{Vs7_u7nq2^`j$vS&GhL2>!3tbbuVVs@P}DIpFj#}?Uyy`3XmktIXZHaO zKqsb@F)(gsnj^=+aFLOLK^L_25ENm$p!yli0IlEvF&OI2K}8{Gc}%e!1A`5y@x*wD z3DhnEO?&8q&dmm^vjwf(1u3%uwVW7Ff|Yy+84fD3!Ac;NBqs}~KU`ZX(ZV0KB#id0;$sm)k{Jk19Cu(GA|I96EqMr z2b4@e2bXGr3Vkg_Se7&gWg*avZn-=IgC#gcZ2&0+-S}kLEWp6PxDhnI3A)Nj8&ovj z&|zTkl?SJkXhsVLZ9PT?22kOj1{RBEDq+xJjA683&;un=kl#RY13HHoG^E4OtiZrv z8K}U(z_=eYJ`Fm*%W{ee0|Vm$PN-F1_s7Mpn)>xi5u#* zK|2W_>o73f2ip||5@XQLV`N|eIqDNckkNucw+AYuy%);hQvf>{BnP^c3#42dbWa(G zp#_z5WY7g2tp+N0v_Xf)?$lvmX2?>2R1wvgYBKd8Z-U!oTR`<2BPdoGv_VTOCdn`` zOotf5RLsDj4O%GmPKSYE8(d5WwE7ENDe5q2mx0#x>M$^zgh+#21v<+QUB>+HR^(Hhy=Mt8??m}6v&`$2+)Am1D)Up(y7B31=^R!$pT6UkZR`v zsCr^vvd59;(VMlgcX7HDQs?F?wpB9aj##~7>*PFvB8b6LF@7?>so zXoE7uA~^u;+ zKTA!to>>=U0+Ip-P8QJlkE*{xOS1QXoe4U6fpLzz5(9%8s8P?jhY`eP3{v|d&cML9 zhcOjYR|ac?&Q9dlWneH=0vQ>_#PMGTvK;3c1AT`inCZiA&NQN<3?JFqp3NyU{4N!z=gX%MB zT?U3t)Awhq$?(A|2~gSqS6pJ#|7WWS)_Z~m##ypKb6%#P5?>Z~uDkugGU`dD30MZ3uP@ONwz`)oF4j#}A8H{tDDKjwWdy0TXLF{MD3=C?l zph1{c#y6nIR0&oGjl?mwgXe9TCI;w&mXd*!I;emLHHOwHLsI&Q95rD!P}(}HJpEyg znq<8?D3(BhS;U~jRLBBK;0&BBpo)x>1vFWqDh8^pRKOkr6>^MoR8<%l9KlBxsxg6k zqo6TL24j#pj8TjR3=FE@KqV5WsDdo3W1RC?g@Hj0Gzq|{4eq5e2I+&wq!_iCTtOKD zw5nYVG%&@e1KtzO7@`ImnS${`)j(rYFkYB0sD1@|4pan#JhyB5!ehK*)34;J2{YPH zH^^5Lo&GmhjlW(AG*${aUV;I9y9DDLMO9Ej1C=^fFn53oCPpi;wV?BYbwN??4XSEY zGe9191$!J+fHKYjjWeo&y623pP~G6-AzYV%AyO5R0*e?JbV1t~K+e-+1!WazGFg_V zCQ!c?7bciu%#TO&!J}}4~zKnC^)fgDm zz_n2tBd9iF3{nGi<{8r%K_vlWFeHPgLo#@X9;o`u2OBuuG+#~F^&%*Ff%a*`%&P&J z2d=tuVCI3k{fs#<^WK5Rx^t1us|E$Kc)inkP)!6nUYmgdRCqDY*{TVvi9^6Ou`>$; z1EiM{#sunHGX^^^5{4WJ4;pr7jA9a0XJ9bgDa^nCnvpkLC(OW5&ceW83o2tlDvXZ^ zGca_sFfeF?h928>85n-6frFaSm|?ndftt7@$UIP;4GMO~Sf(PFdGlBp7{KO%PF=Qz zsQ{Y?x^!6^G|~q$FJ^jmftmu?7*J~pY)k^vWtcHHV8*-#ISZx&Y|MXsIoFJ*uqqRjj?29U;sD7K*q>Tw=IOa1{C|CAYe>m znhG-pw6z*+OgzXKmalD zq9s@)kpWVeMqT6u& zbHVD(Kv%&-TsaRc@E>FVXvhz20H}oxHb8efv@@&+?oxxsk;JBJl&A^Tg9h-NK>Lju zL5Hz2Fx&_C_k4617~H@O=&RsRWDL?sEJ|l!ybiWRh@FAK8q}-=Dboh|3shQUYJ>72 zbgwjnHs~4~kZ=R4FsO_7M3I4EIz(6yvWJ>M8x&~1N(>C!r=KiQldk`y1RZDq)t1*G zYN1MXL9NSApw%Iu@Bvjmx}fVwK~;(_$mgIkT^Dq;6sUOC1*M=#x(p294h5)qRnY-C zGX`pyHfS^fRDfEe2-oY~Wnf@<0_%H#E~)@^jNM<$GB7ZmU`o+pU|@qRgjbXW9kf;h zn$0=MR09$RjixX#fW;k_f|@H*piTFi!bvJ4DGsh~-9 z7Y?sa91IK~%sG+6>nlG40|;}@kWJ?wHCWZU~cR2RBC{ z+CXfWIOre}kQ7Lp3L^u9{B*(l+QPifpzA#t7(my`GlWf_I9Ee`x`K;4&-PV&)mAW1 z+o2#aU64m#Wcr2|%mR=*01Y-V^K9RDQ0)ot)E#AFjHc5QS;|D1EX}4Tg4ahI7@AB^ zT&^KGT}eh&gvr1Jw2WGW$-rQ`qP?96lco7|#|vtrjON?JFQ^$Zv4VzAnWi@eODJ#O za7nF$k&Nt$@kIWV*pBHPP)7 zchn~E)q@5~LDL%`--Awd7m0%e80a`-5F51Z9CY6dhz**R2MwCS)Pu%KLE@l*Tmsq? z5(im~4I1QxsR50X!qgmqssT+ggUWajA%=SJ#d)9t4yNc1R1v7p4H`X#83YUtT-#BQH0Hy{sYzkAO&j>onCJr=-%fMhZedB92`Fc=_ z0PW8MsRuQ{lA(5i+QlF?H>mT*z`y`%$AHWMHS9rbZcvrTz`)Q4RS(h&VsnE+m4Sf) zl%PTCK^wY2Y?%60Q1zgu-6{r#dIp#VP)Y}B067N4hG{qk)d1?xf!Hwhpd0{F51NGm zv0>^TLDhpc4T0D&^`IrvAoZXD9}pX&zMg^MA5;TqTL*{@(*VjtAPt~u5X6RPU|^7f zhBRm+7>Es14+=?;dQig=#D=N2hN=f`4*{`Z>it0Cym1T+pq2=T!(BPOPq8R!`0%^yBNDqGi9HvIy#|SW2#I|jiG2r&{TjlC z9Am%;TF?yj4lfd05{a#f#5P1?+aa;Nkk~m$>RsP>aELc9mZi`V9-TkgU@q<8f1wi z9)!e>Kw`%su~U%PSxD>xBz8GB=z1!s1${^oQ;^uRkk|{6*lUp3hmqKzRV^?dgU+^u zv9BVjxr1QWGkivH7=9wL|0A(kLG$`hhjJsa1(Dd|NNmvA88C}gki@}fXF$yXooLD! z2?~GE5zt7Ae396}NbD#ib|DhG9En|v#BN4ncOkLC=V(A3u^e=?Cd{R4krZu4V(&s? zpG9KdL}EWhVt+(pgU{4}TE+=l)(>TiLfK&dD?&M-vPBPx?TEzoMPh@`*MJ(7iX>i$ z#I8kRcOtQ;BC!|pf=&yA8nhNkVkZ*&C=&Z368jz!`zsRrHxio()SrNwFNwsKhqLP$ z7*ydL1_o^;whNGk=ScN?0Tr7J3$;M`zR9o5)%6* z68k+8`zsO~JXj1h2Xy2HEN!uahIXOiyh!YN5hRW_659}o4eB(&46;QMcSd4^)>y;T zgd&N9mJY+j^N_@=AZ*C~-S+7p#nr`m7eT~8$&g|FbVUhuamH)YbtTl@ZB0Rg5>V$m zA+ZCH*s)0LY$SHY^t}^n#6u?|39Uq8Z$V-oKw_UkV&6bwKS5%Dn7(#WjW{Fc^t+R4 z#Opl;5jCwp5<3)$9gW0JL}I5Sv2&5w#YpT*Bz8R#yA{F)-BH58&<){$!*C)Jdj=AF z2@-oF5_>Na`xFxU8WQ{Qbj92C;)#Edgg8K>Owh;yZH0kFw<3}_Xo3|cZiOW7hQtm= zV#iP4`K(5{ekzjCLL~NDB=#;O_Aw;(B_#H9B=#pH_Fp762WS``>J4EC8(cav$U!*Z zAk{=-n;^06k=R~H>`)|jA`&|XiM<$!y&j3ZOBktjauiA8A`<%shz-d_40nVX7=)qh z=OA&YZ@wb21wa!cp%*7eQ*ByaH)}y80i84K;`Z zv+rq%}ONp5fB^d=o=t5RLvt08+2DT=-x^Y8)_ymXnFw376Y@P91ReM zb-G(`igGo{!fE>rrgT$T&VuNl`W?*2L4`M?tSPWu=Hm!p8 z>4Ml$L-!!D4}#cGHK#yqsG5r)Hq@Lq;?sA%ZsMx{iX;Y}Y=Z^@=ms3vAz8AZWfxF! zH4q!>E@KcIYMu=eI|#&vs*grury#MjKy1*^1<2>c5DtjR&xU0I{KZPa?4|A+bSQd|`)}J(K_yOHhNpBPjx1T@3R*Cur^tYA8R54OK6J#MT3` zp=!*L*bYc+HxL`D*B{0P6-%ig4peg<61yCU-2h@kgB`T<80LecAaQ6KI|E{ark_9u zc}Oxa2t(PoLE=y~FOk^aC6S6HABwy z_d?Zhf!Lsh#Goq}Ky0Wvrbui%FdG#9pz{$y9H>hpk=RK{>}(JlYG^x%4YjNf#0Cwb zF)%Ppl4f8KhO*~^#Gz_dBe9Qx*ic8`st0kPik^VjpaCWZ28Nd)Hq;<~83qQ}ZBi0Q zY%LHQ>S$vmwha>76~u;`nFwM-?Mer+Y?lvAaSUgtspj3d?!>5Xwc{sNF3_p^B^`<{Y@EArwJ-?4BDv0*iV2#5pKAR!0Q02)Tq0f|F3 z7=qYPHC9M$XC$^S5<3uT4ro1F6i6KExKt1uYG#%ks1Sr2S^|=QvMZpPL1Uz~AaSVX z4iFovxfjHSs$UFZL)EMVu|W$O85kJWg3N)kcYws9Y7T+eAag*O@HmJAmAHb$z6WB1 z6frO`JO;6$YTkm_Q1MS7HdOo%hz%8I1npylii0*OFoM=bfsR-Li9;O(Iu*8FSe1bR zv|LUWBmvc+4q`(M(gCrd;$|Q=RNNZGh8pCD#7;+ISAf{i%D554hMLn2VnfWSXP5xu zKqY2@*boVZ`5-n_^AZpns%9OC4OO!l#D+RzyF3E}$TOhh*!O_Mq3TbA*ibbOkl3HW zY*6?!FfjZ9b0DddAG8_@szCyYt&PMsL1KG>*wC^l7>ON+gVp;3?xVnfYusYl|> zKw@u4VxK}{Uq)izL1Mp0V*fy5GlJIhKrItRVjFpF$N+kAr5F4ub91{C8hz+&u7l;j-rvmvB~O;!rcokk~CCHq^{sm3jsSm}QGW z5>Vf-L1J%3V($jAp_-q7*iZ{zgV>-MI0goW_aH|@*}p*IP&FK?h{OvjsKB`iRQ^bS zB%m6UKy0W6O%NM2lLVSkP-S2chO#X{;!rhiAU0Gy3W=SJ#4ZJ~p&qM4Vz;Y;8o^MB zK9B^|(5WCcXxfm0fng@dVkmnFNF1tW6Nn8JKMZ0+#ZQ6Qpf!pN3=HQ$dZFx_AaSUg z=LmK^!&d}{fmw}#ff1@f0mO!CPzSL=buj}2c(ar+lx+qQhpKTwVh16y6F_XJ`dSbh zs=fupb^?Vz0|P^c8UuqcXtgW@1H(L!1T;Y{2C<heY%z5P21cm3lsd$5pdvvFBo5VVjKsD8v7zd1kkq?^ z#G&fFKy0X*SSTCp|8gh?RR2{&HG@`qb%VsAnx`PKXM)&JgXSWsUj`C~s$UIaL)Gj< zV&6bw-%)3%2M0T7hW8Cf0;>5d68jg34K?T=)H0BIb`3;hk_W_ws*y)xTOzS-H6Wn~ znrrt3iG%F|-H{CEFfc@e*ieJwku+q0#K9UE7;-^usG0^O_ADg!Jg8pK>aBGkaj4$y zNbEfzc0JUf14tT9f+V0C&VkraH4l;4zmeGgp?X1U5&1O{p(26AmIbk)<|t}HLIR|| zUJE1vwM-wxhAMJGV#gq{6QG(wYtC{&;!wS%NbD*Q8){A+lKOU#I8=QPi0uR||K~$E zp!CPE4aA0KxxFAZXgvaGEDK~1lzkl}4mIcwhz(W$3W@y##D=Q>1Jw&!2PvS12q6V6 zQ27rvNEIXj)u4yOHb-JRAhA7>*g;6_7$kOr76XH@3uHw?2}m4jR||{{%72|84%FgF zNbEUC>;+JRK#L@|fW)B&9YJEB1hJv!TtZ^sL1I5eVt>~{D*qX@85rQhK1gga5E~l2 zvLH6-968WhL2U*GVJO=bBo1|u7l;j29}Hqc)qw75hV|sL5aRU=)gTV29A#i&XaupL z8YY3*&=HpzAU0HdC5R0jOWFitL&r3CfY?wq2a(v9Ky2s`>4GMn-28LH) z4mkZWd`4pbL1MG&fObVg)bJs(t#CDi&2$J?e5(+?KM@&xyNv9wQWgxK&rcVS(*B}WsAhA29 zA2d}L=belsG<|!ZnL4*n{Sh_>2G~XG%%FW3(A4e(VnYYI8bNI6IMiYg8#>gJ3t9>U z9b~u!Vnh3KD%=bVjL@!DB!~^|3C#hqp`8}+!VLpx5eqtshY{Ltw*)OMfVRm4Kx}A> z7QEI0+7R6Y5{EV{!AlgNZ9VW+AJ8TmJ7|&~+O(1bv7u%D84w#<5Y_W-kMdM6V*)P} zbO7D3C%DgGzuF^??pw1Bru{m+gUygH|$v4i*RPI0WSg z&{+*2HYh9K2B{GPo#Vv7@DR!d4OD^lj)2sF_8h#0ii0)|fDRi6iK~HP;WtzQ6m5K< zbJ3vbKm^JLSs(>vgBFc}4j>Yege-|vgNlQ;SLs06Aj{04Y|z4aD<~VZtJ4?6hNi7x z5F2#t3djP`0p>z75Ff;YBxE2Kq(a#sL$jf5kPk|sY>=UqP&UW|-5@qJ!A^v-L3@v< zL)oA+)n`N5p#6mPYe5`nss>$0Dg;{74ca3Q6$d$PKa>qRClYj|J4g+vs0ZDq24aJ@ z^hN=N&7SQSLLZE>L(Eg_PPzliP1J>Yq2&5=;{$g=&1ux3DB-$b11tVbUF@{4cb}k3}u5h7kfh4pyjguP&R0TaVV4x z+5r&_WrK1`B9slgxm$OK@kZW1%3uS{+GB1=3Dm6h<*dWcI!V$FO62t~=eo=v{0i_Q;C>wNYfGLy>nr5(uvO!Z- zj!-tJrgjIj>lqk8J8*o#90u^6exMUjK^A}#Q6y9xbj*1Qlnpv9Hyg?ZZJjQJvhx@i z7|Nk+(Bj})D7%({fuR}71}(Yngt9@ai2Fe&OoA+%47zLxDgjDd3!rS!Cf(&w_Il9B zHI%&tG}#Je?+0a9DElA-1H*nO8&o78g|b0Alukq0ptEN#LfQ2<85kI@Lph+b`Yx0W z+V1-p%Ki$P{(-VV7YM$GvO%keze3rd-Iu?iY|y|pXw@mmV?v-C$Uz4JsxmN0fR5UM zvXwx~^0^r5!J9uo)H}eU~q6!)_=W zbOjA)0WQeLUl(MVk}2LFK;=0|ThJ4qBKC(g3O$mV*?5N*)FV2GCKS zLVBRX@)#I)Ld8MFFlb>eNE}o(ABT#AJbDYn1`P^9@2(Rvfav`Q5(kyL3=9mvp=@SQ z`43uvD`W&&!OqXazyM-{W_3lOY|sJ^X($`C4owlt25m-Dhq5a{gON}+XeWaqlnpZ9 z1;hpwoeT^N9#A$Yw4!-HZi7UP20ph^XF zTP%nTDth}s>OmC;0|Nu-3`Zdg&?%4%46~r(pt@iIlnn~4Wl**ZsQh0A<$x-Ny&yKU zb$b}f2DucpFjvS5blxTd!$qh#s8)OeVnbWNFQ9CY`rjZn$Yl%+4F92Qkhl=&P;5}G z#=yWJ24>eoe5?uLK%2>+6A^`+AmV0FaZrl2fwDoh8R&{xkQz{}?Ew`Bg^C}P4T}B{ zC>!LTC@33r?M4EW4XQ=c>Y*G^jg$jrgDRvVC>vA>RY2LGxUYka7(mC12)RH)@i9~!G|ux9$_Ax__q?F;-vzRn2eix>qydzz zLCcImY)~+Qj-dpxLG3|yJ_ZI58x(ZBP&TMu7lyJyd0Gz22DSS%pzL%81_pg78+4_B zDU@9ZYX4h9IiR3(gt9?F=L2Pf#&$qg=z=Wn2VHsy6$b@lGL#MKA%T`CgVZcyU|;~< znG0frwojEq)of&7VCVv|p#u&RKG>8M*wFA0$ z7{mr8u6s}opjOQjC>vDZyn?dJLGyu7HYjm@gR*--)3#7HC~YzEGcbV61RWp20cC@> z%JMfwA$H&##ol%ej&s4(3zQ{A62WBSBQb$`wcYZw?nEyC&3ZQF$8r!ROXz%rdDOI?NO z$C~LzS?Yd_2Gbj})cqMNreDlb_h&k=Zn{#ox*sFQ^ula)e@2n%2eZ}vnI5d4E|jD0 z$0##BF-P5>(PR2X5H(>sW3IYC=ZcMxYtN=npO{o2KYha?8J6iax#}uRPc}|pl&kK? z`C%i>35Ll9^3x^q)HN6_raR`T`!l*sp9rEFrauHxJ<|>I)%|%-Y+_&l4U&PVCWrkQC`ppO~jCJl&x{-GJ%Mrs+im>VAw7(+?J? z`!h037c5kN&!{k+u}IyYamMsO5G62uA&Baj{;^11n=x$q#+wEr(`$Wm_!$|dI~J>} zGuli~JYXe0y`flLfcL^q1_n@K0=dR@df-_vX~u}@hQ9>Fr(Y;m7hqJG{;*hGopk{R z1A{Z6&usDqdsP^K=xm@_@GOkJI|hZl51pP(h9@bm>`>H@4BM;I6?rf)4%S7yBc zy2=!y;{!-X!*s@Sb#>M!ybKJpAi@si>H?t91_?LtF);8=e|W)5nXzE{LXZfk5D0)M zd;n6|G5sS*_yHdSgBnEGpaLAUjuqInyVCgiSza%tBOO zs8AQ+y>Se3?Ib9~)29bs@{(qC0p%Eo5`{{20j3YfrW;kNtFcBP#0x6b1sFM|H&&{v zGv)A4=d)xKn|=T!rZD|trMfz+g#ZJC0>lV`Ds|9>X^K_q>Z}n0pgRS@fs;_BF2Ho; z#Pp&nbv0HEK?a8V(+gR=MFcn?JNlp%FT;}Q2SFM^E89)L=1r?s7htrQE?BLu&T1pX zz#uZ6@unA88)!c-Xsa-2z$ajOB1l1o5CelWSljdkAbl;5A_}MFc>5;-LG0LB>6q9tcvv06MZ0V%&rpbpb|&=?iPrK^ICbtWg)A z{s1EMu|{2;>B`yZQnl)8tUE**80JrRtyNcMHMzpTP%=HYR$ZAfeEP&%b#+!(cLs(h zkUOO=)T#?Gtzeq|2&75VpMl{6eSU(B?A~31g1ai;1Zr*01|Hz zoZbWy*9>G}u%6ENH%)l@fjV^o)*KN=hMehF>(rH5QxX^$w5R{AQ&(o}pRQQ1uFiU@ z6@G72LcO{GBh&Q4dUbWC8*0;M)vK$q-fClDSTWr(UR-$kgiA6k)9=))^DxRxe_5}t z&e$|vut8m&X~W#MWd$Teh$5RR3Vf zXa?FAEy`#z{XKJ;=yY?lXx`~_mTT}Zn;98xe|lK`DGQU4(e!=FWl|z0pzERBLj9aW zJpKLR<5euo%q+J5I-$PN3dQ&n%o-aPGa7=76=AY4o~~HyF3xOWX$}@(wlFZ=esHN@8<-eOcjPe>VKkbq$W$iG zVrgJ#uyvKzMm8oR{`|f;Py?-m1MTCFq_`EI#8Wy$NlYLE40J{>UX9Mo3_K1z3=DzFkcxVTnuY`eRh86<@6Zj$_CPubJ;tUKd6F|4^fG-kaV&v%M z0_k8~rOm*=(h9oWMGVw{V3`9tn;v`{H_I|b1_uTvDbQ#R69;RI1_J{V2m2w=RXQxJ zZJ^tASlDww2aU2Yv9Pa|0o}I4(FD4OP*jY8fmsC9zGdl{uKiO>fj1X)gOM(1^n>NO z)bxm-TJqv8ptI=JKnGm0fSO}08ka%$3VBZN`>ACpbrW<<{|Qjl&BAT~I#&NAh|R`+ zT5&qBuCo*mXq76<*&`l={{PRG^S?7Q`jQm!b3=Ax};Ok6S z_}f93Fy(uz#eQq4Gd`Yf_ghPx(PetrZ>_i}VbBfJlH20|S%DZeCCr zw1WI05+wm@z_EaidSX?x1|1;G(gwN(#ZHldflb|jnSnv{A~OSn0-G))3j+f?uLuJJ zn;wYC!2V!5-ybdU`ma(93~Yv?j0_As?4af4Y(^lq0K0?$0|T2e=#C8$cF@7+Y$hPK z1Usl9%w`I@U_*xett0~jn;FQDatypI9boHgLAPYKgRUbo2MMt8u-SlaSY~(CW?*2m z1+`Qe*y})78rgx^EK=+bKn}168OXuFq6Rus#6bdd0(If^eSfsX>ia+)9uZIiViW;g z-@qio3A!mrBp4KoA`YMvK}Fm_-V#Xxjr)kyGBPl5h|Ex9VBi!19mL5cQo_u@z%60{ zI;CD@9}@!uuLy@S0|TE3=y(Ty5gpJyNg~TM85jgb{);m(2#N4BGcX8?oCMv%!N9@; z>iBbbg3jq;5t|~nm@+M8Wnd6@oc`;t zmX$^uF9QRIEfdHBM*bQ}1_lm0Fo%iX7i6G46KKAInV)TX%s(wP+igk=3>*Pq1$+t| zVN9UO2>!#`3=ACMOrStz;LlcPVBm;gnh46F{HLTD7&s!C_(7+J^Pio*|DTqmQ?eoh z14j(l2wwh$atsU{vEcK#`1q&EGB9w&fz1@)FIHh-;D`s?F2U~za!MkT3Nr(PB>&0j zQvbEo>RZJa7&ubF=EyQ|f|AQe(6Q>XL5J)xaD&=P9O+D;bB*{iIC7an*%=u4Z>TXa zaO5$8)G_dH09`&+0JcDZ{}$-z@Di{Wl=wj-ZXBgdA6Xa}RQRnyE-V9Elghu7i-Cco z9L%XtW8el2TyRt|{RLgW!^Ba?)C#i15oA<76X;qa27b`}2^)jw?(TK+Oz(&@satSHb?2 z;0L?(8rWPZ25u%D1_qAnOdmj+IXUh!WrH+>mE41R2JDXeVD*gr_28&`0FF8){*R!1 z@DS_{W(MwwAb&n$(gj^v!^!cSX)D~Q7sy7vgc_9sa^WjvlU~D2+6_9w{|!?)#H5c* z|KTRpe?m6uGt?+4Rt5%+FJKPTQD0$3eFj|<^^NHu2Lpoy3#cmKU}QE2T{QC$6y_q} z6VpTj)fpI=ME-&r^0uA|XpJ^(U`nZtzH8gw5F*zKlJlVm_y$_(sPM*i0zjs=**#K64}q}h_0i;IDQ zkB7sCxfL`T4Dq=wR5#e?c2IZhQe|M^um|hrfFxiCFo%}~O2P*LR$cDHz?JIDeLX3#)119u%L!Fe)+ zMxVJs2Yhq*F~8?xU=aKT8rTI947@BLYq(#5j22|&;bvfv1jVQc_jJChR3*WOpu{1~ z>Hrgun;viOEGZ-}$iTp%%nCXK0j#_itX!I(fqN#XnA2gM$<4qZxNf>4i?)d1RZ!Vz z#<~k;#*OK2EZTDQuB;%7xIvegaRfowU7(=Nfv_ill2j>}&Bw)2!3sJwfd7Fw0|Q4T zE2t1<;0K-B$5F-lgqwkZjeifQII3p-!_C0J&d&=f*K1fmfU-URThQeLwXC4xnv;S1 zEGR_kSUGs=85sCDIT~5#f-b88o7;qJZZopEEy(7!Ld<30{=~z;z|qDU&%?mL7s1iV zssXxt1#D6m)Ff~*-^~gt=Gpka$}li+^ss_TPfq?)&;$fWFDs~c_TdL@$mQq*J28OY z59G&wuqA=~pd&6hCV)9X{Eyff7&s<^9Tv=g5fna?z?={U?tP%lIGGi6&kLUy$23;Z z0RoWFnvU$283?!3GjPm=IEI1yDkwTR;>v51X6gjrCs(>zT0hhGfSi#kXKr#czc2>}_#*6|*3>-VaOhE?jr=X%?C+l~R zMlX&%tcf6v;F#Ep?EZbo?yuhu@c;w&1d#6!uo{5+=-wPhSXaY!A4S%E3|aSah-OGt zaRTf*F9vQ$Q2IT|nhP?Co#PDaZMaEip(b4e9eZ^S6w~z#Yz*ABplo-ZbvqvegIEN| zMb=Evoim_oIyo+Z6TJ9MP~yD|PNd>DwLldXIGKs>1J&49!4V~11j?h=z)>zf6_m)X zgM(W9A1H8dfJ0IIB`8PS1P6>bBdEBzRS)*3IM_kA!7gRsZUgDK!}=U_+2ll!sSjBj z`JpAkRM3FI4bb!jh{eFm0&*)i=;RZQC#=i)85jijfK-4AZXr;{1``b2S)k(R4eJSz zf=6%#FPIpn$8c!#)}IDRe`b9LlKu&j2FEiuXaPD08ymi@x$K@x?V&ZEW^zI1yp?Mu+_7I`X2mI zpo&(P4a8w(;AR2kB|SD-0R{#>77in}{UA$}L2WQ&uxssorK&A`17)CP29I}I{dg2RO^Sdf8%KL(V0T-iV+ z3IjigKefP+B% z0Vq$Uf<3{&t-->;z>&sg0J_bTgCm1&nGgd5e;vrkOmI43;Lia?ZWdUAg@Km^WG8n4 z$c@=-O+pL|VjLW~Z2v$G0q5sDa9V}r+k9}~fbwBI14juseTj2}it|#o02T%YsqEBB z299#JHK55xZeCC=Q^B@Fh=GAS2Xwnv&NRWooWfNG*%wnAYB2JY{md^L$}73lWaT_6X6TqXo!G4Qg0OyN`D zn8{`&!oa`}nk(X%1!gnw_sB6Y)N{;cvjFwc`8hy^(i}EBP|o7_0+mB^*<3(3gYh$f zVqzYfmk0xc06(aK!ZDvMK!kxognvKCb&J?Q?KcVj4IpPMVT%y~%^>r#Fn})UVKD)d zpd*}kS=NEspfZS;rIeq6ftQ5~bQAqW3bC~!AK&#L=u7PF zxW^_c%D^C~FUr6m1djPU5e5b!P_Y3iby@y^uAMXnMFdL<9|HrY2blR0bT4Npn0Xj< z5o_AZ>GycGITS#PA^HDFg0D#h$ujWIQ($1=tbz`e-vjU;x`X17@on1B)>S0|QsCKj=!{8(j4t#2Faa6*w6fxEdgazUOCP z;A#Z1nb;Yod-H2s*WXiTVBl&82?=l{rWG)7b-04Unxh!R?hF7OQ^B4t#K6GS4JwXA z*f~JzdqBPwWe2S>=jsKq#n=zBF)(oTNiZ`oh_kOyVqoCv2gR8jyBdf+0aRtkvxBY( z2V$1N(hB1_rJvAm=)=-v!+%HXUSWJ^NP;1_rJfAa(=$WzbcY zGeMqhVLuJJk$IMtCmt6Bf z>vyg}!i)iQ`yME!>TMZVtU=yeuoyJ7_5yST^%5}&1_nXUnF~UoAtNxsz#^2Gv z3|wnLPUL0(3R)b>wGI^ceC)SDn%9HO5nu;xSK!*POM-zxgrk6gYa_@R670{V85p=W zfqW{%z{>(UH-eW1= zWf=wru3aED3%i3l1A{i#ZV-o!fhAIufq`r9Y0ypT@0b}FxXyrron;*;KrVxsPSe*4 zYDr;$2k3(kTzd^pfm%60Hch876Sv95!gZzMj22a zip!XhUy^}Alu@Pvl(Gi_e()Ci33=B1lGI}6ayEBGMGceRL%4ldaFmQP>8b~rQ++dW+&}3lX z@@52`N^y%36a}DL?N~fOcf+yhgNja2@TW^NFz|qK11AG_GRS%##)py&3@kfA>y35m zKsWNP2AvNIQ|7=R>%z$G$F^67fr0(;ba@eNaVgLUAa@`rEwQi%XfQBv2Z3Unjs1(_ z^Z*fUu}shwQtmL2JO`s3=p1zJa1e)!QSOHt0|R#ih{MAuXROV@z#R!Pn2%8|pNWBi zI|`Ke)EMQS@-i@RM}s)(jB=oXVD4B@XlgLZ1%bv}<3KW+jB<+8&x>eFN`o$v7>^DIAxKmJv=q920!Si;Jy@23fqNoIqK173=n~z@An^wFNgxeV zK;jG7_kq~cK;lc-ML`al4iZ1Y{+ES;fqNE6`~*Hw&m$%6%AgOa&Vc z_mwVCWLSaxdll5|XJ7~Qe7SFeQW^^b%Pf%Xw=(4z7}!d<@7$WMAg(Rrt-{a1!2K9B z_R9gDKHz==vbO+SRd7ECu?rbk+CV}3aw;fJ8$nU}5tMLbMfkZtgLcES9|Wc6FW%GJ z#kFO5--8VN14^!H?2gkniffD48>lldaQ_Dh>F_6mVupbc#L?rQ4B{|?IR^Y|LGES( zbBy>6*%%nOnHitTF)*0$Zvy22Rz{FFO!+};aJjj_WrH=pH>fSl11`pF_(98hxOu?^ zoC80o>C4RrmZ^8)zpcr@z|9Yq^5B;TMZ5r5%7@<+6mx>$0xp0bR9A9~fD6J9{xzZu z4BVoOARm_SgKAxFF|gw*_(9b!w>X$n#XkY$c?rh73JeT2GG9UIOOlb3je+40pNuD{ zn3iJXXk`ZtMahUxKPRCrUB4ORX*sY5`1oZO%QG-=L&|G@ei=>>PZ3<03h>K-s%UO4 zFi((Q<_stgXoGn|{4$A33=G^lU{i$o8F*PhQO|ixj)CDU=)zM_VI|MN%?P;{;X zD;DIJ69A=bFh?EIP)JvVmJgx~+_ykCiEm^C4Z-kbaBpQaRswfAvKhFyF@n-O1OEh& z1>3|c1Aa%4qjrNi^$y^EG520ZP`@|;+%M+d2M+oOaF>#M zKbR8*?vHXG00&PDxTnf}5X_0?-wcYOLtsuEe<>&}9R_pa!5wApqhJpw@V^7udJN1- zVc-TGIm3ONk-u1xfq}1q`y}IOB?bom(&-nZv?Wb*LD6)E5!8}l2X{cZ&w^7Y2R{?2 zO1KC%o{v8l6l0gb9DaVI>2lKAlJ%gDBllfK&;Wxte+DQ#?tueJf`R)44+8`D14esL z%k@1oW0|WmNP6h_Q`bGX&OoEiMS)8l2d)#^dbSZ*z_*gS#aToVRv zGqCpg;K5FAb0$!+xqu%uCdzHW1S&Qc^6vqaAC_P}i}))+ac%|XEaqncxy&By%q9F^ zK{coY*tBKfSu<`&@T}Q#enF6%oj`h~v&d=-)Qf_A=fwm%Jz|wWQcfxZw=WYY6|9jt z2nu>XCQwUKhfxM}H9B_~*hCXXnHErZM}c{!pu!uJLwH$kg1S+lGWi|o(ri%nWMbe3 z-I2>3!}M5*fq^fSJDn*=m4N{~ILw{NR4fgeqUQ%4KggX8aub6i|2a@8mIF50iN6e# zc5<0OtGS)|9jEV?)mHQe9csY60+i7!!K(O-xMwik0hziOR4~m1vl;krffB(iCQzqT zj(;l1oY~;O(cm`)mF{!F94-D+)Ai-FB|X5U&_bp-RR#tF{#Bstvk2@SLk3Qe32#8h z)IdGN4XP6tGl53>_&B(iG0CVgFz`2l=JJ*^$xNRhr!7*?2@0P7p!~Cv=?7>-0C=K_ zdo@#<8UurfF=%s=2>7@|5nFN4MAI@k1_ovkCQx%r1hfv6RisIk0W@HG2b9ycfW66` z1B%llV79c13ioHGgPIHs0?BFV4BTJ9p~}F&2o#w=nfO35VKNs$jgenW9n%fvwUz37 zK7phBg9nQYXbT@V3-fhN1_mD%nJ`ch$IAR%lY!w0i%g~t z0|Pf3GpI8B!y*#{O4RIN-d`4(%OF#DnBzcenptH)n@G5Ym_ZH63O1P_Pz@jgo`DMC zkU3Nj8fg$^-p|Ou5XK<`8u{ZE153tn$bd%sxW&PSCUD4r&aC2=U}h9!U`XPS(F3J% z8L-MC4w;)E>t(^b5)K(LQ2C+E45|z&IOG!xG8wq_nL)=(_K3^qf>N&$^LI@KhBe|c zS)k+QxJ{UOwHO$-h|Bx|r43VNQ1fSpxXfCR)6AGb3HOG$Og2cPIhc1xTxJF+HCljq z55#4DgQDIN?9eCTGN2Zu3+A4aT##RcVh;n{5Rq*&8ysFL5;A}5L7CqNtWixu z2DAr@+m~4wbm5JJj65jq_%SPkcv3Q;gP^$mnL!2e3uT$7p!6KTY^=q=@J3k%bma_p z5ZJ;G$}(Lb#{@HjO3`o1GRmN^3w##h@YsIx&Dd8Z5`7BC`qPrx-AgS49RiiNhTW zRwe^SaY(TKW8UusEJka647eMRu89>XL8RtCGVqj1N&Db(t07n&Lkm7OBM)?cipkfSG0*%An zN@8G81{If2lNcCIPghXZHZ%N?1nOl*F%>bWFh+x~kyGFYomW&3HvAQ65Ngg`9R>!q z>!7nH>zU_HZ&%jV2sYy=L#%8cp`3wvUnx$F{44{46kn40bzQ{5# zFwSD$0oorOtOQ!5`#Xt&K?$@_8|);|h6|9B7Ega@t|vBKT18t}i9MNtVY@ceZEOrm zpcVaK#h@+-Nbx_2;xrX)Wme&2&^o_96>SYonPdhAR~@K6u%Aj97?eP_M1XaJE(`+c z?$Mdp2wIs2+BCyBXQeI! zgKknvA_HR_Xutz>=aybO=-8_`Q2&xKSigXQF#)9I0cb&fMFj(6BB(C_+DE1g3OJKw z28L2ysFT@1aR-XQ7)CP&CD6_ZkY`mvJ0+ebF-&h((-xVopr$RrC^6koOK!q`e(St#C257eqH2Oe0JaoVZBu)dB zs-OS|UBJRP$H0Jr!2q0Wr-6#_U5pG22Kzw~GYu5}5ljpWdR2T342;u33K>I;KzEAG z0vW-mB+kIV0Ctfk0|x^G*aP|y4~S}L3xiYNp6R+8+EQTVo#{Rr+R|*GH2Ft=daed6 zK-Yr2Gkv0lwvPBG(5clvpv58#piKjeb8Z`eZb_bgMMGN+eC-s|!~iAG^)FysVL5h_ z!E{AsZL#Uvn%Y8+p!h#+01gMHVg^t^m@$}wb|x^DFsOhost;gbFfIb+o%oj~uZ2Km1_)&31}(GXvm=S z2BrnHc^{-@iShJ{QQBhDWp%WL9g zGcbIDDk@@NP^x5PU;sJCvVoC-fy)GJA)^6<@+?LMhQ4G523fFBG)M?^OY6*J1_pDm z5Y$+RXfG)wt1y?o<3=tw7>w_Mj^tSnTHVEv&ICGFW=@$I=;lpOo?j1c>|SJL zU{C`M5Hqd^w<14*_@L?v$`@v1V6ZA+VB83f88c9^wF#^cbitoGIFdGlBPo`Rfx$Yp ztb~Da3sWm-)$POpB~TL(oF2_UF~OR|z#wZ13Fk&#ZFNadIbmoD_BQB>P31eFv%QiT z7<{K6)YTS`HZx#gNCZoRt1)HJ#ps|QECq{2fqbuA$jHC|Qr8I<1FN$H-S<8d%#UK4 z7{H*kgAtn9Ux6BBNem3vp^os-)0R>OnfMy2x|o4M3DmO!yIGY9QZgu+L7Y5GPg_`a zX)*(YsTs)0(TvUvN}!FPAjPVn-JamGRc!hLJ#C{{ZVLtmHD%Bd+)T`%1V5dPfk6?R zW|^45r*Q{^GA#?ZG=0U!z@RRy2|DWrtd@hFfk6qhGjszese-P>1zDjC+7AXwcRc10 z_q6E4@-(Ra0m(Q+Wp=}5z$H`?149*5<`Z1zEht8k7#KD}Wi$<7rhzV#0-5##DwANK zEnE-E5};d-k@LEe6C(q|9?<mVOs4WSRxdQd89aLrmT!sUhBC4S>Z{acqP?;T287(7iNv9K# zdhn_>R+CjkJv*u7Z`P z$yN~e-Zs(}X1p@}y^*$<;!!IG21U?pDC05~P<_rA1TWP<$N9k8A~wd_su2;^u%xz? z1(eiEIT#oe-9Rm~tt^P7ww(o3vVu-bPzLQt1;wX|H8_wV4Mk892RaD@6uhe7Xn-_# z&KqkBFvd)OV5}{|#$p4qY5Ff?Z6#BXX;(QI7?eRh?0{0GQ1WpL&P)%w=c z15LCwG9Exe5nS1WGBJZWFR0FV&jPBOLDf5`nZP(_8rU{a7J3i%7bhnJgCe*=^_~UN zqOvYvVEhR77h@DWe3U`04Ny9$pZ?H9TT>I{Hh8LqSQh{~X`YJ}6tE!cj6tR0oU7A~ zO|>=C!S_y|1y`^#;HvAl9Rq_J$V|qwjG&(SMow5ccb*ZnN|I?}fVvFGzzg7^p-Y?$ z4C+y!+3`!@A<7S&3=9aj!7Bd5>4s+7V$*M$Y70XWbOAJp&VWb=n876GKqbzDBs3u@ z=Ll4c%?^@s>daty7j!@Y$nUmLnXPacP>T>GQ(`w=(NJ4#`dc$?A&6<9D~LfdtD$<7 z&0(f3f#!inP?;!mZDGb~)AP)=Rg>>HGBB8cTf3>?`8_6X1_m{7?4&Y+Vn>;qfdLdh z>5QP1!WgVk0IG^I7(pv7nI<|wYK|;MQ1$M@jT}VaR%#Lh!(@Ai=eRAjh2=q!xYiyi zxq>268FXU-sPI2F-PS@|+~_7$!9)iJWzeq7t2PV_Zy;iz)D0S`0jI~4(BRW@fY>nG z0$L5&IlydSPy!tX0apDNs=Cx+`o}0evFYzDU;(EK4W2bnb5ty00S8+D4+_%9P?=~; zSai;S>XDkRXr(PSeG**aAXFj{B5@Kf0Xob8WL5`QVwx4qBv9%EiSGxAYX*W^(V%1w zYB@%OvlcTKsQF<&57e)ght5GunDjGT zpdg8Zbo&?>%pZVKwlUl^(5_p?IcJi zNI4Z2)mxn)5ut0XEzHO^-O*ZGSuEU{fk6%2q45FRc7mIMLGkePDr;>8NU{YTa{%(c zn=?f7K5K2^dQgi36bhg|gRwiPO`ZhW2f?tLk%576&Ky@zn;djyNfOxCpoOw(pwVB( zB(S?dmwTy!7AG@815Ol~8V>&CyTyTPRXUt#) zrRXI*ureZ(71|a8t({{4CF8%&pb(8>0=E)D>CzC^umo*e2KmUuWqM$mp4jxYHrhh< zW(Eulel8F#;6^q$<%3Q<0Ch*w!7|Zc!$3VnWzY^}P=!zpmWX01Wn)kV?O+ErC;Px+ zpjNu_Ee1%lX$4pasX1v0YTfRDicSn*5K$6?wVv#tDfF)kB)~oNv<0Tym+5h9Fetk* zGBAJ|QlO1kpztqaU{C^`K?2S}pk^+}Umnu~ZMDUwAFzeCqoQ3w-U7Fyra~=I1)U`V zZAY=$Y0JrgCMnH98#Ne@fTIjlUPpt=>wm7(9qhD4AzfQ=T?(nNO6{}-bgqET>%RwD zVhYm00P5E>&e3#ZU@$38&SPM_2R7>usQqE?JAI>_wuo{&T=FMa610#RTaK9i&rVyw z05o3BXb4`Y1hU`~*hPNs3=C=spm7{SHc&PQ^`OpzD(FlPP+t+HrEksxO6+ND;H9IW zefnS*{fE0K4eTOy(9T-WbU7o0@4?5wpa`0OXG~`UHx)t@--9$ld7+@>p2-HvwxFxV zl+|G^htuvj9E{v@D09#jkd^@L7Hb7t4hkqpdC}wn3aIG|9kfOCK!!60!-K-lg9wv< zI%uoLhj@Yv0fqJqu<@Xc{c7M5vKipjXK(o+p+5`kehGf0rpjYe?R67w{d%zVj{FeoHiE570$B$Ot)-qs_$k0i8@%P(Nn6At#tY`P zgJ84!_#t)aVX)aqp{3zP*ko%9UXUV05v~OqySoNYDWIbw80XvoSviA+fr0TF8)$G8 zH2JBvd^(@AwwNerc7QPiYi96w))rvYpPt~XEfT!N8{8sbVEh7hw2}Y=gPH~C9_}w} zAgLGu1_nj24PV$mU4F(8Q0n>y_ELuc@<0RV5Didyk>U-BggegA4oIyx$R~(=q70h% zev{0=FcmBj&1eZ4H8EyT2AwYTJ(+=F6-b<^kO9(FAHeDlW`mF4RGh(=WPd z3tOpy+|b3qzyJy=2J;J`2FD6^Sh)sjyD`qG@rSu<1=wANLZHUybUAlzF)L7z?Gu6o z*($KRK)0-!6{VIiFs^0?buny&k=vWFK_YH{NcgRe)8ngGj$>c|*Vd~3NUjA}y`Yvl zDEw@}GVt(Ip1{Ds0IHJ1AmZR&6{t#9n#RDuV3fkZpbScYb}0-DMGzH?1`JA|flRPJ zjqO1>?6&kbwcz-eH{cBnaY6Pp~sAc5@1F?afUFLY;>2SJ?m-V4K7pwI?6YadjJzBhCj`TBG}Z*8NPQ^5=jkXC0E z*d3rt*3`f~rz#FmYq?#Ffk6Y@@~r`f5M!`9czmvw1C$9?h%qpL+nS7x9H6G=aWMu4 zWj+Q522hhebNU@`Z3#$nfHfT!1VdaZ;iD}a2Wq2j35KMCA_fLk(9tBIAuUjw4bpRP zW?(Q+0LAY@4p12gs+{OVa#TbLsPJzaEw}Jg2FV4WA2--l(xE*XMV~F}$(BR5W4p4TT zDUM{3GT5Rd28Q+11%0(OJwPoYOVB0V$3wur0*#e|PVfP>cW;4(z{97YvvNSgr{BOr zQA|ak`4yI81_Mn7RZvgQYO;G85q`s#X#mWD62xpzb{O;573rj z3r%5Qco{xDF+f{57Q|Lzi~{wB!TK4@uY=k?UYww01xneV6=F`g*Nz`$6_0tx}psb`FH z?4w}Q!KL8gG(IU<2$X}j#)8^4qOd50CB5%pgTO`Tn?V^gL<5?Pww%5` z7#7N~DTRh;NGQJu)>bwJO*~J5n7~x5z@YkVtwxmf6!e zL$zh=n^G7U)7#Ng)fR<^eFfbg3ij^=Rvd&|e7(cvE$;9EnpadE-oCPXVY#A9C zmV$~jS4IW~&`dvPEW~2aOneNq?+%`e0XfqlmVsfqv$lZn^c|tv!mOaF<)rBsK#l^H z)=Cac3=A7UhIuhTf~6B;7&vH@K-0FM$!rEr&~gb-yn*NH`5Ck($1*TDgNA_^AAtwm zL9?xlbBf|2Iq4C2&>eIiAEY($1U%>tx-t(^dp>1;$zZ_1uuO)5K^@%ucm|%AxC`Qg zXS$z*XSzSgFfcfP4yyxYGp*@!!eDaZ` z5=fv~B~Ysy+-L#ie~{|;anmxoTI3fGnp2ZxI!EF5*911OT>%H~hB+pl)&~I7GWah4!3zNuZA7boD50c_VOB zHXIz3-{lw>Agd@Mz(K|(&%mH04J$@L!+szqD??gMeNoy9N}%CObLjFNP^tml6%2N9 z5_Ax{1fuv^l(u9&$icmE#gKHN3L5u@Ikp&d0j`w}0|Uzmrj1Dq3~c|wKx-}|1B1&P zDFz0XlT0T;;-DgzfdMS;stVdNk;4pHr{v}#!N35*tUhjS@(c_h%$neKQh|Ztqyj@d z1J8B$1L6z}Ak6)b+1*)`fdPcM|1x{rW@lgkVRtun1_lu3R%LMqol*wEyq!#LpalRR z%qQkiE6TtC!fsnd7#Kj9=ZgDBB?bl%=AFdkRxHQB0K)vi?jJ-M7(kd~I-fgNv^WC; z2y@g;XOGcVt^Y2~zyQKL!S35685lsAV-xiNtbn9^WiV9Rya&}3i$ zVF3n4Hyu_61`uZRbpwq&f-qa28)z^Vgn5>`f8%3d0Aa4pjP9qn7#Kj9dndCS=$bhY z=3#&6wpWyaVefXsSZ$ZE?M<7tGg+n^Jam(vzSrMSVETrYMyA_ic4!CrG8vmsPh74c zKHYMh)zM@!F`r&w?Pxqb zW?iE2b}uoVu2#uUpz9+*2hfAgEeBl<0cDF!e>+>pS~Uzw2y}2iBUHKqNxW^k?;IU* z-n~ddr=}Oq(GmB2iX`+4i48jV9%hmV=-vsasY*y}(Ao7cH7?UH&e2hp%t4ZFL}K?% z=bfvgED7qQz;v8OlD;wBbFPju_=skhH0bno7+ao`fdR%=MPh3su?>;f7D#LtBsOS$ zEX96PNm`ZL%k~oFLzCPV@o{qBTe`Qd>wts5G0{YBzD>Km-BU$CFdat zZAM}rn6A1&Cw_WFPYuuXnw}aSM(^o!7wCvfrhz8dpf*$^u{)-pU7(}PxMBLo1v=uM z7m;M{A+g^eu|cc6VSZ5ML&T#M65D-x;6fd7$s{Bp&>6chZ7tIq7wRb2uR)SNh{QgJ z#J+>X{)oi>i^S#x%~(MFCW^#XL}G&$Rl}^egouOApJHHeg>b;p7Kp@-MPg?mvCELy zbCB43k=T!s*uRk2Y@mq%s6&MWKnq);9CaiKlj%Db=~zpaAqjOOv1d%@U96)lc>qc1 z5fc0TbkD^)%Jt%)i595gI!J6wB(@t8I|PZ{jKl_=xB?5dc}U`$k=SRE*ta0;>DxQJ z1naqk5UE2PiLHvnwnAdNA+dvy*l|egEF^Y061xY9Jrlx)#P3=N2OPhLkl5#t*td|_ z&yd*vk=Wdz7AiDE(~#KJNbJc-?D@h-@p}qM;`(&Kr8>d6$)IJhQ1kMU*d0jhJ|y-O zB=#&M_5vjKawPUOB=+O!7nkaYhyFtn;sTAAL#;PJVp}7z-H_OUNbFQ3cF}a(Wjf9E zpnX-abfN-UX96=Ci5-E&PC;T9AhBzZ*fWvXYmnGGkl05cY)DjJfN;Q34cdMJbI=PU z@h?bh2Ba8LL1G&qv2Bpp9!TsEBzA&0Xwf3n$2mw66-ewBB=!U(_8cVk3MBRxBsQq= z3iHevB=H+CHpu@^U>s0uUjmWyc#zoYNNg`8b{G;n35lJD#I8bOw;{17NiZ4X(YB9f-S{hh~O}|BC&&}hpyC7mTW*0 znu^3;G=1Vq9c9&1NJ7_;*l&>7Kd0YZsbgJl4O+Vmb(tp;I~<9fio`BPVmBhOK}V3l zLS!zI_-Z8fP9*km2pbgB3=CHx9B@j1jKuzk#Qu-O<^>H}K^-lP#MVS&nr}K>S~?+^;ba4>!8vvkl0_4*bJai zOQ;&qCLEX>C6L5bkk|%DY#SuD2NF93!iEHF0)zt&*c>Ew1roaji9G>{JqL-s0*MVe zK@;ZC14!a$k=VCnrz@@1iK~wX%{M?jScJr`Lt=x*Enw!&LlR$w#NLL)K7_7k=WpC;h}nak;G>su~#Co&mpmILD-h zuml6z&Iw}+PXD_}$67TQbdNODxOgOX2@<<;dhBMM;QF^nLQJ6HH>fs#B(^dV+Xjj4 zgv9nhV*4SnLy*`}NNn&`)c&BWKo}Sp(vc*Jk=WCa*x>7@p^n>#B)%VseHMugx@H;{ zEH9D7zaz0()sd=sVbC@as0E5hY<(oQEfU)si5-c=PDf&wBC(s1*b`xFQ1+Y;<1jEV z>_%drL}Fh@Vn0PydhJ;0B|mPKM~Be6j@Lc^ht9&{34E(F)CcboiWvSPvAIDT7NBY*k=W`;Y*Qq*GZH%x zi5(ASgTkMIfgu;n0hbI6)ky44B=&S9_EIGFW+b*3XzCy8xG*GkEQk%d*$H&%6X^P4 zC_6_JBmvb>g~aXvv7w44g4xsC)cLjQ&w$wwhdu_ep?Y6|*x+ez28MSa3!veHlso4ulO!pYK2%sKwur*bJZ>cA?_zAU4zj zK@c0X%9MeDK~$H4K^V%`0*ON-OCQ9Bs&@ggq2fVE>~LLB`3Tiq29kiX>yg+KL2Rfa zW+AZ`Be7S3*ig&1fY_iliVO@4J3x+uvJZpAp=!>8*dPai{C^9^VPIf*fy90bVna25 zLt=C2AySDT5?cz1tq5X6Ez zAr!=hiYJ2DP=m6N*bN{yG=w^l*prah^FVB<-c1O0J;QDUhv6cK4K?T%68kX{`#p#a zHHclGfdMqQ2l9;shz)h95{M1jK*PYmpr+5jAPi+2g2bU}tU+vVQ1~-2FgSoXPzf&( z8|r(15F09<4q`(MDnMelf!I(-_am`qAhG9x*igNDk=S?ZkvM;m*lY$242)0>5+F9z z0!1XY782VW#D+T54#Wmsi^jmf;AFtSAPi;ug2bU}B0y|!&{cU13=A1i4k#FNL2Rg^ z8W0<*xfO{$8^ne>XbBQ~EfRY(hz-?y28n$K#D<#x*npv)ff3SpWq1y9DU|&iqzD=X zT!st`j8HZ|hz(UEfyCAWv7rt!M`Al5vE4vys9t|KyPkm|6~uvR&O>6CBe82iY^dg5 z5F6@)86Y<3o@NFHhB<}|48lVfSbHdOo^h+PkrxD4VzHQzyEe*&?g zj{A+oW-&sP0bC$9RIdVv4YfcU#1;WXDg%SQ5$MJX2-^xI4pmd{3gSQ=;RRwtB|<@L zsCX2J4HZuXv7zF{NbCv_8>*%m#D=Qr0I{LslR<2#_zV!+p8+%z%fPT4!T~#P8xs2v zhz<3@X(aYT5E~jQuaMZErzd{U7q4eBW?*21YU4&?D}vZiZCXfdV-4Yl$O68kF>o7)VWYaoTb2!sPpbh1cn(7sBT+s#1YP($sJ z*nuE6)Im{5>|`W%IfxAn-6jwlbhS1E14ElxJp%*icu0`V6G0MCMRP!GXy`5kv7zES zKy0Y^UJx59egedXik}6sp%z?2V&6w%e+98Yj-I~Mh+m{0#A0Az;5BDp03H7Wa*Y@g zTL;93sxd`k+aa-CKy0Y3zDVq35F4sD2Z>#Z#ICOfaiE%8kl3?8Y^dhNNbEI8>`fpx zRPSyi_C*jIs`nNW`!N#xC5SBs?U^%KAbigQVnf4L7{mshX2HO~Aa23H0Gb*Bg^&_R z9I8ea#D<2y5r_>Hw*|4G;!Yqo)EsXlc8CRNv5WZhTZwUUS~VaEsH;0bY^a8bNbKbx zHtY1T-O+OOM?q|;nsZ3(Cm=S|oVQ5qZ%Aw=O9lo;s9tU)wjziP)vJZXHb!FGgV^HG zkn@0WK!LVz4trz5cokk~aKHq_!)B=&3&8>)8+5_>HYdnbqu)qBbk)MkeU^+k{b zXx%Ua1H)BI1_og$`z1&m8U^n_Y^eI5AU0I|ABYVV=d?mJGWbAjsJJAE4OOoJV}pth zT@VLqnHdt>2gHW@CKQPshr~_+v7vhNKy0XGr64xwB47pvhDs|224N_>1tbntGsz0n zW`|1521!8KYe8(N#oLhB`;pkkKy0W%7eQ<(aO^Q$1z84VKLCkC)w~9=p}zkBVnf91 z8Q856!Nmh&Lp7@+vGtJH4j?wvah^!*AS8Aqhz+rTAqB(+t>^+ZPOTXjgrV$WkhuSJ zsS`Tfu!d7JSP0^eSs*slz4JkAsJ0zQ?1M<`>mWANSr3rdFOk^qL2RfwtTu>|<$3`S z2XtgG0|SGI4FiKPlr0Yuhx$Vc#D+RZAH;@=dxF?d^+8DN3=kXYph6^e6%xAv#Fl|( z!s#Fm)X+sBHt19f1_p*@AO}I&8*LD--UDJo9dr=H25t3bU|={8VnfBRf!I(p?}FH% zMTZOw3=ctOLfLO@kTT(SkRqsNZd-(9VjwnDTpGlN8mb0jL&dd0Y^b3oNNg_<8yXV9 zNbDFG8?+rP3B-YF&PHN4g4nFn-R@`0)z1X6p=uT(v3G#jPzw$su}>kfFM!xky*H8A z??G&+-XBP8Mmuox0-PAxL2Nl_GzmaBU(3!iEV+zwga)D7P}*{V?k`F-ZUh3 zJ`%eW#D?mvvjasFlrse+0o6PgiM;fcq8Hf#aPdyTQDu@l$I}eGy9Kr^LEd#?^5C^Jx8xs2rhz-?z z6^VThiTwn`hU$Hb#AbFxBxD{WwkQ%?+7Xntpqf=c5>U1khz+&a8Hw$K#0~>??Pf90I@-uLAS|+*wFO!0>lQD zDWFZ0jtmUKP&ShjqNZa9v7zDuPM~@i%25JIKrPlrVw)hbtwC(4Wo{t061X&A@N!~c z5QeftLE=y~2_QB!QKy2~Q1N;Y8=}6Rp##BTm`PsG0~68)`v3hz&I}*_nYs7|PBAi9^*?g4j?;)PdMg@lFsMD&7ZTL&ax;*xt}m zcpiuYmDmbmLpAIIv7zF}kk}VNY^a*2AU4!N|B%@1E({EeP;prh8|q0lB(}Z_s0{&? zFa=3KHTWa3GmzLdNbLUUjTd#q>vtjv9YSK?0I{J)KSW}`LSp{|v7uIiF13fbSK1Zf zc0&*wYK|2W+ZnrXaRD17w)g5~KmdVPIhJ2T4FRgn-yk@mM5wK8OuL67R8|nx%5F4uA zABi1-#Lfb-p^hj~z`zJ)8zHe>Ky0WZ ze395;NbFb;8)`uYhz;5R#=yXkN6)Kwl@+x5X6S+jY484Be5&%K^&+-O-Sr+B=$rQ8*0!z5F6@) zl^`}~#~cF#!&)B(24N_B2S^;M<}ip2_5BGD8!CPo#D+~FK7?{W{(lByLlu1lv7ws3 zf!I)SR$oN=5CO5F7Rw^BjX`Xv$83<;u1IWeU(ggHRC6{+0?MvOVoyh6FF<0i0ehKg?jv7zDzkk}WH*jGVps5SSH*k3?wXw3aZV%M|zBRtLnVna2n zA+ha{*x^X*1SEDb61x_}hB~?h#0H(v!N9=K;m^Pz3}w#&iNpE<3qc&HhBY8I)R!AU zY^eBtB=$KZ_Dv8Qs{S5`4ORaV#Dhx+V3hz(W$7K!}_iOn7eYQ{n}@B|{Vzc`2u6_)|Ap$4gg*idmD z5F2W-DH7Wo#0L3{fq@|ei5-i?P6n|ddg~c-5FCb5Bz8B54K-*A5_>KZdliTcF^J(X z68i#(4R!Q&5F2zbD+2?=?LYA4gnAGM>dQp-DZbV{tA+Z;L*ids;BC$6i zvG;@6P;+iT+2Emvryvg0)gM4?b4cR)62!nDY(72j0ivAZM_Rit1!6-zC=X&ojnGA6 zTY%V5HMSr&RE-CS4HfqVv7uIGA+d{**ioGz4%CB_kl3@4*b6~ys6kti*r!2ksKwVn zY|vR0pxx=g3=F~+)8if@{Pz_}`X3ToAOulNN+Pk9kl30aHq;se5Ze+Gj3yxr48l;h zH%J_+CJe-ehCzKahy#_#L}HhK*ic24AU4#XCM5O@5E~jc3z68Xkk}hQY^dIyNbD03 zHmDq8V7Lw8fSvsviOm;^$P%I;wiQ?jgJdWJgD{k>0uqOMKp(`0I@$!phKk#R*idml zBz96Ls2qkGlm<1_mVtqx3Q18thz&KU3&e&RGy%kh>Ya(iUJqhJLuCgN`ydkgIEW3> z3-bR37>9v@;RzC(HH?9Q5u}KLfk7I?hB`tC#I}ZngjyH_gD{kB1rmok&K|^uihCfj z<3Mbv8Rb_-hawD*g+^ zhU#UG1U1>A9LY#TNvDLw)<$9*g4j^?-bm~aBz6{v4Gp1UBz6rFy9vYwn^Vug&;#N? zT{juTc7XVDdL#pbFqFLrBo0-x7Q}}7Y!iqL6+Z}KL)D)`Vm|<}p$>Y9#Qp?g!`9yX z0CAw2d7>B?7@=$hB(?z(+X2LeTI>d5gU)?rU|{fyVqg%4vg1MGP>1Fsv1^dn^^G77 z)Szw<8>(Rfhz%8=1!6Zfa)};q9aHWPmtJek=Wmm*j%v)#|a~`H9>5sQ(BZv*v+l9oQjKrP~Vng+AMq=*)vq9m{ zz`$?`#DN-g8;Sh{iTwe@h8pw}iOm$xz`zIu8oqzW`!G z#czYyQ1J&KHq^40NbLV0Hqz#CC;FLs&pK;9|@Xi5(7NLk&tmVrL?; zOF?X?Bl?io^FeH=qqifm&m*yKCxND}po;DzNjyVhzd~YvL}GtMV*i=`_PvgHJx4O4 z8Owvj7C~Z5AhBhU*osJOO(eE165AAsZHdHofUqHjnG1vi4opuZwl5Mp1c@Di#7;nB zry#Mjk=Xf2>~bV_buy?jg$8Cbl0-WayB~=?8Hqg$i9HXAy$p%H3W>cDiM_-xsjKrRe#Ga4DUWUY8g~Z-Cz4o(?`1B(Y3KH92eAd}8 zg;8Pp%nn_D#*FDNL6pgK%T8T?#)9dcAnM5Un;?p3x@MQIKjVbyl^{xF`biL#FT|Y*R={vi1{TU^ubN1-^Gb&7v1W^LhSAr;s=|4eK&UDXSU4OXCqssK1AZp8W&S|>-j4sn7LDZ7zE2n{iqI>$UX}W%lKGQv?>-sYu znLZOlsZ4)49b|0pbgLPR$Qp-&lobja3Lr#*H1sR5FF!zi*)@N=S)vr1TtaE z^i7L&{TO?uGcJaB3`9jtU$__)oja$0TCD5GC^6k}2{<851W^LhAA+bI(+!vE`ZL;0 zZv;^~(=URk4bv5u>H0I8OfOuf>(6v&|MWx4bp4qA9GEV&T-T40WqRUru!A;&sFLZ7 zD?o~lP7hiE_WZ&XU`KxhQA?&fuGIBsoHBhPh?1E85JWARZnz2@LyaJ+W%@-Bb!58Y zYF&RukLiW0K~ZvP`k~djeoPN8PZwIF>&JBA%Jd`<{o%&+O>1=h7(=EruGRHtWSAbf zR(C$5!t{@8b+sAyPM2M$tIT@j4I@L(bXO4b>lOwEk?DdT_=Tr8tkV@>egr^5=)D>nkG%_`_G?;#|rbL3(z|!2pV*0)P>}pJJIJd9cs2de!T2sWp z06tNbfrZf%bg%jnZU%-MDh!}Adm-f-0|Nt-zb*p^!oXw>5|IK`S znPT`D7+5s6g4}gMg@J)Zlb4Z!ftiu%7>HtFUn9=Iz}l`ky>FJ2)N}`4Jt3wT#p!!y zIY}{^P0#1m(^j3K$iTqj#0a{3ItF$uThSurRZ*f-YBJW?^45y^&8(I%F4UNs2%f=!gaZJADQQCV}s~ z3=GTypo2VE1ZGJvFt9Q(fsSBeRcmKrU|^cB#K6F&Uc=}j5CTnYvzcCFU|^6Dnl8n_z-D%ufq_AefrI5769WSW%VCi9ljRr~*vvr!!aQs? z-5{%t^%xk~Y;!=@l?pj2GBB{&f!HkdLTn%h*n%UWy-KAlxSPtw*&lYxQ#+8WT&(?ZWcHe3gp$|#g6 z#K6FQ;|<6;Lcci}7}#%ubTSLglVV_Czs1DDz`!CTH$7TFPu|Ezj)8&w{z9-33L*>) z><_+!Zm|`LQea?Uf5^nhz`!KrtIzAEDHmx>Gacrdb0JJpxh(C3f>_8LIjisx!FKz zaFzfA1B<{bDFy~sfjUqE6KDb*AflR!CyRRg4jp9!RglZ`{4={Fk#0~g2iS3-JHVq1k6 z7&wfWuCp;Ph_Z2*GHJ3iFo^k0mlD>q(zwsdz`$V(*2l?DhzUei>dTO>_Dhv!90bm833LIffsT>RpTqpGy7&yY2K%vgS)vw9Gz!AYD4N5Cq z9I^}y9Fa_0L4nAnKmES2o}}|%keg$`M(}bSk!N7wh-Cs@UChU|NREMlBMxk)09T?K z0|Q4q*meo7ry!>!GDR{mFi3Jem!57dqNiHFLX3fdBNc3rECU-TV}mXh1qUG`1FHr% z0|Q4o(^7T@2F?tQT&9~Kmx7Lp;mBhGsbk;@;$mRnC;;1_z%>sPd?jE%C~<*~A?GM% z%4B0;P~l1dIk60EO)6I-$kcK$r#_8=6*OtdQN;v0w3m~KqmBu511J|Ld2-Y<#eoiG z;W_~FQv+B7BLnLlQ0dah^pt~vf%UjH0|UoGCPhvL242uPynJ8+bU7^p2MfrBoE#jd zm@+sS7`T=SGca(R1{=b_wU?8Df#VF*X;8tz2np`9kl6B>WZ7$wWuOSf2SM0JL4L>qvn9Zl8Al##Bo70FKq|O4lT`*CztI4yPZ?N$gOXt>SS=?P zM+NH!9tH+3eF+8zj!ITgfx*B9s>3*{SQU8~7}&T#l^91g*fe%7P%T!^QNyYWO5$9g zJ%SvytRQc4GO+#yxuK3Vm4|_Wlar&7^%vaSCS-G)kk+8T?E||o zfNMS|a{IxS1ah%~Tsr~G3F7kMU|`^w2zFR77bhsbCV@F246J%O3=ABTS=o3Q7&yH+ zrm-I4t%o^gI@DX>@^uEXTV_Js!oVsDvVRuqM3C+Pj=8Knd@#-PkTuUo*1Q0snTrEd zGA@L8gn>1Wg@J)%5$ic#hI$6p0#F)X1BpU*j`ggd3mPF&xB+VHY-I)pj*YAmd<+b1 z46MgMnm4hk@G&rODspUPZ3H<3TtaSR1(%TA$qXFZSwS;YjNC;G96P{FK?c?eP;s)8 zH3X#5i(?P#K0XG9dWcPXp*DeizYp01`yn1+VC@5i^d(7)^bqUa+38F$fSC9jx($laHGybjrzpEz`$`19MxGz`$`CoJhsubQu^pu7H!7*hLKn29B%Xh!XPv zW$SCKhjU}VU~L1L`jGV=KeQP6#LvLMC(6UXzz1S6aIk>f%9;ksVNY0D1Q-~2B?TB5 zAmsum8QfPw2-J*XA2)T#_EDOtPHG^K=qd%8>nBv$--g8CL_qezy)gc zau|a(GjM^Ly&NWB4kH(+-OFLh1}bKlxV-i285lUsz&vIKR$WjLY0h>}fPsNihQpez zSdf8%JEtU@fy0Ikl$;s3nn0zjEt@AJ1A_pU4JZZJv4N^!35X^3U`wR9I6)Px1DGSt zz}gRL_c*d?2r@8mN^rQaZ2-BD9h8e)+3G<>3j>!5sGM;FTfzb{${nm*gn`uuWR?e8 zJxI3*hd0|VxTAc)>KV9GGRqh^e8KJzfLQGZ)+_`u$sf!SW?=mfilzXzJs^`LID*++ zgh2TZ?2r&}V+(3jDA*{dJHo)a*&r?q2iwTbzzVulk0XMOO^AVkQ=B7;tx<@9fjhG( zn}H)5tb~E<4JaMNun97OLaGN;?!~f!Dg;3W){CG5Cyp&Zh=D=0UWOxq?XnO9gV=RY ztR{lPTx=~Un3KQ(C1%ddz`&6Vwn3~HREnj5gFx&%C~u{LJ;A{0!^*(Gk;c{wat{Yb z1{KwH5a0q&HHYzB@t zFh_xbRS{Iv&NRWqY)N zWgW|JkT1@Iioj)TvLXx&tbrhh?FA=O)?QFSd>qW?FK#?UX#1AsB7sM75N?>PT;OYYnhKLK(JZDx?7l%=w_6_%%oXE(Q&=fCeP$Z5f!RgS@xEO`L&&$y|bgfosW52?hq< zlM)OJkSZTk?=vu60(o#5s0GCP1SAFOPJ-nbgl)K1hD$Oq2(1T&`zla4F$k@eV_@J~ z4Jzmvh1P@Obq$EkF7yE8l(iry@(P_{XQ*f3S_cYzKA~x#-rIVRIRZkrLH^zlE6Knh zB2vJ>wGre32_Yd_1_rK8AfJK?iglpA1q;ZPOs~}#7`QfrTqVrGwS76rDe<6UYX`_= z1|iVB6kIz&Y$hRoQ1tBru~~!)H5nMRxpsp%Yz$0mK-q3@o+JYU({&aG2Cg%ppkw+k z&cMKR8O&^+{zg?#vR+1tfq_c}6iKX%AT|RR=qPwDHbzkTWZ`lIRXC80%fZzON?eeP z%gMmO0tx|E(1pNUoQ(G*K^+<{ZpIvtd7yzxE*?fuurP3K2f2|K%wYt#in;h0L0Xx( zUUD!@Z&A||s@DSzX6*wdA#rdvl)A&nCCB(ent_3f2Ndt}U{MAx(B6A46-H2Wvv9S_ zGca(egH_$(($HXF;L>1xC(Xd{fa@7Zk0v81XrD;m1vyBEaW`mGm{Iy7C|YzGL79ew zQ5tjy1eYEoxUs^+D7_k#CiEGA;sf^Mw zAXDraE3~8-7}6M}W5pO4xE#P1rZY-kV`X6Aa%5DJVqnN%l;#DcIVZ-w)Ays|Xq?PGw?XFoY>{V32WP=ZTz z2JUbWhl^2GR+E8&I|9VvVU&HR%fP@L2{M;luFeYWi9v^7`UTB9Cb!n zP{QJl1*IzuM%lm23=G_HAQ??Y+1lxRntGDbmXe@~5hSL=C<_|r;Vu9*_H`L$?@o8p z)Kg=;Fg;UKPp-a97V2{*@F*NR1JiMS1_tg*kXL0Y7`a=X$}unq{Z(UN;BEym8H7IQ zFfeepy_N%wL1&9IFmQK(5}SZfr7{BpcNZwFi3n+c+}aHiHxaS~`KT8pZXxs*B;E%S zj}Y1?%fP^0KLI2WBa|h_z`#8bBvB)@4b%Xh3=(e;+5plp1th*e=rD*q4J5uqXoo5T z1NU^0_z|K1tPBj?vq0h}gj_%&HX9`VLP%DLfq{D-Xf*DP5a{Y{?)f0`FG6A89~axMV$(x>;e%62JZEt zj0_A~jIy9M8TZCR!VC;XjIyghk-Q1il}KWg1&tGM?*sLNiWp@jIyAs zdAJXNVlTP`lqUN@1IoYU7#Khp91lzk94w%*VoaC{S+k$TKhqmvG;yogS~PCsS_=iq6NNp;Qj=yb1Rcki7-q zI)(c=h+W9Qv;-8iFD>L57?>`BqVyvu;mC;abAOIfWMB|7(q>@b{sIaL2BB*l3=G^q zL7~SY1gem^e}hu4iV&zm=Kcd>s|h8lGca)f1+g`z|I*gul}ZF9@&6zJ9WFaiT4De< zbo96yrz`5{Db#n!GccHNfsPL6W(Ajtrd)S885p>^z$Jt=*K$zzg9luy*>Hi5ZQ|wy zmv;_aJfJo;A6UkP%Nvw5`N1+CT!$4I7`O$%GCo|PAQuUOi@N|WP}RyU0xlLqxMai_ z7<{=!89^Q`;R4mt++twIRd9i-X>M^ar;6)0C`(H)CMYs6)JTIbG?ZlQWoKac!zcY0 zl-HyfK_kiR{Lo++=1i)4+&%jWi2+g051fhy)4P>Njw_C5pG4;cmq?xkQ33zy6E^SXM*^@0Kn4BYF$ ziUqkkK%Dhpjyj}W!3CNI0<|kd8CWNAGca&(Wb9A`jnZ>(WxNK;W}vPi_clgQ%4gtu z1hQZ|m?OZo59FU6V2%Qp1jysNz#Idv3Xr3AgE;~Y;GQ@4UPe&QJAlh(`b0fF$y89s zp8EheEMmAoeQxf9U`{L-==gH(LtsuESBC}z1NUJtC!Pz`-Q_+C_FV!OAE?vspppf=pG>HPY7l4gdWFg(KuYUHqUfx5HYXTb@PgUbR`2V4Z3 z&c{^=DmyNLIs9B7Rj0@4>q*pu`k~x+89{>=;#{E1V7c#sLq&ptRg{;3f%^gDBP9j~ z){`K;ufckyEEu^zGM1_`FmTm#F)(m{0<#&oK(~)^e`c&!1@*!1f>QGrMo=S(gX=9Q z2YdzlgokS)$XnkS8&yGlZ{~Us?>jh|%77rJEYp z7f_P@&6vu_z@W)hD8azM{RiwYORlvb@A83XRjjxqKxMZ8cvi)Rs|FO4f=r;gsg?^| zH3@;|H?*d5NrP%21u$efE@=Kjd1$WM!VF#lY}{MLJxcfq|P1+%f*cA{_I zkeNKpjG%>etkM@j6`K$Ae$ z!6BDekjcQU&%9rRfuToS+6~k?Fk)V&#lWyeT>7AdD+2?!3G*H;28J!-(lVeFZpsX* z>vxDtZvZ*Xj2V=+Z-`6J2Wd11^X`aCGlIg&0?d0LF0DBIp^2U*WBzn*Q$1A9wQ()Bi=c=ZB1 zf<;2w9+Zf^!9G)wkj?~ECq7{9Y7)}#K8YDlF+%ep2a5tX z0|Oft>3K$qlr$02;6Pw;ACcry=g1H_K zA6Pbpfq?-ey9OeAz+6ulA~69f@fakb$q!b%2P&qZ1G#})&q7bhJRWqdS{c}J{b0wv z&|zRuD_~$O;{c7EfwCmRF`%QIK-P6YO_*b$Cv4_lz`(Fj2h^jDW-4M)VT@t4U{Lm8 zU|;}Uxv~W;5yfZ(xoaHc4)p?%JEj-L>xoUTRn_JG&wtF!!FhmqEFcgC&qF6!6iUHvQWv~kh7#LQ8%n+Nt z&r(m=Go=7*2%~`tV+<3A0Rw|P_$H@baL{Z62hBD;h_iaZL6e9QPq3ho)`JADzLlOZ z*l{L$U~>^c19O}=SOV_28U_XiQ1B@Cfr6)ifuU)7gO#2p7f4Kf3rGwSWGAik1kC01 z85kIsgPpbm?6mXx5T`BY0I_Ccb()|)#A&M5dcv%ra5J24Ypo}(4T>iheUK}o7!4Ve z;z3se6)-R;mBL)q0kXY-fuRLzzzl0WVMS2*&W7lMh3^um26a$yxj>xz$XZWKwHtJ4 z>`Ab5SA(6)V+e8XNw9OTGB7Y`%$hE1qo)W-si0GmKox(rdQeMNkbIn zL0z>Js%R%jQDp%G!^!CvZS>^pK@s}M0OYM`c%&-NVqjnZMdLTHL=@9RCkFMEpyQ=5 zVt*^>Dv|eKH%|t;S=k8U=J(*(2X%NgZh&r<`vlIzOcNb6;z1V|f95#I%D})haeBV3 z9vj4^pf!RZ@3b01yff1l>YaJhH`?lnu!0{UO5TsP)%cqLv8K#gdxGO7Alhll_{~;lLW_7n=!2BHr0@Gz2U~W7Mm9{s5xIWlHPnZ=H%yHAR9rUDF=N2$9 z)J^Yl(31w|pn20*Ip|5ttten%*aR_<2^1KhQ5I0FsmC!fFhDcHPX|4TWY92!-g|il z2F8=1_^AUYtk&qgy9g8~p#xG9H%&M7QlVAzN(!|1@E zlmU%Lbx?T(b@~rSJ@GhD>kM4YF`7ZEIS~fKkERR^df*G@UxNGt+CR-Wr`L>uL7N|R zg#AlUdSeU%yBZ`4bv5YD1hA_?hv0!yR=F9%)q(1ued-`rt1w1EquhZ3YE>90!~FtT z1=_UEIET@kfx!sWw`TkWu?kU7z$(tyP_zF#=?Qyc7;CHxx)G0?5n*JJIRk?UXs(fw z8$7hl7=&qNj5)-;1d0w;e$FJ3Nt|0 zd`mNe)G~%Bs);i&Fv>EPTQD$uVParV23=gVrGSCqzBwqmAfAtAG-6N!9jgfrFwl`H zpa2uIfH*+QMNe1@7|#V}j%qB~Swaq*J{Sl=&b>ALB=UG$VCK#oBqD_F_(7iu53tDdCq0dQFfavlSN*&fh+j$z;d7*H5S zg3{-l+aLpvfqWMR4vQ?%)X!Z|@dDv9217z3oUw3vp{t&_Dack(<4+lMqZKF!+ASge zf#hr>1|`txFd&a8gH9m=1;IW`NDy3d)f3JG1pz3zK)t^e>U{>|DKZQUjJ4qC1)bl( zI49eRfk6RW7}kQF#u%hllv)f@1Il}6nHd-~?t$`W10!h3Fk`S1=+J7g#h?}NAd5q+ zrXTdt6PuptrYEFz1|Alm0;-sSfx#Gj@hqsAVPJsd?>uV;22=g%OWpKz-N6O!bVg7I z!jpx8K@n`%46t44EYKtXDq0^~!Tisl1d0T(3qWZe57KhV$=2A^@JcrE2x?P z$pl(M0wvX5PuSoFn%h7P8_=?PKnm<(g2RHQX8-fSGeoRhk{+W8SKJua2IX? zyHJFcfdQPCTWw$^5ID_(9Q@oGkAvl=KQz%6o37^$Yo3Cf0dj8~M1nU%PkefVhaRi_ z6ErtNo7Nx;!7XlK21AfzjhBMleFp4>77%mJTwAagj(F%yKC zF<2RN83D+>Jhlk;g3dhz2QX->I>=eh(;YqaG$AeNG*HGVU|^`4ZfK@0HoebNPdNGm ziYr0YRt!@Kg9>9T6R6E(d=u2%c?EXdF0kXY>=+nK4S5+D7+--$s1~y_Ferd#Wubh= zU@Idb1_s8rj9SzGcw85op7xA%cO@YEh2^U9!GVnCJmPkRO# z2AHQjp;e%A3^eKu93XCY@zE1zf~fZD8}CR9B`I#dc=pfZ6J#4wsMD1$m9 zpu)2ayL1(_nXnW^8kE#Qy468h4`eSWQw{wV&Zrgl!FT-F$P1BHO8R(-x%+LEe9Qw z#5iZUGXn#}p1Tlxg247{hufnh$iTp$UC4l_-qk^eVnMyN(O*xt9;6s-3m=0a$UI|k zh4KbACHBFqjlDFunvQAjTlYeo(4^4YtvagMmR6lx;!LQ^df)U^X2TF@NEy z5acPwIU8JH<;GvIA%PqW4CVz4jQ^P!%cuJV=&995fW{q}z#}kcIiQskDB7!Bz_9~v zq=B2?AUA;|CZk9gF{pzg4pcrtTmq^pCkBA3qltkG4A$Ht3=E8t%yFR21q=)fT#TSj zi zE3!k47?eOeW-K~V#gkvza! zS8*~hAR2G5*7Z|2uY%m>H1J*o>lwKec)+ah0b9?_#lWDT3rZ0X zK4UPX2IvD@&lrVhw}X-&$ntm(NI_m4q9?2YvKQoIaL(`oU3R_@> z`@urz2sm_JfkFq|t31LC8f;|@HU*_d#v{zk)8B;ZNl07+WxL~GkEC%kFo2xPz<7c= zdb&)Qo+PC5hV}e|yuh{k^r$dBd58=wS4{ANdqGkX^sJ$QOtgq{q6E;Dq@A%qz+=I|G4JaZ&$plc#j#>y9Bu}35<=$}Ak>Yy^Mk$TEnb9}-6 zWV8j@1FFemm?j1=D2cJaEMkFJ^cDxe^v01Qjq6Bb} zTjCEJCz=InKQi$!FlapowOeL^RuhMUxZw0O3zVGtc^DXUz-`32peEv89&9Dg^63{N z^~9#{j?xoW0ws>!eqi^5Q}$G7%2vJzEnpd@e~8jEhlI5nG&$J$L&C*7T2G1c6n~=nJ zG*(ZQ?YS5OgPG9u53zb8;w8Zh3~EU!i42S~tf091&C9@G`dxaubex`Y1V|DRlJczJ z$O_fi3mUOhUkOQX&L7cui z4(9X(sHe_BWgfw0CP8IbgCTk(08Iy( zffi>n?qz|sZQgVtCx?ogLU|<00`-~(58ER)VU{JpTI>rkW zP~cHK1_tA6pqTRqA9M5!91P82uwd|y1;_nNeg*~wRsqmKGT_}w)7JmSOe6A?|ZZh9&1%XrfJp%2fMn^NA>dMgYMYXF{dtK&3Y%>j~GdDP&*( z9bpQpSxOifluj`)Fo49A?l3Sg>;NShV=YjF0n{jDU;wq580VabU|=v60wvLZET9Sc z8UY3d1<(#5#(&^+%^0iznxSWe$TEgN{Kf$G8>H}J1p9lg0E0Dy#(z*T&IHTZ%KQur z3`YtX7(61terGFU;Q9~h1A@kN!QKG(0Sg!y>Ze}}&=#9MIR)CPodMPW>WYHuVG9QE zjKqaP28K0Y3Glcjcn%Vj{vZW1EWLwjQwFokpzh9ma0&z!@}MP8jB^5_85m5#_1%21 zoA(MZFqn#SFfcIAX9dZD_Dm@n-2nyBLa^5V0?@&-v}jn*60<=X5jp*06sX^kswb*d z776w#xa4IjQULXjiWwM`K&NSdJq(+MTN??9@Pnza2nSCO7BDb8iJbls)Q$O>3L6;w z2#ss$D2N{YG}sWFBB-P)U|&e%HcE5pV5I`XU?$$~(7=}eNFqrKHjnaMr2OB8FK?5+1 zbEINmA^rs%;--QO3<}^7{{jwi#$ZKoaDM~q%NK+OH%J?#`-cc_aK+AAz`(#1Gdj@erW}L%2JtRXf&Ji5d?rh*%2byp_*g)fW%Ah^Kph9JdOn}-uAQ^{PP&kQAcgWOJhZHohdHM2KNMh)L z>*0Wg?H;fm(dmaW^%SLU7cwwhh=tp&45|u2&Cn0A)Bk4bNg06Hpyp`F9!5}R1~(Hy zb2jp8K|M9l(GUy_cA!iA43NfLabh;GIB> zAsU*X0dXiVR0Fi|n-RhT)k#XACXq0B2cexXG!70Wz>>Tj=muKQ<-8Kp#j;^Ts<4C{ zF@0jVw%Byg=&!KSL|A)p88pexfXFV+){}7n`DsTy*w4&G5PwZ{0A+7825>b5>SbJl z$U{aWm?kfMBR{0nPhMMWM zIeKbL&kLt7&CxS419=CWUNsmDL1AW`td7-UPLIvivu8}3J~vlS-VhwT6Trb6Cd$B|2o7KfKMTYM2Qh?S3*swH zf19f(&d5HUHBV2I(Qvvxh>D&bnWv|z_PLOOp(Y6uG!r-0t1w10Pux%s3L8TP=PXY%wE*`60NF#JxM{y9%izn;5@fk8YO)rjr&49X^q3=HB$ z3=9@%a(iLMyD>5_C>Jp>ctaF`nhODp3=H~33=GLoAy6|CG&7qE6|aVhn}Et(Lk9I) zMg}GZ>*-i6n|`=JPl6Rx&z+n8pg>PlGdr4r;RRG9Xb?4;2~=6mfTdm76t_kyBt;n) z>dAonh#sk6%b3gl>4P#QXr2l*f~xcrrc)G}7VDupCl~68G0vO5su0%sje#n-16A;{ zP)`cdo&(J_f!wSxU9d>c3?g;{syZAbCN@30NKZ^QGY#wpMgs<=Pq6857El>o07@W& zMS5b>w-o6Ki@SsR1@cVLJ|$=_8)W)Bh)G|HV13tKs8-{2h+i#>^%UztqvJm5V0$35 z&7gkx8YTvY;35WwRIo%e6UTp0@-$;mKFP$u0P4zBf+eCrvnR?|nHU&At*jYvF;IX( zN-;wQrB^U_F+e-WS0U=awI=IyA8i4y>5q%`Bq3Fh8b}eO3X&<&6X69V18`0jVld>K zZd;-!DJGW^R5zSU@(oEo>QWyFA8p(WwC=Qft3=_vQ2LKh7vs`w%#lT z2E~QbZH0#xMKy4_n zFk_hFTy+Kp#)V+*%~A{uir^Sn432?aQVa|l3qd9C5_Ztu5~hg(;K@jk;gAX+p0%%M zBRm4{55f8ad^uoANP=OWzOO=$bGlLmtXY%=t$kdlZ>-Q0n;r?503AOD3i=v|#00nm zs2c>5I1G}oWCO+C`<&??D)iLAvqF5+r7QKMoIo*&)YxQzOdFWJ1@&l-g8d6>`EY`R zt3D4FTt~s-@>7a|!PIAZd8M9g7`RwF0S=IOX$A(xL!k8wC)q*G?}gIPBnr|G4H3|; zW>C~_$pw2F+*pD4kYFw7FS(GE@xKx_)&*+sgZyNY2a&O_f<-#0z=B44b(NlaJ!ta7 z>@jFkj)4Of>9wE|d5&s6%ohwCpo|6DeFkauGjo7)l&=ibxu*H>vYCg0fdS;)hj|F+ zg7)%(+E(hYUb+fn6g2V}7^XMG>#zRS462tfD#F$SP`hv6HqYH zXJBAC!6Z7rW1_lu3;b3-YQea>JVQyU(7i%E~1`y`fW^swuV_*Pb z?ib81>Z}Y5Ak6ce$>o;_0|N-N2QfPR7Gq%eT@RWYHgIWFXJ7zfZWR`%*$NB{Ak1j& zvYCT{0fc#8Gr4$)GcbTK&s!!JK?w#15a#~J?DR&PfdPaW4P96i85lsA`xmpz9YzKQ z5az$e%O}XtAB|qTV6q=>`wo3;23!E8qK&1c!LpP|?4rR}nE_+VjTJ;u^5NOFKOz9saajxmL=k&#S9XS~oVA6im z7oO7>H_Sv5Dn(*9BC)3-u@_H&c~0M5@)ME}I~T%Kk?Ef2^_4wskc0w}*l|egY$SFi z61xwHJ$w4r^ZLs5hmnMCAhDkyu|FWO{~)nBxDl=sMPe%=vF(u9MM&&95H{$TDF%kq z5DqvV-XO8XKnrJ~QKE#z)=WuXL{`wedWXwB%w|u_B15+VkGuPB=!R&_FE+OZzQ(Bbl$7_ z;`QdB^#o8?xFWIBk=P|j>?R~O=nM>)rxqiLuSa6uPZ6vli65APx9fQQqKw=+8V&4E=Fbwm-2PBC0|MI^TV^oQ5<#cdOjgmRGB9v@p&g061c|*KiG2!*{T7M+6N$|# ziAZpQNNiaowx%TL1_r2)O_3zLk=Q9n>~bV_GZMQWi9H*My#k578Hv3Q!B%59iQq6? zL1Mo^Vt<{!@Rq)^BxuPkEbUoKd%E#*Pr>>&2nU?Vry#KxA+a|g zvG*ad&mggHA+fnZa}H2PizBhEk=X7KHfV_+14A%`19n6_5<44-U5>tfdGgqHgU0Hi7EecFFGgaoM`G_rVjrKraJ8p+{e2{%*GTN|NNi@%q7kSy{77tR zB(^#d+Zc&$kHq#yVuwT6kY-FWgaZzbg6WC(^t0=kKywsOJ4KP$ib!ldB(@_G+ZTx) ziNsDtVizK@>yX%;5H@I)I0M662nX!0l}PNZNbG}1?6XMhn@H@ZNbHYD?0?fY-q$}} ze+M*Z1oi7HB=!#^HXCR`8&r)55?cw0ZGgnKLt^_Nu?vydwGcKW4kkf3V870v&ihbb zoc9=#(BB;E}AM0mNmw2MjV;BkAP6ZWDM`BMx zVlPKxZ<+4-MBiHV8Oo#=xGjk6DCK_fy8#s*c-DliTM z1A`F~+X0E~hs4f8Vpkxs+mP5(kl2fm*c*`8`!tZM=QBtWw~*K`kl5dl*eswW5K!L; zA+Z&Z*m_888ziXVsNNgD-wiXiG0*UR0#127XCn2$aBC%QPL6Zbf%XmO+ z@JuZOgMc;zgD{jW4HAc{(L`dKfY_h~x}b?U5F4uA35gv6VzWX#mWag8g0jK>F9UI) zn!yf&vZsQ?p_=C*v6myU*Mitk_1loxXFzPI-m6ILdr0gj+6?>*j8M&QK@x1!#TKQ= z)r*2ATA-R0L2RfR(3#w@>|_cO2k&`iV6fC-U=W6~eL>>TPzeIDq2kd<>_QM5YJL?G zyBWd;EzM+L=mc?~ninClw<59kA+axj*sRmlHbu+TzXY+NQ3g6>jS+Mz3IhYf7m!1t zY!1-E1*k)LL2RhF7!q3t#D+T56p3wz#C8F(p?YH>Y;deHN_EIGFY7iT$_aKN3^%&@i97bM9+B&1lz#t4|KhOo0s!*Rj1!;gvfDXii zX%K0#s>L68^nQHP=ds+MPfID*ig+q zNbGqaHdOC&B=!a*_I3~(8WQ_JY|tt&1_p*hdJGKp!cY!)EiW`AZX+prg2es>VnZ!s z1|60FW%D4hg+OemnV=aQMkw1AN!$;?j%EOzVFOc?3zC2uT86}~M`E{v*ib{Kf!NSc znFC@&#g~HF)7f%~_OdWAFg(;}U=W6~zk%@UiCuxj?gO!*22Dp|FF;~1 z1F@mzoI+whMq+=5utBK|bbAQG2O@?H42;kmCt=9IAPi;efW)D`Hw3YvzIQ-k`-9j} z^$|$yJP;e|=yD`>gCQuFK_%Ki5>UNR50Kd3Ky0Wv|B=`nMhpy$P;ovG z8*07^hz;@p$p3mE4rt~U)OImqU=W6~Z9(E7MGOoK?jSbQ_dXytR6GpChKfgn*ii9Q z5F09<1!6V3i8Vk>~y(Db1?UGtN^Og(75H3I{KJxB(s+XIOm2Vz5=l#awMKw?*d*iduo zL2RfwGm+Svkl4GC*wd#N@=Mg;2Z=y!VK+m#ofpIgtx#lOU=TE8U;qt?g5q5UBn}M& zO(eE4h@A{l!N6bvVng*hBC*3kY^Yrc5H=)TWkNV$-9;ca)SwCw8*0#G5F2XoOb{Ei zgpz@QVJ^sVQ1(_N@qI|_D zNogjC4HaJkVnfAOg4j^;?MUoHAU0IZadS|)2DRV;NCL`!iNyX7VncnyVS&iCf=Fy} z5F4u39Et6K#0~|Lmk}-VuOx2WME+EwP0WXT>}IPmKh*% zsG7wfHq3z&os!1Dz))_*z#t4|H-W^VYI;FzsDtKOfpQ|0vj`*s zRkQ(#y&J@asyP5+L)DxHv7zD@Ky0XGPmtJek=V@Eh;+;YV}o*{D2&6vz#t7`Lk&_v zVq1aO&`@zkV*4PmgFtMk-h2=n>d-O}TLB!n3{}<)48l-$t2HPmLKRH_DT4ZD0TO#D zhz(V<0mO!?*$QGq#SehkQ1PQ6HdOpPhz(kp$iTpG1;mD0`~tytX84HUFtFPof=B>~ zEs4aI2eF|BX@J?&<=&JjPoKFlg{K~BSv*)A;^S@*8|t7*AU0@|9RmZyG#ds6VJLec zNF1tW4Tuf(%pN56c@P__<}MQZH4?l2Cx`UA+{3|yg9V7u|GuSaOFe*>KcS=XDUIoO4`oIvxhFV|& zVuRMXGB7aM*fB5&L)q>iaj2Rg5F2V)IEW1uPXe)_;^`nZRJ;_4-3(zvLTDm{0}hHg zAU0I8TKML3>QIcsE_Y}*lOS;!SKL=fk7C`ehm_bs`&`o;1bR_mtB=&j` z8?+Fafq`KQhz&LKE)x4068nb}Xa_gc2aL{$1jvQN76!4QhU$aZP{)~p*xHbwwsK}* z5Qef{LE=y~!AR^_5F2!SCj$dR5{L~}U(djh4d*a0lpwL&Ky0Yv`jOZ(kk|`BY^b4o zL2RhSM?h@Qv4ac@3@1R2gR<{~#Gz_lf!OuX)c796fhzg~VnY?NyD%^?f{x%~U|`^O zVPFu3vc*8+P&JAmHq;z_B(@2N4OQce#12AY`^ADdP|ZmoHq?S@B=!^}_C^pJYUmyi zTOSey2SAR~pB~3(AP)1>ZICon=`#=;YRzj98!G+{#DytgZ|UjG%irKxf{7 z*idVfk=Qy&Y$p&K8d=j>F6qeDLp5iCB%qp$k=Qjz>`5RtRP$^k_7WuaS`Zs*=4KEZ zYUUm!_9YM-YEJ!aB+e5g_FE7eYS3p88)^`r8v_F)lr4_L)&#Mkh8iKUt&!L+AU4#@ z01z8C%^42jfc9T9Ffc^BF)#>2+4&%GXt0-n*wA2aLSj!qV$VlnuL7~5de?*4P&0QR zvCp|7Rjk)R5>OvJKw>`wv7wrOA+dSg5&bO@5Zefn#3bAq7=)p0Wso@3(Rv^@)Ir7| zHb@*)usgyy3=9lDAU0G{Acze$C<=*P0AfQOT8YGNLSpxU*igNTkl3q{*n8bU6)V)B zV;~7A`#ci+F^COvDFXw;I}qC#;>%AUUqab`LE=y~93F@|jTgj*ic2H0H9>5M-g*Wj z1c$)`#D+Q|5Q!ay#7+RQA(|NqL2Rf6H6S+VU`YlBh6WD?24N_>8zc@@GY!OshVE<- zI|mg03=9m*Kpd#VY7iT$VH=1I72geFL&cAQ*iiA)AU4#pD@g2DAU4!9pOM&qkl0N1 zo(v3(P|e&(Y()?os#yz(ZH&aW1hJudeUaEn17{mEFcg6}P|ejy>=q>UL=YRQ zdFk|v>;~fX_mPDDBe6NW85kI$O65RosL|?3Yy%{=3y2L>pMu2BMPfID*idtNAZ&2N zF-(PUz|l1u#D*HQ3yFOWiTw_V{T+$T>w{?3h#|4%k=Vu{Hq`tOA5g&w<-{UM6oc4M zm)0P$Tanl^L2Rhrok;9MNbDORHq@MlNbFZIHpu_~Kpdz+?7oO#mj$t*n$?il`bcbR z5F4u31&JL6Vng*NBe8Rk*!8}kf)lEFE=U5(UWUZp17brBI*PMi=edB`P;oyH8!8?Q zVnfAaL2Rga5{L~I&jGPBK;h58z)%R{KrO36Vow0Ep}wDq#9oBNUIAi5_3lApA4Ou{ z2C<>$JV9c=tw-W8`ZF+qPDcP`11==C0*DROtck=nLSoy4*ic8LAhAn9Y^aZGKx}i6 z=?n}F{tOJlps{EWw;Ln@RWuWcy&Q?X6~u;W-iO4#0%AiQcNdBM42k^-#D?l+4nQ5Kv7zFMNNjy1wg-p}HOCjkhMJ#<#Lfx=mH$wQ z29N~Q2c1alNl5G&AU0I}LL~Nf5F4uZ022Eo68k)e4b^)C#s-x???4===I=;shG0Z| zvw_%9&8kRjMJ zHZ(|=g4j^;4InmDd@G0z6+Z`JL&YzH*ii9%AT~t2p5ZZw1C{uQ#AXOV6cpSbHbeu1 z0Ei8BoC*?K7m4i*VncoJgTxL+Vkd&w)}ZibU|`4sb07s#1BeaP+=;}Vgv6c)VnZFV z2Z??1Ktncu#7;nBr-9f|_4!EbRuCJiw-1Ru9f>^` z#D?n4-H625g~UDrVncm=8pH;j;m5$ha6X)YK^V%u1rmpypY)S!AP7)5F4tw9Esh4#GVFXLk*gb#9o2KUI$`B&DoB` zJ_}+)^Sm}!4oCu;pvpmP(B%*e z3=GxL3=G0hb{j|>s%9dH4NZ*GKy0Y^5+wF|5F4sy3y2L>vk$}uovaF~8xDgwPz%l= zu^)lhP{+MSVt+wm{{^uj1~D+lFfcGe%~1fcp_ZwG*v{aj#h@L-zyO+k0P!3_;;_D% z8;Aqd5C~#JT^$BuL&Xz8Y^Zn|hz%7lL1H%{u_qw0=OM9If!I(7?W;%P97kf`1+k&N ze}=?76*aYP!H55fXaU;=LARs8g%DDY1 zhKffau~R{8sG2Ge8>*%Yi9IV3RQ^LHmVzXp8dibWQ1PuGHdK5Uhz%7#3SvXWPl4D_ z@v9&-$7#D{<074%BrEL2S^?LJSNHOOqKGgrV#WAaSUgeIPbe z{2~(jEr<^N9V*Mf!0-oT4wTKFf=G-)Aa(|{{1*ptpqfEfsKHhfsw0UTf!NTX zGY7Gu>H|P*sCX!d4Hb_Ev7;a%ngU`&9Z`YAZcJe?W?+O$Ob1Co^YH>C_DUr7RuJ2B zx|V{0T>U378)5-RDx$^{L}E)Jv6Vq=sDm^?Y^c4SNbDdab_R$Ibx$D@y9&aFB%B5i z2WrrKB=!m<_C63BYS3{c_5~#NT@V{;&NC$T9}pX=mo*LHNxn2t!3C921W7+bk#D=P=1hJvwEg&{jyc5KRicbcyK{p#RFfc3z zv7u^KfY?yStpP0w0l5@Z;%)^=Ks6r#v7s7{g4j^;3m`UB{5}%<35X3f^am1~F_VFT z5h^YYVnahz0m=rYKL$-G2NZZlAU4$179ciMb0iYG6^T6$iMs4gj&Cj)+8JC&AhE3=Fj(4peg= z5_=I6do>dKAcze$^b`{NG7|d^hz<4FBM=*E{%a)mUl7|9Y7kpC!k7F=YzYt>YLE(u z4NV97AhsVU!WbBgvl$qK{ieTDMXWIL14%=bW+AaFkl1ZV?1>;YG+9jpv7vewg4j^; zWgs?Gd@B-rKZp%F+meBSq5cSn19jI8B=$oj_ID5)>TiY|gugkF*!&i9^*S zfY=$(?qC{-1C_`Hu|d~2gJ#e{nxX6(B=J@x_G}Ov>d+-f?6pYj%^)_^oFgDMbYuFd zd{C}g2sc}VONNj&3b}$k<8i^f`#7;+I zXCtwTk=W%>HrW5jj%bETfO2m)61yLXJq?LH3yHl5iM}fq{X6V>;u<8u{q~Hx*c>FW6(C!gOcC^kaJr z{1_{yi|#e>XVjUVy4S#;>Bpq$+x8mxF)oPwCU6K8~8D*OnbkhR{{!CA%Pj5S5;Kyh&{ptY&f5wLCss};F&X`_y z(7=zeX8KVO_sh)bVuuX;7;UDf9y0J}Ix}nfHV`*sI_qHrf5r{dLqQbF^ravwV)|DQ zwPw2O5d(k59n+^C0ogrg`m-YjevDhDn;tdrXZkaDdfQP0KgNvdSC4`XP(5bg&*(6{ z6hy^LKMJB)ri&go@MrXyo(iHOrf&sNJkwcE82B^YSUf%Kgn=Jp$@HZs4Ez~Qrhf&A zzF0cl?WBPpW5V>QCk^}=PfULbq6DU!o-*)fda+`9+bIJ-#skx@o-*)f44AHZ+Q6SN zV|pownlt_AX#;(13$(Y(@oDC_%pUlZv{~T)31W4is`BsK&I}WUUmT-?nf^e z_%m*qE_%_xpV4A^Du~)MeJhCCF`e}iB>FCa;^fHmWtYIg^A#kTGTrqu*ygDqs$u%m z%Le{T7fwz$yJFzSm@>Wfih)0)!t|?GK=F2Ny4qC(KgKE3ORpOEGa5`kdKDC37p99{ zGw@@2a$$PfH3L6Jm+4!tfl~nMbpwCKnCYP)Dq{N5>!6srI{n*quo~AJ;NYJMqC}=Y z1yM7mo8C0=XWTQr^`?P8(}zdXuiZ58W6YVZdJC+y6hs9~KMJBGri@?;9*H>P_&GEipv zb7p$pBLg+ovlkc`dZr7$D;J)==8=H_BhU1`j||jVBi}MG+?f8bgG+e&pGO7)Oh?vE z=X-3R#%lPUf#C;4+~=`@0HeV4*vAIytePJg7+R-a^o<0mjzpzE2F)87rojf+*YRbDtQf^YXl6Vt63W zzyP{|iFJD6Cw^&0+39aVGAl|L88!$oFo3RVSTTL!At9ORwoeVT*bI$K%`6S3f0U6F zXEC!hH<(;-S%Xn!`^KjR>Vo2+ZSdgB9vN5|1*I7ncMye~FffUM)~>SzOENGpNrE=1vBZLy zQlRUtm^oOr+8eIv#&7h-tybz`&vey5NGvpPhk$MHzIT9m^&j z1_lHTkwrKAic7#LWb7&|};PYWF0kKC^0Ub z{^^H7oM9Sh53WEB=%h)3P$dQiCV^d?3=GTyY%&ZCECSy_K4oCpCB(qMs+P^fz`(*e zz451knCBcm1_m}gZO~o0LZ#dc3~c%!HjB`61_lN;14Cv81`eTo5s-sHm+W%+1FffP+HBEo;(?Go5L70Jo&Fm#;cRT|p%O)lU22PgcAnVk{7#P^h zK?1@&Y&M{alZA>D85r1X7l9fJLZIVp+3Y}U7NIDRb@rf3;yD;t9F!Os*c_ag85mgR z^Dr>5cY)025@8o$Jj~3%zWLzI6T2IIzya+fg|xLNFT_+uOQFQW?*1&U|?A# z#K6GO1QKOo=3-#rXys;MVBiJaEz1W|#=v4G%fP_VGyUr?15vSa5)2F+lMfg_S>10w?i2X_)T0|Q4CST8rXIuio}M>Lqj z!>uRDz`zj$=J0YWfC40z33TZ=AGetp0|Q4K*ct)uFVY}&@n9E8aMyvHm&g>t#K0iQ z?L0mIkAYhKECB`vj#RKgvJC8?L~@Ijfq?@Qo{S7^)7cpqIMSK8SQ!|&GB|RX?ARC> zxKD$^FpmkOj)D6-8v_GJ0oVcsZqTXR93^0HDRJKhwJu7TZZR`3sBnW0c;+YrTa(KD z0c2`9m{Xs|z$OM#SjF@VWC;^T9aA325>SfasAoD4O7YzJAU`#LH83);odJbSBa;^! z0|VPJQ2Dlysf~?+fp;1k0|OtJh+<>_rD%`~xi~mZF`WgO=*`E#z;POE2m|*Vkh9M) zy#%$586h!n77_ytY>J?yc8&?8gl#Rzd=6$%T(kWH#RexcDAKqjI7FGl*clkO1wf7$ zW4;MGh>lwlq*|QWkCB0ag?l?FT}m*6UCV6=l96Qo!pOkD!(9vFNHK$4SuemnA7p|I z*jN$nBcLdfWtL!KU=U+qn*d5_^2{IE7#O&CIFy(dz-?4UwowIYBiJN0ut^*clhnZ` zaWSyn0(oAOIfalcpp;++_9`RyV-Uvz%wb|+16>@#VadD( zq??DshFP5h=5t%9X0XrgpzdG;B@lbCW)5y}useV`oD6KUKndTG`6W98gNOu&Gjn|< z2LppBI1pXHMu~=ival;Sa7C>^nad6AZP89pSh#~7E_zFbfq}yV>pBhw1~E{CUgKb3m_8}ZMsm7u znhm>P7bu9NSs%fq8KxVi*$7X!|7Of4*ulfVz@f~_!wJ=@50aBHVPJ~{lNE>HnA5$v#FZc9-3OagO47}$P-a@J&4 zZ!QJ~E-#L0tnAz{Urk4L%M7qv>Ya%md6AL0Q9wtb+GJivMhq}!Y02rKA<5=crr zimdw>R5w`jafoJc{myX$>^d(7woFjragvpvhk=2Mo#PB^E!-Vvp(afSMSJ}@a8$D~ zut|Y(=6Tjg9tH-H2#$-a+`J47qT504xdcw|qQRgrybMmHqFSILMi5>)%G*`h9 zC29o9zt_M~E(*GllH)o!s6~%~0`~?u6h$9`QrJy!z=%56gA(p7us=n?4!R9?DFd4= zNXH%4P96pZHY<>+4_TFYp*i22mw|z=3Y619ECx;%kXzY0Kvl*QR!?3A2HrT33Q*SO z17&P5!N7JJRARkh%>pTCfhw4u%3>%~FAnm;XVwWI8PJU^eBdZ%TPw}Lz`@1_GJByGL$H2fP z!QsO8734zDHIE#wY@ot~fg5xMD~B7{5*CO_?qJO#3~Z-BMtQIu0coxm;qYd&=ZCq< z2dsgCCnd9tfx{Q<4grYOeqh}~5TpFT9AO5wdIsgEafkPnf zfS42tHVNvEFtBDehzsk(!8Wopu&o3YYY}YTAfv=NqS%gs9FHt-$O3Bg zvGFj0Ldsi#fq^5I4O9mRGO!&5Wso?wsr(EKA~GBaY!U(t459^~w2}x8b5ReFpOe7h zBnoO>a3q5*5UrO4HO5lFK_Ge=lonILo?u{m3-U!8+a-{DI5;xcJOmgRxOan$%mk+s z25xy!U66r+C$orwqXiO#JmBzb1#<*=QZlj`>N(oLJOu_e z6;LJ9!FC$P_LGj+ty%1Q{5(n?MEMEHIman_C=I3D0J`1?n|(dx46h zIc%Uyb2zv~K}FD9wr3#sa~}o8#5}e)f}nT@9cRojpY4+%1A_=R=!OuEMQlF=85ktE z)j-Zz!uC&)fkB3WlVuSHs0|Eip068TwENN*@}f27IV{{iK~Z-d%wgm90;RMYY%-w2o`LNsD7tU5IctD=sxv^*dXKGJh=GB3sSvCg zB>-Z9iUM$eGO&CB4Otk2ibNLBWgna#VCGBS=^Ho=C4~8fp&d<5c5v5{fm>(#ZB9c; z7f`2?lMB|V1Z7oDZpMp3AdiFea0zf$FoH%JxC4b57&t4Tnr}-mFmP6ZIgH#b(=E6R z9T@jcujDdRt5+6bVBl;9OYw21$TBc+wtzYO3~WV`3=EvDjEcex4D2A+JqDGs(9YCr zQ3eK1NpMS;4RjbRrzi7oVFm^@kVBpFIso@Y>2fa#8OT;S2A0d9ZdESGeBm2h^&3PP z7=+3}>Kh=2wt%YpMi84x$Yy#ux1qJ|PB{h!u6B@+fJ9$=Y3NtWp%>kLYMd%dBvvUf3_^XNfL+DI1UmFj$X<+rfonCWd}b7SEW^OSwFbmy z7pk1D$ZIHD57HnYbPMFc4OL>G?oa^(*G7 zpN$ce_*l5LL2iNMJ`V2Bpk%}W&KR5woGc*EvvGhFa5DZDW2k4~;^g9H>;xGI8ja%O zVFV=+2JRq`HeN7?5#0Rb;$sBqW#aw^id=rMfgB8MZVU_zTmp>V;tULIS3pTg94sSw zhmlK;5p)R=w-zY=<-wv1+@RqrE)_;lw6kzO1lz9;R(6Nm6_kE87`Y`G7#?t+0%_7@ z1cm(*sWy=3bQnRIn1xXa)ZgdQWdt=ZI2fhGK*>=L%;RB{+5`$GeMZoQM*@se#R?1z zTt;AsAi)|&skNXa;m#;7$-q#{C>5#* z>OC=j5MyAt!6>yGltR53FAFm;++t+lWT|2U6`Y`^2q(*XP%#IJLUmBx0m@CB3~Uu3 zxA-tF6lY*y*#&Ad=-Np#FtD#?U|{frDRW?uc46f9tFM(}U=Y#)wVC`uX^cV09yC%D z0Ae!s!g`D7VoCNnZHa7TgCx*DU*bx`Lz z8pKg&lyR8;P{2@jsIN2welI?*)ll2(^Lw+I=AL2%!d11_o}s z2_T6Wp?@IGM36*{5I-*i1NUT*c!Q87NW&D6_yQpx5PKR(e2GwlGy?cLE;jOGN8^S_fk;2$S}$* z2GzzZK{5)AGG9U71s8uRj52RQP4)FTj0_A~j546+757F^GtG!mW)>&{H_ZT*-bsuy zpl&|*K2V>gh*1VK8o<3DG?G!wDDxfEpF996E=oWtl7WSRfn7p|fdPcUq0Yp>$pRYm zWhn!B{qQ^~1_ogs?kirPp#RUrz`%VKl!+OHK;tOfH$kb2g@J_?6a=?4Wf<5PgiE;Z z%$n{aY$#KI2oy+k{T#$DWMI(+DS8s|oD_1=n8?TVwij zVMAUiZaD@9?*AYG9quO}XEK1t%k{WLrt^syD%3BPVPG)f-YUz$z|9ISEKRvLfie;o zxU{h5o(KvC9&ia~!wotkk((D>_Bn8W1Ih4#Wn8$$Kq-qKEaSl)1B!kDu#6A)I*^M5 z!G&D_H>kqp76BKLA>4cd3=F>9qKqJqmT-gWZf-HK<0`m8l{dFIm{Y|a1_}cS##%WB zh8ih0P#j1yeqv!@_`@gl5R|o~7(v6n?EF&w(|?H=O4pl!Y?K4LpO0VaKd7336y^N< zQbi!1BDk~@;Fkhb^W0iso*=(eyBGrlw>Fq3#4jZRN>MssQ-t{$I9Wg`fPIz>14A#U zI|Rz6@(gSqAfFmAZjfPMV0#a8iz8#4Ca73;;9krq4s!PiP?B8&_C5pm8xaNu?xkQ3 z3-@Er=?|WmNld>gYA99j0vf1U2i79Uy&1$=59X*tnjGq&UNy*0Q3f_f&3+ z+*+Vg|0392K5kx6gj@o1__=q267LnTG6C)$P%5|ymJtJYEV=J8f(9VOxz~Y$_#QY= zBpBGZK!x7}#{cpR3~Uu3(_Vx0)H6t0FmiunoTS9Sz|9RB&i({uGjLmiLjE)33?1oxDJoM?VGK&-oGdft7$B2L>p-JHpfu0Kz_uF{`Y}w4L5-tO?sO(0 zWd;WDa4>f!lQC$|8+RippJgk7UF68k3Gz}7*dizHJ)k6!%d~`%fx(&k{`A+9hKl~X zK$DJZL3%2|s<@1}XE4nHnR*yhtIq_p8Mu`}PMpOA>bJ^q-v*g88yrp=+`6DRn+xV> zaVt)bmNJyA2Nx#`ndFoi7!0`Af{N5dVD}g@u!BrkqYRxLV`5;71J!YhnY5G{7`QmN zmoeP|S*;8z;Fp8h4BV?h@wEc%IM4`5J*cm111fG-GVM@iU|?$pMbr_nyrhZ>_h%+s zHFX9Cp5(N22JSE50Ak>N2a1@VOt$I_3}I63pvJ^6CXeZo(uPX)4?rRGkLf8J1A`lj z)J72RKa;OI1A_;PR17F`S(t;>85n$6qgoJSTc@73N&2DEe2ia4ZZf#hVt`bs#YK)1$n zD>H-2=L!zl#DYu)ZhdAJAqIvXajDawYSxIkSe=1kjkpxMPzVD9w+VBnIs?NNaj7;? zESoZeYSta%QehycnK6T^`5WR=oS+134(8nvmwFA#Hx^*t197QRP=c@oJM@XT)L;JT zy)uSU$#+3cv|$F-@6W}hUVx&}7R-AgE;Shx?RH?^OL3`UkfR*I`d^7lfzzxjnD<&- z3Y=)&m_dp5jkpx(?oQ{DHI%Ne1_iel*x4)+Qq3U8c!R@2MM5eK zRKogz4O5elVg^NpFLS>-1A~Ty)J#yS@ME42;z>!_f>io5gUZ4e%2M*6(kFmuH5C-1kzn3mWhpsOh(s}ix-<+bQp-T$8x5A@QIUEA@=^?#$EzZh z1+pO)tWrQl>L6P^0|R#g^Hy~R1{oCwc2MIPlzichxK<7Z26j-E10`IjDElL21_n?X zfbpBv85lqq%m~xaV+GB=gBFQ|fbL-ip8+}vw32p?sTKnRC_oHB3{WP61c))n0=S84pmT*m zZah4FqJp8O(qoYCKpXqtn=vpv&}3jxXN+PhVqj1MZ8!P_y3k|#9R))fZm?@0{sX&a zx`d*kSWpP)V*A&i3<>gD8`v3w+7M^F206o$5$4agAZI9oMo1ao?E$T-m>7U?lm;|- zH)=r)pQ>mm%*txcz;I#uT17)CNa&V86|rkiKd5CQHvNsFp%Bv_jcH1TlJ#CX3=Ddv zp!oLzHxYUm85s1z;Ty;Zve*DLp}`o$2(j705VYJpN{4{~5}2S9Q5m)|FfjboW?(RA zMo`?Sg0|U!LP8A^5)2GSw80@ZolV+AVEPIrLt!=na|VVN z+S3mz8OkYGYk_5%Cb}>%sA@4VFo5-fj!po@fP)Uivm(ld%ISYVK>+TLgPaA<2@(uO zAa5DVg8~`6Wuy!oz@Y2rObQqnBR~nCF$faN(I8(cf}I`%THV7m(E&4f&+AMVlrI&V zzD3zk2<*_$I@8Z68_KDJlA|^#d_fFQ3Yh4?z+kKm$~Tpum<6rqVw}@5T~Gy<)IrV# zc_K}BdZ3}T*mQ3dL!nd|a|VVgU5KBH7#LJR2fBewWH1f^rGL=ME(Xy42gW%fdJGJv z;7qy+G|t8t1oF@(P=k;$7?LlxfINihh0nT>K)bGDC|nP+k4q11A0#3fR6)BwE`kpH zHUr-l4(V)xyZ}0PmT}HBJq89naEx++WAq0j1A}=o7Xt$$7kIdgG1%a^A_D^>54df~ zG%-L8T;+oN1+j;zh(Vn(nrUKyI%5ncqZxxXC|Wh97pWTR7_Zi6V6Z4ENMvA?2O9=j z9Apl*Odf0*W3XjW2?L`dxa+fqiGjgDXZl4|Lq*x$`mmI!3Oe-st1KBDDH~EE(Dcl;PeDC9GsrS z8H_+Kw3-OIF&fl9W?+Ei*m45~26ND8C}R!S-Hbuz;Har#1dWF>23r&`FxG%u>o=HS z*{Tklt&rn~oq+-5Ugzn8>V}%$8s-cPF$SQhi3SH*45Jx?Y6j>kBy9!;%@zibOcbL5 zC@ewg&a41*^YQ|4Fo9yL7M#-E4H+2p=1p%^H`Mk6hvO2kg4xUr4B#9bZU_rEHBb=_ zDlqYw1_s6h;P6?;%)nr-2ud^%K4Y-?G>9yyBxDRR0K4@t z*sYAAV3&e!LxUtyHPCf+pb)=o2o3{KVXF#qJ;-%xpo|6zMbKHz>Wop0hU$#b)48Qh zxTn9fFoGCR%D|uoYQ})#-wQ4V@jZif0RsaAC^A4P0~8w3 z%%y7>)fqv70vZ1UISuSDiiwl1#sirnhMtD#n5R@dWG-YZe9uH68{A1`l%v zh8s{@K=lNuJ^`8k5iSNXTotq}3*=q~s|&&m42*w3%fA?Af!0UN={99x(5s%#s%0q8 zxOBRzmZ7{mIM*>kR(nkhuzm|F^EjA5g{}!JG`44(!eZO{t^flAqcqb3QwD}0Rt5%m zCS5nZTgy;N66D51#*okfxe-+2g53CM`aUf~X-I9-0If|VO+aZuboyT{Lt%)_I;czn zR7O_cT5P(Pwjr-Yh&cm8r3u8`QU!I!XhtIjwNnfX3?PZg5D7@|f@MBHgMQ2Oer-b; zR*(y>Oy8hwD9r|9eleMTQ5#mb1u#N#kG3hqHT*h;!jL)_H1GgPucFhPbPOHrK*0cx zFC7LWP(X6BfLds_Q$Xp_feDm(`oWoJq8S5&o;N66IxvA+G{vk840=Y>59k<*Sb+lW z94i9@q_A^^1-lyP9!Zd2gv=nG1Sc4fCqZXKg0h$4bUs}}DX>=pr|aq(N`sk2(|vUf zW$Hn(t=$XtG%US=6PleTsNa8rX^9yF1KWQvFtTH0V6YPd&F`FK+5-{?Ih}z4EN-s= z8ivSW1~va2K$EW^%QkD)2^bc2U(^4s_N8w#s18ccuq z(?*2J%yN37pM(gLnFW+Ko1Vy0Cdy=HH2q_dz_IBU7#ZcJ|8s9tn11i5pulv$Jp}^W z{YnjYvof1mFibyKXeenOAD>p5mmD9jVqs=x#DK)JFh%BBBJ<1*ET5}semAw`s32j4SA4XzdKw{rRVt+!pR1AB?MUp&(-XO)#Cf+M2_2l?xWG_f@*9#6HzE2@rN(!MZebcwF?cE8H1)@TxclHSUjC^rGPkN z-*nrR0^*X#k@Va_V!xbjxX4gkk_A*wL!Bgv#8#W0xX4hs-VaGA8Hrth#I8ePPex*c zmaM~ExEe_uv~C3^ei%voJQDjhgbi9q%)sy*!T}dApOM)Ak=Q)Eh@g=`V%s6H=j7tExe#k9W-!GB1v4EK6A05wWI_e!cJWzw$=2viw%_}laPd3kk}KaYc4TV z4&8|)bPkDq8;Sh_iTw?UtqN+5Lmg&>#CDj@xJE#{J|9V_28rE;#9o8M-igFMj>Nu$ z#D0Oq{({720M+DBr|>}7kXVz1aKN#qhs3rXMVy{JF za|nViaf7-@7F2yg*`V1jm}QPg;yFm{%IP1M8U}l^3L#=v5Q!~|#P&gAgN8R@MyDZ( zmrUSE0EYNNbCs^HYD2TKsexNUxCElg2X<6#0HII z!Gi7sk~nBm04B~MitvC45?cX@ts`2GP-KB50h(=r85Dpd9)rZrKw_65u|c!HFugrU z;xmxgOJHn}{|~}A3=9lskl4?W*j%7tA81sHA+bRluwa(yA&FZdvE7i^K}hTjG0-_b zP(vG$B&Hy-7a+0MAhCBKv5z9LFCejRBe9<$u|Fc%d2 zgkwnTOGxZ{NbFZg>~BbH(0VyoZ1I71MnXL%jl|YKVw=iNk6UlJss1OD7&~ZC2dYmL ziLH#pHbi3EBe8vv*wIMrOe8jFJ`3i?SrBm{u*cU!IAHdk=?ga)it|2368bRx=mtY& zNey{KqV+;zhfinRXlOm%W1}Gt*F z_Btf??&-Rl41e?91Pw1jl|Gwpy4f&$`kKv#JceaT2*LP7%h*))7KwcuiTx6Z z{T+$Ts*dm(=w?t@C@La}>m#v`A+axk*`V+TjqHIqppBsn3=DVF85o42?DrsX(5wan z1H%^(8=6P|Be8ij5ROm+v7zeKL2RgcQxF?!rlkhNe9)AmPd!Kisv!`>hH8igv7zFL zAU0HU781Jw#D*S=)QQBNgv6c!Vng+=Lt<}-vcdj83*tZxx`xEQkHmfoVnYr33t~eZ z%B;!209qmi%De2E3=F~?AQl6I5J()VMiz;!4q`(+rlZLq4cBZ6l7MP<2eDbFM^)s@ z)hB@1P=nGyZ0KoGSs=@x>{^gG)X*jn8>+q+#D=PwhQwY2VnaQ=6^XqMiG2jb=7JuH zbr!+_d+i|-n@I~aNdy*V;6`H0g4j?C)R5TvNNgJr8|qLu5F0d*4mu883$z9jVrHxs zsDOg{ED59tsv#GNT@7MGHMbzKXMxyIM=VBSuR&sO0wv_eYRo}ws3&beY^b=0Hc|lZc>I*MitkPi{l7)fo08I1EQYY^dg! zNbFzJAMQ33ub0$81c(w6TN{aO0%Akm?g(N-jY|Nrq3%rsu|ZQppnGd{7#Ki%mq0<- z01}6)=|*DD1hEC7X>}2V15(eh1H^`U>L3#P6cYOahz+&u3ljS;5}QvKQO1dY*pL<# zgM=<HL)9EZV&4I=S)n2H6v6>J`yCSd3y2NX%&N!0zz8kxxIt{FxG0DX zwO9ef76BW>prXgXAPi;egT$d~tUzpN+P2pNt3A4(NPpBsQBq1N=^RZV(%4fd~>? z3&e&-pD_~K28rzoVuO}0GcYiCgV<1W%Jf0G8OoW8BykYL2DuJ&w=;+hT8IN0>(FOl z5Qeg^gT$d~o+7dTfY?x9G8!NfDKCf()hmWz*E8sVI8Yy$BC+j|*e)P8RC6p6I}M3l z0b)ZP)C^)vK%%DIfPq06%AN!ghpL$iVrziHpMim45r_ko*a>1oeXtM2hKipAv7zGU zKy0Y^4G10z&i0>p-TSkV!QqlLsa2C<=r#)8;T%Q8T0 zDTvQ<3>g@NrKaCIU?>i1wSWZMLDEpAQ<2zBW`zjLqD-!!35?jO+ z;Y3*^wi*(>wm|F%r85 zi9N{-DOs%oNkA<)gv36F#J+^YzKO)Xi^P6{#D0Oq{(!{(0%LBX|?m);xt@qSp&zyMn70&<7t^u$n2>FFLH z3^jNktYBa`!@$4*61SfIP~1;?`iu{T8jNeEAN*kG&v;(4viw5E88apHfSdVN1orx*?*-)8r<#fl-hU%4pa+L_i02 zfY&mCW0!%!WV+&4Lv_|OKNuJeOy3xgBRoCftDyknmg$9G4b>TYrq2XXKGP3^D4FRm zLDZhD}2B72ixZubCol$`w|Myab!GVDZcK+Xg9R|?(f1H}2ga24p%YZ2MXA;o!|JXsN z12S@alV@OHsS{^lfS&)iefn#0BLyDNurKudzj@QeC5#j_LFWlTPx<5KhoAB%q>gmT z-)+$0ednepNEqody-}JDKHo1}3v|Ap*7#237_Z z0cp??fuKc_EZHgy3~cIWnLrmavoJ6yu<6cVW?&H61UjEj55!~;`3*WdLm$Lu5orhc z*kB&$oDPvSvhX7VMf#;6M+OQqFbIf%4sv9JoEa!$GJTG%rXZFi1M)6+yUABSRa07pvX1QE*;33fg;mE_QB2!1T|#Y9M*%3s1Smk87RmC zD(E>3Ygrf=gu+3qYlWIXZBU`4yP}|=c*+V2idxW#8A1^<3=FJ7%%ThoY(o8vpfd$m zfR6AG`lH3bz$x@smVtpwXd`IrhLAMqEES>SObiUXLaWpm82E&?$uThS3xzT>FbD{_ z=`k<}3VoKGK2zFAhEaa{HfbY0CJy203;tM%>#o#dVBjcR%mT_G((uy-H9-efw0>k^ zVBr75!oVPK8+0-zi{ErD86&BBK^4%!f}jZDWVyh?z#s?HUO>5q9K^W%)mAgbYO-N6DXv(KnE`_ z0_}P^HhsISk(EX?=+GhP!HawcK#>7Gc#*FWv?~jG@FL&p>5_6rYPR`m@Pik5KnE{^ zR&epT86XZ`o z_%47PRR-Qomdck0G8J*iBIvjTjw+^KAWJ}pEH;5GQ3GvOuV(_~H3q&wknRSsZbk;S zt)Nub$P@=URSz_3!Lg8O76$_Z|0)g!1_3YuTIk8Z$pUgA4+qC7riUOCLqI2wKo42u zdj&et26o6IB(&j&EP{`JImfgCWd0Rh1_lo3A&aL$N83RTS>yp7vIyER#0MJG<`83k z3mVAfJEp_HzyUpEkxw3U=8XjN9Z)dvfp#l!NHVi9F);A(1%eEff*!KSrw&p8*>Wbr z#}0~CS>{$I@F9!uKxcxLkV6*v1hyel&(aJfH&GLjoJ$lKh{L1Ezzb~yJZP4FR$AZIYJb%Tj0|Ogq zApwUU^HMGb2L26P3=9Gwf`O9-WDDC1kja9qpl$Qwpk45AhWfIU>_(; zo3R$a)b>r^qhusk4?RNB4Wt2jgyKAqd!a`t-UB76QdW>_ctA%ea`G@R@XZAsMFBlR zk#89&vsJOq0-e9drvu98)vTMi85r34^g+c@4eK&cX5w1{I@$<+gyJ=j6?Lrpxa%1h zctA%e2E)yT9-#;^w;9>o7G!f?rS6#4dn+zUNIk#8?3ef5Ja3FKn{Id=k>6U4^_I+tl8 z*kQqZlAsuv1m=V=u*K;yFmOy}jR&~}bcCWb=(IX;XhDxqgt%n}!Y%a-95W$~VPF#i z**}Z*6-YPe2*p&mZs-w;5Z&_;x*0eYKs56if=W5~5sH^V)xsiHbzTMrwl|=Fha92E z13E%+A>35Z35uWr5WXN)1_q9etc4)u3~ZotdpS0-*77ni@PLj`yamz#F739lf=fGI z@DYlj<^m%x_y|Q1Q;>np3{*7iWCa~>!~;4)5p=vBB(3a)99;-;|2|~**YAgTfPw8W zC?pTCJ_A_`Izkb2ZXQH8^aw?W?qkThk3%%`fn9e3>^d(7wr!wt;v_5R+&mu85sDM} zU}+Y5gd!j4RBw)Rpc5498Q2)u5<&UyJS+G>JkSw}@}TXo6F}~{#0pCA+!H`yc$pQH zNV)s;85lUOu!52qw-PArUu6YF6t_Moi(X>|MLG9-P#t}p6%^Fm)u6z=!3qjRZqPw6 z95-1(0mBVCSAyeKJuAqc++YXYW(B#Ffo(o09PhBs1sz-M3^Mg0D`;OLIOBs(xD)8( zW?&Eiu^2d6KyGCNA9VVJHI|=&fxn2Kfk6ONzX*UbEtp_ndkiX%-munz6oAePgD7Za zVyI^j0PW@y07onvXfllBGwTwNvh^TyAi^x5I+_i9iW!>@Ou*9%!+FmYy>4odM+{ZMJ%lBboUaKt~elu)FadW_hsP z0O=Ot@Ma4JorDK=ln+<~126J=QV!~ldgy_Q5GRI%ZDeO)^8&?A1Y11FDA0L|pi}mE!RP-)gOxDwtpTNj7`95# zd5U~XLFHa7>^wyyQ0k9kTPeuEzy&%_Q3rI?Lpms}B(j0Rock*%+a$4p!l|Acv>TWs z8GMc(H|R(njudbZa7Tj_rGh=dz_uN9dSe>oNI%ediZP(m?f!v`%mk+s20lelp5D%0V==?I#7|L4a`wsVB-bVI2~-SK__Z~&QtUN?Go<- z9SG6Q1~Nzja-JgCAhso-25~Q&I_O~fSWvrh5?g{W0|S47Fara)01yDN7&uu#rtpBy zQ+y%Jz`*wzbj=&bEH)5_f$tBf2|JtZoiGCf3*QV-r80ggPMl% zpqQA)#vsDLAiy^fRJG4%V-sOu5a9zINx`v*jYoumL4pr-5;VsWHX#wnd5YV(Ks{bi zdxn!mgd4<80h2T8`9U0QFnK@-#0~-ZVh<=EE@LYL9q|Y00B&K60iEe*0~)*)@&K*U z7t)mibpW4ggF1j88A1Jf20l;+@Ea=ws8l})@(}bK#x0=o1#%7}59l1m{UQtuyr6R! z>tP2m@**F^$X5btAVLpflisOa!tRYW2EMi06JR{ zde9lxai0xe15j0E>&*j7xp(=}4AUkW;x z5pv8u8>rXLnFl`ggUuOqCSwtVeSwF8fwK(4UI`MffEZz^4RS4ny+|75ScsZrMg|7X zYKZs_&~chIU~wKH&N?O`aRvrH(7_s<^-OA@)8-iXKqvKZHZU29F)%Rkg$gn-a5gg8 zfezv0iw9ZO#N-9Kdx7t;6zFhCFo&Hl0p#o!rZCWPoP57_PVG#2Vhjv?e4y!n&JHHfUS|OYHjoXRogz$aVz6-t&Tb|8|xRA69WW?56zg0|Wm%kP5Jo zVADVbK`L`D0nSxSGNAJ-lGPa)I9G$imwP%$?;0jhn&Z9-ijTESper~S*tUUAJYB~G zGLA=qa|2TvXjJ5?J_7^iMlhR!uLq=J6H_kestZ0jIR*w!!a2^E9@G!7BgYw7`rgb1=c{q@0%3!e7;|1_at58S!`1=Hqt}@HB^elaN;q#Y2}v<9@ZAQv(LM92BCr>cKJ`e5XK3^EQ)`6a#|>U%v(e1Lqwk3n>N$556jpH}8TqW$=MoZJhVO ziKT!q2jsx}U``OwmAXmQzyM~>Ctq61g$Qz~*DFz0f z4$gN>FF~3wgTnAVRI@24fqnqHk&*8ss2u+YR>i`{4?1M_Q$0AWIruJv0{Ao2dnr&= z0Xlo1^9vKmogxgJEFdRwvMdLs_lfch44hw?CW3}g_k-BbV_y3~&hliIlxAQM2W{Ba zm4-EJK?N&=s18>~nluB02xyBF7vz{%5p^vF2CkSakOCGF1<=_-*&sC>BJV-{dE{eW z%RoJMP=LuXu#|8xFmUC9%on}ERew%~fkEUbNPPpS+-4Br0yShH$GnP6oBqt zk9ieQ1RZQU6XdlPky;T32CiA`q6`chMCO8yv77@kbBjne$g|L6UPUf}PQrv7^C~h& ziGhI&`IuMG@^f%Xvt?i@26<*dqcj5p3+M<*t|eb&7#R3jWEr6S2T&)1fu#&|$;C3z zS-br5ASuu>ui*X#gQyMH%1N>e3?g?x0lTV_3Dofvu>l=t1v%zbE~i#;93tdM?geUkAZ<}!wis_lJL`CMdpAGh1&%3Dd_aqm!N{4 z1>{N=9gy*xL9P;g| zRUdm-$}%vp_<{~CJp-yeS;|0%^g>R5y*Az3)JRe{T#kW(&jb`ntc)Nw1K%TQ&`mku zsSXxC4UoOiqh9$IOrL0KBy7M6660i)lmiWjaB(v(2N?m%v#`Tm`Tm1k0zKT7Z|?Lf zrbdb~nQ{yaYzslD1ag9_6!-*JWd#NXzQ*Z-W=6vGph#rldkqR`bw-fH9llslCedKj zRA69uzz5ol!KKLv3b7~Bpj{7KI*g2kxz zo!Khw2a0JY#vif_3?+=ymCTLA>Ot%pM(J8m^tm&dDu9k^m0qt8KB|>Z4s=wj^e<30 z@@Bjx3O%Z|4^-Q+h_iy4q`cA$4D6r?aRoIgL4^h<0~`2MWFN-;atsVC?4Wu>H%0+^ z8d45SnFE6i=%`k<*@~b8$EWW#HxicwjiN(OW)(T313#Hnq;UFMb0hIg&;n}ML9DW% z4d2|*gIHx7wHX+=p$D-URBZB{9l^Mi067fksD) z7-d0&jNJP{1Ej@_vX?=% zlA+ANAaW9P0T<+CR*|`qph$%s&6*Dif?Mv&3=EO1y`NWlUYSBff5JwWY$P)BVH-c`d;YCtbEoQ3=G`RlUex|OmDC@Qm8+y z%)ns6Ck9IP(34sDSV4pFki&wk`I&8oy^Jys&8Q@ zv+`+y!a#y?wkiWdjdV3Aq$L^I*g+?=N(X_?36x?4%@wipOW&KGV`C&;{|n?zIq<G^2vRM`mkm1baXpv=J(SfIH0A=bPLzSI9(1VPMn=%C7#`4} ztb*zckP!~;zWu06OdhR`38i_b*0J!KKEh2TBvr16cXQKqUtB09L*?Am2g{VCC}! z70UwPNm3iWM1a}vv^F0L>O=@7y z3_h>vf9;Lb>c4@k&;pCi<1NlLVc<3cYn>0CP~kRb0u_)8!1FHL7EGW5av@(XsQiYW z-^wQpifQQit$Z6n!2~_Om9Nx*fq@%(ek*uFncEROp}d@L8OZhE^IPi~R`7w&q~L}g z;L4W>Dha%pKxZkg;)R~y3Q8Jlr0;;@!;k5aECYiMqcj^R=fTczmHrC~cBJ!LLHU7` zWxFc${MIv|L3dF0U}9if3yQoLrh}jbLZRF?=}ZP%3=H7ODDF%q(Cje-Ul%ChXM@AU zk#8x813kZ$PZJcJxlCI?=eP3NO^>y^QG>$nImHqf(cH*$jN_pydaM16)sw zFfgzggG!~9OxLs+7}$hCF$FomRSJB7YqXjk0|PJg09Q}|G4Qd0mTUZEiq>Ob2$Qx1 zH64C2rA_a4GE%Bf2c^t^OrUF0+*qUyK)nA<*?OP@T&16ZN+TBLLOsv{uF~8f9xHRB z9_Rp9>C+%;PBk4v;B4%r>CiAgt2AKnHFLF@sut6>QQ5pt4&8Jb4|$ zAze}r3VYZAuF{~n0&ds=uF|0S0r&x~(kh?=LxLGJdY8l@y$aOkgUqHEaY#FW1ay`%iuF{}EE^bq1 zPzAh0Tsj`)G}r;I(ixx>3_HM8+5(hUUcax*KnlrDH%&f*sB({SK5;f|)^u+c#xt32^kl4ri5K11f~Wz)J^yDNDD4jDa1_ zDqReU0@&fK(x6)qxg)_xuKrb)J_RZyqnJT`7X}sS#h^k5b~vkaASmU)4ri6t0)=ZV zSfzl9v3gty~naxpNlgR&DSQ9?!88MGM~K=BLXFVtgT0AVnn zk%5!N88q0!0xDP7L1hgnjKFg24D295P`E((oUtr{{Lt>mW6` zhF)(52K8J928J2l(*^yF#HM>0Xz)(|=4K=()(tuUrwe2uXiR}|4rp74(yr-R?ncV? zAU0!&$`R0rYj+*UWl*cSTR3=D@rR@K0)S^%+XqrZme^o8z5@`fNsbFzS3 z%gF+ACMOHXeVRI;o!iSm?Oc!pOu#-qVZgwkv~c=IcO$ua&=KH_7hv+BQvey~Fc>m0 zDCZ}qF+e1;85tO~7lL*qUIM8Dop8#aqX{~7DuWR;mIg8yw48)-PLd%5gD!Yyb_OG8 zxRslUfk7{mfiVl*fYAY+;rJL7j@e*+j3Meuph1(x-k`p66jKqS24gf+38Mz&j6faG zfrX6CV5J}{K<832&Ups10<-{uu^Bw}0J>WdWJN33iaBsA+Q9l4LkvLc-a$5;G6dTK zISUbFQ7MB4W6X43Pa_WJbx;?8gg~c8!dzeuin&?fW+})8phUwsXNeI5gKh)p2&Y+K zPhMtXV9+(69^q*us}A_N6IkV25FhNmCh$17BntzBu`cNRk!G+wW2hn6nXTX<&Hxq$2E*yWUPdC~ z@AViM)IiI~L220llvHMTGcY7gFPv2+Hhqehkz@cUVU!tz!;z_kfx!Tjfk1KI1ruXr zFxbMtzyOM*B``6Nmzatf7}P*lZG(+wU<73o28Ndqqu=17w0oCoGr1uvT08^M47#QbhS}-su6-qHMF#c6yWnj3^!oZ-dHoeo^NT$946k!bD zq|n34z@QHfCJ3KtVt`>NXeSpVc=avlU^)|U8fOA4XPOvj2o6LD7j(sk;Wp4w8_Zy7 z&_YFhaOnWyGffQA2aSz0vM_?O9Mi-Q{eBGw8wN&J@KrZV6C?D&g#;TTC>JtKj4?gN zz`$T>0Xs-i4Ro#{$h!uhg`S{r_M4vIV`Rw+DvcVZU+^)~;4-0LPc;eGBCt~6q-XcCqczlg2cq8 zpYb))kN_11YEu{?C78i3s0tQyNCYVQ8R>x&s^;_%KO+SdP~rz2atX>nWuOcMO02P< z=r#Dj$iM)S&YnKQ&q$6R>huTxM$Vp}EI?%x=rrzIjG)s{K}Yd1 z7=RATKH$y3AO=#+7{$yL{#S!BhH0XM24gIw2w_m02rG-1fa7F(qK}bSG&3kF;74V1 zvVbORI9Wi`GddZdqVEUXE1>gx8RvY2d*uh%E1;2kW3X3#g1y2RtPA$YFGjEFcLR*% zI}Qd0Nb39tPMx4*|I|TSRF+Ja3^bCjKLt9JM+CBxlYxN&R7Nt+*5N86-r~U@vFSa*MiQ)`B-Ju~Ww4PN zq^tv7zCObnV*UGIBS8Vs+#M$iXm$>KVc?bN0wG2UwpVRoQFjO&b<=raQFj;|b)flX zNHRGBj=Gz?p!5wo9_|>^)#iZr9RMZ;0jw<=-vc}A?SJx z25_MSa_hqBCqj%=Aa3me2N%SxJfTJ+^-pb~N91!d=(vJTX8H_IaYoFbf?C57=Iqa4 zXPfcEoc#st>=Y2+9CUWtS8xhz1@XbD{TtXD%Rqc^iu(>uaSuRzaH;!)>5m9M1H*rQ zm_L6pX-r=iYGi6x11jSGF8%1_lOD zfE7)j5oV+cDQ#t-$z&x+o!In;VMfBNpw{Tk=|97av>~Y^0;)#9Vfw zGN5CNLAJO%K!UtJ+(=j%l*pnTKLM4fkF^m5^FJV zvJ_2kj4+a{-{=C1&|+p#xeHoA11Wb)m_bE|vV1cU8=w60T8%fx!@benT}gsEv6{gn>a%9Mp`j zVFuL&??qrSU(394x8SCfH4&DsePYPpd{lFFbM@^=D-8mNWEpawdj92}FN z)4)Nh+n}oVMH&gSf=cAA)2~GuX@O(w$#m8zBP~`t3kC+J>5WlFqMX+l7#KkDXgECx zBok)Iz~B#(kz@tsh`Q5z}8qzj|MS8qM6gX zKuk~?nlyc9w2=zqy6N|#jpP^)PX8Niq)?yk4h#B6;52z#6qc7BfrB1&@Sd(2=m@OG z%pkS?Vhjwr-~fFB4p2661_nq}JYfbkNnnBh6dL$?ps;-o4qFFtSlGV+hy6@(1_p1v zoYXu9#+Tp@=QEH3a8dr6IoF+mK~RE$L9c*;@ilmTeXa!bz;1AR5>y(4!`c;Gd@wK^ zaRpbD)Bna82`PbM=7uXIWvq89aGg5?gEgqb$>_+S^A>c9XaWl;8G;(6po9Mz z=lFUsFzA976)+~SfO<(+BpDctK{sVFCbEFm3or&l5_=N3i^dqD4-UT+7EqRAn&Wq~i+8N$sBC zC}1iAcMd?ko)}Q;)c|xYz!e(?hUGZq=Q1!bfU?t#>E9EKbW}lE?*|U0plaUEk%2*T zx<{gs4y1JW1Wki!UJy6VNHmg^oM6DfP~`=2Pci6f1V%{qUNZeuqLC`2$n+11M(Xw8 z(_C+XM;6S%ZP1@y3=C>w3=9k)KZ5pHFkJU$U|_Hj2c1v?y33A%0kpo7agL-n1A`jq z>gq=zdE42b&5tLTbi5g02a;QW4kWkL1kJ&pWO4zCgOU{k16bT{FX${P)A}fHSl0n8 zZ0`peoz7tf#hODb=pZiRub{1f;44}jK;v_aCZORtNMY}o#>Kz@!mK`y_mmhIK$tbb zaTPNI0|@hoIWcp9c3LtpIDHdiU;ts~l{^d#Ak1-v-SHb}G#w<$Bk7nS#J~W;Y~GHb z6Rd>UrYFv}$(|k`q+z!GLb6e}!}KQ55#=3Aj1I7Xjwp}bzG0=&5%cM%e%f$vuYYJ{ z#Li@4K0V;Dw#ej_@%r1py)fdkl6((pc7mEDpiQTskp(DQaJrs5!@{&s8=S=LN0dgbBTyKG&p3oRNRJZ=b#XbPg3`6~^r83;XQF z8GEO@su(LXZk?`ZS|rYReR`vcvAEJOZD~H-32?ZjtW0BaI zNbFK1b|VtI4~ac%x^2I`c<5^+A<*V9mVD-b^GlWz!ASjN?7;BME&$Vl#pku|kdDLt@Jy zu?>;fcGGXF87ohZnG(k{okQK2$Fm(tatacA5fXbl68kn1`vVgD@AO!8V{yni*HHI> z&$))Ot)};?8!Oi*fd&hpLgh$o@R`?8@kvPH%aPcdk=Xl@*r$=$*OAzdk=UU142)U~ zQQ%zu8%cs4RIxxU7Di$#AhAJL6T)IW2uZvci9K`r#Q%=sl6#PZP9U-GPFI|4Z_O(Q z+H(rEO=o)MWP9c5Dw@U;l4VHZGmzLzr-y19D@&e55_*Khem{Mprm=WEXlWVDeU_je z2-F5QBz6cAI}?fBjKrRR#0Fi=3N!NnlK5F9_H76oG@i)7@BzXB2k;*xHV5c@YN&%m zkk|@HY+WR_6B64WiJgqZ25nY`Ij%(rbWR1-0?@L2n8X|;4O@}e2a(t^pp&nmdJU1- zo=EIaBz6N5yBEfuuBvV9ohu3IQ$dX~LSkDWvF(u9E=X)IBz6E2I}C{(i^R^Ht~kwJ zpYg!-z-jj4o}Z9p{vxr#Ct*WfBn%qthO*_5*hWZf`{}tl#?6f9r)y5Pk7u->uB)6S zKD}eQy#en8(4Z<*_uT1Ab&a#@K?gX&LRtqj&d#`*$FzIXc}|-&kJ~bfq6mnjh2;hia3V-l}h`T}(`<1roari9H*My<+-O z17qvyZw!oi>X|@ePf#=Ykl1EOY$qhP9}+tXiCvDw?m}WuLt-yNVy}a+Aw|tD2nQVP z$B@{Ukl6Q-*q~d!VUfiLYAQlKAce#R-6{lA1DceEu|aDKVQeoMq@pGaNplhsI}eEs zTGa*9+=e7R35h)qiM~~0P@JZ27*Rg<3XNI!* zk=WpqqM_mj(@Twwl_lelq>GW*4bwLo8!M}>KoZ)5#6E?@zCQh@v9WbMXayk551>0K zVQf>-Vb4%YosrmqNbGndb}kaT8j0PB#Ga1CUJ7ADQtoC52b^*bBC*dSvF{?WK^LXM z9QqSUoE>!3G}O_eNNhJGb`TP~Od*(o0cKDWl0+X8dlnKKw8{mheiM@TJ|y<(>8+;5 z`|CkxTELVZ0}Z!B-E|3xeGiHK3W@yHHGTsLt;xIvDJ{+Mi4e6VC^6raKL&Y zvBQwqNl0wa{kt$nS0RbFA+bR_NMUN`A&IX>V((Cz?qqHpS8od%>V-N!0Er!g#Lh%w z*C4Swkl0g@*b9)@pc`0WZrO<>egwjX1i}pn2OJ1bkk}uP*ng1N9H5i2p^g?oVk;oA zb&%MWNNhJGcCgCyc^1Z->cv5QVyJnbTkc>EHbxQ$E!>5P`y+{i`_oXp*+}A*NbGhb z_8KJi4hS36^=Du>3*mqR;nwtrmd4`KW4x1i82P3*dMAlbm$5SDk#qy~@1d4uAhAoQ zJ6aiAPw%iY=3%@rz0=CrS`u_r5zM{npwpqD+DxY3wKC3DU4G^dx@7-vm?V`I!?I0ZC+1C>~W#0DQu3>ANbB>sN7tgW%Nq#OC<47Bz7_qyHE$Imaj*W=tW}BMq;l-VsA%cA4OtcMq)oiV!uaXgAe8fITYl7 zZqPCW5Ql+*K@y3rj>I-aVml+TK?kqELM0waJQs-#KA0D3ekYPRXlq|RO!HDCiOopt zgGlW2NbI{v?AJ)_pGa(W(9yI|i@}HPLfOg)@p=YB1c$*Mi48tn7pmb2lK2NC_Ad~d z6`X7s{(%nEg|bCKGaXR9(jYcFM2$S?I9ezhd=9P_XvT_xfx!f%NDZRM8Hw!yVnYo| zLSpA5u`5ArwdsBy5pwl2L2T%e!=QuPV8;)G?q`Lu&w9wW&ITG|9vB#p$@Kw=w#*ig;pAU4!u2PAe7 zhz<2jG!i=ni9Hd-hT1jT0F;|JA)z=QbcimLy$VUu77!b1@nIx3_^e#0L6+r8H!*?^nT1O5fY_i}YX$}e0npjEP_{Hk9I8eQ#0F^w zB?Bb3C5R1G1G+R8H2MZ|QZkZw9*7M(VT^%+p~#Sdp&oQV7f4YpNCK+41H^_}Fb#=4 z8^ngHSqWl84cY}_Ll5#j4PryZpM%&?^`Ag&(4aR11H(6v#~|!_21d}yv`|GnAU4!u zK@b}%E(2mi#kG*w`XDw`jV%(}1H^`^_XV*bmN8@_vAe)*Q1~-2Ff0XepayLKv7twk zZvmar3uW&Ii9^+#0s91n1 znu{c{0>p-juLZH8nsZ@TOzTYKx~jf3=9nZAU4#TMkMxTB=#O8_9au$k?BwiZi6JC>?cTUHqddm zP(vk=*h)xj3lJNs*Aa>Bg~W~nv7zRqBiQu}wIB{ua~l%7ABhb<_!p{qGe{iD2HoMy z2xWs0{)L)z8>9xx1|RkdWrMC0hN%|=ossKS&%gkx3FJW>Xu+lhVnYoDpRfyMCxFD= z7#Kj+Q4WX=6)#0%cZ1ka%cdZ)=OVFpfY?yI2kVhI*FkKk<_AdZmq_fdAU0I9hy?=! z%s2KRHZ(DMf!Ly;JkG%2XTiV#8g&KnB0=I%H7OuA=!PDUL?(y>l_&wRp((r)#Dviq8bGq2e1sY^eA_B=!X)_EigpdIm@(5F4sS z(2{|H5wvWQfq_9B#DfY?yqG=kVr@qQ%sED#&2W+f7P9f%E8zZ1lUs@Vr(gSt$hC^!k?KqbzB z*ic7&04sDs#0aUBpFYJ@q64HdTmv7zGb zAU0Io2gHVohlAKq@fZ*rDxMBvL&fWJKpdz<6%xA@#D*&B0G`@=)Nz6f;1 zDl}PCBe7eM*b_i(sNpk_*y}-TsNNk&?1M<`;~+Lv?*%0GGZ32%TF{1fq2lHs zHdNdViR}$yL)C-i%BM8FP_C#6AbsJj$EY^WL9 zAU0Io0K|rhTZ7n8aR(3^D(($pL&XC?Y^ZoNhz%7_OaO795|tn}RH74!Jp+k77sQ6D zUya1x24X|??gp_z*@}UI;rw*N0Aq)G&}v=KA=UN_42)2=28ay}LPI3B6%yM4#D=Q( zL}KTH*w82{2C<=PYLM8IKy0Y_QL~XaOOV*BKy0YyTS)B3NbH{=Hq;;{2c-LW!0hRZ z^jwtdq0*LMA#k>3a6)2xfY?xLVvyLWNbG758){Aq61x|Py$-~NnsXV%hK51?O%Mkv z@e0I-wm-gt*ii9*NNfSn;#a6;l1OYNB(^<>4UK9q5F2`&AU0HU35X39uLQB7;w>OHRJ;?!hKf%|VlPEvZ$@J81F@lc4?BWd=TOb(kRyaeZA+hfwv3Xn&23aGq zvyj-mAT~5{O$M={<}U!Tp=s+7hz$u*F^01sjx;1uTy$Yz5C*ZQ7ls&%z?vOzKq?^0 z8NP$q&SaJ|sJIpq+X=*ms&NOgp=#=bKpdz<5)wNd z#D*#=0~&5E~l9*&sGld@d6E z0Ei7$a}30Ws`-J$7I0@^0G*u!ih5%Z8>-$C#0IGc`M(~-fd+LKhz;6_0t!-h#EnNY zLE=y~OF(RBbgTriq2k+-*hi7rcR_5Z`Zq}IkM5wn0k!NGNCL{1^+0qGltFB$xF3iO zwJZ|EhTf+W>w&lxDFY-9RZ|RNLoKcVv7zG4AT~t2o}mN8fl5pUu^|!+GeB&p_+k(n zD!u~5hKg@PVxI%Cp=$0Su^)rjP=~%jVl#Py(hw;8LFa^kIiOf#U=TrK>w(x%&E`n# z3?z035_<&_`z8|mClXuB3vr*6aXk{p6U2t5(jX*uG!i=<#D+Sk8i~CWiG2~ohKA4$ z5F2_^&>b(t6-CdX;$Z)OfO0_o{{>=0H8XlMFffAle=;yIuzE8v2t(NdNa9i;HdMV4 z659)j9R^}U#|08VY^eGiZ&1$_%BcWJfX>xtU|^^Pv7zFfAhrw0X$%Z~AU0Hd5)ykR z5_>KZdkGSI1rmEboSo0Wuo=!_VAz4g-h;$Gh{QgM#6F9}zKF!WfyBOp#C|+IFv?hb z`;sW*8Hr3UzD&2JBGJP(HIxzk10b_rrH-Dzv9R%6>cY5DJV?RcN>30tr`!kA6*F9wH&*(C}_K@*$ z#+d1@hmFe_Gp6r7Z0yhc=0C%9{v*b|j1kjgj~M$i7EE7z#Mqzd0>kuwM~wZLUNB7e zJ8JC57&3kCQDc9mGmO*Ufw(TyZI2oIGqOzY1yL5$?;Zo`;he5_+}Mxt!1UVVApdYp zKL_FpOqV@j?9cRqe|p{tV?U-hBGdPsF!p2IFrD`#$jMUE<4zj;f$RlwugFgS2jZGc z_dR9o&$wXv+*8K$nJ&mpw>xdD#q`d5de&)UCDs$lj0`%{C!RJ|X5E&1R$G3ozDBzkAwPo#{*Rbhb0bYK$e*bN9|HCASly*S;kh+AxW%voar)`*LsJBA(}krtWWde)eqb;3mkh82)Y zi`JYq7GV0bY5Kmi#%in3=BdL2hTZYEX-zTWNKz!(pMPVlzyn&&1ifCUdiw7-#tK^HLZDlXHi1^Kui=AVF9bRW zkwsIR5o8!s9q6(hC#~s;5=K(fyTmW?O zF{c0{=)N6+5YR3Kfg5}b3_Jp$OCxv%vQ!xu_ylgrGBEH9fbI(t5D3&^U=S3TBgw!Z zByb0GZIOToCj)~B0}Ia*ZUzPpPmnuVZcktE-dHd3oe%>9M?UBrLna|x&>6o4pdBwP z3@mb>lW7W9f^H9*2Rb;k3A6`?=wZbSaMjXn8fW0B8>ri$J6b0|TqTQ_%58 z0+q514D15n+Y|(DgH8q(h*4)?;1U2G&d4pmq6qRhXoVNAKq%<=Spf$HkjKM085jfv z-id)co+}3OcrQBxgRsCgZUzPsfsW~?KNySGOQ*fB9N@az@RGd zmm9PT<-QaHgSxse=}e%z1Gqr9^hAJ;3AzJHgn3LLbqw74AQjMCdbmM5u3)$H zaGQXqY+0H69edEO3*Dm9Ux22gB)JZ z)C@|>+<73~@LPI7=X`NAGNrIHFtEvi4&h(Ow1Ay~fp-Ht0|OtJ0H<3Zm4Sgng82+67`Q=8cQ_=Ozc4Z|@NlmNDTCe8 z!~Fwf0_0pF5$+A3D3WE?fZWp42TE!3%-o=pUqQF@fcE-ugKbnswh?+u55y$sEjD5d;4p<6l?qA;X5gKVjNIm+TU0E-93}>~dXR2Q z=3^k;pj&zzLFX%h-C+yW4E8znmLBd|ppplAOAj|V*d4$oaWb&EgA%?YGc%~@li+Y> zuAj`wz#s}X$^~qcDCqoR4p(MS;EIAyaprJi26eE*UebVU>c@CG{~JdW1GJJn=vcw(jIY8nt)!~13I;U1A1xCD^Lo9T-w70 zy0nKMbpBN=C?`NK?co*$l@(R23qV&AaT|g1eKqS2(2+#kYM>IUhII`nKXNz9Ffeey zFYTEH3ZXjIBcQX5xImZoM8eI5UfKgOw;9>o7G!fywa_Hf?=xfgnA5BEw?y!C@E3FKZ33Y`gH zP7t>q=t7H$V21^B{{V&0Brqq0fh`l1Hz%`#HidD4F6~j|VPN0}hZgkG9*A3JAlw4J zvhdr!uzdgpJmk_IF3_bt%i*TNF74sA0o}^5k+mG8oPq5PNb@GvW*!CxF3_bt4?r5g zh2J(-aN)-TzO-isBLf2?5BSm^5L1wW?GLD=*vYyXq!Dy!k1XhjD)UCs{Q? zX9t5W?ExLy0Eq?Yr9IrB11OL#?coA7T+Xu=^D;1qfG+J(hXk&1#Yr{}oB3QA_8pmRt$uCjt6O4J9GW3RD-qFhuMl*q2Lf`VE!5EQsKSV5sE z`WuwOZnA;`MijJ94|Hh{$e*HM2i;}`xs-ve98{CuVO%Q&|qSi zzUP-QZ~bbJ^k>#pApKiG(%^VzTLC(hlMQ?|4%=r?-2uI<2Xr1O2jsFIF3@E?hM?13 z!R3Gk8>k#$fRqE!%X%Q?fEL?XJ_ZIR?x&#KqYXBbnY$iza=H#%{XtN(o!bm_Ft9Eg zh{MXjb`(@4>9O4eona2Ttfv}e$vRNL8iRE+aK8hEIP|g}?tW0o1HG(=dk?5gH)8`G zR?N)6CIl)2&Dm^0hd_fa>$wEF{|9_6jtv_q=`z%FgXV!bpqKSzK&*yd)&nsLep%0HP&5UwNeeJAaDguCSqwU* z59|);Wjzp+pqKSPG>3u1kPYI(`f#v~>4ym?&09bU`qlW9J?H3 zWF|PBFmQhdWv?u-1n9CJkezJ2AU9^S*$FZ*h=4BZ*#&Y4I6vpHfzm1@-$L%{0p-Jb z296RoQ2G)DZII+BWqZrSz#tC2tS1As+KLUd8JDAitwfN4fvp2{4M;89B|&JOd=0uB z37l=f*$%{I;A8<=$_2WtM^T7@fd_I~4>+~)fWxyD9G(I^pu2kNIoiNH1qL=yCB@Of z_7UWC&}BV-LJSO|dZ3Ka%?2_^9CBF?*dVs$kjr{>K{p6Fftrt#*wTa;7q!Dxc@J~| zfWT4Eo@aq;lAs=Oq!t4MvjFJ)EEa(Uyr7QZQOIRIM?g(;=w&_1G7JnHkjr|wK$rC# z1^ESZSr6>49v;wLJ@p({*}z>}?hl}X5PDe;cL%6t0lln;y9<;=Z?NToN^k}?(8gGf zn`~8}3x?Q0$>AQ`U10_W-tVBxkie+`Up^y@o#R7DDiFyGO1A_$UDkud`-D(jA z1|iT%rkwS9AU1>07SNp+`XDxokOSye8w1d3EF40ept}bQML{ifA<(TKoJJtFfKVdn z_8MbQAtNHh3%aPo1jLpQ0ySPaO+l8+2<3sUzAytN1~~>!7A6r;h=W|oA_2M|!yF_a zSkJ?013Hsc=!Px>1E($MutWx-D$vy&ko$s#NP-4{GdkAZ>HVUh>~gP;PJH0Zia zp-)Pn`?)~l1q?#qyB}mhY(^n|(9H&NAU2awn>+&pmpq8gECeb4jXFBnoP2IDvwQ zMGbTgDCF)WX3)u}kh_!kL0yxymki(m2JQ;RBG6&IouKnPD;YuB7`Tsv&U>x`a~Qdo zPM2mfabVm$J%-6dEzA~ls5|uXB<>%egJ0p7C;bJTVB5-gMidk&py*fHU-N(YTT#SK%_cT~|`VA%%xq3g4%h{Q(gT&u}#6hm%1L=XJI!GSk z7G#nDUF{PJTAeGv1==DjAR-IOL!diXnFTh1YF`F6@TukEOdxZh`Xs@JM+vxs799u( zf(B(6*rtQRO%~i!=BhX0mS>s@IssJ@B&xtv1#&I-9Z?1bZbh&J2lrLbanMRkOT`%& zWVj_k{!j*MHsCG+9doJz<`^=tgIoww1U~tQg@GO9iLIc993<-4xIw|F%H##QtwDiX zok>lCfuWxJIOqgi4KRlRVwEP78R&L!?(3i<@U_4)JltuZnHp^-H_%8B_fJsQTZbu3 z0#tZ`U8DYXa)w5DKG(0z6Twl1m&|ugAR$- zXF3RSas{^`lLYAGdvM?wfg^;0yA+g$jF}dQg2qihg4)?8;QN#~xED=7$6_K`FAYjB z=HO@$jD9OM89v7?!lMI47JQ=@0!<3+F1b86#^9U{0 zU|`^ZT+btP1T@^24N}4(bchqwjsnGn1|$x_t$R=^l4D>g=U`yq$px7&c!Q@tNt%H{ zXa-0<Vi=gHXVMY;?O(^J??Eb0${&ZS1Wp@*kqn3do&3Lff<%7tj6kE= zLfW7k)gf2*2ogH_$(z6pvB4aU843=9vr_kr|i zGJ?YQiS&Aq2Xq+CreEYV5vd2=Tgd~z$;TTM|N4xF<-j-jyaB}({3f3XpsR?D89~E9 zqKwj@lhk-j89|K>2}Wtq?an-AjMHVn7x{p8{PS2cg7)8QFiNL^oCUwg=O-w8z%TM~ ztOw;Hdq#Iz@J&7ipyUs~$tRYTfq}=7@uLj*CZ7|al;FhJBLlk0M>+wN37o;PP{AmD z9^`Bnuv`tJv@0mS-5F2Hfp7NN4a&b>jEiKzH~R>KyyVRYs(WsM4$-ck0=iX^1vHrf zIdGI66hSvZom5bP!^yw~I>L>|hcOs*#?)8C{RFE?8)jqs_pbLY zc)BEyi5lbn=?*+5a`m9o?!iR}{H7n!*=M|!AfL-rF!Hu+QDk5c+5x)WqZPzt5CUBt z&)c>OG#MvUD#5_O+W|^~0zy(CUv_~~pomZ*$gSNVaTB3ZkdJyn;ub=4_!$^@`#|Cm zLbh@Y47~LdKoT)R4?&!XAc-2Gv!F1Y3=(e;0(Av>r+~y42*rRjPXmcB5t^>Xz`#2l zBz{B)G|R#}3nYF*=rSV%1Mh5*_zR(SB?boGd7x4JH$n{z3=F*ULE>M8IzV)<0MufX z1$F#*H-h?oMvStpstgRgn?OCkBt}`#ASCZT&|pguqbz8wl6OC7oVA!yc0Z^G2)_HL zz66v;LBo0MrxY0&Ko}AmppF0w0|U!`PzWCmP+(vXi1QcYD3xI^?gND2RfyA|hWV9FjagI@~WnE{5I%#Kdhg{Rf|k0(-a; z1A__ovFY;sCX)5-pcKvnF6C^vL1&Ef@`B4h2W|n-rLKHn85eHQHeX(Tu#5-ycSQyU zUIDO-54Q%$8PHpQxIwinuL!u94B@^EYLbgGf;?Bk4XUqs#lWXuS8#(WY+i8?r=FpT zy9MNN2}XSt(5*j*Kv`0fk%tX@>(4g@1_oX!M$p_7JHPZ{83qPk8IU#xE`Dh#P|(YQ zc|82m4WJwZzY1s;$c2z1o}XX(9LN;-RY0H`pH~Z9DG2h{OV5*MVBpmTbA|Y&-+(e1 z(p^BH1i=o9X?sww98^-tGq8b9Fy}R31RbNm#s;eC9T`C*j$97Biy2RXdQaM*1Pr|j zh8C%Ia82JYU?NrDEWp6PyAEuCAa^Bf-(mKcQVM*?O=`ow>rrG zJHQ+TZfg){7nozfZ4PqiZZJpC0Xzc8yO%M6k%1wATU%&){ihO%de8_X?*VZ5#DGWO zcn^X(vE1FDc!ORK#GM5yWDkR7;=u!eyhp*lOyCCHnZgUdF^CaVI2>nu3UYb_?@2~m z&7>bEd~%3$ctLfkJwSqgfy z5VtQV6MSO~&|qK?;0D)h(2Iq*!PVIhaQc-456$!b1Up#)Jjl=cixE^#s@Za%0o63n zn}xXdgSs4lz`n8MJ^%^P8-V%7;u0Y-d3M z9m5m~y2~(>H=PM|b3Ax*i#L<$DQFIwfqOBi5QE+V#Jvy1f!+ed?Fq^uxlBtyw*YZp zo_|c47m4!a?T>qVt{%ELk4z` zsd1q3U#KTR2SM>JX1b%nz`(`9yNsz1bfL>hP}#Q}%x2)e28u7l#XuK919I0v*=8jZ zC|9z{fFcThF%a)(CeT?6JfM4lc)x(djDfoeREYl+0Lz3)3xOi!7t=4v=`3Oc_{~7y zK;gs=o^k%mB0U9U3J>!I(7sVt>HDA-i4ZfW(OAJIeHT<|!EXlYtp~*#{AM7~!~`$= zW+2dH1g|*Q&;$-?(1lFA63n2XsU!|*7EsES0bejw#37vmDtF*F11$vcl$k+=I`n2B zUVUacVFrdCaq0b_YTAfdRTq3S(09pt1_oXeW@}yW%|Ks3QE$o&s+o6)OILuL2EQ5T zFGwT&W*}!!UV+~X)DNn<;5P#u0;O>)@U1vc#id(7zPASRo{3980af2NVBT|aX&2DG zEnZtN_l3ChIZ$l_zeH%dG6MrI{1PE>>V{t;1Ww*=%%J4`MqCP~rPeT>1|vV!Xf}WRZ~GF2lf3&+82iL=_3?d7!!je$mhk zP$R{c*-;mK(GWi<3HdRDj@;0Yk}d_Q^k)VYn=h25LHGah1~4b;GBCVRmX-xM8-CGH zJ;*V^%%H;Vo3gYiC`94+3_06rJ}Y^lJ_Cc+ZBUrCfkNW}BLjmrXath64K&`$7_6lXI^wS#B*)0az@QBpwqtAu zjoLAWs@gCxFo5jP0o}3wez^2WcI{mk_i6j@;qzVQG2B=9UGA44Wy`a^TpfP*~4sdj?F@%}27i7vz zkSW)vm&=%V8EAvf@;e9$ZqUieN;5&HQG&Twm>C#UjiGK;^99-9!oa{b{iBSDixVgS zl?=fl&Q;DZF@#Nt>;Hc#2DMoX3=E(!b%w|>PYhsFX9R`2I%5n|IRk^*3aEng>E*H} z@|s6o7#OM{YMF`{7}P*ZZ9r!CL&ZuN7}!yWIf%O-q~#6Be}$lXbwH!kjBi#Nfo@aKjs>09^`>sRuAGS^ zKPVv8Kno&4(H>$nol)9Ebb6K?EQmqZ06~M;OU00P`UW`@dB&;JFUXllyZ$p`V9?(J zI_pXtJov#Fqz_IF;*1~}#$bIGHUoORP7(pq8la+zN7&KwUXw0ZK zy;0soiuHmE1H;tm3*=2yAbtX!xC8RjC1Z%6UdWqBGD=QoQZUhA3$LX0O9A4? zP0vv@QG{p$6)qr6Q%$E&R5lTtzDdzU2qJS8nlNudjeDVJq5zT6gJxj?Gl)exN+!Y( znGC2*G*l*8$wW&&&kU5DW0=Yq7*r=SLb9mZ8mP)mP?ZOjOqAu1BB{I%Qwh2)2;@Re zbBJvc$}o4RGC_(G2dGSpvWb{nusOoE5+aTr4&Y2h{_ zD8YrZ!xG#bMxE*RR7|AUKnd=X#q@tFCd!cF2z0XYoG)E z{)3GI6NPicV`9vXwLkZ05dPm3{43^2M4 zlGbGcl{ybN85q<+OWHx9bi!)-LU|K;VMkc88VXIlEY{Nl)lD>%z=I-Rg6XALWv)iBoED7u^P+)>CUtyeMXA6tnB(MYdxfmD>!LbYB z8-Ok@0>^JMSe`M&5H!)nm;#>Y0v+~l2%76+Oa;$%fffcE>dP`PFs6a0yR5kx81%tK zg-tqm%8O|tv_Q%Py92al${5@-$YO#v4OBsQuz`G_2J$y3fqU6NGKr^#iGj`?P~9HM zz`y{i#?x)U{svd$pbKii+CUf7fV9nnYMZZR!Y_OY7KTqi!Q#TeaMfmdprN(c^iLWl zLdKvJ^#WoRqalNu5+ehHq&@=!lP$>j7)Aqi##rWw3~UT)pi%-<3M$!7chEKwsb|n} zg{oC&jAArWXN&<65XB5;+@RFE0qjvwfP-3?jB`5eVX1cmc+T-7H!SsT1gBmh9?;Eg zpkvw~e8v!caN6AnPP>eukd(U#oN}ER!yuu%2^_eL;gE#91#G1q4+8@vY`0>DEvWSd z3M73yNZ2ZAnb<(W7L>?9Ve4ZD@;s!81ZsPL!?q3@dd*O6^R-Nb`M@$epfXpdAJ8&! zkpPD%!~{@?f)-MMLX>;DjJAm!D=5vHPq)`LQD+5-hEC7chSi*NKxHT-*)GvG5s1+T z6+FMe9s-3SC{;7gnc%>{Uj-_c~}+9PCoiJ%k{yb2>o0 zuBu}q4DmYX*cFi1)f^CB4}&F~45$ZVq1xtanea)fl`=3efc#nj(ZXoJpaUwTB&RRX zF)?rpb%MpUGBc=t*5!q{TLnBT3tBn=i83{2P;uGH3yU&!W>9tjwWEz1r;F*D$T41@ zZmJ8b;9#+r?FjKgm9B|`E;whvVh^I3<~2;9m7wNbA)Lc9%X zT5Sbw%AVX~fyEMw&KMm-Y|R~2Ul21C${ zGh;k>##xgORt_Y9JmNtsDtZ!%2`P{oLz%T5r#z1K4lRtNhH7Cj%FAnpV;-eJ+B z1CAa@y0OI-py%K$fU8 zLa&`t2VHLoYTR;EFff=e2JO^3!Q|q?fN~d#xq%D=1ItOK7?3z9%|q`(vE&5}B<3)K zx@A_PpoXfV7HEGHXe$JR)f~_{qDr7s%0YgazTLotPo_zcfdPbB6Kn#wK|`vbB_S-< z?m`R(cUMYn|6^#vuRr|}8@I@IokWvzlj#e7H^xnuTNkupI+t$PhUt7iWQDfdTz9r( zoPO`9puqHbS}X$7yKXouZT~XEM8Qn*E2xDF-Pg(m3RWmve7f#=6KmB-B%wScb~O^a zb9(Q26LH=HNJ3|)Z#-`zZukO8=nE1XbZ8YL)FM$11_l^gY5LFeChn4jNJ4E$?8(z3 zFPJFX?nV;2fW*Fw#D0au{(;2ioj$kHR($$}3nmivPN17qpsoOIgo3#u8A&`JiCvAv z2HjBzQ$Gbsd;t<0w1Wkv<|C50H0T}`dFZtpUJwpAab+X1ry{WzBC*#Zv3DY|&mpmI zPd|9kL|;+>bk7RZf2v4qqv@QNOq3;~kc9G)*frB#FPX$kJw+1wg~Vp(nZECmiI}7k z4ok=QQN-(E6No_@tGLxQ&#NqpAyiHTX_p?i^p9wM>7A+ecx5k?CjvE`81#z<_3 z=?gELC`*EdZ(!kFizMAOJy$ATJajFR&`u=wQ6%<7B=%h-_Ddx8S0py$^tGZ{;*65h z?}}!LhZ=!K8=wImfyAyvV$VlnZ$n}qLSmmoVn3d)D4r!g{mB&*14$!LOCM^!I}$r& zy6#mIWyu;Op?OH`)zdStnkd&_MiP2~#QuuJW&$m0gW4c~#I{Fb`yjESkl6W1>`o;1 zGzfe8c8yfQ`eP6dIJsX&Vn0M;e?ww3fi6vfI*1R6ErrAeU(XCxV~iy3fy54lut95w z7#P4;y+Ae8K_tKq>Ox{qLt-yNV(&&`A4g&pdl})Q$d$4!mLn75;q33r=LIH#9Gf_59WYPW$;E~ zha<6*k=Xf2><%RMY$Wz_B=%+`_5mdJWiT5O?+o|B9Ec-cBeB0Dv6(@GJW!wUBeA8C z*y>1ZVQ5EAPHUnsxEL1NW5}OB!jhwtCk;K8*-^hbcLt|h7-+u!& z2z>tylpTVkA#u9mZ4-UTZAe0=k=Qq;XWlk(mrMuUKm*lXgT(Hfe)6_Sv!^y_&>Jdk zj>HDtX$y-BeiTw?U4Zhq4 z>M=fP(BU>vjudDB8p>8fVjCf`?U2}BNbIobiD&Y~>+6t&W+JgcJNjXPb^=NK3KIJP z68jAj`v(%6MF!E30N-l^b*?c)91@sr5DqvngOJ#9NbD>mb~zHe35nf{#GZk~UW~*B z&7r|Oc0^{n+nguOqRaBC$Usu|dl)V2%RcJOg!rEa<)%C>wML1x$@4L>zLnggb--4!zLnhCRXJ z^@T`6^+@bqB=&41_DUr7EjdJtJwsxH2ezPY5tB!#Q9@$tLD-OEZLA<1u)Exl*g;6_ z`02V2P4?G=?}ve!9R<3|1yX%8NbG4y>_tfIbx7=8NbF+}HY62Zf^fj@ zy@$kpg~SG}fPzH=6X=o{s6+XX*iuMrH6*qX65Ae$?V~vT)gzO*`in?nPmtIjkl25b z*aDydHK_eENNf!xwh0p30g3I4#EyWlK|2x{7;+#Sa3EA5v0ISX6Oh=Ty*01^S%D+B=JNfb{P`8dHT^8Cf1Bcr!&4Z5$An|B=dQ?>PwU0`gqXH zCe-i}Bz7YbdnyupArkut68j<&`#uu;EfV`T5}Ok=7$eUBNnhd+4miwJk=VvaY)2%v zKN33@iJgtau0&$DPe1!CQ@nmLlF&vZ_I@PxStRyLB=&bCHY?~-7igFXBe4~c*!oCp zTL>Fcpn$KafocXFFa(QD&^Z?{Hu#Dfs2cDUHBdJAiW(>zd_@hE4ZflV$_8Ii17(A+ zsDZMtYlDu-gmS=F)IizbD{7!@@D(*sHu#DfC>wl54U`SOq6W$aUr_^PyMu0rfwIBZ z)j-+c>uNx3kpByj6oD3PzjzODu;4!*7i$_8Io17(A+tAVn? z*VRDT6`&acD7!@$bQBqdL+(QBsM4LN*JhRQXn?eX9^%T=yVtc1_l+- z)iO}FK1dv@#uCJa`rZ!2hKhS5u|q*@X;AnxFfc@cI8a6DAU4#{0wi`5hz)ghHxhda z5*vIs4%D1AAaT%n|DbdOawwF&8zc@@b5x(f9)42hDI^K-1v*e4JOqhD+0Q_1s6p?+ z?CHCN?;39|(6~7H)L&YC}*ii9TAU0I|J%|kz|AWNl1g)lliVK6- zQ1ucYG0ers=RKf}@0nuy^VnfBfKx}Bx`GeR{@eB|fDxM2sLoJ&CVuKbeffkE_ z*iiBLNbIfkAPzLR_93y4Be5@o*ig;yL2RhS-#~2W1x~*}zJ#*Dm*POx2$&!a)RjYG z>p|II|AQ~TfocF>cmrkoLKT6+A_&BWipPT3P#-6O*ii98Bz6sm4OP^cw|s<$19JpqY54aA0;Gare)6~tzRmTUVU98mZ%97kf`0p-T>LU{S7ZRHlbngpPvjh@b5s7UKVzW-K+K?hw z9|&SY9U22-gN_DbU|>kFW?&G8va>eJmWLLlTRD1 z=Hp203rOs1AU0Ij)*gcpbn8R=#416?QsWk=dFFihX^+k_XE z>oY+Lp_)oSY-q4ng4j^;b|m&xB=%w?_C_T39uOO9&Os0xYR&}^8|skyn@F7ZAT~5K zeju?KL082<#ld&lKs8%}#G!0oBz71QI|syu>MccL*Fo5zNMK-S0db%P^&+tsgV<2b zYmnGmk=WNjY^dIsNNgU^g)mTY3nX?J5-lAvVjJVd%8cEy*i5&%EgDhZRU`R${ z=OD3*z<2UM4Q&QVfDUSAU|^U6Vnf9jg4mXj)V>zPhB{~qhz;8J#lXO@1LPnm`!Glx zs^%Ps4Gs3oAU0IZ9R$0c;S-1hb?I*;Hj4`b10z(N3&e(M7Di$#fY?w+8-dtRi@lK8 zNl5HGBz6^uZ4L^51_p+D5C^Kc8^pGN_;><{4Hch)#GZ}Bo{z*{hQwZl#NLF&-iE~9 zi)`^hB#C24>{Cc=(5*$VLFcPT;&+kQ50Tg}kl5h6ji8?S2o(p9XMT0r-o^h%rhbem(=R%k`ZL;0S9CG;XSA4J2%=6*KM10xOc!)D^=Firo(Q5QOyB5g z`kv{}jp>WrOhFfLd~`GQXFN0A(cRRav0?f|5XCe7A&AnMZs=hOx*wwvL)ST&&zNYG|-%1!5Wh&A{+#y5edv5eXwxGX*4IXkuxIxaxw%(!|JMa=~Q{rUwz*|M{D46BhsN zhPde>4Rq6m73i!pHPB5LV)eiI85o#ufU+eE3p>9)0|N^ayOsn41M_}81_oxq0MLST zMmAfJh#crX2_cXxSr|E4#F{QvJ zbFhl*Ffg!iuzv^L55d9;TDQT%!hTDfL5_iyg@uK^O^$(qg^?pko`HcGv|5Qp1k}f2 zW}04?VyeJn3OYeZ7qqpLdByZqDW(eIfkF%ntZJamlg!0 zuFJr{AR+>q3=}ajU|?VpdBMxTz${V<3M>&m&|-52W@#w~1~xSx&{}jB(6QH|Y;5dK zOPCoL*iEPVrkl!0%u{AyV0YJ&2rgV-;{>5b{8(!8rdr-;a{1&2xX z^p)wR8YTvyv%)0RLA$_NbXgb}Btfz^EDQ`npq)?*%m)-17&xV@nHd<^I5=f8SQr@C z`KGgGnCjPqE;Qj%cVuQ@5YJ_1U{K)FWoBhyU|%o7z`&&kVluG1fljT}2eDb$K}P{` z8GtrHanr8%J3$X75sW%3Nm6vu`n>O@o?F=gB%dA&%nTC3-Sg7yDI2dPCF2rg?%B& zQhSgg91P6z)Bk3e%BMD~Gca&lv4W1vVdTG|%)r2H4L(7fi9ZW;bfFC^$bJ@n(0(>< zTQG-%zaDhDpdFaQ!@w=e$H2gC&l&`}ox~1w&RG}8Fy;fGlMy^YM|Uz8O>fLJl~MvN z7vpULOD+W+1JnA4m4QK!osEG(=ozTaWIi{2Z>Fh~s4-}N{3KAY^0D#iGX=6SFz_#) z{wC8@N-P0%;)M~DE*k@b6dSK86X<}mT! z2OZR8&jh{)hX0w$^!hAQRoiCJj`9Go3O)tiFs9w?3=I6s^%)p=!@(P&82JBzP9lh4 z0&NLm;$IBfH6O_&1v;{r-+21NEK^A*U(h)bF<>Kj`Im!s{KqnZPG#leF9V%F5(hR@ zfIk^@4oE!MdI|o^Ah#qk=`%AhNb)C7x5+kDtA7nT4j~n6jw}NwD8NsHjw4$J+EmTJ z4O;Qeo6hu`je&tLgEyB+pM!yczaHeaJSLDj2L216UHb)K3l#VtgHA{(0eeA-A9RZY zZzn685^t6<`-V~Ph^@)dNNM?KR4 zP~`A00(q$ctbvh%+Y)q4Q6rNz2Ll5)1L(+vg-qof3=D$p91ILXVB!d9^E@vL$c20y zyr-D<5! zAaf*{oR)k*@l>TIyKZ9?(;NAdAR`Se`I2aiC zczBhVC&F!1Mz&D}Y9rVrHLyt>5R=rwCUG%vvw_ae&}0q<-2lPNYr=dEYEnG|uPM~1 z9#Bd!1ACQ`KM{1ijRly)#K5f!(rw8+7o?kq*M?bw3+8iMsAjOw?V#?+039n~57x}V z4-R$*Fo%jE}PdNn8wxq<^%niX`Egd5n~ z(knq>;SP4V^kdL@7am||FmSVgl7lC+3Ks(dH|V%KUO(n0E(Qj{UM>a(ArQg9%L1}R za2`ki6nhNZpFx%gvaaIdU|^60l?s=p*X5Zi+th&4h&1axE~xMykQPup2_XnjR%YP- z1xgIctQ_1>mD=3X>+?*dO&GY1K#4$y)tsAwLC}YrfdNS?$PfnZMWEbo#u@?BS~guL z-&C&N6uoTSZuLI?hN>)%Y!N7kGlrO7T zo46Sm*!b6gGF&z5EN%t{cK+|6({O57`#{HL^RELPhf>Q5@&+dZw>K#C>R6X?*E2Bi zaq>2@TJtb4K+J7IHn$ns+!kbWTOsB$a6bi|;?%|px^Rdug13|P7~G^Ts7c_0teX{7 zkg@Tf1Dzq#!wM=NIQe-%H(~Jhg3EOu{#Br&wh!#Y0RFR}q}UI(B#=K7bd=8oFeivV z2y_z9M6knx`DcK_XA+nb!oZyZDi6v^$A+A;cpL+(w|r!Xj3F&;hwz zpkjOtBnH`e*RyuQP2Ipc2jqVSe$WYKyc<~~L02y@a2J6zZ(>d5Wnkb_-hWaKR{$%)q;ym5GUgfl;7{fp-U(DagQG4=P1=vQ7nQ^y1ya`X6r7US#+0Lw0}t zeuxJcxJyC4Kfrnpq}!YK2&*R_%=br;bst04eH@}0;<^)H*Lg8;?*bJmCt0~cS30os zo?!)T%z?zhS*S@1K&ky4D5mQf*ciACLHY7LYbYNBgH#0XMOJox1_tRckb5qH6TI{+ zP~yD|PNdT3KxZ6XVFe{K=~7VIzY2~hY4G8B*T7LOoeWB3*TF$8eGgP+-T;T9H0ZPo z-kacnk^TZox3}uS{)C*?a~teZ2JR$~jytTapjL(osAzb|D$fti@W%WM3_@j~{0(9; z@Unp1%6$e@cRXQr6ojx}fogU!Fq@B!SDj5*fB{+_Xt06G z0|rQWpb1vN2q_P=*w%yk9sJ;<9JSf%L5^hRcK{W+I&6#iK~>lZMbL?%U=Aw-_Z(0i zrpLCMpMimoh1ZBJ7G%jEPyic)&1K-<1_~n+Fo%&Jv;vmblnqqQF!4JYFfj0%fjP_! z+-aZ^(40+PfPsNehS!=6bntw=0O;}wUK=)0a%SK^0t$Ltwo{A@3(l2tz%00mv*5wgVvDBD~&g)`AQS5J&ldH82Q(Zp7gA1-nB4VznPww-CfAe=tXw zf!hq^jsUj5Ad@6`gV|aI85sD%?g)Xn17cDr*d(Ys>chag*&t2~2iwTbz+DI`<09DH z1sNFl#CfCG4uKp6K5j4?tb~Ez8FU0$4BKR68>m7MWZ-rOl{j&169pL< zq-1y#*hGXF7^IJa(n=yY%%yojUQPmsQ@!*OP(USvZID&~ohFt74g%@PpuCj|_5=er zs7J$_#&!v>zjJOKgFl^DEjV2%O0rAIa=HO;7n^}F1B3JqP{!y68zhrj#K7AF zR?Wb@nT>&gx0j7yn1O+N0jP;NiOoZpfk7}rn1KOY00@Ct47@BLQ}`5kXR=)oW?sm_kmv(lqu%2Jp!E@&A$j#JIrHy0rCug zHmKa0&-M;A1T_|6Fu4L$;wHWd|bSj*+Bcp1acEA z7gYGILmstgQF4BW!<3=Djd;8rnrk`x02pC|KiQ3eJ{P-%G^bhNprfTh4wPeH-U8}!=7LOSyTM=IF3!Nfeg)J^YJivtx~qY|@jn9_0|OKL z7rp7)Ri;+;@!AXw{OuqG0vw5H1q}Qh+d*-`Q4C^t9ui?-5M~EmP{Q90DvU(fk7_Y6 z@b`dh7G(!566Nm&vBlUGK)vcdWzg6Kd#Ne|1Ajj#cIDXFKJBTwd@XrK!w}m}T zgn@y7)*2B8h7Igjr5PCb=YR~|!oC_50CPc>U18rX$-uxr52W`h`z4V1^FdwdYmiWz z4m#Ew6l(Rh49u#a?7F~8jDdl9kpu$+|B|)h3=D#M#TlTrH>e6{V4ei>;Ib1SsT&|E zP=^p)yECxa@UQfiU|?W>4GQd4pm1Vf@0Dj@;9m_Yvl-brK#{oy#Aatd2a3$KASd#& zSFkbEGw`ni1wJ3UCaC|l9%POHyNE6W1OJ9V&}|YN1q}QfK`xMB2klkj-vsih3{O*Q4IzL{>>m)v2pNkpAB*f=&BO_9Uzk#*k6H)^PM0z6Z><}U9G!7Y!>#X zS_};J{JTLMHU{RGpe(dE2{a%HI=h4a3@GTBL3dB^Uj{R0fMV|!h{?vnf9DR!mKczm z?}A*%z`zVTr=I`bagYI^i@o@Nf(+*4;b&nq07bw9|58wbN?`baWp#Xp=KP_-JGX!4;tU9zd=V0uc;ycNqEQ7E<`DU9+vK#hAl zD=;^eQGP1O7<@BI?-O<9F&lp7&lJut233Z z-zdSrP{Sy{2$V3~8Reuwhu6!?=z~gH#^(~C!|Ub0f-xEk*`jmTXYP!~(hp zhnHnH=n5K8OzDA+_XlM*P6qCiAlrQyK{3HB4Z1)^*A+Bex{ZN>Arz*}fkDBAQNWL_ zMTUWaJ!!gLy{Wh)Xdq1>5EN}J>=(5e7zBbq*@=z)%JjH;Q}N7istgPQVIXM^M#a}G z3=9I{APyI!;#MsN27w3=hlf#7U7vwLAQEIQAEV+|P%|_Nl%CZX6%F_p7zCn09Cb!T zP|6aB1tlyEM#U$fHdq`;Mw3yId-}b4Q%UK$k_-$2xgaqeMn%x@jz9rubVrv_F><<4 zgQ*&$&UDKLQ@MIj&jwt3Fo8*S2Ih$>3=9I5Ag?M^FbcGAf)4Ii2c2cy3Su&_2kJ2} z2(*EA5VEk>gTki+l-LB=cYySDfzp}?J1@ws-5_xj_BkN+y&!Q5_7r{w27x}1cm(?l z(0vK@6F?F%>~``D3<48D5;g3g_LRV6kaz>TI!MD5koW?2D-e4cNPG$VRW$|%f$1Re zBkWT_fjJ8#eu8~FD8y!i#9y#;D>E<%%mWR=yk3Mn%v#fxtdcKd6XN5j312upcxOQp~70QHX&--~cH0 zqDw$&@*^t)1E;(k0|N+y4vkor>U2VZ5a3v5F8F!c&7zD0@I~MGq zkr;uSpoGT4z#Ih%lv@UJ3=C`~0(TZp*KabFsc!*=+GEfNDhGHNUEm4G-U4t%B=8)> zE@WVq1}SFNm!%{Zx}Fuhdmg68{ep(BThOXJ8Ou0G|}D$KN^q zW0R>u{Tew21`~eJMR@|Oj3D2b^2dVitmXn25Z3%bpitlemufcrDxfIi1($aY{8vCS zd|(+D{zhF;w+$@g!M{-nbm=u%#)rQGnYav#E6bE|53n!0zYcm-hoX22y(S^UJ3yGB5}zf(tkSetA$cKtK!36Xch_2FeNA zV4e`ayb>ru>3~fU=4aq#0VM!V&{4)y6rim>c?RyeAj1v7C-rj&NHH)7I5I|QfV#^L z0*e{tKn;uQA`A=yOTgY|;GZnZz#y;`%wgfroIbzB)VN+$fPq0^9aym-|0@t@J(#1; z0B*v8Ze#$bOHl^y5N-wrfsKrykv_f*fvt?7DJO7OMqnEwDCINoM}REY4(15(FH~S) z5ZD3cDDa;Iadv?@2K?k~Fz_`9oMfB?YWxUHzu#&qY03%;*E5Wu))G6oiz{#zoH#l7K}UrNTm&1>$L|Y@ zu}feMKflIw-8NIndQjI?;4UL*JVTt{02ChgzyT$}z`dS_fkEH_BOB-@tK%T8ufba7 zEEokoGR{Y-$bpB!1b%|Op#YxY5%|RjD)7|!EkP;gH{&x# z1_n+3qo7jY57=Rr{2#;^7zFsh^D9>T9UvzNfah0i_{~A_DaZt>u4?(gwUrQfrbBBg ze+Lr-gMb2<@jSk=FA3%lLr4$P+dM3%+caMHr=k%RI(miG%aLORb^l>;131msYPJ-7&35z zOxO&%gaYaz&=pSti&Rk%c-acd}eY{1J$~qQ|kr3fWwD@Ul=6vlgUMsfgwzO11Pco zVv?W!r_)ra9(0Jbz(1yI91IL@Eb{rFWcr^eM3aHRgGGKTsLWzvj?x63SuYP7j1XXD z2A!1ughjrSV8T2>6Le<1d^ISRO_@Qp^bT=(4^TofW9DLHV7MVJe+#719L&2TE)P1& zUBCj&dmt`-Hx2XunS5?r_^YU}2zwI`auFn9)t{2!zEE4ipK^A#~{iz}$?+B_7 zeZbn)B;*x27#IY6nWt%j4w;t+UC3ESaiYO;JSy^4pv)8l=JBe? zcY$n(1*;TLkmtGYU_b+s^R(Y+QmZ_R|mcn#u$|lxJWN1dppQ zu@@_YraD0lIu`aK&}=~;h|R{4TTsj(*bicJFfcQNG)#D>$-uzoAvo=~76SvjzZe69 z;B=5Y1AFUqy*^WG`C=6Y2En-?AtiPXRR#vZd7vbw!jYC-#2`4|etJirsjPdS2m^!Q zB9Md;dpBrkbMZ=61_l#$UjqgP!6hKgE)2{kK#p4KrNzL&{9cBEL2x}toY_mCfkAM$ zj5Y&T^%erL7 zKs3}dFbEZc#^#to^T2{XL2lp%_2~uK89@ef^K&vV2nsNQv~z>6o|0q)naZalsKD3* z>dw}&F)#=!g4qoG79iD1jFUjitoT894+<(X&H&v|&A$fZ3KhnApzGWCzsfQ&2&ytJ z(P5}(5a8bk^1T}4Djfy}5&lP@5K?CZC1(kKOLhhZK@G-jIt&al{7oQDnv8pN7#I}z z|A;a$2x>7N(gCfk_|3z>AgIlFLWhAtgMpVt5HzCCVg@E1!K4qE1m7jYQUPXz!i$$> zp0*nU124-;u+Vuh`COZUft!Vyfk9B05p;Y2ADf^NqY-G-K}?B(LC_f73}N7x7Ghu! zGy!uM`F|@-KR3ZtqMiZdc5|>G3;#_%1_nV3Fo%_a8?>2Q(2DVv4g&-816c+JAudl{ z1_m(@Qy4r@D(pH@mw`cKD`*jg$WzcMA0n$bL5r~Zr9g|YKqmmQh&YNeFtCc$NHZ|7 ziSVd1FtCe&j!@!YUvriM}Y#~TBfK|evRXJFqT$-p3-@Cy{7EbJL<3=G15Kx#PHSIaXn z2>%7KdDxjW85o5Bu^BTk2=JSLf(p_N72&UzV_*(|JF@w8@68s)&3=G1o zj6B8+3>N%V({m@AN=jQRF)#@8fs>gX|7tA;24Q|M$DZGJ`ohVk!u6m+!-YSM6}0}F zkxiR{p@)CE7z2Z_I3q}A0zc@GZedCAsM!tvR%r$XVJUDI?+L#+69a>=G}s}}_}}p} zFbK;s-q2)Vc)|Z4lsx1ZA8Rr&yyOSnS}80K=Dgw$RA68bRsv_3*Ziw>7#Qk>l^H=v z>WlmukZ~$t<8m0~L5B$mtAcrXjPlQQ7#M`rzz#29lm}h9C9Dp1MIod722ea}fO$oX z@;c%S48po#mBozmn*|vdgbl!QC5-aYvJ4EuCSWtm80Du)Ffa(4)q}Yepc)Ev=z_{+ zSq26lM&U?CP{{LxhOUI8!1@{ZudpyM2uCx5G7bwQ;A6o7&jDVaBpe4eNrV3}D2x&q zJ&YL`bog)aGB5}yF*+H8#tc?~f+ZQO#{#^dN;rjay5Uq)c}9upfm2O|8Rtz;ooXsy zZv)CLxnSdR_}f6v%m;Jw_(As-3m1Sn1^f}9G*|?7ToHdeC~8ZwAH2SN$| zCQuSD19!bD_?Ig(FbJ13E-_|csNqil$y73e28SB>Z-Fk!ZD1^BVQ^#U;O77(vPQ5) zJ^af+Nwf)UTpzz6C@nTKt}U!tG!^B8>8y(>1+y9WH9>B*19L#Fcp+m32JW|@ z=&@&%GX^af6ZU1CWX!<8p9~W811qd&fSBPA=CSZIgCZ>e>;Mk_7?6tt!5mHo?jUUj z2H_ya5Mxj!0je;0S?oZQ%PhCG85lT0aSrkXxK$(1zzMSGf-$r?!^FUS927~589^Qr z?__0QU}H4|E({D>chwmf7(tpCK+B>T=Omai zFld9V@u&n&_6kuRrv@!$LQVa|XppAjdjC0ma_nK*{P(Kx{DT=8G zY#vCH)=Q8dLO>w|S}@5t=b{gjmIB1WI`zH%Nd8V|~y$z_lRH%mXb> zoipE@fkE33bk0^_Eokm>9RmY{3HTJVdXSXSb90LQx zR&xdhh-WlFclUr(11J%JQbUkAC^d*q=bUXS!+O@0fuU}?)@)Pt`kN4kfg?GFsf0nD zF^=ssV-UxG(1KqU&>RrBSr0NAoG%m@B$k>pFql09IdT@bdSqZ=0A2LNI48!Efk7KI z6U7LYxW&N0pbZ*BW}F3@uw`RpU@&?MI*M)%s3XZ3V&u%qAkDxy7c>OMG%-NO6XYLo z`#c4tbj$SDvrXmepSm(Icth_tDP~|$1MM96=*qwl4;G6CB|f!6&`xZSpTJ^>6b8D$ z!Hhu-bj!zIR|bZ;DAE%Hq0*phoj@jT1WSXHnHs1o!{Nrja1^vnAC&w-R)cPx0Gab- z`rJ9DQmh~*^YlG)Or<12NG%Pehr{FWr0qs%OX_I1LU_85Fy7ydDb?;r!i(raDi&|JfQ%lBd zAdR4llNdnPKrzlKwSq;#Ly&1%ObiSL;3#+qiUP)9h=GqcOy4`#R1)k1rRlflno6;P zGQ8vTUvo{RAVpFcyhswAZZgkQK(iTi8kP(=W1E4~>QyTS1`W`5H*h)w9mx+$XNRmH z>8xpd6 z9Sho}Z4J7&mC+tt888NcbIfOJc#e?(O~HW*V*@0gPnvJ45)4uVPW$2v5+HLd)Il!x z0h{gwHa*{lfx#N=S|4Q7>uvCxF1Nr`B@v_uY`P+Y1jrnV_nv! zaX+{v0xF4CfXc2p-|ZL}tSY86E;JPj2Tj$cF*7hgBIh6^azJyujEBIjl%32B47Q+2 zUdF><{v&1v2C$>p?ct6Br5SKS0bM2rin}wmkhp7JXey%!Dmm1u7#J9KnK3ZD0N>LR z1-fViH2eoDtVE_CSZJ!w3M#BDroUNeDz9Yj#=zhWy^+L%LE{B9_SAlX{mj77WCtBhh?530+EK}~{@fx+L6fngg|2wVdiGH3)bGBAK03o3{}j(rO? zZS5jcVclp@w17)RkpI9zDajxK3NQ;#&=JCdOrT(l0jG>@)88&KmEZ>(20By}WLTy> z#A%v~O@&$0-53~}raLY+72yIY(u@MRe|r34Q?-zjphiFg6KKL4WFY9+4aPYZTR|mg zFW3suej3I(q7DoUR!N{p>jkUTVPSx@GK$?87+9efnHVu>f~>Efesi&@0^0&daOD19 zY%0bE%4tqprb{m|)nkmC?zO~JJ_>wxXgN3~uVrOm&;act0tX>zLnJ8RK^vICH{>vA z1Tio$fMXBjaA!9LhDT5v4H+~hfSM_83=C?Zg0tI=fx&kA;U%WNR%h%P7y=+SkuVxD zXs|OfFiZz26JTUu0Lg*2BZG`LX3#K)#)Kv)N)o_LB+=>dOHBppLqL0+t-;}-4i4&{ zjtmUepales)=Z!U1dKsypdbSU&vmF}1`KMTdSBd@f#E$&2-N5?V9)@ynihj1*4`6z zN;G5!0Tk?@%ZV80bU8tjG>8GJW5tlmBTz(uVm8SM60?%aOl7=57MD7K3jHWX0|re{ zs|sW>$YTZ&OCiOH{b|sNX=&i0Z;*u`M=;KL;RMTX8BA%@8MJ(E02P@Z8@B z4oh|y1_mo|O%9RqU}IpgwFXxt4B%1-R#G#83j=Uw7k7bYc2Hn~QnQ*BC^fq>Fl=&$ z1We{~Q<-{DGx!+fq84!N4Z7rJohbvuErggx3IhWJD3yZm#M)-b!0;C;32!`VR5CCy zfI_Uvpt#u$2Rq&Rdv3+S}O}7+i`< z7#O#L<8Brk0|U4fei2mbfvS@`AchhH1H*GS1_n(~BKhnFwglvD23OGOc&sOwUV<)$ z`40vXpt9E$ltx)kGBLU`fR?I(k_1>h!A%=fP#X(@n(PuF(~Qo7R>_-axWWRSmt{XQ z1B3fS0R{$6WlL8E1_{viI*-kuIhq`1(9o>sK79rT5auxR{3F4@0K#lOp1Mj547$@z zR+_3h`iL?xfG|h2rzkT60~l*~o)%?b0AY?q&qhH81`y^*_1q@UzyQJ=Io^9^85lsA zch>Y-D^1nv19%x2Kv?V=ljmP11_lro7xR8B&cFb|VmFw)xy2b6K$wq*&HJhZ0|N+) zU19R9RA68LVToXG&@q}I%zv8Ed%pk!0|@i)X7u*dWMBYcv6D>RvYZSIAj}`l=* z+xM+9)zg^Xv{_qW`nx6zo#_iC%~+=MNSX0(kGO1lfn~bELpS;DAva8GjTsH6Ut}s1 zX0|jkm|oaWEy8Fxy--F`gwb+(fGCS7lcnMG0`+=PCPOo@EQg`78G~L@aq;wx%x2=- zi+RkJaa$RiF~rBGmF6YK$E#QxS{R}5P~rdFET;!cn5lrwu9PrSW-_zfK2O4| zNKf(%=%O7^+XmEjLt?+1uIX-O?P&nI4F@Xiio^~=VkaQ6bCB56k=RS7uXQ&QH{6dT zbQ+0$9f|!0iT!i>S9ddaRS!^C59$igf(}L~I}1s?e0pN4x;XD7B%$TgC#I^4PoLvq z#>04i`oUCnamJ6+4|

*Gq!#zkwQ}hs3r*V!I)+gOJ#9NNn&OJWzAWk;LaCu`eUB z|3cWH8kB)S2Xs#kRI@J#d{t{61s!Leu=~e-@pSkl?Bwdg|a1)*lN>XdYLIR`c3Ec zHWT;EN0O;QVuPl*V9uY9Bz_o)eFKU8bb7A0nYbha=-L~orJ_h|rRj6M&6MlCkc8rq z*f~h-DkOG45_>ihdpQz&GZK4068kg~`#OXT+L_6~@EF1Y73>V}k=VbH*c_k>b)fzb zL1KfJslkFJ8cDnni9G{}y#$H9fgjYeff{-gN#fG79{puBsO@I396n2)EtAdC6U;MNNigqb_No=6p20E!r#opkP$S# z1~rWri7ko522J3@l2qvQjs9lhp#@0NpzWhD=|xE5YmwMHkl2Tj*r1hRFuhNv%LbS= z*O!29lYzQuE)sh&5_=^Qdjk@C4-)%568kq2n;mrD4AgvKB(?#B4atGd5DqxnL6gQX zH%23ggQovs;^0efpoZ2Xsp&>ygXUmh>USfFA4g(e7OQ7qfGN65B+iVK zW07+&Xz4Iay*iQ_VVLvgU!TwHzUa$ znEo}`%(|WlG|C6nD1gKUUjhUb*Fh4uLSlO$vBQwqDM)Pa#XnGU8j!^MAZ$>gU|^U7 z;ea#6DkSy}BsTaGAgDoCki;J$u|FWO{~@vUL6_=4^;#pb#I{Fbdn2*Kk=V&d?0h74H4?iWi9H30y-;?#UAS4?^c&(% zJf7eScc3nH1zm~*Wd|X#Q<2!<3wWSvYLUb{r}s)Yfvy(WE8!%bco0eEEE4-B68k9< z`y&$jFA|#*bfXT`Hc=$D()7j%v(xnqpfN9~G#?UM28peO#I`_UgKy@6>J32>PeNiB zAhD++u|dm=8J!qFgCz_M+mIvTanm@re{W*{pNiDT4e&& z{dRg`j9K>d7cpi$hP9xpVW8sONbGG$?9)i>8`C9Y&8$_WKsUiawSi_8VVT4lN!(+4 zWvp3n{T3vllSu4qNbFZgY|wrcm~oPznIxDsNNf`%wi6ON0Erz3VM7YA90&(ofK?%} zJCNAZkl0I**qe~p2awq3kl1&S*sqY-Kh%(FbvDqTEz~z6NNgn}wjC1N2Z@vKz&H#H4C|2Cdyv?tkk~hn*w2vIUy#^LpfOgcX9SSga!70)4WwG# z3Q58Pi5-T-PC;T9A+Z~f*nLRsIY{hPNbDU5c0I!}1c%`Y68jMn`vVgD9}=5K6H)(w zw&K7NrUsI@84~*}68k2Y4GMn-28JhK4mkZWd`Dt4gO1>W1|vTbTN;V2j>L9AVh1C! zHCE90Ya5btLh}NbL7W>_13scF>?FRId;c+Z@UU``-!5 z0r}q-iJgbUu0&!_L1Ke12!dL$3Q7DZ68i!Y`wkNOg*Jm2yixrZNrG#7WRh9Arkk}WH*!PgwpOM&%pxaxZ=I}w-)4!*gMe;U5 zIN(IsKRq_x?0S6_=nfR9+72Z4G$i&CB=#mG_5mdJIVAQSB=##L_75bsuratu22C0> zFn|`bz|x;7L;~zaPb7965<7eP%M3H+`pHN_7m?U^k=QSh*x(yapnhcp-T47!vxC^+ zBT^X{xJ?i@aET#_8-duMnIr}V1`80I4SJNnBbYON(P2Y<(E3%7yTO;2K+SFfNppcj z85r6?W<%K%LE=y~vq5ao7E{oa7>ErOUj<@A#n*$_P`x{l*yliO&~bC1!#J)ZaULMC zUm~%;f!I)k{v)x$x12!5wM`iq7@=%0Bz8K84Ru^0hz$*pQd0&7VIF8_r~@Pcb@dDo z8>(nMhz->YzUBn9YKnn@VJAp4lzjwA%|#F!D*gz>hU$F*VuQD^GcddX>4mbtn}SL@ zD2EZWFbk>yeEkV%p&A1N1HTyq{L%sN^(Rm@8X)yhHKrgoXo8i2fx!vHhN|%av7zDt zAakJXXplHa4XC6`1#zIh&jPVQ5)2FsiNaEn@QlJ*>MiM^=VuRLy zFfcG21vvuBzF@|{pbN`Gw?K-ZhTaFUp^kWk#Qr`#H^)r8o)2_+325ygXrVQT4K+^& ziH+-K6&H{iXxj4yv7zP!gV<1W>XF#HL2Rf~j)K_Y&?Ixx9JIO_l1Z+BB%q4!f!I)g zJO;6$;%`B0sQ4!k8!G-EiOmbTyaXyP4q`*q%YfKWaV_x8Do~CENCJBLv=0(H0f}9Y z#GZ%5-h{+HhQxk~#AX3qDgrfM0>%a<84DPPfdPC|3L{ieEJz&cIPi5Tpc!Wd28L|V zZ7NW98Iqa?5F6^tUL^KxB=!Oj8>)A^B?E&cEXnKzNk~GX;2_8XDEkaZ9O{T`AU4#3 z+tc^vB#HZdLK6Cq#AX3q7y>my8Ho+P1qCYZjU*lmVzW-ac1%aEz6`{MT3HKXOF^6k zy75F9%I-lDpNhm@4Prx+1Qpd<;tI|amH zU|`q{l7Kn_d|e8ZeHKal8i)-w=qHE`wG4bM3gjkR1{NCz24N_hA9TS8RE;bWTiu3% zK?+oMgJN6(3XbfE~; z0`PSypw%G^3=Ha^Yf+$VBP2DpAU4!-P9Qc^uP=xV6%PWjq2h56HYk!97{J%5Ko#Xd zB)|>=U#9{UuR{{=0I@-WcgQg*|*MQj2DBg<1-iO3KZVO7JP=n5bB%lUe zLt?)~VvB-qEP<*4U#9|P`yh#jBC)eUY^Wnjkl3{_Hpu_YAP&@^9whdBB=&YB_5ma| z_&OD+1@}SXQ1%NX_B#+8YCbRMdJ)MU8DkKgD-7?s<8&Cfrgv|hz%9@L1ITEvD4~79H@qD5F4tY48(?t zSA*D4@iq_}D&7rZL&c|o*iiA=AU0Hd8Hf!P2jBPtb@UdHxH|Oq*5gnP$j29u*pHFe zZ;;q_po>wU1_dIqqmbCSNbE8sb_a+JjqZt#4E69!GiD)4ECjKkK3D-_gVt;_Ffgof zWMB}6vbTf8p=yqT*ii8sNbC|Y=@R6Q%`ZWGWdQ&78&6Lbp;n8Uyz0+N6#0^jli z+MU3_z@Q8ghpN#*Vk6)3;tdjq`YZ&A9SdSZ%}EBaq2`o<*r4$+P_Rz`aiA8@2C+e_ z<`@_l=7SsuWv>E>L)9Dvv7zyL48(@2xrxMn31UOle*m$;t791$zJSbxvg`kYB%q3T zLHC(JCB%@}3LrLAjW&p_4{|aCgFfgY6)4*ZBo0;M3SvVY=LKRz#Uqf|DG)Y9cOHlX zTC&T)z)%cgLxdS>kl2$zY}VW| zq3j-zI8@Da5F2VJ_%0SGdo@TLs(uR+doP3yDYU?Mu0R!C2T4E;eUHRucLk45fL$Sh z#8v^ZK}%j47#Q?HY^Yv)B(^sa+aHM?=87~^9)%>4INhvpVqZdH-$G*F zLt;NeV!uLSe?nq^Lt_7fupu$U5FKswB7lORZUnHq(u>)3a8Z`7s7e-?`GvpXtiE>0GPK{Fok`n;x~w%x`*v zgDK1OHLJ{g7zL*PTxI6ZXfoY%wV6Mo!}OUTYQglEAj)96<8kI`j%*ts`7=GZGJVztGe1U_=`S~!`7_E)x7=vv&$wWE zCx|*S{pLoq_lykFPi`{vXFM=na=Z*4R4WAvG> zxgDhF-t?;NW`2wz(@$ z1UvmFh*~h+bC;Pv)1BwjXYDfcW8|3rau>*e?UuXE`WYEdOh38DOq=Py+w{0PbtTr6 z4-5t(hr#I|16JXk+JAKk#Gc{I;GzNwrkPD11 z>@^c$w3+@8q+B4Kf#C&2SYe-;0PhQHMur7U3=ESP7#P~7GhQ|jo*uBzjDz(@Is?P| z>4p;mgr^tmGZSF!nBKV0Or7<4DFegA>56BKg{L0?30F+N2om1BjDf)dVyeJ?GXd7u z%NQ6QK=>B>%>)=XO!wSxrp|bJdLf8nm_8Fkt)6}mM9EBl38HwW3m!1jVuN0Z6u7KN zg2lkV(rmioR0WOgtq07KnZ=KSPRRh*3M`CEKu4(kWoBUTR{&jzBq0TwV`XMy|0=@3 zz_M1Ifq_X7v|p8(k&R=z;Sn>5xJ(TO1{Tl>s!U>_W(^CU90LR7Tp|`b5K{`&7GdUK zovzBjz|6tUq{P6$%))v~97M6N6k%XsWnpGv?*yGb!pPwz#lXOlDGWLp0#qNdm``7R z#7rS<0_bp3-D=QnJ=zis3@nPEn~qpmI2agMlt4GjurzWqFt8|tE z11|#uiw5YjBNlfB1_l;Q(AGj`My66m1_rhamFbBRMpDzwkD3WF)yPcmmoSoI@=%`M z|JGPaYKII11B(-52T0*}(Am$f5H=g{^!T4vQq#8{HPc{xGX36BGiAmr)0vK$#Tjyf zn!o~uprs4~n?NUA2u$Z;U|<%gRb*gb5qJVRFoS_*p&00%rfen#29_<;Cmu5s^PDEg zz`&-b4cdb(RL#f0z@`skvj~AU5V08;GBYr62w6%nFt8bdj=|*-(i3A~U^4=-1%yB= zc-f3WXG4exbx!|q%uGBMblNVP*-Ox6d<>i{o0u3FI9Zm1tn-&*U|=%`2?+DB+2k`b zFbIKW#@TEafg)Zg4Rn^G9f-{$qyneFVBiqAq|Cs;DNrH7 zz`!NI&dk8TEg-j17kZ2=PudU3$z|k`cbP)O~76t}BkR%^SCj(2RECU0_qy%ulC9^Ov zh_HatFUMTQ$E={!0zsqx0wSOV&jKqzC-w^zfv%Ba0w*OH z7}y2AgZ&O#DZ(jmUJ>N?US$Rbb#8$VphHsy;y{~~1wac~`2^ggLHD@$fsT0+&<7pn zBXDZE+(|Rd`ff!A21$Ww(hLkz0-Ev+4AKIgatsVI0#0lU46*_RstgQr0-Hn_7~}v>A9uSH0|Q4K*h~TLY|wRJ z@nGvExLHAZ5}87n7#JkEd8ezLHdCuV20Gw96>N?y13M^xHL^1>aLfj6F=Jpm#>v3I zkj z6u6gybT@!CFfy?DgKjozWctX?z`z!x#=yX_kVzMGrmrmr0|OtJ04Hxw7LW_MI5LPGm2B(xdWN2flcCon4}IiiHm{lJ;?K#%$%GI3|!0{Cd@6I3=ANX z>KQmpp+*&eQi2)StBl-QA`A>17GMq&1Dlu-0|SR8_!cKF9u6DuWk?|13>>yl&0wF~ zLEZ6NiGhK`9;}&z8yxHoU=Ak(TQDe*J2Fq;WMB}L;BaQH2VM9e2KJH**eEg39%T+! zaNvqrfpU@?*xO?Ips;WUJ6!BM$N~?rGZ@%ZLCL`re66UfJ(%Ru-yPfo(}6HkcHo;H-0k~5jrK$z`$X~%FGS5Mv;5^gESk7 z`hB2;;K~ZJnGLkhnIj0owg9<52g23?C9zU4n~RI1f^`lz=yEzxR;XkJl?4pk)}YK+ z#i|RsY>C?fl<%uqT|t*EaXWzOhZ9h7t@69JQ>VVuzD~t$>Mvp`N3THISQu zfs2!)k@Xqe+$Lmmn~}|JK{mG)VlD&QEs*hTtSdk!MR0Vo7J}}Rvnp9P3$4KsPXf!l#~N1Ju|ZatsU{8(BenuhpkVcSA9DAV_ zfn#DH)cy6~sMrtj00Y|BC#)Yp7do?~EDQ0eWP`RqZ<_GFN za4X3$FmULCIjjt9%%D7_#|FA5ii?HAh>b&lfq|O`RR0=-H8XI}1%;6bn8V0j4Jv_5 z*+AtC6Zd{l;cf=zFf*|AfyzO1wp08J3|ulC*7a=h0t^g1IVIT)95!sA>>fN#2##k6!%?_G6yh6nt^RED0m#%Ks({MBsg5y=73!IA5@6C zg0FUA;Qj_mZ*E{aSRf|3vw>@R5e7EUy)qmgY}ueYM@2Zi*`C22HVb|7~Iu&n@@B*78PW+2GGzzuds2*e!_lS08Jv2fRe!z~P~ zn+@W`aIlT+3~Z&KGA@D*wDpcloFj@YSCD~$2Xr|QM>JRo12-ER0|Q448xN?z!2J#s zN3m?63PF&84Rjv}M;seyPoAg@M*`b^K?Vjf&;|&OL~xLc^@D;hsU93qVyi#_l?=8) zEELqbO92Og7#B!UD%cYYY(*>#3>;}}m4XZmTpS!3;MM~-=$c!OOmI43;4TJ5ZWdUA zg@Ka=WGCAqP+HAqJ1xk-Aj-j!%jPZw%h!2q`}pe_7$6xq9~?SjFG2aS1f0Iamhmw# zaFnuDF*7hofG%6&C};aB$iTqB<^obw!Nw@Wz`*tt)Cj3%ix-0CP0+4AK5(`HXFm{^ zfs+MfDVG69Gut}QwXB&%3>+h zaf8kZ;F!lY8FY9pcRZ-vna>6~Ia-8!5y*9m*ye*STjKr%NMM3@FdeF_z0^OjVr+^0!s1KMAI%bW5?J=l~*b7PCmqF#raWI>Ui{mm|kO%`q zJrC%XCXOrM?7+YSx}}NZDwxB>9SAB2uYox%+{vK8xDMv9ao2#7=nb~tppao;djLu& zH`&-l7#P@kLCN7BTNdc*w-ylw25_I259De-P#+l_5ezKWpi7dBK}9Jq%OW`j22KwU zo8{W{c{j`?6~aUr7`Ow)85lS#8A0L<+-DOf*P6Is6Q4l^~N_88?V9FtCHnDFU^Jpj{}?dKXSfaQm0dON@bm(;9r} zFe1zb%oo1FReuN$A$}S+~rr>z}DG zFmSblgajl(H$8E6%mUr?Bni6diK}xd=%y#3S)c;98&ndC2pNIY_ke<2RH#Xvfq|#VBneoVmAnZ&fw;n3G!@{wO%ETBL zSe!)}7`T?a1YM#8+M@|+I)K^_3@jHw9$dx(x`tH*bmI`H%L$fe5Vql3*)GArAhZk= z)T=<@#2_?5ih+S^HK@X16uJSr9eWLk%`U_s%fP_37UV=;p;Mrnp19V50-sMP4%AUx z4>CtUs6dT@fonrA=%y#h0tT*)AQwmo@klZ-aBTwlREB|* z1E6b}85p?EfP#)i1QZ~b!A!a7f9{w`)`PZia)*KBBcl?G(w?9&Fk}1yzO+d?3uK`s<7DuqP118g3C9}j`xHiLLr{@m z2j-NOot`0^iys{Tbw7FGglb(5+3-A~KC1{9$xjIvBZ3=G`sbHKMY z$$}bp+#5lSL?cF7Mo=Vg0`*Cf7-c~N4&3`d9jYQmSmc4&0AHGJIee7w(&C z3=G`-U>OhY$1)5I+yY=3AMQSoiv+>tT>v+zZsisMmy03Xa>5J@zTBdWAdi-CyMbax z4D7fHZcshVEe_^XaUTMOfdu0O(5+3KIqHyx1?W;E zux+9YYzClv>Nhg(Pyh|(b8iJ-KLqX)ac^S;rF;hN%@Pa@+}pt%0d8H8Uw42x3fzt$ z&Mq*=fcqTCQMWse$_>Bj`>Z?%UJl zpP5OThJwQI3?rzO!w&8jbDsq#L=NsSP#tg)Y&sveDJXU>fjRu#2Get&nMu}z`m@}3 z89{>};@sUJzuyA~iUb22=v*f52aH0X*{yXTt*^mar7Re^KZ0*q;&um(pML_g8My61 z0sonCHRy&WZXHm$`GpbGNaEl=0!rpz!5-n^UIp^iH^z;iOKZ53>Os8k;8ZFDp8Mhc z0p`eo8yVa`!QM~+&;4-!Vgwa#YTWxlspL0f4d{j@ZqP|9+<(9hv*bPv@+}{D=EaJ; z8{`B5@XU)1Hw!541eripQ!O{RW)cF=foM(T?gM291u$M9r zEav_N%HZ~3*Dc`&?IGrN0Nc8Z8#E=w?FgQdTF!j}6x2>&JuA4)K||E;V9rWz(Cum5 zUZBg8>KRt?fUaZW_66U~v_?7x6!?BjpmwGXqjUr)EIiWz@yjPnM|PRN(SycP`b}n0=vkO zyA#CA0UPbaJrk6Aa+#KZPA}y?Hl6RKnWFz$6$S>j zYzFQ~kP~MyfqKYt+&e(#%m#;(2KN+Di9Q$1(cWvL0OKECk=NWWfCdlz$e1 z-DAkW4l)6BixSL3aiDr|F_SI0(aXJz={?A51yC)p9L#3mZU9xlE5MEejp4+Bdew(P z`DrE7X;sinxCR3Q_YttXl!^-XXQlu(O$G)Y&~;4QU%&yx!2K9hK>uV40A0r<-3Mw) z{9=lpZu81aseU0S75-!D;Q(F7BwYmJ{bx!5U&kcf4JwRSnA5=5F-h+MWhPeUGED}C zCoIyZLDsT?JIsGrq}@Qtk{!(Z%ObrEWC{wWon1*p3<06nH5v4LTr^+YzktmAEuGb-IFiuf?Tj zP8WP*Cc*()+WkjdT4cKJ8#C#86HqXFft|!6A?*uFdEQ`usz^w8fyxXYuy!>G>GPmO z<;ykj zSR1HVVFwj8pfCc~^uh)-HM0qO%0|Qw4A_D^hNculi`rmVL9d}Q_urcdvx4p&5}yA3y_qsMNW10& zup)?7s}E*k3d=w%vQ981=rAy_fsbeXuMN6cN9%z&0|U!Rri$qWAI!wnKq0IPYNRvD ze*-N}0I&-ezGRleR_s%0#Cgz=txYciC#$TIwUseb{3fL zuOo^7Kw>L_hL@q{=pnJKkl1cW>}UuZvfVpl`c*S?eaX2HG0^%hhD}K9{nKU5&6Ope zBMJRMVslQ9G&hfzECL;m33Wj`5_`(@i{|FylAsGaVV*dGBz9601zdcHWGIfrRz+f4A+g<%*g;6_I3#u!61xnE4H`{l}c>=d{7MqND{Tv-&&emOYTP! z0!@a)%zHT9(aKy|k`r_cCRDdJ65C>Wt(CcQQUa1tDH6L0iQSLHo{PjjgT%gx#D0#% z{v$A*&)Qt9URe+kZH7qfU?g?|5*yS=h54izNxUD4JsXJ)YM{c@Z$=V70AbgIGt^ZG z2h4ti#QuiF<_4XW2@NlCB(^dVTOWz-fy53$Vy{PH9}xnb!2vb&4wA$RB(^Z?y}3ANZ1bnqpV?TEw%HSJ;QBPBrlVxWprkrY)Uv8N!h z!6$J-)q}=|UWH3#s=+G{0ZZL7OsO@mQV{Mkl3ozzdD#JO9mqe zWgxLjryDw&E33{$5?YDG-jBpSGriK$+`66*bj&5xA{ivM782V6iS35O4nblkA+ZaP z*mX$k9whcG2pbabDwlc zCzK67vlGe&pV=z4jW*>Ol}z(;pN)qs!ggt9x4)J#QUFGOOmLt^iQupz1IEQAA2T{n@~Pm$Ok zk=WqVJ)stJf=={=vcac&LfMK);(ADIYb3UZ{B$`t^G)?Upwl;@`atXOVIJ2&5;sF) zyCAWHkk|=G>^vlP4H6rC>?hQ&wGeU05uk@49B?3o^*3&sW%y}4(PUrM6x0YlF^@^cNWsumK(_=l%vsJ+denO?e9cU=~ zAd=E^)8BfS|Kkl9afo^z)S^5Y`{2LOR33OB@)HqcnwhvnV&6hyzd&MtLt?Y2*CR5n z5a_5(s7n=)*m_88FC=yZ5<3lvU4q00tu%r8cmk66JQy3~|1~fU=*BE0_6a2RH6->E zB=#pHHUnt$5!3^GNNgD-wiXiG0({mdRD&Cm1o$#0sCW{RcmWc-4vF1^#GZx3UV+5k zhQvOCVAnHTLU0%!AhF*evHu{kxik?`CV|8TjX1-C+5}1535g9p-xKPwr(khV_%kpt zyasU~!vqZPH4&%6{Q`+YHL!q=(BuZEQ3gRIwgM7c6~uPL-jAy1#j51eex-en-t|)Ug#=X-YMwzQKGEC=;HdkkSI^7UN*-Vd&Hdkl; zYr?=VclyOnF5&4jqRj;ubEdBZ3D2@%V7M{;YP7jBW6|`7ONzv&3&fZUFs_}h7-O!^ z`ZSS&K>)nVciMDC0j3{Qrx(STtFeAfWMKFJ7M{KVq*`G5L9ps128OQbg@=Tc84IQh z#+s|M2Ba}C?13l@h&306?fqTYBrVQnWMpY#WHJ5Tes(pcIsV(%#hS-z*NgM8Dl#xA zU1AGz+GF#EhkGFdLn8yj0}ckUV335-B{n1GJw}Hew3LmO)mj-Tu`o!xv~e;>AL8D! zmKmZ_x~a=}A_K#un`}*-d%BvWJDNQAXt{t@&S7d~U}(C**2J+#t3$fO=4JcJBeEYD z%n}(43`#&!)3s2MyTEQzR$}_~Er_X2d-}s>Mrji_6|mbN z#))}woMq&ZMmX1t-H3|;tW8{rsmndd*q}jV&5h|F#2r+)c!U&O6dW8%+<2zfcbQvm z-`-`uU4YSLd;V;5Uf$^w&Pqy5-@>gYv3<=7^CL|4FEbe!Knr~t7+4r{KvR66-N$b= z7#Kho(}Ghw0|NsS3u|Ux2?H|=`(#4~24*I9P+x;3!w_kgbcQqo1Iu>MmPMg(1_lOZ zMh+R!wqPb!T_Xktmg8Iu4A6bkf}p+ClAz;@Sfte%+!&aoK+_z|9IS8k7(g4R&uW2o zOtVVMgDCceQqYalQHl%BFE-=4a5JX{B=@W(GHC`}7kKGX%8wT5Si23A&GmMdK!j`4lvzplQem@&MCyMg|7< z!_!x-F_*4C&CbBUVhCR9z{UdFYsdZpG~;i{SOi)<4iac$WMJR~t;%9&V4noqXl}#U z2a}rzljCP#2esZWQfrWv| z0<;l{fqmh0*>&c6Ay+^*u?p=5l|4cqj2IZ0gbwgAFfa>&YB3feFBt{~RtAo!Q6>Ra(56-nYo=)+lfcXOZJ0pL zVBlK;TCi^m<}mW{g7&@HfjLZki$NP=?U~d-*^FnoM$I8IKt_#{=6aY4X2efZGkBxzWFTe=AZyFR)41A|`85lSsz;0#Ys{%PZ zl4%<#JMmRd57=lfS$_@W`53SfynKer;C<7eJ5Blcv_PA-;+Q~Y3h+g0F)(n%gPkYA z2RhDyBavx4Xx}s+c;`zJ*Z?U$&{PdaGMFRHr_I5@z>&fP+6E)T2U-)%kqVZPW#9lM z(KA=Xq{vPDVbSBV(QXbI8>PH}-fQ~um$YTO2WZ?S=+U!vPc7XyPA1G=| zm_UA1;wuOFrJfMx$ zjc}7pp(b&Fb|;#FeagsJzYxT;0P~m_*lj=?Wh|KkK)OL2t3fv_@`2r93)KzwxgFFU z{5s%`)u2G*fCRe(*d$H{c5zTHaAXEe2y=lpR)cQal_RW?7u<<)pUog<}%a&Z82xJ23^s`A#*MEWMJU`f~lE--3L@Cn6WZ&L2Z|tK4Gi5T)itR z$SLfgeE=Lm5cW2ZhjJk722h$S1+#fTJFRDec8hNUEflY01yykje6v9oSFvhwF)*<4 z6@f~MYE~!EvJgHSP$^l%Y6i-oe9Pp)JFP)};ACKb2eP7$)ep4YiU+jQ`Z3(xCS-G) zkB&%iMg;ur?@f1ur4vskOR85np# zJFUOMbvqtF_ZOgmUjvCj&`xVZ9tH+J zaQJLswE+2_fiDGAuWV#x1Z~V_VE+r!yor^Uhk=0yw9`5ZqybzUZes-(hrHmO)}V$O zBQJQTHHaz5zz(|2hGQqIEl4A1r}c7>MzBqLk=?%!+5PqVAs%30&j$Ja0BadYw>QTT z){k)AN0D_OL)Lv9q8U_ zU}Ipf0phXk#d(CGB9vlVFe{KZcR|y zzsd@VDDHEh&1~0LK~c`_1WIJrSwTS!US-O0gB28t-0wgs>?SKHV7T9b((SE!us^xM z4!X?>aw!A*Q&1s%hgFxCfr0%w$kd0d$9bW-_BJmAgMb_t1A_pF#lXe_ax439P=)q{ z^(`+013wcV0|TVc0A*|e5W&E{5L95jVddjvVBpt)E2w5-sAmuWEx{E4M=X07sNnp} zY64OQTCEEe76R4sY-}K-*iV3J6+sAl9jI|424?esc3STSZ373F2O4ak@_+$S9%zD9 zFha@$Ew*qz1_mZR(4rX*ZMJ%lq0D?UKn1N1n>Qb*;#v#ZW2+11urjb`f+{OLwq!mA z1|HB(Yw%9;8=wF-2Aj*k*9EFuOu!sQK3e8fd3A-+55pwqpa;w-OLb?7@~u@ri+IQwK0d znt>fOw8Y`a2HM8X1KMdl6SPO&6_kry*+3-=1D^`0j&)-L*}(!a$sMd&grS~22V|B9 zTL!3o3)*S@n4f_G;wT@m1_oZ}PHT`m1Rz%XfprT(jPeI_gc;a%K+zPywiIL%Xs5NV z00RRb*c~AdcR)-E1^WoS;0H4%Rsx(K|8JAfV?IS z$|srNbi%*~I+Kheiwz{f!obD?vXlKLD6M9*od7umwA0!Jw4fB6uk+YIX_Z?ObY~1l zJ~(tB8M1^8l)kt@8?`w~+3qqkFo;8UT7!0-GqBf#a%~0MKLG{?_7cz;7PV|KppE39 zWLzr9z#st5HsCrN#ARS(0a?le+G)L75FCb}oz~zW1czrmM=LnY1$d!5twB->4D2$X z8mEJ;8niJFw9^`N(<^w79Y;4C$RKgZPHT{A2KGEqjnvDwU66r+T?14ROkxAw0L#xH z#J~V900clR1~wLuDLkN^)}USBd<=}BhUP3b5Ql+J22^#=2Jh`=;R7v+;+Vq*y5*IF zZ!ajE=dyKyc8c?XHmq^XW19dnn(qLp+?mfdO^AU(gij0HOYlBfccpr#EQ3#g64#-dRVIw*o=H!ny!0Mun=0o`NEz66vHm$9)4F)*;N z0yVz(f|Dt`3aB7H4rcR!c1(*4GcfQ%H%x=_2Lms3!!(G)#0MHdR*(K-&vA7}!-nS^Xy48IXOTg$5k=*gywv@q2=HcY|Yd3&_JDQ^5hszyXSI zP*MVqV{kFBYyxd3HU^2Z{1s_}nZZm@E0fa$%rq2bVBib|GwUyLFfeeY zf!OSO6&M&e&B4PEJOZ2*jJ_fa419|~d!{SF0}c#)=4#+=*C5r5d>$YhtHC1}OnfY$ zUQ-QN84KS!b_NE{S}=!|?eD)x9jbP)r z_!xK?7&x2293DP9kSChKn)vt@>o72IwtzYO4D4p09oemn%R!s)SvWfwYo@>4Z!T9K z4C=o3Fh+_nFz|42_A~AT`Q#Qz?F6t+20l>4aZUtV&B(V0<%C^W-*=ynIXtIm(d8c7aVN!Jg_zf zJ~eIz2G055Q6)wO_I;qxS-{9A3U>A)@UBYUoYXu9&c#qW)j)n&0v=XkVPL-nTF1PU z(GH|uhI0kue31D8tPImx51NasfYq)BtCe72@0Ma<;9SF)2U5$yxsLG;NUiU5hlA#l z^WT@V1hx$<0SYgWQS6|j=Qy`B zz5wac;oQl15u{5|fPsN?7bEE2V+Ote&>sKYU9rgR0JYzHZPq{k@EL z#TXcP_j?&_#U(XQk#K|1+<5i zjb%S*dj$(9rr21RKzs68gg~Q1ETFJu{{hN4#~I~78(S9}Ffedl0h`6H2x7lrloV%R z;5Qa$U=RRp-Unw?q}C0O1?OwVrQ!?>eB~fFy#Z@w;A@uy9r^GUoFEwa>OtZ14lKpQ zTU3z9!1G-fX@PyhCYK0FkxV0 z;T30KV6OrlEAWL8Ht4hFHf1px}f!z!gvtG=g z79D#yC^ZB#+k(z=WO0^YVBil1soq`>3Ndg4P*jI2qX)Esy%*NTkuEL<2Cf{CxCW#+oFf4p)|F#mi3RPz&IOq-dV{O}izEYsNFYdk z1H{b5pn9zl#AXs{moQ{t;A#TpSQe3spsmx*AU21{^y%40%$4h-^+1OmfYibcJ7^VV zU=V^Hb}&Jhfk9XVwCs;S}W5Sanmrau!D3N0dmpv~#Cs)QLBHi+->CRS{5T;F=E_VY>ziOcqdi0U8AZ9d=MC!oa|_0JO-AZP7I)A|2FpNu`1oC=7#IXVgEC-w22mTXm7u$iMKVBfunH7T3?jy$JzT3n ziJMX6oHhdk*BTI;U1SnyE7V$$6M01}I2h^~xYmIJpHBpIej3+$kU0V(w?O{huuqDC zK?HHwfe0v%aBTwl6jbT+OEEC8v4C93A_+2oGssn<99-Kuq!}1Q7J))&2gqaw5jBwi zc7oVUBIiImFL#01EFzn985ruhc7r%<3@la>pu-N%gU*9h0&SZ=0}48piJ$5Ye0}#%F3&X0G;{C2wFwPZVXCE;$RubVF;eG3=DjrT{c|uU{MA>Q0WLd4FQxM zSol7H;!K?pr0fn~3n*i1F#5|fFg)N}0Xm{W6I?t!kv<{Ez`&)$2r58W7^U+;hZ^XD z+Z7y)(uYBzs0ZfpFiOjS(u_W1s4S?^lzwQyz`$h$wpoNxdKoA$8rL%lOEWNtGD?2} z+Zcs|~W(1v6atl<% z%CUn|W&B8$HIT&T-LA%Mqe=#svGH@}pM3N%rX4pN}a zD0>LBi7^+%(P5MYjr?*KfJSR|8D&F2+p7veuGM3d)dFn^D*`DqVUz_Q=2;AqF=dqX z0d3bS0m)c1%Dw>kyp)ZJfx(6mQiNRxHC@3Y`Apynj-7!;2juliP$+^=UjSWbEuyW> zz`)%KVls#bg1pw|13H;m77>wmpq;GUAaN6sAdvcAkhq1& z1W-4#4;6 zTN8Bpg8y{h)8^v!An6w(pbMY5=YfXt--rZ(&QzEW68|Ey31svlkhUMPnxN^!#UODB zMp@99Bll8J9Lq4ueg|#%TnUmF;l9$Rz`!6<4N4AILA5P|2xy>=`z9!6Sr}L% zKtXUTSAl_>L9~SX&OMM~{^`1B%*E>ufB1w{!Ts5QYY26kKpAE-IOEe_^X@kxL}NrDlyK(a=966kSfR~fK2E`I6PARo$tc|82mt3bgb2lf>ozw|HAQ5BH7g`Zzq z1H@AV7rz4h(xCPTw-%Tu$S>WZ#K6F<4dw~)OP>d2KpjRk#s~%mVSWZS7Et=(0HuqI zpiUO3=#*z*_XPRhfbok00|WaDkP96dLBo+eppzP+l^GcLK-(0!mw>~BfiDYmpvO`$ zhlMX~`iyhtYW4Ry7#O%$f^8Mxiv^9>tYZY}6y*C0;;aXA)FI_dHmGe2vRRaYy#!Q9 zZDf3@#K6Fl!M&ByTm?MXlFh)qjS)OZ!WROvZ9AAFzy~_*n|lYCqrle&+H$)K%!xDL z1MQyR-VNqCfX4&5_cDUU0|UV0f!zDR;Ti!RO5@%S=0t(V;kXZgT^$1+q2oRX=EU;J zgW~WIm=nkMVEXLy=92Z(L7Dy-*xxA(>{6g2r{x+B?8~5o{G7A0sICE`d4xd~%>9a0RSP zfbV%dXg>WWSW1i!G=|1~mk~7ZD$b_}3Zi@9u#;e5-wGN9f57Oh!oa|u0y6G3SP$fM z2hjX5A7~dM_a{aWn}II~6hEICK{v~@@cjej3h3z$d{01G=_}a3JbVJ6trgtg7$2#D zx|iUp^E)^cWxzAk+&{n^IdBV#`zP4V3g8)P?q7_c;#7@q8z^D@W&|xF(d6R-)nR|Y z4zuJ-2GtmR;OSp0K1)#5AON2Jwc$Gra=#!GsLrgNZg|mLn$c&v??rP-jgO$xOdYIc z79S{txi!FZ$#eLcKq*lZ+)Z&AT67qt_k;3i7}#(VMrlwdjXMg= zGX>QQpxna7au+n11}gABsX;qyObqNNKoJzf^jw93fd_P`Lzp@P19+m0JCmtgmVtqR z4|LizcXmD4MUH${ATQ;BjdtP#pZt`|vP1G?ioxEKo%YWwPa?3*$jL&pgb~*2{c$E#}^4om$R9Efx2QE ze5s)0FXn;+REzI3sQQ}+=IHRHfJ~SV=IHT(OS6ScN$Ly?27IERa()rmU4{%CAX7hp zMsh%f2NMJPdQknmm?=*kH15N_j7b5szGMO@{+EN<416m<(YvA^>|)T6i?T2S13T!< z2=0|kf7BTmAboc3)l69$3=Bfipi|C;z&ogfa-~3PUV@cDYhHq6L2F)g`572kg?4H) zfTo`QfKurZu(^=KBS7N3(6b{z@xZ`$6BPeHnRaS3)H8%hdxIkR7ZWIUl~|+$K|%Z* z>|-Yu=^3D${Rhl*VUdmj8U2r`lbwOVjYV1k#QV>5Qk#LngGCyA+7=7*d2I#;9~SAS zpc<8x`Mx&zU8srMO+#*?89x!3~FWU5SKOvIn9h2lnri(ON)XskvW)mM_l?fDDPT; zc@M;;w}2{EORz(qh)dTm236cv%%DcjQ*miqkngR*yl3Ll^`I8M4Vd>_Tv`tlF}7gd z3vub^paf=zaZ=|dnFdV>Q94O5el?gcfie3`j*7#K7pq$5D- z$d6eX#FLW#465|}nL%au3uS509yIO%W^Ek?hBwO6&7cD!f|x;V!4JyPUv(H5xPzHN zh3_|I>15EhN$yav6+e}wIYEu_Ffi|zvNUK72X{D__gh)|ASkjTz`p*YEWHI3%#mQ; zUu9`=P>4h^gF2H8D$=c>K#vB?@u*0H5*K$2n8&Lk?E|tQ7OYZ0MS3e}#Q=8#v!M5_1{oZWI1MkuEW3}(!|BUz>^1Rt}=+^voJ95!)`q>~uNpnH!Q z=VX9%UIZPEz{3kNTo1H9Qf($^yX-q|n9@A(=^0jf3=GOrG7Joi@3=wiASMO|WzbkG z<2!DU>pw6tFsK)mFfe}LP6O$bVP;^^5My9qIH1eGpvf4;XvhHCJ;iVV!e!!cV9?NH zU|@Iv<0~*|fNpX92;nnxF)%S`*n*s@2hs1qpatsJb*D2hXoF5*n>Kyn3v;pQ>u;Ki z*T2yuHUaM&}INigVVGB7agNM~SRHUNt;nlR{BFfcG2NoQbCh6phgGiWkKGna2+ z)MSidG-J@8$iTpGHl2aN8Y0hVqRAM|Xvm24Ga70#MzbN85kIzrZX^HG6cr~NDvgH2AYg9OdLNMK>Izw5%L*Do~e`p zq@aX>K|hdzf#F>`1B2Z3_Pge4Ouy2nufJ<9UJtrii18)J&7jl;TByi4r_hLj!8DAQ zfdL``I>yrME@=1mOHi1Cij+>!`6I^Qek(}ZQjjO+Y&K?KPzLqj8I8eh{;3=c49fWs zm7wbUJjmOi5l%)EaDRg_L}e;y{(#X0tei1a3+|aau(D+^FqBPyde2;e z3nZ;Q6C@4EU#j=bWj#Pffa?iG26>PV4BL1Z7#Ph!#UX<|*k6_=3=AqCK>jyl0vV^n;Xc2kooO1-FzLgBUD!g2HwuxP1zW1!2%a zb;db5Pp2C`Fc(qlG-Y5=294-4HiLC6;ACJh0GAnUOdvUM0M4JD{lHw74-_)`pu1y1 zezBZ>@nnqH^feF6Wh}vEQw9SAgHQ$ogBGYh067Gl{pB(k7&1)3sgbFefkCSdT9j!Y zU|?X-n$GypTtphw_~Zc9#`8^~JsJ@P`F>Ld28&bE4IY|{#(=lma)Fx@ATNNnG%(J2 zVaC9qd;+w|mkT`4c7~IIK^Zg{&dALS8VrBS$-tn;X~@99$P3n~&c(o>1=|RhwQ~(vqf(jWh=vOf?FgRr}Ff>DjK;;9- zYx+G`O}IRgXeN+7V)1kE8%GhhH+?Zw~+3U82~qClaq$}xSzBXbegljaNz%HW(C1@^fc z7XyO|IBQ0MR}3=-gJbokIXqi{i~t7nYPrMN$HeLR)xl(;v2G~+2P)dyk zd6fYiTOj@5JR!y)5399xiC2Xv=gA!2B?xK z0p}`nP_6<^;aN^*V_;we9rnn;@CfX-$CeBX%5G|4QP6sk4v^bGbC-;L;H3wQ!7A;b z!~^ApsDRG=W9(Eg>FT^T1rf(F~ejG}bUMF!Wj?MFgV(gT@X9 z28Kl_f~E{wC!q#vKR^^>|DKu4)PwVsP{=I@HIEfoL6sipY%Y~VP{=8O*YPq2YlF(=x{T=uo|}tI zZ+dPns^MwFz@Tgnii2dZp6j6S1D|q{jI8J8^!?Axwall0R6hY74pjkGEy%;bp!X28 zpS=pS_Lae#hk-$xmw|zy3!XQ^EG*q%2H6*iUAy4I_5Q? z47`;U)P4b#)SwIR80W08WneIOHDq7_F`%g)*4#p92G=Fxc90OZ-V17o9z!!o*bZut zvK>54;4(-UQb>VRf}>87L0)+J`j_UCCes`k7?f{=+6k9gLF{Z^1_l*=K?VlK%dB%8 zK*#?nuK*nrR(^WiH2fZ@R@Rb6F|SA|A%utf19B z|3n!WY(Pg2$}li6{IHvz|H@p3QEYn8D|1;!qv@+&nM;QU*fTJwXJ%zHFiNt4HU#E@ zIzKj6psh{}3=Da2*;ue_FIZNMg@Hkefq|h1E?WbZT>z2=H6j?6O_zCXF3Wgiy47oQ zSMI!sTz6(cr%+G}$m#c7~AWF;d5!$J_lj}_9x z&`)56^hS~#AX)6*Yja^p+en6u0TSI}^*fkASt||_r=YTSwlIhUzgejIzI3KvpqLbU^qK);@7_gt+_A8))^Q52_wC>=+pG9YKx; z9oMMI7|k@%0o3*_W?;|;)%A7YY!nT$fPq2h1*lJK!U}UdXjdiUoDL_L<4ssWj^6=y zya_nLd=h71&|3`ZYnriw`WZSB4AVp2nu|$;6f;c>!EA%bIZanQ9V0e<_FHoyK5z+^ z1-hl)j)B2_`tG;p(vbcJxJjDMz)K;FXt?BtU%&P`z}94OB5RhN!FtH4~w{PzKAzJPZtspmk&n z41QoEHJuq4RMvuO(O=+etQdooKk0(npTF2ZQlKM~l(j&8u-{<*6$u6gEl^x6oWA~@ zxwOiAkoHfY-i#zWsB~Zqf~bb@zDh7K7{^V2_s(2S6x>CVVFv}Bz8(Vu1IRDSrz^fU z7lnkw1W>J(&cN{084|%!@6Dy^LFEpEjtHoCm&5^!uUTM+UvObyPzJYtlEA&JNJ$0; zWzd>?#v~4q9O%L~NG~~w12ms0A;rL8paLplQ#h`5kC~ z)HC)2!SHL0<*hcfARAUNoZtC|`2eF=&I*AFQ(k9zkF#sRzk{=G;}k zf!bkNU{gS0!wH&gXPlGa&cI*~?pbGnElihYV1T55h|-195Vu2Q4}qNX8k9D3z^WgE z_~4O)9I(NRGSHzb2-jJLfx#H$TE<+kG}FWYgYTevFOM_B-I{^H0PO30u&?z&cL?9k zU|?A51`Bjh44W}%fp&m`o7|vc2UI9Oaf77im`~>XI=u`G44}IIFIZbNXb>U>biSQmR~_ zr1Dgjfx!;6>XuOrY#LMj!~jSDtAq8o%E7Xj1{Wxc>48I26RZ}rk3b19%Fy`qAFaWWUEz^#>MV9=WiYUNA;$2e$Sguzf5)OcMD)&)w3jB~2IVSUBb z;4ozjg5;ak;GjG%538slvY?%5Dq-Ms15v;j3W>|LVC8HIuyg?7Gfi~R0}X96t^=D5 zI>EsB2dJU9jtf++Gfi~V7lD=n|GcIbelwR~1%;vP^uBNAQedXd^tIp2r6fSbL4Y?X zBBGckIx<*+#^RWY88WBe|7I>){|sE1Mu7@A2Gt{={#q$FtWE$GCX91ldczW6IX5U# zLCVSsu&O8p1_pi5e_Nh?$FlkwM#ufq?-e2yu}OeFxo)V=$z>vznhyuhG#&r2uf9#L1JRly?>Ysvw`|TKYgbE z`(Z9Kz2S#Bi}t?^1_mBqaPTo2F=&AXlR@#Wbr)KE=zoHm9O?^6{YQS7%gBPlBNwX6 z05p(c$e=I62MEgM;c=@Nfa6QQOVn2wtpbpgb z1+CT0go-gRI23^fj4pu91@#vh=N$8ch5RLMP{WZccLc;Fw`?BF9x|f0zBgR93I~hkfF+8Wm`~JEE2p1i9?ZrL75#i zP!I`TYm}h~OOVlwhy)n}w&a8&1A`uTWFihcBC4mvz+em>n}`SV8NUd0&aOjc_Bsx z42%$!jG^iUpek6D8&n0iDZxB02KKlfXvtbVqc}HcVcHTU1_nLQ(qTpkF#j+}@oG@( zN)l3lf%djDN`dF(9)Z+u0X6QW!46oTC-Wz@P#i0=NmTrx=6mz-`IfT%dVc&@2NuLhpdupaJ=NVD4pQ1_nqCc^}N@P+?%u+YXAyhv1f! zrV0atjWz=V18DyBbO@*!0~#^-zy%sH2nH!;0u>q`z?Kz(noZy-o7hYShF2lru$r1^ zA;OxO$-uxnwaP*+bt)wNGffNtWm3>YPb_!@R|&L5it!|P?f^6t&p78n7z2X}=q?q; zlT4u92#i6X1|NjIN`-;JxE^$h-DxJ!dJM)OJ#Y$#9Di|R>R$`lFn(3gd?Bb6eI7j7 z5TeS!U;`S{1f2zTEfnUJt4tuT)Pod*y>gWalxgOH1i^(ZIQPOPOnAc}NvM_40@^kL zO)h{EmkU&852J;!J*YX55(f4@bI~3~aJL@hUr@RMwWLck85rsy^5AY)G^i=9KL^?& zn>(G4$wG=1WXRs>x=a?*j8mt3GFixlw1Ju?5uqIDcvqG^K$I>7^TV$&0tEd=VpXJ;P*U0cD> z1ukrtM}WEk42*|(K#{$m9;Q`5jZYIMXdzHs{K%Imc zYS0$uaUM|g-Bn{?umweUS_C|@!4ja8DM59&AhhKRi`}^q;LxZCZB^D}gpDF;)i5wH z%mmFQv$0&4V_-0R3kvt=U{`~REyg)_A{ZDzrRa08s~LkJQScHR1q@ELpd<*|PS3y~ z4ECg|73k0=8OVG-0|NuZ5Xnde=)`}$40z_>K%IesLA4#!tMLLyA*d-0ni681Qy&S7 zb04HQ_XS%Bj&nb-20wKM27NUK1_n?xDu88R_2IGch>gx??w z?lUl?GBD1`jbdOh-3B@q|2JrBRIWM$g9~{4<}WB+^{F#3xJrPgNdAH5x|t>hxF&#_ zwf`aIQJ@}ZlN2KZxSavIj7ZBAngaAe6T+bEA{qq_>gm0#7Q%+$W&o(62nqxJ4h9AW z&?*SWD3A-InI;B;N{WdA4Ek3X7#NmhGB6}hzsPDKTMsHA7D`vH6PUH ze8LQxSYiw{0Q>71Gss_h;5d8E42m?+aw0cyZh65BE<%jKarP3tD2r)gfH62iUs*Fl zqBP7Hw6lxxHIy3;iPJaWB^~QQ!D0!EQ&5u@6sLhPkT^Zb4vka&BhV79I0h61(M+&O zFs*Aay)U3`zEx1YH#sf%>p|-!z(EL__W&h@%TWE0N@HS}CSxqq#Bc_ET}DWP_zISf z2URLeg$&5iV#dh807)ldpk}lxc=#5SPP{;wc+T=TSXisFfJ&6}ps=k62R1~2F<1pW z&7caIOA1jb0*!sCftPqNhC-r24KiC8rUH%zbrx_mgd2fwQD#(U0c9W1G!r;hG+98g z0!eLJ;3+525G7;~4>WuZ3dXaHv5;_d<+Kp?1SdSuC^e{8_bL_?j!{e;3Jm(7`8SZ* zUx*l^1B3n^21w^mFb=BBfk7V>z@VB$Yx+V?3lT^&g$LS9NsNP7bd%FUm=7G_CeQ$# zJN*}@g&rh_skVYzm=5gVG{eBazyxX`&#_NrU{Kx*YF9Xb$4@_KFfc$;o)bIBkC2q- z%nnL=HwxTr_fLd1KD9tsBY|?Hz7I4t zUX2F_;B+-^3#$lF0{jXV09DiAvIw34LF=DDWuRGJril^Y1RBMl1&TOu zhhRM{!C!z{k(2-l`?K5@3QBs;3=CyZBS52|e2feX;P?P}7F6ObpU%%?p&STG$y#+V z$)(VK&n2i%jx5kno*#q$CPv6IrdMDIM9Bjh#{v5jRD*$%n#S~I9t(qd=wL4sM+(Sy z99tM54O37Efg7gM4Dz7pRt4QU&$t*IBcLqQ0?tAK$*_d57#!T^HDL*1DN;gM22Kbc zKoJX02+P50`Lq}q^hD}GDPaXT=0WF;=z&whN-*CWqySuItpZz{sRc_2tKkV@4`|ST z4K(JVrPf*~7n%^(fo+2)1Q-{R5CUYAF;fDpOlwM-uE=d+T@MPI9C7|fO4^{{s6Vkc|YF|e(Fz9nYv!6gR$d(vzc?mAnrg!jJ2!peu z7U;flaM~z^M!z*!aWoSw`n5ql6HvtiTEqygbRd(MI)2g&42=1Z(w~6=IydtL6oH_v zQH=S_DZ&g49a^vzH-+GO1KgPhDUyP;=MeKnptcn#89hvfq-9Tj3uW-i2dw}G28IyO zk|uf36sgh_Q1$~ISH!>os^%Hz>`7r@fRqq9;6}?zEd~a6(7C)IJ&!?B=NUjfuR8d7xZWw4tl^>FEKw~MO`0ASei{C<;6_kfIPL~p}P;vm}AqED+ zd7z2rZg3-R6}ZWelFGoKybdA?x_NDn7PbbnWGcj~69p`U>%l_{pcQJMKB8730|Nsn zX0<@;ZomtVrZF%u^qVj+=!2R98!{OfqEbQe3W;>kAlFaO&Rs+Bl^HsqNpl8}4#qi8 zK~Av-O$h6Nmud2AGcYJuft;oTZZz6zGcf22f~G}4t+=%iLm6!tzzc>zb;1FtkO_l6 z$We|jDj@(3_pTaYX*W{09hFrpT@wT0(L_Z#bSMJ@!wC=r)Qr6XYEm0k zfF>qEn^PD-{$XI8^CJzGG)j0oO&J*Cv|*zK>F{g{nPcZ=fGi*cCBZ9cka%$xvXH3< ztvGxKb_rzGhMDUQBZF2gsD%cy6TDc6BON;M!^0pCveM%u=%m~eObY4n`|RXh7#SEm z3_)kvo@BBBiGxZ#1_rRWCuoZSqm@TG1A{zhnVi>6&~CaMW=9={ddOa~QkV@~;6fBa zGBS9_g1YxXZE)YnN2W6{_-M;8Fn}#D z5av6|C?5j@ z2y^u@`qs-bFn}<3JF~BsJ_7>?bN4X&f@X?An7fzR7j$YG2y+{-_?YoAFn}KDd^wF77(ke70i*9JDFy}* z<~z*fb4G%J0fhM;_$mrBFn}=M4kq7KQVa|r%yod#cc&Hu0|;|vGWxpkGcbTK*AhnG z5+eo%5ayc6=&LEnzyQKrCm9(S1sPShmy25H%TNDPr^Y?~P?Mh6^nmUr?&*u?sf*Qv zSBNr%fGE(~dq##3NXmwgpd~_#451(jB+J6^nK5)eM2dj{G}#NvNsJ7^Fd zLkW28DJb7FF_hGUXwdRwMus2|1DA?h*% z0|RK$6e9!ZPD`-+K#LGSqi9SF2J=BQNF@_P6$6L{DQ9E|22mhgAYl;A3ToFd1Wy;d z93?Sb$;?8Gk!kuYPdC}^VP+O$0-T^Q0U6CX{jP__@9hQd7AcHqg6zk&7#NrsrcYP= znUTEx?HZeRjN1)-ECLxBXKruuwb;Ta*CWNq%*4se03wAL7&$?OJtG4vc=(I?-SiND ziyFq6+b{ZC+!WMh=j3EyWM%}bX5{2%U}R?IOqVha?%9*``mN>?S<@L6!x}bb%a;66@!ZjLa-x4={1EGB9$2mK4LC_gfO? zJ7$pYI6>VFxa6Ga`*SRm7*B0~lw%>w#`tPlv4tB`wd!$Q|``hnxjJk$LyS@29>BNxrXXgz)5{2=}5^W8;xrrS$8@=QN>&_ZJREaN~P zQ&4760@Y-otyG{pU>O(~Kxqh+C_vlvKx{3jIB32CB&IaoPgq}jx`K;4&-S=O7Qa*& zji(=cZXv;BVK`lpsZ5x~(7@bs`oY?2aaKbEGb3}5q!gTQU;^SxFq=XdOr{3Y747Xn zx=hUAER*SpEM>w>h6d9OqH9H23=NDera$~?BRsv~g$2v>Ln`_p^~OeEF;+tZV?&GS zn_pNwoqnE?QGR;fZ()P&&t6*0;ui!Za3O|s3{ODo>KPaqIJZyyX|a$w$*Zi~K zWi;O2_0J;8T@^IACIT99WncgoS|Vl)44@JUv}Fe-o;_XB%~CiNG^!060|E(y;u6H> zJ`0L%1_qEENGqsF^k86M0I2~rDnV>+(85;+h_Ns=pvBrCw$t>fZkF-&prQs;@`->t ziVO@4Eg&Q2GJwuEVE~m@FmccZ6c`({;sV45Ib|!lpyt>#19&+hp|C(Gaxo-c?f6?1IQfE?AV6sxgM6v zo*?BQX;46b28Cd3(3)rv8Hco zic5AO3C%}hubKX^+tOVUeCaUMQ~}V?9h5CQ-Lc0~S<)3rC<=+4KE1ZbQd|r z=}6K`rmyX>RIWdRB=iu8{T7M+6N$|VnmvX(KoE&7hr|XgIfGg0jwD`<#9j(vLn_`Y z5Dqw=z9O;ZL6;9hEz?F~ne1W2}y_@v;Z9HE)gWQ z5)#`SiS3NU_D5nzBeBzw*u_X}&|#*GRp72114B2G#B?O~VkGtkB=#O8_9G-VGiab5 z>H$q8wgVCyw5Jyq*AaZ6sR^itTqH$R(+^Itw3gh1ByM-5_4j4*#S<4G32jAUpGRWfMPh$KV*f{C3xhfWPm`kffQA z@-%Y(wnY;6nm%`$r8sXPl2G0BgVQXP>(?L&ffmTaEP9S4{uYV-8Ho+P0vPH@HVFm> zm|is`whkVMDSP=yYe8<_3raIN;|Zu{R*G_aL!PAhE9?u^%9@-ypGnAhB5_ zL94K#KG2Xv_`n2-?SRDgL1ITBu~U%P1xV}~Bz6Z9dkTyV^8W%D2eelkiM<1feFTYp z0f~JFiTwhJ%_@cPi~tf_8;R{F#lTPx3-%}^i8LfOXhAwm4d^g57`qEe%`_zT8YK2n zB=!v?_7emRpYay{sk=UL{?6BzvXId&twjc@3 zL}D+S{&%LOGUK`FinA=mc|Rb@{GIMP%hI~u9yB=)wc8ho9gV~W9e@H0m~tfXRwVXh zB=$li_If1tUL^Ku2pg0@7#MCsIN(h29EtrEiOmd}fQ33#5Q#01#0ISnhdI<5NjwLM zU4g`&BO8oJN1$UbVVbufDLR0}K7+)*fy91-#Qr$_;%v+P^*2EC&QSNhL1Kdzi^Hs8 z0c});su4h9%OJ5ekk}?jYzHK^4-z{9!iEHF3WNg=*a9SW4HCNpi9H304Z6$?=Fl}r z;yaMoN08VTk=Xa-r}xdZjH^!uO#neXScb%ILSpwLu@@n+*CDZYA+e7ku`eO9?<28a zLD-<Aedqt$AM}34NP>b%CX|qy=cD5Y!M~BzDwv&4rfPsuz%i z?jW&0A+i5Y-?`B8H?J&cLJMk=*7SpmEVHLuEVkq^+=V250*U<@iOm68bO_ZeIz4l- zrL}4}l29@dy8?;bI{oBg%i#KtNJ4C&MTAh3gpt_lNNfirHuzp&sCv--N3fg`grp_{ zi5-W;PJyr?Suz{K0mo1u5_>ihdnFQkI}-aS68ka|`ymqhJresb5}R8SsWBj_i75Bf zk=Uk4Y-c2PAQC$siJgnYu0~>aBC)5#*dYIJhH)4e7!D$_L8}K~L3$TS9DJcLG}wP4 ziL-;2$3ewKk=V*eY(pfry%thq0DM6(RC6?vBG4)Wm?O%O#9NWrlabiq%YUKftVa^x zi^M*SVAnI;L~t0MBeB0Cv6(@0vQR?>k=XJ`Y+WR_H4@tsi4DH{7ivx_SR54o3=9m# zU=BF_F@TTjfhy`p5}%92UX8?d0>0=stC1wOA+f=C>Ow6z zgCu?(iTxOf{SJxE30iOo)hhsEgN`i$jTP!LFbK0UFo4cAVvq+(Kox=Zg))K`_c1Uq zfX)+v#l0Pp8cz@#Iv@_39TaAt?zh5HydJ786C@2at^~veZ(L+xr~ugsWjBMwp=$a- zY^dJJAU0Hd9*7MUUyH=v1Y$$YIf%rrzlg+nh{OhOZG~!J1f7NeWpg31Wk77uurO$$ zDH2-`iR}ntLmlS>VuMDv85kG>^cWa~d7uM5;PY^xiqb%epgt%Ev7zEkAU0II9mIx; zPXe)_;?qHFsQ4lf8!EmW#DK*x-d1 z3=C=d3=G0hb|FX{s-_0ShI*h8#D?MI8gU`fY^c{=P)q%7&0&jL)qaV zaj2Rk5F6^JQV<&|-T-1l#alsas5t1}XPCd|fyAL|7K7NZ(bml%4%D*CNbE02YhQ_@P65AAsZ3kjQ%?UCFH7KA4m4hUp>;@$EBoG^F z=xikR5+wFo5F2XfNe~i}Xy3}tW!u|em0FfcH9n=mkd#_B++A`B!BRg(>7=YWJ67>Ym~ z(B>Kj28J?_1}M7`Bo5Uu0f{{u#0JeoGB7aA2dRg$mx08g>NkSepuI;73=CUAY9yzh zTaT!AFMy<>O79@CpMlu<5NEvxv7u^yf!I*vm`xcN7@=%Q5E~jnN=R&NB(@2N4K=gg z3dDhGc1B|RAhAP{*qKP|A|&=w5F6^a4InmXGc5xH!xmEp2GAuLATR6&i9^*K1F>Zo zz}x*8PJtB3On+kn_mz4fk0oCqX#HWIr9i9H>Oy&j3Z1BrbK#D+TJG7|d^68j~H4J!gafH}ix>j~Lk@@yHK-Jc-3?+xeK`e*Jr{|+48(?-vl+yOnsXn- z2H6EF0-u36ppD|7RZt*TL)l+J;vhw!XtqF#dk`BcE{w!hL}G(Zwu03>)*x}HnJ!4| zC<{;#2=zfSNCL{vL1Gty*ig;YNbKn#Hq;UGKy1*NS_}*fi!2xzgrV%UAaSUg9UwL| z*!P0i5OFnz(+Cd3O(gbnB=*T_GiMb4Ic zwlcIG{>74kL0B0S%?u3xK@w0!TviAV^Mlw>aVZcR>S1{h8!E1g#I^vjp=xYFY^WM< zBzB|~Qu@z8k|;r9*MrzlgIYjrs6qW8HdK5Hhz%8=2V!SKJhK?YhI(ub68jK{4GJw# z`acchfNDx4_FWJgYS3d48*0!SB({Pz0|O&e+yaRmfW(eOVrPTcAd49o7)q>>(tjY>YI%qHfUEOs3NmwU=W6~4}ip>YEFaL(2%$QVnfC6f!I*>KR|4#II|4{10!gE zA873~yA1<_FoeS(1d@O%k_EA$hAM&BP;mng8>-$5#D=ckV zR82mJ4K=d_#I6E`KLZ0pJ%|I9XaTXInx}%;P|XWKY|v67&~7@A1yJ^SkT_J$E)W}P z&VCRZDt;D;{RG5@s(A^v7^>(ClEhCC8!FCXi^v6>AU4!uAtbg6hz*TbT_m;{65AQX zhMMUIVuKd@g3@V_Edzrv=(t`628LLW1XNKvhz;7f4ypw}Y^a)2Bz8N94Yhaz5_={R zdl85YHD?`&4K;tKEoiG0XqPqv1H)dBBcSXPNQy3j*q{||3=9m{L2Rg+2T1HsAU4zy zzmeE1c8F#qFNh5_M-#*bJ3@qk!34wst(gXOgY6g?gmtIy+lgqI1cRi(Y8e<3k=QvP zHZ&RwL2Rg+4iFnE-V0(w#b*)M7!v0+hz(VA4a9~jx(#AO z-F_eJb_VbY;m;s(sG6T3HdM`DsG8>t3=D$yh-4)WVnfwP+k?V@p`O8xk%2)MBmp(Z z7{rDuGKVN)03Ax=4HAc{2?VjBYC@rEKu7asg2bU}@&B{n@o#~D~!Q%DaAR&+$pxs1B>{ujrGKdW|A_s|G z2Vz6@wj;48AhB11*wECl1;hp&@5aEuu)~3YL0Au3ryd4LKoy+>v7sKn3}QpY?}6A* z@y8%GRQw%?4Hf?kVnf9R92pougL0r~kwjwagV<0 zn?P)+WxXIa=m;hT28M}_pyS*@)-o{60f|G^EC;cn4qXFcgTz5)`gRZpDzOK|21zh5 zFdPT5q2f0|Y^eAP5F2XQMixog@s6qN5HdKunh;0n=F9U;>GXsM#l3sxYpHzKi*gV@k$x`4#KiNt;eVnfaO0Ag2x+B6Id48K7fP#MC& z!0;dB8z`I01rc1LAU4!-QXn?eajGCTR9p+hhKiel*idmR5F0A)24X|a_jdu+sZdS? zl0+Ve4fRbq61xG3-3DSq_09#cK}QKOFfc3zv7zF7kl1%YY^Wn%fY_k(5wwr$aVrQL zlK<>M9H=5M5F4t~e#9jwtgB39_90IYSYR-b#Q1MG3HdOo} zhz)hne;>Y68k0+yZ#l312yO?hz&Yml7WHYC&)4=o5csw4&Vo|p%#dM z*igMnNNimY8>+?##D=P|Lt=YD*pU1e0^&dxkTFDp*ieg;kk}O^&ehRPRwF_BkI=`45%20+N7g{)NQm^<`jSgo=wHvE`B2rXV)d96KboI}$qp z#D;n@48#VR3G#m)i~}l&kl1UG*jtg@6TRL=nSYB=&I-8>;>ihz&Y2k%58X8pu#6`yogis^$%d z4NZ(6L2Rh_e=r*q{-D!B{Sh@4KZp%gBn4taHOqt8P;qS}wi$>GRbvfeL)Ex}*idnA z5F08UiNsE>2XR2>buch6WPsRE9~2_7+d*t-6ih&3&qQJ`0y&ohFRdX7NeI1GY5X4Ra>8)pA zcn0D?HNQt<|3G3h27<2S0%>4i5C^fL4pl&6Ya+3YKy0uD3=9?^Hq?AaB(@ib4eI}a zj12~Hpo%g;RdmxY6L)Rs2XVy8!D~* zoezmE4q`(c0baunb%Yv79Llx<|zesy-IR29-Z)Fb)F)LnRV>J`#Hc z5_=zr4Ylkz68i!Y`x=N1wd^Gln=b?rm7*b__CIJBHRx=l5C#TeC|dj)5SsoI*62yk8uLH56YC1t|hIUC+P}3F1ICXMxy9A&w{jv7zG4NbDXY_IxDv1`r!` z4HW|e!!{5bs&_vU`yz-9bck)ZM)%J~P9fW{wt6r^wf1)cyBTMWd8 zs+UJ%Yap?mkk~0m>^u+~>d;CM8*~T=X#Alzih)5G!eQtDNkA1%2C<>8o&jP*#TSFv zQ1KNYHdK5I68iuW`!t9RReu4*hT3%#%m#%&Xdx4r1M)8e!(SveTQma$BUFPN5?dXK zZ3$vSL(U0_?Ty5a2eF|J%>uEZ2Rr4}M>8-8LphZo38viq8bG zq2kMt*jtg<2a(ukKy0Yqiy$^^{Qn-51M>e{B=#R9Hg^mn+lYbKP=lmFY^VoRkl0or zHZ)Y6k=Q;+?4TG>`480`4U&MeOOV*LNbJcVHq_8LNbIFZ?A0JP)SN9y>?=s@Z*Vp! z{$mk7;|8%oXAgn8&9Mv&!cevpNE{l}svtJh_gWw}RNMlI?S{k-L1HH%vFkzXdZ^}Z z5C_Vh4q`(sUVy~j24X{fzaNQx0*QSN#D?mLYA#QulGt`~}9U|@u5&_-gLAhEqb zY^cS-NbDFSb`ppUH76U1Jr9Y!0>p-Tax;h>3YvdmU|`rD$G{*AI=GO5f#DEH0;=dN zhz$+uOCUB>{2mhfC5R1G^A5y@s`&|GL&g7r*idoKc%+&$9#sBAB_xp~y$3SeT z_-POuDt--YF;wC`>M-rm25=UaIA+ZfWY|v?d3=9mWAU4$Zc1Y|H5F0lB z6AR^l0xS)QoeyF|4Qd9lp$08RVjo6gpFv_jKw`f{VhbiSFfc;RkxB-Y|4@!Hl7tNs zI}F5z23I189SL$K14C*u1A{P>T>uh?s;LICp&{A;VnfAykl52e>|BsJ^$ZNNK^&+- zOOV*RKx}A^IE=(TgT%fHVuKB0V0Z*#L(O@O#Qp_hLmk1G!oa{74YHVlfi(p*{|n^^ zfFz)bq(N+`4-`Obs2UZJhG+%`(2f{QkT_JmDH7WSi5-l@P6Dx^=42zW>${OSn~>Oh zL2Rf6M?h@Qak8KT`9O|S0;;GD#D@B& z8^nf+PXn=`;Q24 zX^6Zofy7n=v7zd%k=QOsY+odH7!o@H#D2*=0zI8bNHR zkJ~_OsOAYEHt1+&P^SgNhU%S%#NGm8LvzqxB=#``yPn}Zhyyj~Du@j==sgmfFC7sQ zYDjE5B(@(Cy9|ll1Y(0ONdR4`3u41O0A@qC!%PQrAcMn7{*~> zU?@jogN}=b?V4yt67NQ0_am{VBe7>Au@@n+mm#s&WiT*g!YtT?B(V#Ly$^|f6p4Kj ziG2}?eHDp)2Z{Y)dhAn6<@(P^Lf?_t|B=|tnMg5>#O6n0izBh6k=V*eY;`2IK7~NgOUfWEuR>yjPRNHT)j$$AKw_I9u|c=^!qmGXiTfk5 zgOS)#5H=`XFfhbHIG~7PNJV0UPi%sEA9STIBXq?~4M+`?-HgO;M`BMvVoyP0&qHD_ zk^$uls6i`{B-SFawxDs81)zaB|?GZK3@5*vKsHq_{2NaClE*q4yl*O1ttyN_X3zC;rL z0AWMY&ld;>oPI#}k-;>ufDWvJTFi~a=0{>nAhBhT*cwP|9VE6X65CP^bd&(p0#_sn zPb78_5<6@fB zEtI_wiMYNtW!q3h8uA+fI^u|XF>Gg>i#PXA|Mcr$&W zyp?$UcO-exP0%p&xIpKELCq6FVv8ZM<&fA)NNmuR(J*sNk;H9~*bWdjWY4xcm@|Fe zvS{&o==!%fkPwuehQ!W7VuNmLhAs4}1&Kq~PqiSiJCNAm!_=T^CL@W1?sbNlQ@;{P zVj~iJD-wGT68iuW`vemE3=;b?68kz58+83JY+cT4khmjseDxEA1I{wvkl3IbiD4Re zK&Pxh7xjQP1;fO}k;D~{*eXbD@F{Lky+%mlmWrS(1C_8vl5j_2dn2*IN4-JShariB zu1bbECQku#BPAGK}ALjjKjdd(1*mHgv6eS#GZ@9UXH|Gjl|xB#NLL)2Ho2X zbLbgG28QWxl&m;xuOO+ofy91*#D0RrevQO_KV4PXO1Yj1bl4m;WZ00{d`N5|B(@Y1 zTMmg0x=0%4KqDk^OC&bAY%I*7XOFq>mu6LH8TOlwL;?zmLRzjKqG0#D0gw{))u@iNxjroona;O@cfS4k$nv zM3C4LNNmuB$}k7%B8h`n=4{Q-&n1&RF!!Uh$ppySLCi>dfk5p2+|d)Oi?86kk~0m>>MO^0TLT@H#N+hW+d@$Bz8ZH4e~$e@@kld zMKB2l28Pv0?Da_OZAk20NbJK%?Bhsm&|T7u&=o|tK;lsLBUR9#EtK;NN#Y$6`x6rT z7ZUp)5*u{!Gb3~{ju7bBPbgawi48tJ6e_NU5NBf0njWZSC7x)C5M!`IVml$RK^IEH z>BcGf3NHCfF$mY#P&vFgKn5+3}%@AT-QplJ{2SZU89nT#0FhE%?K5*M-p#CVs|02 zLDx;g)Gt61UysDzjKtmpVS~yq28II=4mdtQcQV6Pfq)OYg|6hd1yTcL-$P=9ZX$*) zDfj{shfc!(Mq>X*VuNlchN%|?AC3#vAft&`o1lQi23=na(_oAwZiU3QLt=X%v3-!( zplgp|=70~=1=$PgN2enx%AP(^-%7l`3`wXKiQS0A23?yBGjA%AIOz6dnD`1L@eN4q zElBL$NbLO(HY8TShx0n?0ZOT&~?AC`SdSH;=hsD|B=|B>wsbEg+NE) zLd}=d0@bQejx3S{=(=E-1_LB<3naD;5*u`#FigEal6V*rI|_*nJ_s0OFUbG7ND`$; z>`Ejy=b50J#4AhF*eu|FZPed{iLH&q2Hjl?Gsh80+yja2gTw}1|H_yMJ$N^1yRDJcbG~|G(B&4;VQn_hbr8_e zuBB2846xB7F3_+&bW|r3#DN_jhnIrb(1pQ=Kx}Ab_!Pv3 zR)9vJZU(eM19x4ZHNz>DYz78c$+{BMYJwJmO`sYZRE97xFzg1^E})bPTD1l$?4XH{ z8I;|iiOdVchNctn8Qjn)RRG01bPm69d#{t#X$A0B(0}3#3_@lM;Op{OBp__i9iLoK zHpo8$P&UY|Vo-Jx0|SE$lnvTx%612Ba)h$O z7#J94LD?msX4V2Ir-6ZiVHuP?fq{WxBa{ugu5SmF4Z553Fq93ty6+T}y@7#&;R2Km zx)AR+lnuHC?-7&@x&`kolnuJZ?+b`sZ_dB~y87-Hh-1#c0J;|MACwKcI!{oNfk6nG z3B;jn(1FjgP&R1nQ5nhx9sjBaWrI%Ww1l!jXMx#6*$xa046aZ%=(y~9Zzu;8uYpiD zDA|QW*`TBr3uVVJFfb%T*`Oqq3uS}SK{=G2$H2f)3uQMlFff2_jRAR}8MFlxD&7xT zz5!v^Gk}6_HiQE{nQ0-Ey^Dc?VL6n&pMim4EtCz~?64WiJ`Y;D4`ttAU|;}UxDB%G zF#`j`QK~nJ_Xia6{QXj0_B7P<9+61A{D-ox#Y!paEqU)H5P669dCcD4TY*1)5)I&L-JDJ;{Y*6Xe17(AbgPH_ogF<@-lnpAL=Rw(^e7pq8231unplnd} zv>U{RR*Il`aL@sQpz;GW4-R72gNokEP(>hh_n>T0J@*pI29*Ktp={8m*soAF=z`PV zPlqk8Q|TZ>tr!^?N}v*Mj0_CbP_{oK14AQ}UBJk|0Gdh%sV`z=VCaR4H!(6W zOoXyq7#SFrfY{LX2k3$%Av*@p<=70{pyHs_lzTwzdOJv>15KHO6oF1kIsuZfV_*QK zmvc}yD4|_~vO!Iaryw@8Q3JZ4T*w|`!AGb#=s5fDP&O!v|3cZI!%IOIErHa7>VqhbfQo;=ujg`C>xXubUkJ@BLl-9C|jM8 zfq_X5Vy^|LZ0CS-+!+}d_@HcGMg|5+C_9jmfk6ezj$veA(1Nln7#SE0pzIn(1_m=I zyMd8`!4}E}B}PXmyN!{7Aq2#RHhQDv7#Qk>oFNG(0V)AXIB8HeD6!-~*`UNy24#cx zhc-ajpfuP9WrNzx6QOKSn-Mf~4>BKgb?iK-cq!;`P$;_^RQ|7razKrRZBRDo=J#Dt z_7(;PhO;0xC<}ltykm_a~GMsxSV7+4T$z zAm6acGcX9bGBAL$A2*Z@O6`JBHmJ-Ohq6KCyeyOr@})AA4Qil+rtU%JfEwBQP;pS} z$P~&3oic6>Wj8S}FgVsjIiLn7Xc`}+c^(4;Lm*Tf)H;fWvO%dg5y}Q7*mNlS0Rsa= zE|mQQlxv{uHw+96jZpRv1_p+9D4P*fSV7tKEQ|~cv!NU|Mg|7ZoIS`9oQw<%>!IR2 zj0_B0p=?kJKLBNeQaEV-9;6;r#DeDRL2OIVMb%I>phSHi%JyPpV0a2;2QV@)yp{)* z|E>%SVT=q6AE6SUrV?mEA7oG#BLl-dWMEK) zvez*(FsMV>8yOiGjG*kDj0_BxQ1)I>`ELv59A{);2mrA`$(VtGAq>g}CA1hQ8?>%C z3Cac~vfbLfVu|YXP5GoFGG-$>i zBo4|Qpu5&UY><7LP&J@#mp+sY>LZv!*!2v>3=9m`5Do)4OF-G6P6BAg9%Rr$&`kwU zaZrwk1F=CZ6woE?P&O!<3ZQI|XUd>#kY{S3Y)~Jx3Caewjyga~1%$jA7(nNHgJ$VL zY)~aM1*!f%w=ys=EP%47f%=M2_5#qgmr(W^(7rM#dk3h84rPNnEudL?kolm# z-#MuGU62K!iF%L(sIs{QmH5WMzyO-42Z{e;U|@I#75~S;!0-mj230~Iplnb!W>#Wg z5CVCNfq?-uLl0tuLPZoR4hj`%C>sWYH)(4 z>p_NsN@5qNI4HCDL)oD5jVLG^G%S$_WrNy`po{T9dO^`$2o~m|-TA4f4%gC>xX&H-OlnG8nY`9m)o&*#%{T>V>l)Hgpu`GL#Kca}&(2 zX8RvO#`RtA}zx!KDRdgGO;|L2OU~z`(%Z3}u6QGoDa3sNe4o zWrKQ1pb2`RKn4a-HJu0*2OYAS4rP0S>If)10(3_hlwA)Rx2c43KqpXx9TdpG0E)9# zs5odRMn9AdYR}JvvOy_-0hGNG)Ln;Y=Y*2K7=Iue^prb$;zv~cn)QQg8D6#t-`>-@B_*Q1@(U@8ssvzONhmvxfq~(C zJ(N=f%6?EbXs_69C>vC0fF}Dv7J%Ax&!OT|7#J8nLD`^O^ApMj6~mwjevo=l%4bz) zU;wc}1JMFdHmD2`hqCM6GB7ZJCip>$K*J}>Pzer31_n(i8A&|1mN!Y=*KyBcjJZY|txYMK0w)^^zjYEt`CP4jekI#a0UiYGnrk3fdOOzs5<6@vOx`0(8>Xj zIA~-<3MvjtAE1>3AaPLoP=ktt(g$ee07x8^K8&E^peoxI$_8ccdKV}MR3Cdm*`UfJ z0LlgptA|0^_dqA0LfN1T5|W^7P#VgBvbh);81kTOVbF*glr0I$a!|G=sKkV@>lw5` zgU=8S1E?sS1Z9Idku#ud8%73(c~CYeyDovUL7m7|P&Q~}WCN6)&d9*94ax?kn_W;g zXqfIShz)9PfrfT8K;u7=khr`Ll>m)UKZUYEt>M>DHfT8SBa{v5<$Q;-L8Ucl34%~0 zB>MO?85o2>4Fv`U1`#M5)P9tLvO(=f(5eHF8gWqjUkxe&YJBQI*`Riu5tOY1x_1N0 z1~ni-OAtVsLES4Ss5s~}hENb2I_;MLWrHjRtvV2jg>2yl-RBEpgBq*FpzBRQ9ME`B zB~$~bp;!-PgL+u4P&TM7+6`rcnh2mZ2_U^7i$NCvgV>v{nJ62IR4CP;pR{{Qm%>B$@_4k{aLp=?mA$r;K9jTv~>Lph)(6lmcB zNHZwWffg%(*r0A#DpU<9zVo4MPy-dTRsp02RH=a0DuCFaG77XlK?u}3Wnf?ctw{i} zLFr%~NN*w}9V~&e9YKj}6_f*-J=p+dgACdRWrIerKnoW@27wBtLr`&0rFCrk%tk8( zDPB-egYGmC2W^_0er&c?KQCyA0Ms`I30Z7Unq%e9$P1doU|?Y20L|@NPTx1z%9 zBxE zRMHinw$RFv7u352Sq_qQ-R`&0N}G`v)XN1;@yaqVFnUaHTV$2Z3yKW}1_lq%$^ozG z|3E^Z{KCM%Z~!FaJ-uwP)ofl+9f{YDc3{y?t`jC(D4?a00mWpjG);BP}G7}Mt~;XK;8whL7g%N1_n@V z#|X;gpacgJ2Q5{A)@qEPqz#HIkT_`B0_X-X5F1qYf(9o*Z0NBYW<4MdXdDZaQb24_ zqZ>4|4Pt}(&I}9;pxTHLREmJ6MM2_4lQ&-0n;wuQE;9YhS}PyM3DYIlS@|>0nVz}M z%Ae`U>gl`IS@|)>Oy^v0<lSU>&L zCM!S2i0P7>t^AoTY?z+4*~*VGWctp{R{o3$(>b?T`7`EBj|5Q_(^qb>@@Lwzar&<< zR(?!>Hct22YURi1GJWP&D}Sa3o2I`4aUG^xZnN@dy0dwD*ETCZrWc#1-vZHJHc!{u zZso`5F}-rTl|R#sEz?hdxFXXfcUbu|x=hd90dmdO>AQAV`7!cL=iF)K&nPiH5=13T zUkRcnO#ca@mQ45D1yZ_W`m9}6evBs5U+w}cwcHKz?5^ouyRH0~uI!$EYqymjqrh~{ zJy!mVYo=F%sD$Y!_kcXGce>PGD?g?Kd#7iC=ren#?*h>`_D<*82lCk7=~4Tv{1|(t zuiR(l&*(7yCx~L0?ztai!-46u_FMTevP^#o;@&wl-RgjqAEV9m&I4Bdj4jh|f+(Ho zng^}?88fC=9t1_&k?E%nS{-B5m_G54l|Q4*^oNJ6${97LM;^BFXIwCS@OxHYS<V%aa9bCP0`2DXS0MVw&FNOBto#@|rgxsQ@@Hh2eiKAhOxHYZ<ah?Sy&qxq8XZp&sR@#j9(*-RV zg{RBB;}>B4@SKrh#q_^tt&~~6XfrTyPItV=FFbuuaJ&H1j2F|r&RMB3GE6T#XQj^c zb#X2DmTmp;=(l;f3hWpbC&+v;(*SuoI&)72E@`{x@ zWm@NBS93$^hOYsF?}V3x(K2irvJPSiV7D72Hxp~CUPRv zEpJ%yv;J^lU=W2^o^ZoTfKgz2;SDQwRs&ZC1~G{629U7F^n)Pb6jufY8L;rQn^pph z4bug0TB$S60ZEEa4*&`6n4WmkN}ctJE8N%xAmKM4mEzM++_Vy4<#1zQ5C2HwFfNh_J&gD*;B2>46~O95)7rPY~e=AmN1R3vYqr>Etadb+#S83=D5G zr+>R;rNneVZMxKLD>cTY(;aVHsk1uoVPGhno_pI$nQcWU69a?y^l7)PyckzZe|X!< zpXtx7=|*>~v=~oMkG*51%y#7=6T=tB>1}tclvu^Z85xYHuf1cX%;+`!;vFk>)>bb@ z28-zjEf|HT3*5C5VB9-h@vfCR(+TD2UU#k3SdaQJGMtzmSm-Z2z2mNx0P7VsW`+~f z=iaqaX6&7Q@UE3Qy|o|(tUaAdk;ytwdmjeAzYY=%arW|juiKgvjovsxOO zT9`~OysXZ&BV>EqJu5Xyab9Nz2GG7A1_l;J&~_D`$GQv*(yG(XTlh-UuhV5^ zmSA9D$Odl(&NvgO&&j~d$RWfHQp&ngkAZ>Z1SbOnlbA861-C<(1XBB$kAZmsdcTB`6l3`GzPHBGQa*|d3@lEJ9Ux8S;tUKdt`PQ1 zzUlElt)v(;rr&#OtZt<$z`(!~3O0vrE)N3(O9UfmfP+hbWhJ8(69WVHBM}A$mQ{?P z5ijnSq6`cys~P_@FfeedPrv=sO5by_JOcyEdazP9eQpK@mM@H8*MKG=S$=`pJnSt0 z7?(0JFz{t?GBB|GXUt>*t-nc1Nn~JQU@`)&RAXREn;!hjO0T{H6z)O|poWRiZ#@PE zCZT9P1_ov!&|n*j5NMGgD+3FQ6axdR+6g8G29^XR1_n0uy-W-Y!ptlT3<_+z9n1_2 zA`K!83~YKJCWFXn0R{#(eGr>PBmxu~27Sy73>+e$#XxL^piw#=k)@Ih3~WZCjDidd z0wTAWw>js7)9AZ6#h0S_8&r2J)C311AeVGbqqmm>C#Yiscv>*vvr!qC9Li zXFzrb=rJ&`*@AkD3?jc27#P^>Kx`I~PtptwZ1$jVo^e7ceh4D5p7&|~211#N<17XtGb`R1`QFt7`Q_VVreH=m$ zH5eE;h1_Hq7`TK=nHd51cWweGcX7W zftQF1y#|H9&?OEA1`!4p9(EoE1`bbfTKAY<@W)Cou~&$Jfg>N}btaK(A`A>11)y}x z!obp}!N9;#c$Wo~ZX_8PIGRAgz#_)az`)U}&C0;QZ^p{NARx*L$`*1UwLOj?(Lj(W zNT~qG90nHE>Hq&&$<}9prq+bA1VA2_5dwL9IX}qbpu&Jf2s8u5D&(Wiz`!Q7SO(;A z2_^;x4j~&*13(D0Q;JInw2g#Y2(-< zgS5~CB?bl=p*}VS23aA{VtqLw4G9JYc_DXD5*G3lXJAkiiqvCZP!hT&!N8y_^h||; zK}G1MA_Ie}P&E$&gPM@G6a$00kUSp)gND#mO$G){AxBYl1_mvm3pxx8+CrbT85neg zPAV`k=n8?B59=}TuyN=!tz%7cJ-aXi1BVe)7aIcu7aNBu(;YSj25u`^ z1_ll@aGvB|!ok46VGh>Az@`g|QwyeDYzz!M+#J?S4(tpJd}Uk=3>-F0pon1LbLL}U z;IIXA82M&MF)(o0fjLZkdleZNIP94e7#SFt`8t&u7&si5UV?^SSoqF^OmGC-&C0+Q z#LK|I;mY)aje&tJSA~IrBLHjyj{-*+lLQ9?1K(yn1_q9BCQw3R;9IK6z`zj!b}JL# z9T^4&j!32rp!FDhI|LXQIHJIMx%rGhnLQfJ;o<91VqoBi0deXXc=_hZGca((GJ!@1 z`S@1LF)(n%f$b6Cb5LVo;D`r1S%PmP$o+{-8<`jwB>8SjGca%@flOeK;(G-Om1HnS znvav6fq^51$%mbRL57b_oPmKO6)Ypmzz!-)G(f>Q8?+#if$b?5Lp=jWI#UEY0|QS6 zM=nzj$akQvK^%EZAcYKkzc@kJ1ndF@zB8b_Q3Ce25+7&@FGnfUAr=M(6+SDF7s|l) zr1C{_Gca(JgE?soY@oppjw&V-4h9AuCXPC$Js>+k1q(+#({>h6`19QX`MCkCfsui& z8I&CwnPzY>FtF8YGca&0WV*t^z`*~6gMmQ+On`G6Ckx1hJRBUSn4~!w82FSx8TvHX z5C*<#kh9N#IgF4PItz&*2DWD)*PUZ}1u{NOyPko8gM%5Abl5Tl85lS?nL)A2Bf%lc zyaZ$_XgMB-7_&NPbd9f3i-CbdoY{|&fq{i@2P*>uhXnH(a8#cF$w)GPVPs(7;o|{0 zT8bIuN&!9rkh~1oR1rSV3Ih&V=29jG1~CS54Kia9A>f;+ltt!-lyOuG8|-sCs5?NL`#9`Dx*0ei!R`R&a5At> z2IUM#W^*nE1}+H>XXfKv3=G_0cesE};ywsULayMjVF1MCb2wn$KN@MLb}Vqjo91ah|@^L;J`2L4xE3=9Gwf`O9-WDVOLkkNvyf4CSJ z#6c0NGM!J!NLeru6g1MT2Ha3#zv+LNtR)4{fMQ#jH3}wN3sNn^&%pK*Gz6!^+R4qp zz&~$#AhWfI;51MnV8*%%ruM}2JxWHB)BBmNS?gU{L3Xj}gQ7VI!p;G?I0wS60a;TD zX7g}yRIobpFfj1#mSAAusAL5-IT-k2LFGpk>lJPW1~$GmpnO!#`i7f?ZeE&fizLphKdT}zaEdg0k$NGc2o`HdflcSNf7jAA7vboL3=C&Z4+X^w4fh`{t z@NKOAJPZsx5geVY61*@Mc0o-77i!(CphAs}4|K{BM-M9~+jH_2g64=gdRajQiw~a( zs3`9PJ28Oo4k)Vn!IlK_?FNO;1TZIvPY_fBO$0kEm~RRwd?tZ8Aq;G%KsjeJ>r9Ya zyf~(@hQi%49oa225N@ew;Ft+<3uQj4 z1~v{B1_q8ztlL4(P~_OkD#8bCNpWmr-45zI@Fp{GY-gPTYH;!vF>vevGX)vg96`0h zPS)ojjb0pkSOY;C!D(eLvitWTyT5)v!~+a$9w6TzU{&B_VBqoQIKny`uKOsm?qkTh zk3%$r+j$%(z^?ORV7m$`Do(P-f=puPIKz4xZqiw(NgqLZlxS>*vdgU?>y^r zJ_ZJ^2#$-ak^Bq{+@K~1$0cxr=Y9=JyqCd=lzWmc0|Unua5Cd&2c`Y1;E3XW3Q9fK zz){Yf2de+CgM*qo5)`;Mz@f;U0#b7m95CE3GOm$Pdl^t^5oO0w=f`7z98p22K``TiK*Q73dSz>HG`~{A)lez-2cmV+()? z1~$-qC&wGs9Uujl;0j8a7^e5ITl3cc2NhVKS?__QUxK8;@yzx?m4ShSjSXZ3+g?z0 zAqZiER=aVCf!RE49O`VT0u0b{K!Xib4lqE<0Zp(9Mo2lJ#l|SWz`(>e9h7^t!7|Kz zFG1}a9k%+f{Gb|Xn*sv^hb|k4!^*&>2Fgo%Y`g*t3_L6xMr`Xrmau?oT4S(o2EKL? z1_lljFo%)vJ*ea{WdoHjOne;rpvnTwVP;@+1QmbgY=t0`WH_wZ*aR6Ecymg!88~d% zK&hCap3fc>Nw#dDhP(jZaZsMNV*^#B5)e!5!Intz{RPFh1DGStz%~igx^ZON4Ki1P z!-dURkb!|O7nJo}*+3-<10QHYox=@m2@Av|cd%v=1~zd}jqAZCB*?(PQ!m2d&DINd zl@C}018+)Z83Tte*c}28tNp;bg&;=xgE_(sY{DRS1hDyojFR98X1fk|M+n3n5R*c| zCPCd12G-05abbNp*hY2+HUm)XM6k^S870mU#U>)ez`&bXl+C~q4OYUy=g9_Y`murf zo&tPcI-r&x8>k`>WMC@*l{9f|j|CYRxMVmI*wTa;7`VH^tv+y=a~}Z(UlKT+xF3UR zfMl=*-1YvT_G=0_2)HFdic-OzU|?$kl|^Z63PKDFJRBSuY}155-3Ui3DAVCNT&sH!;fHx&0o1vbg4a`$uU^@Y-X*$?cg&7#Q z3^=;jnuHk`xIv49Il93HNu(AraP)vxGq8bn*mCr;B?^NkB|#OyB(_bZ zfs^F}7pRM`!VMz*z~nqI2`Ym)SyK5y;=hFIK~x{e7qdY5a2eYMVFm^<7SI?5#}>9} zA`A>d=Rg&YkSQ;yPii6w>XU*tzcUN10kvg?c=#9?ScN)RLE*rr4JrxtLelp_P{Dm1 z%;w?ZxXkubgn@xKH?e|&;|e%8F!1JP<}uWBTm|!(_!2;!<7;3J3*Qe=oL>iX*dU#> z8*Ga}A;Z9C04gGGvaJJk|M!DhpZC}VMHv|QwM7{iz@2FUkgEkiMF^w>W~mluVBj6fq}CY%wgrb4&u~- zIc$70L0+i`bJ+Pn+gv#t7(pd72cIBFStHmqF1~M|)X~KF1=PUi;R9`F<7@_N;^PA? zIpJ&pbNCt9#FQBrI9nM(Ane85lSxfmMNu3Q***eUW2e;GE330Aj>6MiJ0B1=xt` z$VSXSHex1N6$?W>Ckv>UXFCWoV;19MkQsuUa~ZurW`J#;2iC^Grw;Pyd~p0QGO(=x zh0X#-HF2=B7co|egX*KyJO<9iP&+|Kf^jYZk0!D(u-)clVBlQJ7zR==!?}WSJIMS@ z7KVBT&XtU@;6cC~knUAr-6DKo-K)X6B^cOVf)d^u#x{^{4$gIqUqHHpLD8@tte$}v zta$^N!wAv55v-Yofh|;lfq`=q<6(&AEsQD>3=DjU0t^hCTN%M)4-9-WK*?+ySOy%b z;tULIpZORVIJYx0NH8$)=y2|2dD9ON}z!xgXz`%K!kzEqh&3BV!VBkCgPJJ5Su?5bfU~g;jf%aB#9s_f< z88}%$QNqb`9hCH0K+(y`A_WRY7A*+|22K`G1h5H+fQqf-jAjxH3~XUK3=EuCz}k5@ zIBzh5c1iQCQDR`=ya~3Afe*Cjj`J3n!^8&;{@Y;XEPPF%#BqnwOq79vmCqfNmhLh- zih_DmU`O3!+$_q#z|O!nACz(LGpb60dfS{28IOauar2ddg6k1Dz8LtrK*{|vn8U&s z4GQlkU`sgo4(Ks3a6ScdI2qXLK_U5!u@f|0dkZvf_k!`hBm)EgPe}#_0m#-ounZG#Q9&XD=X*v_JAj$*8K|)Nz&M2& zRBeDpia9?rf(+B)D+NW&Cq~dXt^uDeC>MMN8(_k~$#NOw7SPrV&M%B0XGri!aDHQ4 z2XcfL$Rppuxrc#o)AVQ|YpME0QVa~7zZh$!7#Mg2IR7x-11a1FiiN*mHUnQ9DA)XB zJT3{E@Ze-Alwx3DYvpBN;QY_HONxPk9aPXVfT{=RV3H~*7`Spl=8N9osy{2kz#tL^Qr`eE^OgVu16L!6%_Oo& zmw|z+2~^^+i132Cc3jOM4u?q0^af#T<$5+P1_rKnkXixB#Iynit`1Nt5|S(iu{(W4 z85o2`L_zI}ZcyV*L?lF$fq|lzPSpaGXP6ruUFCwnZ zz`!*F#BLCA5NBZEnh6Sp77=d|1_rKKptQe1Bv+b&fol%P&@Cc?pm3QBvh0e;F-Zmn zu6ZE6S4BWsf@?l#sPP&kFz&>*~=ECYi8XgmxeC2GU9a-u8)gGeqY4pxD}i9rN(&M?<%P}*h` zISq>AH6S*-$Qn=_uLU`gS45Ycp`L+j9VqbmL?S?=N9#f62#8Du`FjKC1Zfe;0tT*) zAZJL3fU*eJCXi1-jieW#48sC)CCgh-{A>ofN|b|Z`$LdZwu3@w2gqawk>w!&?F6xz zMA&5+7`S$U*eoJFnhXr}T)ROWHU^dtq6`dNdsoOZFtA9nFfeeP0Ry2HpN#|S#Vmv1^KCCGzC8TjsTGca(eFoF^Q3m@p% zV=i^Dsylq18Vn3v8jKnW3=9wWL_i+U1Q$n7q%}ZEOotJa?^zh7`#=$;3vL#1FiNM1 zF)(oHG1h}J6%V8IFHp$nGwLZYFbFV8Pt{>y;4%W+EW#+w017~3#y7GI45EzEMk)*p zT&9emSt|)f>Aj#hGGheo0#;#^2Ax*GWyv^KmVrToQTmD;0|S>e*zYNf(wd;c!w$?# zWt6s7U|`^~XWUdT$H0)rD7_ox8V9h2>5S68tPBiXj*KyK3=A2J(xCO)TuzMNWf>Ss z7^R#O&m!7)_9DBTH4+%90b8b;|Wprqi=XrjQtP|GNN43x{g728LUV44f<{I6!q`7-U=+x&1&J>qL4*85p?zL5Yh&fq^?5#NlF; zbM}5JN6wnQQNmhS<2WA!19vnik*hPxf>I!NEGVyPFv=!_rsd*5 zGMbFC=cm7su$HU`ojSsu3lh^|lm!iQa~FU{xpf(3K{p9-7lIt9$0)17&A`B21X57CR4#!&)p)g%)lTbug<{0-3nqdh#b^mVBl_3Rc2sd5m_P5z`)%BO3(r#pyOP* zyFi79h{z0(C%Zx7CL(qq-}i#VEkrJWMzH!o;t?VMMIiM*WMx3=7lXtl7-c~NvfN8S(JaF#3p!$h zyM84|N`X=KE+_!N1*{6AEH^0qtOw1bYca}#I>Fo;85p=<7J;HV zR)T?n`y(hF$%ycCf1aYsz##Gqlt;dRLWn`62$bl4f&!HV+*08F4NCkfBA}K6_a6{j zO$2m$BKKbqTSH_zXa?gSh^-}31IjG_L2Mm912qN)ZU%6BRFAJ^`hRI_$@&datpajhYE~>2geu9FE2VA_`@TGwkG4O&5UI)I(pwS9Gu#5|z zC@B5%gJnGUKxb)l3xH*O_?keGEC?=l1NcC-KDP*{e6D8*;foUk4ZSjgyj{WvYCv#{ zf!$ca2WmlZi-S2;d{03kBEdLIm4Tr~`XXq3g(M?rF7*$ebeRI^m>x#ZG#xv?H0b0J zZW*vHE`I5gAP>rdc|82mpwl?H<-nfeaI%2X4m&7OtWsrQ0H-o}2DW5S9x-4%tIWW_ z79_>M!0pHg8mQ%Q;9krK+A_s=M1(<-fqMx!P#E~m$S^Q)F9ma0_%8EJ*S9s2sNW3o z=L)dv`S|{`Gca(k1iL|iZ-D@4ln88)ARi~FBw7#Vs6z@L7tjD9sMrx@U~2)DU>g|^ zsWLF|WN>d~1Z^Awk4SNEV+7?V20qYvDBRn@905Mi@&DXAz#MG_KF~n{+`GU$1HKC) z3=G`6!5jzh04n!hM$iCi0N-)J=^t&4Bs4$+wA=^4Zj1pBU~(S>b7J}4fa32Em=njh zZ~6u~Ysvcgpxk~8?B^5)wir;Ub(}Fkje&uuf%_yQXeSR}ASiR30;fp^@T@WSY49o- zHa^f+ckVM_4m)^QlKU)J83*4qP>Q+;wu+B05>)2yw^42`{ zpcBuz?=phMpvCzjL9uWT97GZfY_7Zv4BQVGWk4$*K!;FpzXqElWx>e(k#W5y0|TEU zD6f42vl;lNg5u;e<5o@3(DrIjUibp;`Ec+>fpW=Lut$0L?tpy#jS+NwqX1to=*S-K z@8Bqw0Z-F&{{VC3z%3>2pJ2x-fT!uXe=&keP&Ga!P;&as2s$N1lMi%u822Br!z}r@ zLA3@Sc)r_;PZd->2!Q9iZTLVpMsN!s0mg*mroRApB7lbJl^7569#TGu*`h$G#R%! z6R3<{0G>_bwqOF4(F^(hgABC<>siEi4wNjcz?{W=xu7t!2fKa=-$^|N25twiY0JPX z3Ai0WD+%fumh%b7Gca&Ffi2e%&+sDZ7+DE$Of6^DThH(``E10@*9vIkR8tpUnCoGhT@mca`UPHRGQH4_7y zay=+2W0(%8GcfRka;G!tYcVi@rx>|2nLy`FFz`iya!EGWL5_UIAWjb0A}79dQ0mHM zTEfV{;LOJkN-cR{Wx;&rpkgW?tSp3q?Iz`(r->EYu2eTRY zW`Y_BE5NP;4F$1+1~I}x1>Z_0&{3Cc4WLLo0+yFjQQ`i~6s4=jz`&cFmd?Qa1srw^ zeAhs6_LC_}kAWdfS{oEGznDP%XeAbD<>`XT*3$JJpoIL7$(WOY!Hq?l1;qQ$l%>bO z;K3sO2UNPTFc;`CF!-=Y-v;GJR%Vd3PgtZy^cfhq*}xtAKP=LLpz?(s%=^nCT?#UV zhuK=0fq{Wlx*Js62{D73z7=fJs-R**1iWk^ghSe?9ux(l%%GAkj6)hUSHvv_mW<<& z2F(v~i-QeK;E-MovOxUb%kfMk~dKXAe7Oby?LmJeQ=T>G0RTvc< za)||*4BYz6K_UzcJ>t@zK`jU)<_UTX3~R)tQ$VNMahotN(_>)RA}+la6xpWCpyt31 zacNzU)6AGbEsq=G(uSZUWe(=u5tm+~&A`BI0p>jrmj<2M#cc_8=o4{iUr>s-Vg|KF zo{CF5fqZWb<~`e62W4r{vBccL%%DQ_o3iu{a8?clTk%s_dOfJH4+Hal zDNBPEpKynRdB2sV--6;U0_^KQ%F?d|K%EXS@2|4-0Z?Ha#SH2TGN?$Kf&x7nEXSiF zJsaeu7%-1lMfwWJhFGvl0Tt<`oS-IP0`nz31_l`w26j+?0hFe}?FUdR^)eR&1N%uW z1_n@ShKjQP*J5A*B@7sUfgS?`2!r{cva1$6+X5=G*g?e@D2%{z>}xZXg8NDNEaJ3Nb!7S(8#|PXdfIWOFd|$PTpRafq^js zBnjHn$2eyd$cjIp^HL)~BWNI{il9+WMlhE#SaBr}NCQZYF$7{k6tV@N9b#Y$T1FrTw7aSpH2erU`%7uU^tbBP@_cSi3=C?Z(UXJD9Nz`&r+7{xR(NS!g7X<~pnV+_;8Kn7*dhAFT{(8gbo#%t3HHLMLF zhJj9;0f|XX|0rW3HeJKGR$%&74Qm02Ea-?BkZd?awt9CVuar7tJW~k+gR%o70|VID z5JmG8WiDpe}Nq(>n&^~LB4nCvljM64z(^oN<@=QOgY0U$X zz6jOl4VD(2{#Vml)p-v)0|Vne@B#t`1_sdK8H{scjTsmeR&aqNK!prwKRG0!>;nZg zW3VDPp+GnxO3c$!wXCfmR)CJF0l7fJ7~}%c=`$>91*UiDns9TefwsfNI599dPJf|g zt-|z9Z#tj0wOBnL$eKr>F$qvA0v&6?IHwI{KWNa05p>%D!)iv*HnOWAhkk)MbT2qj zgqkuiD1f8%3n)sTGQ!fxSC9-F69WUpso%iv4p9QFac2AxZOXvFG|@q|pn!pK`eJQs zF<~#zs^MRtf`(~g1n5LE2C3<1w5=sIY)u##^fI%u85nsPLC59=GczzKgW@{_l(h9h zQ?sChaigd6>cAr5D(J{CCkBQECXgWT(y>;Q0EMVBXy6hYPoVR&K%w*%tVC@3OdV@= zR#4c;O+Tt*t-@OD#K2%b{hf}rO!7NDaN=V$1f@FAaY&pjpvemGaCo*Uv}q&GVBiW` z{_DjE3!a^z+%spp83ThMIC#9kqwEuy85j)rbAYbu0FOUyWM*J6VxFF>Ypo?|sLQ}` z+>C*N6`a-eLHh?mhh6+NoxVZWS^^Tgpo2p|?shSQcOtaD;uXfy-69xS~AbkvO#1H+=}fqK?5^)Qc_s58be8bC`jkORO4oHT|1_oyq1_mQxP?1s!UO~<@(ZNC&lupXP zP3mbZ3=9@v|CfXP|AU2r!35+{1JFs95T7c`GC=d25j5iR%pty$)wh;`_#1RW2gu(` zp)#@h*1~L^P7Dku&8MGHHk6#+uW!u?QThRD2!jR0kRAHg!dajaO&fF=1}MfrMM*IO zs3<9BhI-q;0veHW45lCtnsG=lFffA7k!4^29r(jIXPE^oCf9>~BF@Ud04|Ne=?SzG z9pt`AP)ofGtcCriI)TF;;!6ewv+JOJpQk}ti2<}_o^cMdB?E&Yxcom24lU5~awBkP zodw&$7^DU|eG*jgezKUp+Q3>~NEft2;Us7ZlYs%80rjTeF|bx*oHPBufwjI;4XFG* z3vRKdurV+wgK81513_o3fgHGHdVry|zR5yRaSJ*;Y^@Um!v#x_J7XBl7?ig$Fff3^ zO8G1-PC)17fHVqNL4xyyp|!9mC@@s4K)RxsiWnG_K?iYdoBqMjT8wRh6$69Sis?K? z*3$K0ue^kKB}5H$6r8CA149#3V+jKTXvq=-D49-!iSaNfgQ`l98yF0BgH|uFFu}4E z=%5nDIq5bG42Ixph=mDM#vEm1U@!#DnlZ96fu^Cn*clkCKoe(-)0Y`pt0{sV!N~+F zofyNErC|O7t(5@z%gY+#FD7GaVMqdsfhM3vsLU%9YkpzSNsZuu1Z{W+>DvL7Eikqg z)&&)p*R3JpQ3g&~MGTN!rMwSjA?U0ZkVd}g8;q?r)j^S}W&_p&E?O838I(as4uUO_ zfYuYSHW0@t$d>ZjF(`vhgn)!h7B>R}qYFG_K;h3g=d>*>Ik|wl4D1}RkaA%Pot|J~ zEe;6`cSvA_D1%N10NV%JPY!b1Z=2}{IZMT+uQP!aIH2vmAQ>ZDh)Z6XSPM&l+@K6P zTm`HdwBZ7zqynl$%hX!39^}1gwh-?bfU+7aK-54dzJbDPD@2y51RP$V{0J(Av_U6S zgES-b7&9;!oCmdX3gG?))!vMArr5*$TLAViXaTulKWL|VK{&Wiwi6TppczNTLZ;=S z3=Fq87#OT3fl8+$CXi;vP$O`CRKhe1bYkqp3H8RH8mWW{)MjCxxTW6c1uFvsV=35l z#t@6|n$soCtYtk!bQu^JE5WK#I2jm>K>ZfRDkf0Bg?ZwRdNok4JLJT`u*41=03b02 zWzYct;P3+Nl?R2_Z9907@@c4n_G+JVVqka=(Zf`##h?tTZNOS!iB88JqUD~MwIu6J zCk6)J>3__uWxzF8#dKM7Yc)@3sSXWRNT{2D<|%kVTYEsY@G5&~S*OTgkOK~;b}cc60|uTBq`tsay3{IbapdXBj}u6kem)&P8(FI|3og;)fuB14H+2B>Oc*3 zO>o5xDp(ljlshsoD1&Y}VRdF;0M~F}h86<@1Bk(3z+DeI7{P@ZG`|UIcYy+wan5c> zP|$-8R&W7#o{YF)^`{#%s00hvfxFKi-0i?=e2er2} zouH|Og~7H3bZo>!Nheqv#cn+p0|N+iCbQY=b1^W0FsqL}lOh8H2(u>GZQ@~I0AY?R z?Dhrn3=AO56Ko%%%TUh{qRYU*`^vsrmw^F5%yDS@DJyF;rR`j?)~ngKA4;*#W8uunEG~&p z&MnB9uK&<2X8MMeMg`M#IxP&RPY5t{+g_h#?V!tOF#Tg)wK$7~k)`SO+taNJ*hP&j zO&Q|j-9r7GLp=Tc;^S2;j1A1TC(O5gU?`~xYWaaqvteLhutQ>dPmjE4ZEe_#B(w;L zy&j3Z7m0mxdhV2RaVAF2>Gv*Liy6v*A{1)61`^u@iS3ER4x6re$=ZE-M+!gB^ff8` zJdDSuw_dVVmVA$-h6U6)fSM^d{oo~QaY-E{AhCKw^g>v9pob71JfJS}QXym~MO3THNy>lFT_I_8lblMeu%_=i^Tqk#AfAZV1T6pK_s>;5*sxA z&!`4IBawl@6iLDniS3KTjzVImA+dXq*lUs4myy_@c}SRpz9ES-34l)UfrgzpsLuyw zt4wFTZfz}@h9p#t#O|0LdEHuBas!eOXdMvDiu=>2f~4665y2pX#MYdC@w&Bmy$h01 zF%r80iQR|9UW~-vi^M*K#J+*V{)NP57eY7%v=kg3@>)m|W=L!&B(@(CI|_-Nj>N7( zVs|33=OVE;A+h&?mOaD5>lBj2H6-?XB=&D4b{MFk1C6O{Bz7|ryB~?Y3yFOk#-5&f z)7o1ySOgI;IY{iH>ADJ8;=FZ8LM_t+6|%%VCm;z;M`ABVVqZdH-$!D}%7%-m-311+Dmj#lTcC zgez7dvA0j3d)r!E@&=O7TO{_c>1S_Si`Ppd65A7r9g4(Ggt0-Jm~&wq1_p*oBz7wj8*~c_%x80v#8)D*w<56*BC+owv0oyw zS!6-i&q95v4(cjE*~Un0dnC3u5<47;os7iJM`E`kvF9PNHzL?x40{nAhLcF_t4Qoe zNNms)5G*8qAc-?i-y4@8KK)Hx0uQ79bk&E}%9635juF&PMM&)W>4^`ml~tD`32jDV zpG0C`o4)d)wROFOJR+T_A+b%6*iK0703>!C5<3TpU4_K%Kw?irVlRQPL8*j+VH1P{ zE@VJ=MZiMg9Fq7QB=##L_75aBn*zc!B1mlT1%1%q3PchwRR~6CXhf3eMPkoHVlPEv zZ$x76MPi?tZu;1Ie?91A0+>IJf-e7q+J6y=eHV%S5{dm4iOmR_3xew9MPf@Lu~m`S zh7dL+U~M5BaKL&Zu|tvAphNdz4$VapuS8J+Y3f zw*gJ=LDhm5V#3r$BZ+4qv8$2T;QQa9dM6`^&qrdfMq=+kVjqUEA%OtCG7)MJ_=a~V z`#nSvIBmy#E>}gdVOt# zV?f8!z@)v9#3PW{X-I6)s%V({CM59*NbGq?>@`U2T@W@TDW8CFz)AKR68i}f`x6qI z0W{YE^)eq4TLy^@8bE?M&H_n11c{xbgVdZTK$56KV)r1iXCbjyAhAKaX<(KeK@z`& z#D0Lpeg|WN{12Wvhx&#KG``h4Q14!(1NbEaE>{m$aA4qIA&@3<1V-N3V#L$1_dw&BB2FhLlxzfU*-oZ0ME9SxD?+Bz7f;4OKrAiM!gva2*`*+HsG52Z8=7ufjF5`w zi69B6qIpQ{tspj3!x1F*RS+9$!967Q7Z4ljfxk#>He-bEB|&VEUQqF11LA;JaxpMC zf!H7k1_p*W5F6^C3=kW17ZC#kLyj>6gD{j`4ibl|X#}yM4s8dqq2d!kY|z9G=r&-G zUMPEkF;elo3Zw|Cc|C{?)w~nLhKlb4v7zFpk=TzwY^a*gAU0GDqX`28Bj~_&1_lOE z5F4sS8pMW(*E8sYI8X@_5F6?`J0!M~2?GOYAqZ$iP8diWsy+t9hN@3RVpoIM&?sm@ zV)r7k7lPP4pzvp4U|0p_KoZVoB=$)V8*0!cB=&72_BRk4>Ig|w1_nlGRLX%FYW@deLmk9!#=yV`Wy^xt&`<#_tb-L+ z`bgpyAU4!8R}dSjHv`0mhESdvsCb4-G=U_b?8QjzvmiFq2UkFB(6tVrD<#Yr7=)qh zHz0ASqd$V!Q1uMvh_)v;hz(UE0AhpH)H5(hgE&wL1rQr7!N8yeVuRLyF)%RbgV<2Z zERfiKAT~54!jaesNbF1y8){BIhz&KT0>rL|a{53Vs6o?_*b9)@%Rp?X`cp{k%Sh~( zAU4#TPe|U&!d8+7#p=<-Yp1_og$+Xo~LRTB}h6dvTB=$-q_Er!Z zs&^j}`yvwi783ihC8+#|YWN9~fLg$0g{Y~xk=TMDHdMVT5?dd{2Kk18fx!&K23-LT zTJ2>8+U5=_VHg-(LE=y~F(5X?!}Sb_AP!U_AH;@gZbo8HM`AAov7zeMfY_i_rJzdy zK$bz-yFubmHOD|~h-D0?L2Rh_H4s|~6#k$~*gzbp#3v9Ns)5lO(fDKov7u^2Ky0XG zvPf)W5E~kbHb`t&B(^t*4b>Y`kHpCWv7wrak=Qjz>?RN!s<|79y%5BP>RpAz-i*ZF z31UO_-hi^f{(lJNfMV)9hz&J}!3L2IIFZ==AU4z>btJX{659>LhMMD##Ew8>$JsEb zGcZC8$^c0~gSQyO1|3ZTx@6aefk9Yo`n%uO;`Pv2nFNxCDxC{rL&eu1u{VO)P&NBO zY^ZT3kl6P?Y^WQbBe6dqvHyVBP`&l6whRo6P>wW+4b`lI#MVV(8-v(T^)^UsS0r{c zhz&I-1&N)D#I6Lf#lZKJGcZhta6pm8unmcQ2E>N?_&SIUTHy;y+qMi0!s65I{vrbK z8%P?el+g|;iG$csaX}Cp8n9v@HdI^%iS3NU4n$(dfY?yI*+}gA0uTpkP&J4RRn!1t zL&Yb6*ig4GMPjc*Vjlsqp@DW5iG2-;eFwybn)3m|2B&t0pAZf>0Qv0^Nn8Snt%$_d z1+k$9`6023L2PJKrV_-4s#y(ULp`$%#0ITw16_h{U(diG4CNdJNkA1{0I{JVaUY5O z1jL4_`3z!1_5ML(3ppS>AdSRUL1G(#*dV;3C68jAj z`v(%6#fgCdl$Alw-~_RudPPBO=#@rVpmm9`;Vd(d1oXNkYY-c%!5)e2j>PsxVh16y z!;sjqNbE!;b|#dq336R7lmlXyAh9cu*!9!zGTMmOcOeP&A+e_+v1cK%7a_5iA+gsX zu{R;HwO)cXH1U-Q4Z5rf~X_Ye}bqv(>={>{F(lom_EzQ#*a~C`b#q#f5tu2EzNEG zncke7-eqp%$MoXV^jqdOevB)oYg*X&GX_krw6O7K`f+CZDGM7v#+vDpmNua4fHEy@ zjx!#aZfIrW&-&sl1B1%+LhoYX=`*Zs5*T@=|FiHlTZ!R@&S6Gd4{B38Dn1dpg)0XY`pa=xC$OBv#r+&gl<7@e5Bs;b28IvQ6;+gkr(bZk5#T-H#mMl1lYs%Wyg6gKVllT2%O(Z}pXrKBV#y5PYG+x@!oa|+16pd$BE}8U2)UYM;yjXj16=o z6ztNGIv(()Bhxp=*=R7vO}`aqqs(}5`oB1vxRAM^!7TxM&}_5-=vrJR0VN&=24(@! zYnSxFkkrA3H z#=wBM@M9C`ls=Z_AnPZBj(al)2?+DB+2n()UZ4uU@I#0jbjb(g!Vf7S&_XEqjUUl! z3=C`zPM{k;)Z>a32($ zc}yU64BRCgh?^d`cYs0{deZ|p=(bsoQYLB8O%L4MAQwV!df?^-ojVM<>7hQ2fz1ST zFm4r7D(K`d&{YrMLw)o>M%6P3fDWML-Usp${HBK>&>6;!OrTR`*jPd55HDn6WoKaE z6=i2&-~$uj=;LGoxsVHV(*x*M3vPE%l7Qayzzv!#;W)ztK0c2T658;q9uh##JI5r= z&cMKS4|Fmv^rnZ&pgTe!H$8BHZh8RiWaS2BI}R~s&|Me|-25Qb(3>8(LCJ$df*E|% z1Ghd%271#2cQJ?qx#^)^fcrkk`;Zd~M7TeIqDYn*bhnEb1KSVKfxq(11)#&lKsPKGdLI+L_jw^)c@dMU=Rg+$pvhb=vq+3yE20US9CHcBe^kyye;|>6c+Aa zhl|byy)@4qS482?n;8pj>Xo3OYv?tn(*Gr|@*S^JZ-IpncCA&`Tgd zhjej3FM+TIc?Nn3#4=END+OO6zy-Plq6BoV#vPCkp_f2#OMps=Dppp|B^TUTpe$C+ zDhoQXfcqxM)itbwprp(VIyjXBehEY|6X@vaI#x~4F?^s)Aojt{ggn9z2 zfG&Y(gS%xq=3<&Iha;dI_B> z%9Q6>Z}2cMh=4AE=;CEy5Ct7Q%W;Vnl;A}dgTnAKD=3kQ>VQg*E3BYoCVCZA3ta_A zl;}gy`SI6SK~XMx0909CX9Weds52;VZ-7HlbOK1tO;%9Ah_0>&CEQ!AAb*O29dw%& z5ihj7*ao`7<0mMmgIEllEFibC%>reyC#)xU85nr) zf>eNu0Z{qE2O=2Q`ap%%8`hT~1_abuI0&jJAeTXKfi8oX20D@uTpnn!fyx60NO=Ig3<6Rf zXt5dbF)%Q3d$EJ=FVY4Z%FGQqgquT$O%2p;<9-e*M0CL%RtC0Jpo&V5%?@nB>j|uJ%P3*bacq@?diYod^oL3}PSLQ9h8f{&|ougMe5Ky$k|k z6#O!XRFFFY*cw14fi8pK5MW^72D<}#83e>6=w%Sx_26)W-Ub12BK$Il$DlGUg6$N@ zD9~jPpd%r8kS~MaUI|JEF>E}b7BY7es09=Yy9@$!6B|byn}`4dg9zv{i0J|h45D*D zX(bUH6$90z&rImpONa5`b&o&<{AEH;n?=m08^oou=wH)gXf1~~+D8HBtbEMMobP2;O) zV1Q&`$ZZg!t3mm(gbkFwM8ASALnvjdVrF0vhh7G87PJSJjUS|_g6$^gM#RgY7D+9e zxga!e27oT#0B0L;_5*PlI9WiJa)B;`09EijnMLr+AnG9j3cU@22Xq?*;xdS3pcGP6lBeu8eX}m-Ypy!iAh;E_4ZW5OG!%V(?v6&nuUJoL6oo%)lTd0XeVSRTy+7q%kP3cZ13o5g~q%`W{fQiVD2~9l6{K zVv7k0fx2sb9!#K{BKLp}#qI}1n4C~Hhz&WfTnMz1hijraXrM#rBFHI|UxLotaS-YS zoen((^v^q1m9r&LQWO3xQ&dYbMCEEkXsLbE#+P3o|fm5E7lfuE<8b zev>HtcyghSAmfmaCw~uWRe&PKmVpIy#vj*$NuZ&uC!j;Um#~U~I*Xu7E5Ow+h+tp| z1bJtf0!YdLBn3L;2V6Zf2-|S2TnxG|lN%Hft3aW`Ahc2fbS5_Bcygg-pr`|%p35$@ zbb3s&jch$ggMg4ED7-eT6a#g3;Kz^)WrB_b-vkO3&@tq{L_y~&h>9^Vu*ibU*$lE? zn1gHkXONxSK_1@$O8X2#he0(0%qs6bAgT_&j6iN_zn~utc)Nw19ubX=xH|aAww+OptEkd zpvRDNzXVx|IEEZ_<`Ua>P_p4<)DmYJBKQ*fSof7YCg@E>#F}4eaD`sb0_t@{Wvo;-Hhq zrR+fo!-b_(?H@& zgg|$ya!&_|9}!v&^7kx|_z9ttprgQNgT!A5T>>2-IS(`{_C_ce)C-*t68|Ek0kUfm zNc|6)`qvPng3#-Ly$o-3XC#4KmhZ?0K(w(20E3oA2gKv2c-1ySt-zhQSK|C&67eOKqJbKqr-(j-Bp2Bn>(!9CTJc_-v3# z2kxbymN*|+#)UfQK%lL2?f?NST_nTW3RK|;dOUDpy(84!vQSfaM zCETET7e_p9Q$3*P{r*7%Ci!TYvdRhYNTd^vYsSkAu9vJA3iB@P+E{;1dZ9U z^Gn?anGQSmTk0q1U|QI@-%^i39)+FzEu{@|A*5vI=aTk?6(xCYKI^DT`zSF zlq$8sXPXJ}OSOYC6VkcgponJ&#poW;C551ZOP+zP1Z27a<9*Qlh$_g1j*OtbITz^M zZ#R%TjtDZqkNxKM2jw^DvESTbptxQJJ|>!jr=U1@`nxA)T+;<=Y^3UEf|ABMMvwu5 z+{U23@Om%@dfqqabZ2l96=h(P1C6O|WV`~pc>;9aH|QP>aGwKq-Z!@;$WrKe-`w#a z|3l9ER^ToMaiGV2b6)^C6ms0RfCIRX3_I_en{E2Sr)HAit|aWZZ*Uit8+zO~cQ7d0 z4uJzMj=Kj`mL3Lk;=w&r?xSE&CUBR5GA;ZB@O2<}9cN4e-6#V(0elxI^?*;`g`NP; z4Ze-xG$W`X#K!%r9^~3HU>-ZTGYUHboEy|!?Ii3GC>1+55PBrupI{_3CKa<^^)L|zz>45 zR0n8W`V%9F&A{CUimlI#$CVfuShx>>a>p0QN#NXVpnL;837mT~$oJnE&nkgBRp1H? zdJs5xLI!paICv}&b`UstGz@kSxGgv63?OdkN#NXapre7ICxLSx1l5^*;3*v|?$016 z2!Q89Y`A4Xp(e<*W_nMZjXdM2>1*n2BpH3CAFH!bV>~_mZJmu|J!p87+nfnhN-hA8 zf^u6hflA4R+*zPv9eQ{-H|SCYZs_6N+NO}3kq++$Wd%-_6LJiY+r#gI1|2|IlZk;1biqA$3=_D!13J6g5tK+3Kn}`eN&+ni z;;scH`D`Wd;cJfE2_P@!fRE&I;+6-c2DjDl;$`a32KaCh(cv^$dm#>>yKbg9gi>p4<*9a~3m2f?8Z0+{>7_L7r#_ z)i}$+YzA)7&5GQJL%aWhZn(?cUCDC zP+k*a1~nHe*rduqIU06aw^VvPC^}%LbxVN;^Wdj-OMwRP;HPyGWG<|TLy85IDqyE|OF4pg%FLi*zJfy*dRlk05a_gSDIHK=H)39-4mzz{DqIwF zsy|nSs?1=g zbxSdU@-pnSZm9>L)-CL`ZmG*4XTwhGmP%k{s7IXEE%hFh7VN<1PrnqG`UI+89Kk{Q zN?Zz@xLv`#*Wyy()D1hWTWTJt{pHRqs{%T$Tk0by!FhmH{uP(H1S&HE ziWo1j2U#SfE{lW4mtbdjORWZ#G_W(grEEd&_GR9u4m!hIDh8C>{g}^zcv4bLAeH{i zpwjb&vJ|K{&mF*gPaSlIw^TW(=?go!&~YVDDWe}A@f&RDg+cxQOuxT6@!WtXiGXb>I~o`yg|+OntIU9%8 z7(mGd#^0pQzyQKvKIjbZb>N{gP|3v(D$PJ)1eRlGUD9{gAyb7lvU8#gc%@$lLgdGRAFObU|@^_ zHJuq4rsuWVaA@4rU|>)MRo#qHAWJ}NeB^yWOI5%fCzv%cvD4?Z+DO$G+cGemL$@S= zfq?;R34_W`&;bCY5c3%rK&MJF&e7L|*-#3y0klvD;`VZ|+d;<>g50jE335B=lvk+R zV`0Y1S%S{S>;=sUG1!4arh2-4n~kY7*iw~F&<6cQpg;jRJ|C<=V0wR>jlPnC7VH2) z@F|TT^~#_V%B(e=qG_f zm7fvhNYGKOjC0OwGcXtwFfj6i$4=@Q85j)zgAP962RHPUnHU(1Koe(-)`H-Mj|&q6 zgLW|k1H*l7n6He%sY48W^$6(DOwejkklz$R%OyH(85rEB3wGF8DuE(7S{veC&~cfd z^SQz5Kxcr1)J+1Z6PxbcZNtyMjDdjxB&o9p6hOAq1HICfrvL4-0SyR)FBAjW4-PF& z23?RJ^d&&YUzvh^)&maydpZ!GnSy3u!E;om{9O6+6us^w(q5cHz zT8EqusSNfQpDhCe+-JQy(;v3kh)(~|Wh1Rt!oZ*iO64GbF4RHz6O=N+UI8V#&gl=@ zY{aG?>9mop2N@0af)0Z&$g%q1BhWx+`!X>60ej)H9>fa~U@vHaPSXZQP6XHs&7jk? z!I2XMb~9)c%_IYKdNE9WVYD6Wa~sgcc%2Fc28K1$b9-!5 zZTcXeM>7{~VPwz&6($Veax99eNI{7)n$Z|KTz?02KRu{c z5N5Cp0UgJ75$<--@@U368Ph-Z*hs5~8Za?I zkVC*H+8zO=Qp;Y@884sU=7LUqW}KsH2n&->j60@x_S(p+e}vn?z=RYgjNtQt-Pjly zbV9(sKHqDjS`V^A5p<5~1zQFNenTYBW`c?w6wjJ6Fj)Nu6`PRzgFy12%+5Gxxgi6C zHRy&qMr9@tTN$(+=Z-A{gR&O1R8Rz+;0!7aIwwF0%`~9KLb@k0pKHb-N1?AHQdf1gq=Kg3=GQZ3=9ksAO`55 zZqQB>1}g*5nVk8MC0`5-44|Wq8Rw)MF)$cD1|3(L&!oUOowwhHodcYd3YpGKm+80B zU|ci(e6Nkd^wfSEG5u{u3=GPg3=9mQ5LXs~)-sBq1@9oIEHeTHT@<4MgN^|M1B1cz zRsA+H)}Zu(&;;6?2o7)1`O6?pAEBBI8FWCW@*3Dd%rInNu*{myIKf6lEY+BS!Eg%? z0|Vm@aDyFmDYtFxbnOW?iozhHltI^FfII@OI@V5)pI{@#wjHc#di4YwWr!lsA}Fx? zK?VHU=^H25NCkZXo%|2ZOm~?;byOrf1A}={2?OJOaPJ5-)nf#<_yO2rGY)9+%3=;L zex5QgFo5pgcx1xBVEk2ey6i+7BR^1GpJM{{2vaGjS;0JULp`K!Ruo}mU;tIx-N^Dx zC9r0P4kM%rQFLTvU;rhS(vpnjSdWM#Kyh?`2TM#S9FJFBusa zKw_N`G0IZ5#|QDT*nqHGhHz_U2OW3$u`3EpvVK4v+@kO zpacNEBtp_0x++thLH{M__)l9*_TXl@IVUt- zgj>1*F;q)w-a|U_c=^&m0_3jMJaD+3-(qonj-C2g(`SA;L`XU;>p(pn$yqm4F13 zF@qv#DY>c^0|RJhvJztyILSnV0ycwzf#HQ71H)ga4$xu$b+9sL0<^|4v48}O%2XTS zdQd2Wi~!Z0;C2bf;ovY)WY7iq*0K)N8Z86&9Y94KsFln(r_KVJ{XwzCV8a1A8nzuA zPM~AB8RzI*GBDVJ!=)V@E{s7&CqPBk3~;E0b22bkfGUDp>7d&wG8q_Wf>nWTlGaIN zfW$4xRYeTY^Rq$LfJ-tELlKnAK@MlI1P3JOP6I`7Yu}iGK@u(os*nsBbU+u~Fiw}9 zW~0QYJ>6lNjbuHj#cccrYHoViHPP0)4S2y;3 zpqYj7v!=N~5ng9f;f^$66um*;{e&}G&P3>lDyp_w&kV=)5*!*eSJ z1`W`035;(+w*+``F)(O=!|4l%3tA+m4C+~d;{cR6L9u)t;xAA@=z!|rU~s7oN{tL= z2N)O_v_Za`{(icR7^Ij1-E0BM1fJHARH!)vRxE>BHQ;;-I<_6!&fN7-Qf#{Y3>((z z6K2?OYJeOK4hdBTU67~s<3UH2Hh~HY22cuSoU;RT-9**&gEMTTo%BH!1!PG9=yoY1 zaGj+>1%XQ(P@l^V+)KU0 z3`)4*x)!t};-K8kzyKC^dJP)T%V7rfvYkOo(Lvb7T#A7Kgn5EpKuviN<`r`> z6=h%mVOAd(VQB^i5N1tq1sy96!rXtDU3J76>KSxEI}tW9x}M=;U;tr`E9|bUatsV0 z%qPI?Dkj6g0K$C2%&v|C3=AO5C(7*lNuGfLgt;;qT|wtDf-qMeqw5Y41_lu3ie_~E zFU-II!dx>LUDJ3N7(kdSm(dk;;TH&V<+C%os;epbdedfYh3z)SY!aBK8$5KApT5`MPylp{yw>yu9TvjdMNiqd=`$HyPJj5* zMuf@Oe0m~FnTUk3nE``dQGQBdNupkSd|GKT=@Bps&f9Teo+Uh~_=oTJ`=0b!z% zxiK=&!VsBfiL4UjB7{C;a|t?Q;ZGF8InqJY7SMu`w_(f(kzd28MhjcFpvumbTW3`;de#Be5SKvEL!FL6?uij8g?&4*@mW2#IZv z#P*$TXk{xdnTjM-g~V>3o@iz3&U+0>==F5pNzvld&sfV&@>SE0NgkNNmumc9_FfPVb!(tz3T*N%}4l z`x6rTKN6c4RK`QC2W<$08Rv#19*xA#Kw_67v6~@m$blv^ARKUkxO6(Fovm{HStOxH zNbL7W?7v8CAznm&kwao@A+gPn*iJ}nKO}Y(gbixlFfgP+IAC`bA+f428q3M`c!*c zWhwB50Z<*x{0M&w@K3*FZ>uC}fg}b#?;ol*YC5ljt+-(+lJpWJ_C_T3ekAsl>4^@u z;`P6ggg8O%bf~G?NNfuvwi^;V8i}2b#4bi+*CVmJk=UTskBn9fkd4f1ktB8@vCko~ zA0x5fBe8!YvB4J!Ks}%UI@KS_)uPcO*9WIDe>`cqH-c>4_T*#KUGI2`xurZ$@J8M`E8wVqZsM zKSpA|7nvTnAWp1a9(2M!)M{-cHuz9~sJJtdxIYp*8i}2b#4bi+gD%I0g-$n;_;d&x zlHwLaIN&m1Jra9268kt3`!W*y0}}f;5?c(^iiUc?5{d1K#10e#oxTrM6pJL0IlXai zw0M0ZlF)P{Ht1?un5RHX_F(MuNNR2)v7aNczaX(eOQB$TxsaR!T4uv&#Q<8e$iSe0 zBw>QYcAUP@)mE7)UwrzzxzS>b6Q|#GwN+-^Ii1nXR-E@XlEN3$Ro!f@8MUVWmDUxn zcauOAW+6!IBqVkL61xtG-GjuQg~VQg#NLL)K7z!)1YxIvBl!V@17^QNV*f#6bAj$B zfW{4Iy(}!C)R4r(k=V&d?DpvkE!o6v=OYQNMq+PAVjo6gpGRWfnZD88c7Oe0&~19XbR_m-B=&kF_8uhmN$Kf%p0;uIexP{ng?;){YPv`Zq73UQK zow^Toh5U3wA6sQf(6T3(ZIwvUZPRmoY^|r)$XoGD*I5?LGyQ;%t%0O6Xvzs{fCUoU zbvmc7ZMN!eB%$L-?7K+pSJP+u+WzL{P(l$7mWqwHPWF&UM^p*a$!S#2Lggzp%{~@u3Kog@-^ zNbGG$>?26*OGxYo2zEWgI|PT}4-%UTbmBhLXA($k@In1haT6qQCnR=Y0isy+|Ih92Kt z1TquKt_6uh)wI`xIG}|K3=9lCAU0HD35X4vU}Iol*a%`n)ocT?p$45tV&4L>p?aTy z*wEv{UVtoyvOj~wp=$nu*k;f(!FfR!5I_~FA+ZfWY^Vk^5F2{Vvy~ClPz^`|s-X?Uh914#1+omvo(mF(8ng(+hN|C# z#6AXMgRYonU|={6Vng*_L1N#9v+Efc-h()xDMX;4K-&D5_=tp4b{6{8&v*7IR}s=PJ-A_2R#L`p}u?rVnfgC{h*CF^_T^8#{)F9 zI6-WvdJzyCDlQ3PL&Y^@wrK^&+e@a+{)MNS}beNb{@U~mVqp%w=qvC}|os0Z?q z*cC|ZMi3inP9KO3HD{3y=ommKXEl<?2(ESilPl7MIfT*u$P)3r_0I?ww48|ZfRD%VG4HXAnCkrcvlaa)8L2S?z zJp%(n5r_?SM42wc5ukaVE|56X%zh9XR{qZdai9_lKx}Byy9LCCithxmp^i8LVnfAG zf!I*XE+esDg4obd{Dj2*jl^cD2i;@=b+sUf4K+v=iLHmkb^)=WhWaA0!;si9AU4#T zR3vsahz-@-0%e2JA44yc14?SsKy0Xkc7WJWgIecia>cM9_gF+j8{RY$mcaS2e1|JX`sv!V$+l4R#18Djz1tbnt zlLcZ!)pUZ`pi|ix7#Jpi*iiAANbE&$c0B{bb~uND;Vy^`bp-fE4A2S{1_p*VAd8`F zM$r8bP>b0>Y^XSw0py5f(2#;KNE~X8Hi!*XZvbLL)%%0k;Ons&7#PAp9H>M*5<3&b zh8k1?VuKcAFfcGwfGmTun?d4GHGLp9)Uvrq>_s3pRQ)ojUeMyt`t=|QsOIA!HdON& z5F4uDHHZxj(oY~ZRQxv*TL5&q1XNrN#D~$bDP{(aG1eO1wb!`j`3_C%t zgR+kxDY^h+L&a|*u^%C^-+lG40g_-~V6X*=L)lIsHq@X*5E~jD86Y-PZ!w4s+MoeCsu^_U29(`|B;Jk0o?^tn zFkK`;OQe1~NEB+yJ`fvv{OTc)DNy!VB=KuV?E6UUPe^Pg(CrgYGkHO5&@xg61_nXU zwHHvf3`iW72-HCwsCRWhY^Y`{B(^Jv4OQa>VnYoIMqjWH+@Kox;6>wsF&1JVE$pAKR}#pi(7P|Zt`*z1tkJ3wrx-oqd^^!|n8Ad8{w zOCWKO8c-s*3*ta6c!R|L2x5a2F)%Rv0kNTKz!!Qz#koxw7#KlI-xwGe1VC)41tOrk zI%F9bKr75-LE=#Lx=3sb6Hp@nYN#!ega?QX754?Pp@!xnv3ro%Q<2!KL2PJV-Gap4 zi^M(#VnZBV&u|9Bfm-kw#0J#}pmG<)hPs;7l!1W}>L4x<8>*fUbY+GtXyY{lgAzy_ zszw9EhN{tls+q{hzyQ7g1ggdjtOgYR3=9luAPzKN<$~By&1FdJ9uOPqv#Chzc}VQ# zAU4Ej3~NDbs5#q^*x-vnpyF4-H;+IKy$4bRWj{w^e*m$ehJFLFp_=(YcWgk}8c1wM zB(@h4I~j>x4rPP=-v#A>is#8l?3Exk)Ipn&*t?O~2SIG8BTgZ)?||4)y-$(Y?~vG1 z=Acd>G>#QPcVozdoWQ`KYRYCDjoo0L&c*&Y|vU4 z1_p+B5F2V{2Ao~bz)%O`Kwa97#GZh}o(W<@4Vn*PLk-%2#J-5ceuc#Ths0(FU3&r5 zD+^+S4t)XnSq;R2Izk_bZ3<#THAI8hP@koN*q~Lg3=9lepnEu=>{2B0dJr3`z752N z9&p_SQV(Uid3`!t2G}yI~*d|D9TM!%SGcOPuVh}?x5<3Qood;q=%`8V^ zH-Ooo@CPlo1aY8-t^u*3z6W320a^~vz`(HGnt?$W%07go<}8Q}_1QfT8>;suhz%8g z2Vz6Te}dRh@qgf(N1zfMpi3@5EprA223`;wYMB@kTL;93`of4H|e$l_2)o5s4K35*r3&{pc?~i7#M`1Z18m)Q1(wGHB6veETH1tNNg!2 zHuz=^sQKU#Y>RHE0EarNbF`LcGvWc z8Mfl}Q;~#bBC!`Dv6mvT*CMeuBC&TOvG*dek0P;8BC#(**pLKw6~Y1g^)3?oArku~ z68kL@`zsRrClVWU?*MFcgcWqT1~i;_k=TNENDW>|Bneq0wki@^6Nznz#5P4@+aj?Y zk=UL{Y+o2#gMon|1jb=tV2D6s$0D&4x3A2yO}1eAb7VT-Vp~5(h3T=2ZT%TtrmqE2 z8PorQsD|mjOKkm_t{j~{Z;7oRqrmjHOKd@h;M*>>^`9<~?!q#C!ctowrZdN<-&<-6 zI#^$K8Q6?k5Y;gK>@r(_rZ*?1%PqI{W0aYmyWG~F(Pa8w5S22WcZID#nZBHy{%?h?A7jRJ-<7tYL-FT=D2?fFK~%?d+f}yyj6BnOLDY)rcR`fGblugq z#~EX$e_d@0I{e>tjjcbU#`LKms%HArHMZr9Yo^Dpwe@FAn7$T7aZLXUq83c|U1#gh zbmsE(dFyQb7^h5syUy01v1PjLdRu>{Ki8)Bt+(}K+%x^|dRu=+hUvN+Z2cMMOt0Nw z>(BJ$=JazLZ2cHxrps;w1?d{){%$*Mg{o z>3=~~%yi$)U_Z|VQ32E6f+(Nuwp(nsGcqzv|GL#yn=xa$;x=1l)`WKq3^CI^x7jK) zE|{LX%~qYYCW?VUaQa0?G2!WJw%H0W?NOb+Z=0#Ft69R;%&jATx~VBopN!oV>wSi z=M@+jSOh_AF;L^51$3Mi6X?oH1{OO>1~&#KDNxPF#KF2mj)8%RgZ-a00|OHaYnCvG zVrLNq9pul%!v0Hyfq{)>BgE*Vq6`cy@A%=z`KwGXJz=ZBV<@Vqjp=xCvrTmttUG(KG}(mXS%4k%58zmF)D_Cv0^BcY{`iTQU}b zj%R$&z`y`nV9yEK&d1Kc&MM2mz+%JL2a}t}$iM)W<7Z(14$|iYmSe9GU|?Wzg|M}! zXPmTkW@MSZ=A^AMW90M;CvD>l_k$Y30-#fQ83jPciZKa1;RGG%4?1s^Mc^>V#|$jV zLJSP7YK5Q^^>0s)KV>WCnE^VLUk`MmJ%dmN=qz7-5Sv8^bT&Vm0qE!f4xx9#3=C|B z(u@oYJVKy@lGuzuYyqJKAoa$qj0_ASLdnzjow60L2c0LuW(M-490ME64kl3Wf)49s zIR&~2z#Jq1I>5gabb$Xv1;hdVOF@?g*nv*8V-dOtvd;b&cxyGwXOJQX577Dj`8*5^ z>|G$US-L=HetI4T1-m)ubjQSnpc5wFgH{o4WQGQy0|N`_kV=jwuntqusgte8nHd;( zL1z%~fs`?@ya1h2*>e{p`j(l2fe)mVF9Edwfn^HlINnKVObiTMY#jPbGN7YNszJvl z8Zd1GDd5fkok3~{<}fp`2Y?R$G!kI?!3;fQ-;0HTL3HQz$ER(rG|q4`FmTv1flO!Q z-U~WC(hkgF;tl}WV$Y<;$iTqNy?(mu8C$h_J<$1G0bm8-L-yN1rxD#$U|`?~X99%^ z1NSG;xup?I7NE4o4R%x{*c}|)pmU%(qQH8&xoto$j0SUfxJ5w6qs4$ZyxgFbV;r$e z0*nj{eB3udXAZ_OfvgeWUM~$&7Y}xk1h)&wd5KI>;Dh&fO=mu9t5)v~I*&LNY>+Gi z2PpQZu|k8Kk%4^|=nT(vremOE;4(OJnSOyBUkh??9ur6%1GgziMFH3X1#WFnV3dHp zrNsRi6y>E%)0i0;RJg-HN2r&9tx4qu&8l*ggE{qS4D6tBc#bNjMW9mvK?m<^fet8H z1v=5Uo~awO*@OE#$WIMm4U7!z*Fd?ek%^6sfq~r~bl~kmCMPxq2Hqex1_nMb0giJv z7LW_MKnL%4f=uKD9q@S?YzPDQEzs$IN7GRrYBFo-d*F9D@AdFHjCv-Lm+ z@5jJxR7SQ@1!^PMBsH)}91xS#!6tDru!9eA*JPFh9m)whcz-6;B=Eue5XXN7opo#m z_9`RzOfL=#Fo%hO{VXWxESWPvx<(ZK zCjwLU9gogVPF>m zMW7DrcaSwapp&>kQ3)<-zyt%kFDTQSu}XkW@&{REHvPo~Te*5yRuG3Bw8N7l2*TbE za(xbj%>uHo6wC&nw7(H_CQd#mBUG}2N(Tn+y`ZdD#p=Y#z`({0y4-}Lnl%b^t_U{^ zsKlya^#g?x_dU?@=e4Y$a)^_G{WHjlI@UDM=?Yw+llFhZ&22(9w;9>o7G!fyi9qg&dv6Zz6>EG@#ZJgg z0bU$?Soec8f^FK%3P~&AnAnHx{`&n84=}KU4#wv=z}g407Ie}+C+IjJu;6e#gtW(6fu(O^(%tVVpY5yuKD569^fKtyjR#23S zJ_3dLb;xP_%RzyA100H?lR#>2f&)g>8I*2s1+jwsDGGMbZB~#=8Q7IUI_`ka=4bx_ z((#b>J`c2j_{;;^w++hQAQl4~3&^eP;1kN9u!2s?WB@f=I0PZ=XiyA`f!W}r z^)K@>Knnm3Hc$b;04V@8*`SpexCGE*%jX51t?vh_-?YJ+nYn+03O*gSWL{9U)Cg)} z>4G_|4D14+Or*zF4LTJWbhN%K=s3XwP_{J&Yi8ii2bKLMU=AZUKS;AF8>nDm;uZxR zt!>7p21?h=4D5oSGS8gtKFBB;4r{g&J_ZIJ=+XM1M9aYa6cmHDY@jQc1h_$WN^sb* zfof9;h$Z%5OQg6pL8Yq$m?O==eiwA6xFee;=wM#Z(fS)fE{p_a8&@_^QNqBz4^)YB zxUqpOVSyOs4%RKg!0rq(%Y&@}q+5i;o9#E;Q9fYx43GoyeZlS!fLQGZ)+_`u$sf!S zW?*juxg&sWFUTa&(fXjPzPQ2e2&soS1Y%Su*eIww!oa%OxIw4!aD;=yx@ ztsetAw{D?uxEl|tC#IO$Wc9@ zY&D6E19Y^$gdnVoQ4eA=u(5!Q0iUfu0d%Oiw(qP;9du6|ITKc2I>KGdx1)$ zIc#%4B_a23P&m(JTO`Q9z{C9(6kYS!RtSPlfdn0+!7-n0ognCF{f8jeEn)-hW|H7e z0Xbs{+b%)S(fVvG^>Ls}hgd-E88#NsCQLRKP^*NE1ymNXv4E;NHkJ&~eFZFkK)yHt zip^zga)O{kZ9xv(3r?o&#h{Y+IG7DST3;XOXnjyVWq=*658^O!^MTUPHMU=%ei{om zXagt5b#UTm+gJbgyC@evy zg8OU?EZabb=o^EIM3x#!(9!x}=5o*-0ij?f=w`|qwXMxl;gQfVm#Xv{*w}3hP4D7)m+gcfW zLFXW{fQlCmkZGYH4WKSQBLjOm=%92-aC?@0l@R!V{aj%N1~E{X*a*5S0PG-Knhrd-itFZaAkwka0uN8weoX7;u;KKTR{~ecbilq6=z#sLAfX0`q2-|Jw-Ll<5{jOF@V2dWy%Ffl*LIMQ0Q7);(6tP( z1NNJQKnLu{fy(M`P$?rKv_+PIfvX4PTTvk%&_Un5Ahwv$X;9y<&kuaSz5?j9^L|jY z$q9kBxNuDX`C4A+DyTg;5p)!Yf>1ulDU;uWjz)11VgUJX3dp&RLUN#62Bw1ytrubh z9qT#+#BLCp13IpKCdjibLPns{bykiL=z#s0>3i?kir1@xjuM{-QhHUW8)V#kP(Sw? zB#4YakpYSrTLu;*kY^TL6=q;yDF+=_zr;fn)C&-0V1QJ@py3DxmQYYHb6GM-3beb7 z57bu!%QJuu*nb8J*fXGjT?Gmi2BAk1prhYcgUVh;p{X(q3|wnKY<400>DhN}W$Qs2 z1cZV?-r4X*6!n1pR?uPhn?Ru=!@$O33mP(Ei2#jCiGs}846+_{z`hyifc5Eo!|rZSA&i?)CJkX$_QdJa9;uiG8-c(@v(4&t_b2{2j>V5?i^4u z;sA3v8Q56Bo<9Z(X->vmG1vk7zd;6q28+0O7(pq5fg5y6J{K>T!^oXKea$^v#gx5b z3=HhYLCHfLY#!u*{c_Nmir+xamIsS6fNs@f;8I}(#VreW3+Nzwbw-e?JKWzv0jI%O zD*-xSzZm3ZO-4}oK9SM{9b2!%7&_hXzO6|8aZupsF@o|h52KVZD9ZI2nT=tCYkQ4P8K30*$V4IfG-Nf>8=|!WWkdSgwXq%9@{nfyfKG{x0O{jll&J?9 z5(%=0k5OhW=&ai)P^wj9lwkyQ>7qd#bw-&_Leq5~+De#8fZDCvTaqMi&=$04Fv8EP#P2vDgf#00wqBap^uMq0TSgCryvWkB6T?xmoZl3|nqZAa!_36fD@lvxf60B~`q z!YH#7)a+gl8uZp;lmRuBxHp0V!iZ6(5OiMaCQw@`iBaYRXn=4ZsC!bxC;W|&yQCQyKo}ekObl!+pwV0wbx;f+7Jwe9586j4WDWA~ zRZxaz5CZj6xo?6J8Vdu<9gyv}W`oXFDdE1u13FTF7D)SDh+43|dmuK8&`D5OKK{iD zYCH*j5}JPCv8}jTFi7y_aZt=kf?91KLCFVvratK2M4>03!&AT1PXGJZR@M$w%X0q# zrCK$i98lo=1+g`RCWD5<{(;z9LPtO;`#*@S!#y7qVGN8Qjvn{<=@CzC71+hWXX>X< zuYY1ISr0nbfSU(gp4o7Nju_+S1($RV+*?3?-~-FJaQA~!A3s>egIfs{!vbI#AMON@ zD+Iv>T>y6ss0}0nE)YYwL1zMRi!y>dQNj(Xdb!2G4yoV<)xF%}AP(qE{qrCXN-(~c z1)Zrc4LaCHl5rgi1L#csE>L!oVgwDxvhz#vfo>d-0cm64;+NV48bFr?^LY5B-h(_U z2QL5k_#p=tLke?#ekm=`@x_YZ;!l8I3RIhOYk_%!{Pj|bpo&8q%oXC7dJW1=I$&dj z`5D+)Krzn&iqij}HX5ktl4oG&1Nq;8QAvh@fqe$Zg^r9;pn@87rhX^LGgCk*bqP33 z7`U@Ru3ie}uz)Xoqaojeb6nGfSi3fL3xsQUqoWRWnI#m1^n3KZ5egWjvbW z;1nY$cQJ6k1|6<_ni13#V&k3yipVoy4m&rfPs)83tc-*EHptwIU>o_kH-Ji-OJEK^ zH>mXFz5-Szz`YQZx^9AH#JEA-OYXaj$-MOp4C36nAh+CO1cj#r13MR}Bz?eGD9^wk z3)7WV!6CxK4Z44i`x~PH_y~S*jrScK@-p1uYVHS^ zBL^PN33e(N-%z!{`G~e8e`OSnU}VbF`$u8ZgVD3 zxw-&6K+0{w1S(e-a)ZW@xGll+FN?T$fYN~#n6sFB1IVZLU^|y^KLgq60G|9<2A&7v zb_CA@E$7ymKJlfkWW5)tB=KSb1vC7>eNci}BLyDA^kV`wQ*{`nZiDh@7}y{aMyctb zn1@VInSxp#pv=O?0&4t$r;_Nm^+hcse}$_ z`otcTE3(1PcZ6I>k^{ELiQ5{KK605>F)}bXb3dCN`pQr4pA=3sW(1H8$pv<)h`^zHb3ragY%o9MX z&{?IPf|`Fq%%Ij}1)J0qP{}U>o^lG|kkYIN1-2+Ns3Z&HkOB?yaf^W^<2a;1!+PA} zU_%o)q{KnRgak9F-=4%FRR&79kU6j-4kngTb(r364_f;pIX zM_eie6iyak-UD%|FQ7=Y1UvMJxYRn3DOSv&hRaiNDNw+2TZ4Je#HGSO&b9&bo{LLK zf-V&1wgq!vh)bD)jIjgrUW!Z22f5S{Z0IX-De!GOu3+A4aVc=>c4G#m?lQN<98_vXF@ri?3@TFcps0uj%kij4C4&-T44B8OB9#TQA{MMt zKt<|5$V&;#?vMlbIY5p2`=FEjpal*aiz8?>5tKVYX&frbQKHPi07@<}zNk6_0|J!j%TLg>1*p>$t_~>!oETUb*fT**(j?{{ zWd;U$PG$xMMhPZRiUci_0i6ubIA^yy1B1eA(D5x&a2bV7pp(R;nWU#Dyth>gO$XI+ z&tTd>6)@wRFQ8N3L5*L=XP}Nc=*(3WuqiJ<>P|2)FsK{>S@#m8P?V8@K{bh4;)wr?05d>K$VJPhCw{aQVQn>LU^qIx>Z7exeV;J{!#%iukj+L6T7MZC z7(fyr=aevj1PwvGV^C*XTb_}DfzcVX00cBr#lSd6UyFf32OOx*jG$0u4AKH^_nKu4 z^9}=pZUpG$s2;F1C{8WFCs9^tF)&OQ{$wl20oL8eC_P>0ldYUK$Pkb!(219fb7Zs` z81%qVxB}eGS7(BygjI~v(@Q_u%GZN@_CyO}U5SDw_^Jg>@Kp;MpoJ13X%=m;G;_%s zMr3&{&??AfaF>FlNG_{+McKgtv;hz{lTDU zFJfTO038wzN|`gJ`+TvLt_P)>jXI!k1l?r;4Pej-%b=uk3M>Ijy@m`L9E=PMpw#ym zED_Db@gJnafpxZ1y!!H!j0Nqlt*O-C9M-SrlB9O}&jTkgQTj@X&pk29|j8W6o zzS;6Y$_>!@xFA<9)q}V);+w5ZJt(4f!p&gN03GT0OOt`&EJ92Rbh*MwSjq-v3efgc z4p7MpauC>a!VJbBKPVM~Qt1WI-H;&9fl4>VIllU^#C`$fxl)kl=7LV_xwINId9j|A zfkEvAC|g_xd6qFs3v@;S$X(FH!(h@1I*u*|+%*LmdjuS2sRppz90ShHpnFUq<$4^r zbO5bTQmm+8V2lTM13))>Du6DDWJ~}X1iG_Xg9o&`9AwoleONFufXn2o#taPV_6*SY z1?>d}h1@Uw=?lNxYCwW>8Uv&ZH8g+(=iBeL!d#%_panW=-+%god*))(6@J(X#C-rA zz6eT73=E)XXPk4^kbyz3L70Jo@eJ6hEo`uY=scKzl8u4E^d;ypy9$fVC@JU$fXWs|cohpe?3Zy4XfG+G2xepgB?eh`n9rHPD(%=A7}P;!KFC}R z(8?rGxH}s`g82VWTVZgD4L5=~x`=@RT<(JEbXaQ9-3H2Fp5V?DD78Qm;YK4^YVibH z3|iG>3N8!1!4_jlcDhBNMnN2?y8$wX0kj>HaZWvlG0dbmuu0R{85ndx9XQ4~u$_#- z5OWh?=7O>+D2>4!X!ZxR;PwQQv@!g|V`CRa1_rZU(Co=cCS#B|*hU7hxVb5)>z>05 zYUWsM1l_8&5wrr;$6~EG0|N-NCRijgF))BIkC^2Ieg*~*wgTO$4Z<8pI4wW|Aj~6a zd61QX0fenih%qpLFvo5_tC^w<3?R&{!D1D~!N35*+|QUTWVsj^K$u6xYN`kW!&DIl zX$Fp2T%fuR>_U#yd=^v17#Kj9H+XtuGMB>i`FYOr(_=3baZcYQY9T*euDywUyTl(` z8F}z2#?xbb4EeU_OWS>CLOsgZbb8DVZN=?BFd@82~59tUrb?pnuFa!78T@khfPh9PYgCQFa;kKoSZbh@QI%Ab~{(QAQ{Q& zpo@l}JJ{ABv3E{inP_M2`5Q?{0CXfUR4M41P(~Hq;q&rvLqEDXzK=N$3a?`z8|m+4Rg*J7q?`>Ak6T;=KBx zvwoq5*i3I+!YQr_K4lmx)QluO1BtzK`rA}HamfQnLRXR4kEY9}*(uj^f$9vXN%BZ+ z9V9mB8ey2n{E@`LhYCaWrXz_LBeCm|*xg9%=@2$#r_^Ey2b|N_Be8cQu|Y#OFh^WL z690w7mgZ$(fT?jrVnWg@YUAhB;Eu|FcQ{|Zd6I}{jZB=IC9b{-PD3W?o@#GZu2o;O{$GD2K(8l`dlRGY9w|i5_>ul8?=uHX2fPB@q%n(W39*OOX#0IU8g{jX(5(l3r3^jil zlK3f!U_`WBLy~xe#0H-s4AuM#Nt_LIpf6Nh2#GB}{b;`3{(3ekgwaw+Y&9gd5fa-D ziS32N4ntxmA+ht2*i}gEHV7LMu#+GhaC)DI#9oEO-iE{mT~P`Pz;j6Aw~*M+kl3G) z*#D8(Jkryf3hm;i@3BncFT_RiM=0*eHMv*8;K1%rW@vO9?(g?uvVucgadY$-gLzhJ8|AnB%!3~t|fNL zlCzM6_8_rOPH!x+vz~sU#EyqiW%|hyJ8Q`_(5b&rUsWTqJEqH)+GTtGLlP2KK%{J0 zBsTb1V5kvVNa7AiY~Se@OYMG7zfoq#!&ou>W|>{K?Jv*`rBH3)^MIjjG0<7RP_`oy zI}C}PJiW2p&YE%Q^u6VF;=IR@WG+vCSZ)_wZx1@n7ivfd5<3xzU5dnRL}D*NVsAuZ z??+;vMPh?4@`Xj#ONclm7k-Cuz>&oYI-M8lAYmjn=r&!LW_=`aTO_tO5<3!!osPsV zMPfIrfcCpXEt`lWF&~M&7KwcliG3Z3{S=7}x-1^%P|!`7Fg8EvpkAn5vM@Ht|JpDP z0|SF465Ab#9g4(GMq(EtvFnl8y-4iYNNmu3(=Z2ZR|OsL0d>()Bt@5z*bkA|?~&Ml zk=Wdz!+D|RNFuR87bL+fGer`2MzHx90udaB`00uJ1jOsBk%U0En#0VPjwHSmiM<(# zeGrKq0Xozd>aG+dc0Py=J)^f+9dV{_9Y|aeG`a~o^8>_zo?O%iVnYp@31UOVS0J&s zA+h&>*iiMyKy2tqwx>XrLD^S9;!rjBL2Rg*Pt=jp5ZNf(d=hyxl`1hJuq04F1{bCB4e zV~iQ0>KB8=q3ktC>_Z?n)SS~u>?=rY&}qf>FoPb0B%lT{gU;WDvU!l$N+34WP;Df( z2@)H0DlyDVKae=ooIE6UAA()aupGf*0G}ER)o>q4{5OaV4Mrx=aktQ8SJ*&j>q6Or zAaSS~c@P^a4muDRmZ-r80z*$Cwg>6u0);;V1A`Yx15|S;hz*UWC=eSeo(f_^#fy>H zpj)tE7PNrGxk0IefuRFr0hB!%Bn~wPbmJT>4K1!ml2`{~LoL`0VuSYBGcYh51hJvw z$3SeTp-++6te_)tq2jV2Hq7>isypZQ1K!V8!BD{Vnf9nL2Rgaw>Id|F{s1@B#C)Q>@`U2 zT}bRBAU0I*MI`n;B=%zv8*15G5F4ug6Nn8KuV-NR1L8mrX#}0$#|RBBR?xY*JPZt= zIX*tndAeW?3=E*PK(P3e1BpY`t0S>(L2PJFaYJJJBe5eu?0TrhsUQy2ph_h6OeFRu zB=%_}_7fyFGw4`bs5#&>eW7e;B=IC9c6~MyrxC=4x*B{)FO)qQNqi584K?%~hz$*u zA0Rep93ON-BIvMRC>ykU9+o@6N9#hPKn!$xEv)=k0CAua;4^ojhU$aFL9-JK3=Ae9 zHq=n?nY&PS8j^TE61x?|hI*h6i9H>Oy+99C{zENT29kgpx(kVY4vGB}#D+Q!e9kUt zTNvo%deF(VP__{0^jfGI84w%lF+~s?Dy|J;gTz7Qj{%4Sm9Pb|p$7SZ*ii9E5F2_3 za4g6&C_4ir4pmbOVuK6?olFa2L&cjxY^eAoB=&TDq&5loFkYylF)Uy3x%NQ6yQ<4`!;!tz0sem|8MPHHFVxZ$|q2d

+_L>CL*zCA+gth*ieseMPlzmVjl;wp>DhkVnh9L55yLM)Lo!cbwT%efp~90 z;;@|h1H^$k{x66P)yx4pa~3Mj3t~eJ0-vf2W$S>%p^h^}V%s6HT|jK8`UoU;rV%Ko zLMxH$4w?*NL&X<@*iiMGKy0Y^UJx6!d>2&Vg3N@n z&w#{1YNo$!wd1IVns^5$%D}+z3W@y##D?nR1f3HL(#gQUpoqk_L}G(a(uJz=L=q1` zVuv8H8KbAiw%Li-gHP0j>dQis&qrbxBeAQI*!4*4HY9cz61yLXJsF8T8^VU+JlP{`61pTW9CTIAi+V zb#|bG#&p+%)z*TjDbvrcw>!?bVEWVzcIAu)(|I@A`7^GV9t)xlOkWG4IHvyvQ5&ZF zZnE=djF>(bL?ujr3!+-4+ite=XLOj}3!)B8zYC&brt5C8^Ji?BUc1HaIOCG(u3PQ2 z86QqB+-j%Hx@QpsgTnNgTkVt?8K>{vYNyU>=gPovVfw{LF5&5aw%Q3W-8nm*Z=0PO zE1xd|Lj&YsEuU?60*pG-W4GC zf|D5N*en+I#hRcKx!6~UBF^wi2MNK>@Y)O7aOld2bcPq`Fc2mtR&6Z?29^UH3=B+= zGrTlFCx1cC@G??hh(ny=Rih3*!)vB81LzE|V9+vt7WQ^g=owz1{XCE}yx7@TK!;&%ZM{Fmz`y{?@}RYQ`$0!V8G}yp5&^9PU2a2ec&>dbXF>bl1~%3Yzl# z3=Ax47eLDWctB@+eFQN-D}v7U@&tK;k;$Ktfq|=Zdf#a~U8bM1)AydXlQR9F0zSrT z8E6?eJ0k-FXu&HFX#WX61DB~B0|Sc_BS?JnSp^rI6{(vf!z?a29!s56=)Bp5r{1y%*@BYz-}xH zT4E<$q`<(yZUSOU2!q_rZYspcP|qMEyh@ybf!z!g2%sat7??r9{}tq*i_#1X?B*Z= zAs%*{y&%Wj(qv#@w*~LB6@Dzsz`zbU0!-K$peVhdqptGD9Sk$M#KW8Uq3OfCP zLGV3jhFEaEENBA?%Rey&2F@msCs=ZL7#KKPKZ4F~_`|}$z#;aIj$w>obp#q%Dt zk7yDo0$KJ{0r4$f0d=Rqdk5oBQCJPkI4fv*$f>@!U4^`I5U zkQg`%i2(*KJ1zzW&T~xj*cljjIXUk#NrFzU0=wrP)IDIM?t_hDgoOSBaOgAfrGicv zdV@v5y%QqM&}e`Rt1d+ z@qq>yImMZCKWtu5l&@f8&#k-f{juG8^r-JN*!zz z7X#Nk&?yU=%{(QYl2SX0lVE4YLXQwO__nc%E+eyIupPG%wb~SIttQk$@~MP znTOMcxxN^#+ZL)D>~lM)JK9wk7&z_0x;gm3!R`R&a58X-g7T0fvneM7gQx_jGxJf< z>0V%WxPVO(I}J)guHdj0TLQ|aZeVYVodJb~JJ{V~?$IC%JeWbwVBq=$iak$e(9!5z z2_Sd-G2aCp4)Ow&U_k@}8w(X;wWh1_rRO z4=5#p;)WAJfC>i&t}CDvpv)QpQ(28gC0Gy0bOx@updvzt6|_o;V-BWL2CjNgDN}F8 zx&mh4F-%pE>Y5959Ra5+E68B37ob`^2*N%OinSaFy9VUEQZSpBi?f2&k(+^m?=~nz zDp^706a$|&$VFAGpdCMKd{;oZyPCEB73k0{zF(kHyN2~1=uk+$08jx`%L?)}Cj*xU zC_~h-e&YgXtwz>vxVcTp<~Adn+ro-uY%9cA1}<+;t5HdAW_K9xt{eV+}I6JV;3qgFmP^UUCG11z{bF}7^HU->sB5H23|$Zt*kIQ z*oW+a{SXf@aDlcha2{XKPa~ zPqIdX4)kK@Ji~etZq!+*QCmRC{Tw)|*%-J=K;^@E)}_1*45AU77g@vk7#PGrx_uK|Ml!5C3C>-ywUgc$A;Mxu{^&u=%HvO1r-F_ITgAt~AO|UCKslQeL@;oHE=%Qn!@3Qm;=**kn|6}* zGe8C2XVyC)q30lD!I8`LM~Q)flZ_3ejY|ep-3UV1piNhtVqi8e8>c#3GCu<}^J}ny zGCu<(^J{`tFhcUa7TbS51_ma+MW8IB4VGc%I|eF&b=c}ZgIbMzpb2GJ6bDW>uq7-I zlib0YMHsl=fQ<5B6A)lv;H?+o^k(Z8U|@i_$_K20fj=d)jDgb^><$5l)qY^zLJ*_; z!5m=*E-{ch0@!>(MoDl6vt5O|BLw0Oh)JPflc4Sh18Zi3xUfDPY$H1Zml7y;BG{&b zj1uRJViOW%VBiNGd&U_JR>HtH5tI&M*t9_HbG|d6LN1mKRQd}ta4~~YdK}wB&`Dh~ zoC$0xf(#5|C7>opA~?*&K-ac%CV|6AtO-==Cxa~zs}}>+r77Sb5IX|ONU2~?FmQbb zg=QM~7%W~6&J4CGphKwkgN)1srxOM~F;L`Yfh9njbwPG=>4Myt%~l}Dz#z)OnalPD z!17|H8=wN1WMwA7mLvXeM*Ulg=0~-s-QeFejW;W27$o!c_44f^HAcTZx zE0`m|pOTTyP|w*0<|#06Re`FP4mM>W1_n_B&MvkFAqEDq?Vz;X4K_$3wTOYU2dtWb zYc(4K17|N=Jm{32|Dc$g#0ENUfnx>8L7-gA31Ts@v4BkBRp6Y-rT{wqY9gq_n+0Yw z@U4_#V5sMu&87z0R=}4CDv0K=>3|NT;RBs%!8w=BNSJ|vhwnTnCg!nO2!nEn0Vp)) zv)KtVFo^KUgQ8;*n~N|5g9P6WkTaIBc?m;~J$nZ_1(ijKi-CcS1=R3iV*#~P*jO&` zfkcwQsz5qLk0aEL{1albq znn3yB71%;12CfC5g#LyNWFm{DC<6nRF(_tOx2vPcNh&aaj={PBIzFqC z5hTvQ_Xl+BLlv0A$hT$s)q8dhj55>3?%S!=zm{NN;A#d-@$rF{eQ>paIs6P8m26sKDI0J*QGe~^{#7xjxR@{vs zHk0slO$G+;CfVs$5A00qZ>updaJPdb1f&wv3K+OMKqoH>Nfm?Go&F*W48p?Ypkp1n zLB*AbunS1D%sFncWF=hnKK2Xv6gskfR-ir-3%GPX`%VFMLy-fq{Dlh}|H} z0oq$V6XfLRFZ|3=A8Dt*0A2v=gtt0NUL>52W;}@JWzy^FiJAYmk7F6o*Ei zEdvYaByjEpdqCrRk3mK*(FYwlXb-AIK|?y6AcBFV66Bp_ULdI`kQAuD2$2%9;a+(b z6ujV_JF7sU!XW%o0(3yYYEU80D4YU{zcnB>yKwFFdk^ho>p>a>gtavo7`QiF7H41( zkt$%|-UzZvLO2?i*i6EAR2dk!cY)X}!ttOO+6`i}F|c%kcIWS{eV0gd>S|7}<$p{MHCoysF=Moo03D|$^AcpCCF4zT&~a)q-$1Fv8tmN^Mj6n~5NgVGa&@CSAV2A%*An@JcnO2-ojVzUUxsWUL}1cA~EoA4S11_mC{U{J@B zM;J8B#S`)kbex*pGsWqFPwga3nLvkxM1VB%Fv{)LWMJTl1X;w#D0d2U;(Qb+6{|7I zNr47Lqd^>XM!8kf=RLKPG?fLNn;H*Fby|#aIxGwfJn0|>+Kh5L#26TOazPv&Mmf;v z4o?ASa7UL>j&b^%r*>-ffuO^5OF#;&8Raf>Ffj0xg3epBVT2SeZ=|6i#KZ#{J7;HL zi2(Vd5)>q|6^uMB(XtE-!iSU@7L^ZtVq{>@Vw3|l#CSG>8gxdCa%UA87{0`S5pX1_mJ>o-3er z%EFwW*uDzN)(pa+?laF#P;z5oV2J?*!L24)26hIa5}rGsWv6q!u#@%%9e2U=7&Iiy z0iGA&c>=PyKsXGPgr9@hg$yiRpkRHu4itxTKvDP+ls;rd_<25GkY`{J1}!J#`I0id z;Dw#69jNl<`2$L}YQhGffcXnzYX}E%GBEJ`1F^M)jX+8JKZvcvXADX!42&R-9$)hG z(=Y54>i@|yFqrU7R%Kw|VPyol-;{4YC@FG*%MWY5Xpp~oz-68dALxuV9$s*1=)flo zI&zl}EaSqrU4wyvhaW8C!IuDvZvn8351$IiVS?boFo4e*6qh34LNkQ#u`mNeJ&!0O z$YUjZp!%6d4D7fHK2QbCBM#@(c_$G6hTw3_OyIUsyqBtjU;yDqtx_ z&6NeS zjO){R85nrhfmI9gf$o6dSr6u@L&}B*P)PtP6+{`hK!ch*8yWw}GcfRG@N8xDQH1sj zdA5NM)?(lj0a>se%n{%N-7dki1I$t2V+VPB7nozfR||60ZZJo{0o?88*~lL|gzKHRZ8j z0+omh`DTF1G)pE>VYG;E0w_|gz?{W=H$XYu9&G6nzAh~W1|A3Sgvv7TG!>5{c$#WC zpB2ajPGCJN_)c&!Fz~p8IV<^|f?~&u=>ur3&MN+-oKyxLUnWp0SR+#j3R6EOP*YTg zQRX)&afg8oH(`|70*Y?PoErFyG*HrKWBCL+=Ll5vvV+0`loOa3xK@D5su-p}iVO_A zp*-nK*(wYS;DKbGOr{>tu^N1!BTjj;mB21?3E1d5;F@j5L{Npftk< z?!W$FkpZ=0c-X-#i!bvF4F(1c37Pkx`0-=@ z0pdx?NPtxOGlR;_7s@iAv*36Fm^m~V7~Uw$xPj`(Ah3lWlw~48jtOQ46?Wg0Wh?~q z85np%!B+fKmMH}l%3)yMFJ&3f1SL;6nD<**26T`wPXstD{wT{_2gOe$nDXC}+lidAuqzYo}lQWG7P3r^&z|qr$)qYHfoOF}&4x z5!8tTWjs*wg^F@pt1>WvQUZ*BM}vU@gu#4J3lcOh$i@OHl(<0!6(~@^a_kJ;AVE+- zK>2JeoqV9MEjHMDZGAaX#7a=YIaW~L@ zhx&!w3=9GipeSPy?$Tsn5RiNZT1h4h>T3!}fy7yapD8jh2uOp(*@P`w85jg)Kx_^M z7SI(S01B0?V3j+gV38*Irl28Fn2i7x|g66ZBCI+a2*0v{DFfgcr z4kpvoVPH^ajAArk(C}gaGnpm^FfeF3f%bH6g1Ssek48Y<4RhNN5 z2efc`-*nR-cG>|FdJGJzpe;zpK}SF7N`r#+9Vk{n;m0^9Pmh5?zZ0~N^_> zmPRugs@F5dFd8v1n7jfdR?zw!1_sd0-i&iVI|fV(7#M|^KtqzXpaBL?P%sFA+iM3v zM?HblvIr9>F*AmkgOW0%D7Z=W5Oi`RD8X@CGB8+x*0(T~FkIIM*%`%D#K@olIAPVPHQv7%(tsfyO`>4Z#i&XJTLg-3`egX34;yW&kn@bn2cu zV+^A)gQ_V50|O{B1$JY;R1Smv7amF~uxE6GpKpaRk93;vB zN)?QAS`CmAga&Af2gHpG#&MuSCyJQBLre?|44{1ujC1yZoCppBh)gpR1A`f81tnt% zQ}lGc-*z&Ia}607w0?uKd?z^A7BMj}Sbz<)E{TdYC|C*@u}J7*s*W=Yn#8HYkcfxifA0M;Q~b>28|Vg44ToO}M1AEg2XX zbS)VestiFv6vb4`&!FSU09rhJ?YEtZ&}-0PFzc8=o(6RW80YX!=lNqNCkBq%bznC# zhFBd2C5H7(DbpSP*r{6EfetD;1CO5@;P??WW?;|)yY>tdXr$;N69a?R3D9XNXF$z% zh8|`H2HPvs7yPl)gA^N}#l|2fuQGxZ8=wBb3KY;8bRe0BP#Mj?cEa2sZ|WRi0A+ND z`k23V0?JjO^A!Goo$n8J#$00t2I~R_#y^k%46^c^-v8H59%3aZrGpIaGM;XzX)QMW z@?Seeo712iEyfJXVvrNvL`@hNv_KPajF5Kp6cz>s(3l$o$Qjz8!Wd)@%XEW(cKTi} zNa@RX3#io4ha2YrcGX0XaVpFV42=5V*5g*J#?_cWe75hOouqF7#89>(2Co00iE3l; zCQ2{3!JwmB8RyJ3WneHn20E<+(hvpJ8K8Uyb|xsFft>jfYOdvfJ7LxsO9lp!>4E?4 ze8D6wQ<2!cu*sWV0+q*Xx&xHecaFsOn~ z;p+xvzzR^zOh547PE=|#SWh&g0VppTs58bg8ZfA~GcYhroBsa4ofMms83TjX?Wz3s zVvH$M)$BDPaRW+|AjfK(fdgS`vArWop~n$W}*lr2w!?so;9;m*J~=b9MIU zQLIG_9H1j7?0;TH%Dhvz^qUH1>3{S)xyl63Tj?4 zSurrEf-V8&12I5L;-suVwHqS?!z44XTF~*9Y%Dj-85k53rW-KXi`1)FFfizYv+PMw z=rRU@ou>vefS-YZ;l4Hl1Gtp{Do9m9_i}?mlfiidXjT3RCUXl02DblTpcn%hAh;*N zz`$~n$sZ&RDo+>~z~U}fL8Fs7%%JwX>vk>%1`y_X&+JxjFUG(C!mK`SuVon+K$tbb zH9?Vq0fc#kSX@Cj0fR872&e070R{#T7W8IvH5XuD0AWsZPFE!<1_lu3RONJEE6l(E z!fq2}7#Kj9FW9Y#gMk5rg%sV~co-N!SV+ZHP?SNHK@c<>{E5+(iIsr?goSyS+|+m& z7(iI$g`24s1B2=GbY^?mdeE6!Ak6OVYOBD&0K&qROs*mv3=AMF%**6zqrt!c!otc- zuJ5E67(iI~4x?*{76StabH3+r&6Z+d0AbE>4mZ#VSRgE#=mxq`8HC03U329b7(iG! zj>+|e90LOg3%_J%bWK-fU`U_N#bPfXcNTP#DX5#XgW2`41Oo#I3(jJ4y~@SF0K(jR z7+palpCBwO%j^m|*b9WYr!u4AEN zveP&07T4K+fyI7<3iy1(?Q1pdyP3g98*We0wbzN4yvxSGzz8Z(85kHoA+i5YU)f`C z?db@rsi4xJv3!`)WF+xIBz7$ldj%4E>vY{-dvVDNNJ3AM*q^4y_S!2mN=C9f=(>ePge^yX0adp&dxN;Nt8+5`g149jj1I~SO zk=VzP*q4#m_mSAIk=P8Nqx+y1@J_Gnx7U|+LJ|r`Vy8?$*l({a*@Gkm>b}9^d)@TE z{r2&^;yj4dqBH%gs#|2sHB!Q{;^#9)ZM8L1Kf(sA1|? zBZ*%`V!uFQe?ek1@K1NrFcxD}nm%!oy|rWts51n0Yb6r9ZTizm_R5l=D+*vXfsXHo zvF}b-oNTWw$qG6$52_npeR}L0j8ywmURY>f1B=&41_68*O9waunDGRmt z3X=F+B=%1vb_l4Eti>>WvX-%+D)=CCsAkYTkT6H@fG7gH?&$QFQ|yBc13}FjsM1&@ zb|w;g1`>Pe^xUcT;OF(V|Ff<>?2f+KWqq1{7fq12?3gN&}|* zW@d>q7Eb4!X5U=T2S1C=xpniJgnYu0&$D zBC#hz*pOU47s3I%a3vCZD-!!468kI?`z8|mDH8i568kR_TME>9g?d<39JJ{g%5gxF zNJe7kBeB6}_CeLRBZ-5SAHm{wK9cxqBsTcWKB(SXFmX_?<1LKCz`y`Ls1K@$71UjW zvIVCfbS@H?)I<_8L1NoaS9B>7=Z!-W%AW2z(_UE;bWIG*WuVbm7<>2h#+mlYs*jO$ zyhmcQf{xgO+ATEw?26*OGxYo z5H=*Gyn}GSDdi6mn+tRt9@M=ONNn)=e^7A~BylGsb^sE)5sBT4#NH?cI=c{R&|V~o zlSu5VNbHA5?6*klpGa)B>7ldj_t(D#9lZxNnh`X10A+)Z-h;9wk;GMz*oH`KTO_t8 z5*xJC78VhSNaDE=HY8vxAslePwj!}7BC+Qpu|X?~VTNu+5>pW(5Zb;4WNb3FblMi#Lbb|pv%o+YW$JJqmkI@NNmt@d6@b}B=J7E>3Q?)H%+&> zl+RP202*R}IwB8=U4z8#LSoNAVlP8tZ$V-oLSjEhVt+`qlaN%94#pLW_~u8>R~`u(zHbvA~{(iCb}c)B<~}>3>X(d3cjRBL-0a zL7ujb|-?PY`$M8Io_+2D6 z2WTh)s$Ld}tu_7aB71Aq93-I%Bz7+nd)9Q{#rDDVY@ki!P?MyQ*cwP|8zi;|5<44- zU4g`ILt;-sVlP5sZ-B5N*>WF*1CD?*NbFlk>=#JvZ%Aww(BK->142k_1thi}659re z?WKlPGe#guq#?0Okk}KD*z=IsYmnHxkk}`X*w>KQPhf12|3ASvApff)Iz@a)Y|xxH zEKg}6iCZAC-H_NJNbDpeb^#I_batO2%+MYriCIYO71KSfjg{*!AqhP|VuMfHgNFVe zBysQwdr)x+(3x~lwi*)K1c~j0#124W$3fVjU}9hZpPmObs0tzh3NnTcB(^+g{sF4S z5{Vs##7;zF=OVEyk=U(B?1`F4$z(2)#7ZRgRwVX8BsOSd1{TOSk;I=Ou|FcQ|01zD zK}W-ZJOlDSXkReQAVru2Xe1wrZHdHoMPh>{jbVCYk;F5R*riD9MkIEx7U+B_kSiD% z7-k|#EJb2(L}KqnVxL4}UqxcSLSlbMVsn8`af8|=hG5q-C?PludPr<5B(^&e`vDUB z8Hf!%yz&)jHW|wP3KEA}_8-Jn11Bd27SKs-P;ns;n-vuP3=9m?U=Bo)782VW#D;3H z1F=CAU0Gy7sQ6@EvrZ3^nlpV^OvR~vF9PN zSAp12&6|{YVt)j&q2~Mnu|aDHK=y%-po6lxK_|O`)PT~u7>EP4ObNsWNr1{45F0cRz`(#@ z2+|B?+knKOYTQ9=s9qls8>%K0iJb*vL)908*r1721_p*w&{=lEP);XE0%}knhz->+ z6U2s!&jYcc;%kuD+d*uonmr&k)Xbwu>>EhzCm=S&oO*`$AP#7Phk=3NGsu@v_CJs~ zL=gig=#)381$-bjRE;_k+W?8}2x3F^`heJwQ459u=#g@u*a!!SYk|U_fq@|j#1RGw zGcbS-zY~VCK?mM3LfKVFYT7_-s09;2Y|xw*0|UcUkOffo0+2XV&1w)E>VXX)HdK7S zEE4Awhz*)NWME)82Qo->I^Q~banSvjAeX%aNkjF0M`E*rj+BFn3nQ`RKy0X;${;q> zXdNWB6Nn8hX}poxAxP}{bPxxsxf+SR1jL3~yc)z7138m{VZ9*(gD{kR3?vR!a|MYF zIxG)XM}9yO{|{nA_40!bhSOrO2Ae7c;)sKp4052e=Adj%kT}!=6A&BfV@nWQYr2_> zv0QyThz%7_0kNU#^FeH=cnOFNHM16p4L%1C8bWhG;!yTdB=%|$8>)8;68jX0%?|Ad zUWRbMJ^&wu2Q}ysNF1v9H4^(Thz(W4X3W6A2xaplvBf}asAptBZ0NC^priAIp==9d zr1li(+A~I|kHKf;K^4U!X$GHx2eqsQBo1YRZf%1(q8lU*)jJQwhB{&;h%E{BBg0x_ z1_oge8_Q}VEr<=(I|;;w znm-rB2HoujIv!`C2?K*Lgu}1~Bmq^l8^nf+A3}JP9NYwKyHbhB~we#D|xlLwZ5CCzYmWhGbPz_S%3=G1c>sdiZ zU4z7-Y79VZs2T?(b_fzX7KxoUed4WbanA}Qp++Qj7ZQ6i5_<&_dm|Ei*YvZuvc>D~ zfrOymd;(&F4v}MEV0Zy?HI)4sBo0->V8Ot^2o>i02qKsaDOT}EPGM`GWbeh}o|mqVsA!b??z(pM`9mG zVxLB0Uq)hIM`GWHupt%1V+aTAzt>3Y_ekvTNbKK8Y-TG&tg|Dr`H|SdNNi~&w!9V6 zWR*ISg!cB8JMEb@8AYbAePr*?s5AX9h?1G^``8|I{_I>3z>;CF{(^I`_$f_(O|mlGkbqVo9VeA%47Oo5H)8y?{j;9 zMuq9IAS!11S`f8l`rqgF{!DMSO!s?X@5fj(eeMf;f2KQIr@wn)@5l6F>vX%9_I^xX zwodPRY469lV*1^e_Q#oSY@5F9m3ALUj z{TV%`*Mg`M)6asai0QH)K+ZcjJ@12k8DqlqryuP78JA2q{b=vcIAwY(h*~rKDu_BV zUGuXM1JF{^_=#?bTVA`74p;mgs10xu@_+UnO^(FUY$)fm4V^2*7Q|h?3EZLrcb=BDn9+m z7kdHL;0d4=vIi{~g{Sj;wHILQo-X^~y!U_G*mY({sPttMf|8Gcs^+F)-9J zFfdd>PSp*b&A_l}dgFuu6`sWm3<(?z40Q|)4DOIabu*^(ezS)ks=KgBT7t#g$kbqZ zEb#L3gYKL=l7_A zmM*f`2!LGp8e~M~bUz&jLkH091uQ2XfJC@&2!WOrg4k@_i!>P+SWfkWj*w*Fy~@DA zFb}i`1++HBpYbQw2Jf2-pl&8RS)Q`bRS^0ONFklp_v1?E!V zLw3Pzr|Gu34$h1%(;Iai^cgv)Z`5^&v*a^jU|o72| zh|QA$AF?Yb2RdZ;9TNis7aN2loRN1_ln*8qj_>?p}Qc z1`f4JpiM5^|3T_CHnB1=h;W1Mhvv}Q%gVqY!Mz+Lu5*HwfkB4*2q<=R@3HzaFeq@p zmSJGv&<7c+!u?pDfq}yS#Ma;j4U%yfg4jCT_f;7fIE+AS1MYrV1_lme5Zi=X#f*W0 z!vw^(;8vQRpzokxucX1iz+nXv^5K3e$H2g04PpmyhYK+J^`JOBmqhq4BQf? z3=Eu-pp?VJ{RVU-o)k!&g*#??uz|zIdeDYUF7?Mu3=HB1EDQ_^T)M?<3=G_F#26U3 z^gv7oZZFWePWm7=3wJB%P-g?sSv4Hoxu7G940S=XKx_eS(0U#&V{y>& z$KbTeWddSLaCe%1}^hotPBiXJX|)Qdy~1F zO&J)tAV(f^&sJk#;DQ`^%ndr}g3BIc2nPd8rx^nSmjmc7W|rN;3=G^|jEoEnqM*TS z1|Gu*b_ND9&?YSgu}V<$T6!q#9o4S(~D&@GcX8<1sXFj2#UE) zk2Z3URo@NTzL=N?I&>D~o;r301_4m+bYNh40onuE1QKP5nm*siK~x5G83#|#D$uF7 zyVw~RI6-op7eRYjSlFgtFme#DUjQ0S6x%1rz`!VWOBm#ZZvr4M#DfY3vDca)FWl5+ zU|7HUoo- z*mQLU234_CUIqp=v0ym{26Zt^)JO$wy0&Ek8OA6)AG8bF4$NT^4h3xvwP&(m zWME(x7M{M!#6is#bjUbQ09b*L0#6td=m1w?P$!uuoC%Z~8H7RCY4AiatppwZ3~^K> z*c}|g=F@pi9VDIpfj0WafQ{f423;7(6UzkJwZtdf2ihnb2R2hc_^A#915Z5Ib_rom zkW&(wu7eJG7IvJTVd|h(4_Yh3lL|IRmVp10w_f zLD1^=MkaP{1_n76MxIutGPs5|CP?ss4_Ii22H!+bGf>f$;Ft$G1rJPsvkw~!$hSfqJg1mIcW?_gfX+!c4R#QN z@D2Q97TImfhwn}I=ynddi?5D(02e;{6~hZyx2syh*st^R={ zl8J%;1Ss$SXL<;7+%+Qx1|AM(Py*xE1Z@ZBWCnRvNP=h7%KKZV<BqHgLGRme+22~;jv-P zforyfY6kn<4(bljrA0jUV9gwmfOY_LI2rhlnKCf&I5OAk@iH*TNboo_gHCjl1-ruq zY?Q1nC^5T&16TGOC`Y@2y)7#W3JZ6zyJbNe7vgqlDRuFMKL$q6i80#+~0&%h7bqspVh+5oD{r%vBs=^#@726O;|8S6qm1_rR= z{h<0A6vN<}078J|?NAQ$k1_M7koLD;K69?5~QZ9rC+g4se`JQb`~{0t1j z;Ote&3M!o#gi{Sb*_ZV+=p;wsOQ8ELd8%0-gKjMlJ_tHxtA_PD$aTW0pyM5CSwRIM zCjHsPC~W0QJVLFE#sFsP-&)5{7f_k4tBf=c*4unPl(c|eCX z^n)!46n+6J%O-$1LBf)t^Cl*O9TqGMI_8pR5||Uhz(3QNp`L+fGV26>1_mK7o@uP0 znjR8d(~;dW1KBMzA#P#d?*s+cELLd&1_q%3p1G{k;2xQWta(1N<^>SV!p5L-cpn@-P68dwb_?uJS+ILl#fq~}@ z>v~Y9;^g%Ewhof@Pe4MSS+9bG9)R?KBbOhv5Q2w|4WyU94s_s)AcS23YCVX7*+OhQ z>TIB6Q6ZUMgAJ7V8H6u^DtS$?3PwoY*JAqtx*0_H2q?>FgJqb7e}M{99k%*6pl+ye zIH=0gWdm_o8Tea3)tnw1i!cL&5DSkH+cIHLURGvc;4ud4W)S`i3J?=8hfx@`w2sG= z4OFHu39mL|VBj$WbC?+ z9r-L=3yN+#Hc+K10kOm$Y>AYxAgD5R0CS`n_|0`e6$jfUkP9VvT-ZQs{Do(Lni#HZ zpkjnUSOrvAxPdKUftchD)-1xn5874Cs{qa=8O+0KE^It9BU1mX^eNugkqpza6* zYi5JEus$4YBRd1X1t@kR*d~CC66c9x;}&IL5CI+e%o7b(!XW$;ln!Fp`awrN3qJt0 zlVaIGrN1Bpza^-}9LIJ`gn>auh9`k7R+NE37IdB_Pa-(XWiNv2ha@&oILW$!!YLVS zfoy#*sK`nI2Z5{%NKq=-6Ab*9K?P76o46 zz!IRdhd_4n_k-M+&6X+3z#zlHlgsuL0$%z zhmiFLWsGjHLGr0Z3_Lwx)eQV=K*tvKvPFn7Fz|bTnx2!`K>H*(7J?iE%C(#z76Tg# z$P^(3o|$Z*Ge(79f=awuU^as==(P8Gp4n{jpo3L~mw*bQIc%z+K?dOqphA2un>MJW zC0q=OiFs^>;tUJ|!bd>O_W5k)paWoquY+8-h|N|UbW+PLPy$-Q20DZebO`KoUeL%E zXuB30iz}#Ezydmpo{i-s=r$mh7%=%!6nx|}XtxKy3Me+0u`L&4V33CNx3{qMiZd{X zMT1tFiGjCtiGi+tXA%QlC&(-YIwyriOphPbTUB8LS6VWlvS%+iee;8k@Z&iSW(#rg zTxRT3T+Iox0#fR-R7){1@EU_6g{1;? za*hX>2|Bo!H`D~o2Hm*An+9SE3Gh}hegPem%K|!MuM*rdWe^5k^u${Q<}eE1n7+{2 z!GSS$`XgrtwR%O+A$QGSDL!FWeFg^J7BGjOfq#-F0|Rd>qn`vQCO{5iV*wRTydaBY zBpD!M2#gH;e4rk@B)Cz`-y_Gs!0X9uBFVrY1u9WJK=&Mgy#*o|xODh38YMx)IiO9h znLLc3B@Wz=H5nNAvOo%0xL<>gvdM0oKF`HL%mOrY2_C7CV_<0q-R6=DGLP#9U;Rta ziNWi+7#R2(KrUn82AxyL*9c-WajQ;$&(|-0UAx<0iEm2 z*XaxjCGG&wY1!SNGD(Cx#(;r=uLtBiQEt#2JYO$}Eylecbj45KY0!ui_kPgPKmAG) z3=DGI#vt|tkT2!AK}}D-iS=v@3<})eSs57kCNqN1b>`Lu9lI|!<)Hm_*Sk3 z9l{H`^MP*_$mew8^mT~U^xXk z)@kn%ka2FHgO<*K0+I!EKNa6)Fp~vz&BOE{cL&k>A{hn-;Z#u2voeC%48mLF7#R52 z7{LinSXGRHfsY-W<~fAxK}m)K%mJO@3c7r*beV_<>G((qo)n?%}{!?+b7u^Y1D)Bd5MT;A-HK6D26Se#!cS1f@n+VG4|+O?NrDE`_ya*Hj)nW2Ap-+{5GYdFxKB_2;OQWq2|B8Z zKMW+z!Kk#5je&tb9K_*bR01t7zUO&J*YBS8l9F)HOVF);8)fl{a%qY`NF zn?D-FQD;;FB`E$_P2l01d3@ zGAfx*U*hGU#wa-bw3mZi{TX>^$;<>UBG?&NIy4y=_$xtvRjgp-Z?OiQvb{!^fq}mj z#AM)hHeq1kZ*x>+U|`{10ScfFP$CoHUJugORnG>R)BtTZ=I;iHn{eL%sqY1eTX4&R z`WJm5@d)lRB?bom`UxP37;ar<1_u6#Ac-38SP=#W{>dQm2JXY4-sBXJ_yX?xAoetn z_!9139R>#e=^*hV-0YyhoCOj;!L1AmvDqN;7u@T47#R5Hfd z*;~L}#L2+G{~W|FWMEkW3fh-_im=%S{x^RW85qR8K^NkQaf8kj5PQH6x~qX@o-_jk z|3^@|QWW9m{|wsh#O-Lrz`*|n6jBV_^FhY`1O+Y&H>kp$9^>o4!3(Nx`Tu~DxEi?;@%kJC1_u8BAR!&$tDx9qU<7gWgf&5FjSC+J{j1#vY727W0<4$zP@JHNu( z>3x0<()FNK_WW{S5Ag9T>;|cUl=1xh3iDJM82A;z1+W0W!hcW-*8=kd`4zr_@{Kl_ zC&aG+I=q%&2W$%X3};Ys;k~TLzyLa-7M!l+8Th$CJ~d$E0Of)zIR*xPN5;h(LJSN- z4*ZK5LC2#COMqINOTgY|5S|5^CRz&Sun6l+5Ab&|u9pN20IUNm78E`P;;aXA)FBOy zdKGAyBFexIxOs5Do!ZupP`15MBRG0Njt}-vkW z47g{@e-O-x6*dN?*+XDXobVh_S~?8o#DhE5{71naP7rpLU|`@s2IizN@XLY1>^LKT zw+aJ;Py_!-#>c9lajNMP0vsewyFih4h7r_4Vh49v`Okt=Cx%Lp2f5EqsLg~vT`KuIw0`|~j{@IPP-2c?0nAg!;#TIDPl z`9CtgQfFWgt_O|Pe*&`^g!w>`@tN_1I%pK$0#x!s&u|uA0!sT|!9L*;-Ujm4H^y)3 zpib8FdT|B@{_o%*lL5~O@&5pGH{-0oPD1hgL_g~4^35O@+|`qw}QerYRE z;3|Trb*2l0rr7z_z?>Pv(bMIF9MtOnf(+IIi_H@$&NX4+Hv?;*4;~TaH)jGBwF`tn z1E>5JOrWB6q3}vj`C$pxvq)GJ6z5i8&SK&Jpxkc{cIFb{SThC&eh08=%Y;F5R{V}k zpgF7M!i*p{JAw2}KN931P!HPD!tcfOUX_7il?dplXMSHMP%2oX06NEx-;W8@Le*hZ z$kSqA;12_vXu_x<2XcB8m;`_rVSdj%6AQ3 zzl;fV`Hk>74h9DPi>W&{ig=1Xqf~wVSRD_)l7Ao3=Cq4pshJ#ZJ?E1 zV!x$8Gsk;WKr_cTKz9g;i3))F;^lhazW8QP6X*!oe{w1+{GXZ5>M$^ffKGnq{{jv| z2I1+TD*Pu{B1~a9sIl^kiK%h=(+~%x`bVIg@{dUibhH$U!V(bgKhs?u1_lon1xC>1 z3JddN9R>y;76m>~qk@(BvkvIwX9dt&Tz)oiU-l1+0xKv5vx9kmSriyRPU2w>2OSZ~ zs_=)4fq`F$8Pw9OU{g2+s_;a>vsED+3JdB%aVW|RD$T+;6hOm*{9<6qI1UBSP$0iJ z*w6$Hg+`DS63n1JdlH92C#abTnLaDxP}mESlLhN5;ZXPm;wdwOO8yECWzfmb{QAtE z;-HhC6|6yR0wZQ-T?U3V;tK0zKz9Y0FiYx!PJUJZUA)b2$_%Q)cZe%=gPdl@3~FuM z5LcK0(r6Cm-4R!C24x`&FzE3R-H)MD~v1~rrZi7PAzMT{5NgDesX zpt~pQ`MtrxrXryb2r6iOz#7#g6t;s}Grr97x(o~&5(>klaE9?N3@9|+^ z?k{Bp&_pDEIGFcaS>XdH4kN%}@kd#q2~@U6f_Z8@ zqoR-r%DypR96(P;mwd6|h=%240XLC?ueKHWrZ6EqFnFs8E;@ zEDZe8p!RAKbC)IqgUT<^mi@($F)RkqHEy7@b!Y1`FsOP?Umf8fFSbmCfq`)c7pRR0 zTCE0JH^ew6YWjl+2W{ObJq89=@PUCEpcKxy7p&|ZBLjm5=vXzzeO#dQ8^pxGpz(u$ zx<#aeBA0qF1A`XmNIs+K6KfsBrt2?L;j?6r1T7|0`3Txs>cAEO-8_*4KK=0?=v-N0 z(8gEDxV$Vg1B2>J&>^6XZ1<)gh;)#s{~^J^!05uZ6|{n4Vt|GrXmf=t8))3%Ei(gy zRxASpgKaPagEnInqoFn<=%7cLuZ0K0|Vn`(AXpNSX%*o1_s@ypnc|BSwU<~ z(CDydFat;jC{ODh0i92<5aveEsr{ymbJz?S81%1!4q93W3MelY1_u2}pksExT+q;} zKB#DC1anuhFfbV0p57DXpu>22`pzf^ZTs&aC$9jR!Za}$bSNVO<4RB#KEletV4w&( z&R`XYE6c{fpb6T)018E8kUFDa1_lX(>4`pqqSGy+9fVCof*BZ$-53}c;)59&Obx)k zW-4M}&;*?^36j(V)e>O++ZY%aK>9nO`lm)asIz7VGcYWgelXfWq#ncsoyrOeH%Lq~ z7)ODQEDmO1xB)f2gaH(&#S9F_pjBSY!3+#7?dd? zr?(m#Gcc%L0Og^@j0}(-O7|awwsSv_v3)*%=sA+d-!XTmbXGfcW6EU@m|=a-tjz3>u(?JdBsX zA?(Nj%SM+O!PyA3M+s!JG3ZQTkcZzHgVQEBN3u@O@e$;j7Vn_Q5AwS483qQ1>%j~R z;wIA*lO048wLtT1@p>Q)(M(0)YrjCfI@61wgJaZ~U{MM=)peZ-%xVoLkkt@pX@XV7 zb1*Q#1Hl+{b~nf=vrQn;tM@pIx1IsC=#l~C49yq@28IWqtZ(8DS_l{lHUbphW#FSu zpPMo;sCt2lgHUiIt&4+!K^2_qA$$o=1_o7dwukWjIT;u;wm46HvM__F!OOcpc2ZkYNf64DhMUn$-*p3?NC( z`Ji*nLHQqa0{}?-9*Fi62@dMH--8(#u0eIdbF7vnBLf2{$7(Z1F_khfFqr0ovfoCq ze?UHkq^w{wSjyVS1WH+;MPiVY1>s{)Sr(w1m9!b-pydXGsVS&Mc@}OqXhAjOoP}mc zQG%Q<4CLc7#LK+$=jA0 zH2V7(#5d4nU|_Uk29399al_o>zzj-#DcrC$=g167bBHtsIzbu~6&E1x`Hk%0jmCM%#yPe7D1F=8383U^2V#Hh=tgn=Q|3Y6iZ87;NJXQYE}6JSUH`OJxd zfguOvGjm^%&wRmc3D6#T#yJ*zpwoBaz#@>0bfDgffx(gi%s>m^82ed44IRcHNOqVAZnQxB zJc$()b~2zfv!I}z%*w;aFx@N7fh)K?1mu}0rV=ht&0WL*@{<_@gDGg+G2?!Cuz)IB z#yPFl3=FDZtM;>itV-jBrGtaubf5+5XkD7VJk3F_-rt6SL7fA1Y9a$GXsIUi#0#|$ zhcSX3rVd(C%g6-wI@81u4IR)ye9U0(TwVqSb#M*B0$$w1G%*wuec-UQ0#zDJMGTBK z5O+@uVbBDnC{Vatb%JiUC}NPaVPKfxT_@RW2fr0T1>-p(>(j6pO zL1B4t`mJ;aDPvHT1u95OSWtsC6%?QE!Lb3d2DCeZagLKM$eQWu84hyw;H3Tutbm!H zfk8_KbRIa4IJyW5vQ&7=hn(+!2y7TAPo#q5NQ|F>K^<&r7B~YjMj=WhP*{Qro{hHP zz+^Pko}TF=$UFUFhJ&yM$nzjCfG*lFoeVmum6HvWia_oz1cla|#dctK^JF^6g@bM2 z0V~)5T8{kz)L`HR^Uv`!FsS91Ffj6gS7CrAQH(*SfH#FOFnHR5ZDs-`yl6%PZN?ZT zjuHlNdlnRg8Pgjx9i&)6D%+>x*03NSE0lKyKje+GyT+L6Hc2FyP$z`&rZ3(ER$*;PUJJ%F};cZV=AnA$@e z1abu^KtZkuot~TJAk7M5mQL@5F{e&no8=&_0_qTef~lN=fx-HRECT~0KWNN^0kpJ| zan5!J1_ss2>2IU%*BPMl(noeG#Zo znF>v!nhRic`&tGD22jvzUVv5dAE3?mYzIiG+mh`d1!*9=Kuh#R5Sgj6qI}aYWIM3d zuY;s1aGMKsqPfm~&{2c8*+8*-4jj9y9T^x@!QG$RY#>*v3oRLGdYIEBH7fniq&1A{qO zEQSfxW2jz^xK+3}uSs54@+t@&{n=Qn^pb5%b z;3_u)8aaW}A3n+wo1UHPAQ_YB1P&fh=f`*<)ZZl#F-9u}P0&CJsNOaH2$h?FkmF@! zU;w2m1`8!nj8%dY8>l15IOm%a1A|%R^ar^P@`<2GxDVB33ModQ;Q+~Npde>3JpyXX zPU3)7ejC6M&*j3vpxOfJNKfJb1xK9_1A{8KE}g^ys!C0T85mTzOi##jP%#5}moW^I zn5Tjhvj!+XF;3$Eby7hqn877CsM%!<>gZeuVPII|JY7EDLBhuvbX_YbQ|)yIg$AfI z4yk>NL9K02O?wR@!Dt047fKlzj6pqDkP)xI65uwkRu=j-6`$)|K<OZJp+SJD%fYXWN6 zHGn+6d4nzvz0k0 z%2xU?FsQPC8YUmWLE|LBz+eV;!UwK-(_P9OR2e;|XO%e^vhsK`F!WAeQ0AZj$r_+L zc0kd3#2XT=Ps$vGr9eKo;SF(Ku>gZHs2c~;_}6>7V7Y^QJ!t4u%m*T03K|$=G+{6X z?feC4)PhQYG=l1JkVb!~7^E@e04nq*252+JGEEF*Fa~YE1eurtRRr$1GdeJ6fhvEH ziJ(SEu>b>u#dXlV4&v<7*OxnRsl@q1a)&rOC^0lif&EkJxG&{&Z?J7~FEzBH^u zpui4lGiZS3{uve7K^^CrAhqVxD=Hl11ws4R7*)Vd_yH1LJAFlkgPav;{SKo#JE(}W zkYQlZ_ykH08eo_E$S^Q~?f_zV=*z&MmYJ2!z-R%gX&6Aa(rRc=t8|cH7c0$ zDu7k|z~Rn3aYH?W=3Q6`3<@exG)7O~Sm_`(y}HstSQ*q$DL_^Yy1^QpmmQ&Pr*$CJ z29RE>K1RE&X7ev)vz-)tI?JSxsCPoYl5e zffM$%DhE|1sQ{P~8L$#>Sq28@0tQAIE|3gkuvyl0*=h%A2?3DV^5Cr93hK?Wfh$DQ z4buav9Yh%Wr>9ms81dJE2G~8o8H6!Zb@%jT)ea$gprIbdQ1v&Q3=E8ZU^^H?)k{DH zr9W4H5Ca4A#Etcipm7LL=9ZhTQRAQq&P1-$!)hFqAejhM-GjoeIS`VG=G4Gish|N^ zkjz1-%q_UgK4{VW11cj?>mUpn|CBZ5$htN0NNtYbZYv$S_iTE2SKnY4M|X|(P*_Q z0|TSkH&jtxP-5i{hMKL*;Hm=}Wo-oAEfQt&AS(85lsAcO{GaQY8ik5Ed|Se`CzR0Kx+D z?v2I_3?MA9-=kHUfdPd1LK!`n%orFzm|v2`Bglk-0fYsr7~S*u85lsAtI2(z5HkbA zzU_7m4!c6Ycl%6Vt7)&ZJ@Bf-PL}QBw;b*TG8vg}|E}$Lfsfh9lwtY?IY;U3Ppuq{ zQzU1AmUDr!1L){2B=)Z9hVvb*Z9x;&j8JJo(0wpawj2^$2Z;^7QU?SX z)6dR#6z5%sq-yu{kMkYH8Lv&Z?Wz%H{4rf|fup#gFzDtNs8)F-wl)&m0g3H9J#&Gh zyW|`sp^ZrFebY}aa8&kuh9vYGiOm73NuaigBC(Z`*cM1^*XgDU9hK{Ik%XF%*nLQB z@Rc-Bqn9CxZ$e`4M`E8wV!uFQ%Yd2(P;=ZM>}XI~%uov9fZ5ZK*awihxVlSV*b&+GdqyT8L5vp4i ziET7pcd?_mq%V?C5)wOqdhB9HWya~#8y7o@d+tDzIf}%-jKqF{#O48woj@&BL}Ker ze+aVF6G>EhzCrIoMNbEmIY!1+{D%5o%NNfcN z8*)&R4uk`aQ41ut3lbYVtOYeF7D*g@xg=D436l6JB=$oj_FE+OPa#mV2CA74G(rkx zOHcP)>S!$qzO4o-RD>j5KYi{}M`g+7NJ1x(*w?1tT7}TYJnxufl)dnD2 zjw_OQAQC$ciCqlZUj)<8fFv;miMpVphBhSjMkMyW=?j-T2G@HbC52=pb|w-Ve9H{fo>C-n@QpK2@kS(Z@a;2D@jfK+ zSxD@Y5H@Jsh=Ji6gagh9kCE6Pr%znrC~m6^8VZ7%r-#J0L}I%ju_KV!snegXaBQys ziXyg;q(x8*@p^6qF zN$f&mpG9KdL}EWhVt+(p|3hMPf@c1q=8GV)Qt@Bk<*(b*v+7`&(dUG1nW37%|% zn$d?OJ$t(48b@Wu!_#BeIEwQ=MUwe6y>X4Bb-f8_z#pp735gwm#EwH^=OD4Gkk}na z>}g1B@Vz!r^EV-hgAS8`C+u@b5_gc;uaMZ_nF**tY@mq8%v2&5w z6XifRA3+V8izESB7zYdOtw`brk=SRE*f){b&!+RPbKGBlRvuAGJVau@MPmO%VzYu4 zuR)z6h{TpfVrwF?O_A7+NNisS88I8^#??oFR+K3Yz4c`*5S&{{aCow-QtY9w|i5*xH*5~g=4lK5sM_CX}}GbHvW2pe+zJUeK> z6l$@^^xjR5;=I;KLLSpMZgNzXY(NrPgv4Gy{p}`4YreloLR_lT%{Dt)N&0{W7@!6x zBC+$PcW!pfR(*mb^Z|*@23n#B)h0Y$a*N|{UPI6rE>y^Fy5d&H?CCSMI`SBvLlVD( z#AXMtR{%#VgA5W|bNb1xj@GK#NJ8aE>>ecc%;}oj9E0mwL36NBo28K0>PT#BBz6cA zI|_-NfW%HiV&@>Si;&nA5H=*q)*ii8<5F08!1;mDm zgKwmPiZ2FTVFODb+dzt-5=W5O=Rj9RLxxw8!G+?#D<2%Ya}*ki3==!aDnEl zplL`L!LDbJ1aY96m5|tGNNjr~wg(bB4#b8UnvTRSKw@`+*iiEqBe8da*sh@PXJBC1 z58^---9%!)MPh$LV#|VN^PnN20b)ZMDGZ?NVT7S^cw|s=ghGJpqXgzFG!qG3YuO*d08ZL08K_@8j7AQt!*aFn!HF zM^0EF1lqk1Q+yqy0IK*chz)hvHzf9dBsME(mL95}4~Z>~#MTC}p$;Cb|r`d)ldgwLp5}Q z*ii945F08!6U2s!gRiE6imw8RLmjjkiG32phI;Z668kpz-W;gJdyoWF^A9Ap1ZZsy zR9qj#hFWF?VuMb+0j+ZZUH$@PgKw9CstE&}4Yh0+hz;7H!oa|=59Bx~`y@yls^$vl-W*tb+(eRi z0%Aj5`Vz#3YWMfBmv=L$VnIgD{kxha_HKj>G|-QVpxVK$F)n_H2+EsKtvwY^VimL2PM=UpIm*fU@_1 z#Gz`ym(@UH^bC^t4G>!z+8hGiR>KI@{2e3#wTuCDT?>@WiNxjyv7zcEkl2byY%L_V z35X4KkUfYETJOxjz~F2SY7Rj;ejo{`qDT-M>gqTU8!Da&VnfCAKy0XZC5R0buLH56 z;+-HiRJ;$whKkPuu|f8N3ev?e4g&+jP7s@Yy418Zx%!JBHb@Zz1H&yO_6HCf8Y(}L z*i4{{RiNS=AU0I50uoyjiS3ER4nksQfY`8$$iSD?Kn<;eNPr`}0mOz{(22yJgv18l zQUg`95hM;ZXBQG1eCrHU{3J*ms{WD%XgC|nc>$7uD*A}T{)NP509`NwRWAr)LxWld z#0D)xVPIfTutZ!yr415?sxb$#p=umpY*2w32I4?1jz?l=AhGj6Y^dgPBz6N5y9>mI zS~eBLhD?bt%mg_I%3cQ&ho%+K^)2T?t}CjcWk0LHjsBH5JG>D7zaZ4plP=#0IVO0rfILYM|_eAaSUg`gI@2w-4f@U>=O5QefNK;lp}$sjh=%nT44DqaF& zL)EuggE9$Jq8B6q+TFy!z%UVHD3m=1Bo0-x28q1`iG3W2eF?;dT6`VEhU$F=VnfY* z4`YM2Iy2cYFu<+}17-gJi9^*e+cGe~%JX_5B#t9SahNs>uMcq2}a**ii9m5L**k zMYcdV;Lw=`Vna)%#YpTmNbF4@Hq^4iAU4#{b09Y4UN44AAO}I&cR}J%H7`JHsDr-S zf|3}N^9LjWRm5(G2qGR38!9diVnfxdA+fbVY^Y^kNbF1`b_WuB35X3c6O_ePgE-n? z&oivIV_*=5vX6kop_W}nV&4FHQz9frg%Lt;-uVlM}=p%$zIu|eD37#J8f*)uQ*L)m*l;t)0U3@1Pw zs3XpT*boVZ8z44R{4R(M6@QJy{tjY84drrRU|@u@g^}1YNNiOkwjP)b3V#L$26He6 z5(T~>HZ%c-A+h6;*f}6J)Ur|}b~lI()jI`=Jr{|+7{rF^-BAzXKz+6!#MXs4;;;h) z1L&*@5bqpF9IECfhz$*umq_e)AU0IZPY@fb<{yX+HB-=$fq@aqR)Mm?naBdl0a@ma z#127XXHL&O?NGJt_$uOkD4FqC}}Bo1}UH4q!B{vn7B6@La| zL&d)$u^F5Y>6R75hAoW|0CAw2ML}$+WpYSt6A&936ShcfHzalthz-@7gv2gIV%H(D zCpv+O3#f+KAPK0e7lGK&KGHHL1_scO7$__@g2bU}_9L;+g4j^?50Kd3L2RgcCT9i) zM$pc6&|w+Q3=E+AjKRgFAV>nLNCw1)hJ+%B4Hee`v7zFIAU0Io2E>MnJA&9yaepLs zED}2tiCyB1R9sYoB%rQqLSipPV(&v@Uq@oUMq+cjfLj`%z+w;su|X#|FfcGkxiByY zL)oezafn0f84N%is1Hm*Y={JdGZH%xi5&xCL)GUXu?s>y87L^6Ky0YTJV9*G=6+Cf zD#4Y3K^V$O21!7DR*b~10I{K(n?Y=-nhp>fDn1Q~y$p%HX?oygNAdd8AR(x>3m`UB z+iegVD*gb(hC1aX68k@h4fQvN8{(Q;K_s>~hz-@NfW$Tfv0sS&yXXD2NU9**PTk zbtLv(5F4uZ7ZO{>oq>T7DsBd1LmgoYVw-~f$l&PCz#t4_gHl;2NCFzvQ6M%{Lk1GN z9K;4`U|?WqKw@_yvFC%>P)DyoVsAuZ?*p-+=A3p1<#MQH*FX}WE%KmFI>>cU_EV5J zRLutv8|u)nAU0IZKO{E02WZ(p#Fw%lHq=3CNNjxs+nm7^#DN;*hs2Htv7r`cf!O8{ zL-RZs7=+EI^Ib!KW`L}UP75F2W!1c+?`al4Es1A{P>tqu~0sxbnwp%$Bi*idmN5F0A) z4q`*aLm_NX;$dJ&hH$_(SAZww3!??66-vVS5eV(~&$?3^GrRI@k|TM5L5Izk=9hMHpoVnfxt zgV@$!KQefGF)#>&*wYnnIEujLK+-@epsGtiY>)~D28MnR8!A2x#I}K$G7Dr1l)V%r z4pp-O#D=lsQw9H>Mkhz*foXaTXI;xj;OsQ6+K8!Em6#DyJ3wsEO;>ehz%+PKr!_Q#DT`sGhaxYWq=mXg2bVkx%?2pC;(zZ)vF@0^^n*uAT~5H z`XaHzkk~QxAP&@^LL_z-5_gr6+R@kI1*a{iEWI;_CsRFgV@lZP6M&Q8#);nviunsK)qg&`KA60 z$?)aj4Io9(pl$`Rp_(TnvFCxi%r}y1O)VA+H z(om&;kl0)Si1xiGhz+$y5yXb7*8#CX2mdfIFc<_dFbG50)*x}H8aEIds@EIDhKkpR zfjCf!Xb>AJk%`1EM`AaD*iiNDAU0I}BoG@aJ{`n{if;t5q2dRS*hfKZScmj7gaZzp zhe+&?AU4!DU!gt&?eOFbM5K91B(^+=4OQ=k#P&yGr-Infq?Z>6DrljcawLfs5F2Vx zFA{q(hz(W028q2DiG2vfhUz_y#C`~3L-oFbu|Wy_GmOK)!0;2qhH7RCVqjo|vL!%l zsAfeZwiXiG0K|r>_Xn||>O(;>jhz&Y~1at!s(mHJ!1iPL=1Hoa?L1G&tvCWa#c1Ua|B(@h4+YgBy zio}jYVkdyv)7c(63f1R;+2G{IP=Lg)Kw{S*v0ISX9Z2j6NbD&{>^Vs61xV}_5H=_g zFfgovaKNtEg2di|#6Ez;K7zzPgT%go#J+*VzJtVmh{S#x49W!1D0_n>@d1hb1Bv|y ziOmv%D4#fx*!)OrVI;OR5?da|2Kiqd#$jM!&_-e#BeBhq*!DvMbR_m{B=%wmI|>}}%OM;v zdp#0+GZK3@5_>-q`xp}Y6cYR5bjBx+;<8JA4Y1yOsZ?*&l{rt_9L`7<(1j|EW))7OHi z1JnPOIr%gF@tf{f?&QZ9GktEklRx8z>2E=l&ve@gCx6C{>AfK8$n?7)%3!)~rISCS z%k)|hwPE^M5VdEzY?YHg(}SStc~wq+j55>rRyp}IYE0*?cJgQRnH~$GBBrkeQ3ccg zf~bz^zBNw%OfQ0`&#Q6rW8|6sw#LbyQDwSqt&=}v&h%aowPO0+T9D&Hrt8%?`7v&o zUR&qn&uB9JEQs1MUAErIpXox_^t^f}KSrDBd+VM284pb7ZE*5u%$OeA;N;JAC1U!z z1}8s8jp=_uq8-zH8=d?ak4&H2=;Y6ICvy6`Mkha}7m?HLnwoCx6C<>9ruLXZqP@r{jz@)2FsLl`}4w&f5xB5(}b4rmqE2G1LFHg6vG3 z?$_qz$8;fS`aBSQCVBe1HYY#E6Vq+mo%|V7ruTxVfa!NZRK#@M4kv%6H(Ar`I-L9% zJEornald3wm+N%$V=S4T+X)W;y&!7Bblxto4`V@;#q_mZAlr(k|Lbz{V|q|L-LKop zkFjR@+-|Uzx80!7EtziDhbv`l{o z;%=C3I}zf~iBA4ZU)rYMo9N`n*fL#rl9NB>Gm1?Qoa&^^3c9miW_smR zCuPP{)8|fgQfIy2%fOH|ec=-W;pum#Itef;On(a!_FT)ruwnYc4ld#8I@6p47!#)3 zPIFRc{ke{TVFyIG1|)1Uy%!|BaRUQ`Cd804AYq;9cR|9p&NDFFn$9`hNttoWblvGr z>a6eC7#S?4AGBZ;o}M$^Nq|v(dhK*4bw-2fOF`87>1U@qsq@yvF)_HvGcY`5U|@JO zy->nghEaXG+zcl*ULP|?h7G(749^%C7@DUS7IRB8{c)b2H^WJj&Ctly%+g@Gp>(AL zi;=mB$>hSz>Wm4~AI@;30p0w@!@|tM`aqO{ftiIpPn>~)7jzLeALy2Q z2Btn~1_oC31SZf0FU$-K3aq;CLHAwyfvz^t12Gu{T&K-(60i3cV_;x4{0?eP34jja zWHkb@1q5n&85mfNA2Kj7hzMBAFfg#1fY=fOpa}+6(`%rU)CDp`85mg2PBSnt$T4uR zl!5N#W&yc@NnL`0fz=!&AjrdNW6aFJAn-(mfq~T)>^K2CDFy~sI}n>iO27)_0DF*u z91KjL{Xwh_pyOni?51y+<0Kj}Uy^}=Ju#k{fq@NVQ9d&R1G@+#=+qphlOhZZ>`fq1 zrXSo44D79~%nS^?6POto_&~}Sm}V<5FtGQ`28pf)iGq~!IWvMH$9cN!Tqp5d&=n^P z!uNO>7#M|P`4||Ognf8GciV$no-D%cAb$(rm1kgJ6Fwuxz`!p2fRTZLLs&zZfq_#v z1ax(h@IwU#25#XKpi6p%%_JBYc!eJeF);86%YlyV7Y5z5Bp`fBkbyx^IBxpFxlWq( z0`d$DlEQhQiwT8q%P=rV3;&j8V2}~s#LB=RD_pO{z#u2=E6l(kFPsXBIAPE}d`026 zDhv!t!e50M7?g!~$}%vh2!EGiU{DqQ$jQK)phk39x#1TPmiC{e^RyR@AF;ACR2V-jFzVBi9s!N*?D zp9S!?wrh^2;!7r7iIndG8L5n*~OTvLH#;$mR!5ny0o*JNhlU|`^6W;bE3 zhniH+z-|gPiW`&?%)nk{x29!&DsK!S;Wb}04^Aj2v7!QU{&X1 zU|?5fT?bQnar%QrPBJD8tT#ZhqQiO@Wb-FX?F_6npgeEJ`VXd4X8OazD&cxi<;%dj z9F$jFSwXI1>5@RE(Qh;E_YDTUCRpc5NACDs~5#{ zi8CzzQ-mpiCvSqSk61M6{6=q_RfUChc_3kvu(kQiiVU(c$~ z!%z>6!VOSkvt$?;*f+BN2VI`Yz^VqS-8Zpv^Dr=QDza~7&ENs$e^4^s#tJSOxsw^# zx3e~a4iM!oVqo6^W(qQ}f==jT-^pqX(&)v$hjl4PBRH+>g<1rTiG8f~h^S!S5Ags4 zYbVI}2Utr$y1m(tu)c@uK8mdS7_#q=Lo`Fm?Gs?vc`>jWfQpfmtf0fAIN90Hu*&no zQp8z^N%dTyV-eZUfuov@fi(u?x$~@`mG(V7~%RW};T0w0{*GQKHvDsplFv%08x>p>wS zdJ&XxZ-MC12Mfrp ztV=+Z#}n4qybKJy44^AqL8Uw&C}V>O237-5+4Y8%hmV1QSBCm#c}JkVeRl?M!v z@<0=;f)P?4Xt9NY>}TTgVP{}q*9J>5bLE4|Tpcz~K2RO@3si{cf;p@VtU{nXrN@@Y z$H2hJ!fwO{I=Y2_uU=0l1DVb#q?7m=k2tcg%18Ww7ILaT) z5oTb$2#Tfvw#6WmB-n%5v;|=92!Xf*Vp1quJ;+NShcGa(hkTGD@61iY-Hcfq^@-D4T&j8mxqYtBjR_fjx%pD>$S;R~E6yvVkfDK?c^PpxhG2 zW-h?MAR@z_z_v?(fkE^jD6J%dgIu)!A}E-XzyT%N0t%>PunnS3pi(Ra90a01AT_CA zPcX1f29-%^Y$XB=44fS78EmgWUNZpYlT2_rVc=2)MQ#>Yf`x&D1!N~HC&-Q2Y{x(j z;b6~Ya}tE)>v{(EJaA%#WZ-;o=s@yg2{?U;7J!QNQZ_qg1_tr$)Jg{Sa<&hk+ZI@L zK$*6J?T-Kh18b!q0|R?4Ta+L)Zx#zOFz|u14LJLOxC|UDAWJz7*qhl_3WCFsfxV?3 z5{8ffZ3S}#xKlE+8Q9yv90dl}37{IMgAHVbhyi;S+cl8WKY`MAH`pNY)FKA<9K-p>%+dDx92Ht-l2Z2ig5Q~9>1!M}R0(<>TwlX0G2Cm(pWH}4W zX5jh;YVOWvs{wU-xo&{GIft!D2vl{?0)_Kjwhqu`^<1D5fqfoZpAaaAB!bGF`D{~! z7#KvjazHV>hz)cgqy$$I$Qeu676>sg$S`oQxNtHsaIk>dJ{&BIIO{7Y#{>bD;`t? z^%YA%tzTgSZUzQc;d&O(rGc!wK_1!*PTs69LFLPFFq@N$z5X&AsB_1in^?iXeg&Md z7`SsY^BCB#f;miF2SEklH86*T%NrCJ*TEb%u9cu9dV>vgdp8FI>r_xWxyi-^8c_fp zRmXmh4RpCUZ$0RSad0XCxtb4@-ykJ1(>0JUIE+ED!W1IIz`)@FX7){2T>3##EjJ$6P0*4N?;3>=c+wlOQ{#A*&tX3!yQVxS@ueBV0Q z-5`QNP=_<)k_ZEXfD@=z&IEabL7+r|fq^s2nK6=qfkmK7ih+SM8>EIqfD6=8&jD%F zfQ%D7g4rs^z{C&gPUM2j7ren)4;pU}cmNV=fEXIW%fP_d2x2n{teZY_os+dKuMz_T zXFEtpKq4`%fPu4PsxSkCkVG+v-MK)Rfk9Xx2vk6Ig9;%Lff7Xq2F@N(sEG>XOcz`a z8ds5JVBqWrMTVTfc^L)<&Iuq-$_o^LnphKmGchnI2>5_(o($6FAmAd&z`!{L z)Nd+a;M@puhJ*mWI0FOcCXi1-SvwSz3Rys|WSS?>z`(f~1z`$hA%)r2T1{88k z>p=l>8O&sx{(FOyr0!vH1_mzBef6BIj371x7wF_ZPBunR0%YL=-BHfT4$co8T<+5y zH#!L$tOW%yCu1wfYEDjWMqvpC1}@O}87B`TC?FWPZi8IH3+6C#U7Oyr(MeI}syG7! z>k?3E5Cy6_l-df)GrEkR4hRRM)IpHn^}swHMkzT^OzShwmSkWM zV3cA|VPN1i0=qzjQ7RbJ#V}@!6lY)%t!I=n1SND+M$jOi1fvuq$e(76pu_!C7^OgW zg>hOka)AzHXOt=hxzZZ!!xTm-a3kLi%u8jI$_JTZ&nPd!z>vl$B?e094qyw@8Kpv5 z7#KJm89|5pWiUz|0L8QuV~RKfLkZ*bOPid;>Ot%pMkzCp7u*>aN-{9iGD;l>IogY{ zN}Pe=2BTC0C^>mEf^LAn#mKd*H!EP6k$ckQ00u zwIvuBm>NMfmM&bf#C+IE(B#92L@>uMlL^gc4-C%fo}rS^ENw)NrHy8xB@{b zibbGUiGhJD2$bmA1WKpR-RvZuc~h2wfh!Co&A})m3L1e62XVL9^r68_YPy*6mlv&2az`zv;lF?+8 z;h8SG#Ys}S15~Q#g2Z$fWk7>1Tm_((w=ScMKF@Xbs zoqw_{3>0+$koy#!@wZ00W{><3Su${D1uzrHc19l6f=X)EA9ZLH~|3fy5&O8bFz;ega4$M&KWaGZ7?FBd`(Fq@N5D zZxB!dX_x{MUm#!#Vow8!FA-QK$H2ff9VC840CWi@*DR3u34zUw3=CYeLEC(sk|IVKP~VXc-)@r3CP|8aDBn`9Kc;gSB%s6f4&+J(Mi57j%VfI2b|-~;eOU$u6D~baMqp(G`Not>8Z`9A1uiD6 zxy(SJzymJYY`D@uQN{}{^c=WmgJk%?GA>*flo=Sf_`xzBT%aQ*xdgy6K3u{e7YTw( zxd1LuwaFy{E*nF*b_y~u_;QIdf;?Kn1*(C$#K4ZL-~v^_T;gC(71u>j7)UU(%QG<4 zNELx{oFwBERtAPYd{VnW<+2nbXgHUhUn+mP%nm2%`U+5%kpsJ*k6$W4ih+Sk9$c{T z^Gkuw`s7js^91;%K$SI@7MLfr9a028>p+3=FK|pj7L~$e;nL_Z+wuGcE+VqY9K_mw>&`!1Yy(fq`o& zn8U(#WBR=vPR8{jpz(@zV8w!5%^=QtFh?EIWY`F^O_YHZblD@wT%&!@)@{5w~2FY2Xh3tSV4ia1I$t2k_2&ffjI_TZ6HVO26F@)z};Z3y^Nr4 zZ~&Lm^aVSeBsD<2Y_0>~u!sToLb(otIk8+fK(TQM%!%V-p8jyBlcWlxAOi!}F|fZ< z7+76Ex%@ceUXU{zxK1*Pf)ZERbh%wllBT+#06W77YQwQ}fjW|0XThnCgX<&6jEi7% z`M7vNQE>^(;paL$J!hAbWId<@$aR+yG-@Eu)dvd6d*Bd|U|^jA8c%${2s$;9wGE{8 zHCU^p1tZr-Mj24jECHqIPhd6!7bhr`KQk&RgT^1kK!xNNMo?pigR2IVroVzc!oy_; za?v+N(A1Lv*SC65n0*H)Ng41&3fB)XM-Dtd%JmcM4F&K-3fC`2P)Vl7^&C_c{ANsL zWMI(bQUr1SfE{MZl?JNc_`uT`R$QeZCkTM2F>JW*fZQ+01geK>xxm$s5O_jCYbsX; zDD5kNdDFNOK%uM%o)wwSwH{P3sew5&xYkTxyW2^vz5rx}7FcW^cX6%>1D6?C>wNGq zCYL!AsC--i9_{3^U;>qo3%S@?7#O%L!Fm>P?E=NL6_~S_3v|Cdmp$0QOSnQ*85p=6 zz@{w&Px){;f~S0zb1eY5-U+0qo?!)-JSbk=K|F?)T$e%F!HY>zk%3_qcT!F&1D7uo zC~2&bQUk?@ACsRr1A`8u6c;Gtg@Fw>VU(H(ii9XI&lFT(gYp9hi!x|}5L6CZfX0hJ znURTsH31ZPF-*FkR$VBUO*+#YP|SmdfVnc6KnM6TaH)YJF&pe4M=nPYCkJe_6W1J2 zg34v;Wn^G*=2|eFcdwJ8zl$;h18Y1;RV7#zrxDi-CN)rG>4RcoCYa5@^%kUJ789tG zDaW-NWX^1GIB9U{gDUB{V2&2o;pw$|oh0kQWzIsT70L_@23%^Otg#5}9zzCjH`Po9 zIyJ_`z}f~XQ5G|80X3vJxRx=cfvlbYnjc#ZW;1Y20L9k|u;W1EAd#S+X)h>?tz>cn z&HjRB(YcO*wQj2_1z!~|1q_*GcdTZNX3A7|Cz3SJW>AMZi9;$7lyD)_ zT}2#Hpwp_kWWoAMIHazFR4Oxr3h@dK*~EfO1}=T(WkL)LJ>pV5pbFcF`L8+y!y0iZ zPmy2-1}+n3VGRa`E#gxApoD13461&2h)ewjr8P5VP!hZ$E_Di|(HzXXBQ7-ol8W&Qc{*6mHy12V)BKu)H9Gb1DGu}7#Q9t zOM%W`<_cm4wF^EdOG$uIYcMmYZ2P7xb)X&;2BBapekx170p;~DFz=VL6lkW8D;&)G ztt@pG6zCCPfBsRHN(E*2NHFiOvXmPr45FApof!rdDbT&-T+v`T9u=u0ATPy$dAur8 zKR`Cbf>jErNNI7@Gca%^FxzV|FvzGduz{M>pri?J#Hn*KFtCBL6DUzaMcHyx7#KkD z3*+-@Fff2Hm=7vnE`rCdK*b6hsHg#j5m=6$fej=G3KuA!qn_nHF9QR(f8wtJ&9y8H ztTRC6R}yoJ3Il_jJ1cDaDrm09<)hTQImmTD?|sQ34@{;14BK7E@i8%tt*3@xV3arWQ-`jXRr zrs)O`-J+*&SZQQBJ!Xft;`BGV_MF>`IL)UpPVdjCP@fiL$U5DZ+uU?}+6^Z+1;*Ox zzG6w@jPs`-{o!Pt_z-jzD(L!01_p+2NNi@%ZB$TkK_s>;659ib9g4&T4Nx*d^%hJ| z{OKev*?}ZI7m2-U`oy13?vg)|g!niZ7+|`kr+@tEq%7%-Bou+fPMxm%%Sl|a0ZC{o z5_{3~*k4Y{^{0@8?jx~ZBeB0Dv6(@)B|)9fkHnTiVrw9=U6I(8NbJQBHe`|NB?t$c zGCm`*WkJKOP|Gxt*rrHqM#CJ_!_}fWY>JgIAcO*6o z_w;+eo#H%mK?gNMt!_eM_am|AAhA~=u|a7S7D;EOxBhWbuK$80&A@|*Ls29)sGAGZ zW`HE_ip0)DV%H(DyOG#4kl4#0Y{-#@yCEEKFrS!i`PWIg{sWQ_E9lA?sF#J1*a}E& zQzW({65AJv9f`yS6|gWr6(Wg)7ML-DCWJwb=|qwM4Q#_SEJPAths556#D0LpW&~YB z1N8uC=>p6gJ0x*0Bz71d=wb+{hHNB>is^;_oUA2xAqkyFV&9p5^q-TmBnv+x9zjE> zFzbw`GyZo{mW)P{EP3AP~0)xMPh$MVzUV%LPrRR zEr-O`LSj23vHg+QtB~0HK}$bjzPyek@feBC2fCI98bZ=SQ%^Yu)h|a9I)KDJhQvOD z#J+^YzJbKPhs1t@#D0y${*J^}1KnH0!vMaNm%(`YLPlrtP(O$mIP9X3*bPYRZY1_J zB=$li_EseJq3OI#&ds(#pqpr*KF>p9gI0FJLTwR}_&Ox^uIY}NP2%;Bk%Yb>v6(=3 z#6XSaLt;xIvDJ{+Mo4TsB(@h4I}eFn1z|&y7pSuVb1!HR8OELmQ3MXURY>e@NbEyM z>~l!$TS#p1`ot@l z;;IEm^5Cm^paIg4BtB=lDyy@ypl~qMRx8*=}DTF%#iX=T5iMS1I1)P*iCv7uZbV{lLSpYjVn31uZH9un=pB*-XmJWGpx8in-9Xg{A+hC< z*jh+z^XaDS&im`-KsU@lwHYC??U2}BNbE2qb`lah4~boc#BM`kPeNkPgRnuD4l^*U zf^fhAyA6pAT6_fa-#H}lTS)9@NbFD3*FK08=j8(3Ujy}%`1Ge7&e`=Vk%aaju}>he zuOhKuAhEw7u^D6$H5d;PTLOs)pdo2=sHxm0K68kz5`zaFp zGZI?@bY~6JE)@tH(%`g&aKM4!Hhm(uvp8=ql2Fz3t=!JalADl(t{|}=PXEa5Y(4$X zolG7^o9UK3&eoE3pbKT7HcduiFPPrT_^Vx}gQC zv|zd_pL6!~IegAMh76!vQJ~^{NNh_awjUBZdiq&DXKU5DNJ1--*!z&!r>E=kI|tXB zgKkNI+Ter4jznVTBC#ux*mIEBE0NgSk=RF(*q4#m4V*4VoqmkH|NbGVXb}JHlG7@_s5_`QGXoED= zMSGDXP9w2zBC($%vA-g*nbi@|B#6Y8M`G(DvBCGBL+q_*@I;abM`EWUv5S$|jY#Z% zB=%e+_G%>dP9$~!=r$dQ#SAfEHfR8efq@|j#DU)Sk*2}GAPi*}B8g7~v!{pcFqEs` z24;iPE5iX08*1ncB=!d+_8$-%QVKCJY9c}le3uVYFBg(H9}-&(i4DH*hlc@j_@WY$ zgc=fC4~cE0IelNhg4^^9!p?sfS4=-E;(VO-LpTG&gy|C}DhN+sBkF9y)DSWK-b4kl z>3>9>MHsE73yL`_vz~}xU^p<{Qp{PI>6Pa6I5B56#+%bGN=u4QpCjfhz}PW;t(dbq z>rZV41_8+Cyf+}>HPiosgh3a<)J#vbV-%i#KunTlx`Vhg57UvV>3-tQYOJ8UK>DXw ziaRSaicFs??ySz}KmA~JsQC0d;?4rBpq<7X5EENs#08jCs;Bc!Q4pK1BjGH-*gxG? z!dackpn7`T6a_U_(B|Mj5VafjhzNo<>rR-yaf*U6t4}xsLli_NV52U}^dAz={ILCg zA7vyZSS-xU3_$z+n6`LL|8>q-YI}~Pvx!jsAtwg-w!c4G3=BLyVhju&(1SZ6u?^aW z$L?mrz`(@BzE=vg-wnKZkL8RpXfGgWuND&{+Xc|}xrw0tLqg%89bSwa3OpbktgNOC z3@j_TKzji}M?A8qYk)QZf=(-AanWFKU|^C`1*zv?y=K6`z{J5mK?h_X>oGYH#hwV- ztH#2_!VX&O$Hd4nSBZgv<*@{4Qy}R0BbEcx<8_=Bc$^hLn*ysrI}2N;ck4JSh|dsa zU|><(1QJme0Bs7q3}QA+KcwSqD7jn*G)j5`B*Gp7TK0Gn#AajfpU$J}EX~^py0QDT z5hDWw_j>(lzqF*L`{_ChG2WVZ8(B{iLFo%Qx z>U1wXXLZJ9(~I<+)tO$YOrNdi99s{%tbsu!2Xu*xNUA9V1CvM$KPVVJYBMmfh^z!{ zIAmY}EjedZ^JZpXU;z~%Z0Zio3=E=bEDQ_^Y`WZ_1>7=X3=C{~ASMGlXptqGK8Vf2 z9?QtUz-A!G!oa}6J{L5jW+)2UJjDJ@nt_4MNEDQV1=wwb7#P@$K~5H7?*|Pfn}FC7 z?4S)bY^Gm8yAs(?PhX(#EMd7wiGhL5d=h9$1rM8zKgjCECJYR0wu?YP!Mf!!9&;oyG^TAOVL=I}6ZKLM?uw`YxFVPN28X#*`1Z53u<;OGJwDa-;&bDV~e ztPBhyr$LEb!~t|*zlbhq@tMd()<{suZUDuQh^ZU{1FHzAL&+urn!IHfsRQjo6uF|u zz`!ZO0-8P%naRw+z%61cz`(#G@|1~zfmcLci-Cbp#8#1kfnOvFv;k8@*NA~ZP$X{p z3j=4_$itx3QHlAWeQqH4)Uz@$@XTfaZL4I-mtkPwYyye0cndHvaJEimWnd6oz{NE$B#gPO=P83qP*5g~pC1`Uy~`V0)3B7ejf7_>wjjTsoUMY4<-7<5Fc zRT&s`Mcz3`fp%K*v2p4%39&OU@ZSQh%QIl&XJTMr;NJ^cUuX#CFf(xP6ag);V|vHN zz#z`XY0Bil&cGlMJN=}Qvy~=j%?qb36DW`w`DH-MzP1#kAa^Jq`LvEfsujxG81Sm zFw-9n1_thXh71gx3z;l985jgTI2jm(zyvs*^Rj?k$j8BXim4uC;v&$(%F|#&82DX5 z&OXER64cCOgoO54NN6)~9|Sq?9Frd>0|WOWkog?Uporz316pm!$qb4hJ_$}yW)3a} z27XYX#wo_!%?U~{a}5|6IK`RQg31y8_n>?$!K}^1z`()(1SBKL9L&VPz{76=GE|Bg z2 zflcCon4}IiiHm_dRSdMmlvxC{Gl-efgt;GTQauBwDb%P}pp~CyV6QUrUj!u!3owU? zf%^qWw{q6Hw#_LD+jh9?5~QPlM80 zDVWX2#aY3+iHCuKpBa=VDp^5=0t0_OC>K_-I`c3vu<;9m3V>?XXdVUzc7D*(Va^&> ze;!c6>yl?+;H+f@l|P&e++RRe)Ul@XfVOyXayGL5ft%ZeY;H5Mxh=@%wnEHh;7$U? zM;q%t9tH-!2+mH{c3zkZyPzh4%hGOEP+7{x&j~7(dRRfF0VjVMXz4j;FSru+;b#Vg zc^}w`0sPLOW#|21O9J_yfI?>im=naG%fZ0FIT7rzV1CdA_nec!oDc@?C?f_2&dIDC zpv`YyoYPp3z}+$(*)1~=ZmDPBoC$FZ1GhVT=w{$t z0MX391yqhKgm{F3`wXbUSj2jP7gREV0)7o72H82+vw~){AThXsbt1_B4E$>~7#KJ= zvP$uR_M>oXgH}*)Vg>DZ;Zx+?%GwNa2Dlj9#tJS51(F#!x3hi+?W+_hV&L2XW(qQJ zhk&Yrovfe@iF{t1dsq*EG=kI0US#+0Lw0}teuxJcxG#W`_5s#@&~`p=&LgZ`{4n1i zMb>=`S@&^>W=J7@0_-|325t#ZnQ@Z!49FyQ&NHl5aFfnLO?m{%EayNmUC+SAzO^laFk2T11;pb4i0LGL!iLD0S-k836Pqb;DC`R1f|{149(5ep3 zJFIS?4R#YjIv%n<;D_egFZ>J)Lgt|S4Pr6yvVh#m4O$k+`Gl2CfPq0!S^$>$LFI`M zh+yEZ1Qk?oSk*xaK+AI=1;Y;}hI$4eP_tGD9I@Q&pvKx~R$q{^2#`4t;TmlQ22M6M zkWt)UK(&b=gxw9QB*egMJ~mEuwkrY*(DFco4OAX5K*|G6unI;FXQAGFY&Q->`D)c4`{RApe`)CF@`8MuQC85lVA*lGkA82DH?jo3gFg8b&7 zTx<+Bmw{gyR4bT(IgI@Apc2TG4OGrB@q;eT;xq$um>IY?fJ#7fwg(`SWH_zaN(C7h z>IFdiDmiV~K*^bbe+4MAY}xjMb_?>`fKq@R8>pm~fLLM=wnU0w98`-sfH~3(+~zu< zx`YihJIN=(>B6>2kb!}}3zP+2*+2~$27Vz>`QZk(g9T!eJ6N*_Lp`@2$Se=GM$jHO z5l(NmKY|Pl5J&ldH82Q(_EmEFg54nivDy!;TL@y5KbRxTz`Y3+O#y8CKqg6W2D7;d z!Q2r7aRxLqToVIJO`m1_p5%&IGorLJSNNp`f&q2o7_J zYoKhC1P-Tq2|Z9iC4+5{Fa|aAQounVVFFT=3ibp8_X1Fvl*ZN%at{Y*1{V_k#AV=R0a?mtz}d`pM3{j=AhU>pvjq}_0-*4$=WGS@1O!0)DmmN090dmM zkDwIO!8S#hfkE7Wvy1H`$mx!tjL{7?NGi36fwKp!nt}T{I|Bn}FB_-?<=()_z`!|) zjZ=hyK~PeJfdO0q2!U7(yeuG7_!Ky2vP~3WVBkN?z`#(?ISb5T;QtP4+s8rP+xHo zE4Ut;0`kyaaPo$lae&PhWX2*1&_PA!pqu?f>UBZmI3nsYAVUQ785jf@xX;TmFmN6R zYvkkNyv#O56tq7qv4Vl~3OMU92!Qrra$W^|6$2JRk^0b1;!GLq#H zXtAR)m!Q}yFDuC7?hJu;KparREASRyxR|Vq|F$Mztdx3i$X#^cWbpTEHBB2JU(d1_rKH#($vd z2xP?pF+}GKbbCFQB)DbG4cZRE<;i?QjDbNCR0h8hgZT}VCm003!}ttrI@}ospzZN@ zzzLmeQ;z;Yhc z1Iq;&&31#keue}C1G@r9eFG>c8Q4Krz;ZW&*i7s))771wt!-@$7#O(QK|%r?pgo)1 z9WOwUzyaE`$=&%`lz~B*{kRAN19vy5fD>U)(`R7d?g7~=%HA`5zO%D<{eDdb2JU{) zwh%dXArN~4$iMRJ_TXw;95hJ44q8jfJsG6UfjvNlfq{Dp$Z?MBZ-p2bxTk}}>)D+R z85p={fY=S}3ndvCxMzaA*1~=olul;d6=h)9z}_Ioz`#8RWabw3V<6AYRRHhVWOtNd zVBnqy(tMRYSe1c+dp@Y|eGL*sD-UzZvg8d2TD6CB&FUc_Q zvTOz&hQ$JM4$BT51_tiUAnVyUxVNtXZJ#q2V_@Lk0g5dK_5@I@>;$oy*ku$M7`S(V z*evYxKryr%#Aah)c_z-lz`eH~G?~s~!@|J8eFhXnEO(?B7`QKknOFH37`ShNnZh7X z{{-peCn;oqmsz`(5zR(6Nq6f|I_!N@Gb!0>>-AC!nR89{OJL`DOY)N~j@ z`J07NCXJhcfm;_c(#t3VI%$eq56t6Xl*t8!n?55aXnPr>%zGmS25uv;%_594&p|zp zdSk}zk_-%@j4~yl{9(!n8dsHIlqmy6p&8>@Nd^WLMi~x}g_evNk_-$Qj57Z~Daslg zG%1WSaiF5X4$Mnsl(`Qw#h$TN3bgH0=AQ%u1GfX%!gNNNbXEoiZbwFSDF%iNMwwfn zG~~p@cxZaIyR&rtAxQ>?8b+CQpj6?`$S(uh@+lK+!oa}o#R%H7c!N>qGANOHGj0%L zV7SG|z{{coI;w~TG-Aoi0y@o&6BLW`GSCdg$-r#|%Bnt$pr~M}0UhY3YX<7euV!Fi zaDypxV32iTE{j7@N|F@p8)$DkiITZ+7n^l336CB zNZf>dB}jcQNZf)Qw1I)A4qvM5?{ietfKp@^sN)4X4-kaGq0Yp>%K{o{XPE#}d3c&E0|Ofm&lT`7FPm5x7nkt=Q)U7$iT7^6p}A}K~cCK6oVf@=|on9pXYNv=nND!Lk0$(FQBksV1Eu8yZs3Y zJr;0P%<~(RELFf&G0z_mTaDck6kLBnY>ny5y`6cb`atRTKS)4_|2!zB7#KkuJ$}vU z=e(U2>Om7dCj7tj7#Mh1!R4hXe=QdS0}mItfUxFY4GIPxaG_?y58Cj_!wW9%9Qbub z85nr@z%nlUJw~8*ELg^a-w_o30$>>*eqE4@1i|H706(bCY zG6MsTHkc>GFB7ZDz`&yeHbt19ftLl80yrnhGcdG*GRtfR1_pTsZe5U14H#F*Gca(U z1!Z$bMrjRDSJ;7PF(bbc0|UPcD9J7Xd!K>-lmY_-&r&dlg7Z!_J_&skCf)cxl< z01k^7aQB$!Aea-&4;s(qIRxg!@o$`7@8>M30^0u1a}4aS6b5e4SsXma8MT!d82B1^ zPBJztGcfQkp1#M=S+agMC^pV8f*OGA;2ti|S#YZ3;J*NBSX~60%g5gV^7SP!ho655 zDA`^CD-+-s1?9n;U>PxRXO-tJBWQ#}oZk-Q_j}+#kznA~;bUOndBFG`RP{-LBK9>% zPd$UQ1tZT##x7L`27Xm;1_qu_U^WB)2~aeAW}E=pJi{*pDkr}%f*MsE{Gg?_JYT_{ z2$#WXL-gI z(+vZhB^mvvdj~kH)n|irX@Tcx<_UoIb@G^jr$Od}hf#UVnLx$h0`O=nj|CH`7+lCN z37TxQ1nXJE|I2`ZfyWBWSZY6kfnk*ZXkRCfFB2#QtdV&N3SvJdQ0r5NQN|aP zzrw(Vn=s0_fnq-j%rgZQ%%Eh?%Q6u(Jm>aDM`oNHI*al^GcLLV0Y` znYh##7{Ei&Jef?Ovu_yqZ-9!XY_NkI`T0SKJqK*G6Tc5Ak>oNlGchnY^E*#p9q6oB zze$yW0n(Y}DPnR`V_*=8Qv-EokAil=h=97$Od`#ipuX%Z&;gwc-1eY~x)N+6FAJz6 z%V)$hgXtK^8K*#Pf|+181HTujJ2i_5q(Y7#bVMc3Y;eeG@LPk5`nh0^78AeCbl)In z$$D^Uv=Hn91O8{A5_u8W3x*7wAS14U${J`Gd;qy%F;j>d0|Ori&oU-9bp{50QBeJ` z9L#3mzW|Ej6<{}lhHe&s8qkU$6IL=k0(Ai|gPJl&!1B^6Dm4tXDZhMZ3UJ2 z1S+Ojm}|8d7<^b{K$~)SSebjZKwCj&T0lvP4cx8$!y=OjDoWYGyuU0m4?(8zFpGgM zqh^&U0@Xr7%%J9B1)IzfP#GWsp8X2pkU3NjieOP@P>~hJAp;sy2A;AplxF>PQG=kDPWIC>hL*^|=P8O`MghNIPROTo%gNpYG4tda4P#%5e zgCd}9azdrM2BbZ6G^l zP$S``xQrnv>>a@>Ux~|r6SOOs_gY-WXZnK>XAuqwbQ;UH?LqbLo6ytu(CqXgri~=aoBf$Rrqb#EWs{SIuyuZpaCZI$f#SH4;FsR6+fm#94 zU^yNYnGR4sjsf#{Rb-BXY={M`6i|`r;i_j~;7MSI@7lvc?Pyybhqo9?L>q1_oa6$P*hEZ%fkj3t`SO zfo{qS47}jM5hivIbp{6BUQn}*giP|U#F4`OpLu-Ji?XiN~)W?*3R z;GHI?!@$6v2O0pF4w7eJXPa&t?rbeD2io8|7bK*_K1q{-fp;D#iK%d;B^NR9&QF>? zJ=|H=9W+$Ky9gv<#QsEtfq{4NMivGJ6ZSe&1_s_GAk8ieEE7SFTAB-5dURTzfq{2D zNSvk5gn@x~x4jMngJ9(J-{H>k^_`$qVXj6D47?{oKu5Dr1Q~L^3Z$Y-hk*gos|y;@l>zx*o$<0RXhb)JgMoopgYl*=1A`3zP6Y-A zUQNdPx(o~o{Gh!WyjqN)?vDz81?WspZN}HS3=A3!yeuXP`K&LqHae;qH>HsbO5&lHvUh=VBp^ls(T_BSU5mFz5E;GQxpDY76uFq;EpFh zxUN@`SA3@2OfyEzW`iKAe3=E2es-Phr{vZ6H zC3c`5EdNiC>lxTVqcZ#nzd$j{!rlp5TJ;B{hJ&3S)YShAV)L+X2RZ+rrU|H}Tn(C9 zVgNUeMfkUYmc%iFIb!^GKqG9-;2xm_|4}Ul27XpXeG>)-3;ylXYhs)wV=jW4>U`jI zX22~CF!b<)wi@w^gJmZ0 zgU-F;mjn-*-Qbs-{xQZ`vVH<+YEhQ)w-y7#3w}#bB*`(dX)`dqba-w!mypTwAI!oXm{e-4yklEIolF=G|ytXkhH%D}*%0d{W!{}WKS zWilQ#VPHt%Zv=6&z=me<&jYO|$_Be6i=P>kk#fN@IsDupZ{&kHdHgp)!CL_46!3%A z&GQ$5^%U`IfFivF%qiyQ0L61D$kKX-68`<5)L#bfn^o}t00nM2BdG0D!=DS1sbmC= z6*cgKPWj+(U<75c4t`%y@@oWJ)Wd%Olz5v!#xeBqM}UI7nenU%1H%OVE>M`YF@oC3 zQ^0K|{&uh)5k?u%7#@F@BO_=OPmED!J7_^l54cY&4vm{$uu=&|nNKnd4E&S9=1Vck z90uj?sbD!7Mj6)W^WvQ~>u-XJj`@s_O~50!b3g;z3&0vYKv4_I_`EEjtjz5VDksbt zL6ObJ!EXbO8GZp11_pjxFq?tD0OSEXFbCA=HwBHxf;JWL+cP?vFfj1(@cS}u1!?#L zD%m<|9tfPxoXV7z=)7hxsBk1jz>`q2JLQy$TNnh6{Qw4Fm41pQ;(5>L0yo6 zf#JR*14GSp#YAT*RuFUcbO#u77f4i$vlpu9CP+q%NU}46|^zk5ZoJPni!x3n#W}{ zVgdy)=zwP}a4;G(fr4=(GXsMbr~}L>YXa^8bFwio=qzAhU`VrIU;ynNU;rf&`RSXI zoptIzJ2Ein)-WvQOu?Z9z zfgtW0&{_acADDC`qpbYlwyDASIFW;{e=-G4xH3vG!h*v99L6!$uoN!=PVu0%$B=v}!5B0B zLz=UcAIQz1`~r#;UKWtIP4|P&<}rgC1H|frDLL#8XGpOWYV6X=3STkKF!&#aSWdAEp1_sa>MGUdi zT{E1O>N&I+7#I(L8p%-8S#22@R6*+w84rMSEn|=wIK3SLXFRQ$pmO3c6KKfJ@v2CGDhJ2EgZ zeg=!* zAK;NOC2j@=El|^v@h8)N69xt|ZfMc)(vE>aT@+MCI599hv<102imjM|>;Hc#26a#r z6ge?4{DO#slTb9HA%iX`n!(9#7c^xX+D+f+uOT}9Zl<$vbe$6eLx3IFDCUU)Y#N|* znKT$dL7}d~$iM(fmiZ8ACXNPB^p=5=CZhp^x(`&k14$aB&$*4It|*-?!^oW>RcWM z2CdDYiViY31ZuW{PGn?An;w4G|Si$GZ(w15E=oVuXRH6Rgn&~@*iyl>+G3D=w1&PuZDKx#q94uRDsF)%QIL^LbG zaR5=Lo8zp^3$g+n2C58t6Q{@KI7=#;fC_m~#kdP(2518q$P9H*xeT&~!4aZ;O^&lL zH%Laa3CYm=InDz0Ge90*&kR~11oD*v*jI@lV?o{k1*$Hn{jdyl-?LpLXzSVurV>Z^ zVOn~iII?2`P1v1e>H&#^OkrREi`xf-rl)e4L8CqnuM8L%7%kU1!h%Upnu&qIK~@N~ zz1{i&1_lszF4JdV0AZf_%+8==m_e9djmi13 z76Sta^G{=PzRttI0Kz>?y~!*oR^7jelMNJ49o*t@0&GP$@*a&j>+z)Y1xVrx&|$mF6d2|9`!CY^yKT{`_O z$nXhBLQ9d@o2JV$yC^5#LK1q9#Qu%MW(S>G1@)FN5?daLt%Jn2Kw>9M_dTg9p12Q5 z=q(bP4|MPp)MyJNwhIzF0Er!g#4bc)*G-pXanYCDj3jgdiG6i?B8!W%NAc+_Y%UV@+@NM0)IkbJ zY+WR_H4-}ji4EGv33F%$l6VOcy8(&agT$TzVS_e1F)%EFaKJ^<1|;?#B=$)p_EjV{ z=nzYoBV<60b*N{Ykl2w(>{KLnp#Z4m0M!6GPZ(y<`up@& zb{AzydC)#ZsI(&z+i&_okaQW6P&X2L#`M4JF5-rpk%T}uh`KAKNCr4DH3}l5_>Na`y>(@blV5aDd5wopdS2zq=pAn z#X`juk=VKrHY8FlAsld|x+1aTkl0yB?4wBRTS)9rNbG+|Y)#N1Q&2~kA+eoBrcdK^ zajQRsBz7B#{Sb)_I@=iLS?!rltc)dm_MOjh4lr0k5YkDT1i!x);^jRo z{77ujxw|mWX(Ne)ZoYttyCaE*BC(T^*o8=J(6Pge8VsO_WnkzXAhEw7u^B+!AE;eC5H=)WB_JGd ziJ^kTHb7$AAhA7=*da*l1SED261xJ4-HODXBscw+pi5jm=nQU{$F)E+dQeB2A+ep2 z*kMR)@C+bSeIAl{6%xA*i9H#K4Z669QG)@rwvmAWd=3`WpnXV+P9d?cA+aAJvEL!F ze<88i6cDi}Jl$5<<#hc=B%%LEY+lf?3e|i8zA`%-sR0B10 z5=2}M9LdWe958ze68qrvjUq1Mj4!6|6>(9P1g+43S?vTmunTIG|MZ_CF4nxD(^z2A ztEM}Ox>!$_aZBRiWdw~GLzVJPpDOB-&Db)XQOrf0cNvn*=IN?pF2ASih`aDiuklRc znQkHOl3<$vIzI}kHxG$jgT!8r#NLC%J~{oWxQlfnH|U@ys1YhiY%L_V0TSB`iEV?# zc1B`@R)xX5nmxTx!X>!=I+FAoB=%1vHZN$r4(b$1B(@C_8+;rTR1NqzC@33z92Ard zI?V-UJ@_~%ScwQe4+^RXd>#~(4L%PF$_AeY1!aSd_JIL3^QKW`fQXfw6BR)YLP)L~t0sBe7XQ1HVw82_vx;k=Xi3Y+EF@HxfG%iTweI z4LT=^5fuNR(t}+aQNT$dvDJ{+Mo4TsB(@h4I~j>xhQw|{V$VWiZ>mS)>_cLoLSjEc zV*f&7vw_Bxp&=xM#Fj^5Yay{sk=RjCHYoiuq(V8MkSIW6PefwRL1J%5Vjn_cpG9K7 zKw^JJV*f{CbL%pQ!H1?4K*NVn-{?*clyxbW{DdR~+Jg>DKO)l~%DPxHhE121a}lr4 z1}g2sIY{h9NbD6z>~%=&tq?ZkJkm1|4k!c}E+MgRAhGWu zv7aEZUm>wSPG^*N5w8brIfeOFMjw$jK?@0B;-H<-Ft!7d8qf+8n0N$|cnT7`0Eu0L z#O{Ew!Ks2_3WNjp(*h*+8YK1(B=!*`_5~#N9VGS(BsS>mBbY-uKqJl2NK`P$M)=qg zNx}t*9f-t^MPg?nu}hKIpmnn_%X*Q-XH9QZaCu)p-w>MO^BNDrB`a@+GWwUKaLSK;B zY@k!hpmqv^*w8~8MNL5mI8N77aS^Xq0b9mk0Fs6(wFa@F;^2eMpyHqj4o0YW97qk+ zxLPFk93=K`B=#*N_BRk4YGys783O|&JH!#JW}tn)5VinF9I8kf#D-d|0AfSM^^n*$ zNbC?08>&7M#D=O*0kNUtnIJZ-SyTezKqV?cY^Z}~AhGu#v2P=>e}LFf3z*Fr7#KlQ zL!b+j%^4U#^A8~J2!X_*YGgrds9oCTpk@)2V}&GP4`M?NN(8Z?nsY#GZjg}-3hz%8g4`M?dr(nUrzzAh)BC(AuK+Phkgf)_c3liHGiJb#tLoFxJWI}sd)LrCm%AU0I|Q1LPl8!FyV58^;2T0v~6L_dfP6<-KqL&aBv*ii8e zAU0Hd7l;iN-w$F##ZQ9RQ1NphHdOouh^+#;iHL!L;Vy^+_02OR_8$-%5>E`QRtyY` zP&OYDTLZ*~>a{^)yCSjukk~08Hq@M4D~5Wwp=C%C6G3dKp{tPCn~~TjL2Rf&myp=E zk=V~cY^XUb)`;}M4`PE)yRBzn5VmGu03DG4N{@0N31|>$g4ocY(*v=g;x6Th9Jg`cj7bF7JH3P(knmiZ8hKjF7 zV(&y^9|5tU>Q92$Q1w?qY^aSdk=SfDh~TK_1#v*@VHg+~1Z_ZPLxKW>fk6!<4mH#i ziERa9L)8a>*ig&DL2S^%4h9B>XplKjb|FX{YEBu54OQO=Vyi$$3)?^(sD`y5HdN6T z5L*o5pdBDXq3pvTaj2S$NbI{v>=z(5)Z(`wHdOB)BsQBZs1kr0#B0mIz$gx}Owg8r zK^V%G0f|G^Xd$spL2Rf6Rvj*KNdd8;YVtvBkT|FksDp7B7#Mny*mIEB z3qfqC<~1NTNHYTi!$uGrD!vEAhKe5qv7zFpKy0XI9wD)R+kz?qs0520!uL`jHZ*@J zBe8Xm*hU~WRBs>>y8wyZiNs!q#6E;z*E75aaiA{!24aJjjW94U{IX+U0Nwr#iV!|~ z1_oI3M;OG0s+R+?p*~gyv7zF6AU0Io7{rE(+kx0nac2-4RtfllI8cc!Bz8WC4b@zY z#BKwzq3XLqY^a)PAU0HdHi!-N%n~H_9uOO<{&+ozBMI^&1H);11_og$`x;0bs^|fT z4O+9qz`*bn#D=PQhs6Gl#Aa|{U|@u*5d*QIQ7Mna)`PM^>5su2#DQ913t~exyCJdt zk=PMP>?{x)YC$m)y9tTi4PryhUk+kJJ+{dKR0&8!e80_sfk7C`J_u3-WuHP~Uq)iT z1hJtOe?nsaMq)F9mbO97;X-1|fY@NY^$ZNEa1H~59unIW#D==m0mKGfe#yYV;Nr-@ zAPi;uBZ)^Kv6Db-sNO0h_9P_sJP;dnxDd$yt3VuY5Q~9f3y2NXd;r7-Et_IsU^oS0 zL&dLw*me;04?t|F_!A`dOC5st%!U2270g3I7#P&vF2O+V;kl1lZ>?9<1Iubh@iCyf3RQ{JENz@~; zn~~VvNbG(j_H-onY$Wz#B=&M7_Iel_w61M4jKjddup5cJAH<$+_}N!}`+?_{Cm6RU zn79}iFz%T?F~!B7k!AWr5alr4FxADMF=Bcnh}tpzB8Xy`u9)WH&&V^qFwMoE>Bh0? zhtgd9ct0FtU;vd(Nua8JdgBLC>FFCfrC6rhq`RmvicC*TckyRbn7$E2SxjflaPemh zm>!tn;?McuI0FNyAWNFQSFBKc`hg4=1KuCU85lro@j-^kPJg)CMR>YEri%gNlL>-y#ne9@}^y1v~L)k8Vj1#5{=D7HS8~~zXrf&pM zJ<}O;UHlmZrU!zk9n%-)y7=?nxq`6McKXG@4C(0-c`h1^71JH_T>KfQOrHp%c&0xD zQ8CjE^TC3R`7ZC7?%bMQRN$h;cx?LI0vBc0C-)c_6s8{qG0j357}ig}*vTb4tGaSd7iA{@mDBx-xW%SVC~^^C?3%u?$VHv?&`Jh|4#=_p4?w~brhfzpd#z$%h?stn zQA~KcL9vSfW6X5NVi$GRMOzsd4o`Os&roK}m_89C(s7W1!3gZk=@*J!gyA;^%#o7V z&RF7dpSgZA^KQ`214j^Xj`WVtgjay|1+ym;0|Q?I8v_ID zOXiCp6?_jF85me!fjKPT&KK)zW{_SEKG4zZtZ%>^E-iX1Z!t44u)b#oo#4mI#`=*NwA%n;)F-e828iy@U=9;R_ZP5k76w*O(q#S0911#? zosabg^LLO7r+^&w6Re(r4^%C&{sMED_$)yl`px_fbSyvLbQXqs2G&1dqqz9qfTaF{ zIoy2bK<@nq=J4>vfH?ob99{-i2M~{eWfI6n0ahlK3}yxfK5>vAm{~wRXW#={&jRK! zL9Ay5b66nOv$24zXX6WDW?-miWoH3J01w1^4lsuoVm&9A!^gnN&ceXJ%EiJA+Stj% z%EPh=ZX++)Tn31_d|-2#`0j!n$j>4GI>#R5M+Q~_mP4S3Wng^`a;6|l320NB0IM*| z1AS%&27zvns0i320(U^6APTmEfwcw15o6g0l9vEQn)G(=Dwh%yc0(gmGfM;G>GPPx z#90l^4UG(@`+W#g-+pqP%jLcGyay4NPAs-$VBnd_z`)>P$-wXflw_coiG`U3a?u0} zJChp&0}B&7=&o_r23OFv6Yii0Vq_~&Wnf@k&cwjLBoql2;Sdl6DP@&#XJBA;;Rjti zVG45OTr<$M6Y3!5E;kTcN)M!-gO$&bfq{jCJ;$1XfrW+j6X+ra7WPgR5RZM9E&~G_ z%SMnwMvm2b3=FIVN(>ClBA|86tXb0&b6pj9wrYc}o&fE8V0}2fH`i4`Tu=sd^~4U4 zRZ^hi;WTc7m=4pAEH8Q6-=c;tCq7FL1r-U8-nb~0dpAnRY7-v)IHPA*}*2?Ju1+Lolpw2X#6)VUUjQk%>85r2CS$}~p0O5}?U|?XgVTHJ2 zpEKyL2r!3(|08Hms~wob!@#o~bc2OGYbPkpEih$ZU{^N-U2?I2je$XdUAF*qg9Vp7 z0|UDrh{?dQOOkA=962|C-f3FLUzGI0h5&erLy3=D#x6GVkT${1L~Y^OUGxk}bA0Ua1W2^4o?5MRz^ z{J_S*Ai@ahQH!{PmM)3N%7DCS1HSL20+eS&g3UqRd}j^XCGM*O@+RnLZVnMpBal%qb2CB3eYV%sv>;Cpt~y8sDtjR2onX}RdLE5bXUb&dC*-I9WJ1|Dyp49cU8PK z0^L<{#zB>VL63nCbXSE4Xiw^N(3VOACh!J#ejPRj22MjThnax~v|5PMhzS%@;JYfE z*clikbf+ILcD2#~-Qme;%LEF0Mt&#I!OM1F4io=Z&=K4AOlsh}DypYzmbj|fW?6u* zssO3x16@^72ijq3=nlTB0+cct_(9!K&IqRIpj|8cU^hjAox#Dse0oobtE5w$8ThIS zkP*E6%R$F3$1;Ix6+ZqKpd(!4m_TL<@GrMwVBm}g+b+TX66BObCN1z)6?3LPFL70? zmjfLvn+kTTECUxP&-H=MMgWy^j0`-F1sE7O)0y_cuB!M1a_CG@vd&`ysbk7HmoRnf<;N)Zm`3`(l1s7<8HK=^z6l3lM%`fn8cK}~iu^C*NU*lk4 z;FMqn?SACo2lY=mC7B~Z#W;VrBLf4c6!;XKdIA2spwp3Mz{ZO3&jRI4S>|`(t15Uv z>uovZnU`{c_7HO_F^9lyR7SQ@g&ATa*d#TuNgNQ9)WIfkG4RxY4t>{T76V;20lKPU zBGe@CRTU7&mxGQWHv@Z>k^eR*Sy+HMObk3XLAouO6F|B_S5@4G>So}yMRtcB)E#QJ z3=Ew1V9gx-;9z$Eb2u4zm_Ui#k$EosstR4uRTbbsbO9SB0Xh$c)0G(%xDuc>CY)|y zZ%b&2GB9wuGlLv1vD$`#fzyK-W)3l(K{n1SnTC@Jt0Axv$K69j5XZ_w*?hu1fVftZY1>L+n8(+#~dWSPVR~K}CQW zt2*cg3y`Iti_Vb@1}PE(HJKQoCA1}LKMwa*k zA}wy95_&nPVid6#ss|O(v2F|u93odhw=ppAq=JqocLlcqcodiz7&wC<>}XIB=78By z>+)DHgRFDW1vM{PK(lfppbM&)7R9iCuD;;pY-BBg zo7;qJZZqp_gt0Bi#DhAipvwBqxA5LHzqcCx=f2J1m%= z50n@tfjIRHAq+gh&fr@#8bEFV-J)Rwx<>*WT+@-=G6UHyGa+ta;Q0?ag>@DyH|X*Q z&?OpeaLx0OHP1)Zya1w^-=80J9Q;CvPZ)TtK~>ozRu9mLP3fSs_18e65Oj;iA-J&{ zpvLN%gD=sT1inOrXDLYUCf0c%XMirz_zhAIE}*xuf(vNKB^rN08&V;cXn>f4^$a{g zpzD`*vYrF!1l^)x0Xo|P?EAe?o4_%#57`6zAs%4h@dWw)04qB`0|TEo=MmN>xaOnC znvWrCJ`T|gJ~gkN^90y=UJN`JKxNxWaHoV1bc@C&xKU@JM(qQY!sozI&Bnm99(4Ts zdDcGIB^nL_3=9%tAopBi1toZi%b>J-8JtKZ`dz`7Xn<0gL_er*yvhoSD2aMwPziF4 z6%^$X<)B1%ofQ<+63(E|y}=3!Mv2#;BzBV(6fhF)poDu1>`w`>dv3FW9Lm5`465w! zuGeu!63=7n}@I0xnTN z8iYUu15W{{41L2oA9Ov&PPhV4#Uli2DGPxkmd6}alz(PD3Q`5S`5r2)3~E-ev4KqD zc>}8F1R-oyQ1vASX7jPtbE>oXfX;XU7YG_`pp47F4=xWh!Ack*<$)I43-B!(mAniL zoZ4U+W`17Kq4_#&p!3vO_;-V@WY7h3SQ&UgqobU9Y+pdPnVN^rWc zX@Slf0UdA4>Bt=(vFdS?nI|I)>P#G7&)&MdIbcx1qkfT7CK5#~Zl`!!4ae`W;Y>${g2M=v>W?-o2 zjAaAW2!aeepoM;%acrkxw`ll+Zh!!tEy9_|1`2bD)u8Z80*8}?An0)5WHyiu5;g)1 z44f(8AdpxK%3G;yAU`nh#DcDgNMmCc2A#ynnZZ^II)Y^)DEVcA(+LAVS3M|lv%oSe z3~VeQJ9)%Gj?89@1YJeJ!I{f;732_b#?Aw$RY(TT2L}!$KbEk8(w7A24nEFOwxdXw zXf%UnVtJ;5E>@{v>lbEV;Mt=Hs?pfq3NtWBz6Z^OvVktG0OuQU_5*Pl*jPZ8f^X5V z5dj}03%W%EoZ7&*XmGZI0~CIV21rJMfyV$;<8-j`h%i7d(Z~c{O|co2F}m46=0Gpe z0I6o+`3E{_ufCVf1Ju4T2Hk%#iLDWIiw5Yf3~&J;1Y$9;v4D&L-=e_@I#p;TC{@m4 z1F;$SCxL42*=+oxpflIDfXb#hY@(u|GuO;O<|zWMhl#%% zR1jWc194dRe}jVQI+(-8pA1T(H`qEsA;ZAa4r(6VWCLw^v*+0bx;*9{+YeC&203(%f%TOxIDnj&$81WHn~bDJP~7H;0G;|=Bfmb z{4nsJHvwOL0aC@t&oN!H+0}tDczRT`t6F`H76SuUGguuT|72V6r57M|{0uw{=HN>& z>_9^}ETA$7Jbb_=4jn#VWZ-cHU6LUQZmILIg09H$WR??WV2}hAoJOFlCc&-;5e$O1 zFg^pj4tEA=You8zrkI9PlADgV+u%p1H{aek_-&ojUYA?$8%Q(2JR-1H&{5bKu7R5 zgV@vST3prYB^^NbVSv;La6<0G&;W%!C*(d1V=)E>VUAg#D-60pWt9krf<5Ry3{WtM za(r}QVBqcrvBfy{fo_NBlVfIJ5a)=o09}v)ibFY$+2#xk+!H{dBF`}sbiV6E(9n?r z$3c+$CWE__4jjIqGx(=~{NTtT1-i&!I>^v^j-8I68!|xb296fcEe10|A<)9H5p;9F zELkxIh7BBtL3abp0U5f5Ljn{gb3v9};m}qGU629NdzIrT=!$~*pdSA=9Xbi> zw%6M-u;zihw_qaZSU*-Z&z`(s>g(L%m2q);`43G;XI2MBLHrNF6sSE=f%TEbVb{COk zU|?Nu4Z1i3*eo2m_6!W#+`B;> zHU?JEf!N%8cY@5@%f`UKeFhYCtR0}MMJ|JxlG9JOxk~D$gUa21!TVAS43MG#!wAaLEQ~VwpwQQaj3zV6 zaDxuy)&ui+7-d*NF|W_)54r9_29)THz%CMDlmXvaWX$*%blXKeql_3R<(o2s22~{( zWvoB}Z^kGr1wJ&*29!`O8P`FsyU+&R1Y!;LaSEeMC+LC-J1{SmQKk=Miaq0D$aNP> zK#p+$TbRx$lf(hO?jjd*-Ni*v%sVl1NHH*!Fizjp;VM=SV%IRraDi?}ac2yLTzSFo z2EOt_PKtry2BXYeQ1bF-{06!5f{jIw6O@$pf-X;D5dsyepa@Epffjb03_O28PViv_ zMF6WG=u~ap8W{!#F3^MnXwx8cNELkL1>0^}1_qAO>Asz=;*y|II-WpKY_V|cbpV~k z3(5p+9G25-J6**yjX_f?VIXM^MmbH;2vRtR!^J2kU=O;`0>t5AlrwPyU1$L^myc2I zGwAG+C{Th_W0czkIyE~Q#8GFI10^V)SWtS>V3eB%I$1gnB%{eF7c%{Cr>ms&KhVk2 zxgaqeMmf;f5l;cA1+U8}H)*2UXZv2N2&w^15Y1FJc45l=v>zN2_T6Wjsnne#S=jiH5|u4=dn))i8pY3 z291hO0f{f*5CdtR1`=PwA!G%*;sPXogrgfY+&2p(euASJ6k@YM;x9OAKu6up1C8*# z;Q(Fy$ul1${)OWe$l^sH^*`k5LFbP1ECxwPFv@|toIFcGeSaB7xwW9<&{u+F6d2{c z+kh^;07a+@qg+4enCSJO$sa97IZ#83XCtVcWyC1=!h(T;XA`KUmBc6q>iqNU1NCi+ z80A1?1U&me!yCnna+5(mJOGNl=n_T-HkKaHm_2CsBnX4!fr){Q1vEU*3c8ht=P+m+ zDLW6(l@3s3=^yGtW(syI2@lr-PE%t#r^lO9{`N8`J%ITxIHOK%w>+ zG(5`zo+jaW0O^J1$a0|Q5;Bk0Zx zP*5;%Sb~n0{|O2`7H}QR^Ba_MRX9L(FwY+lTaCj26k2~lY>nwJdt7;?VnIp#KS)4_ ze>y1Y7#KkuJ$}CF0==#Z^^fI2M_M-9f$zKk`Nou=5!9vS0+$lj{B@v%r+L67n+^Xz z(ETO6;4;sFAGCRvhYu{{!avs;eCGwIH1yyH9hSx;0G9FLR{^<5kP#GU0sNp^lt%}Sb$M{P#?LRa(-3^;1t^dO_+>zq zH;)!rPLN-wM<0CW1xQYaU*^9#1L)2RP&5hiGqACM5&+i?c?O2lp!1AD`Bt8RXFkYq z14htpSDwqDQ@|Y=Cxgz%&`z~2tK4`3;n!@~bpZ2JB_SEKq) z(4__I7(uE9`O`qP(RwgP9nywK1)cj0vQCtNX9eg4^^J^=VV7PQDueqf;7cz+NuPmV z8DztDMi57UeQ4voCroeXca_ut zb=P?gfP*Fm+@0k)2{S5SSCkFFXBUzpJFmEYK0;$G{#-Vc-b_W%J{Vg|JI6 zPJ)gzRha&--&N9-7ZhS=7(uNUc79Ngl;7bHH4a}LrzjS)4V*W3n9BvPG@Dl!|?hK&YFhHg)15aV`ID)6Jmh-;^g}xI= z59l@w&`B&j?jRn+O8zIHeCfq>75O#{P|{cKa==DA@pFQ5PA(HC_%@80)89^VRrLP>Dv?2p2YD*Ns`x;6 zTigN}nhA=DnM@!y1AibWWz1p%^;YHhH9+Rf28WXdKj{2pp1EL-7XOXuv6EdT>%oQ2 zLZ%os1_lFu(2;pOi@@$NWZ(js@JbEZAYx+RQ2|wiiximw%5$AQLE-hg`llR;T*CDS)G&{ZCw33Hy+OrR?YL_pV1Fw~2z1?|Td@l^r! z%hwoy`sIV?a!7xkXFJmtbp{5JaDLE~!(-544I&Fb*@&8dj=^620jIz3rzN) z<8)O)F>n#=eFpxA)BC2lN@{?nAb75T#ke3j^(qr6r}FTFbLurFP)-%#cb$HIimPN0 zxPf((3Dm-pVc=N=YW>|}IsnRcA)rIyUV+Vl-0A_^E(^QV1C%lt_&gEs*nHBY*fDvT|70F>7GN3U|9xpzI!whQaDKmrWFT|xDmZIQGJz7C+6(i;g+Tcq)=BR~$FZFn) z4ZhT41t@)+GJ{$kJH%xsgPdl@464v?h|4?xX*37(?ug4UfC>o~6^InU~fODoB zGbm@i5tnHNE$eY-2BphC;xgN(YfpETuHOSnU0z@pvPj7Af$a4Lds{_9rVv!+`+yBo zlaR>)HKKf(-)MvH_>cf406*qGAfA+rIY^~HGpLSup)BJ7s*eJgd33;ceAIw0YYAco zRaGC9WkBold4icih5R>V8N+%|qdOFA#ZP6K6QIf{49xqbECZUtBw=K}AN+33Q1bSdK?U#uZem#DICcDl*)lY#s|% zDWD=F0Gd_eNni#I=*p-taDh4&pp*)4&RTLaFmQp&6;K+5igGEaGcbUn8^(X2&AVSX_K@9b-!bwSf-&2;6hpJE1bJV>DuhpGkWMi7uf6;8;F zAX9Z17}Pj~co-OX7l6bKIMb4g8F&|h9Bs&P6LjarB9OQd$97QHZt(+V1_l!jFAvZ~ zAs{nd7+6n$e71Cf4g&*gh&Je=5Rf=)z8mPGkRn|c1_r^N=~}Z~|>Dd63_)ffTStfI{Xj=pGHhm%6aA43NVZ zSZfVIH-&%=zYMzl7*zQCK-aZsGs@|MZVF*z zNe8c9>;aS0!Q>(^c^FKd1CyZeVq^KD>k1mF09_T##-a*ZZO38@av%d6_@)p~J?Kp# zpgr#Va>fh{yvE>G9RvS1X$A&f6EKI7-)uVf99PNu&!B5Z%)w$T{Chz|s}^7mD+A9L z&@w+|;c^@=G%pmd)w5?dA610d@1a!m*vxp<; zo)-~eaQ*A4395hftw8lJ=$3g72G$(V6%zISOY}iEg@76Y{K3iw3=ATmg|rMJ`$0!o zh&bASngJKVOUkmr7mt80v1Mgoy#P9*KI#+bhL8&WdFqA?3>=-H3k&9hk~;%Oxg7%o z{{j%3k;4~c4>%hzaioE&^+h0YW)1~$1_pkP#UKs~$DZk0b6u6|`9Y`cuLPw=4vu%A z0lHNnHYbNR=(>*8AT}3=zZvKT77&}819Ztd|2hzxhXZtyEdK^jmf_>@0j(d{2uh;@ z9BWJ&82C4V%1sfD*)|Le{F^~+1&(h{po>C4Y#olRAUAHS0bdltanhB6fqy%wK8s*r zeFC!iGH5uD-Gu*HHpru(F&=(!51oOt0DMsh$WkVbd!YLQUV_*xoREt`RP-4bI2c&h zfK2~jWXQmv_}BC;ui*U9QZ-&oB2fP-O`y)JI9O%^e?Mq8R}wtlc!NJ^y25-{$$B}^4IQ$KdODz+LV`gG2FgQ$Xed5kjs zAcbmRM;0*3@PRITQ3rSE3mIi%KtZHY59Ssz%EW^@m%3o3#f&nVpfEE4%at(7RA@6W z@SA`QEn}4V3F-%$fq5063a-qMfkElG4)mrFP?+tp4>H-&&QMFM{hXzn+Y@rxGBC?2;`0W1#t_T(C?I|4WcJ z^1+-ueos*F7JxYg{0yLcPz2Uf#J>;}=_O!JF~2)#0edMZkU%$uM1Yci8Mu>M!S4tP z+;YZWrVI=<{99ZY82Bq0K?7_J{Gda$_!}5Od8~t97L@)P!4~!K?**maCXjIqef(=c zLEg;BU$lrfrqcA=|gJsZf@`HW(qTPPT1Btc=a0Ib0S z6ty14paL9}mw8%2_pg{Uf+8DyQwS(#_-}(kz!n@!4E#qxM%jTmpgvRvsHOKD6sPu# zC8nTNe*C_SFF-+S021^AE39XLnBfoRvG9KZMOOgW0UZ3fAO{D6Ih+hUJPzQSLRNtm zce8-%S2h;Vc_?fwhM>7UkaIwu05_%N8Mr_esezjzpjF@uJfQm^_!l!mJOq+Z)&iX{ zS>FaOR6u)-AZK=i!a)XfWJnvR(GK1-pgaw<>ufrz!Y;VN=^%xm`z;uhRY5(%6{rd~ z!xgRoDRcrEsXQHY=*mttMo!7;;7(_u=iGoH(7;lJxEZ1OUU|>)?1oGd1xUrzBka5l-kg=d7 z!U&N`0%-+1hfx${@Ep)RB$*71OroGQf9pX8X|sWrVMmLC+y+`N&A>Q^)q;UR2kfV4 z(P!GzXDo45vD^qcqJ&)>R62lEg7)t+&hfEeU{L1;#T`WE93umR4%nsa;vknY2J5R$ z|GLCg+32JN1A_sm+F?8)1~TJ4BLjmWn=1puO$*rZ=|-T9VlI0b7>q&JJory9+~z7a zJz=S*z^laU6p0+tl+kSECbnU8q2`I;J=rFVd`{&Wv&kVV6iDsvB#Fv8HL=$rk5^r z)#L)n7%MR{FhJe7Z<(uhJ;+3`8>JacKrYb^2gT2N(4qkbc2GRexnvCs)%9TaF$O_g zw;t?|GfWH&hM-$c9$CYjX6DSmz;J|tfuY)(fk9shl<@blgBEHrO$;y!1??x@%fMg? zTGi|iy7}m))$~R&H?iqW%Uy-oqV_T{{IHrnYq_h8ihwl(gC1iPqop2WG}FWY2BXC= zy*r`abGM!zsK+Ea{rz%RVTkuYJz=Q#lvcQkKtcnwND~x7yRD}mly=kcFa{l=f6oGJ zI#Uq?$oOIgXrBq>4RCmfGMIpTt`-G422l!}3PEwU2AmDH+JNF{`py-uvL>KWWkzXH zkj;!CIxTDr3@~1(Ca4$7C=1pc$;`l@2~N^-q8Fxft#p-=JZb|AGDI2zyA_g#qE@(y zJ42@2Kq|qm5@9d_*{#L|+Bg0gT%&+or3AijrN|zZIX^RkGUpX$1_t%lcGK6cbd_Ti zoPK7dt1P4I^j9lgl^HKg=Ue5f;aChh^Y9ng7z>vnm%NvOLBtLmsLT_6*g&CLBB;k0!|2LjTEoD=0FpOBlUIkz zPhenR$lJ@n5DbxLDgi|bqk$e{3=@X~gV6z4#9x70+;0c5*l4w@1Z(+T28Q+1{a3q6 zgPG^2=dX5^hQ#~_P-@@Hz+h-U-SE1r*!1HHE?)Y;asJ;Pn$r2<7fcvw!WS17D=-UfR zULd_-YXlffKnALT?#W`jD+;>#2NaQ@vV?I?oC5=cI%sT?@vbOnaHW!!fx#Gb1jVfB zzt*@Kq=7bGLyC-IR#1^Ki`G712$1SK_0c930M~F{mSupWVS9|WtH~qj`S5`={f^H`P zsd03izR`_IZ2GIUu0kS9_k!ad5_g~*cNo;JP8V3`DpJ495mv&j76&=^8XE(HRsjR! zT5*t!0O;Ny(4NT+Py>n-^cX>xpfIqpfQC=h)_|(7aBvj@3L;RHFwOxja)bmyxCqEh zFLnk7Bhcw5dq82Wb`rEFzCjFB!ZO%`A_*LY9iS_MKr;l44Pv0R3)$=p3_75;5MzTF zs42u4tPYxvU~Civ4RS68$=XkUu+CK^2c(lR%#??Lf#LXG28IYHh+jDr8B7fs7#Kjs z7HBuM9%B?!86zm^gNl_HMl%Lu(1yHAV4p=Zl`$|du(5zfTh*R}>Ln?N0~r_?Ks$&S z=bU$DU{HTJJz>48EI(-Il@X$VF+|68de3@S>3Xp1WWcWb19lxKj%CC^qp(a98MF%G zQyCcL#6XTU;ee*r`_8cZYYGZvkn5eCp{`e8Fa_;E1i3y5Dpmw?J?K&yP|h@CFam96 z1gDEsklR6#zRwwwFam6t1g5XQg`4)6Z4|u@<$O+&? zFTr2}@}e4Oy8)vuJVv#^k>l(FOC`487>(s%V9*Q#9e`vn0&1ayc9a>*fKKq4ertoP zg0(iN{;vj0fs(}qupzvzFhi=rhHM8J0vd~AtOcvI0bN9-Jl%Aot1{Dmm+AADxQb0L z*yzdyN!Qb$x%iI@#EbJbx=PkRfrSjH_3{T~X*%5Hp#8awbKK#Urh_g0%*nt2T2#pJ z5)$u>h71g9BA_mQC%Ab5axQ2WIpdt)aGjmtoFT%+z@WbZbewg!IH*Elniw$MY?G^q z95-m^0%&gogApkGgJT4g@IVoA&lOayiA}HDQ1_#wYH(0%XTMU$g7=s{L;WjiY=+uJzdPfWt_KYDG;IwrQoVFN4wUP=M z81IYybDJ)^*;O|5s2c-=<~NY3uffW5xEL5L3mF&~wzxr3S{bN3XDVjUV~k}gXJ9Y} z)dvjwKyuOG>!!e-;@-!=06NW*L2Mrb!&|rM{hM7SvlYRrqQI)ySU}?kR;i#Q0#P{ zuDI1zXS)3sSSbhEbpw()=?+N^8CzUstaLz*tYTmQJMy(V#0wJxK)J<%!3cDzkHtO) z1|v`qgN+B>NCYy(!~@b2yRyYqniZ7cqNjh^;;ICxj6l0^p_P%w7FTh51~wMZTmU%p zfZPm@NPY&Bc^(W5HqxM>Cr)r34N6F$6Tukg-1A^yfRtUFjH1(fwz|r>iF?9?BpE@2 z$!EA27(k74X+}^Rngw(enhl=^0|TQG+$>OvVw@8I*J#A}VETuxuHsn+pu<)?;p#w} zY8mG|0I36)rk;$T(sUi@%BxP$p}Y`2W3VQ;S?kRRN?tFx85qFjr^`MDhBcm`fQw=( zVqk#Rq2Q7d913dnd7y@J9Na$8^=^!F>byXuBj`-!IIw-7%|kk1`yhPAU`PUvX9Sn! zArRXW!L~>8Fff42KalNSUI^R4l>?~p9stezpcd!!ifyj^(^a>-3WU1KGB7Y!f;t=w zpwgRhj=eVngF0yHk`c1rw48^5K?gJ~!dMA*6=SdtXvzdC%NSxL4XS=XEnZMj3rY&y z-qRVG+{C6Y*zT$(7XV66phhvMjiBKTcbGBg9=WLLPqw=%vuy!cX*ZpBhpQqay@28g z98zM_{dTzO8G)|Dvp}`pDex32$Y{{Tk&JWZgNz1ihRFQpVPMeQ25Lv2 zVFGpjBzYMaG&fHFu@mNf(CIKx?_2J2HDWBCp0mqUnhT_M0YvS@U9O6J;QR;bwt@oP zWcq3< z(y}ujQd-{c2ahx(C0Ja;TFBr0AZ5qA-LM`?2PmCE8u%A?yXw?0_J^hFyDXqwl)}fr zpaWW~zzE^Pa?yPjkjkqft7!*sOVg=L!0hO~cj1CM8Hs?V;`_2N|*#`=5 zP&q#2!h<5y2-G$eabRFD^#ldtUIvCc z0n-oeauu6ixYt!p3RG=;4FCm6G`Lp>Zhoy}U|>j}zHzUs93#v03wvEfOnm}j&EIG? z&?X*zkQJcqsm1#k7#Qqdf{rqt!3OH=gMusuRBg^#KV5R4s{>>2^r(HVx`Mr+qq^sT zm81$WFla8GK4YJ&j)qPUsDRDNW?)@4f|Z4FWjp^B+ z18V^#3W)WlmW+_j&3A|dOX-K>;HDg`dt(~G$iOgl9|Hq-ILzS;#wm;p3=5&{Hc;UK z?&;dGGczzS9tH9xuPPaPZYJ?H%Jx5#x>T5yW`F~&|K*|~CXhnb$6e#-t zae?yA32|5<$iNMXc5H>;CuL1iPuX0SVaB0odIu>SP80drv@HtZ}rdu6#)wMkq0V_e=K-;_-nn7vV6f|JF zV;=*|fgJRug`nhASx{O)V{~UAGgmk(pOBl{Q_B%>i=SH!?z3d*RU!3txz7^uTu%)kIT-xA!e_Ynn4MKhHsK$4(w zCIbUQ+;ol;u9{wxVi*{7z#-!X-jL211Zf(02!ZVMmx4A8KryxvYz!znF(8TuSVQwg zG{nCXPPhtdfa)&B7?2y0@++t@0*++RC_5;K>|>^1SgmVrV2Ea;|}eIg&k7#I$MtVja!4~T$@ zs^6fdgxZSfjHg^h%sM$1H*L`nNkJ@qh@H38P9+Q z8KOV8>8z`)5~%jqNQ9ZkU<4YT0|y-}TgFfSc-B>uv0=LOIadWp9|CmhA1G9}gQUc! z$DeZ*X1oECmlQQ%Fgguu^WOtCH1;wu@K0ZO&Q+5YG(u@Q{rovs6{g6f=`!bBC8qP9 zcV&kd=?it;1dv*>=@#c*g;_z_V9E4=^RBAWpdIPp-ajaiz>y%xU~)K#fx-Up^a0TFHUxPn`naP27ZG1vI-0gF0(*=xnE#D zWCjT2CdkFh;QY8J8y>%)R%LGr1A`{`9P$Vb(AbTg0t17Q4kH5txMk!IjW%%1g2Fn7 zF$I!u{$6nPhU8Yzr~^pqHdH3(qN|o9sF;190*TLZ1_skO1_lPu+$QJr^%q@5AsRtL z@F0x=sSqPqW-;+jUvtTokEe`*!5q}WVk%-Nna+R7RY3wYHQ12~F%KjQntEU=Vps!` zm7Jb%$(3ChG|hMbtOPuGWdu4I4xEHQ6P_S@MAIPl%)jJnC;^f&+RDhl0PeWlgvNU@ zRLS2Z%3F>>HpmBGW%!brqYw_^PXp z5@;e_BNO5#P!ax=1zI#SvOyZJ^LiI%4h3RpC%KR*Vv@B=db(LoAb7EjH zo4)g|t2J|UAvi6FP3OJm$_c5hrZ7WmtF=(Q8w(*WalQxZv@L;^ab}^xu$d9cU1$I3tiLA?z`&NgWC8eAVOOZ zGz>f$+--jX?zC=XBZe5I1(5bCL)P}mMJLiXJA+g6)R$3Fb0jv=C7w1{g1XiAR( zw4sx6j$SEfdI2=WvjIHyAE*o}WULt&7&n3W2Hncg;V6(wh!^2g3`QWog4-FewvvAd zWDM%%16M_5P#!e}wZ%Y6a!Md>0TmCe(3b1U5{O5g9=a;kn}Y&qD+2?A(|!hq({Rn+}oPmMC52Od=d(apTYbneIP*Q-6=9q%w5oDwUSQ<3Z zZ~O-|g$@pzXht{iq7P+;ddO^q+Idh4kmQEd3?<-EI)!prCr}bRShEcjN}%<+jMCgj zW(*9LD$qazDTD-)DQKcBbw2~cRIt5KkaY@-h76#U!jN8;8#EZMf>cZo(PI*tUh>FQ zMyGH;1H)&K7$aO4Xjs6I!3Z>M4-VC3P_6dU6(75bO~3TWRYSdYKLbNV86*tAl_SV9 zP%;4P;DHvAb3r=H%{uopFl>Y?W-wI%jjQcvU^oI1V>DtgGJ>^{6QEiJ$|2FU__3=- z{ccEFV>DubEH<;#0F4-f&PZlp_zYeiw6zLWo$7;UH7ZmX7z~P1iy0X8!CPWL%LvrL z_oYMl5vmLfI^dJ=A?g`J)j_*38TFY#o%BjoSdYRGG$&%iFiVwz!4b5OXLC6NgXSC1 z%7kd}?xVG!suht&bwK;qkO%SkD#<~(uLgOqcy^ypRr@!-2B&>@oe3P^B*dV-+g zeWR7I&etAj1Wbc!v3u$&tPJYxt%7S|FajMA4Gw(JA=aRx=pj^f=TlcP;HZSz$zbZk$iM&!XlaNTqXC2IN$3cvDOd>9KnEq@5(Wm-8;lGLpd~;a zV3{aT?Eip8As4hHuZPL$F;16$<|?lUGJO(M(1^iE2i9Y^gK9WA{hXWnlOK5n=*&hnOG^X08Hzg3*A%yahD&Sj3OMc0l8vcH8>o>18yKc5c{bWm5B zagI?fWH2`$JPPik2Ado!R0AJ?ln)9Z&@eQ}o#458Z~(ztol>Xv|>B04)n9fW<-S(Fjzge*)uri-6+PuVDtjklK%sB?b>=sMEk#Sm9zy}3dwg2Y%HK% zhH4jB7#JAM;LF(@z?n~_5mrl^fmawE1SPJe)0e(+HIf6#K`Le=P+9^-v?=JAd{F#W zHbCs+dh4pC4Jtu<8X$f)WH1FSR0mlR5pgMbh!0+Gxq=x~I)RRE)C8Sz z%(xPye|pI~SE&Hdpl6#V1A`-IZRM{f(b?;pzl|kcc zAK(@;7`=d%ZGWMv)tey(o`3Hu3>ixBfF_x^=^x&^YS#bT&%jXLjO1icAvFP7YtDd3 zFqgd1*JF%ko*2RgYFRljn1Z@?pgLs-Ou;{p0unH{^TA>-VKzwrJgR8JMXjIa41`}lM zu1^ct`Jftn8%!5yBnuSO6QH`ZKf;1q4BBhD3YE$K=&A@wm3~ke;a149g{>c5CH+A& z2@tF&Z(LRxv|b;lU6ga43Kp&PJdeDd33T3N?9RDnulnyX3+@Id~$yHJd6jq<0vPKL> z%FsTXkqHa5YZwIW0J=?23}h0Ye*2TFnkcC85!D9wiE%Cq1H0kvltLp8y9 zz7*^pb1mq4F{=X%46EBAegbvlKy6vgMi?K|XabecvEbgs^tvyu?D3YMg`QhjLDQC? z`!g8loa=zKv$ufPTZe&M1)dn*0-i*Ht?=0fo*yaKVqk!82LR`6aOMORlAz=kKmB7c zli2iMUtAUHL6e3R9U!-WiUCl@F=H?Vty%=dUN=}G3e=JXHOfJam-!GOP%qbX3j+fK zsK(m?7Xx+d3>l2iKqU~Bj{yUN-Eq+6l8?cj`V4NXsdq65LwgU8!M^I!0>$w3HD6uT z>zg`ZCE$CopFo$an}XJ1fL!6)33721*cH8?X;lXXhB&AgI2VH&pfea47(mUzBB(?$ z1A{SW1q8@v(3%H#ATcwX?}TLKtZ%LgPM~0V0X7FIm_YkeK!*JROGJT|W}AYRVS=iB zfiAcUjX`TB+@_!T=BmsnH~qsmR}sdC(^PLw2u0)#?>+YYnszn{m$aZfM7LJHmQU zy#Oi%5Y1Q6q9agZnLhnt7?b#P!ym4SvLM@`AqSpW0vQ0FSrTS2Sw21ghpVWx=>$kq zFcQ3)VUjj%K|nN**7W&5T*W=W?YLO*+6D<71_n*=8ud6H(AcXPh_3=#!4uB|%EGNW z&}lx9p^%CmyxIY@8Zu}4zaOreIyZY@L!WEGMhNLLFc?KML5Ds;7lnX)Weh5Wq3akj zf4XWzDy<+`ClWL<5Av!;FC@kf{&ZCWS6Vi`kYEL^mS}@jT5F+|R#)$I!DX&u(`A0a z2DF|+WlllO$^7Li1F=d9))caW)@urVkVxJ9%T)tXt`|aO^7_D~@3h~pn(Clb*WL$n z10-`Aodq|r7#K`J7vg}NeQtWdZ&yo*DNfLOh_4?qX0z_Mt8{(b0R{$*euOcgB+Ot6 zI?f(6qi+M3VK9|thAc`Bg^NKfHFbfO_8AZfMso&pP#wcm#Lxg0F#z?nENV0%d0V)$9O4k2zHHZVXltD$u!~h1!!gD(@AqECU zG4Q&RFW{oXdLks5iGdfE80f;v3JG4&pnItSniv31IG}#P>gl$BU3J+{ zP5?KLrWgKo74`%*Q0`8E1rVbA`v4JRv|uo*V_;y&I>5kS3Q7l{VB?*LP(Kygi&L9^ z_OGj|9QfMx2(W7pgGWs~r!X+6g9=r~2;Tnb0{>jaJi%?bC|*!oE?W=g+Gt+T!Q#vl z8|pQ|i$h|-zFVsY^Ia_1ccA_MW}sD+pq&GEr|183)r5p<1}s5?8n~d4H=hJq>v8O# zt4=+r-1M0Qb~MNa22)U32ufjTV8LjRAT+i?+h0Hpr#7%m6hsEGk_Egv476ivIZVE@ z9u)f}HlVtU!-2sR)ZYOW7P}w{7)=0)WT=oSgSiN3G@_WH79s*^*?`>4VB`a9X~EiOyC5b{jd7C% z*YsDRdO#I0I0P6>>zEiAK-KM6bSY5a7%-TEW;#K&9{&`un?M$Usyzb+Q_y@TD3nzY zG7P3$nHU&Ai=E8Dg3*ko48{kU7#N=IuZL@AV6gkG$-uz)9-L$v!2KSXX^;f|9-IUW z3}8v*BX1Kw0|WEK3H6X3@h5PSNHc(Sxj*xQO3r=|KVFT2f$trgK_P3#U?j-MzyKaG zHiWk9KTMrIk;zS}o^2Y$R10wXenLHiaUFC>15`{vMlDPk80^?U6KUq4ElLcKVq*7n zNGO_vSDD!wGB7|gmL-^J76t}J27&!73=B0!u$6C2 z0wCWr2EoT$!Sf#=|EkS^`1c%(o3Jvdsctm`>|ap-$OzQ+2Bi;hD-EQ&a0X<@q!g>0 z5G%+VEz=EI-7M=BX2aIt#S4PwVCNda*5Jj1*Wm4gyCf0122cMxXdy`wSe9vGfF^i1 zR8w46N4tWaQ2NR9vv(t+zU zP!xcaNKJ2Ka|?m=WjUbbT_Q+KZ2C_&H)U2(xmz_|k=;#%3luPxpaHk})9u;aq*Os{2klY%Tp1(kdL(-*S4nbm`K@7k4v?x#5payY{-a3!NNkAXoQTx}c| z1kZFEgW?yovZttz2$K z^)~ZBhf*;xFvv2PfZ_~H*mZ+OFrR^znlku+Vqwn4MX>0623{f>4T=zO=(L5GLZAUsm+7D_u5ZBS-LvSg0PUE6D+D@Y4b=Eq0BV0SFfbgN$Dj|LSCJD2 zEpONlT0dX}T0RSkByiymPRFpJ9{%~$8GV_=rmyC9laB<&g2sGEB!LQD@E{7P69^hM zwSh}8n1VV+YxXlR1R%t~W1(O>K)oTb9U%Kbp)+khBy=oz+$15bSWRe-ISZ93<#7|1 z1V!}&h=HJXfF~nlTHycu=?i(>BppD~LJPo-14(B?K-ls>JH#6U~@ zK#4DE`Y#?>DtH66e&Pa%!z_8-AkB~^5RD-7S)sEMJ0L<}^FhbQfx_q_Tnt*VrNB~5 z1+;n2u@IcTJU|!YF~)&QB?bml(DXeh*kl%hy#Y3J0kpZJ4-sRuWH17qwF(MJQ_w0V zPym)Jgt(KB&rQ*P;eG~&4v1o~0gBL;`)r69Xw(^W%>~HMTfjm{IVu6xbO&9K3NraM z)a1#0Zo*pZi(t+IdE-DlSS526ki)<=E zSz!)X8e|YCNi)vzTnyU;KSvbQE|M^XHKpf)Ra(}YGB7xRW==r68W(_12Jrzc_+`-E z2b%h91h*wXQ!I>g#FxNotwugjt(6Tos~Ox{=rLtrFam9`UkWNDlo=QpKnzpRgfPfI zOBRDe4>V2&>Ue^Lwl8MT2cJ%1#9#{A%L}T3PD7M|qRyxiR`GxaUqI2pv;-2-s|4JH z>!ZMPV(@kqgI&E10|O)YdPxS*(tgG{OP9cQ=Q4uF&KZL=z*Du1;0?Bn!8+}r5gA7C zh&y8lq!MKYZw%jV%D`X=TI1ff1ng?&qBWpB-Hb+hjIpf63>^QZ7>q4JtNCX`G^_g%6Z_fk2g0cK0M4|@!<=eg9j}Z z1jU3OH>he~VaC9q4?0Pl(VrWXw?H-jc2E;90Id158MI3Jy9!nX!G}@6dw@YfmN!kv zO;Z9i0^N2C zF0(*M1!Sz`GDy|2K*-Gm()j{S<$#q)KueF@Wsva!CSf-<@SzgD({+VmMGUCE2bptZ z86-w?gx!Q0A53o$c9Uadnm%9HO%A-AUwS#%&EPH#sI)Z#73d%rnSxGu0T~dv9AdyP zVK?ZsMFzBtnE;is5OEXsUH~=-(&_}&N}$qmGgvGNR3aPz-G#W1f#D2T2&qK43M;wZ zKuzUZ0kLnjh?|rmXx_{ev}_1uoZ1SITS0SJ=4z0YjovG!skn(x|109g2`K?$p#?+} z)DSIEH(`j(5va_o71Mo0-6EAiqs{*y27(5(jo^#eIG}}y=}L$@?utTNqMj?k)`L}R zL5G@6ZJ??fRzikbG{xM6BtVXx3{ef5+lylXFT>ova+->pgqS&l5$Ntqa2SKGkOhVD zyOp5RWi$*yW7}-2K-NHJ#Xxy^BMSoq=;R?OusCQ@8iP4#B8#br!EV(w6*nniqc1Sm za6ng1mQH_I$|N>jR@_aPZv$vd!H|`K0aU!qnQkZUCJAXZ#z7TdhA6HUcN4A$t?qt~ zu*kRqst?o)0+q)xj0OyljdpfFIT;ujSAmPKbD&LAbGEF56<@2s#g`-KxFm2^Tm{}@ zlVr}opn2Arfq`)in13F`2cP({mJf7(2&)A{00X2DUI#Ak7(+B`Ktq6q1KPLu+6qN1-EW4r`_d z{&p3cepSLvEeTYZhpa)E{GEY;0n~srQUtB>2ZbYOJ{wd4*F#mow%(XlK>M6C&?JmN zoo!Hhums%&cX)cNq?-!k3lJrvYpTV>0G>8yTnn)iHf?SMT1Nr$5_q))D1lh4h4|!w zq?@oZ=p+XpxE2PZCRi4l0?k6rP}SN}Zo*QaV_2pmRGY2^onD&2z_4rW^#6Qrk}{yV zB2XGJdIB?s0h(19*Fh{@Bn8X)pmQKW&asEeJdkpeG6$uZ;B_z`Fo36qKxwTIE(RLC zumZJI3>Zv7*G_|`j=QECO1p`G6WlzwLIz{dWyB!OpacgB4se3gjt8yNaRLn?Gk_)! z8RrD7XJF8I4O)QaBns+UG6sRW3Ls%fTL-eY%Tp9I{8eCqw0r_yZkw-XV9=X>MA}Uc z>;^I!;&xL|9S=(7 zZ$M6D1gCOS(DvdzpmqKmAR!G}%w`0uzG3_8yf;9WTt1L-Q-c(Hu&mIu0o)#(t}W{( zqzp>u(~!)uhjnj2$r}{EXE%VBf{0BolXVkv5pZK*cn(z!E(1WzX-z?c#3v3gFfeTd zyN9_HTz`Y4z|->J)C=1!;JFc!$sWnNDVc*(Z!AO;s3-;3GoUnDh!8UZ?Gpf-Py$WS z8#h9dVt||*bd@Qn*$Q&%N2tsMIX4;QD+d@DST}(k#8j%lV00Ijq(4E;vDpMM=ZTz~ za6PD04S=a;U@#SBW?%rV!AyaPDKMDofG&<&!obi369diQGQtuwXv`Os{HMWX8H`<_ zIzTBH99-Zc6FgDk2ilt~2Oc4jV`E@pV4RaQy-MCq#R;5%OB3S({ko*U?=?~=HL?b|Hir1QfL9-0hRZ{^gP_Tv$PbBSt zHDXLbJG?Y% zCTd~bPR2x2^R1Z7_YXRGL32GnnHjvXm*&I|*g3c2I)%&1Q802tiuq@o+ zMxebSU@P>X#dOd%NSgkoFbrJwU}xMEAh~28O**HK3(| zpgk6E4lpoWgo&{+n8vU&F#I^cz`!_tqKca~q@4Q+ZOmBgfCR<^6*u7kP}cO>0e7LX z3>(BRs96)VW6e$qRM6*w@&$t(c>d?l4#>c6F60a@(D8z&r#q{ZSl*8*cZ6n}LCG9@tFKvSY?MlDj}7E}*frd19cfx)Wq7c*JEMr27=C zuL?TJWq}yz)Ob*5WD}^1vk>eAMjL2n1Y`=tezQdk3=E)Jv2iDOz&)FRal06(UnA*e z!@$5`{}Wz**3C5Xbb1YHmj1d!W<2;E6HN+IG8oJq89w zNzjRu44_U8qXH{5h1&`L>gJb^}#q0_Yd8g2^pphKr@8bA}mK5$z>y;8m&%~#M797$jWpb-Pm9zMo77xyqQsC$C;4JV1$ zgGzikTLuQ5NErqO#w4&!jKMl`AQvTxgOoCcxa5Hpr$CH>%pRnJonUVZiggCY3~^AL z2iZc)`RjXNkSyRSd=>`l zzn~r2g~oef4m9D}%fR4f2D%e1hZ(d)&z)0%fdPbBecVlrnHd;Nr*mt$N!1HEF))Cz zySF(50|*PKc)oXJU;tr3MJCS`tPBhwEXc*=E-l5t0K!7|+&AhlFo3XNuxE@W0|N;2 zY-M&&c4lAzVZqJrJ8c;lK$zXz{k;eS0|>L{dB%D$Fn};m6|?&cP6h^L5FxnDv)hz` z0fc$~Gr2DlW?%qe_EPr)?hFhErXSaGb6`z30G;H*qwOYF4?1lggaxNCy6@y;U;tqO zMfW{U3=AMFSmC+df`I{q`6n=WE;M3b0AZeA%gi3pRT8^D;1iF#mie&-(Xr3=AO5d4$t*zZwGr2y>S+dQMYj zU;ttMP9}E^BL)T#W-oF-#lgS;!tB28whjyoAk3cYuH??Z0Ky_KJ*`w37(kd`gUK_> ziGcxxdAgb1uZb}*fUw95&kOnt3?R&}#^hQ5MS_6=g!z@3JX2j67(kf6jmh)3Jp%&> z^Q$s>g3cfZVV;@H?jBMM3?M8x-(A?1fdPaCCwqdXU_h87gVEhfoPhy^1=Bq(wHX*d zm@|#jv)P(~0fYr-GJ1k8?EzuI74?js4t5L-AS}3(5p)(0IC*lO=JUK@$iM)?Ji08N z>8cD2Aj}cO=vl1KzyQLW0i2$8$_xx3%*Dgz3EHO&!d#cwJhN387(iHX0i)+Na|Q+w z7F^HhSt`xI0K$SjjGmcd3=Em|pesJQm_2=j85lsA$BM<1!i{!0|@iXXZB1mVqgGa?kYx40|f>K z5ax(w^t|oHzyQKLOPDRSG2bio*q!`&H`q!7#dg@Prt}iCd_JRU}0o1-BFB1 zbo#0)cTpAtOEcr?8>`)=rVI8|fQ&Vp-l(cC!enSLUBN6`bhoUT~wF3D&*U9jI*l-a=40PF-7Ljy~L>5dIx(@jjFHX0fjg2k8(4a}hG zEzQ9J08(!ORb^miHvJqxY?r8W=TTrXW|*!U=Po|ocAh&A zlex)s?|JSPOy-u;-zT_=PoD!4G&P$(KfzUO`hj`wyo|=v&&_k!U@|wI{$rl|9A*Ox zhUw?y-6f}QnC~9RXgvLOysOf5odxa+-bR)d4Ds=9p?=OGp8kIE@hXM}#>STDLZ&80 z4Ds=4rFqF<6=p`p=qfA?OsB6;bd}CRGt9&kWIkM{DW-L%mLTikD$EQ`(akn9G{X=w zF=CkhzrMlP0-)T3F=_?nyD>50HPQRb% zDl`4XLU&#jR4U6tB?!3x|=x(qu0|~($ZeeCLeFCSu^z_a} z?i%r+0D?vM93=J%B=$ih_HiWkStRxqB=$=fn}vaa;oJ1sOCI`?+Pnz2I3Tfo zr!T$ap)6U7B-Dk(o<9BIC69Pd20nytQ6#n!5?ddMZHvSXLSn~H@4W1x%-BAC?PU*f z&lN~ATanm@k=Qqo*ng1Ng8T><$xY|I;vp^xx-$b7_I^mx(bH|OcqrF5BMHqwVlPEv zZ$@IDKw@7(Vn0A)zd>UEKw`59AY3N^VMEfQ41@ztiyBC56C}1H65AJvU5vz@g2dj1 z#J-5czKg_uDFC{90GinUAxUsgFTLtvE$It7B?&5>gv8FDe)6h^vgC9mp`A$VW7Ao$ zc_>T1LlR;Jt-XYrBrx6anumD3Hj+>j5<4A=q>UOeFSFVWd)EBa*~kB=$8V_9G;= ztq39=1tGDskl1BN?1f0|bujkytJgie>#al)Mg=3WBaztgNbFQ3b~X~b5Q$xm#I8eP zcOkKNLfD`INd|^v5Dqx`Uq)g-oWA#lhq$dU=)^o|9LXWEHIdjRNNf)zcIb4$n;y;e zPmzS!k{659=l9fZV=Ltx-PhWe-!@AxQH2(l~fjbgA6p5XT#4bc)*CVlek=V15 z*ej9P+mYBuA#6}gGca6+aKI`3ArkvN68kR_n;SGT26eO~5?dXKZHmNBLt+;pv8Txd zBZ{*{ND}Li*t?L}pu6p1QE>@L{2mhf^>oX79{cMrfkthiZhVHs{)EK-hs5TRLpVhY ziLHdh)Cr=}Z z-;kUB?Y>7`eJtos9;kc)61xV8-HF7WgT!8e#NL9$K7hnNgTw}%^#+TZClGPaX|)Ut zKOh`%Ah3W&QK1eJKw`@vu{Ds`CP-`tB(@I{J94_^Lyyz-=Aa>2sL`%SY|ss8Fn1*) ziRUA+YmwO9NbH$N?Bz)8Gf3S!fkvsJ zPVGQqPo4htk%#qko5vnJj31`kKK8JdGy+|;16Asd#15H0@v%oXlzLhyip+08}F{5?c|8ZH2^kKw`Tgv3-!(K}hTfBz7ExJ)QZv zhirWvgaZ!u79@5T5_4-z{ciCu%l?m}YEKw>XLVsAlWA3|bZKw{s6uptG|8wdv+F29i2 z9H6ZyP{)ZOu~m@Rpgp9pjN^bL?uWz%4d27mWFd)HfQ}Y`NlZbKScJshfW+R1#6E+> zzJtVn0PBU9F462HoZk3kg>w@gO92ED}2diQS9Do`J+( zjKn?yWrO{H9?Ajv{}mGZD-xRlG@A=`s5BB=4T)`p#I{3X2P3f)kl49;4Ab-9cw|bd zf{qD;8g7NecAx(7jfXX3=XBk-9^&;2kYqL@v9}|!_ad=Dm&3xs@FbG>c_j8#B=&72 z_CqB03kVxDC(gj|AHo3z6$2}1=MU7`+(>LeB(^vbTNa6}GF|YUhj_g+l8`?VI~s`% zni+)oqZmoN9*NzJ#Ga1CUW~+EkHp>$VS}Te;W&f?_S0n~_I)JwYa}*!#}m}w%!Y^t zDL)ch8i}oe#I{Ca2ODN1H0K~mlq0cQkk}KD*mIEBE0EY*kk|*1*k`9teDCqT{*n>G z$_Gg7cS!6%NNg@+gn9`iwi*)K1c~j5#12Pdr$E@#|9|j^5xp?a%8Y^ZoEhz;Jw$H34DvRH8XyDuK%^-!ftK+;g9>p^U& z_+BLTVGtXt<`jqxy7z^Ff#Dp;I4JujNF1u>IfxAvX9L}e0TmYnu|eyV7#JApMJ*T@ zgrOV-kOWkbHi!*%gaL>R6}LlT`y#O;Ky1*i9tH-67?7Dzb`eM%YEC(b4K=3`#6HiE z4NjnKAP!VRKN5Q(hz(x!#K5o$iM<(#y$8fT4>pG3K8Ovq;1!4sIzfVgf#DsiGbKpH%fxoP$N`8Y^b;vH31UMX z)P%&I0%AjbKNpF;42iuS#D10ysjwu2;~?6V*? zG^np3vF{_XUx3(9gT8{;P`#p{d*h&NQzUi>5<3>ou4iB<263R4)gZB3k=PSJY^b3d zkk}WH*f){b??G&+nLm)&jP?u+j8JhS5W5~~s5OWKW&48IP(@)#?06)02Z#*~-hL2U z0}`Z@?HL$^q3n4eaj2RVAU0?hAp--$S`ZtmrhXd|=M0DqwfHI$`yLYeIfxB4=q-p1 zHRu}>TNHFUD%4^H5L+AKI28v524N^$A0+;a0dzDJ1A`Ta15G&gAU0G{5Qq(RP&|kY zH8cyv1|1j;x_cXBsP6QAe-V{wCrBEqbP9+KHF_q94HaLG#NGsAL)B~tv7u@Xf!I*- z;~+NF$_q&BXCOAziS_T1I6sis+@NjoP|YGpY%LHQs@WKcZG*&i0q9HkVvqz>Q5}d4^+693dm@Mp)w~wOhN|BIVuP;eWME*}12PoKJ`NIx zs<{MWL(RMnVnfwDbVQm0c>|IF-JHe1!0-WNkn!}q|A-jkc0x3FB$3!EAU4!&O%NMu zrz?mJH7*i~U4g{z2eF~*XMxz@4b=<`^PCtMgrV%IES`d}Htund8mRiKNbJW*?2kz7 zKOi>LZH%A|i%`ANAU0H70mO!iYk}A&ArYhxVnf|f?~KF&EjVU`O5`AkH-XsDl+lgE zo`S@l3t~ep*bibu&3Ou9Lmlw}#I}Gq;)^o_gRliOmHY=uKoxO;Hqt?TzzIG#D=Qz2eGXn76iL6FbG50aUgN1noJNIYEGUDX!8P8q7q4>4#b9vcY@eZ z4SgUsRD33g4Hcg^o$*+-c>PI`5Y*25AT~76ULdhQBC-F1*iiL+p#4x#qa{IX(EbR} z2^pY;#!$8fNF1uh7{rEJZvkT4Km*eQ#DOXb2C+fAMHm*-0RAsG3|58){Gy zhz%8QL}E`sV$TAx4?_ZZK8Ou9bA>CY{R-vm14%%Ae;kQ@0f~JR#D*GlAH;_06$EW` zfjUA0#CC*OCgaAyAPi-zgT$d~K*tM!yP+uz3=Gal5}6=2)MqsyHdJ#1)F5jH28K?M zIMkpiAU0I}Ob{EYek&6D*z~*1p5pcIkc3!~5)nU$4Qh}xFfa(aGcX84*>WIps5KfO zHq;tj5F09Pjl^~Zu|a3tGcYiCf!I)Uf+1{hONk*9#DNBK5fZx^iQNKXLk;Qzv7rV{ zMq;l7v7zRGxAQ>RyOG3?fY?xTPPv0(8fwsGkOY+d28sO@iTw|WEdshK8)|_p5?c+4 ztq)>DEi(nNq2|ZH*dYI>!Z@G}#Bu>(PDsG1lM8+7X%0|P?>$Q&qp`V=-q z-BJxw1l7=q#GV3TLoJvIVna2rMPhG5VxIu9p@Do6iG2%+{Sd^4+ExDs#DQ*W_yBSp zl>Hkd4pqeFg$N;T5F08kiNsb%VuMbig7rVlLE=y|y^+`<5H={0FfgQnI8ayTBe5%x z*!3Vb)Z#V}8?=v%fq|jRi-AEH%AN`mhpJfsVnai2DToaf-;BgQ=mp9oP|c@65>WO7 z5F6^Cmq_eSNNgT&1_nl`dQl{{CKB5L#D-ez4q|(QQV;`!w>JZWFo+HEe;7ytswfe} zhPpZp#D zkOWlGH4q!>h}$4GRQxH34LUgtl&L^$sNT;=Y*rschlLM`Esn%i0I?zF$TK*DI8Y1x zKy1j=3PX?&1B0;N^nIL&oSF-ghAOQ_Vs|33mm;w@Be4&G*ifU{eG!dGArRXi5-Vc9 z3=G0hwjxLzYFE7uhyx7}Ll7G(VFO}A#T`LxsJIV^4Hb_tiG31@eILYzI_L!w`y&$j zyB}!G3u+L9KLZ0Jlr02eLp4hyu~m@RMj$rSakd~f=tLz31_noe1_og$+Xo~LRTBMX^ZiN+fm*hz<33Cx{KzI|+$B8;QLU#D+%DE+qCz2piO}WMH@p;y?}h zhQyW(MEFbv#0H(~!N9K12^^z?~*o)Yz-t6f0z2OvdIb~;EF z>a!vc8>*`u#D)se2vPa7f!I)waRo6j2!}H;fKJzv1BpL^_HC3w9H=5) zB(@<`185hyD@Yt_u{VefRqqc~13I}i86*x>lL=x&)#O6eTn3d2AaSUg_8?F>1y$4y zRb;@(z%U<4(NYi_s%8U-4fW-25F2zT3U_7RXc zRLyx18)9ZX!xaz*D)9)3{S(B7C}Q{rVnfw%h9DA`BobQ=#D=QT1hJud^+0T>xFv`U z6}JPiVPo^2AP!W*AH;@g2m`S}$ESe~{0(7X5Qef-LE=y~1t2z5Zz+fk6>k8sq2jF| zHdK59hz%8=S`XqtB^D#G*MZnjMVmovXf`_vVnfAGf!I(7T}EO*1+k%N;vEwEI})2G zlz{Z3hyETI`F&4g#^EdSgLssG1}Y8!Day zVxNGdvqBIXYG!LFXlx$J=|hrO0%Ajbuoj8E4T-%U#D*Gr6vT#_a}J4p9f|!G#D<#r z4bHA-VE7N`Ffg!&F)%Pf4U$7*t0S>(L2Rf&Zb)o@Bz7o>4K*hZiQSIGo&aLkLlrFp zaiE5-M`G_lV($a7q3W+Av40@3dBPDMPy(@`QJ@K8$3vn(H=Kb%7|O1<07*aiGX@;_kki@Hz*b_l)sAo2T*iiMmk=SQJY;kD$e+|L`JMTUc z`x%H0b;Mf`I}xme;UmZqQ1%~?I8+UL1fp!<0kNUtQXn=|y*7vq6*r0imH(jgDH#|T z%pw>VgrRINkRoVG_6M<{8e);yIY{hk5F4tu9%>FV0|UckkT}$w86Y;)oW&qENF0>^ zR)RQC&1<2WL5@8L5(g<_U|={7Vnfy3Mq)ofV*diMp~21^iD-25AhCr&Y^XWXk)ZM) z%FzW$KsB2ovF(xAz92T#2O%JKG9)@8A{iKjq3j%xIMmUFAU0He0}{Ij#D)}T^$ZI@ z9H@q+AU0IP1`r!6z752NT5uY~hN`&)VuOYU85kI@fgAy4zXFLv^}YwOq3Zu5vALo^ zX$2Ji3=9nXAP!VBs1_7XVPF7F1*n6>p$3^Fv28(YsCvgJ1_qFNP?IneBo0-dip0(a zv7zcqkl0=IAPzLxCnK@vAhB0~*ig;;Ky0XQPJ-B}kSI6{as-rp10)Vr^BBa2I_L$6 z4Hf?kVm|`Sjf2|fAP!W5Et-LW5o(YW659lc?Tf_D0lPCGF%tVFhz&J|DTaZ85z6L9Vk?5! zU~|+N7_{IV1_om!wgZR_)f_TCP|8!hz6nWaGKdZJ)GQD?9TF4sVi*{Nq3o3)aj2T@ zNbEx(Hq_t8L2Rg+OCUB>{5psY6@LU`!y3!aK^&+B|B=}Iv55YM6o?JFGlPMFK`xeo zK^V%`1c^fpH36}qmRW+>P;nO!8!GMvVnfA4V?kSSL5sy07#Jc!hGtHWlScFkOOVvo zf!Lr!*cccXnn7%+wjLz*A`lxK2@DLYk=R?1*atyusNPdZ><1t=RB!!DB+e%!_74yn zs+lK_fq@aq7DZxfgV<1mOpw^NNNi^i8>%-PiJbspLyC|x5C>{dJrcVEiQNZcLk(Jl z#9ocWJ_uq%%{hg{zKq1a17br%_hlTY3WFN@2_yk!bHpQR06`?S6cSq##D=Q3MPj=l zv137OsDsjw*!eIv$p57v4%DDdB=#gE_6iUiYS2a`_AVs$0T3H%&PgQpZ4eu(_X!gF zZ9J$7gGz8FATodmhz+_@3v@9^0t16El&uUBhbCw}5F47%jX`XvxFZtVABi0WVnfwu zBG~>6c_0o{b0vrkRa6IJL&ZBl?5mI>q8G%5)PD@~L2Rh{B_MXr^lNgSa`g|vY>4{L zAU4#Ke~{R$iHIoX1F@mzi-Oot4{IW^jgZ(LAU4#@KqPh)gbj*R28IL>2Wn6w61xkD zy#U098nhCLy$OlE1H^`!a}$aE2#Ngz#Dx z31UOdX+mOmBe5rf*ibW(f0(z1|2-fz`*b#iGe{F%Ki)zhpPDpVnd^n zFB#OjfJ7gtX#|^Cl0y<#2C<=f^+0T>UgKm?qJ~P?AxSuc*idml5F4r?7{rE($AQ>T z@njGiDxL>oL&b|hY^Zo0hz%8Q2C*UH^$dL=4pd??hz*fom9;SXBH3gSQ&{Q$8qK!Wryhz-p_Y$=FrF9>2o zEf52-q0uCd#MVG!+kx27^x=-g4yZ@sM1t5*i*rG2sG)sG?CD7CwIDXs&}~TU{YdN+ zAofLwXYPR5P%}S3*DN z149Cc4fRb4hz)gIEfRY&hz&Jp4ibAQ5_>0z4b^)YiTxaj{TsxdK2fAxSXDV4;eK-@ zwl@+xe)>WcPjS^=B%$RSI?AhDN#*ig+Ukk}WI*v~<1sNN4q z?4L+%)+~f)v|wzI|BYcB1_lOC5F2Vx5E45YiJbvrLmgCz#BK+%p?W7Ev1cN&7lGK& z&|Q%QD*2%XodHQe*;kR+uR(06pIEq0CP)Hm&?6-FYb5p;5F2XHFAy85*SruBLNQ3} zR3vsD61xS&2H6EFmwI6w1_p*XNbIE`Hq^3BAU4#p-AL?E&<0d z!=WMu24M)hp5X>a0$TXI2C< z2|{8=gV~_)XJBAR0db&~Wr5gG3+j;AlaScUkl1@bY^b9TgV^N|M;|X{U=W6~FM-6N zYVLyAP!B(<2XUYhZ$WIR#3v9ND*gw=23?a4IzGIFfq@ZfC>IhN6r3<|O^`U$$3{qO zM`agZd7-Aeq8mcrC#D)fP9*7MU zuK=-cL5!#cv7yFILt@WIVs8bpq2aL)iG3W2U4H?@ff{-Z#D*IB1&RF^i7i})sFq}q z*s4fu2M`--P9zdL35i_+V#5m8MhFM&wJs#~JP;dd&?Y4IQ6%;`B=!>!8|ve?NbGM& zY{7B{21clvYUQB96&k#{APLZw&M{Ne8i^ zYH~nqsCX3;yA{L+sR3o~E)WN*Xex*el3-w9m<3`(+d_*$Y^a)bAU0IZ77!ci(7j0P zV@T{fAT~5qo+7comV*jcsDwZT0|O(}AW0;)K8OufV}ZnWL}I&x*igL*NbF1`c0Gs< zHKzl?u4kBt;4n-Fv7rX7Mq+P4VxI!Bp$1(>V&6exKLW9#=6pqBb5~ch{Uc!VmE-;P`f50vF9MMH-Xqtb9N)Kk3iU2`U>I7=)p0 zIgmKi0!1|9^5K?%f$8l;WHHbG)Lg4htv3|>g= zWF&SC5_3!5>Q9XL}IT% zVy^?Sq3Vx-*w8pW4`R21B9DRLayU+*NbH$N?43yL%Si0!NbFxoY~~h3)JTHZP)8_1 z*hKMt15F6?U6(qJX65AcbhU$$* zVrPTc(5zbqVt0Zfn1P|Hje$WJ%C2t(NkA1%0I{L@dn$+x6<>_R-iXBBkHkKU#J+>X zehp$nE#q!yU|@u@O+f5t3=pr`gE(Cf*EzQ{FbH=|mvcZGApl83-I9aEu0mpWAh9Qd z*ie7W0I{J)uR&s;2eF}MUIVeaA=cjlSr28`e*j594f+aVLp3mWK%4Ij3=DiAHdGC$ zYG8zFmH~-F*{VovYY-daZ3Y)4b}$k<0mSZxE|jf=aKO&%L1HgJV(&y^p9is_4!s6q z_kguB-0EOp5QefpfW)DW{t9A4)iZP=YJJvDP~`}f5I~X;1+k$9Np?aE1ua!n0*OP_ z>w?%&3yeT)sCqXfc03Zh7>V5sV}lB(9vFv#fnh2Vdo_p+4aO}Pvz3kf>oE(Qi+DBBaH2SkbIgo>+x z*iZ*)gV_BLkLhYx8W#}zI4Jx&|t#D}}#Ky0Wv{YdN?NbFT0HZ*iMBeC}& zv5$h-P`BLzv7u%@Mqq$r)b3-^F|1wA+v6Vq=sG*u5Hq=mCB(@t8I|jst zIy4oDorlCO2eF}McK3qH7^tCBKoU^)Di9lL&}Jm|9whcr5F2XHX%HK#_X-mGE)x4Q zhz&LK4~z}+KX)HED8RlK0kNTmDuUQhL$#3D4j?wvAWtNA5E45Y#D;siCP>JOr38;e!QYEU(Z4OPG;vvg*ieIf zk=W@->~Ggbm4mb3q)a1yg;IL2Rf6*O1uXkk|rK5FSuPVp|}wy+CYe z^aV}h=2t(PKAVtu4%>%Ka8tRbPogg+;O&^F2RWlRBhKkPvv7zEC zL2Rh_IuILV7s&scpcZp5FfbegNkA2y2C<=~Ihp8Z`+>?0h74Gl&hz)0kNSDJq%(`hlJem=?o0QAU4SVmp~Fw zMR!4LsBa#D*ii8gAT~$?0|UcPBsTvHL{gGKVk;uC)j@2iUTY+_%M4Hx11b>(l7NOp zG7>uniCqL@L)Et;u@{5bP=~Gpu|fBXGcYi$o58>!3}x>Gi9^*K0kI*TtYQIy$wK|1CY2e z1+k$T96)TS23HUp>YGR;b`lah8;RWrVnai;3yD1$i9M$t#DQA80mOz{uoH=W2#I|I z#D*IB5Q+T(iTxAAhMFloi-7?YN+7SPAhE4LY;kB4!x_o}De^&Lhl1EpgOWgOsN<@U z*eyux1xW1uNbI{v>}N>qAG1JB45)7yXCqQF7ZO_-#D+RT4a9~U6}hDM(chz%7F2eHB8^$ZL#AP!U_9mEDpFfinR*ii8*Bz7x^4OP9$4fWY<5F6@&y-4h1 zNbEZxHq^|g5H_g%V_D}APK0U(~#Knk=UC-Y^eI{NbCnl>~A18)SUlFY>s(|1kMLygUkW> z-yOt(CJH|gdmcC-7=q?8FbG50u^@4%nhX#dn$U7VY^Znzhz%951+k&xok;9yNbIHa zK;=Kwf|XFq7BDg}Y(i4B7sQ4ddKkopsy~CozKXa z4#b9Peu%_oSir!*2o)DbVyh#ut&!N#NbD3Oc2zxy1NA{O61xY9Jqg5yTDBC4y%ULj z35k6hiTx48hMNBiiOswa5*?uQ$G{2VKrN6(VjCc_Es@y%AU4#{2qbnQ61x<{hML)l z#GZr1-ntM}{zDb*Lz1`xVnZ#si^P70#C`)}L-lejLPUok5?dX_hMHr5#I}U9>lqmA zK^&+-Nl5H$Bz7Z+4K=6>i9H#KJrl%+nzISShGxILAohGn+B&$1fk7C`J_8c>getlY z;y|<69S|ET{tCo~YWNLeL&ez^GcYhNfEdcPn1Mlf!F0Pw#H@%aNE)it0K|qGZ3<#T zXK$TBY^b;whz(UA2x5ayPXcwjKt@B^2_SK(nrsjosC#D+%17bNyy2pgQ78JL$aFfc+bmH@G#u9F9`mp}qdc?ko9 zFqEwa5{IhsLSjcCv6De;sK+uuY^dILB=(#opy~uFu?!>uHFPbAy%b{cMv%o&_8yQp zRLyY^8*0HB5F09f9mIx;-vP0q;?F^BsQ4QY8zc_$|921vD#5xG(Lm+`u|bL$7#Jjx z*eW14RJ|sM4OL?dVjqJz+5*IeI@%G59S&kcqa$G{s5*giGLa&4e~}}MXhy#`)|jHi!*1zXXY0y8=|5KqZ<%5>OxXAh8#N*ibcVkl0(1*!w_i zXv%*LVnfaOkHqF!iSU3Nhz&Ngo`FFf&S79MKw_JL*ieJKkl4XU>`V|FY!CxO5fZx^ ziQNcdL(Q3j#NGj7*Fz-^f;dq2br2hB=mRA7OCBbCKA~kl1@bY^b3}k=W;u*jGSosF^PyY;gKxU|x-w-{S(Y zmqW55-)aU1VJKS?Bn~aY#2U_7o)cTqO2p5E~jQdyv?tVQi59--0+$L%$)h|0A(Q*Fc(o zpm32xV(TKY9YJiUIiX1GI3#vD61!mysQia&n298@2#I|JiTx6Z&9s(*ff1^g8;Pw5 zVncnbg~T>SVq1dP5WV#bz6cIO7!o@N#D*GFio~u%Vz+?U5Q7+IAhCBNv5z3J&myrO zgV?b0{|%S}3S0(;uSjgBbx6KMVk?5!P{(N@v5k?~4j?wvaUn?TA|!TqJrZX=5_>C% z4NawcKZ0Ub_aT+hJ3 z2sKn3#D@Az0g0`N#5Mx4p%z$x*igNWNbE2W8)|VZh`kEppv3hI48l-$&U#S!4^>nS zQUrBf4TudDZwIlV;yoZXRD3#!4HcgQVnfAOA+fiD*ibdQKy0X*qaZd|yqB)1_lO3s5loATLHv|hMXo6+X#v617btp-je+IFk z;y*xas5tXxME`U-4ULX9NbIdh?0q0M!~%vRAU4$evqY7c)J@>!(7+KoK(!iM<8H zhI(o*68jhu`!a|PwdWZUn`IjV10z&i28peT#I^>p#i0u%T_7Bg8yI|%*ufw+)Swt7 zb}ACP8pMV=v;~RXi^QG`VnfYYhQvO-4OA3BB|acY@NGxeFvy0fM(SmkRqstSxD@qAU0IZDi9m0W($bD7h>p65F2XfAtd${5F6@&yGZP3 z2zEWgdk_a|5YtXXmw*$*-T<+HcP9gbFqAC;5{EiM8N`MkWd4$H$gn6wTpp47|J#U ziNkh}IYT)hWxgQxZV-!sAqd2VYKTT+7lPPO$5kP*n~~T(AU4#TNgy`VoJ~mV6T6U_ zf|o%OTObx+2e}l=ehU(Z2Ky%v8|t&aAU0H-X*VL>@PgP-aUl>Js$K@f-UTsV5yS?Y zU(di`3g<8|*deh4Ky0WlBazriNbGD78)|4Bhz+%@6U5#Iv8;DD1A{P>y%;18b=(RN z8#c1M4a9+JJ_uq%6&(Yyp_;FQ*ibc(K-hH|0!J2! zt%bxk1+k%4IwP??Ky0X$K_K={h?U_WHq`nABzAonhyx9@dL(uS61xw?hH9RU#9j$v zL-lS#V(&&`9|5tUj<^eALml@O!Uh$m3=GP95kA%jvF|}#Z3$vSHMk|ob zxOO5*>_uW9MPi>sVqZjJUqxcyL1I5ZVn3g*TjD8R{~1Z>I}-ap5}SEHBEq?m*!)Or zaU`}h5?cw0t%k(bg|Md|F7XtUw19BH0d9lDcAowgHYdm|Ei$Mn0Up5paKkc3Vk zvCkv1FC(#UBeCxzv7aNcUn8+UBeB0DvHwHZkVMaX04b7@*!)OraU`}h5?dLGt&YUj zM`9Zzv8|EV_6LxPV0R=5ZzOgw5<47;9goCLMq+0pvGbAGB1xP?VxL7~UqxcyL}EWgVn0P< zzeQqyL}LF$u;m&4A~+1J2NCIj6U?4IPr5j}-L%qkyJ@ADxff%>^xVT<{)`>d_kyS? z(|M10l`}4w-g?B#pXmkT^lL}F{1{uNs~+|8XAGEL3Zj-wKMJB2Ocy=o<=0vXL{%vFMp;hoYR+`@$%z*z{$)2y20`C^v3O0^3%3ku}oJu>!re}!Ntq~I<@%n z^o!fA9QSX(c~>%{ea(Mw{tZ z&w2SXu9&WR-pikH%kWYaO9mH zcG1g^(PR43i(dYWA=AHtr~}hoFM0Vho#C54?UI)tBggcom%xE+dfCgL=?DMxw##0A zi~`fIUItsHdd171@x=5}5LGk%D2R%fE_xO0@Kg}RF?}nDVwui*4HP`G)5ETL`7w%2 zUwX~UpHX1?R}hsl-SxVcKjVSvQ$bY5^rs+7WV-1MFMmdz>8&8jW%|_{pnz1Fu6EPQ zkFjHV=}oX5M?qA=bkSSj#FBc;%b)3v#`JBsy!;p~rnBA#+Yt()rc7T7qIjl%1yLf? zUGI4LGuBL>3Zhu1KLt?&(@pPs`7_E)Zv|01re6h7N2aUZ^YUlpnO=I&%b)3u+4N)g zy!;q_ri5?N^X!#B|q( zUdI`aOy_;%<Gsh1zq1?TDCo`OB@`pnCp^Nj~H z!v}C$QM_m+KYh7_3q zfeWHkri;D=CxBECRWf}mh?1Gk`pV0nQDS;1i1L}f6huW#{|cfyrn|oO@@L#JeJY5u znf~-O$c@3%&E9zVF>aXN`UV`vS3%U2>8fwN{2A9wF9lHv(~p9vnCYVLy!;s>rl*3a z1=F{_1BF+_bhh{4a0z|y<7t*#{2BL5PX$pm)3<^so9V1y zKvAAHJ?x8@AEU$crC+@K8B?Zz1yMVuyM6^11yjF*LauK5v#(x$OlLZ$n|<^0V=S27 z`VE{fu7W6+>8jts1xzW35}1DUJIF(`ri=aX@?)GZJ@p4za_bK-f2IfXr?dS8MfAey zVL!e67+t0>{RxifuRlRfSv}qDmzN)7!t|-Xy!;sprauKyEz?bZLoy183YmTtL@k-F z`p3(k(PMfkh*~rK=pRs!9GWin7aSC+f4%$}eWq^(Q5@4*|9SZ{s!R_BQ6AHmf~c11 zUqO_{bl3l2Pfz_1a^1t}&;EP)F&>#}>g~_iGPTv)pXto|sn@(g1%fK0Hz-4uf~W)2 zkAkR}>7q>D{){HmQ$bY9_N`3b_H2xErhnz|)@Br(uE^=F%*r9o!f<7}C#SbEBkS~B zPH%Nax#?3mz15lSoSeRo(_4+T`2ZtB#Po}uT*A};aC!?cnoQ^A@>XZPeVCEKVfw=T zLL$?BxxD!q8K%c_d8;!@PjBV&R%hDbK7AdRw;F4h7!yPL^qXAX%1n3TrvC#8NyIZT zSWFL;mlv6C%k9n27%<(J+gqJ6WO^xxikLo^+gqLY!Esgw3m*oC%Zv;R7p50};+JNe zF#Rn^0nc<%9&dHVnCZ4W-db#iMy6(#2GbWdNlR{TbR>%8{3~wO2!5eM{ z1`y_O*)HbkeZGXzVEV@*fn(DzFfz(b=Q}JYFnwOMyu$Wh`@ENlFdA%Mc-dR%JCcdw z+b^8*sbrpBdRSIqd*nHvRu;xB+wWiU`NqQNy8YU9pLg<12BzDOefK%W3S#vA_1UU{ zqCG*)*Hf4$OO=6vf#p6o0|QIp_N|t_g3OFtwja0gT_eV*HN7O*SDVMi^dt)d0|>L3 zO)p#~t1w+4vRGpJhA&x~+j&BK4_GmpPFJ+I6J{|qG&Grhk*N&KGM=93Cn3ygXlQ6` zFuhTfMRYo^7z^)o-wSH&AVCB3?T-Dv=eQURruVwA$m$y#FvQ2FmF6YK$E$$!n4)k^ z%uu+dhTCIi`Mz#N@{RU+o&%&(1axma%SMo1QP5qvEXLdn49tq48+lm%GczzS>lT3G zCQOilfdw?I%fQ0I#K6F!1iEmY!Gkb=)3rrKH%^AbpbrT`-Y12ZF2F&hH| zI|s|r7)AyL4m%bG29{$Wtqhzw(=(O)xFsXm7#LVifP`2$u7jL)62xZXD4gD_0|SrN^esw$ii|$fuPOPd)IS5M&1M9jDan7Bi-Cb92h3sQzYB6nF5`QU zQ}_?@Gcd5^fjJ!fIUvLG!5kibHckcxmI5$GfL{n?Kp~hT!oVXAk}6`{03uY!TVGArdKNai3Z$aVqjpkVg*Su@;~QcU|_Xo1+9K$;ujZWU|_Xjg*YOe zi-CdF7R=$`?_pzLV6_8tco=xX*cljD?O8!4v;60oeoxs?vYv&Rfq`w3Ark|GFbgPd z+2%67WoBRy=>g4th&%?}iX$?Ig@J)dL=Y4~B3D2`D6$q5(;~MR85r0^su>v=*hTs{ z85lT3Wce5vI7LL*7#O%j{_-<0aEsjFWMJSC*~rMiz$;?Q!N9;L(#FHUz%OFM&%huc z!dTD8z#u3h$OA|lVqz#uB}fscVfOr(aHfk9kkEhhtmgvbLX z1_nuy59|yKQX*x13=GmD%sdPXG9m>`3=Fa&mpK?1*;DEh_^9 zTMU@P%RiZefq^ZS=@;na4gP*X1_rh`uss6&u^Sa+!2l85sCifGo{p0;yx**95t(0PF$<{yI(u2DTEgzm@oBfMiOU<})!c zsPKD%WXizyr1G|E?EmsuGYI9!<-7}z^OIfH>?8508o zdpC&9$Z=SZfq}gT#Af110g3m5Vuytz0aQ-(f!J)Exdp`x?EOy|7*rTI7+6@@85r0n zfZW0E!9J~@je&u~oP~jbeL6@n1IMrFAEpP0dnJI9{47ueuyGdV7c;QWmSkdJ;NVE) zW?*2S0}@x@*vZepz&;nGO^HK8fPsO19!Ok;GcCD@fqg#6*=igYnWqQN2oSS929jR{ zk~iY$1DUaSG7|%X3CC)XJxf4lxG=DAgFLYG9w-$2LCoDt*%%lE_OnedoSPwD&oT$( z@T2Nk))Kd^+q3jFKD-4E+3{5LX1V8TiBa7#P@<809$_ z7+ClZgOn>Xs&X(eaPV&c#kvZkHU|R(Pd)zukSA3c4LKMX1o&@)G^sI~b1*Q7@MnNz z)EPmgj|9I4C`dIJojDj7WcX`Ap4DXZ;FkiqSc}o01C(^@L3*?qLpc~2G#J=e zW`Qym%YHBk3SBmqr(iZ4C?~N9vNO~(u(5ywiH!xExmZ9U!NvmeIU7p}I|Bnx63BF2 z#s+o<20k`+BgXw8kIn_95o2&w!oY6wCSXF}3ZY(HZS$shSPx3=h$b960MLM`@VfW%l zmjjjD`hpA$92uZUV&Ir6z`($f2`;)gGT9jzII=+5nS+5vmVtqRBO7D{I|oN@5=dVz z3j+g3-V>1h3>+rB3=ACkAVZiqKs6pm0f^1QAq~nLg&;N?1B(gB^dgW;ML9T1K&85v zEXaMOAoIkExEUBY%0PCDx$`kFaFl~|iM?QEVBn|#B`mR3Tnr2xm7pxmz|zUjz`#+R z3#veQltB)uJ+c6+!0laD=fiFmNl?gWSl+!Og|Mz^x3*HT(>0EZ0CWW5dqCz^$SP$~Ph0 z>U%&|C~`6|aBF~!V&JghWnkde1PQZnfJ$9%EpQA$OwtCK6vV*B0xFbQ!a#=WG=og) z;5JwU3cGC}2b$kxVDMpJ;D`VjWe0KyBgY*c1_o{i5Sxj^2BgRl!V5+)f}i z8wVrEN6sKCI5@6=s&5yNdQOfR(;IdC#Ow2!85p?TK}v-<)_|lvK}tn9dO${afx=sY zBa@YZf!iCzR^i|QS?>#~UJN*5IT#qY{XtGN;Y?0TXW$M56*m?fJ3)aF1j-E!3~Vf? zLE)n&$iToIe3pxWLA-{QJM=2ZTYQ`h4E5ZR(V(5{9P%LhqCw(13|uR?85o{&GcbT_ zFHQ!Q#~_ErYzF0Q9_}Pr9tH-EJ0SJRAa^rxfO0Z-3W&|bVFmI}DkurEFtAJq#d6vQ zP<_m@1C);xxQn}a7#KK{QW6=sOUf8QX`BNbQKcFnQ#pQvLa_{F6c5K2Q0RgaD>TY0 zKtUtGkqHXXN)TI+V+kk-sz5;_!oU&(@??!34+Dev7IyABeo#71%E@Nnt_Lw0IIe&U zZ;~7kpNW^ z+})<2dXr6JA;@DruDlEk25b`dK)QQHxfmEWurqK~a4|4|tN@1{BLkN{F9QPzL-}kh zyOggR|u@~5WUf=H?%l5M-evE9>6EFA+Z+~ay zr^G!y2y+!p7VzN4#%hp}vWqLrz5VmByApgN}`u@@t;*CVlaBeAa_v7aNcKO?cZ zryC|jh^y+eF)%Pft+7U82P3hwr=LxT5TE`B?8IwfJd(4KBtdNkm;tw^_cG;(PtUj` z&J!xcjxbmkiEV+z_CsQW>JpearAXpkNbKp;F9!RSPrngV#KTxP{cli_^7J0o9G>Yd zA$}6m-&iH^On<|g!^3x-17Y_I1ysI#JCWGWkl3G)*#D5&prRgTgBU1zLjzq4iEW0& zc0ywNLD--y&cF}_;egX}8WOt_iQR+5o`J+(g2di{#0K?RVUD|oB>o7A{f-MXD+G1* zFC+;zP-7e_E`-FELt<+ov7M0Een{*nBz77S8&vCq9S8D%9g@T}BsM6UgB39_FziJV zKZ(SChQ$7f#Af9|qzyqNwj2`MnFlm01ofpql0-BTI~|E#jKr=-V)r1i*C4TXAhC}i zu`eLlQVgJK8s^Iv2nmL-)BlG1iPwkmB0Q3a#Lfn>L9J^B28MiI1_n@B2}(azAaSUl zT0m?rkSGH~7l;iNp8#Tm&K_c5V3-2Z3uVto65kJDgW`vQ;RJ*OHt74tHB>P$~8 zrbos3sWIwJZv=^oOkWx2r_QP@!oa{W{c4<_GNbnN#J!T@(*@%F1Q^q%E5`e&v(8gv zU=VC6KDt!)D?hUdJm2+5W%D* z02==@0QIUF*-9lC7??OkK;wT-U=a>kG4S}GiVy<>lPm{l{4W|L!NfijG*rmKnweL^ zz@#k(8Vv;9Ps7Z@{s%O;$ib=w$_30E>|SgP3`|>C85o#FKx3^;`JmxJQF8_c2Br%F zpaH)C5OXz1fiCDiTqa#f(10K4$R(!Zpz%B<&?aG~C7}9V8MJboX&Q*B20Brd=@)3k zP4f-NMT|_opusKJA9RkqCcLo-=sXPn}EGI$6v9ZZcpIGWA zEBFfJ*AOYtP~T?;1_rLC>HACl3>j;ue=PM=ssAC$z`&BtxD^yoe9j;b=YTnke1#x4 zyV*75Qm3P9yAJD09GczX9XG&ECh2z7`Q-bnWczvIU@rD zzW~chMmHt~27yG7=2eUb7#J7?m{~zhnblzR0#l~XFZ0tkpAE8hJy zARllrZ3PDeM;A8(gAfZd3v0O$cqo=-I%~O~qWoph+^ATo6axdJ*avV_GVwDoFpGJB zoG)fH-L>3L&0m;>fq~766=V`4pBEnk1DiD~$T>`W4qjOA2BwhdyUP8f>TN-N_(`jn7#PG^K&ga%F5@B=1_m)u zmz+WDsu0LUpF!zF%nLL!EcOjFC@OYHgn@xo3^e$`CI%XlWEYzU>QjpOi83&7ihI|GBfSPLHmgM!#fAqECTF(xqv1|_k(Vhjw*VxSsd zMGQ1DsVa7aqn?35P3#OC1B1F)jtB#ThFF0l1B0emu>b>umKbPoUR&&kAOnMr*nbHI z23@gPvo9srJ0UIq3rraV>#2EHQDa7j25C`K6g`Xv|`*dv%CLF0;inV_M7 zNTzO3_nB`JD8Qq@db#xzm@nVfn-XVLYNsCRQQTOGG$SAMM zU=aSvIz7M2Pc&x>n>iZ;gIES=U`p(}04V7tf|DL-K!aI~A5>n58A^eY-fU1JXJF;x zXz2hA@brR46*@sVgMsY^Xb_?s#AamUl44-s=mD{r*g(Uv9KE3EVPWItnjWZCD`v^0 z&dtEUF#%*Ps|Uw47tk<~0UM~I0I6eO1J!~YGe9BD#GYGH%D^!bB+kNidb)kJpLo4C zXf$RHNLqo-UYvn}V=hQqiS0UwJr5+V!VVfoVqoA{0y5KufvFTUjUfdm3&knj6 zjh%r(q?D0?K?I}@LV!$VV2T3ueh+~a^@9|_lV$U)aY3YcU;_TIe+Qu~mdfuSB^8_3-ZOco#`pMY#*dIlQrdG#Hnj0rTd z2XY+)({^D729A%s91IM?pxO$e_a~?=#Pwd1fq{da5o9ozIVeUX89@f|>ToD9o&!xr z+yMogBACs<*DlJyz@fx=1(bPN_!>d>Dl^^!4K?zqfYhllJ^&3h^4$a#Nve#`I2afN z_{_u@7&z1z-+1C3KzfH|xTT$Z50IV(mPP6h_1XwbM?EGS@^b}%w9a3)XV zWMB|p#tBP0Q!EWFmM*#1I-(8aF!%-F)&E>g4|aMGEUM)kb!}-3}m-t1*mobtx{u<1og=|H7h_V zOHxRHfq}DfE2t&F^jD05fwLMkL&a3V&cMJ~3mQ5Ro;3YOou6#|BG51#sF34iVCCVm zIS+E}ZxIFtE?cnI*(CTG7`W^}Y!Ffi4CMjIVK+Id(&LR|cykrYO7 zVa6oD%)r3o4YHo;xF7=q57>cB2Lu=xcus*txhjPj7nQd?8#+R0L?EZF!2;Hp5tL)5ZDP4 zEd)DXARFYtVzB*?P$&c2A_pqbdCI|Tfvuphu3$XH4Qgt(axpOQRMs=LgNFUU%_5#! zMmAms2C;BZH%Cm19n{(umjX4>xIiseF+E`h237{HA~psFo)&QMaqR((Q%?r7Ax$fu z`HTS|Gvq*HHe$CWL1wH2HMzx}gKIV?kQrjPL3I!VuME%Xdd5Cbg9)4p)__w11K%2u zGuMKh%*2<(&%nU54$NWUYXODIdd5spS-`-h4wBjcwvShWXDcJ9zU2d(v<+&~YDoqL zp6y`GOni?((Y}Lm5~y*213D&< z=QKD31Uf;+pMkJJgKIoz!Tu5W!N;y=XxDRGCaK&;nFz`HJoW{q%P|vj*q~i@Z3V9`XJ}~m}GcfQ4 zgH(KEWCEoWJ~fbvPhh=Fe0xFe{0xo)76vYUP`3ZVc$bfXfmed(2csQGGdRkAg4HvC zyDdDwVCuO*q5hjuiXW_=fvLJ4qyf~m;bCL~MJqJ+nZQjg5lHMagE?XhT%jP{EKFYf z3=I4dJZww{LG$)=KuM6DsT#zV0=blf3FHchk9omb1%7~v2mvOL*BH2%KpY{ac90tk z>UqSN{(;=^S(Jf+M;z(~aLh}9^@@PADUT%BG6@E*8ju^Ln9hQV(Z8T7ScOSUfPq0+ z8?;maRBnoZ8jd0$E&~q>$Y`#Kpq!?`WD8OjgsSXKJ!lMsYZl1e+DvgE6%}w57x@?% zMBZ>QFo=M}7E|A)FAhi!bDnOM4q_qJmrbNDj#Xxl(mm$b(W2Rjo z^;baZ!HxvAheg^;HV2z| zJ*d;B2nrG&HWv_E2~_Lwu_=I3hcYNE`5AavxOB+SAF>PYZvftnZ`5Rm*Ob0-Q>--0qRNujCAScYg zz}6$kz`$z`vYdhKsW1ZruN{cZ$aYGIfq~Zn#Aaf<3G#&_$gwPJjS>tDyiOoC8=DHq zN6sKCIM_1885nq7KEqzdI||YVRts*TLF23dB+SCV!&09MT7R}06!V2kKw1=di;YDX7}!BG zZM-F*u!CwT1!>`61GQ*)%RtuhuqlJ$3EUKdCYTCPFbc4N2G)5iL2N;`y`cJ{3KWbY z3`~xo2&uUy%)lVOg`Kx#VO{+_oY3=9Tr z3ZFr`dqLTE13Lr97eNLFkPY0RW>q~S1IKj{1_lrY3otV9uz==PIY0pp(hnA8X5avY z%3l#^^l&pUO%!8b;O(~)VPH^v2I^CLWI;z&O~G?$Af6H^5E(r{WfKDf1A}r6XiU}% zowJ`~>XaGLVBogL)7LSAfjnVq{=|m{SST=flXrpbm0xk2+{%2I6LrYoi$r zR2gHKI20IEKx3Lyr!VO86E_nBSqQ#(1>|wYIcLNe7&JlNXY2==#u%hk5MRi^I1wZs z&&a@_4GPMR>2JII7}UV7SOIcHEh7ViCMc&ct^g%(#$ZiQ z@m9~c0+jF>Lm*CE1#;qckncg`=3CSm7|g`MZez4yP*GrDVAv0hz#>q>04+mf+y}E2 zfZKVN48b|o7Th>w3^LSUVqjpj1&=W^21C4M2etyViqQb4q(TLure^127@BW5!?%8p7^24$QIP;aAJHY&A`Br!^*&*Bf-GH019Sx9dIx+ zFhof~g8E3GpJX;D$5cy!BMPKll@XG8nYogf7}P;~{!U9UFwB7{fEGxlpaKb`m_fag zfq}tJl7V3xngRwL(8X3@TR~@*zENjjcnh^Pw%<>fA1rec>K+wohP3o8Khy6gQU4v5sX%#~shB~PF&69y2D1jx;B^r=kki0{+$+n#V9FrEz`$4nZgewG z+)!@{&ef%0KGQ@O)3u;UZb<(S7Io!}M* zsRCMLt--)xG=0`YKWP;^kjb(j2S$T~Cx+3OLC2L568kDCj0_BKpqcF5L_fI{(1Ibx z6W~w-9l*dir%8^1!Jq?FJ)Hn2&6}(Y42IzH;RGW{4i-$Oz`^v3m4U%HlY#LxI4LT# zF)-+W3T$x9YC_{rW_rOSKYc#1SPWDw5+o)z{qQ6|N!F?A3=9?1A5QX&>&Zs21qiR(GXOH zO>|&jFcSskPjOH`f&sMVjB$>;0t15~*eT*nAg3?}8T^o#zI(EtjF=B-j$51wR4Out znu6*MMoFfl)89_^ljH&i11KrInXcELBQ;%Xik~DTY_gzX^L=`uM5NgC^eKMAjFQu< zr}!z>cgQg?=qiAm1adEf4(M97Bn<`z70{&{pz0b@-7zqjn1fcDfXZzK1_y91n5M+Q zU;r*^BEh{leRc*0i~Irx#z-bmuPT6@fx!Tr&Lf#X#cLrutU!xo0`;{RLrsN6K&c@H z>PaJ|=^9i0^aVlVdyH{lBl$TP7>uq@&zS0Gq*frxz@V=Pb}3sC1K0omQVcqvgaGz7 zsCfZOgCmdw*& zV0Z!7%%J{?fq?;JAouiwX?}8$T*U`Y?F^G2Lpp4sPW5a37$7$3^nWl6*ZPjp#CUhn4uJ?w6bCX^%EJxO~J{?1{%WZf}lh0 zI6#d#Wr#CDjUCXGEhrgSLB)y~7}PDHevXBU!AfpeAgX|Z965pLpA=?bV4Mqf6ewE> zffEUXDg%Ro4=Cx(1$#!So|A#W09;ni1^dT>lYzkyoRH@-K^j3uU^mYPyE&4RfdP`w z7Jv;d=VV~8GsE zfqQ7?Y=WC}4{Qu*=`1AR??D1SSOtrr3?M_9iWwLf^tao98ar>$jO9>+MerN2u}|Rf z`3A+<>3OsKBok+gGB7ayf*S!kT7_|rsXEMvUtl9xxfmEAiQo@75qNPy8>OIF4pW1~ zXb}U04rn?LoR2~0dw}wBuNovf{+$JD1c0(SNahGs#$>jiu;wHU28MfJbE26)GX{Zz z&5%K72dp7;3YrQ;q19RIY(HT}vFS5s`$^YN2JH+w!Q`RNz`zDxlK9^$m63tL8Z^+t za*`SLSD&%gk}tO@qbQVa|r%u~c{3$hc0`6TVVB^ek%m`9q$ew8o-0|@h& zv)Hd?W?%qep7TuhPqTO!7@mTLqrNfO=W{bKfH039vwbTk0|N-N$FbXg=Vo94VV)Dr z_BIj>3?R&t#bO^Iz`y{)+*?@fqoo)aK$vF&i@gIE0|N;2c(B-S5oBNhVV-D~=?m-h zET;R%2u4lk-&rR!{dTR3)bu@uk#^IWuW-pvuhSP0+#WQ~&p~Q>zfvRb_We8j7&*6} zJ?Qt4AF*U}y0%-0$oBIW{WOG`j4ihReBvj`!DVd0ke*l&pPa-n{oy@7$?0{k^VqlB zy!CTYXRMzt=v*w$xN!PR5r6CY$Dm>hRK+lWX4V)O7@=%oP!kx+mPBI9Be7MH*xE>J zLnO8X659uf9RXoO)?TGRIN&r@fW+=ZV$VThuRvmh=5k<;zJVnE1c?pW`2kbI0jfx# z9#dcktqp{7Ksy~^iomNqq2jJc8bI|uObvLoCsfS@BsH^<*r1geF!jfg#2>-fpcdO( z7zecK1+)efYN#9%TWh+ZX0bS<&-966{^gQ_paq&xRcc6VJ zWY#0GcO$WnBeAa_u|bn8Fo%Ce6913H1}_bTx~JJ@G7=lK9tY-#)kxyok=WoRpiuKcThd_aA979iNeHw;ALfGnNaClbZ=4t>&iHnEAUChLBs*vc zB-CzEB)0bSz1+Ow^+8BN@ks1kBz6rFdlC|R9ugb00vzU;LrCK1k=WqXm{6y@gNQ@o z4Yc+jrui2{0vvA)pw=u@13MC17>TWe#5O`=TOhIRkk~FrY%gBWU<%ZNC?tvW=`*GL zm2>-%gq9$&HzKk3A+gUOu^%F_-yyL36$JH$pw`PxFXYx0=LIbbfJysJ7v$#^ zXH1)3>nRAQ zA#TuWB&d6hkl4XU?0O{jdL;I3B=&P8HV}yEuM@a0iNNf&Jn-l5?5hS((gbm3#IuH&x(Cm@eK}hU4Bz6`Oy9|ll zgv9PcV$VWiFGFJQ6VgXi-=NtZSZrNGQuGLk{cd{Uy%h0!AyAhF>M2zuwj~nV6^WgM z#4bf*HzKink=V14*lUs4J0WaHpq+tmz=8G}iTxdk%?#>3LLJJF#Fj>4t0S>Zkk}ze zY|tDCENpT_kOHj&Nl^ zXE6o_VGtXXX#7ADP(xEeY^b4GAT~%50|P@R5_>KZdm|G2GKdW|2ej&y5j3R;>L!6K zgRB@pq)4PryZC6L&vNNg<-8)}&e zhz(V531UOV-9c=qcLx1Kmi{Kl7K2o0kNS5fx6(Z#8nOwhpK4; zv7u@vAhG9w*ibc#L2U5p3JeU(B^elmq3lf{aj=?t28IK04glv7u_@Ky1)zACT|WK^&;-Y(Z>jT)H8# z{gK$9?l>bP7bW?*21Y8FFc z%OkN>L2RgAJtVdZhz-^23t>a@Ul@b~3J8WI5F4tw0mOy|T|0;^2v)+-EzQ6n3}sIP zi9^*aLt<}5Vjo6gp98U>QE*ursoM;iBx8gc$|%FY0Aovn*oqK~@Di4`M^rw1C)93wn{* zi$QE?pshh-Z$)As1hGY-ZLw1j4#;r~4?t|F=9ft9Pe|+^AU4!uDFp@wMkrekiEWO= z_5iV=p795<#lTiE1S^2rVo**TNCK)T6U2u4vI2=+3t~gnbb#1UHN7Ae+0$`<;5#74g&+jO%NMu&=U|Fs^KMw4Hf?aVnfAQ6hWKlA-)ktVoQM7P>&fP zu`Q9<{)(Ws7&NFOKoU@PA`-hA#D*F)4~e}TiMv`4Gp<@AU0?@0s{lXA|(a}VF^(9 zGcYi$1xY{^?EtZ%!Fw9ShKgSUv7zF(L2Rh_OC`st4RLv9+8|ti?AU0Hd35X39UkPGE#kV7| z4}sXK&`fw7#DOZh1Y$!qUk9Oglv7r%a zhQzj4sYjH_t{@4hW$Y(ipRKw^J@u|Ydd#Z(co zr3hk!))Fx=FsQ0BFbG501|V^0NLYi|&=7I}v7u^WL2Rg+3=kVM1qE6O12RW;`aL~F zncohQhAN#3VndZ~2C<>y`#@~a(kcc9hC?7DpzO0Caj2RbAU4z~cR_5Z_-haws-9B~ z;k|kh5Jw)8jvmS^IHPjfyhKk#P*idn25F4sD9EqKP#4ZD|p%GUP zVf%q??tpN>>^=}1YS45f_F51ds(Bj{dp{EU==9o-F!A~qAR(v`|3GZ0Hg@*~H5r_?Kk(GnkQ1wj^Hl!SBgK)rp>P2EtL}E`vV$VWi&qrb} zMq;l*Vy{DDZ$)D7RG)5V=+7m207>i!68rS@L_>dZ&+AA+w~^S7kl4?V*l&^8ACcHU zrXMu)7q4g0K%^-SBsM=1TNsHgjl`BmVyh#uwUOAyNNjT?wmpOm336u$2OQ+yNNj&3 zb~q9{8i}2Z#7;+I=OeL;k=WHp?0OBPv9ER{iEbqJWF+?V?T*I&tMwTxroT<{_h+0i z-8R`Dbl!F^h&nL+ZnD2W)06(`dMW;XOn>^P*QNM_&VW9f;tx92KsMFipRr+jE{N)x zz86HLOy^DW2OVDr5LGb!Er?Q? zZkyo`I@q@tMA=Ng3!*%x>t^~NXZkR8`nODf&~du1S^l6?xu<6N`!l_nHvL(azaL}7 zbkl5qf5s`(TeJPknJ!G9{x93#kMYEG-yD#lnbYUx_=AoQew*VDI(5M|*B^Asb}xu> zn0^;TbxhaI0}IxID3$4FLDZb-vibg?6LE7v)Pm`ILDZ4yyaoRLOfQyAk1OymW1KPl zYJorK++o#1e{IJ3(*q0rm07o}Wnefky|U0>nX!EO+(LhK*7x=d3>niOe&QFNey7l1 zfU#uyTaa+L7f4~FSFy-+-6DT}Mw{ujMgHon;@%7l8z5&W)D-y(Fgi@{1qmPbW?&GV z?iepFJpBwv*kbx!kno*w(E1L?IYPqIWs3a;7<;Gd7W=ESo+x5quz(nn0}^JKUR&(1 z&X_TMDTrDz{cN$nI&aE%28IAG1_sd5>b&WS#oW@YKWZ5mc%~~di7E54v@$R}U}In? z0u9eiFD&MkW_r>+J+H)HlMQift~jf?k(rqZ=vW6vi|r3f{1=PX%PS#HbpYi9o)_#4 z44}gr9Kaa?LNM8bR@DoFRzNc|vPJVVFfg6sK|0mpATRh-hojsK3`~bX$0~|JPjzSn zZO($8>TsSH=~Rbpp!I$ntS>+Z(=l_fmw+_g1Rnwlsu7r!!N<6QPjvtt%Eqh+KGop@ zNCD(j2c_xO-TvBqQ$Xg!4s1x9UefKaBIyM>$N+joLp*2+1@wr9^V2tW`^yUIft&$a zVaakDd_+Ud^!wfZij3Q*GxqqaXyk!3z>a7DZ9Zjz9nmlgbT$O+h=$$MeS7>RgC2p7 z6oZ||umrRr4t^fPXOL78<8(#_2CfGntD};)jU8axAL&rY-D0! zU;~|`#b&Dxl4ASHIbFWjUz~Btbn{++BQtp(1_pL(=-CVBK!^Up&Rzf=Kg13@djWJ9 z20Q%hg)P(P_xg+1gN~SF5C%^z34>M;G6{orHZcnaGBGf)2tQ(EU|<#I1D%j1{0_8b zU$`5zvt3w;nSp^**aNf;RTz9!nJ_nK$DZ&BE(Qi(;p=vUssU&l9S7_L1CB88!2o;-ppB-m6AVg0 zo48>o7-UTE?(>(70j-1Phz4(a<>3RJg2xd9=J4`82Aw|$JFUPKbaY@G*h~SwFQEO% zu+s{ZK}R4YGKqjsD-Z&0w1=NoFs2(ipfFf)rLU?E{4)=3!C#iQg`a_e6M7Ut(DZ{7{N)5YLEH2}X_Rw!02>2?K-TmR6Z|FX`9S-d50!#M zTG<#F!0rSS3{0S7KRHh*f%N?V9iVs~bWE54XeSR?fgp&*z{3J^G*b&V0|VzZkOHPt zpv^^hkAqCS4mT0xb_S+zpiSLRK$bE61)ak9>Mdw@n7|K^GSI442Br?szVMICpo2s~ z^C%FD_JFbv7ig;*Cp#m^U@mu%L6VFhlX!JF6&R0z4%&PNO5TcKHUnP`$b2QnQ=rm= z&l}`PWyTAjc;)j3DN|v*2HF+JSHGTvfq_$%@easFzFVMk`P3Lei%>-Pc7QagGlEKA z2|m#76iyAsckB!dGJI|zJ(`SP*cliU_+mgV)?)m{4%*&-9;8Q`kpX;=C=ZJ(Xd^F6 z7MKKuE)UBDFdKA`ClAXWHU@@z9u`m_@vuAsOMpUxhXv$w9v09pB(9wx({&lOK|7Mz zIE@&yK<5}FgQ6X_y^F84=O2>dq4*t%mE!F3QCfK;G&Gxi!1#k=uBVG84X;} z?ft=^4V%#I{oqK-0%a2p1}4zf0IqD15v&|sxxAob0c3d@7`Q;Y`|BAP*vfbq7`VWD z$C%ha@a}#wO;Di+-Q5q`SIku{!3jDEiJOIifvYwTbdYGrbiOJ6CiNdd z?mNuLz`!F1_AA>y(B@KkkT44yXc;t*0*KAQrUKe=3EkMJ1!6-tHqHg@>V$7>Yy<^r zA1HEF7H~2!u!iucTZ2vv0Pk$o0GY(VRtH*BrwI~fVXFs~L_Auc(B)tQ8wKCl2r8(U zu7XV00Ucb*+QDO>2s(5&J?U7iG_hFjftV2fhP^Tu8}1f6kQ5D#h|VE;LVCW(9MeA zs4HC#s^-|vgTfxVSGbr&iuz~gh z@w9uAIs-Ndb6y4pp57^(;8Q_4zH>4#fNTJ-MP_7( z-~b&a0K!lK9+uOfx)BtJApKxbW(E#Ws9fQJ201qalN2b(`$3DgB(HuTM>+Ai}lFvx?IF*1YfVGIH-KVkTwz`&pgT2A;|fq|Lf zDDU)#Z8l2NlVVlRa$zB7kyZ#Egn~UKN0|SFBC{;6lWd`Mmzo0=Pu!-N9HK%Ww z;V)*)!^XhC_>&n_B^fd@Fvx&PK*nFppdE}+j0_A4pn*WJjd~0W48Ii^7`pjD7K%>i zo9V9*c%O%XVLs@1dPeYu3kA^9Wi~|y1~t&;9U(;q1|^V$1OtN{Xy-lSWw7r+V=9bu zGWZ!7WdDJJ_A=P5xr_`9vX;~9XZnlTKzyqRiffP!qWoZkU>hYAL2i;&WMI&Qh=Ue% zD}qis&`@MxaGri~roV(uI9Mv0nTv^$K@D_S14uo{F`&iYavMQwn99MoO@P*~GtQ9_ zU|^612TVDO=5*Cr{_6Fh(uT2`1r!i^ObiT)lAzOF6&V;n2Z@0UDpFxk0FB9j3|0hf zQ~`PS9oX6^rXmRj1yJ7tED74qXROG;z%2mw251Sr8fYJ#Jv4m4PHG1&Q`-g(AJ9b> zjIMKDfZPNQpl#p)@?~ORkT(G>%iIQzOvYeUu#0y<5=RIksz4PKD5_=)K%z=@w!fq; zC?G-WufT3+U{D10z`PY17!E^S1==X#3p&}Zh~YX|D4Lmzk&!_ylmXORt)A^KTVE>( zi?WGe7v+JjEwBeUd?GWb@zl@6zyNX6WQd!B;8Exz2=+TX3T+q|7(m$~0wT@?vK_Rg zfvK1w2P_1&JrHC&G*F#ET~9fAP~0Ve0}8}voFgd&b5#P^Rgd7VN&vfxnHlD)BxcR& zQFHvIEI?uL6l@J7*@AXBhAT2KD1vrRB`Gp6fYyIO0!oPywDW;M4Ro7A*7P-V{AJni zfwrgr}>3o}+t=ULz{X%6xOs6@5~m%>*-=jl~cFfc}e%Wh2;1_nsk z9SttKvsoAz)Ifvbo2JJs@YnE&0hOnqdjdfwFbILl;yDK-7#Orc>ungTLAMgru`n=b zLy8wr=>pnEto;hKV!0aRQftsQ)GyrA&n)nlst0GT8c^N>-L9bnYFIGVf{bID$e^PN z%6YY*RxHy*79CJ)hp`r9Ak#z+9aGR!^Eyz|glQs=9=M!n0QrkCSU)*4g@LgVq-{AX z1A_u+Y#1B|pezXrl82ye?Tk^3hDwanU$xorOfOvMFRTuVe8n&Z1_n^1GK)h3x)c_~ zpqK^4fYS8U3;m_!L1jB=mp3R26*Dj>fT9;{#{zJiPFH*&DLMV`LVsZ=kfvU!X~h#^Eb^C>1X&AOsRXrF z(S(tK;W#)A&RXPe2#NSGsJ?g!NW{NikJ0HX#YsLT*$V_=X49lZgS_he&WkXHt6 z5z%1m0M#*}kVLM<2y!jx04Et90Z`J`W&|}AK>IRe)=qC+;xAke@&l(7IPl=bJ7|dQ zz9IvIEJU2CoPj|B)NXnODrDmr7#KjI>j0H32FG|21A}4{0|UcXMFs}Y`KF*CDPv$z z1nrFmRjnCN)gYrLF)%QIs#b-q4B$M^z@Tu1fdSkyQo9RDVh`JFM5o&>^%qY8-9N#Y z%9sR-3{cq$&eh)1uqIh5IOIT^NMx-*nI@I757bZw?e7FUu%RFuA;&kI16c=-4u}kBtBLF^P{j2xg5=Ub{cx~# zePHV*f%xF2SwA?uK?mo7>rzl)@0CUgY&BTR1QcRL(=(U(%ZnY5fkppDuuE>TGcd^V zOrN*RUku!2^#W~01v$@A2G-^~5AIll?jTYCZNUb$;uzpoM#`XA32%YrLd3x>Fi@)l z6e*2JVxVo6AhD?kFZ z1D%r&PCXDGgH~370=aNH;|hOa7j7j621OSJ(3Kbr44|FzN{msA#te#}AOfY~<+9*_ zVJZ@Z`T4HKw_U<`(2Svw|Bmi@uWfQY_KIj}3) z1fg4v6+smi$oZYq1y}k@*MpiSAjg1Oq6P_|Y9$43IjG&wI7dJp6ayg3Au>9kyBAnN zEfWYIW_cRea?lx7im;IU1+^S%H)zEYgP0P?L7;RR=mJjf783l0>sp!}!^I?4kS>NDjb1*h^Ve@RHmUjxpm3=G$y zG6}2vrMN+Q)F3f6UGPh;*!0<}{8j2B;EtFNb_8h11d_BCLL3pL2I`xD(uopd6s*)^ zF!%@xx@}-Bpm+oIQyAwgg&PKu0c}o#7`6k4VfCQx;0(sAc^Md3PB86IfbY&U0qxE- z&IKK_e3Iz`NE~Dh0|Qvx^cm_w6N!7U;trr3vLDm5ax_wG>>IuU;tr`2R!DW<4!@Cb3UUPE2ww|4Ql0^ePLu^ z0AaRzGtjw~Ak0>1woQP6VH=MC0|Q%~*&h}LhCeLZH>~lWpgi4aO`^#5#0<nWy*I z`YCQ#zT$7o&hHfB8}IDv5+5Am7!=~_vOVXv{{t_{&7kf%s1{~mU^s!qzB)ZsEx@{7 z98^_8rOlAoPDpG&Bz6=MI}M2qnv7tCnllMWd>#@TG`s^-a}FX7nnz<`xCP;W)4($% z_CF-H7^u>QS^$b2m_d3-;^2EVplU$Z0>RW|BdKXaVozjqXJCLS+Jq#r7l{qtq6szh zF_QRCB(})(g_h;wyx_(vRH@T+PK|(aNp?_&1}Y?j#MYcXQzO8dHycT)e0r~Hgn0c@ zB%zH+?7c|rQ%LN)NbHwL?5{{{&<+8ZKS6i+z}TRBbYN^9P+4ul0ErRMxzjKSCx`?% zc6^c8pi=-~YCw}QF!od=HJ}scVB%Ym#1A5|&mysJa%Ll9 zMPeU9VxL1|-{J7WY?k=T+T zHpnst1_l)n8>+^Dmw`bFW|=ie0=lUO)Fu&TpWdevAYKnu3*O%eH6sfhy7fv7w5L zL2RfvXc7k&n9fMz9w0W|G!>)IkS9 zY*4?Hfq?;ZbSUVccTldn01}6)xea1N9sK~rhKj!iv7zFin@_=>0r?+vX$kC37%|Y` z9n=CXB(@6@I|7Lfy7Uxm5Ca240Z1Hls0RZBLkZ|o1SlJ{MFgg%3#10>h?)GLCBsk- zc(*H*y$+-Z>T1wEmyA&HeIRkDp_h=@w~^TIk=Q?w*r4VH=!O7LXvuFEzIR?n@3=C6{ z)XWF54Hy_eXR;N5W3JVNBBsHL`KR_GlK;9?-i9^kq z24aIwrek1WSPWuA#rGny&mq|L4EI4CsKw7fY^df}LJSPTQ1(}lI8+TYXwNN_Er`U{ z0+b)T_hz%9r31UOlUj?zDYQP(dK^=Hd{R=V^ z#0I6NXGn@ZfY_jU2?hp+FCaxw_J5E#)F4jK9$lzqd>}SdTmr;~ii39_L&epR#C1Sy zs5of%aXl=jdLT&zf!I)k!a;1P2Jo(AD7zR*yb+1rkHlUEVnfYY4Prw*vjxGfXE+7o zK;sF#bs5UOgCzb4#D;2qjl^aF?a_sbgD%ftgtEcAlA&w|BsHL&$go-@9wZLS&7i}f zVG?;D38>~iB=#aC_G%>dK@c12=u=4S%Si0|AU4#@&q!=d(8gbwtBpW=YoUrfKy0X? zfkPwK=;0?i0@eN4g$3bjp^j!k6m7p7cuYorHf+hz+yTm~fP(^P* zY-s#}HvvP%LDwNMLe&d{wzxvsGDvLjk*iP-ScAl&Y!@VUfFy%41I!@s#$TvGSs+DF z%Su6PWl&CMV5kIb-c_EiXMt#PPXS3omCgsTq3&G*VnfB(gV<2q70N_n z7a_4hXRpGHXh9O624X|QaXu1z1ri%{>ME?BIS3M0fdt)ADFy~%6=->T0VDzS$ZZfC z>W>E?HdOpIhz%A00AfSM*+3g-q2k;iHq-(UB(@re4RxqK659g2(H1J<1CoFm8V+KE zW>Xj#7@|SDdZFwzkT_ILA&3pNxD3RGiZ_DTQ1Lbp8!A2##DJAPo!*3=cqT&>_PN3=B^|j#Ha{&I*wN|AVBVO1VILb)k0hgV<1U zDG(bf4&FQrnluN^4}ip>YK%c_s2U3p8)~H!5<3csU7v@I_Ncs4Hf?eVjDn{(r*w4D!~TY)eF_Y4PryZC6U-$M#D<271BeaP>kVQ<)dYapP=`jzg7&vTIYmek)ky5V>2qxY#Mw52g{GHz zYbk?HvIP11K3E9EVqo}*#O4BR;)Pl*3Sxs+ATcm7NP_kUL)oD7*kM^rAEXBAJQENb zs@DmL?F(W<)zk-pI8cMKkl0;F?AahT)SzV`HfZvifq`Ka$PrNXR**PU%>fV_YQa$u z8!CPoiG2^mHediv_A@X%263PU{YGL7f;RC&HOqk5kYkg;D}aQxrvI}I5RZY{V-1pq zD)j`hp-N+s*l9@Y8W0KQ&yd(3k=S36 z*ng&8#OqCvge;KQ4oGYlB(@I{ zI{=9d-scRpJ_boV8Ht^a#LkDXK}}}{hGGZ@9E0GE(NKfxk;L1P*xg9%$w=(!NNn(? zYN$Djki@|otfAto6+z87C}%U0qV3at9RtL34{ZV!uXW zzei$!n|{$TKwJ{kl7f{>tV)Q1a-QjoP66V);z&Z$+Y_AvoUIrQrZ24t@MpA{{&-A2Y`m@>q&>lF`x&VL9j7|oI z1O^6%rs;;Jsq)h&ycb}ZzM(Eah4IAnt91eXOm8};tJMeiamsYTj8!yCm7m^_P{1;M zL4AM$N*S6XXxfIrif{^{461N<0MrmMCD_%jwvFKr1p&R8?u zwl%B}pXtH8>1ka7evApzw{`{iGm1=S?GEr~jF}z^qEe8?Eipxt^? zL6pSwry$B^x@m8KKV!o5*4_YZM&;=ndjphNTh=fz+?jr}H$a)`x%u>ey#Z>hEY_ey z-!C$X2~W4_3lLyTnC{ybpw4RM#=!6bvL&vkFF=6l#{KE@`U2Eg<=hztXW|U34@Mpt_&=UF`y;s)l3Ww-OSVNt7Rp4b3xm^nAinD+uOXSznBytSMLPc z634_E3EJIO1=>v@W(>M5_!x*O1uA%%IatfVyXx4Vfle@GVGRb|oXo-wnv`T^VP;|X z2i?WXvJ522$l(pzt+oqvO|l4R5e&;dkd30CwYV&fplx=FsUXvzaxgG3>w;ESda!`b z&0$dlom|Xv7PO&F=`ctIXa?DZI#$mxWy-&$ciq{)7i+)-hv@wF2W%^bnKLw`i zEYq(m`6<_fc8joNGlH*v;Ro$-VaWk=82RHtnsOQ6gIvIG2)g4g56t1<2d%PX$p>?I z_(AuYvJ`+h0{kJME0PPr91#W{BhUt(BE~Hsd#`~^<6r{WBVfbCz#s@ZF`t2NdZn_T zsIxu`0|ToSD@c-&A2dzOYR&otv_6+V5hP>73UP!2h+_-paPYqbO^w@uIXnzJD$^aO z28h>#?&f3=S;q-Fcm;HM2$RTpP?(DpgF;XQwA77N} z=#Ep7IM9t^3@p>HPYqD3|HjO~z&6Pcv^k*}x&+wlF4j76u0Xi=gEO;Y=V8 zGVnWql2HUx8R(i|{{5icC6P=ZcXIHzf^N!=0_)}GPvBu-V2cKGc=$CyD*|G`9A19V zTpU|0(=X6P6a1j1=qhY+V0#4k#X#!fnLz75CHO(7{IVr7sWLGzNb<8xUob5|vVIOL z0|Q$MQ#3OJgA9K#C|pv(rphvKfkNCIbQ9JD(1IKWo;M(+=}hU&3=Di3Y`ILcK|T=% zZIjGn0;yx*KMlIJumEhE0)G!kc?sB$O8gr^p-{>My0cb=e?G{XGO#uEsr;a;$=J%l zyfg-$2#{PAlQU@N9cVkBAUKTJSh5)z7}&YkTR1_NyM}`9JMILf6$Xw4pnHtFL2O2j zAP~C;#Af0EowUy03)0QPQO3%^z}^R9vvKAY6f>~*gV-DlELrj(9TRqd?ltycpLP^v zIA}(aeL6@10|)2y57Pt0Jwb~#*k^$Pk&Ux3znFo2wj^l3AO~n!1p6G2xB`bc7Xt(P zT#z;;4$y==`#g}i3Mc65U-tPRXRC2MnI14BK-}gP69WVLB9OEZM?4z?1N&moCE6w& zf*{8%0U6=K!15R5=B1!(Tv)Dyn7cu18U?;iFPNJlQO|M`6dZ>bK)dun>lDGE1SS|* zWI+2+PAq3(U|<2=sKkC=4W!Bpv`G(Sv>=GZz{UddD@!p*?KO}BmU|!*?*@U?Cc)K$ z+{nOk5ft1{K$fw{f}H!Rz5=AI8Ki6y=#mf?J&?;kg7!%X%maynEdoU!0}lfzm$5T~ z4Cc`Ru_YNnCh_U8D=>oY&*e`82`Ylw4E!fSp{T?d3Mw}EK{w>GD>Fue_WkjL?kHhb zVN3*-?DhOnASbCZri1qV@q=zJWLIO%1>IcC{}2?H>Wszg3=9(dpk2W18jO{o^@aSP zyR6wY!Iugv@XrKUq{Y|@+V{sV3c7P!o3Wc6bgeHN%LP!%W%&vwL7~gWA`Qx~EH+@$ zosGeafsF+eNNg;*U?EUQu(5!A&c?C|v{{TBR6^@AZewF$;A3MqV*JX^z`#F$dfu!6 z$@;mVAT$M+uuS}GK^!wMhnXK#ytA8wIV}7dp!l!=b66R8R)Ug%72{k`xPXou=ZFOb zBFh!f-kxM}&>lZ^&>lZpzUAWav*&S9OjG+4BYY{ zVHOT+CI$v>1rVEq<05G9u_DMk9*&8epp}vJASd#1oZw(!;8q6Z5Pk+W79NmOzk$q9 z2?wRk5N`EPASryU}FIlt1QwW7wCW% zYqEE68{7Z|V>{^LV)L8ev09D~AdVf#A&eZLO_1CUAT|>Rs2t~Z1i6-l!xiK}ClH&B z1GICP+Zkj92Zs*GY!{GvPL6wQ3=G_^paj9i3AzE1+YO{%fCIF#i`yN<7UBSHnB(>Y z=@sFSXJlZg=k@}{fCL9GNV7MHt-=9X48iRSsxk~X96)>d{6UU3;RM})$Q=kOY%DlH zBZS;RpuEt)z{bJ|3Ng?IV(wtjo9QL z<6>Zt=4Pm8;04u4oD3}NAd6yNg0eCXcTzA&^D2-~GRWZ!908!{N&&H%IK)BXsh~v3 z!oULB1;t4vh%Lxr0BS>2fr3Vafd#Zfgu4c`uTOjnJ9nKcXj5=fPBsH~ zJ&4J`@gL;L2GEK@1&&*w#kY;1$kE^cUCO}S1X|Oi!!aG?mu67fX{hIj0mWdOG&ci7 zi$oPO0|R$=HfX5>o5Tqarw4Sqm;svv=&~yAUQoMq13Lp3s6_;_0vvXX3|y%^3=AL) z<+HH_fVSI$!Vsh#EXvHl1qzjJ&_YX4h;uWrfL45IaQC0#W?+y6T@A>n2wH{->UD$m ze=*Jh@ud7f+d!0`@l3CqA0Sb`1GF6wv@ec97IcA_EMp9#0|Nsa3&=ro;6>v0ApM|a z5{z^BL7M=<`t3nRF$OV6f>+svfPxjI3^dHbI46Xcfk7b*v_L8Z6e(VyOSHhc!a%w} ztCgiI7#PDr!I)nS(k2Po2hIp7%|Q2(fm$?kYC)!eZm(d>(_&^|*aT9js03=Io?w~) zI(`9iNr+MtBLjotKQ;yimXk~?K;j^U3=Cj#@DM)tBv2Ts+~s0mxI3M3Zh_PE*b7CR z+s`iuh+v)jf#PRA!>T!!2oO3IY>eW zk=SRE*f*!YENW1mE>YaTqbdtp_Xsrtw2d5gLZu^;c;xi6OY_AU3#T7Eo+3UyCn}W3 zXf2ZTP9!!cxxkFLh$Q}vb^0P%HKplyWYr`Xlc(oKh=@;*iFe_dZX>70!?=1nqho?uewuXS(f);NW`jJrz)C(CT5BwsS~IZy~WkXNbVm{6rGx0i}7U zIiQm;U}{v5#0`+xHV`&sF%0PF5SWIL>2F0$#SJSU@?fvEAh9PPvB5ihpmwg9zEIRu z-1ZET^nE1uXC(H2B(@A_g&@=j{pl0MOvR_a$PMP1o@1ZD<5`I$*^0!Th{Oi3PlOt< z5=ne368q5fhvKHvxBS+raPL`*)9h7F}={79(FOnk5Og%(u3oivIvo6tQ zVAwHz=A{5-M!)HMF9oQx>IgD0T!xH4{kaq%z!)=~_i}(bE9gRL=&?{fmjeVC*G!KE z37ZQsFlazj&jATbOkWEUju&EJxH|n}CztT_Hz47P>3>1OCSnW>?b8oNaS2bixe_42 zxO@7<{l((bQ?3LEuzphlje{MuU=*I-1LEr`g9g{Ye2>Rr0*nRIk6sB-XLOtX_DX;{ z?-XkWhBu(wT^Se{)F4A(MyjA1r0|fCGAHOnybp{F3|iAaYN^PxGH5a|BtaaxRsD#AIYK z{bP~9)9HPGgaxL@g%m1npCb|Kz`|r?vHhM*sA>X=2@18LMXHQj+9xjx-9C9y*bHBG z$O&A=)Ato~OK$i65cd5JqrvoxeiFjWmIfx%FEW)0Gg%r;e^6g7#$;pyvgz3L3yh3% z)9r4k2~4*OQ&HGH>s)vkyN;0wLwtN%X~^E#0-gNXkgwhb1i(k%(Vz* zHWbIj+=*aSV%)Ml>0gA1A>)JT<@%AzjJw-s>ql;%tsgZ(4(`@GbtQ@IUVc%Bo=I2@0tLqR}GLk2ys13z(ZC z++<;9WH|kna+ws9xluc#WAt`L$C!EiaO?b5i-~XF8xS+agK^9DpqVk3{1_)sSA7xl zlaZla{$)(N{L9$w@-O37G{SVWpUaBhel9EFt`kgT`a0%hiS|=#6WUL$P27HJZPMLP znAG-l%*mD=jDg!-zWKg$c z`t`z81?R(Zpix{bwv^k3@ok?_M_>wzqF*MyA-Et zF!E2&ElyQ1JtxY*z>>}Q5>&YJf01KgV95b<82OX*7#LV`89~SLu<&cEGcd5^fjJ!f zXQv-3PF0tzl3`$ADPqh9bv{5xo3MNV>*TJP&Qy{br}hMN%C?BFHfZ2A+lYaINko>9 zfq_{>3gkzTaw!G|RtA=`>1`#c@~Ik{3=C{mtRPn~^6yb)U|_Rm1?_ca;@4GTU|_Rh zg}7p_J_7@rEttc>ub{}lz-9;L@Gx*U^D!{6*|U~|2F`a2F)*-qfed4b1C3*Nf}Xj+Gi zCnyF!fR4VI4eBc~aNC1A!s$#3prLTkxoaVyllHcPf-;W@q>h2V05nQb0JcDZ-wYHO zC17tU@f(ANno5~IfX-dx{{T90q6}4PXt74BTr#!?2A^37~<9DS8YH91EF1_vs0)VPjwr0u$hP z_M%_B2HV&E(!1{k=-K*{MG6KK;H zcP_|$4rWkXbFUF(VBp|n21Od51cxYd4rqK2w3ePjjQKsNF~=XK%fP@P&b$^h8^WIh z8a|U?)&{wje>q4-k{L9a#KX@HGE|BgWYyj5G0SR^oFo%5f&Yl7i(z3=AB~ti~|mFp#kDbcL!^P7?<1d7x~p!>wrpc0Ccfg5yv zEk_;eMbJuEK2DBC)-<@eO~~dpBb(cTY;G&WTn26jQ1rC1YJd);jNs^G{RlUy3u+R$ zWb0-Hm9K34`3j)om=#nwaPqq|)-y10^ny!yAO7DU_x6FE7{D(E@?$^Pl0bgY-Q*k- zz?>j{dC+k6M6knx`Hes^GYQNIVc@pXXJFu%%nCZDlFy4{8Y^g`0uox&k=-%_;g)&^ zj+qe0FmRiI?4QL7+KI;(z%iE-R%Ez`%VA6p{y6e}Z&-a~xp>?Yx8d{wT8UW5~LXLp1Y)U3UWPIxhxp z&>cz~Ct1yS7#R52InJ;yfxF`@)Fe=i&2bJC)AbB&4BWFoMgDo#1|9|m(Fl%2(&?82pqB8FF?vZvw}AH2_6EO0})=J!N9=5#s)HqyAV{l2twFfK-Ib! zn9aw=q0VLpIt~_G9%!(E$^!;Sd7uea!3Zf2wAeuBW-{?Jf$BkRwtA4E%>2t_7#KKo z*v^4Af!5xO@^E zE^IRV3=I6%pe*Rh25Q$Z@LvPfv~FNKSRf|3gEfmV)N`|gDrgV3*C1DkaCoz&@iQ<$ z9OVPnz#x#4S;oNO3wDP9#A-jVZXt+K{$P$U1NUuEGzG9}@G~&*NpJ+SZGgKY1mX^e zNugkqpzf#-1M6mkI58Y-BRd1P9jJ_pU@HO{CC(AW20G?NAhRf&fg>8Mgn|DPC>_MG z-C+WS)I?CZ7t02!5Cj>xuYz(*9NQj#1_n_Xjs!M)0R{%Keo$IT1c$j;Jt+8+z~NLc z#sLbbWUvil3qhq=3OESFu7UDaD%cYY+^wK8DUIzX$UPh!8El{fO8H-bjLZb569#@3 zP~>KTC0H1ESwMDjH-X%k&E_otItP>^m+d&nA>e$S2TrSEtF=Mpe?B;LAQ`d*oW8^! zgWA8PY`2&h7$mY&D;YS-*-Ale1@2p*CRznsqW}W~w+E=*QpL&yeuF~`3yLk+4KY%7z8ql7&uxWK?n}ddX82wPe33gBb$Mv4a`ws;Jyl~k2~1@ zft+r@(Zv=m$iN^r8Rz)N{-Na~Sv&K~?u`HqdrT7Jkqm8^;_rc2ExB z{{t%5=d$q%F);A(gH|DN%wq%Xv=rd~3u>j$X9FD)C&F(9ijGBW@$W5$Z;J5-#)eHi;nRyHxSHT=6eqB%+ zx(4R3@c#rw-E}aBjURN1HOCD$=X#J28Mr~g#c`9(Ux+A5CenY86gG+ zNLdLQwi5ys1>j|d1`7&z@f zY!-HTIR*w!dyv~X7+AuL7#KJm(uElqSVRmM7`PljX0y!DVqoC%05RFPxLVjm7#P?= zA;dNPYfGxIBxsc?R}V;*i9K1Bfq|FJ8CsS=7y6c`w|CTtaEU|{p$ng;6a zus4b`FmO!=sbXM%B{V&%HPx!#OO1hnYc5DkiCtcufq`otsE}6S04-VJnh&y5jok+% zz5pa{z>$_*%)qq}WUC>2rYHjg*CLR(5&Ios1_rLh=a?B7OxRnD7#O&gfXsAZU|9ol z+EPIg1_qWSIR*x<^&oMUZbJqJuHBD8OIrm0icJ3#?kq9gpe>cHonGSbPRa}nT>tifR9&3@p)FOUJ`i-uF*_s3R_;@r3=CWXj3BeQw}DhjGJ>q+)8SHJ z>=R>P;E!ZyVBk^&vl;krfK)3nP7z~ZVBz-yd0Clp7AV>Ci_0=FaH%jZ5Ci4)8hHi= zE>%X*hB^WMeIR9OjBCUg7)1DmjTji}xzrgqiGeaZ=#X754aOZ}pjBO`DOd!wJCc{>BAESB6tpk^wETcem+`A8Xx$5!5u=GX0|WmvknfGbV?_-7GlUoz zxJrZ)H3ndsBL@Ghs6+}*gZVVFf0$m#+vQrN$`-JJ%U8%~dF2W29 zJS#!5#=(A9kb!|`6^PBr4!W0uXElh;#V$I%xhqw(9u!Lg?6XuE7E?EF!KDkE)6s3C)gx*&`vm>U!ZtnVb=#ORr>={!oi-c$iTq!7sTdaUk7siKagnx z{2M`4I0GZdIuU+$1qKElMleT=f0Yyi0}nG}45(h0;BN;7Gb`hFSq26R{^is6bf-$z zbE_~g@bH1Ng&qGpZBY3D=GgOt3Sk~$Fvo!(G+xUi$_OeTUHI)mtJB07&x$ZG^zh#l zXJFtF2g^+0zXUq0T9OeIkT>|RgPbeH2=dbtekLUb1|Dg!v!3w>fKJ(xWt=a}P|xs! zzXqg9j&YSR1H()HB_K`mV9qOk8IUKHzy-i-etS?HDKml+&led1(4`eBVB>NaWnO>` zR|WI(7-gzK3e~_4FJP2OQf6S_Q3t!CkWt1FWTFO`SHvh22TIsHx?rWnj55BUa5Ml* zmN3e+$uThSn1Br}W0bis$-uy42If^TGVro+gAR-ImS`?5eImDjwcRmk_NwqA1FN}FdEA-FzE2}gOYd>qplnSg9$%q zlz}H1tjU7EV0u+=s%rgGPz+{(-J8G?59Z|Y%YlNe0L&@i_W&i?BCwt!{&;x?2A&cyrGP1Y*7zC zXoV$D6UaD*K7P>M?L5tlQ{@;KCh*IF(p4KHXvf+V89|WI?O;73j545cOr9<$M({u; zqYUUg9-baXP&Y*!8aKUQr4o!Xk3faSWU%>Cj51nA3=BL|!E!Q;GJo`^-|tJ+sMi9; z^nAwEatsVAj50x>Kv@9R;Q@-~M0u7o&QxGv;6Dpme8#f^Yy|^-yBCV`Hb-^{pEfq~%yzf2G)C2nQZ1*N+JK^b>Ydf5gJf)YWQi=gs*2iQ#&f-=R^ zmrY33tOwmv&$Abtz8VB&zJqF!ec&9?A}GTGirE82CFm@m0_Fi zH!)SZ{s+kDYm7T27#M6sWzK@q@^!EVJ5iZxP^jDh^BhEFIzWm3CYa|WD)SnYtZsn~ za}kyK46^7h<9!7N1`ko0XpotY!76=388|_41`0B8JTftGf>IGE&_MiP26hHcP+|o6 z6ePgF&cMq8(!nVt!N34A5G*Rsz{|2xl!1Y}804lWjK@Lqa+^VE#TZ;^a`7`T@Pa!7 zES}S?C#6a%99Cpt;0JB$<*fvVI|D!H21MQ}Fo%&}e0s^GREK&^DFz1K2Cz3c_(6M9 zcp*8Ni+{HP0|Rdp*b_Yb2W1%;c$>jm`S?w>85nq5z#M)C?jkh?2HsXi(4nTBAg6#% zxdl6!k%1d@YbviKcsQT?JSg9JGJjWOU=Rn@8lZzjh3dh*ZVT!B@XVnSp_Q21tDa#7uDKz7fP`VrLYazIk%0b^SLT1_r)%keC2RVp;(MUk7Lh zq!33jh}{V~id2{#bhZj#H>gw+Vb=qx2luW-+0zXe82EZYUKeBk4O-6KC&A3XAkMx; zoq>U`|Dyr}gB<%^H3kO02_SFFvonB3jV6Ms3kCN50t^g%lfe^94(vjD3=DizK<;&9 z2OX2cHyvbXJ-Z@EdXh;_O@MAY0|Vb?kXzU|__iMaIp7AUZ?OXu znGEc{)6Y*$6|WBm#n*0-5E}!Fv^WC;-`;l6j5ugd5#Je5@UX0rWMJUC3}&7Mja%LV zGtYq{^e0Fo9}gc3qp2zb1Amkd0|Or`n9aa%Ed%PvFoKdI3%?U6M%ckQgM;5dmw|zg z1I)4HWZ-21`J6igq=J+2JIMc>eB6w!AOk^d3qBrjCS>661UZ!#%wgm|K7HP_RKj1vj7xQdW`&_ z;SC-}8PK&weEN*M(|xC>O4pxOVPFttlmV?m;xh%e3MCk2l0m7+jPaogxbD3QGTV}| zMumYvgHa|5lo+hRK1*Sg0bOmyX9wn`GRkCuGK)RqL{$ccG)9?6AbTCao=RtwQ3TEP zIx>PTZOvemxdn=FC&p{_Dhv!Ij544T#`&DV;a|ZhvkEln=)!nS1=RSKIV;A%z~{~g zI?G{?dCMumal2BSxVb?&&xdiYDgy(HuLJ`_CcmzgIs*geY6b=dFPJ(926-1oe!ogkH!B6yh4%*~ z9R_yLb|n4)5SxkpyCDMue;|m>!XBf`z`!2_N*QeItJN47_=7<+UOeoe>2UrK(AoI> z3WuhjpOGqQDyPH1z#jq9#>1%K2{I!RWDOsqLNRF9SrjO_sxc}|0}ZuDgE;Dp3iGGS z&PZM1A`4Cqy*^)ExiGiAWYz3VrO8<0QsU46d>{yjQlPC zG#MD!Pl4=j1u+@eH4PXT_}f^t7#LXCAA!2j9iTKRz}^qi*9FSpBJ7~+ulTz`;`Ju% zogfXpAPEchy`a(YK9EENdnE${1OEh&cnmwJn&h7d60czw7iM7Kp9~UjV6OnFp8^tJ zz&;too(2+M!VYpa|8$V}5q5vj5{p?N@e}N(ppcvm5`V#dRfU0pzkVKQHNYEo&?ON3 z^Fb0{*vmn!tVJLVKNN0*9I+TAF2Se(nzQ6z3W`7(Mg=Wd1_u6>AQ=Tlg=1O_4E*4t zPlZu|3zRO_gBsFWj0&LPVg8MvVP+#nh1sACy$Lj{k;JF~nzH1t-v^qLDPmLrO>Oe; z2TjWsGb;QSVqoAu0E*8NP|^i$9^e$wVqgGaa6B+E@UrNDws%#40^{&34F(1_9{wwC zS_};ApiK+>S3xusb!nqJ3CdJ_X;TJ z9)p&1aInvxzHxS{M12lO=w%=%8dD`182CSel8C$rKmX@q9R>#Wub_1O1>}1McFW?4ULB{Qp2~Ep~TMqW=$K>+t^o zxewA2)??z=o9;CyRe^n>7N|Ehe|q7ZRLT0qAm8$U3ppEp(3SyyUU2c}z#k^Uz`)N3 zmT}>a(`R7d=LgGp@K=MPSpY2K!!H1eCqZ!O7r+myQu#%|rDOC$0Zmmbr=|GWWIrtlO!VtD+9wHKAH8>3=I5IjGzT8 z?EEqzpk9LvNE-tezYOSdIDT0$kB48z50qczz(pe;zlW~scSr=NQiZXD6_TKStWLyZU@iO?gGQQUZ z&$eVU@NZ)T@b3U~6!_PGIJ>|c1OAU7H|_>=0v*5;g8X|K zK@)-j;0Zzgec+Id0MDiI?+0_Dz!P!&2f%?91D>MeKM3Z;@;?Xp`w*BD$Dcg?_q8Z82CY*SpL)CPAnV$RZygz z0dv^-K@)HMXTi!i__u(DKQDr<;^Th@Dp@XpIsE)*LCO6JSeXF-gL-BL2L791DKYRQ z8vk8J(9Eki|2|L<-2;c61Oqo0F9QSr1IFLF3=G_5pdP?$upT)JM*feCeW2tq8B~aW z0<#(TYd~j`e`cIw02;RB1WA8k1U0xg_(9{9{9nQT<>9|7R?on||BZ2$0chqBT(Nxz zhoTI4aT@;*Fh`CbT%P;{yIFxBTpa#l1eJ$s{8K=Q|2N}p&|+qOKTxgn2kbCQe$ZKF z{CwbLU{?GEASVcbmx0;ve*+bBf=r-Vu6Fvw1*y_ZKjo*dTaYTj^p}77i3O>uj5gEX zEl8F02QBE}H)jGBl?%Y@KKLz|Kt<(3{(qp#&Jw)fY!UxjP_$ZsIg9zPf(ik9u(eD0 z8$glk0AB62jDPO*u!X5=^>0C$(2HrZ9s|QFfux*N27X^AP&BWRnF$IsKPFIHQ-@LJ zB`BALf%Td&%0!BT8i-(?DX44)C3jwysX7dh<#MY)y<%{E$-w;zR9eL_%?C9^Liy8~ z_&{|!XsHW-CX>E8Xn2?34pjVQgI(;%-wsOTIbfrm_|Jf1J(r1@iGjhH|KoJ^MX8GQ z+YA^OxOHV182Br}s`!lfXE4nGnYtKM5X}U$8Tg|?o}I-6nue3(e+@EcHaHkG`1wEy zcrKWu#jgo+-aIfzhaa?aihn+sqsI>}bQUs688R>!@K4ufVBlW_a$-G$ApjSAZQ18e##BxNt{<3Z<1yTMQW( zxVM6I90AMAsi^ROX0kM8U=RRp8sz^14l@S+{h(s|CqGywOr{+aA-|YhriU(0RjQv1 zN>TrqKpitT7MXAm??02LDFcHCi%c+RkqHa4zbONQ4~vWnXw3{ObG#`7!xI)6K~T`M zfxE7MSY*mTr42in_m@RxE65ZcW+~9ALaZ{N9e4af%%HYn1)I!UP_`8TkMM_Z$UFia ze914$3@VGlIAlPp6Zplzl5rd|pcM)H;$TA)IAlOa1o2BSgSzcW95Pm*v8hULtF+l!pm>Q3~CA75SP&cC2Dgp?~b_4D^Pi60p>jrm$3pR z5=*c{pNPv8fReZsGpPCTR9vQo6TEN&#Cs+#BL#A{4Os5ExJpF)L{z( zTlhg)rUK-cU}jJm_f1(w3sfP7f^GPzEHfKa6xWA=xxbWUKr1Hs!@<1Y$}(-BIE(;? z#UEvv8=%0C1oQqX%W#A8OcXO{oSi{M#sw4=(O@|q6&Vgt#S;VO@v6w&0m;RJRSKxc zfOdZICopd`Wnhp|Vc-Ncay{!!q17#@NjMv{*BO*ML1`S^0AOO^1g(Y#B^MYUqyvP( zd{7Y<2A=x|m0X;l(hL+vU^#XMPLLodT%dejmK4zax}YA>L8!g%3@i-XlR@p;B<631 z3=B$&`V0(=$3Qbo44^c_IOmfY1A{VX!h`V`c(@O=>|6!Zg=ahgu2nohr>y%b`lohE$8cF^P3?1emr+}_;Q3K!CrVi?Tfc1dx zbOLEP2G$}v{qc%asrp=yX`oAW;9|@{RBFO#GiqI(E?#;G@~JdDib3E zL#sangD6y@gn>Z=G&VHRAFPnkn1MmlREmLtF#+aTP>3+jNwtJ|HUZ>WdlAqMq^&w2 zg`jpi=z6_8P@nHd;xTuqYrlRYmhaJ!P;{`N65Ybr4Dfx z1_p3e23cZYgBtXzQqTnLi6)^AI$>?DKLdk?186(K%IRHeQ)L;0rmt9=YE=KnfPsOL z30$7!urM$vp8}-_2)`G^_mP3igU$dk0lSO^Tplrom|O;(hsMeXszn*YRYB=?t3Lw+ zyDh|J#S9GUy0G*BO0b~xkO+}vG*n}ZW@Vl}cYP}7^rUsEX7M0DRY4?~ilNC#6?AXs zL4O8@87LA4pzLqNpxVg5z;M=|fng(57M==0JMKZDuL^3igKT|a3yA@q^{K*EH~kqH zeuK3{Gnz1{g68Kzrij=FkN;-sub%7f6!hU|W}rgG z)*kE-Mgs;76($CTKhSaq6k?2q3=F0Mpkus2_d78#fQnGYIf>J!Z-B*R8aOUNr+S!y z;}XJW3^N1AB$O8piN_3RJgR`>F%uk*pwkyrL3s!iA3q^3LBt2BVF!v2aR;yyp%Rez z&|^@wghq$~R2m+Xpt=eiVxVL8K_QXu0Ev+9jj6)cpa`h~YXL_H=sq`4giHntL5h2D zp$97Kz^2TA79ppgrsS_r<&#qdZQKB*zk5)9#S9Fppfe#r!OJvVYE!Cw04OY_9Kmj9 zGy!FPLk4xwHHhFE4^)h=^k-l&hbRD*II5ts5mfaAK*c~QGltQOK|_m?f#HYQ^v+GG zGK^u?TXbo)u1H)$|W5JaV=u$FJiJ&%J ze{-rHQ;_|1gUzWL)7v+v3cIg#W?)bTd6JO_+~EjdWnfT_1Jy)4;9dY|H8Z5J<6{Dq z9iUsH)Fohv7!-A&kiR_r;pS9LWsv{|hUZS;kYFleU{Ht0Pz*F|Rh%I)h-* zg~}vCW$L%2O3H(Z=Tc{gIVB7X>T96(X+WxEh#6?ItN%6?73-d3=AszpnEg)!SdTd{LJZwTT|tfxaG8E_TdEwlDyWsB6Tram-(|Y& zwp2+r5L?a_Bq==Ie_JY>6v%f*t`Of9F)*ltj*SDE5Diu&C#+ro%i=B2qF~1K1=~{f z85O2q*p{kTZwYc~6Q~mis+t%Mfto^dOg&%$(F6_%(1nALEZD*XDoS^8GB8+yPI6&v zWdf;H0nI%ywt@Y3gOh*be4@<78kkkptCO9gvMz69Y_+fJ)^~P?DHlusu~$ z1(YY!-N2q;F1o?MpboF3L8tA3!e*WuB%Tg!PZegh2w-5?H~rT3ROx!h00xGO5S^fw z5$NPL-v9=N*AOA5i2-Vi(M%J=7*vljK*}j*cd#|!(jBA&bQWJ^00V;AtAXye1vPL%U0BQYprb4-4Hr3Yn{bVwbj)GRpbn~7KsAiUDsWi`QE#v}Rgrgt z4+Dc4*ah>MPfm~9o2sG&Y7-yufwhU%K?j9^^s0ig7s$SOJ`nvo_om9!Zw~-F5|jp^ zb7LT_;C8GegC59qBT&E0vy($ab+{mk}O6DpE20XLVZiaV#25r_vrq7axKE3LK@~I$3JNb9U$9ePmr<&NDkG4?H9*xjtgSkEU#f}*NH^Gt z>I`}y$C!Q)U|?W;2zKHuP-Ak=5kCe728YgLu!Y85U7p7e z?L&anL;Db*`~YfXDEon(gXlxR+l-*wR6zlmMD9dz|M$jPc@;CNzS z*bG&2ZhxvwJ+BYULcYAo5h*#_%SfBK~5&po6E?+V7){Zv~is23rHMXLNkEH zZBBru@A#OWDljnEh=WF$bC^LLcU#aI?jX#+mDx^Nl7Rt)1%hqA3NkQ&u;48w+gh!9 z28LSDg1by6+gMEo1`y`UWVB0_VqgGaRv$aitUL&_CfNBfGcbU#keKa!c?Jd$7QDb@ zyHSyW0fc$fm~3z8Fff2Hk1CVx3?&8z5a!Ebv=x(KU;ttMbg?eSoozaXcZa=^G{{A z%`s$P0AapejJBYg#6g&EA)_rQiGnbXI+N`rNd^WG=CNS1oyyF>0K(JL52mUnd+RYU zfH2=_M%#O;3=AMFc$&#>6CVQu2n)Zk1s#V6!hA~^ZCfNjCvq_`@XcVfb7Wy)0AX$g zTRA}n1`rnf$7Bn-S^QtlYO`Ekvrt9lwi*DcbB~^rVy1_#? z`RRN84F#sx+%V4Lgx5=@XYJH#0cr$5-!bYl8hMn=Wy za_fQwrgu#(R@z>nm$sSR!Vq+fgPU|?foU|@u@g{RNVPqX$6MH0$FVwWSaTanlkk=T2X*e9pU7Nm(Ag07{8 z+3*2L`VSIYkR9O)x#_6|Y3`DsWr;9tO-R!H(~lOUDNAlg5;}v#zB!$-Fil+Y3z85g zsCtBYQEa+lVVbfeXyX;kaM1avFn0X(!hIFuyyZwbny2@2Mv2?bK@tLA!3j0+ACfru z=qRW-=)6FfsTI>h_g5&Zf?7{7A<%)uF!pUugy&yO*DXrZmy`t^vjjEC2#IY!y|gGz zSu!0-s0NAMIelYMTD<2cBq7jgdN7MbxDgg9BC++6*e*!y!0D02Y08Y1(`$><#3g4T z$t*`=Z=HVdOS-t^J0u}y(D6r5=L<}~3(~EPBm}CdVQ%uB&RdeETwjVL-G#&kAJhaj z33NCUOdI$>CaCx^B=wh&*!PgwuaMZ^kl5h!n6x2xtTFI`hHIdPf)8YZvel5p!G|zG z#X*-u!W;y?5fUoihNOPY^tV&u#8uBD34!lwgev`jB>s20YiXLbq&*)ZmO_x&iPLA6 zrYTEyA_=WVV(*xKwKPrH6MUT^)bOuJ(oCTCK2)3^i7ku7_CaDtPH#M1AH!NR zwhI!w7>V65U9lofTyi#&&~ha9+3B5DF%i=Zk5y>r#tI{xRe;2kfuT2*;U=x>oha|)HWIrGiQR+5UXH}xG~LmdONJDtF()f{3e*gZ(>8AxpK zC1oHB7#J8fAc^lqVqcJCU~q-`{soc*xE~AE%meDvLfMi?Y*057rq^(~?wJa4Nlzqc z@MUCBZAsHJ>(bs!rh`VYphBfc?B?mRXDh@#=OYQNMPlzpVxL4}-$P=*L1O=$ez86+ zo;MdXLJzgAYPxMh+V%QW&}~dmp<*OyDU%fN6I!U1R5$4Kmt zNbLVeY+g{09BL5gIwY9Inn>d2NNiUmHfT8mOnst4J;KMJ)h{rKS|knKNNn&eMo^1C zA&LJ*VuLnX!^{C+Sp-!N8UuidgYP5)iBEsnoK{_b1T-TA;)1SmLt?){VvB%A9HD9y zkk~p%YzriIC=xpZiCu!kZh){MkbVKw|qKu_KV!DM;)BBz6rFy90?m1;z&Xe*uicz`(EXe{4%rmb5_<3PfVZP1kKtQ)X2ABJ2`?upuEN1L1%} z2y`4GOoIuMxC0W~2Z}i_Q_jRSk)k|w39HxiFwnAdNBeA29 z*l9@YA|!Sl61xkDJspX?2*OSSdwd&&17;sWVxL1|-$G(PLt=kIV*f*8bAe8vgk~@C z>5M&Tr|Z8W2{D5fvp}Um%K%~FE{`Oxi^R4@VtXR7!K;;^=A8yQe){-BPgjn?u zkt#GjvM()LwF5~AbVMS|zpIeMw@-iBm-d?%v}zV6{b>5f{ZzCV4TNQO8g z-*iUN4DotR(5w*DP2d?KDBBfDJQ#_ch{VoEV%H+EyOG#4k=V#7;+Imm;y7k=PTF z*z=LtYmwNyVQi59Pr^713=G$i*iVtzpOM&%rU;+$Be7+X*xE?!LrCm%NbIYopjHR; zxc8f;3=G0h_7fyU??G(n)wN$hY-k$(4`M^bS`$)!EBK885k}gv0oywnJf?<6GLLFf!I(F7=YNI16&vw7)&e} z7(iDMflRdri9^+Rg4j?``hnQm&>H|EKpdzf|2T4HLH;~v5k=WlsY-q4ESTZm$LfM>1Y%vfU zYK}Y-+Z4oxs<(r&r|*4M!CxN&;zG5gf!I*D7J%5GwE+wa3?-Hf48l-$JxCm?rW3@5 z`lk=XhKkPsv7zE~L2Rh_au6FTz6QjGMZz`^2Yky51H*0*8*14VB=%h-_Gb_q>YqPI zY*s5oxCnvRP;;b_*oGiBRIim4C=#F?XCw(95F6^CNDv!pP!bZm0>p;uZA4;sA+aZe z*iduUf!I)Uu7KE}Pyv;n_dp!b-9iiu43DfB7=)qhw;*wlA_fMA?;tib=>CA%P;oYE z1_sbBW>9+P2C<>y5+F9z96b;lDsBN{gO;{3FfiCyGceQ(Lpkms38ErO zPex+rg4j?sMIbg*O$~?*6>kKwq2|v+VlPLq>lt=}IM84`gv36L#J&MyLoK)mVuKdY zf0g{L0cRc7#MOL85o42>q zhBYEPKpdzV1L4{#cL1VRuGU z;Q~l(NhG!^hz&JJ4~gvpVnZF_i^L8?Vkd#vP`zbPHYoiu)I&L-;F<_xLk*gR#9oZV zUIk)9Luez2Eez7hz_8Vsfk7C`J^&JjsyPi}LqqW<68oMrs1SrIdWj_Q4#b9v{{*q2 zn*V{=P;pKdMD;I$#FhoIp=vZhY^Yvc5F09P0b+y2>lqkqK^&-r2Z#-pU|{eCv7zD- zAU0Gy7Q}{%XMosH@mvra>iaSzb`OXR4biDc?0Fz|Jyc=`hy&I95Q)v;%D}(~6_-b1 z8zZq}kl3k6>}n7jYJLk6yBCRFKNG}(TCg9)hWhLjhz(kP$iTpG&Xs{d7|Om05{IgJ z0%Ajb{}RN8ihlvIq2fP5Y^XS^8=^fT0Ai~{dm^GB4pfl>hz-@O3SvXWO_12mNNhh4 z8>&7S#D+RF1BqRT#BK+%p`kLt4OIR^IWv(Y=7ZQ!gZ3k_FCnqtAhB8885kI$>cx@R z+DL2@B(@ib4YC)M|AJv01_p*0Bz6*r4K;Kz5_>xm`v4OA8i)-tl!1ZaJ`(!{68jy9 z4K$Y-q5%gV>;ZQy3T+yge8ggvF-cTaqST4-N4&kTg_j9f%DT zZw9fU+Io=K3y|0=k=Xk|Y^d8$Ah9nZvG0P|P&4a4B5{6$*ic6>c``6CibKjHHctiy zVJKS=Bo0+017brRssv&~#Wg`}&}I+@1_oV_UMSlMBo0*{2w{Wbje#Ky#DQu~1hJut z(m-secp-=l6)yv^q2i4oHdMR~#Dj)*#1{}7D*hkDhKjRzBg!lx1iPL=0l{I=LtNNRtK#Qq9mLk;?e#Af$_#vcO%10RSD z^|2_34cZ*Zz`!8s!@wX6WvhV1p=ykf*tYc`4%C<4NbCR*8>%4+#8!ehE*`{&8k&K` zt^={54sAzbPe5YN1hJv!%m=Zhz?W1rFdPGMpq8Blu|c~l85kHYf_wmF-vNn3)jS8W zp^kn7VnfA$A+b4p5%DdC#8v>YLAwAL7#LK2LG2c(1-2jwDBBH*9RXrPeU^yC&O%}r zgV<0*r-9f|2h9bsA#(r>3w~$bE)X*&;Hq_8lAU4!DkC52E zkl1XXt?p1YLP%^eB(@xc4at8>5Dqw8G?Cc4NNiIiwj~nV5sB@J#P&sE2O_Z}kk~Q) zNGlnVktEWQ*m=_n*QANpS0M@2A+g(#*j-5MNl5HzNbGq?>_tfIRY>f0NbGG8HYA{S zK{()mI)ubNhQvOH#J+^YzJ>W@@W{zZ~t3_xUaP9!!j5?d6B zEs4ZdL}IHVv2~HyhA=kB|CTTg0|SFC659!h?S{nmLt+OZv7?aKaY*bmBz6`OyC?uu zQ9=`R8InXT61x$J-HF8RMPg4yV$VckFF;~1L1M2#u%#F_AUF&=kl1^+N3Ku%Y{zux z)pWmiX?~0b)91cR^Jn_-dipyMw`98Q`!s(>nd!YCN@Mz65LGZ;_d}XLruj3y_%MCn$2332In#MRrTH`NnH~$GG^VcwQ6|&> zeoFIay7PIu-{&+x#)Ro}Kd1RKZkhfTL~%^F{gQT^amIAkuW99sJkx8xf*o)cM0re? z{g&p>^yc^Uyl-iKi~`g5egiv%_j{T@qr~)B5alv`Er^;k{qJ{>N0_Jk{Ydj;JTiUm zk2HU#AMDfL{Ydj;dciT>?q`}GW5x8|pK1P#0n_h-sFLZrzta2}XH2gJQ9Gue1yOUR z%l=ODXSA4}`#bGDW5@K^KWW;GN2YiFNmFKZkz{0Gn7$Fj32cePM!p9F1*MnCOlo{f0_WJ%XHoUY3i(jR~Z=gOjl$QQ)U#H zUJDZW@PvWk_4Gh{M&apu{-+7U?``!<&=lYP_J7(w4aNi0*Jz|`MI2`X-D?WI0_Hdi z1A{2^3K-D&9Sow-D_}qzCjNZTJyX}%KpYl+JIdD8#J~$O9CTa+ zALw{629^hk3=Ax%y%-r7_@^08KcM3vHJxoymJm~@`t)}?4pNNQr*rB$NJ~xxT{Y{( z_#dRsOA35>EtuUn-B#B@nsN8^)TxR0|R$0=x#1W(6LJl+&Q3Y?36%k7H($H)o{wE zK{sk~gKh`mP<;qG+MU}CbRC}BcUA@l0q%Ps^%~-A3=AUNrl8Bnw3OHw7$ms6K;k;O zYzz!C+~9k_be-9J85k6}SAed4(+3%34C7U(`vUl6;1`#B#21BbtoD;ont3HK4u)pP-%>{7wN#sW&9TwI*uyFp>g&dr*uu7`W6uK(W)$!oZ-wrTYSO z>nscCJ{>&}lY!e>h=GAiAH-(i4rOFu;4*l}#=yYAy#aI=k)bZ=P8IHVpc{vbKx_f- zR*-sQQ0fx_XCy8Y5L*ItV*vw~Dd=1l8SbT^dy~u<8Kwwp3la>z{SI5 zqr=X?zzsT2iVJeb6t@}ZvL?tKQ{1ybmfC|1;b35in4Y&hOTPXh=-@~zR!|;c6q>Bb zz`$+I3R1x&sIZ+SLk^s@m;-Jg`N@vWXUB>mG+#oE^z`!bMC(gjY zCJH)Eie0n}RCb?h-(!*C)DhFfj0foH@OFMHWwe zJ?OOiCJ>(mbk-wpYYymYJOPE z3=GoJ&p{f@m{u|}Fi1ZG9lvG{Hi&`0XS(6aERp(?+zbr7HcTLE8HCC}NB`S`IgCO) zpsOV8z#Jx_SLzH5y!K2Mpc|%zy0sV>cpbnpEJD0I3=F)EVB1(3_5(4`z66_rgA&u#G zS7u4p-_>Mb;Ee&B!7DUfm4SgbmPv_`fq_rRL4|>VHx6v5fY3%=1_s`Eu=6B@?t$Ez z$YcY$oJ}ZJfq{WH32cCrkRZr)$zYDO5F;q2Qkdd785m@Qet;a33YL*&;02{jYc2)` zfqGEo!pOjH0`g=!Q#R<1-3;DbruiVR90Xl!kjDg4$RHFC3daJl3lxOhL9t!}_N0=K zCnEy`Zz+>C=$sWHHjo#}!1kmHtpk}_4(6mW@PoRkyj4u@Tnr3?OuThW=eZad>V*Pj z7#Mi#nLvr1K`000=LWC_Mh5<`ObiUXjZCXSr?BoYW?0xfq~;Y7Xt$)m;k3E zHWrWz1vz+6F@dg%5h@g8VBkFsHiSWF2^Rwc?-?+MQD~ka0|W0_NNh0hOYkx<)bpNW z0$oVUUjs6qgBg@e`1ynx7Bj za3z?-#=yWU!R!nwJ%wI^WF(ohLHCUa>4FTEVg|WVKNW?mC!JGe=vP?KhYQi2)Sr;I}N#h^IVDV4(g6pP~Nr&YvzCiy91cR$-ut>lnor2y?7WHq$GHqnQ!qhFi3;L&;@Lgv=}G} zxz>XNSGo$672Uwzmi7XLg*({c(i$KOJiyLi;NJ~O4xY?YKqrx&1v%S~`4i~Q!@oQX z44fc>fsF-Z4F_mDF()YY82H0Mwg|FP;?@at=praSz(o+}#p#`EvqS_pfKrS! zs~;}|16Wng^mS{qBn7vF(t$E-1x$GM^s2R4G6D?zcR=Y#hjlsVYUVw>(>Gc=2n%(B z3Ij9N6EMZkc&BTw%aW~k1y>OKI-pDv1YzF;c_atI_5|5c3T6v(@m8=V@-Z+7EdkyC zQOOD_(-?&EK$cape&S_dU=!K|%3js1Tzm`+>_SgLcgxkV{sTEfXa%SosAUBeV4Mv6 zVxV%qj#Uh_>_w21w~-aJV;N#@6SBF@$mX^no7)O8mw~?wRHn4C=JGKx2uARBvYPS3 zT-XIQ30$sqvx3TOHlZ2Hpz@v-R2py!<$*3>=IsU7cRoTZK?Qgp*ogr`KR_|q54I#w z=s75KCV)9XLd>92d?MIk!9qo#@Ra*G%5G}dCcTc#tsWd_16 z^$ff-A&z0--wz6}S*%X{3=Dz+ymMJWN904oWFE5a`3T(%ybBnYs}bm4Rd6x5jTKxB3MVu0ZU^53%_v;Nz`Fy?6lCC60M!*cSy=@b7zDj| z_ppL)iG|p-7uo&$klkOuAL0Q9elL*k53qtx{t)!$J;J&ZWGy(Q9YxlC3|aSah-OG3 zeFE${FUbAqyeCSIRgD#-v?*WzZ=UI;mFfd3(@Lpss z7i3_Nb_TiU5;(z2PXQ&~%iu&R4O#}vdj*`#q_=}=psV1Bk~RTl(re%-mlg#jvg_cW zmaYa>);GYRD18}}!ft{CM!FT0Zf^yF{V5H0&~30w8Tdbe!toC4SI|ka5g=0^vi1u? zv;Jbx9i^blm^nc#1~wLuTlp(Nt)M5YTS2$QpPDYXDNCfD6I3+4VZ8%FK zFem7UK~8W?^3MjT`po(VqzZJ~EL7MNRGqW2fl4I)LQwS~2w{Wn72p*Evjy3B)!CXs z_p^cv01Y-!0l)w$05sVc>p_P%K}rBE@SU_wLN`JAMjNb|S?D0BMAZS`W6L7+1k`fV z1#?&#_`^W8k{%oA6l6gbUL&@%AWM#cLev<$5l z)qY^jLJ*Vu!5m=*{uYos0@!jvCQ0xHvwelTBcvYU5QtHsV56Y!2m|Y86Z#3N@58}1 zvNP~2fg&e@4OFEFit|RX8Hq432!n2%=8Xm`VGw!^N(V7)pd-8lgdT$mx>z<)4Is$C zzXepp#IZ4oFfd5T@FuXeh%nSMNM8Uq1HoY~y%$tTB!L4;Iu{gB$zU6#7lDec6mSqo zKLTZ@RIn!)_=Q**7M}dLg3gqDqHfK==1}OvHF17_Am)`-U?QXC+GO0xj zyggvm4E&v-rgJY_J?I#DZ%_+z659^YE$k;i4g%#`&Uz4&fsF-ZjGzMVOg0BG1_q(i zpg5leW-|ztgX-$pY;K@iXoVJlN~1Y!KA_7lg|>nUpt)>8pj&8#&V#Chd2FD9NI>X6 zsKq>=Ee>=Gtxz>6f)}xY?hud=VgWg030syJ=*DR_mU>Vlhm8f)o?&Cj0ksWS_JB!H zS;WTDEC?FN0$n@H#T(1|6Y5i+0- z=2}D0Xbb4DH5SoiesKSi4P0@7Zerry3r^nr^|R#}7nY79n|1U|a`t*o43xv>R*(Kq14xzYlZ;^i8%ipySuu zL3g&@W77xSL+&ZgzyN8pfn3eW11kSGK{3I=0y-d(&jG|{G1O;Z;PU`6xw!aRHi$DY zaD$BJ>jVigaDzKm-5@q2_b$-2QavCx6ZcOI(6wZsVu^*@PmqCuuMfm#3X5i}w zu{ju6&VsH4n-C8gq440FCX^$=z`$(Wnj?&-PiU6WEo4B90LR2D=m;JQ_!3}IKmiMK>L3AK01JeLFYX{ zG=oOt7+AJ~E}Q!ac8)K|oPTK`Rn?NP$OichVhaBq0R{#>c1DmJ_*a6i-V$I0*~I@H zq)(C&eGi6}lQ)3L1Vqg#vQUL{(I%A9!1A~OnE6|;B8jML& zpnmmxP!wn~W=JtGC^MmINKm!NvlL z6*iW$V3BuV@+X)Cg)JM4yd+4aDVPKW1sls`&}|dHm>C%ObQ$MMGB60T@fk7R19?;( zbQzd2c>I(>=mzLUF%vL{QK%kt>L8yfn8zga3v@A<8JNQ?q+rg#z-JETun3(6g{uXa z!^*%P36ip6Yy*YPFDY0wfMc5fDd>){70hhX3=ABq(y(*|E}B6KAn^)n0Wt7*ii5&` zJ+mQ5tsAOZaLn^x0$m)po%xj%1B0Lp-)`nr(hLkjaiEO22h3&=0`;!>_A+mfW?*0u z3I};@AM-Ylc|z%`3=DkxnL(L}N9d#x0|VbdaA#Od=p^WZ!9&cTFt3+jU}FJ!fsF;^ zST+`rGx(K3Hzpot4gwiE0W<){by=E$K@P-(jJpZAO3N@Xh$evcZ-_1cZS@re9n-}m z`o$PjEbin74ZEEX2NjEdf0 zGH5(Yv;lPPg6J*Kq=e`^L6C8v)4*6n6@|fL+MwEAAWBUJWP=_9gTNfnup3u}z`Qij zU8t1eSqfjEy^vhk-$0If%{9eO`otL0~0_&B1Ly-F9!5xa2ua1_psO zAR%sUUS0+Ufps7@54Y>|+`U=i^`Ohr1U7*NPDQvS^cffgHiOs-+`J|X3<6s~Y#r`0 zkn^^EVPjyh;C^Ywz#y<4#ExKKdC$PWAaEIURtcAhz_V2#FM@_=1)hVfVBi7WA}#O& zl>eEyS7|UX2)qQbS$IHqcnG|&0;SJ-29{iq=^qMZ85rbw)Ik^73H$&}_J9X^1%84} z;+B?WU=a8Pid7bFJ`M&3fj=N69NeWU3=9H)L2MpwcaZD<%~k~E{Exz*d$t)t)`rwL`?4hKebgBk1o*(2$xi4O z_zEB}$6g3jh6@OTISxYIOrSwmMo=m1BIL`?z#t&TST4c9&?B@&l7T@$94s?IXg|mX zNk&jW-Vk~Va;_93$WKp%Bvcs~1f;>vdM0#Pkbyx!meCWG=Uxb9f;7o7hKMsTyc9YP z(j*V&yb`(qN>obVa^tm7sxbqDfHET}X?;=X1`PtMfQ`#xRQL=sTougAV^o+AQm6)Y zcmbnAt{MY_fI8R}g^UVcK_+T|c}0v0_EKpK3T~ zKj^4!0dq!BWD0T!*nlHNh{K$LLBJNwW)OM?GRh9j0d*>tD>5+fm&r3Q2-q`jRs;=x z3ivXrE7dbF2t5H6Wqx3l3=lK?!5kK$Vr~WofdH@vIE3DSN~l0Ehm(O{-iU!gAc*m$ zBFIUgwgwx^326|!9n`Y`r4f)P1VDq{@(jG{N(>CCppXagnHcy3K=HVkv0dJYfk7!i zRA4!yvkC))P#tLUZw1&22B8O_ytWb?GE73B4H*~&R)aY#LSCSfVhxzXCL}VQ`*4OOGZXc1I+1B#UcjKwOTOQRJ)=MV@S1Z!L&sL(CMz#wo0%v&X>AScSeAaD$9 z;Tl1OpP)+O9Al*l=+bC~AdvqqfmIraDr^I#tjl1PMxqLZ8VvOe0#_J8wVJW00%+J) z;3`DCDj&Cdq)Vl2-T(iiGQ6IXh8>v!L4J2AJm{s^ADJ5O0EcPNE8+*c7-0 zw!%eJ;UCEQyNsPGpsS=6LP5ptW3WmeQ3l>rC5CziP+)_jn~8xJl-NMQ4d$~m@Pd*o z$p2728w)5c@PbMvkbz)Pc?LF?Xi(ehD9BAu7z>pc7z70b-Y|X!B@EEunZR4H2N}Ra zWCHKNvBV}^P@Kyk@SbtH!qF_@`pckN<0IHzJdpb26PUxtz&{HV(VrP-gYMUD0kwpT zK~*%%cF@QgxEsUrL6m_(Fcd6$l7oRkFb%{M6cDUnyr>H5aLO?-2v&k^We}RJ!N4F` z1?DgcJpwfos~LG1r*Ar%Wx*&r{q@l-$@;Zs3=D!zVC#8=Y!w(71e?L?`Go%HGcX9Y zfI0jO{1#da41%qU+Nz+;1F8wZQ-0uz0hC!78TjuiGcX8Bf`|M0U&t~r2zoMet1&Q0 zg6b!EHCV$D)Hr0|(hN)hf< zLk0#RaGy|=`?)CtgHSIhw8gm3vokOV^%;P!s^*r}VPFvI|F6QpAjiEL% zXM#N5!aWN#kT8o&m4RUccii;X$Fr2{->ES$2+areUavvsUO_`Y;2^SPVBrIKU_r4O z0|U!@P#b#5Gj#?Aj&Gp*cEJOYAcBDfbWViOGDgq}0znN122N1p8az$I| zPXh()Do{u;aEGffFbJ&%WnD(@qgh`2H^2<-%Mn7DtiFfa)101uV-XP=H(pGcBhFp3IW0_ta!y5Sj&w23AH8n?cA=j)6gl4ZIeH zMd&3cFxkPmfJ0~^DEV-JIh+h^ET913=Lf|OCnL8e1A`!^5I5sYka?h{iVzRDRALZ1 z4ssSRn8OGjofqN*7ZFTC$2l3MzdV^GR38nxFYyT|?TUjO1kP`Rd<9=f}%u&QCgdU;epV6Sq26nO>oKnM1f77fk8-z z5tLO~7!{s_qD2?n8sT76h?Hbt5Yl6;2W1i-MuktHWUbGrs10i3Dl~(#ni1G$5k>`d z&^(ke<9!X##nlQ@Ag7sv8=?}73hzK;g=UOjH9!|vD|`TjpCu#c7$^-!1<;vbLe^m4 zr!Xq40nH59fqAKn3N;{8>=~D`Yl3dBR#-djbe2fHza|4i2BShgC=oa@zS3Y|C}C6p z-G3qE433iuMum-_bmjt%|jt9wTF{;F|GB60IgJiTBRsP6;2I)W?9Yz&UW)&^~wHS4D8C5_B4GI^69IeNw zQpUr;AY24eXTqq$&&j|bTnv&iWmNelH2wUUEZO?SIt&cp5{L;*vNN!Nj=d7D1PyH| zS1<~<2O83!u^P!fkC(% zByPg}2c*6iByPd&AjrTV+y@em;BIDMU=XgK0FsE|=1^f^5S|EW}!mY^0z#u#eBz}V10Tj%$LEi>Zx7K0=t7*#+Mpu$T*ku1Zg;vvt#AiNSJqrj+A zqR+q}3@$oV7*!HLL!|3L3+=QRRX{_}!W%&&*hY*hETGh|2{dDp#Ha$A{}kQ_n(irL zQ~^zs3hxI^@fI_xDCMZr>7+98oY`f9RVd#L2wBfAQT6RI}vb68Y0xl0a^#e2=YXU5UA!B z76Ut^LI_lK3yXs|sSH&@Y#Oa~2e}YZ3-I$RI80x4Axpacq8S5& zur|1W7UEZ6)@EQ3)&Xk}=4W7I0Yxz{DDLKhn!%vrO`d^&1;`u&#si?cFRy{z;>dVP zkbyzaL3lBvI;ft~0VT;LVBa$c34$VIDVW0|6ak9WWnc~mxIH`F zKPU%(W?W$c8da?Vm9fxktcA9KGR#-7hk1mSfPDXraUH1NBLuGWzJmfbjX?&y!cF)G zh{qrYZr}+21ba;ZyueNP7bB=3R1;bYN^idzKZCBZ7IFktJb%CrvlJ2rmHvF-)nisd zA3#nJ0Iwdi5lRCUaDq&|(@$Q`l9!eTg}EYl$=P%vJy7YT2IkBVYM9P^B}=Vd7G#hX zSZtnfajpr2uo-xz*L?7@5n*#CP$9Yiyt+i#f(cZJE)+TlGRG3EXOYl*P?EF)a~2D^ zfm~t_cGeOhbCCZbO8}RF7u*RuGJzJ{EeBU-!cHJP^$aV7KJzj#2)l!L3@e42KxK&+ z6X=AyRl=Zqu!Vh@KpdppFve#7}%*Mj0!@Mpei2BGX<6EpghFJ zvJx~~3o3N?fuaDErI;A_XMmz8hH0}As8c9xlg^|B>ZO2|+z4kfIfJ&o2rU<5U=Yp* zJIGP!28fdbHrh#OH7MESGD(B(!4@i+o_sY+vHp|^0|URl90P-JC0Lc9k?;(rH6TOZ zfNI2PIw`co+$%^fzV=5o?8TRBIq7$UXZDKKpkPICvSk9vzW=slz~BzLwFg}8<2BW zg9_v2U^atLG^plY0d_EG6iFF$>+l>Va98>di$V{m=wk=-{<0`og3RP$*3)BPU|?0a z2x@T(F@svL6>JLAK;?x9c;+L7Lt$b)D6&PFK?P$NhXQD=g|HY{GLAz5w7x=E9BgO; zhe8}EV@WWBMi7!X6hJ9d7_u<2h(jS4Bqs~jSHhvN6U0+y2GuDQ9IBwPcVT_z0x{72 z*$N4ulEjD^bd1*;afM2mU5GN9fZ(h}^@C*lg4(`{~KNvBkUvZ)O-sB(NRt{?z1+7`@v zA+DebsULg5L>G2Y;?P>}!+xC;A#O;eLlI0I@G`!Zj*1YL@)FcXyX z{g|JFcv1>4KvC$=3@UtIC@Um^@^=99cT3Qv*a}{npw0m^sOj}VSpjqysBkbdsKorH ztgsR^h#(vaw&JIRTRWQVIK=tDWIb8nya3HK{$c=uO;|a zY+g_sAC!FIEz4)1)d`@i3QD+8QQl9ckfYpS{L_{U3?K~VgUU0|<=$*8pkj;{RJ4J@ z2rS3WzzY%tg$tC=R?o6hkb!|0)cfMKf_5-i82JBy+B!+hPM~|I*Mlx@S;YcM3!vRZ zs!R+FjB{37Gcc%w=5QESv4Dp3Kr-sJpzD2Bv4Ex>H0nX84X$AUH7uh+d@j)0 z^lQO<&{iM~9V3S67jI>WNP|p!$H2g#2|6wBUmyd6))WQ?2F@S`hV9dCXNg&ZSeL9A z7_=Fqn2H&+8KarG7!(<_8W|yqK&QDONiixiXib1haZC@qoh8OE62!oub%&9GK|Y9q zA=-NS#C}cX=`(L{2HfOFa z1A`u@P0wfn8c+k}GktJySb;*Lijjdq9~2~v*2UBP?_`P9+k(!-v;~>*6?7#v=ujlB zAO;2_8;GZhK%QbWWY7X_LpKXzUw}XL!p&*EX;kV6n$GcgQDIjzBZ6WS2VPMb#MIgu=WvEy&1B2Ed zs5$0PF_1bzMu;Z@;9}a0(Tw&CnxNq}uqVu*5!G%xJ<&%{bo%AHS;F-oe}kM?0uCx` z1_r}PpyP)@rZF(wX8g5Z%1c_s!1BT%QCQ4l;&!x*d%YJV{bGJ=Na zBAFN%)IqC283h?Z9jJLs3=GD}nGB4=;K635i2)km7!?7J*?a6^Vqnnt4NB3X;CX`I zAU@t!4_$M9{5!AQL~?K?2F{ewHvK zoo`?OrDg^OO?!w;th*pT=OJk9xlixCpCwt}5(KdpWNr-8!~g~clck_!9tiH=fRgSE za5}GXWMEJSt$t?=1h+p!nHd<=K}#1IAyYv8AYX%nDHt3~$3T2=D20GSp{IA{iJM!@vSMAOUb3g@fZLiG_i|6m+LN=x8n}2L=YSf;| zvKSZ`Ag+&QG}dN>INlVLU_n=Nwok8nkR_2hA&7y&#{uj`=HeR+44R-zQ0IUP0R{$! z<)ADCmIZ}4gVqxU28K;R3=FkkG4Lgpnr}hp{0A{GFqne^<0Qx-6%`DOi$PbTALQQsdy3=ENuU@tI%vQiId>q9UDLk>iY(U3uB8Y2S( zNCznY7&0*EZUi;Crh*C?kely;BQVc}fk7{D`p1V^vi0DsG4&!yJj4o=(x-!FRhT9Q zSc7A52B_#_4Alom-%QZlT`nsFgZ@u31_s7ipjO5jRt5&sUeFdsP+9H7z+eE1oA)4< z?^zibbY?LkqQ(#wHCmvE6bNQuun~3w`-ah&K?`&y1t|4LPhapTOG+J-(n}z+OyG>b zXvm-mx_=WKMxgKmrS#R)A3n;`X^Yb^r< z1E`H8Ha+oimWZTAFav{@GuR2>a_=nYOxs`v2G8kzkF%s$O@bL1il(o9oTXCl5X`{P z230vRfI$m%ovKeT0|V&1GEfl&iVh)028M`W28Oi|b&LiKS~83b3@O133mwkAn(i>*)KW&}c7bJg$iyKN8v_HR6ub`3-ZmgUIDOmz=g25F1_mwAS*TZn#2FYa zK%5Cn_&T6#aa*PvJk1jGW&mCEkqBCo!;lXuBjx+?=*{rF6u_%ut36_k2%rf+zfC9MT14WKOpMrT;UGh_v=C7KAf^B5@2 z&oP<)^=Xz;peyJCpUL2Uk^wu+e^bD&r~~m+LAR<*1}s<#os{u7Thd8R(K?ND#6!U!T7Ad6qb1=k%k` zv*eY`LGI;Y4q;qol&HZbSVAR5JP;aEpuP$9m>%dBE;haYMV2bWpFf~7vpgX7-FT6u2$8V?x4#$| z?n7l{UuG#9PYQ+@S^_#m_A}^qAJCo73=E(}%#3qHJsB8`K$G!|IpFRBV-SN$(DcHW zSt9k(o(v4?8K6t=>X`4UGB9v*F)$cuf@(JipE1~W3JU`RV*|Kp&%j{#7jzxfB=C*8 zpn8{a&VP^z;MUzF@Ln=4E(Qj5(B3P?Nnkyo70O1SU2jl6V+bUZOkploVUS_S;bLGg z2Gtf*nTsF0lQKK@juzfXrv;;$mRX0-gN}GSSBiVGO8&paa_U2Pzd{sfCH7f`P%L43z)Q zfqNmK+};Rs)*KCQSR?)%*x*%M3=B3Wxfw(l7%wm%5CbKb07#O$$b5bJzgJl@E}&$o z1+rpWFy!1TZN@0(;v0+%T8<113Rtg_U%9w zzcynWBndMx7;XTy=Kg>qp&gu{_xiwG_Xq5{a&86&b#U49hxz*Sjjyw;L(T>>Ff8;2 z1wb^oNC#Egps?Et7K2pepj`nVS8K8`GBALf0HC59)C9N+5L8cXg#XvTI8h@Z_MU#nv;YKh+Jwq#8ib2biiGcy69CT0>s3<66V9?BCVqgGS zq|?d-sUyG=sAYsL=sK_Opc4fciogZnCO=rA`yE`IGeQg9pWwn=fR}+m1GEr{@z?aA zw^@pkj=s?57ZBrqjTkgH!;;HUL~@y~@GeUPQuTv6 zL7*a5c>2al2l45V@3JK8pMdJVE(Qh$P^-zn4-s#m6!9ULfdO=06eveHGiY%zGBErJ zW?%?MQlAM8Vo+YK}bIt<_awXsO%ny zEJ!>WM8tra8K8y)$niI)D}2b3fE3A~ss|LxssZ5aIz8q?mIg%T3$z$7M98S{b1*?V zIyxrcq8y^VlSooy3?M8b?K(?10U1`y`gcAC!gIm@zsq7(xI z2n#J_bOznM0m1@pOwN3ub={!#e5y>&pe<@3EYQs4Y@o@&0K&pEnVmId7#KiUz?I3_ zotJ?DgoXbwJBKPVFo3Y|RA%Sj!VC-`%-g`_+%Cev0Kx()OwJ1I3=9hFpfzf8OirL% zDL`2CrL(pY0|N*PI5Igu)n;G-VSyGVC(tz?Aj}oud{v8q0fYtInVjF7Fff3yfHsr! zb}a@55Ef`>aylTxzyQKrCC<5$3=AO5JDtzzt2zS%2=hBR=P5EU+v!$ zfH0p4i}O`g1_lro7H4rj$;ZF|!U8XuoPw1Y7=pKFe94M4o&ICGbJBKat?biG;LFap z>+5F6uueaaoh?1RSk6u#e9!rGv0tf5)9*cWGvBUbobAyf30kng2&yg_7#IRUcU42# zanpOZXIrZ-KoZ)D#6Ez1H*w&yssiB6uBe7$U z*qPHKcVxRu?m!Yci^RS)UGP$h`1A`qvUxn2Ko>_tjT1*=t01urk=XV~><}b&;&j!W z*~+$^NJ8_F*sGA(+mP6Ykl5#@pS_$S&h(sTy55x(v0P`+Xe88SprbNi0Wb$id@mCF zIT9N*bp%uYA4!}Wv=<9%rUDXMce>)PY<& z#S1kYeAP6R?SUj7I{hNZ(gGx*RwVYM>5O}_mFssQ37tn`gEj=g!tWK5_t~WYB>^nHxl~-68jDk`vnsF3lf_bbU8KD1CmJW z5+rt~s6HZ)7a~clMPlDTVn3ZeaesDjJ-FirHM?cz=6hvl;R|&Hy+3qulGU{3PoaPAhE$StWdW%Ac^-Nv1cH$ z!NY@4^+%AzFCejBK-g?xcQH(#8J4nblkAhC0i*cC|ZW+e6s zB=%t>_BjZ9x_DTEVEr!$2kb6UP=6ijAn*m)P_`M8cpwrRe9tvhO%0NG2NHV<5_=^Q zdmDs3-T6>HWJ$siS3TW4n<-oBe4r1Y)~?1V5o<1!2aw-V$VimuS8;RM`9mEVqZpL zKSW}`M`Hg)Vsop2Zij&SQWA8fG?cB5#5P4@gYUJ5s#%I8zG=Gc>1=Vyn@B>>kl0_Q zC!Wq0H{=FgE)CT!hQwAxVw)ndou;omo!wl22}$S+5}QE{k!m%N*d|D92PC!+5<3%# zU4z8#Kw?jUupv>j0Kx%B(HbQ74kY#wB=!X)_7@~J1LzKEXc&O@>%!8T1d=%T!fL1* z1NC}@FKv(%c_6XDH(5h9Bp``{Z?cApS0IUlFS3S;Pe2j}tssLr2()k(%obo^VAz7B z=;HL=^`heS-;so*G!Sl7Lt+~tvF(u9UP$aPBz6)Ky8?+l5s3}HU|WF!5-Z>vwxJ#Y z->?m3gKyY|vacd(2H&s^6@QH+{tb!E2%4pWsu4wEDv?tp!fUOCcOEdovRIAQJoh^oQ%C#p_=q3H?N3vx8=Fp#HExV!I%* zGmzLNNbCkAb`KJJ1`>M-gbkV^V_?_-;eg${clyN(+57833-@7Rw*xd`0d>m}B=!X) z_8lbl3ncazBsK%+0&J)`JVC=0!W?S=aMG`tR{p!_hYe^Q+4c|~5l1OZ|>6+KFvsLFH39Ue4??Ymr zp1$*1_HSPBRohULzD+-PJv)24#f@wp!!{E{Q9T8Ty&s8v1&RG|dghI6YgJ{?ayh7R z`bcaSBzEBRlQ*)1>-QoFT|#2tM`C|QV)KA5cZM1bIywLrD-uZJa!73Ojnq)}T1euc z^V1n&S<)OyA_|EOzJ(g9xfDsf8Hqg+i9H{Q4ca*jbKGtuanNynF!AeVNY(XIBt@T* z*o>e>YfwkJ@a@!4^`NbBFv~)b)Fi{$pz0dD&J(Jkce>zKd-3{}FnIPT!;2pdveJ3~0&d=rSojz?mH&O3*B z5Pa!0)PhbVHQP>2x5bFNiZ-l90gsp3}s&ci9^-g0lqmCf;dn`k3ejw zqPHM6RGa~HsWDWX8^nf+3xL>AacK}6Dy{%xL&dd0Y^b;ahz%9D2C?g*5)L2^)Hj|; z?066x8Y&q`>_Q}V3y2NXyBLYR2Z?G7#Qprp`24l5|5DBUy<1Vkk}%io0wUrzdEZU zSFZzNL(OqRVn-pdbCKA!AU4#)?I1Qcq~z@eT^|i)PXmcV)hqz9p&nQYVnfB(gV-|A zG_(c8fl8c1VuP=bhKfH0i9-!~1!6&Xj z3DmNKa%_<#VvyLSNbEW!_7o5snw!AaN<-P;Yo(#=H6S%m^S2_gPlMPXHJ~&EzE>K= zVPIgm3zJ}AV0Z;$LpA?HVvB<=P=<I z31UOVmw?z%@s%JpRD27F4He%BVnYmNxQN7l17btfe+IEZi#iz?7`}rX!3zq1(AqfA z1;0jp&DdCY^b;fhz%9j1+k&x79ciM+!n-!`qB-F9Rp%R6L=~TJI@Vt1t(OZA0z?Q zJOhcn4#bA4*^b0MfW*EGVng-bL1KRbv7vf@BeB6ZJ%h#T85jgX%@TiCqd} zL-m61jfS$@k;G?%*igMokl4FGY|t@*pnyCK;eeP7XOP$rKy0Yyk03TQw0?ltpiVIZ z1H&KCeb!JmJLr~Us2VXOwjziP+9CtG_Z4&}G?Z-szJeL5!5X9p8h;KTHdNdXi5-K) zP6n|dV@C|>AVZ<-B9J&#Z!L%oHM0rChKl!s*dTFG`7;T`fl4euVy_0VL5e`Tq(E$_ z1>pOhq3ria;tXDhVIc4w&(Is;xj{E4L)l_TYE-~iFhecY2T4FJGXb%o8hnx1$sjgV zeIAGn+9d!Q83$PaW!Hklp=vrnY^a&NAU0Hd4uW0JupGpJDp~_#LltcYv7zF7Ky0W5 zN0HdKkl0_5*#D5&0-&3dp$StGiLC@?gTf!Q&kDqWT5JGfgZ2`Dwk~;t4od;2O9p$8 zI8==nhz)g|KZp$#j{>ow;_)ChR6GmBhKg4rvFqwV9H=7jh0;((eIRkDBNidCw;{3j zBe72)vF{+Uzag=?KsO{q&6I<(H9>v@UkVMCu!c&2#9ffs5z}?wW{cOiAqmYwVlPHw z?*p-+emV+bi-8PdU^of7(HY9V0uqO+d4$A%3t~gV;1h@qRr43bhBX&?K$jXr6$yga zP(wvQw=9b>Fo3o~Xn@3_YIH$ts2V3EHt42jVKD}V84L^z{vdIvWlD*h294rPA>v7u@hLD&33#lbf^L&WPD1d$}b zS2{x^7!;Aj)j({hBdn0v&PeP?5E~j=Nl5H$Bz7T)4K=3;%m#%&0|UbXFbCq}y+~~E zEyqv|kCDWGg4j^Ym_WDZLfPC%Y&8%Ys#hP0?FwQ;)%(>Wal(<iCv7r_yBe8Xm*iIle)Y0C7NX^9%B#8tN8){Gq61xM5y$p%H z9mIw@=sXhpITHIb68k@#t*b|Z1 zQ<2znk=P57*ej6OYe2Wc!R7=uPjCF3EiSnaN&XNL`{eYEpR>j5uObQEL}EWgVn0P< zzeQqyL}LF$V*f>Avj!t#mJ^9B2w_9QOBBKZhnFl8TM>z^iNw}LVw)ndEs@xcNNiUm zwl5MpFc>sc0Zp`#ND{F~>{KLnCK9^_bTGV@T|C!JxVa>ibJb5;u|9cahjnk=QSh*dLMDUy;~< zk=TqONa+B`ke#_SO;dJ=Lz%YS56Am<);gTE3r&>aL!R-I`eyansbgHW5e{V&N=>^DSsIlVi>^&%&3*0 zuH%xU!Fk{x1Nfrp`00xKW#p&Vxa4Rs-S{_snM;lz=bwKJ44^|9;-@Dj6v$6EcpSzu zUBNX+g>lJrSJxbW#*XPzLDZD#PeIg?>85Tu{!DimrnkA}_%Yf{zv`Cb&!{t9)jh|b zQDAzhdyYTn9cD&`3a}RplMCdhzj4nw!5A`qt4EGMW6pF|&m4b7hUuXoie>sz5G64E zD~MV!-PH>$Hx)#!nEn((nR@4d?qzTF&M9X+F#RuxmoeSfC&!<0!}Pfz>d5rBAj)UD zt#6J$W5M)Z5S26iE{KYmuIrbh%_u*;F+E;*dX8U?0P6zKow(B*{c@C9mlrcItc2W` zzQ->|fH7eDS-%{0#s$;A`sJvzUTK40j4n~+BEZ-&-PJ!wowcT&fnfvWzI2!F0MMQ0 zQ~h()8Fi-b1yL%~pMn%M&IR3vE*Oxb%%pg2x?d5u*mR$O90A6d>9GMh>a0_)f$l{w z^otRhJ~tqTpD|$iT9B~Jbp{5P=@UQk3r~LoQY|z6FGx7yIRnG1>5kzU%8WkKeFJmU zS3b(dvTr}|Cg=AoxKVvc;u70$wdV?Qu^Aefnpql5 zKe(S=g4xp8czVO?Kn=!>?WU7*H#^rK_d;B3K3|4`fd{ll(N>0m0kjbkT*85d#yHp) z$b#-0XFsI`zu26KiG4Nb{_jpD(Ea8UJL2RKo5Xs0fg&lmqxtucS0&vjI zcrnnCMJxi+3=B+?py6@`7AX*03UnPX69+5kRt+W=R%H>eeWjo?%s>~LtAch(Gji+! zT{(3RbZItd0GokDVEXcFxeCspT@1{+O`to;XNoW|uqf^YF+qo^u_&DYF+)HX5i5i5 zk`Lu!U|>-L9mK>E3cBE219Txhi|KT(>$!$f+hsvp6~S8AyFquJp9Hbl*j1&c^XfWF z@oI>I?kWduS>@g(Ki!}(N1lm0Z~ENpxzdbBrtiF-E6rOW$-uzk#CV&Lfq^@9`ortF zDyC;acM@eYz61p)zck2%959EG{~l-uWG>@>kQ4c5fNpNd19Ld|?@YJ4k*h8Vx+IdN zh*6k{fq{D$$PZt@I=PQbuey<|XZ{0pzK8HxIR*ws;jPLH3{1icI2jn2g^NJm5S}Z@ zz`)ADvRjCOfmLlY=xR=uHqhZF#nbQK$QAPh->Rio3EBzH9>vYTz@`skv#_6JU|?V~ z0Nvlp!9HJvfq~6X6m%suJEIT-1Dg?uEx?`#Qf~}$w+OrHbi13m;z3J<85r2iK%SIi z;AH_FzRSx3y62V!v^9gx93;TT!)CLW8FZ-(=$d-SWz_7T+mqNJmr=7%0$FGOg@J*A zgMnqu^yN2m19bP8@I?j&26o{`AcqMH$TKi-3f~Z6VBivF0^L9@oX^F;z#|OW zbj&M!Uz&k|Pk1-zW-{SjpgRnN-9Xnr2+K|Hy_GA=STTL|tz0Ps@NGW`eb${^8A)}}^=dsJK_+$`(6vv!Ae&g&4^2ORCs#rd zbhIGngvp?5;5;~|EnsJ0V4noK?0q^&6$5(|&-8}U9I@$gcXL(L*rgd5IOl>Sl-PSf z?0KLdR^b3$fW|rh2^#~08v82g=?_YC#5`(1*YPd_$s4i123_O3Se}J}!G!&gG6MtW z5|9}#3@o6{!JJFqvoSERY!G2!;9L(9XJG&-*?kancg}70>2_r~64US9&1I{91`_$k z4h<_vfU(3WGB9wS&;S{60;KOe4+jH-fDGtD1(0EaAQl5J3&>+EkN6lEIIn>eu=I;D zFmT?r0IBtWs|C51fyEbeW7-ptWh^zq3=EvF;y|i0IY7hYYe8omu!w?!^dtB(mln9@ z_n`A%SUlMn7&w1|os$YO=ie-l=Jg;|AiZEm3xZe-+{;0CU9&TS+`v5rq)mVkWD~al z=!!H+Mvw#ebT}0lb2u3o_)|f{#GHy?4g>#cka8u)B2ESd7XD&T2q-gFa56A(@ZSTu zScS2UlYxPUe}yOm1E(ru3nv4E0RJVBGBw67P6h@M{zyfUhNIQ34%Z&7un?L1D|w5)5W%f=N(N@Uk4|U|`@DWoBUD)MdO3x^#_=(})pN zOz~%eBE}e8$TRTkf)b7in8V1=xPAJ=`?-=XyFm%w94yGfKLZqq7GMr51NVE7lojJH zkcag^myv@)S`Zwq+$%r{as{&$7XyPp5y+OoD-z1>`1PmPpWjk1SPO3=G^gpddZW+y*jpswe|PJr@@{ zHv@whhz%*Kxn2E1XZ&`8Rs#ud18w;dehg|w2=gd{it4qXBp~d`$H2fUd>B*#3G;!f z3t=~5a24V$!oa}o&jY$D09^2M2ZJhgVbD<_48nDwZIHs>K@A(>(_A3auBLn-ylx zE(Ece*p-AC7`PXK*v#zFApb4~v02zJPJj6@S6OuyHvKE0u-^c&SAp1^?4VT$ z+^a!sF80UM4Iky|2i8k5FmP`I)tw^jrg97n+?zpc1$I?M1_tgeAhr&B3CQMct;`Gz z7VLAC7#O&>gV+%aETA*IxGygRRoN!o&+dU-zhwHxN4etl93W#~g5rvW19Su`_xp9A zY{bBl4KnM)QXU2daaBps?PJ_Owt{Zv237LhKS54oU=J2zVBr1*iXImBP*w&8?mr+U z9PH1<7#O(!g4jIlWgxfy1MO`V;P>WXVBlt81lcCSF9lLm&j{v;@q-R$;AUn7xmSWe z6%?ARj8_F17%ccfxu2VjQJay0!G^zpg@J*a7o6H{`NJd`7`XYs96Nq%c?Je^P>1?3HX zeQ5>;ZYf5PKcDbV23@u(4R+}>{x_g#lx3`CV_xg$s2#?w0yZtDo>4*_blIjVn48Ba0XjZ{TMg{;0!E2e zkeoW$6@`ovLZG130P~6%C7cBq7`S!8DvKELW9g>^1iCWrqG$Q$`!P9FbqP*@j$ zIR*TJphR2*)>FhkN0fnqy9CTB=D!STgqMOWt!F6V&j$Ic4BWo1;J*Y4+j7QSK?a5z zej|`fCF6cZ28ITHZhi&^?gmCseb&K$8f07}*rFc(wV*`a1Tv1Hj~{d)8+S8fu^x|X1_p6x-1LH# zN-#?N0A;AjVDqIIB?^=o7`Uf`ffd#>K+Nz5^H})BKrtNvb^r%IBPi1Zf;pTF+@QUO z+(C@8pi^&IK+ObRmOtQve>VpM11BhT<5fqHuz(G(VC~*c9B|E@wst}Z5njZ2ZSF>IXl-&1%lUIYF1n9B^?tS14 z(IP0}0*crJjLU^V7nDi-2W9JnV7IOilt>2|b_C2@B`9$il&z0}UAsn5Vkd}qj&ZFp z1H%SEiK8ILUjnN%5S6$BN;;RpDvd-X9#8-CB3HWJ6%;1d7^iWAt|F6o1xm`-!5ZvD zCHg_3as$kB5S5q-O7l0tJSR~J4nYP6?pt8PTtp>|K*{+o<6dFVRb&#kLC$>)R_PoP>@06jT4lLK!FD0*E6s)aDoye$fqCy26hHs7LX3k4_pikAOpdo@(jEz{h(~o z4sz2I#-*Seo;i57bBHi7uwUn8VBpySsxuhaK^Lv@>;$oy*q1XiF!1aGv02zx$}=$V z>;|#f7+9qE85nr>o)>0daOVWowwfZaR0Xz-oq_uq=ptrEMsGF-20jPg#f+e%6!@R; zGBEHi0T&Jo{0^cF47^Lh92S1p=`pWzjq8;`_l>UuD;DIh1aa1bIqD2xYqrCz5oO?( z0JZcsGMb8jI#9e@8Jk5J7(_wWL-1~6d<|+r^NWEj*be3h@ZSR6NxuWkQQ!w%NWi-b z%rW5q0CLoBFh{_FUrU;Sfp;(CW<~~v0DiIQa<6kGH4cMR8~`W282-PYi>nWUIkEi9 z6&M(J4}m#x{Ew%{zs{9ZSq&;5j)DD^!od9tWXskpXO&^;JpYomyaKGBtP#ZFo&PtL6(7m_X=2<0RKeL zRqZ#yGGhG4L8jehEM#L~5a;IrS$hv0C=v|ZDxllrA29ZV5+@rdAYOy?)H6s~F!Fw6 zRFYs|;0K)@$@>Y+X5g0qh5Tnm4GB=wzY!E7&`TcpWk5mk73?`4{;MFLeq+=F-9^b? z3*vkSr&$?rC!6;Nm?OvkM1X;T_b1rN3j6^ehy7v%o#SSw#(x@=N`5n*2VL^O?+Yr$ z{(xM@V9C!1(!>Yu@LKT)Dlstd3V=JjHvDOzQ^W|I8MqfbpZ_n&FXl|3?(YJA(8-y+7EJbR3=9kT89+CuTY~j0;-3JDNh>gC zG5<@&=?mZHO4QE)1*s#rTfdw?4HR%rU==I)pMX-IJD9VQe;+7LyqMI*7#LQGg6?hL z^<@IZ^BM_1kmY_%piHL2C{YLs$uO|HOc*7KL2(=f=9z-(6;R^lWdY?R@L++R1VcT% zr2Yx=a}1NQ7z2YexQ)%bnhA6vwD2s@l%22u=%60qLJkH7CgE4iphosoAqEB(VKrt@ zlf4FX&oBcoi=6}mgUn8l(gJQ!)c_hPGXkICrYpt3APZ_mG8S-y$`O!^+;-56J!27A z>0|~52DxC+7)~)a_w=*xay9r9Js21iK__+RcrY-iN=|>+W}~FVpa44F7A%zs+Nj~d zz~C&&z@P*@R#6djQX@!xtK@XYU%6t_)86N*)i-%CFwBCfTEN7h_=ACg0VKE{CU}F9 zK@oH!T(1WM!y$+uqcMXb=$OM99t;fEAVQ!+))YbK7=!e_hKPYrb5sBw@&TQk5|*1VB9z#yLNwrn`N}RWt@QF&K?O z4GhK*bmw-;91BaX$NE_&IT1C)Fq@Wd8>!#28kSoo))`NlJ-1J=^a;0sy zc`z_2w1SS71TjFTC7<9S&CU{D5)^ge+Y%3N}TK?!^ww-O`hJZ=W9iJ&u% z(m|$!=C2v&?3!NlF;~tNY(yr=2*xO7&{D6TQeamx6@m1F4%*cLT`9# z&H)|eAv+0l7=SS2^6B?K=F0J=$-t77BjfVvT%U4->)%6M!)V07U=RiJVm+vsW&ka) zVw^KmhJnElY=1qt(q;@YoCi?@s$Up`84ON=+zdJipMjwdeDvOAS(p_Qz*@F2Gcd?j zfKH;B04{mnF*7h2ih@qYn!xyyfnoZcPq|8rUDN-6%GK8ex!6q>$#YEQOrXFqWKaMd z{Rv7eilC$nN-VY03mwzNrWbzB6=wS7F}>|`t}2_Q90P-_-}H^2b7iE!u2um%;VlaT zgCc0D56Cmf=RL?UaPB(5$UQyk zORkm`DEKDGf!r4jO6j1;1UY#HRLBJ6RwD)lTLuOOknxJ3lU_k?y)QRC@msEnJLqu2 zU*PZtozTr-&?Lyf!1xqwCnWGT$uls>g6(_?Zev|$Wnhp64azY-1qU848v}!E>~zhq zxrS;Wo3rI1jV)ho4@BODuEpF0O|-+1_jV@lHia7ogoQwgt!ve z5qh9oi;*3{4+^-?U`MM$74Ue&iZMA`EoSDacyi=^KCMicL5EnX3qqh=Rss3q+#gXRfdsnDF%faSSW(hFUX|JAPt&qpyKt5^7IEkbEP45QXL~CX=tl}>Lk(W z^1pJ0Ay$D#q(D0Jr#t-0H4BIPT8S|Rbi_J?0q7oW##x}b8t}{<t3_cdin|Rj>pbstR$H=kHu$ z1BeTdlWi2}fUlik7l3Am8RulF!CbJDdHM97-??rUPgNNhs;T2Tm3 zjG#-6l^9`W8bOL9P-2js&h;l(3gQ}ArVUYpxW;y=Kd%{sGUyft3^$q7fc$$4>?UDw ziU6HD0ckGWVqQMI`%i9g><`fF*gbG4fEt)`DxgDg-ZF#c^$bC`K79gRrt%KVcM)e` zFa~8ERdtv@m{>rySU9LIQc#A)vjsF^B&kmq{E{m+J@9X?gc7I)P^u2fZJ@(-6+rW+ z;8YDd0u>asYt$hgTJSel*cM#ff-WZjF%)MqFfa&uGB8|(YgYtSyda?`2%&?}{L4B0 z!{1y5NN9m>Q~(+7paC)5C^7-UVR zH~h=hmjjg>2Q|PRf!40Zh^V?h{p`P7Nr>fs&|nbLoF3?vE;gO}f36Tj22|95oE5AI zahBu%TuD|LPtdG){Qq1jUo;njQaLE|8=M9W@S20&3Az3Sbd@qBKFz`I{3H%b<>oBV zRBkf;*#BHtM%k%6c@pZN)MTcGaC;1+HG=|Zt_d6!uxc}RdZS;u*wn;4P^~$&EKkwh zNgGy@%x3`=!8ars801nw<;_AcUq}j6#KspgFfL*NsWp&dU;y2+45{KkCyIl-%Qs!H z!$xfCmpnyokbTOKsD}iBDPx|XFKDpLpc8bG^B1ruL1(x#&iM|v{0rE!8n|WOz?Q85 zSq5s0fDBdCfQI^3uw~O%GUf?GYy%ZTIUW$(?l9)bd42*lIP5^pa0bxKCF7h<9hfie zSV6x00%}|@03Fe8#|j$J6qRORPym?^wg^;@f_#;t12Hp#DNoqhLz{u2LI)PW49cK` zlR=RL$=3`FIx|77_)M_zpyU<`t}Q@UXhNbflXdy@bxe5@#^4G*8?0^>=s;c2I6Gqw zn131M3{c4db_S@;0&<3eF2osp%z4oCcL5p_u}~Rr<~&JBkYfsUAr35IU{F+KWMBX_ zc_&Vga@UGJ&m4yw`H*gz2j3OP_)opH`OJy=FY392hC{fn1GJXTEqq#KnEFQ0M7A0^cWa)LASRvE&^-xl3`$w0}Zt^E~y7A z&6Z(ckO%c1mV)K$Kt>sKfMW9iX!3;tv_2 zKo>GG&PmsY+4l}?9_YkihKW(M8^DZS2R1qvZuB~^(aU8S805e$=nd@4r#rCa$$&ddrPCAH@}wO@L2+il2|5cD zH1Eg2U<3~47X}OrhTyc#$N_RMV~`=(wTv7f*D?mf-Fk8QUbZ}G-$YMv5`q-8pl%|A z0r)68&=?W}gC*EZJws^BNO6EFBLz8_yQDclNy1)^fk7E`pH=R3RrWkZwhBWA2D#kn zKJ0mN^fR%w7=nOiGL80&zEC32*Q0tv>&Ot*42H7}JY4?-^H0-}y4pjXyFh1u1 z#mrZ@eJ{ZJbmSQr7<4{?T7-<8peYiNL7>oJoFiofa~d-z$Z7ue^03}H3wX>oNFHJ` zD<{b00+4JhsBU5d8?+o`ve{CQL-fD`Ad~li!$8BBfkF1kbPJ9=S&50D8XcnGImiUC zCk;54PtWDZ6Ze(|ooQ^u$;<@4RzdDEh-(ZUquZ#!z@P{!S3rHookmCj&uGY?0166l zfnx_PRz4U(3Y;e#dBS|)dU^^214E@J1B2XjR?a+ydQcCU!2r~HXq}9I(?1oPuH?0Qcfi2(&6;@(k zPyltjCwek4D1b^ZaEOBXf*|L;ff{*>D^C)VOMAd!4Y5d=J5R2DBd8D*WCzvlpvW%) zx9SwlU^!I~oKxME7#JYgN)Vh=8H43yL9IApc2IJhrNqD>cOTR;6an)ug7__1|w*oqL>2|ULFjJ ze;F7UK=R)p@=PF!Xo#v9Mh^x>0Y(OfxtE#DH5EZ= zdZi}=!*Yl?QxOM)A}BIIHPs%77;_nD2rCBan>!Feree^j3R4LKsAX2pz@Q8oGF$5c z?zKlTm%ReZg4Dz?l{0`AK!E1{4M2C>GtL8VBwqkd;%m%dBPa8?K*a%LkldN+8oYVB zQhnwO407OeJ=b!9ipg3P1_lLCX~!}>pEoa%m&FpMQ;uu-^s~Hq7LbGvy8jE5l1wci zX-1PTPq==ICj*0r1t^%K8J!svGe8N)oPi+*EClLqFerlBMxYzU3XsG=TYe6BGB7lQ z#lTuY*VTcPfexa9Mvnq$IUG0@-vy^t28JtO^+=<1`QLImrXS|ZlVAfiaX(v3f5?|7 z$+&X*Z@xTPHybNh+BE`K(Z;F_4Eo?`H33)Xj3JO((G*-OhNviXkf$N~Is3pkTpevae6hU$H$diF#BSZ`|w8o$aYJ!4Nz)^@G zQ;`INVl4yYR-Btqv0?@W1<>8|KS3r>gpP22Lr5xuMh95D7#O&$7#Jd;;i9;Kfq?OsT9;7Zvv7_lMNp7~ zPN)F~76*f(Ea;RIPX>l5U`wKyiYy=vZE%qHGB7ZJ#zVJ(B|$grfXWy%2E}k#dOQV| z0VidJwV=hKmJAGvpdPH67X!m{s3a(`zcVl}7h zoDY@-oyI8#TCvEu0NhH5S7Tt%-#WcZC{H$C7SxJc%mJDPU<{Ls2c7J^1gvSI8Uup@ zs1Ec1g*<2vVe2ImG)83oD>X44r<0j}Q8-V+5VR!HtO7KuY`_7kazJSkvJ%<6bRB~HH%1Guf6zyM0S4CbK>kS&1_HB-Q9)`HZ4>IbkA27@1<@*o2| zOt%f}nibBlN-={OWdCU$1_phw>#~@^t_zW~o4!jTPZ2!Z@Z1R$qTtyE(DkmM#P%O5 z1fFd$V^9FO6kJHa8VF|2kW`>0nI~)vx&jV#G72cXiy0UcL9I?uz@|8Z3_u>2xKx*c0n{C308Qu=xqymY(CGdZHqh$S)w&D}pqr5x5znQT6zo&pwl)PIH$jo%2Q)Bm@X)tr>0Ww!NB0^ z3bvfN2sFR}8u$VSJ7}~Ml=+%nA;DfCohKzX39J+}fuH~yrvxhmU2_Ohcmb+#uXLWO z(QD93Ob&3m1f~21;M!f)1D5hRctF+r13g$m=i=d>E+Uhs4W6F$b%VI47&JW#YTJUQ zSd(Captdb&m=ZiV3lRj3)}%5pFo33KJ0U`#DjwWY+ULc658VWfe=#w^=rXF0=hC66eRlYkg!vh z%@fmbbO(70bkQJq&KYEXC|C%TS{W3X7#SEqDL8+6qHLaMV21<)Lo-wwlqx{itbzP8 z2Py_?oPgp%(UuX?^xFuLfXqRIZa)RP1a$2h$R#hJF1aI{CszLptQ72$7DfgJkW2U= z9RX0VDT6N61i1v1x4?A*NR+|$BL`?B4U>fj{LU}Cxu7PA9cX*bNu~ghI4G_e7{KE8 z*`Nhed`zGf_)cY0bdkA<4kNn&6Nq%)kJ`Y{d>|1sNDXn61QNtsnyf z2(tw_7JzQ(11;k^%;c2A&%lr~eT`h6M18F?0|N+i-(qsKkYZo}VeaWn4$1rs3?R%U z>hPP1fdPd1#T+)sF))BIn~!6g3y&`@Sz0AYcbj$9H93?R%a&cfzUBnldMKOvtdTOTLSzyQL$b}SA?3JeS&%$Dm= z!@|G-!fd{dpleG(n0qgi!%`6j1`y`bc5qc-U;tq*A4kwlgdog2o!KE)iGcxxxfC44 zSs55Wm`ld-9X|sD2y@7BJ9=?2Fn}=cA7)2`bYTVt1JKg!h3t;Aco`T#nBxd1sPqOW z20d;+qsnT)}(V5B`3ufZ< z2^x+ERkjQa4Cj#8x2Ic1gAfSLbgCy}3iTwkK&BD&W0JA^_iEVHl1OZMB(^FNTN{aOh{QHWV%s9Iogr*c zFf%ZCLO7rl#}I(T2CYhk`7akqycmfMS`rCUQ;#Ixip1_gVoyh6ui{2ZX4{Y?4k5A6 zA+c{Ev7aHaKOwRIA+fnY&0%OLiXpL;VC?Chy`KE_RxmCD1A`k9I|zv#hs4f8VwWMY zn~>OjNbK22>~%=&V-Pmv!1enO4mc8CA+f(Bv6(@ml~DiiBeA8C*y>1ZV4O&DAi{EY}aqxT})STr=;(L(Tr;ym!A?)ep@%fRw-k{N5 zsOE_2cjNP~*Ml}T!0ZVGbwi=j@ks1kBz83tyAz2$9f`dZiM<(#eGrKazH`r$!3-Sk zACV;fA+d!(4QZ%@)REXG(=!wEl~rSqgk~YJHz2Y1PT!cAA6zd98uNvjgv174ga;LO zMiLK1V#gz~bCKB9NbF7|_H-mRcya|+t!ze;IEchPkHo%<#D0y${)xn92h9LL9W9E) zRz_kQBC+j-k@CAQl0-BTI}?e01c`kEiTwnL{Q-&n2Z_xI>Rdn_rv+n!RuJ05I1CI7 zKGP>A=Zo_eBMCK3-mb^#K*42fNX#O{Q!Ayvf`5C`1lWnh>g!N4F4WiJMa zLmjsc#0GUx85kHggV<2||Y$WyuB=%t> z_H`uo8zlBuBsM#!`wg{N0EsP$#MYAnoq+-kE>J%PGWE>BU?auAAPhZa+a06x7 zf!I)sSwPdtppjwF7JF&Lap1xrai|(u5Ze_L{tOHZN+1qY!UDvGxQ@XV#DG}OS4AU1eBhJoQLNGX)f09uv`Rl^NpLme-T#I^>pp=yFa zY^a)W5F2VvI*1KbQ=bRo@PeGcz)&Q^z#t4|*Mh{Min@{5;QRle;tN6Ipb1?D28N{| zy-@ZBkT_J$ZV(&l2+%4ISnYipA`XeK3m^_u!wV1_s^L2l`wxf>Rl^0kJ`c(k1+k&( zm66yQAU4!N?nvwaBzBrC=+r=Hw#o-dK-m>Y>^cw|YS0uA8*1@<5F51ag@J)#u`KAw z*XeROh!{N$l7=e124X|q2)-T=s*M3O;0|STBC(}GY^YOIkl4CNY%35OYQ7_g4L!27 z9yE$C4CMrXB%q3-L2RfaK!+i~Vj>$!yb_6B2Vz6b0WYe6vR5LBZ$e_90I@+k@j;2{ zB7_5CGTf45fS)_~0K|qG^Z~?%I_^7&4O+#hpypcK6r z#DN;L8N`NKybHvJo}0Q)o`FFa%03AahpM>(VnZEw6U2s!KLN3!;x9pLsQ7mzHWTOs zK1Qe_cF=?}C)fVop87Ob`cZ z@d6MVH0Q~{z_3Jtfk7C`UJnw7s@Vl%Lmjst#D5?cs~EdgRf&Cvj{p%&|d*q|9&1_lOWB?bo2mMc(L z+bMxgV1z321Sx{L&JVX#=sLq1X#zgV#MVFiccofFB(@ z2P6(vvmC^RM!^~o8!EmFiG38rhN?LQV#9j5S3w-8#4QjTs`)914Hf^4#Qp(dLmea! zx|bBn)<9z0f!I)wxg)Uykl10Wpo$8rIR_*GwYV6>1}*Xd?L$;WoUqyi5{Ihk1+k%y zn*?G*#TOv4*CDZYg4j^?$6;(xK>=FD!RQW-C58tu2?hp+XCOAz5&x0ca-d61q2lUD zY+Dc;>SH$~wm%X(6vT$=%~nI|suY1FBq5F{Q)6HdhO!$$;!vOUfY?wU%tm5^Z)k<8 zSqBn_vUh^mQ1$yjY^eB25E~+1&u|^VVYmZgLlr#-u_1~W-hkLp@$VouRQwN!4Hahx z-HHko2Vd_B4N(OoaWxPd>M?yV8#EQqz`)=N;y{DW4~ZR)#7>@GXq_uwUk?(3nlTl` zhH9IK#9ofXUJGJF)o(*$??+-^LSjEfVsn8mM}_JYhOj{ihJis7#DQ82zUmdqwnh?n z1hJu-!$E9lK*fRBQjnMiUHd8wW#@v#p=!Waz(NDF7D>EA1C(K)61_+g;Jaa=;wwSo zP(u$PvB6isLd9PqiT?+&p&sA>UDyg`3nH<_L2Qs-kpC5690mpkGY}i9!5)e2fy530 zu|b*{7#NC?*!>_j)W_36Y-vcS%+h3F0QG7?yrm#XoQR;%I@`P|e0jY#SuDCx{JoTmXm- zTIa{Wz!0L%z#t4|$AiS7YO+9Vs0XT$*kF4>x6^}s-vN?>wm|9Ec6oTckTZ?~RF=>Lw(y<4Ei~NbC>O8HF;$ z86~Fk3T24bo9lsFXrN@o;DE&TL}JH)*if6&Kx}9*6oS~Gy$YaijUEGoFqGW@5{Ihk z2C<<*H37tiii58bhBdfWf+V1d)`QqkMY}+3(21oC3=I1~7C_loK;lsKH$iNu`X?YZ zRQxj%`zMGERl@+fN*J{H1+)%IA9ObZl*12_fGPstHwPz-wX6(@-2h@kG%&P- z*r2t(3=9n2Ajd)3(?H@-HA|4#n?P)+noCIRmmsz$XfHnl1H%UpM;+qhFCasqY);V4 z%uvVif!I(BBtdMbxEzQLRj&_XL)BP;*r0tj3=9l*h71hC8q@n4^2I%&+LA%iP<950 z4b@f*Vnf9%L2Rga3y2L`W6Hq5&;c?|bNV|Zfk7C`wg-tr)p&u}PzMEo*ii9s5L*{|*I_hBGiWI*0|P@ENCK*;5X6RRE(5Wl z;*B6SRJ;wuhKf%Fv7zGAKy0Y^LJ%7&z5$87)fm*khFZK2Bmre#0kNT>auA}P$7s7^+5%Q4O*Mcz`#&r z!oVO5Ww(RGp=u_9*ic_i2eF~zi$H9s_;L^%s&|74sDOlWb|Oif2eF|py@AAjh{S#i zVng+QLt=A)ZajzT6+~i7A+f<1t3w=D&tL_T0Bw;4l_RDM48l;hCrBKkh#>^ThWa29 z#DY^a)Y5F4td3B-nqw}aSF@kt=It3RYroDSkZB^H6$Pz}pLY^eAq5F0AK z9mIw@^g0sz`}DW1`Qr6Tpi9u9+H^r|(4GJW1_nbj1_og$+Xf^KRpSm~Lyh(Uv7zGO zAU0Gy2E>MngKu|-isvASmxI`@&`ebW;y^8%g2Y~d#NLap; zVnfZz0I{Lw6e6+vk=ScNY>-}1rrHAHfVLnrFfi-@Spa1p28n|dF)%RP2C<10)GE5F4t&6Nw#*#4bc)w;-`+ zAh8!BvA2WRP>T;B*!2u25gdlAAU4$EFGy@wOGGb*2gC;Lr3P&Rvt(cphO(tW;?Pi0 z1F@l@q77n0#VwK8E+95+KEe~kff^Kq#LfV*p{_1OVpk!t8$fKR-cBU;TqO1;B=#{R z_N{s(&SNC@cO*79=xTPT1@cI2VY6flmW3@)aH$R9C)gS_5L)FV7vB8(oL&cqt#N9ym#+x!QfOY`-gT$c@iUhI2 zX4W$>#DO?a&ACYIMkMxBB=$TcHu%DNsNT~^;#ZK^FOb+Dk=VaL?0TqXW*Y_uMkt#X z#D=<50>p+aY-5nIVPFu3veiN2P&Gy%HrO`|4CWvs%A5U4J!W_81{iU zP(_D9Y^X2KAh91Hv0oywKOwPyBe4ZRcgRDtt`rhm8HsIf3o8GimU)9DpzItZb}16O z8^nehIt7V67m2+X#D{6GU#pex%U?0N=1&|U6OMUo&k)TMGDHdI^_#DZUOBtpju{R^J z_aLz^f!NUWaT|#ZzPuhP{t6@xHItzpbgw(qb?hKEXd^uX0|PhcmU<{#3?vR!qX=R{ z9jXRmL&Xh2Y^b;yhz%8YL1O!Z*ibdGP&O$2F(iRFP|G@z*prahD?n_h4>lsPcOkJs zx7ss8&AA2=hdSaRhz&ZD2y_Y-$YW6U2M31f;S=)tU>$KT(EaaF2l9j1Q2kOMHdGvR zkRohtj5bKz8j^AJLHEU5PhU3y(R20!NkfeY1+k$;8(RC6eZ z4OJhH#7>6l4P{_p$N-5$^%jHJP`wo(wk@<_-wfhF6?K8wpaWVM7#R9M20_^~LE=y~ zOF(R>K`TLQsQ7jy_8|}(s^$U``znYHHS>iN=t4LshryYFff35)L}JT>*w7@cfy6dM zVw;25P`%#MZ71g|*H18rLp9&IN7l~~NVnfyY zBC!*Z*u_Zf8W&KF3DwXCl7Lz;9f`dFiM&VL#D=OdL}I%k zvHg+QsUSAglX3RE*h6iW0I{J#r-;PX zLSh?$*iiLOAT|e-6E^+tw0!aU7LXWJXf6_a6B2tj68j>E4Yl(Y68kX{`z44CHS;$T zn;&#hJycu`#P(zW?MP-|u!C^GArgkfPC{a*A+d9j*o8>!is>7t=Zi}=BMG%5vHPY! zoSrXUKNCr4E)shw5_=^QdmR#c6B2tn5_>li`w$ZQ7!vy&gbg}Nm4V?Bgah{SEhP3m zB=%Dz_Ddx82PF0vB=+y=7iZ*)d$M~Xx_jJ6Y#}7J7!q3+iLHpl)|hTMGhe*k7)i(+ ziEWR>c1B`*A+i0C*kMTQC?s|g5<3lvod;oq3MdAKA_xZ@TvbTyIwW=*61xkDJqd|D z4T(JuiMpVqZXF-#}vDL1I5fVn2tmLH>Ua z<1jEVd`4pbLSp|zVzYW7QUE6sTM&sYio}*dVk;oA)x8)Prn}6}7pXT!5;aF++aa-? zkl3C`Y+odHC=xpoiJgeVPDNtpLfD`{U|=YOaKMS65{X@l#BM=icObDRAhD+)vF9MM z7a*}$AhFkYfhHHBb;1@Ti5*Dn{YdP?+YipkPd~^QF5(96&GeNZYRB}SAc|qSXIgwvpD|&2Cy2_KeiKAhOxMgP@Mn6GJ-sTUz>n!e_ViO31)xiO zB{K{Bncn0~&&n+DW0aY`Gqb>-F=aYu7T70|Aj)9+$}Etx@}~dFD)3|EnC_Wf;Lmts z`b-ctW%|qP0)M721=Fo^3j7#Drg!FmgY71W+A>`;x4@t2M&b0T+yXzQCxz2b<$_I+ z%q#F`oH0EUL6V2B{){Hm zJ3-Wx={G^tn(3NF1^$c^rdNU}h3O|j6w7qU;sSrh9n&*GRL=CBAc|u;X9?JIksxZq z^pzkgXZlYN#WCHp6ci3E(`S_y_%XUne_2`py4=^YtiYe?Pv`WmvI0NGg6TKQ3j7&4 zrfZgi1E3N_?U{bEyuhF7$Asxp6$NFC8q+6MfGv3lqHLxcRu+KnD{cf)4bv}H7WnhN znas!l>NSB*K~&B3g&@jf`p23Af8IZ{85vBN7#Kk2o|v9^$3S{|Ms0xxqrvov zwP14}f~bV)hIIv?E0G&PRLb;=AgX1$Vts)>qs8>XdQj?IG5t_|fghv5bisxKf5tV_ z6B|HLymI=ch5|pvEz=nrK|!^8dQfA5AJdC9(-(p0H|wT`F#uw$EIJjkP{IA?N9}m4-g`C`opFIb;g|OoXrL5jIGlRL6pn% zND!4fy|KAKo#{a0^i|CTYK%*#Uj%VKq)-3VT%gA4{EmU)&UDq50%c}-A;#(cMcks( z6Iu!c7^9{awiKwdP7-2d*fITK2bb{l4Itr&=?6i=ULuSPHPa8iEf=2FS|GstW;qi> zjWQ(Qeoa>_=9XqXX3og)9CS6ZGUJBniLC|dtPBy14B^uiRg{FMFK8`5+=0BWm|J}N z#nu8Z7WiGpeyhdAw_A1<_{G75w)ed#n5YlqP45F;c5Ek6D9Z&G0_&+%Dtwm?6WX5F zRcHvm4cRbONpkzXDTTkwnas_%@8&5IW(P4Y2p3gPLb@?oe0#>SBKGw#Gp6sm8X&&C zH?;VY7+eT!Q*BOhT?mRkiG#(PcO#3i85x4% z3=BMCpv|EAkSo0*u?e~dnKd)7gn^lbeX0cm12Yr*UpWQ_mOtj8dzV4&bY@02f$6p9 zN+jw7Eg2YCrt&Z_Fo}W2`dJEfK({P|mSC{-ftcV+mYF$NnN1lOm^s*a4Z*iL_bP)Z z_Q`S#46H27EbO0E85o!uIat*}HyO(^FffaN##&f-MHv{FMM3AYvpfLZ5h%Go>{(OmoR-!okvgNO!dtV@zErS;DuxNtr^kZgZVr61r zU^{9&JyF6)YI^he5+No7t?B&|Mp8_XM$`M>8cR+;bG}4SZJ8FxHH;mM3=C}NK-U|) zLf9NS3=Axuj59#uJi^m|vs6e;m%UJ;!B{rk?Lvt%W7YJm3ng)uBIcl}9`G^(0ahyp z1||V62LJJib7&su;Dhq7^sfS#vEOcY~!iy#1^>>vR z7&xHUDs!@kgYFDv;bCTAVBu0{VBjzZ2?+9V*jxcwecghAfdg`_vXGP(0|N)-T4f|T>fioM-ysFN?z*!1n^0VlGmalWx$g?mo z2uuZ~BLQR3>Ue>=>3)|=Wa~jq1O|aT(B3xz&>{sUfes4>24)5pKhPDiT_7`9gk%^P zI5&ftPL>P|oIAkG78V8u&ck44o+1MS=OqwRkd5=|bruE&p&7=Yn`*y;P7D*8roq6# zc^%{eMj;Og1_sU>Q7jA$OhWS93}OtNH$nQCg+O~ZIB$XOhhz~tG3|1Ryito90|V!M z(3L|BLeZdme;=fRjxrPi-GRdS5Oks&laP=V0|VzH5Sy8S<-zp8%O&a}M%oMvoG;W^ z85jgRIA70aWnd6`JiX^~i85b;DFXxNhZH6T21TLo+SB)5E)f@*0P@^7Kagq-&YzDV zs$YOqgBG1|{spUMU|BL<@=A%nB*9&C0+awtRZyl@bZYE7NCP zDRHW|15LCGJOEAJ3B*Z*l4>$2j|rRs-5f4ppv=I)D)2~(fq_k686yJ&y8!6gLJolk zMhpy`0+Uo27`OxqLATrqhzT<=@CbNV%Fo-a)Opm@=!X1&T$-uysXal+r85F{x!(uo!Qpy*_2r3r(rtiC2B3`co+Bqk% z8?>EXAXgmZ#RI~i+?WqiBcP%S@*-$O6`R0!6_6LVg06xVm<5Ue0no}YE&d2tgr1A~A7hb+j8ZZaS*wsA5r2n&SsGcbqtYQ=`-C2-F_D}{nxb;DX~SMlbei~K({1{vT>O* z@p3XSh;5p#b-lz&+!TlNJltd=b zVO)~jpOvS3-zZV7pDWA2zy-T;oE>!IIOrB&aEfANV0*#Kz`&Kx)XB-fz?H$3%d{8d zQUQ?T@|ZyC7`WL%Dxf!xbBii6FmRQC{h-7>iIIVUtCY!*oq<7xn;Yar=#AstaeNF6 zT#y^b>(dz65*Zj6xT=^yw;gjaan&)s1zB=io`Hd@o=FXKEIc=8^95G}I7As4*vy$3 z7`PglPI56YuzfIPVBlKF#LCUUz$?nlz`zG4z)6}De4jBF2iGYkAJFBEyCfMHxK4u& zVc-TGD8qGz=_RNq#|R1TvrORNW?(x2a^5*6Y0$O2M?mItfbVT#n<&P>z{Lr^uY^m2 zOO*L4$kb?%$25hVdcZ)Uy1D7l_sC6sGz_u8atmK&sxEUC@c(|09-h%L2?{VqlYyW?ZyTgWg8B{j|mn~E?*ynaocf2wLrFpPs4sLL;JAgTy z3~V}<3=CY3%o#ik45AWT&dl{cco-POz+Q3z8zmMCDkxpSfh%@KiGhL34eV{P9#B}g zgB>n*6l8%1*cl9LKbRO8xICFR@h~v3<$#>+$1DK4aS(Lm4j+hM;A8>W!e$Igor0{o zybKKDpqv`Y%fK+b<#vgJ;7?G}kY-JU$<$A8yj>zZ-Ts>~o1m&V0|S>bYd1`89Y{{b zgn>;Ll)iOXcY*9W&&$97E=Ums16vI!o13xThUxqX(kVP$?z|aWJ*aWQ<;n_j23sb` zpdbia0hG3LAnY@s^i~RHb8&H1u$F-Cg^dQ~i%M2dQf1%<)y7;^te^{H*|8l*~D~8d>+j&22(9w;9>o z7G!fxODx0MX370F*5jLOjC22D-?WYY{8xS~LmpwToO!SV0$43RHoP zB@ws<>P86E7n*_U*1MqAzCbwWB6EQxHqhPXY>l9}S_6r6cCPiTcA(pT!9ltK>JWBa z1_rK;U^Cem*pgTo7`QgEN`YcRk!ve!IY>RY@Z81x2}StwqC3ll;y91Q;FDZPz8G(9MobmpwPVm4o0zmphR&K957-a4|3fC`%?_; zp4(uDGO&U6&T!pfwF2FZyAWjPL)I&T&=Tf_AOi#6Pf*zaVli;CfZWQa#m}J4!1aXn z7wGO%(A8;>LIYG5@PP;hwr!yD?G39m=%!QC>DdoTB8Af&o%oXo6KRLW&D5HqgCF zOx*IIN9G|EF)(nka2c@)f$pOQ zHSf8M!MYi^LG61k6EKI78`Qw(GGzl5LrmPD7Cx65n8VD#2HFwBWzGh=ESXD&%bE>z z#1v0XNj3wQ4I3!wGSqV)0L7jyTLL2kg8;VzDEZlekL;CzSYi*hM2g!QR0TVLInoSl zEui*~BbywkH7vp9!nO?L!Xy?31};}NP{G5%9R^BUZeUATASStkHH$E?WrK|JU@HY_ zt{36*W&<5$1#y)RSOWu3N@f`YmoL~I0uZbHz`BJXM)`v|!VGMzAa?|?Z2}o3!4=GA z1-b|x?2ZtKJ0K>7f=zq zVJ`Lt6v|29a1wh7s*94r7KqgcgW7p1;2;o_04YiZdxC+@ij9GRD~+vLgn@yJgDZpW zC&+8npyZbcPA3f9s-Su>3oOCHz{vu#lkGAnt!A@b1v!L+E0--$lmVKF^T25pl3DY? zfdk5W^$c7k;PfT7Tolx-WboAuqDbcFmTnf zWr{*GVv{JS4+P3Kphg!Th|9pq03g!s#q-10> z)N{3gc?t|{QJ@N`gRKK}ceDXl7u!>i(+_|$MmN|X$2*^=$ zLHTMD+h0)z23}q<1_p3u=L4}AI9WiZa4B%jWNQUokq%0mT(iJz25wsoP=!64ty_$N zfrVQQ)DD^hZj5qpgEl&F&1IV|#=yYCy$Iy#d2DmVK=D2UR4318TP()FAi@pW7s|DW zZKW6kg9JC|d~2>HZ0p4s7-SeYSrmC07&uu#Z6QvUdN3Q*nBimrop;B{azYR!8!K85 zqCSFr5eq6Hm$3H$znh(_90!IV`iz?^_bz@Lb%JNZ%fq~lt%w&^fVBiil0kh>mJ(DyLlS_cRf-wPf z0sA}9o%5BT%VHTAxL0a3FmP9aIgH%x({-PfI56&?p7*RoE#xxja`|Sk6d!k%5d#Bv z3z);tz;*&;TPx!(aRvtP{W_qt-C#YiZZ!r5Zb@+Sne9918g@@+& z0Jcbuf#newDBMA(!3o~rsSlB2U=aGu&A`CZ05LNMltmgrY$l;J3kC+BCQuq>5qc;v zz2$j{o^6x~0|QSxNM1lBF|B}sr(=mY1A~xAF^Ju{UL16+&;|(x2A*zExg;XgZ_L2J z(*p`hQK8=H@1K{5*Zb=+F!1z);zv#>N0)(tX9CER@x}JeSXo(a91J4eS(F{V?AP?>Yv6+O5L9w+9#AXp%4`S~IvDp|{ zjAa-Yc=qZ`Gcd3evobL7oB@R#iwr10E`yoXf(#5ix4_KJ91ILRKS3I~cz9SC?@BW; zaC3liJ1dx7&%h13xPym{5tKq%xN|_!#SYFR9NbGl$%_Nb;bh=s0R;-1Do6n*<9tx& z=H%gK)Rkdi;0BG#^6)T%LW+SKbkQ{rFPOs!Zk_V*F@m%*ar1(bHb2-r4hFVOpdBUk z0*vpa85r1DK!vF|SW4;+Baa;8N?8U5?#T)a3_S8+Q3md1d<+acDvY4yz{0Jj!N90?3#(hLl|{-9*VAk+sM2MPeOnS?+CYP^9UHjB^&69xv}AW+n^2?^;kFz^P0 zdZau;pfM`mkS~l34E(Zh^cWa;!$9ge7-iprMoz;)94Ws2?r$2mCBFUIF{r8&^Ng2>NTfDg-DIG>x z&>#6Xsm#DAE>ia#3&0IQsCVW8V)ID zlzjqf2OIzu5hb7`84emt-=o050K(u{$~#cdgN~Hv zy$Z^>3__q@D(_8DvSMLii3bJ2t+NUYYz%@Wym#!T`@Aoaska7&@MF-pDTffKY~pF_=Wu?rbkszD+7@+T+?--BZCBPgNBi171%mR4q95OOwUVBq}%3JV6IUtA0f zygxyq#{#aOd4Ge_rHT-!e&+oHVyg))1*ML^AhyQz=kH5+rREzmF!25d3FvSu889&L zGJx-E*W)gm&iA22q25!Gfx(0uw9}TC6X|?2VAPza8Cfm zB`>(VbKnM@7sSg4mT}?UYR168%MX_E;J&B@8v6&!_;AkzxkwOPz6EfD>Rw(EaIqM| z{auEE!IxK*5#-SlZcsJOD+YF41vjW3=M@KYs<=TH9P&yqDk?KD)JR_kO`S+G7IHE$ z{Na=C&}3lXm0|=98?*CE`%nM%p+vg=3CNprVE6O!OIv{)11Y`v`K1#;8Wh0=oB+Qx zsK)2j0`mmo85lq(hJllcJOkTakl_Z5 zpcCrY&MGo6@H#T`Yk>O14!nyQcY~UJ8$tE|60r9fxV=;v7JzL3D;DJ51>&p+bJQX2j?>D}LP3;)4RrK3??y&XP_sFMcPry`6>#4rn}K&5Be<)~ zeN%;jfp_cDUI*8$uL)9XH! zNNRw3@4N@VVG#rF-SQp;b7HwoK`HVOm=njnefs`SC6X%5pmO*a*k36OY$rj!JkEF> zB3aJ~3a~SbpoSnjH>iWkdlsDPIJose1^z{_xqRFoKn2Am zFo&P}J1BQu0V@;W_F-jU;Jpc!5#t8+HF@tcg2p7oxi^CReh(Zd5)5od1sE83A22Rf zVPIgJ0V>2_gY?uhNLeuQeq=OLXJFuV1r6VR0<#&oML{9|nb8I`zs_wADkr}%f?81= z+_yjl!B?>7c(_?*7#MiJF@k1V1h~P~&v$StmEi{0IX}Q0IdFr6_b1rN3gAf`-d~KM z(#=kddoC!M{AR3SWMI(bJ}u9{!21W}G6qZTMW7Ji15cq?aZdv|K>$33V#6&9iabFk z#p!`xO5_=zPA~jYBFUICz57dv8q*rt>2rlmBft+JA=tVgMoot4^*_w1hW~q(?Lmk789sTD#!f{WX^1GIB9T$ z4rt|_3+8BXD@>36Rw7x?4~o=WlRkqtIu&VFz_x1vl+OTf*K$zz>WhAnq+{wu^U18W+hXM1_J{dJ1C-# zfaRrBRCqr#Jyh3bVBkqkOK0Hy0uCSs?wg>9`N{N9n}H!r`YxzB@Qdk<#B{0eC5rXO zK(YRhDTSMX!Hq?_7R39{^ii9E!GlGb4HUa9%%I!PeORRLfpQ2dGrJB0!xI*1FDnKH zUN&%l^bd>lK2R=a2lM{2NSlJ1Mm)@iK*!UtN+*D75Futz+pdC5S{zg!i-6~*LO7&v z)q~;ws(x4$cUU9IY2^`V_pi)4B8PwNK;*eekYREw*%ZfOp ztw3_JV0|SV(&ZqYGBc=XuHcYMEXZWw)o0!+#=y`cF6{!UhK-oTbr=}dh)e4#xH2&C znlS6?FfeQpm!1fUW>aQRrMg30`Y6b0X3U^8ctc#e38c{+%)28l?G38oEWo@6;?kwc7ICij8dWWx-q%b$x&{{cmuEtvO0T-piLjIjgrUW!XsgW|vu?6X(m(%@9;3g*2Q zmj)+OH)c>WeIqV?8&t`A?*xGkKSO>!o?%%IZmg|f5?sJsba4%T5{ zc%v+R0@P*;Vg|KnJ}66H0;S<#W>A^+O%F>|8L*8&O z@3*paE+{4y&6$W-tLm8A_!L=}`!N$VNz`zd5WT2D^6=iSJ zU|;}6I*hNb!@vN-U_PkSSqC2S0u?swpaKXKMqoL126m7jC|sa?&U%)2g3z8wrVcbO zvoNr&2DK5AnCEFQFtAJp4fyMUT5tT|u`#}mpE?W-0*0U?tOYVa2X+e72r)1)37j}Yyes~!VMaQ74Q{cV5sL7kOg(|1-L*# zC=javT2>*g4O&*QUl+8j;yybAgCGM7=zL$kIY^G!s}GW90gumt?pI(G*ue{O#C#2q zBPJMuR=Tmw)@ESfJA$O^W;RGyI%uhn0B9POv0gw-1f;D5v~k?=iS9&%m;km4Sip3CKiw4!&pCK{x4v<)4G(6+z>; zd@n#ID1fF9_+EmVstTZaHNID%e5e2#^yRC64I1=iU=g!mVBmW*U6+AD>I4%XE8}8A z21wP-#|CCIaG#fEVBlj1w=h|_K?#))GIXHAt;fc|z{d%$lU2Dv1vVcSBPfcrxj_km zj~m?7)8V!TS-}J5=yJa|XJFvtWz-O6VqnnYt_GP68Aj0O7Mi~CPl<3SD16PhMa>u( z_yocAxH)K&i-AuF%&`EkHsBKmb1b<**Yfg-fZGUG+&!R36a~xJfaeVO#27)#p=`N7 zOqcvyV$678y6@i-Nz-C61_nM^#siED4D-4DIT#rDAQ zbD#U(^x1z))V0@xoUg*@%*wzZ&nTUv!N9<$3g*Q#N`u2yjS&>C^BJX2On>{gMAPrK zCIbVX79(h3R}hnQv?T)rpEj5m%p}bUvQ38(w9qSrNgC9v;?o85LYbtiB^em_^uU1@ z#w5K!iGhL7fU$IX%D)mN%PNqy#*Ec03=C0B((-By416YFUNn=mIY`bF90oB=(l(&+ zSu=1;D}hP6d;0!=CDN8VL5{ElD=B4?J_GWl6_{7XBz*~Fku{iC&Lq85g@J+32F$Bq zlHNI8_#&J+Fd)<(Mfe%dF z1)UPY$+8kG2TJiuHlPctK zl=B!=K?}0()-f=sfmTw#sAFKLHk!^TZ6Z2d!J<}d8dE8&a0vs0>I()229PQZ&|SDM z>cA?dzAKfk2blyez=RnzLH21?fez$011<3c+1JLvz`!_Xw=n~Qc2Y_r1EU!zKUy*} zFzCdAPUtWL-*_IZo0y!#z-R$d29j4f2s#eJ80JJZ(6t4h>lhf!jTso!89|pJt20J3 z8ZoG9FbG1Nr3Tt=3UYk8G1zI-*D;pLaDyETTA&Jb@bp)VrHZbgf*m~EbI}-D$OKuZms zm>3wq&IYx1(L)w=S`^4}wI&e9tz{}z<_9@WZ3+Ve14w2IROSm)sW9vRItGT@(|MRn zRn@+lfP4(P7+Re%hI!(JItEqH{ls9spjl#&UL(`#hX3rursp!3N4DF72VLCG5C=|zE6rhXc^4Fyp-iy2ybH=lEwJbVDT78I=qO5XK*Q43 zWOInMhgnON>$U5_o?tXpXN+b7-L(#}RvvV-3Fs1W1`n{cl@<&PI^Zn$4rDE35F`P; z16jJ1iGe}?FX)uo51@u3V=y=YfpkDzpa#0r19Zj^zXjMXrXp1aRar3=9k~M;gK%2}B z?)8xatqX-Z;2_)qawravLw3MLJPufG2@0a=s_dn@jM~%xvzLmdf|P@8(WnQx>D zIv^i(K`PAKxmGZ5YoOSwfov;C5hOkkMJ3GJ;Z|U8XT!qT1mS8eJsJC39`y)38)yeK?>)sa0l3+IKT$k z0U$-V95CM+9L`5MOLgJCwudN61Y*_=gkQ-cM-?L+2Fac-8HDC*mF)=WhfV1Knu#I1t7#K`JYwsA>F@hG; zfa)nTP;t+=o^gc)0|V2<05ebvmvIBQHNiA75bQ!ZkhxGNf=+G#7i*w1?Lc{##ST)e znedblWD^4e$g2!frk~@3)wZzM zyy7sukgZgA`Uk;M7SZ&228I_7pd1ToG%;v^ZtWJHE-zUso&_$4e}K|*8rYG^prknG zGu)ABD2_}6JCc_L;>ZlJBi&hGj?6@HB*+Y?BSE>bdHP;{bVnX`1Vxz6G{I61y!w>o2SxY%@gp;A^` zkR9N%RE|LtY?niJCN`XstV|Q4o{t@iFxoogf{UbOz>|=u@ zhtJ^T0J_>4lKH>D9Bc}1C4OZBH4|Gw`yD_XB#^1B%nYDHPz_Wrfm(_IZculsGN^)1 zlLm(`XzLotR}-dh6e%@g12w_dyG=I`Efq0V%V1z&0JR(sLp7E#FsOlMBtV|N4izh6 zU{Kr2z`y{~_zkR464JF|1otK&wMV9Csbn@d1*L)tS#5Ab5mL54cZbD}HZyX`r_Bs1 z`DU;)Fqjvm7BevFf`|8Z!u*^U8HctN_UMiB^RnNe1#1rBJ69$biP`ZY-Q@~v_W02DgphJ=%8^Gbq&!7o% zq|r>!MW?bXpc*a-9KO%JVBsqZbvmRnm1Vg*JzoNr3l+c)hlMUk57gZlxp0aX$lZn( z)9M)*)_Q^632#8Dfp(*UBu=A97(iUC0S;_X9u_JQi37MW+T#mzi8s_GkambS%iZbcrAj3rWu+gAOF(*{0ReXjXq*Y;lD|HX z0zg+9HmLCi+A?(Ug~*ghmnwr3eA4te(xsAYpj^=CJ6%DtRAl;j=~7m(zygQ>n}!`D z0|O*W7=k+TM$bVvMYn@JumPOR{`kQ>&<^zgB$>6d+?{SCQ>rEhQUG-==s0(9xPcDg z0=YKT58|e&GBDR>L0!8NDsxAsQ~^?-PKC-mgUTq#mTKpK+fCrx$x^{ZTp!p?SNvfm zd@8tT;pc>v@TuU!#f}qJxTK>LE>Ha7Q4CN14p3{S`a{Nb&dQcbs~+@aU|8=D%>$s! z$yCh1pbB#Px_Sl%jV5sM3@+2_Ap;^Hlfel=j6oCRIwOB!1_s7`;BW*DRx!@`5(Ep! zeb8`(B!qq7EC5;rXa*W_W;_5(3a0l!{j7svZUZL+gB564o$(M$k1nX=5dvzy9%i|# zWyrwrpA%Xvu>@oK4|Gl`C@R(mK%(Nl94sn8gM}cOX91wmDGf+0fJO*Gg0g`S<+1Xm z!uq@F85nE>!NI{?^os@5sRCtvaG-pEjF2#>v4X2728I%-&Moq#!Voh-eR7bQtD!Ql z;W9B$J&&L=N(!aIeBcz+2bGbW&Zt-_Ha$|IRG9T}Jp+T$^g@MF5r`Vl@HxobOo*D5 zaLpf}nioJM9>67xpo3)BK@yrw!u8V~v`s{&J1Ca2r-A|x9ECCrnxM!sx(B+KiUHhx z0gY-h&bbr}i$VsJ?h6BQ_XVT~njJ7ov94fH5vyD83mq(491IRqMk8pSSPfLNpRZ?N z*aMMZf{fW2Flgj4FfhDCPLPZS43J?|BWuv@DL=u^+y*Xk#KK_C{0Vg?B&GcXJ2Q=o zAr;*B`3+u}+0F&aDv%`$OcMhj&7Z%FpytnSE@;vM84B?hy!8_u0(L!koD8G&Gdl$A zRU=Pmi)TGlF{s7U!oa`)YVjO~ih)`@pf&@jqE=3=C=>j0_B%!3+#d(+?__ihxa@ zhLBb*gP9IG`v8=#&W27ebS@Q}&Zkl;1UCH*#PoVK(8?T;=?r0T(>1m*;*6pSP{&UU z)C^}>2QI*}!(mY*#tLb6KnhhcR#3BpF&NSym0$(sMp)eq(gTSB5zHp^>M&4n8~TG9 z8T%lPVl-krUNrAh<3dI#xP*-SxWYru4GKarCm#7y1s#~u0F8S8M{3U)fvy{7OavPa859eOgauV1irI-!vsDg)+6W+3ki>y# zHpALZj**bCnxJ0F5{_&ccnsZW7w8g~T(FIx<3||hT!h=0i(+Fg)J8<=gEh<#M1m8_ zG>uZ>dSnZX*g!W3Re{Y0&s5KmjDq>53dQUysM#8zsdZ3Dfm0DUlnfXcjGll-usgx# zfX?(|obw27PA7^vomxr-FgGi0lp0k4C|txQNzFhI;)qV$clmC zI9v=8_ZpyPFsPIQyAISYVDy7DfuTw4K4{GQG}xUc;IjBw46LPc8thI!ZUzQORzD4K zs0w5n0;CR?OS7WEE)53t7{nVG80w-CE(Nu`<*XSPro+V`E(P~AL50C8hyfeG~Q4bMAxPp@r;)+QS z36NhvJ$;a0G$3sYh(D^#OZn>|B~C0C0|O&FXo&>FWN<{d$HO9moefmt+QK7(oejCn z8AU zijb73wvB;-0c5o-T$(}c3{;Cv9N21awTDovL*a^`R{w#6)Piu6DV{Y7*s(`H&DU@4={il2_^{; zhnDC;E6Lyla2Sgq@*Aja15(-rReDOVRJa}#C@T^`#)AfnL7`;}vciBt;|?^k5QU5f zLz_x>yFfh&$PlDOrfMRr-GD&ZB=2=1etGi6m+TmM6j)(HZtR!+i+VaqS!hS*;bGuXf$KA zAl4>)L!kqjER1CRVmfm+;WlEIz?XJODt2`CZ1P6nq} z4-L@j2pvc$K*|(w9|Jtd_!88cT?`I>P$!si&I-7X7ej*|(#KfLc6WNCQK^(1NCCt* zm<^KYDd5yr4;l>x6)cd1&Hx<}Z)Ig*VB7|_D+ye5JEp@zcN>ab+rUx%lLy*E2~3A2 zF;mc9G{#+QVd)GEQoIZd)>}ZAzcDZ{JWquc2WQw`GGu`I(E)1b7#J8pYe4K$!C}K( z^qx_jF`Bu!lMytD2I{XofT~DDHUeiHC@gGHrWTu8R}`^G|CBzDv%RBrq{#OfZ_pUNPXILLrrV3 z=?6?oh4erj^?7Mff7}PTk`dHVXLMjt1?}?yXFJe%Gf3mrwCREBCSudYOiP8>KpMZK zP1iFmm1MPUU|_cm99N)wY(Q}}4=x7E^=^<{uL`Ox z!9fRF#|REOs8yoorNXwLQHggb`V1JFSoH8uizV z85l&fA!^|RBcK8?xB(^z9Xtow3=T?V22GG-jTk}Ihc@W&DNwFwV4TC9!@ytzULvQ> z4w?dH3^G;#4X|s2cWg5T+k#gG=(2;Fir~_jJ4XiY8~BhvXh|R_Tu)?!lAhQ!t5RuJ zP_yCTbOozY5uNx328OS22Qz4-!7KJ?Mn_QLGBE%;Rc>cCJ;AC}q~0Qzfx#Z^EO)T8 zmchajBms$4(|*t;@?Pwq78vL(5(`kqK9$43U{(t1W&5*(TEy^CoB(#vD2_EB1A|&1 z0|NtS(rRiBJhaq6Crg4HybdB}2~MXmjAjfPpuqr;3?wOlh7BeLfU<)b1JW8snE$zQ zr%zNi5u5I0T`FA<(xsdWvjd_>1J-5*Wh;1V2E3X?8`M&tgcLPCd9c(q2^{>4L6B5F zi5=Qb2OWpQIE5WF*92>)gY-axM@0$LP!G(5M;3gb7uLSJlM70Ex@w?-(d-5Wh7WMJ zGN^(^*}*v-bc{MEW(}qX+LRhWCym%ZH4&&_vndq~b;^fzDCU62bDQ~KW6*QJBf6XT zV0Fzr@DMJ{sUUq2ry{Cr*ckLHkZoeq6>UppY(YcNEcu9Fj0TUkf=d1J1_lPT1_lNO z+gt_)HDo1>1`HarK#2@AMIoLA4&Tq9(F#x!XJ9x6&b_A!VBs5uGCUXs9v-|5ayIy) zvlvFu0Vzxq9l+@yqzme7cvA}0bp{2}gM3I8BxqNv6!zGVf#DyDqYOc5zyL8AC0+pb z6{8s_Re{F-Kq(Wnrpo{-VGff>fmXZ$1=G(tl!|eJrU;rF7#K>XudpkXhZO&yE-J_o zTMEF93il%n3=Cm;U>m@xIU3xG0WZW`$H&0H*Z`hKfDA)TDTD<@19%<*)^2NHzB}E^ zzEsKvqyXY;Yf$n5wY=;KVePV3X3)9-2hdm&W~EhE2zCx+fC`6unn4A8FW5bhxt8-q zF!%JLxThC9s}al(X-D>hkD6=bXJ9Y`N7Mvn(D^#Bhys}bbuws>4|J|5qxked2iSrO zP!k^%Ug1TcGD~!NpF^n(D=5-Rr>}P?l>}D>Q>UMGD3xXf1@+G9ZyieIqcME|o-LXN z>W*cDGcRapgmF%9F#`jn?92scUKP;P`P^c7ZiJ^DSe4{j49<B)jbJx{hCdnSgqOfVwGr$lSb@?A zEl|L21Sx_98zL@YZd5J-xoLVSTd5`|Xow8tCdcX3PT1T88GZ->h098?8z2L|-%4R_ zSc&3>l~6aBfeW?OD1{nG55!5}!H3_a@KA)8X%y#@PQ`SKnAWWg(Q!s&ZRQ-polqyFcG|D0Tc)i z;9{V19h%QIKm);y7;_b%fnZ4BXo9W)-VY8ONCa&tg9Xlhl)%{!4IE`~41rWZf&(*# z8q2`m2QLVy2iZNV4Ca53%M2jPS}+n2WC6);P=YB3PoRJbPsTX{6)^XdLrX|V4O9*; zAsK@q*{+fibo3D{+kx~zTqlBX9;_YjS`Ky|Cn%AF!Yz6FT-Q=bb5NOAQx0}0qXn$Y z1Fby*Nlb-GSi&SgEgevf+%^5JD{Rgb7F)l{!KF<-XrzGw&Fj!LfMy_H_JDm^2d)Rq zD`CFuLGfh|)R$J^`Nlp*(BW1vUxM^Ne2MAFr4GsB<;14s|lWAMxc8r}e9g)^04cSA<@ zm_1;fG}tIAPZcDmID3@JSb`SqXjOsLLu(&sYe($_Xyry31A{Y)tO0|@O~hofF|_3m zI*f{O71&FVib}H@=A~6oFF{(|tC;Ujzwc2hB?3|aaX-AGx;&lN6ISTM5~6T5Xgoj{ zTq`+ah9`Ko{S)Z;=Ivn1SAi4C4-b3n6}2f#JiBGA+TW_tPqcB@Xh8Z13Y)gXtf5h#%uGN^$X)u2RV z1(luX07^u~zhJ!xP(ukM9|@H&(g!8KiGd*PW(;cc7#J8pX{>hoMz2zNENKiJCV#{k z7#J^u!vs`PGR|383k#FWC}DCLoW^bm!0P6!%%C&sV1WbD1qmEX?`qXDFsM&I!da@R z0r#;7NDRIM#{}eLLr6Oc_gXmprcbGC{iZrtZKv5<$H2h8 z)sTVVcpY>H5i^6+KF}bj{tbkx?R5+c&N{pd3?R(vG-LX_(LS z=lpfT+aqU}YOqZ=c<2_r{pG^a`EiUU(-T?BM5dlClL0fBEsf2mPh74c!Du{P(cVsE zx-esz#PpAhWg<+LhSMMZv=L#noUUMRCptYFBmq*wWMMh|B2$?NlZ6FX!Sur*8IY+= z7Ut6xnaV^N%^+r5m>Gl27H6_Boqo|zLX^=2tbxhG7;1nK$R^S0Mb9lnm@O;}K%%14 zFZfA_GMQUIj4(GhnC`$_CcW_)O@-iE7+%C<))?(lTA&)HZz(|7wq>H zVYV;@J57|)2&{T~9c!8B^p&h-V$)mM%EXvV!9EsYGJ&|0(PVm|jG_pWg~{|lQ5KQu z-e%Df(+^g;i!fW5m`^Wc16v0Q`RVy=W#WubD@}~RRx+EI7;K-%R`yq#(Rg~|eDwC==H$)aSH$&!GpvYOE$XTMuSt84s z8W|&*Vrq=6($vHVSJr)ib@k?hngE2 z*CQEfZfJ?jGeS{{;tO+Q3uKihrpP=~6zfeC8wK^hSyrlu&ySXfM76DA>9 zZ()G!4hs}FS{S3qnSk8y7V765;_2@Pih2uE_2Gh~-ppaiysIb4n{Ud6)H z(sa6lYMErcg$2k4Si-U}LXHv(lr&&zfE*>32FUKPG(?dz289W-t1VH(+6=C`9^@93 z;4m{oc7mBXatK9C zquc`76=o>GVvZURCezO))M`!_SYXY%{jyrw$=Q-opz%4-{00L9Lp~C_X8P7cW!8!N zkc2KHu^%9@-yyL<2VOBkjZ@`jV1TiWkl6M}Y~SgDhs(qzQ;~$Kkl5|h8xNPcOI||~ zdX2>XG5z7;GG$2x(C#3prKU)1r|Ggs%ETpOk%Wqn*!9zWkCZ9bFGmvEgTy|8#J+;W zet^V&gTw~SRKdK<%8T&25)vCUJpxnH01*cbMKUm~hj75Hs0&E!Ur1~=P)`WzO(7(< z91`0YiS01m^JtmAWGRwR7ZQ8=^od8ylqL5g30*;AKb(H{Xj#0c7ic~hYH2(YI|qqf ziNtP4V$VThubf_btW3H7B9hQ6B=!d+_BSN={77sSB(@_{Ybst~B#1l3T5B+)*7<%u$D$&*Mz_mJ4Hr~f@srYtE8nskQhHbr7PO}9K* zrd*$eBvg;Y?m=SDL}G)E)P-fOYe?dck=P%R*leKfsZi?`kl4BqHt2j;1_sc1fG|U2 zArjzJlZC{tKw|eIv1cN&mm;x2Cq%-`+>0cB3W?26*i_=}tlr`5Uf)*-5eO`;i?nGj*L}KqjVxK@_UqNC&Kw|$zVhczj zl7I|^4M~(55DwUzCP-`tB(@I{I|7NFg2e7XVoyP0FF<0iL1OQaL`sxLkR&c3vF{+U zUm&r+Ah8)h6C==2WTO*cM1^7bJE75<3Qoor%OQL1Nb< z*lG-22oA$kB=$-q_O|Jn=gX9(o*)VRL}IhaOkZ}sOi5J_G{gdRw-pjQ0Erzt{q6ZO z>-zafLTi!OyOG!@k=WOf*iVtzpOM&%pxf@C*7GB=Ws%t05H={<85k@f9B{ICM`DK} zv6GS5g-GmrBz7+ndo~jL3=;bW68n#AFd`#zfL0nnT@AW*36>xfki>P6*cM1^7bJGz z^va86`|B-0`-7pz`5>_)kk~0m>;fcq4H6r4j~dJ=Q;@_LAhFjVv3Ee&kbpe`;eZ47 z0uuWU68i-b`wJ4A0kky_>H!`kwgeJe1&M8l#I{qIZg#mWuKqBR*fk_JcpEs>?Dt6G zOrW7Xs5l=ITMCJ-hQu~PV%sCJy&!DR2r~mi9E1Z7ge)X>84|k*iQR|9o`u8)-CPHY ziA_l2`=?i4DLY+17c@-+b^B^0_D&@BaU}LtB=%z@_D3Z4e`9?@=I|v(6 zPX&DIA!|Jt7XcPXOLvxA+di?H@#M7J-y~y84qLF^xA7>){-+o zTiKwtu0>++ntt(GSvI4=bldA?;=Dnil`T+J@zWEpm;Iieaifffv1@wfjk0W89(6=E zlR{!^AhCmy*cnLd(&>UX%d8oJ|)VjCl|9g*1nNbFc7b~X~b5{cc8 z#Ga~&RByVeIcnYFI(X@jydV7>TWj#MXzgLH@UeaTpjF zyphBqKNsg-GmrBz7+n8+5=U%t4@gN?`2mNNSEEu`eUBvp|z? z(5NW`vq9m{z`)Q8=794(!(=2j=)z8z1@n=_mm;xOBe6Fkv9}|!_adaT5}I0up;35_=62dlwS>1QPoi68i}f`x6qI0kq!?HZ;Kp;edlj z28peO#I`_UyCJbdkl0B`>;fcq9TK|-i9O2zsl;1>B(V*NeFTa98;Q+nhzL1xB(^FN z+Zc)Mh{X1Xu|dfr7RF&k zL)kwKkxD#f&~hBm=@ty2`>_!|6G9Rf2eF|!MiIn@s#gQCq2dN0_H}SfGMIwcP|NI) z*dZV`czYZ}Jwq&l!;pr=&Ihrf2GxMrP=i{L*waC5h(Qbskk~7c*k?d&sN=4I*qji@ z-7;ce5atAhKLZ29dyoXwH(x+(s0MD(qGzZ$=!RTa;UonTe*`f|9>j(kYJtRdL}G`7 z*ieTiAh9#+kvK&lHq_7x5F2VJ=&El-l3IGE2sx9fn9F=Jq0_zltk)y!(bzyK2mt?hxS2VJ`iV=E)6 z(EzcbdW}Hr$B@u62eF}!a4=!0XJCYK!ax#GpT#4wGmzMYAU4#XIuIMGw;hQ+7sQ5| zvkZy79*Mmb#0KkCU|;}UJq>fjH@E}?!+$V)y51KPt$Jfq2Dn3Qkk~;WHq^3cBz6iC zI}5}HTgJdpjKuB)v7ve=A+cv8u~&fDJPe>K${83ALO9@Xyo$uWhs6E@VzW;FwK_$v zUJA747izHu65A1p9S&kc9g%><&O~C@g4j@VW+Sn8BC!u4v9EyGtdOL|a2LV>JNg+C z`#p#ajY@8FM0q0!VuKdbGB7ZRnlms6L)i)-acFwd0lbaB(~`y&$j7l;ithyk>l0cwyohz)gw5r_@i zfx*DQU}nj{APi+Yg2bU}{2^>e=81)HK%QYp2eHA&)G{#SfY?yY;H?v))Ac&@HVY4ps9Ti49sp3=4H(D+UHe z(0)$_1_lWbTO68s6d@e2qs>8VsDm7k*q%u2AP^gBPy~n#bwn|U4Ru5nh%E^=lA+Fu zfdO>c4~W+Z5{IgpZiUn?T8bpG9>fN%uVi3g*aBih4cd#uz6@eR9eM|e{S=A)4#b9< z^996)nj>!wEeSyNvKojZ4RRX;gO)V|gD{kB3KEC9)ES8#h{TQtv2Q{2CV<#by_rbt zdJr4x&<-T_L~BsH2r4lPBmp&O0f-GXXg7!rb;KbM8+1l60|Ub`kVB#Diy(2Rn)^uX zw@B>oAU0_6Cn#rw*bu$-46HT`44}bJkRPN$Y^Z}&kl4CNY%>rWYLE?x4Kauz9mIw@ zA`irt2bsvgP-MfvAPi;Kg2bU}y1{Hv_%kpt%mi_uiq?bJP(|B7Y|yb63=9mrKn6kC zM?vCHHJ6dt50TifL2S@j0SpWbA3$uV-k(Tp{(4&m21cllC6L&PNNg<-8)}dNhz&K! z8^ne>A_&A*g7`ShmVrSS%1#7{L)GMf*w6yF5X629DZCkKKpdz?a^LG_+oW*q{@GK<#fk1_og$`xi*O9;%4L9$FxP_A`Ol&|p_aVrzidQ1wP2 z_9aMAn}gU;LmiOVVIVftGx1353?z1aA&3Jts2s$G8Z-mMhFUfs#8!h?w%DG5K^V$j z2NH*>*@MJBg~YxBVqb*ly$NDN^*(~IA^GnMhy!)$UnDl010r|ugV<1mq(N+`#Y!MH zXnK}`0lbGs7|J#Ti9^-cBeA_eY-s34IDpE3C?^&q0o9O$#4ZD|&qI7r4Pw8Bu=_!5 zsNSg{Hq_#INbD^jHq>K#k=VyzY>@xYgE&wNu7cQ5gI*%Bxf~JcLlDG-$CiR}zxpN5wI9v}|X$1xx_)Sx5~8)|Vj61x$^ zhWfY*i9H#KJqN@-4GGajAU4#TZAk3r&YbiFz3D6!(1_p*t&I}B~Q1)MtI8+U{ z3&O`@AU4#YDoAWi5F4uA0*UPeVuQ{^2ko;4vB4g;U|@&_ai9hzg4j@tvyj*gAU4#; zonZF#b30SS>!Ic?1PMX4ZAD@~1F@lQc?)72K?3BX3j>2Nl>G-J4pqbDitwK(hz)g? zG7?(@#D=QZGDqS#g4ib^7Px`fPz(IQ?CC;G2FmqNFEoIJpi0|7Y^c&%NbJ)fHq@R= zAU0@Y3g{diR|W=QDElEu9IECGhz)h`M-Uq-{s+W{iq~_wAx2mDL2RfZIV83whz-@C z2Vz6jSb*5zeMJlmwjegt5rIhTC?s|Phz<2{C4>#h?M)C4IHbBkY^b3VL2Rg@8<5yX zkk~hn*x!-Z4DJjJj8MHoAU4!uX(YCaJE*pSO6Y!jkl1^X*vCL@ zkU;?q8o}m-Ofg02gVnYpDiNrpR#D0pzX7fbk zPF@fjv^$o8fkDudfdSOD1vyU!Bo6g}782VO#C{1$e+*V24pfmVhz<3<7l;iN4*{|F zfsABehy<~rmL(yvD?n_hj~kKLT}bT7AU4#Tne`wJ)SyjB?4wBRuOK$m5r05z(8e~9 zJG>YegrRJ1FGNU4BC(A?Y^Z0?v3)^os0YH}?0N=9ynq3mpsI8;$361xS&hWelr z#D=Pw0%AkOXM)&J@fAqyO&~VtyaWaYhV3A>6Lhrc0E7ef@-+|}8c+9;*e{USA3>D6)sG4U;>@P4jDF1Q$A*x^j5F4sN3dG(C4ipA?5F2W!1`^v2 z#D@CP9f=))#Et~9q2{E4*iduw{Xj#tF4O<{)M(YOLXy~w#6AgPLoK+3#J-Khehy+o z4Q292WLHiQ8??oqfq{Y7pMgOb%9a3$Lp`YsV!wo@0}T)dDq##_Llcw*hz%8YM`8zp z*q{R;L1%7&*iZ}Nk=UgmHq--kNbGhb_5{#{J&aI;rhz1&25mrM??ht10K!gMz5?d0)hI&j6#0HrIN(Z_y4g&*&1&9q*6pF--0ael7Jet6N!Bu#D*Gl1Bv|* ziTxbJhU)!*#AXXb6juC5YzYLro{7m2+L%m#%&0|Ubv5C^JxD-!!Ohz-?z1&MtZiTxPFhU$HT#AXUY_?{byErP_B zst0kPnvIdzHc0Fs5F6@7*q~!K85kHI zgM0vGzXORw)%-zXvxgvxb5SI=6o?H~uZhGq0kL(UdEFAkfhuwau|X%pffka3*iegO zrVBoH6tAxa2|+#Hg2e7cVow9Hp+?LBv7tt6Kw=+3Vn0S=e@9|7gfcKNLiLJ)*sw`f zc?bs_MH)zKLl7Hku{nqh)f|Sz&O%~0BeAC=u@@k*w}IGD5AP2J)!b0d2_%VgAU4#p zw@7TpFoX|eKx}9rD}&geLoOH?7}UcU7=)p0Bak>$jRO+f55@-Nm{=GGbf7$l4LbXl zfq@|h#D*GFip1^)v7wHhg2bMS#9jtsL(N$OVnfZ@kHo$a1}d?k5^spyRSY<5V@_3=F~$4nsRg0;*^#5_>Tcdo75) z6`WKUHi6hsy}Oav7eQ=j2;D+rKSpA|0kOA&!XGp+1>!&rl8r#rxGEraFvK#A2nGgW zDBBn$4t1y_65AidhN?*gv7u^mKy1(%tqcqd1t4>v?CN@u1XNKc5_>v`4OO%OiG2{n zhN?dSVuwN;cLroAlzkl}4ps9MiTxRg{TIaE0t$Zy1_q``1_nl`W^N?5B8UwQMlB?^ zF%sJb#0H&A%D}+j1Y$$Yi2$*oj)(`b!yyh$j$~jEhO+Y_kxJ|ukRqstE)W~4XfhIe zC5R1m&?Y4IZY1_W5F4uZ5{L~o^CpNL0dd4#kR!ls&|P;R382YV45MK1l2^5PLI3Z#0Nq57nFk;y~F|AU4#O%}DGX zB=%Gg8*0#O5F4s@Jrer_68i;+4Rzdm5IY*;i2BbUA3!<(KoU?zoY9E-hY!StipwCe z)j;fx5QDTqY^XUVNNg_<8|s;0Bz6ph4atA0AP&@^Y!Dl2P(2cR1`>NU5_=00`xJ-` zwd^ty`wkNO5r_>n|2OF7N=7J$FNT2u##TaNTO+YUkl5)+>;@$EWF+<+B=$NG8|t|2 zFgD2l2Vfk~=o^R)4eHAvHs~T^1_p-fF$@gCQ1&B`I8@DB5F1+Se*&?g;ta8fLX01Y zEeT?Sj_CuPbsx*XpaxsRp#hRu4~a`%5F2Wl8JIoY?UjyPeH@4l^+7s_4K*ki#D=PG zL}D*MV(&y^-#}u&Mq+ctF)%Pf&5=W5+d|loay1OX0lPF4iCv4to`b~Rip0Kx#J&q= zPtS^}fe)W^$0O_)L1L?c*ie7#Be5-z*p47JH2i`~atr>ahkSb|;)&&%iJV#DN+#1H^_Jv<}3ETDBF$23;Y>z`(E*JZSmv36g+X5QN0e0I{KtD@0;fA+Z}kY^dJ(NbD6z?0q0M)STl;>Z&jztKK@!da5F2XHN+kAv5F6^C6G-ffNbFl6Hq@L4 z>7eo-YS2rN1eE~#D=O@Kw_JL*igOpNNf)zwjYQM(Ob`ui{LOc zBC+Qqu~#6m_kq|@3yvePFCek6f!GiW7~UhXIWid-7@^{VU^XcHL03_8A38Z{9hHt3#q1_p+hOa=yFC_5b_4pmc%#BN4n_k!4<Ak=PqS zY^Z~FA+Zl5vCn|mP=hXk*idu6AhE@=7#J9#;yNHU)N#fjb}6(IZl1-!AY2MbTuvYf zsG=ht3)X^J}*t?L}he2$pIVVAEs5y_2*xx|xdZ>h84x+l00kJC~j!?*9 zU=W6~%|PPND6j^xp}uhiv6n*Bdx6+c@lX&Osy+(DhPE4$L2Rg+`XVGwEr<=(&;(*b zEuMzNUXR2+jl{l!#C`>0Lqq5@68jGln>Ck#fpICc{O1O7pq8m1vF$)?s7qZz>}rTF zJ#!ftgrV#ZkT_IL5)!)riCvGx?gX(xSGX`RF!beu%73Wl86b&;5DVsl*iZ|WA+h&> z*ifGxMPi>rVqXWbp%&Z)v7zRCL}LGfu|egJKpvuql|*7IA+fbVY^dW5L2Rg@;UG5D z192cW=xAyN28N_O1_og$I~ODlRZ{_CL!-Dh4^;j`B|4BKdO>Wc_#7nmG7x(QB!pIj z*iZ|$AhAz@*w7HVjKsc!#C{55L(HjXcn#t}4Pwn_U|@u@`H!caP(}NY*e5}3sN=39vG0J`Q1!2o z*k3{H!;q-_1!99OU|{$MwG4EbgisM8v?M_6dZ;2r5C_UO2eF|(c0gi#BC&%&Y^Y@s zAU0HQ84`OM5_=aC`znYH^+5d{5C?Q$Edv9?gCYh7VJQ1GNF1u@I}#hzm|$E2@g-X^ z0|O&eJwFm#6~u;mKo5y+j>L8Vv6n#0e>V^ZYETpsy8?;57{rD;XcdUv0dd5-Vg?3b zD0?SJ9IECx68kC=`#y-h7^3$H=&Bt?sOGmI2`HPn1W_dOAhAV}*m58?)F2fQ8>-g{ zi5&}KLmiX?Vs}9-&M0AE5C*Y9*iZ}pfY?xj1WFkg7@=%QB(^??4K>FC ziS3BQ_5!h?jtc;>A?DOGYGfv1dtLAVzZbmAZhXppKRv5k?~wjeg>y5-t1hJtW z$U$h*cosSQf+v-31G(gen*qgrRI5kT^KB>KPcU z;2Z{qa3ppjh`4iE=)uNCO< z8W0<5&@?3W8W0=m%dJT4eMs!%AU4#TvmiFqoNGwzHy}3DoUafzB>(+`aKPSSuVP?e zgc`&PVnYqmMq;}lu~R{8sE>0%Y|tH7ptB#B|3mBeMIZ?% zdpU>=)vyu7J_L3f!!{5bYUnPg1)!G9IgmJ1?-dXms^%^d`!k3Q_5B|h8{~i1YD8tj z2Vz4l69KWI2I+&?PzRZT*wY~nvZ`ia5Qef{LE=y~!AR^l5F6^a93*yOHK_cDYG?pS zK-pa&Ht60d&;nr)8*0I1sAV<`3=GRb;!s1^fY?yI+d*uo_+Ahjs`nTY`woZ=35j}! zrw9(iJ0$jZ5F6@Hi9^+#hO)u_zX|1lv^)l} z=Ym)a3@<=zsOFDIZ1y^YZv>Fol1OYN5F2Wa28azc#}34XIwGtNRQ^Lbc}NmfNbE&O z>~$daI`9=t3@1QrsNO3eb~Z%(9*7MUe}u$-iNt;jXV)_@e1UTq7=9qJL2Xmm6g3N| zoPZh%I`{@A&Wj|De4wxdlDGmATLp=&17gF*|B+8qvH(dyEwe#lyCAVWkk|o8><}b& z3=$hW(Frv(14+C-2Z>XH#I8VM*CVl;k=Wfx?0zKnbR_m{B=%w?_HqatocJ_CaEYAh9Em*a=ANlm?{oKL<&o z0Eu0J#I8YNw;-`Qkk}KD*i(?$bCB2z5bWujvur)LOX!u)X=I!-ee3#ie@2GstQ*Sx z87roTf+(5kOF>k@^sgJr{h97;o9?!;+>g;<`qYi({){ctpKdJoXS%U{y4j|3KSrJD zt((gI85^cw-Bj++bY;hMwaw*zOb>QUFWX%1$7nMB=;m^NrY}3Ei)|_QWAvDwx~1Ho zal-ViTgv^JKJ1##wzb@kF<^S=)^dNw4bzu`D1qr;K~%wX*KOtgoEP>mGJuBLCrzLD zy+(ezLRtaK^aI<u5~hppEca*nb6|Sf&T>D-jOklDp06-2F>?z+3& zpK-_Zsk_VlnJyfi{%m)-AEU~2(>>+>j5*U=K~%-`t9#1*nVuY*uC}+_kCA11>E3dG z#*pbpL6pdJ(S7Cqj2Y8YLDZhdL-&J1_w@8-`@!M(6(s62-Sq&( zN)Tl*{V9lAG2QfFxj&=D^i~jcV)|7O1mxnY)4v@l_hT%X?s~M`pYg=>sUXT{`cn{f zWV-3G^7o7q(^Zd``!mK&F9lHr(~p8Eo#~<{z#39PRK)bHAWC97>&bF|#yQhNL6pMu zr66j_^sgXFW4i09a(~7()2D(cgXvE}l*e?_)1df!GQI6|xgX<>=~qve`!jk>S3Ohi z&$wlJDTwNseiTIcOcy;{?$5|GJ@qUo;k}x^?QFRpMF~2S?FV5alxc>3LAv{5ak0Lb)Gf!SvP(<^GH=)31W49n)1WLTm(49n+73D2C~x zmq3pDGd=B6xgYbH|BTbOUn=)yESS!E85HJ>)59*8`!VuNUwRqr=&vBrGfdOnu7H#C z)GOdfe+r^Brkh>`hgK_yVwrvwL`6(jy;kneIAwY%h;o^J6hxhvE_%J(pD|*3Du|Mp zz7<4qOlQ4O?$6jWJrqPWOkWD3M5ccQQ32CkZ8-cGS^6r7nlWAVHaNAHf~YOikAkQT(?#!qgD@3D@l4-(2NX<-)7kEp`!Uu` z54{UYCd$*7-7WWHx}q}u8%S7Xy6Zh~I-7bAq*#6WvwNWE+irTlJe`}-WBS}z<>ibO z(?wsGYcsBx?)bV~nQeg;6T^qn=~=JKm6%>!oZk1kT#a?lRR)IN(Q8S|&hzAaa0UFFWmU@`rm1*7ovn78EuOpn~B z=e;dgW4ggLecIb{HAb!Jd*7C;^SbacGh9$+V3@?nz|cRv@Dsl@)34m=eDBKDcyqcK z89qocFid7-V6dL9$m1=|7&ATgUAY#Up^>SXrNMN=SS1N&GYg~11(!9L_Q+0^N|)OH z=3Tjih`7E30|N`Vnq^^ZP+(x-=@esNP*Rv~Uo9(9FRsqOz|6${S%iUsWs4dE1Ct== zHfLr=Ha1ZP1{MQG1_mY}(CSuZMvgvCkW$uV>I@7l4jc>&Ok&2Ma}?s`7#Nr&L6`cn zWP+Gdpfd@WIau3O7#Ns2*w-pDFfg;Q-WLZ^?E6I+7+6`DS=i@EGB7YRatO9dF)*;q z5oTau76EN2WjQ(hHFJdm&w2?424-E*d( zVC(>?16|O`;tF9)%P}ypcrwlai5E@(#ZuwS7(d;PwL+OuZ+a4IMO^(akoN@sflh=L z;M8DXU=rZuVPIeuh*V@?U=e5&Wnf@sU`Y~VU|>~iXJTMrc_quhz@}cq#K0g}$jrc? zz^3cY%)lU2B*?(PrUzm&2=VeUFtF)^*epVzTgllBe3=;-IE11k7#P?LMHv|wc!WUL zMz9%)G72&<2ne}?G#LM9U|YX0IRv}&=AkM(RW(Ml2$T4uToMU2O;AA-rvcE@) zfq~5&Bp}SgX44I_J5rs2fz1{?MI}@w!@$612V%1bxq|Go{{q@&&A{>mq{tzTnSp_& zM2>-h-5F#y%Q0032KH<)^QjaA1A8f$xrllCGqwuR`gqVWLISrycYp{~D1*X=3zVi9 zSfcnD7}&eOYWE5;FtBe1GpDOFFtG0cGliHL7}yVknSo*q4D6RcOkp_4j^iYquOl=);qUib@E%)oMZ`bv%pf5{?HsBkcXyeRgFiGhKglW{W( z1A~~wbV1Gv3FU913=Hf%jN4cl7`Q~(1sL7f7#O&7L4tyi<0QGyPxs-hkmT2uW?*0! z0jFOU1~!lBC7czGIf^n23>=A**%%nWw?ZyvgI@jUz`)`t#=yYQ1PUpZ8Xg7)j@F%Q z3=F(SK=&nrlrgZZQet4>=s6D(y$=!vDdhuSfzHw`%fP@f36z|<*f{i=_}Cd3xLKzw za#cu)ISGKyKV^Ew#=s!T#$n22!_L4U7C1eStHMh2BR2yBhbrEGeKK%gRc2t| zh+r}Tl}g;Kk_-$SkxXY885lUYK^Ho4M1l2kbDw8oVBm-bb9lJzOm9Grj{vzhj|rrXfx8=|x&Ul} z0=Fb6HcG(WQsNc?d7+f4gN=bfg@c} zyf{Hc8OVGN@b$oK8~7L)I5?R>k;Wy#Azz0>nFY8Q z7`T`@Oqjc&Ce<@=m_m(OEX=^bVFvapBexGISy+HMObl#4KtX5847&b}i-*I8`6^U5 z1BWeCGuY>LP;@|-~Jw_kOdxKXE3mR1qHAt^FuBM2DTX>XZtaO zE{)^$;$~pr0}%|IEFfFhG(o9TkTr&zfdSO=VQArIV3#%Z<-CePy)!4(yS9; z((AaV>wYtq5HjRvVBk<@-31fB%RPNUnvJaSS5P+4VSUNXz`*+tWEUvafr}O}!N3N( z9)rV-m5T>zp9atL2Wd7E)ARW&SnFL`K?MlgcTf!#1Yyg9(sd4m{Th_kO2KR{E{+P; z#XJlQ+$y3B3>=lLpn`&d8&r{SRI!@yFfg!jgK83vYE~Z}1_pL+P*uWF!|DJk54nRt z!CA`+Dw8-F*xW!?)UihJ)H5(}adI@WzJ;6HglujzvbinD=C(r2Wnj|=#YY?KdL9M_ zt_Y4!)(T#j3%j5ufs3+kR!~vK#?1)I!ab~@(twj&gR!20fuoldRNVM*7l8`fKClx5 zxHo}fupewmAa^4uYA1j>LENW7#r{OF!-Ba%x9@UH0&_wb*rtGT>10;WrFvXm9Mf30 z!rd|**)1~=ZmDPBmnp9P3%F`C#F*fz=4)e+KT0atsU{8(FzQO&|ug zGLYs?tm1qO3|xvFTUkp$8bEa<$2L}QG02n5z_Fcm1taJX;vxo)9bl#)1KVLxnX!}A z9i-8VV-M>_kVbG?*^BJ{eaP;w-w*Ks0~_c*K8^#d4Itg#97kAx!*w4;)_n|F_i>13 za1G9J0_-|31~vsy1f68v3o?nF;|!}dKg`Exp(cS2KHxY9is^a=HU_qpp!9s6m7Sk~ zK{SHnBI{0m1_m)uOM>GPIKhkAfx_@IIFX9oRbyb_xB^aQVt$~kcNH8_VoacHdkq}r zVpX8p?m9TA#h!rz_Xao=#o9qB>?Sy1#H>K+_EtUEpJHGK-3Ggqfz1!3;|{AiKLZ0B z7s%9yte_hR!DYo$(9P5uJPZtcAQl5B3&^c(iJ+R|3F~)$1_oXp0r1_`3=Djrj149j z*mOVz)f-j`0R{$MBe((+CWh%b!WF#r-5}}Dtac!2PmnY?p4k`_85lU&*g)p6Jpt7s zf)F<7h9eF!Fq?~wL!IrY00Xof&|m|V0}POIKohKj5mF9lu_X#HFfehavNJGnXoF># zxj}784js1oPytXy9T=1tPE^|puD8VmMg%(z{SF0#Ktekz`zY^adH@gbu(~- znw%UaU=AZUsLjb?$_6T5n7BcWP7X6Lhnay5bhi+PIom~$NirPPY-xfF3_Lj{*$f;u zY@k%kP|tk=6p^-U35*O30^B;Fd}zl8s$V4_me_+Wk>ch7RhSN7jx+;XDJXax*+3Nw zmjs6k+hULlnL)Y7l?_y)FmOKsm8x!FOIRQ#xq~%}FtDkCjPhUu^;x*;ML4|K-ojnw z1J=O6lag7+z~KvahXBNCKd^2gh*ADvjxYlo=n5f@0Jiml3=CWn9KmenLJSPtV0VN- z+yOBu6l@aI9bsV2Y!DaLhl6coXJ7+0G&v&Jeu9h==ZIn}5n^EA$t=od;D`n*Vc;%g z1vU8CG?+jkbqN$lv237VaHN2PKn!%Z4@WB46AWzkL7|z()*!^dz{SCl!S)U0wF;1t znc#H7z+DMy)@FevSQt22Kz6cy1*O$&wo4#~aB$?Z`3b}Fa~?RYLh@}sIB-Duu%3aV z1f0IaEWp(r+jC|H28ry{N(PQ{wm(7)3=C|`K{>2~jYF7$femymBu6bz-rw*h60Zm>ZTsYMJNJz&)gY@winu9xi~$Wfa>`Dzl|FJT4-UM>+> z?gz0LI9WiZa4B%iWNQ*(VBiKVHR6~BW;1XHN;5FjbIfMz01Z)a`-2LlIc$BP%8y$O zR1VE$n<4^gE9!$p|2zkT3p&tX#$>Ai}`F2D+k- zV=p9~egQSWj)U1;TpX9#KsQJ7~%1Qjr%hwrQKiyU0cb)z!nRN?wf2**Fg4F2r)2l++zb>KFJ#_3M)kSfx;406hKN+ z7SM&7oW`Ick!80W0|TcAm^pR&Mu`eZMO85d2JS?01_sVbXm@g%ECT~)6_~@w{aJYW zYl#Yb#=z;?k`-$8d=d-{oXuc4KJI5q3=EttU=BY6TP?`wR>pcz&lF?|k-IAQ1%<*Cj4C0^yuviS{dQgI7U^&mtz`&&kGKZf9G z@m-98p^`g82ljIl}_ylZZ85sBlq~sYG1O!043I!Qh z4oERDaLqw-1k+yK>48!eVnOqyL4!R!%Aj#HmKm}P3|vQ$l-fxGh2E@G*i)Kz(qv!^IC)X3A|2>P8AM>WVWkm~sD;VPN2b3^AC4 zTPs{b;Hb6$cL2GBK^$!cOKv3%(7*&ED7{&6gRVH`5(P;y*no?CE-^;X0E;bm&h#VF z6~_LcT8m4X5mbleb9=HeFmTB*9$;i(sOO#pYWv87IrF(eVXex=stodn$~#Sr{1P8KttN85p=!!Mu1zDNymqrN#&<9_KSk zy%L>1Q>H?LKOE#aEk@AzQ4o{VhUph%Dx_6F?Po4sM$kY~D3g>d$WT3S$b>OT1E2J&2gZy9#R#M6&z3GoK=4l+qypWY}}p;#8r zvCJUUti-^;odwFMEJCMc7#O&-K}tA;SV2P^IUsQj$Z*qk(9i{_43J}B(EyDR<>pB< zFbLn^t_R&jDRdho)BrJ42Gn+L1hJWfnEt6v*OsrasuxvZVBl^C2?~fLrWG)7cVvn( zFbIhhgV>!Vq6`eeLII$bTsJ6biwLzTGca)XfO4X!P?8!019vZoEhhAom4Sh~4^#+= z3oVuhwfsP(rJN8Sh&=(6VdRB=aWgP*PXy&I1tAfTV9aA^GjOj11wNn9aZt>z2bm)v6r;+(z`fz7ECYjx zNC5-)MvyZkg!m;H7`QiqdWwLoT zW)OM_3elY)Hj|JQ$c$YeHjB`9Wd;Uq?%f~`8w1N}P$OzDXb_#Hotc4w`wS@PScE_U zav99rKD|e=Lb85_90LQl2*^lQMi85UTMrZiY>c2p$-?~`lvdcmiJgPn9~6HaU=Ak( zCkrS9*tUQaa56^8f%^E|+>9?k=79#)xp~0Zhk^SYD2efcIgH>@1#U=D%ETSa&M;j? zsY0lJl^g>D8>myrEeKQ0aI5ApIk5jIYuD6t9V5nh~ znhlC$cg8XW28LQjDHU}F25v7#e>nz*8;nx6pfu;rXeh?Oa0}F)(BK5Mzd)nXoGihh znF3HmwJAVHUpX1ro`Y=nVPud8%?5#5gSvAS7#P?=8@kuRlsPcSxG?hgvE5N*U=Y%q z{!h6=ToN?8%o7Mobu2>FDhv!fLEv;DbZ5GrN`-hPFKD(b3?$9LD9g{vz`zp@;&3s_ zz6W(XB0wA-Mp+wm1_qu;khy$}vd=&>H&LKes>Ud*#>2qC6Aj|1Gs=Pz7EdfFyJ;}W z{sfJ0#(`us8D+VquT!azl)fX%z`&CW64POn1&wd=6o7^|bs1$@a1A<#|3Jo7-K&~L!gjy&^0;$MU~L3S+yssABc|3ZL)foCyD zLV{5iGz zLERoBMp@9kyF8mfO_U@?S0lWjZhnx91i{5!05_;=OeV8l5qh$1H&Iasb^vg3_MbdGMo$y?EF$y)7NTL zNY~E;c~cJTem;JwX)+89Jdo0xpI=G@#8U(pa02{NpcoD>GO3{Z)4oN*G!xo47i`e&J7yr;W-OVh#cIVpb?FWVAJ`yi$Jk+3C!W==9&Iit3t9KG(y93 zmk~6QC(gYJ6gv07fg-`c#>maU!1I7H4m1^h8l?3#SgWK3BhN?1kD8#?5Ga{{0<$5V zHlELnpgVk7xI;nN{0k$fjl{uS3rgl+!5-n^UJUZpH^#r3pwS7vdJykBIF-t9gDasQ zV2&KPjluI1>|qK+~%OT6J!EaO|{(Mnn?&et*14Wy9AUS6u`V`+*?8UP7ypeIi34A$P;Q{ z&J1qf>2^95YV{HzE4093^LUDLO&EC0z*^^n=NEX)nLtJ60`N2hj|CH`$Xv)B3@YO- z!Fm>P&jv-l6_~S_`!y)f+k+jvg!>dIEjoZrTLzwZ<#A*JO}sAW{s;qu-DxRdAR0bYjCQ#B?BlQlHEBu&1El(XrDQ9^G2A(jm z;U^Z94p4&1W!l2Xz~Id7IDMXOg`&Tt76SuY zGe}D%SQVEM&kUyDAVal5F)a1kom!xQN}gp**4hjV+~sTx z3_Q!hYzFQFp!iw=b{uG+Qdbl-k_gITE1AT#85r2|KoNBWEH9~|!tg4*ulKN zEK;XHrtmP=Dl;%Juu5@*@}&?ns9{*aCZz*PA|lM73M_;}%CR04^rFn5j&m4?6sS|p zBLCTSLRqQ~l*0m;`SckW-Y83fdXPLp%%G;u2W2T8Q2GpJ29;*tl%gNnycuoXX* zrIJCVZWx&NOIZpu!_E^9=KWTdk^lvB1lXT{l%;e*HAf_v_g7g;859Ol%%IK;gNl>} zD72!%ay%+hZ$Vy)0rPlOq^5&xhy|+@P?1vQsApi{NnjSyXJC*~VPFTfsX>Vm-jXxs z2F(y_GcbUXAykyzQJaAQ6r(WyBRvKN5C-!>CCXiHP)`L^kg$Ua7f=|1<=7e6L4u%g zf$}*$Szd#d0)hG{D*DiT%EG|*22^4tF-K}MFvu<8Wnf@51TEbIU2McSr(K_cLB3p# zfnmBn1A_wSR>cMO3=DbG=NVNR*DFfh)EFkoO%0|_x^f`%v+ z85kIpK+_Ee>=_soKqIxM?HL$U45ojyuMnGF_goT^29LY2>KojJ5kOo#}kQ0?8pf)Lhbb(y*!T@5MxJiYK(=~er1|~yLSVS`wF(@*| zFcmW}DAX`8Fx|ARmDaXovV{6~afW;XYzuU|46wzyR?P z*n^wlT!aTXL4gW#li2iyrWIn-T}>-w96%n_H$w6tqZxw&XiqrEe;#0oC`NOb_ol+U z2Re`qWK;*pD5LuCP@lQMd`1QsRlL2kUl z$iSdolv>Qd_#Wgi#$Y8-UIH7f$-uw>GMd)}l9F7_D}?Jou2C~Vb&WzQ0|Nsn?Cc>D zj4sgdQvhuV2kD4_NI=paqZxzp90mpkm|I<;su^@nh%hiPN`m(>IfGU#%n3AOV9*8U z2ubij7T@&i<`tUipwKk@C&R$NC$(l7YpkDb(5ArVwY_SX4;ygFOT~$PVNo zC#X!7MTM{i$a$dqmlYYK;LcO(gc$~MCrHaA)9H-~$zsz_TT}=s^EoguEHed#0Z0pj z66h!oumzyIt3aynLM;%rtPth{%kVHl!ct_qVr{b6bRWwK;Q)~TbjUO~@AZ10S z1uSQQk{TqXfyz^md%r%$2L}`Am;%N* z6D`5PbjG^E#T5}ukO@Dgi2=r-No2-qM$ohr)5H*P0R++lDUXyum!g6lZwqyvlO-f@ zvTQ1pki(oNnA_uAl7c=TwGcbUb1B2ZNy2uvdMw1PoGI%q%zkP$5fdNryf;Q=b z0^H3C;^tD@3K0N$e+ z22RbO01%jNZ&xA1^xA%UtX+koFv!K=s8V21F}7x4Fnu9DeWG23aMDX_1_nKFG&}+4 zcP17F27Q0fTJtC1AYcsE&y#0hV0;ReWem}mWCQcSMOUc48Ym>6F@j8C3^M^2urI-Z zq0GX-pbRS5)TXo9R~RHcRbyaa`~ePf6>yMWumvRzQLreeSabqe+%Ev;gAETh0N2F7 z7(uZD4)zDO@C*eq860M?3{__X3Ffu-6*Axge7X%Nm_fNfkuiqRj6umCme@fDmV#pD z`t%R>6-MB)1$50VB$F{HHNez?>MW2tZCi-ZQ4X-^0NrB?k|~19%yNKbVA=M)gGU~HJr0O1B32cb+8O* zo_i__0|O*v)R;gaV*)O$)tNwH_?d-)0UT1n_VADrVGv}1ls&N8rOFQCpOua<|9~1F zApabM%Di-h`3E$N36f!iwxkT4Dr8te=}Ucjpi_mSFDOBS0uIuU;m`nuwE@(BAV+}x zr_P`P@`c%7(B_R3OxgAf3~c|wK*f%cfx(PXf`NhMBvbSB{Z19)^`NOh^KGDRX$~`} zZEEpfh=BowEi;rD7(kfo0;5%~FarY!^V(a1=H@_{)yJw%hJgWuSraTkgP|a7c}1Fm z0fhM;GF$FdV_*Pbu6jnxdR_(w5aw!OwBiO$^e{6p@QYb08E`Q$fH2P=W=jtq1_lu3 zy1{7K$_!E9<^ zI{jmjz_IBU7#ZcJ=ke$WY|rYg=wYolFlC63Pbv#*^>YsK^!I~^ z7@><8o1u%CV2GF+qpLB;6tQF|&fQ)*xk6Z5vJK{X@Pg96ic9;}F$tV9y(Lt@XKZg{9dTyh(d&}k(0 zjp>PpDwOLP_z+&+|Y;M9F( zy6E8w<>_a5bb0Cp`4NtjLt=vlb6||;pmH%M$=P~8fRE@LFN7ZN)RiJgSRE*C&baV^t*k5pJo9z&A9 zjl_O2ec_P`Wk~^0%K&Pf5fa;e`rRWH%8BVnLN!S2P9*j;B=!;{_GKjY10?o4BsTN( z+@lrZhFYNJ8PpXPNbD#ib~+NfbUN>^bn*IWNJ5K{*z1tkyO7w&k=S>T*e{XTf05Wi zpe`cRS#n5hEeIQOQn?v~1CDHeBz80sdm9q_G!pwU68k+8TME?QgIcUUy|ywt?8Va`DrbrFu16Bu zI{mG3mU#U^B%$L-?6XMh%Sh~-NbLJa?59ZV*GTM-NbDa-Y<|$8g3(A4nMmw%B=$Na_MYi`>(az?Zy*Uh zLt=kHVlzo2+$ey=mP2CeAhE5G*d9pi*y)02E5sR_rx(_ziHFWclG%a8K8?h_j>LY9 z#D0&&{*A_XDOk z{)!f7ES%nWzCu}YK9bB9B=*7Sd(T%WGrpYu@O*_hFE^-r4~;{K>8uwjtV5%agffuW zWk~E6B=#gE_5vjKIwba<>3=WfiyPiR5_*Qj1}%hv1vrxeA_xSgH(t&cuh&5mvO;2e zAhE-c*zHK{$w=(&NbJK%?DI(M+eqx^5VjmRbU#BlVD^6`HqZ2l7c2JHe^x{|n;kTQ z0u5AQB(^*fTN{aOj>L9GVuMFwpyos)iKip6iy>@C5m^u6fZYh%w*(8*=}6*>k=W~z z*t?O~pk;wDy_b>1?<29_AhCZcP4~N85jTBDYZ_1eL}f%s%td0aLSpYlVxL4}gSJ`2 zEPjY2{uYV-3yICDg0M>x!j1y_UKPRtvkj5hwn%JGBz7ngI}wSUi^Q&)KJiM$>G}xJ zI43k#(va9CNbDvg_5>vMJS6rSB=#;O_6a2RTO{^R2piH-;RB7RK^-AI{q5BXab71R zA^+)u*D91H+mVD;BC)qk_q|qO&C3EBSb`cNIDP813Tw$=B%ur>cIot&*DA6ZUr)E~ zOcUqj)j$Nh)bz^h6~B2cG!a6s(;IJ8WKaKbqk_lqDw6nPBsQNGLcKB)+hDrp%?fMP zA|#OFSp%qB%ZAk1R zNbE~U><38fcS!6%NNg@0gmWd3*lG|qBqN(ZIN;>#gv1U&V#gt|bCB3oNbG4y>?KI- zO-SqmNbGZ@p;F z3le)05_dmR#c4-)$n68i>(4GG6*5DqvTzaX)h^bl?rKw`@wv2~ExR!D3QBz71Q zI|Yedqz5|14VtwYkRM}g|fGS#Gz^qfY|Ebz+yNCVnf9*fY=-m@hc#`Q1*S0 zI8@C`5F4uZoj&NKH>jfTAPFd&*MNb6ksV@?7!q3^iLDA^L)Ggcu^m8cs9sMbb`TOf z62yi$$cP~s#NmWkmTthnAPi*}fy5z-7-~RlsH+>Nmrh7ij#>f|0!VslQvb+1CMUd@n!fe~t^4Tudj#}$d~hr|vCv7zR~ zg4j^K6(Ba$8%-cKH^i%Lh71hCQ1(QSI8@DS5L+GE8(je6KqXcqv3DY|4};jCtplJ1 z6CgHJ{Us0^v>XF;StE!Iwd?^B`x}T2_1J$THir=?UqB@UjTjghp%#dP*ieHEkl3C` z>>wm|28azcrx1x2*_S}#P&Icz zY-lQZ2x3FU-ypGnA+cGE85kI$>N!DdsF^~>pnL)4Xn-W3J}^XLTOqL>Ky0Y`NF;U= z61xJ#hMLoe#O^|3PXMtY=F~GR196}}SOa47Lwvu%n1MkU%H9nUhpIUWVncm%9mIyJ zd4Ro;d>}SIDEvWJM}s*Kiye^Ikx1-(5F6@9VxI%Cp@v>ZV!s8kp+5VD#Qu-O<}n3ry@WVU z6p5`3Vng+sK-pmb+d?@YEzTe|)Z!Qcwm28JLI2O1xd zAhsYV92gj4%@`Pjq3jHhI8;qBhz*U`HV_*sJ_(7v5Q)7S#0IUCWnf^~0AfSU+zDcX z7Gr{}I}hSOeRBhe{Sb-$3dDvQ^c}>88pL4Ez`zJ)i-FisbL5fO8c1wI5F2Vvy&Z@H z)f|q*PC#Opf!I((>yg+UNbHFqHq_ARAU4#@)ky3uNbFM}Hao-g{-cgcl2CoGL1IvS zU%>3?r;a*md8%44Ffc;ZXoJ{LH7-c(d=MKN6J;Q_Feq3V7^*B77=)qh*6DAjrHR)s z07*k5a03#1D~Js>;xH2XJQDjY68k%dEf2Bg4~Px5hSidRff34<2C<<*rvhPvvmApi zgag)X24X`Eat5)Xnq!dIHAw8~AU4#Y^FVCS3IqlQhDDYP48lfybX zpehe4aS|i}W#2$zKL)X(8eV|dP&J=GY{>Wn!*>uHD$ZnusA1SaY^Wmykl1P_8Op%G(1FCBh{T=+VnfYbU||k=WNkY^eGVNNhpSfGkwp6U2swN(hK84vt}l2x|rgVF*oZiQSLHo{Pj@jl|vtVnfZ@4PrwqVE6!HL(TjSVuO~4GB7aw202242jU_& z8&Gq9df%)xxq1~a8zOFi#I^#lK`Wma7#Qq9Y^XsVNbEQe8ya%yNbCY6b|r`nHK!iL zhMF@2!Um-X28M+Y4%ijjL2Rg@2awn&k=U0&Y^b3(Ky0X?Z;;quk=Wd}h)O~Pi7jgj z$`Me@)IbtYLv=uGsG+7vY;O=7sy+mX9gD&0q(LVu(05hz(6E0w6Y2uZ$fi zM?g91APJ}<9S|ETZU$n5mRK?{Fj#}wPzzj;*ij%h$TtiO49Q6B93*xrhz&KT8pMW} zQ_s+X;4sVrv7rVnMq;l)Vs8bpp#~iSu^|RAoJL|l1hJv!yh37sMq>W~v1LHv&%nUI zWY53=I&%yZU>Zp5NDvzu5`{?YP9*kJB=$li_EIGFDkSzgB=$A~B+f1*_CX}}Q6%=6 z>1W?mh}U0761t7Vet^V&g2aA<#QuQ9{(;2)gT!WWKqMayBsM>UZ4L@224M&X%$7!C z%OkPXk=WV})BVIVthNihtKg8Ip3soXGF^tZ(uZ-u^i1AL(9zU8K@`t)PQFTi#ud{e zK~%u>m3)={Ob=E}|HW77#~3l)lfM#lMEXn+)ieDih+>&;DNqSIS-Vr9(x2(Vn(4O$ zD*c#ltevhUSb2=GVfshGN`Iy+>!v#iRhBXRST}u_P^BN!i}lmFge(0Rd!|PUSNby= zOkWA2GN%6&uJmVmv30taNTnasmmSk*f#?^zr@s=Z^kY<*ZYf&n&&V;o6GSOYzbRVj z&-CZeb}g~WK1RkP(|3wjYV#U{mg<571$19WeEN>nN{uAgowQK`=Q zIGlkYXnLSMqww?siAn*cC;z55NmQz_n#M9PbU+SCJ|Iyk!1{!pks)S!VrYi&^cNuh z-dF~P3W&UbWTgP3!*oT-N_AG#I0lAe(-l>egr_HfgeOcd1PT96XJBxfK3B3*nbC3j zL6Atz1P16K%+sVQ1sJzX7nG`0XB3!j38GY{CrVYSGwl$a-X&G3#;7rUBS_R^`c0`y zb=Dt?85l~ZC%z~UnJy_^DFi!mdE)~GiS3@!l~w|bTei1oSH3o!F4$8c&SGw0VX(a` zwlbE3(O~+E)Jj7}qwP{@m9pk28bjw+{^MiZvOQ!?rHL7{iKY4W?njj`SU{}l=M!o* zw$FQBIoA%R<=}pH2^LFZBa`WO_p_@r&e-0nR<+o{#IOoNg`7#Nlw`K;(__-BBtjDn7#Nt2bAgU=js{6Ev4f6@V3Gix0WFye zI@p4Oe+W@Xd`QS1ja85o$1K*!vOfDTAzGM#=hy-I-x zbnFnbZV9Mtk)8fEy-LAQ19Wzi+7yro=(sc%jjbT&eb8b=OFdg*{b@fq_*{ zXL{c(C#mTP8C60|?aI^l%yN=qda5BLf5LRY?X07FP(nRTX@Q zGw38l)|Tn_Gpd{!*G^Z?tWstaneLuhxaLbBrXU;JRnQV>p^KmmdDmWo&Kwf5Q(|CXyZ!~V zK3<4Zl!1ZmhCcXkAC9~gWZpw2M$iGvj|>+cmIfFd)7p$FuDQWtn>?;3yT~Ii2FoHZS8pX`Oz{bh=fti6pbgK~P z>_J8q5PJ$Q=wweukV_a?_eq0J=3)e`!{roV6JTrxoumw!y=N0-1O){H*HMs>LSPOf zS1=m`1Di1DRx}1CuH}jh3~VCcJwmKU~m1#%D}+O2s$nK0caSQY1ee^+$t&28=ym?!RIA&va#zkd9yJva5+qm%B_+T zO9UO5WyGY;#=s!L#%{_~2|76W==84KDk}}p5d-YDOd#_axz>X0vIBFNxNJZM+B1RU zfou8nH@Q`6wq>A$v;)8jI2G8#n6`qB9ru*krNjk3t?R<>^8^Oy3+EU9N%k&0x%nX;PA_D_^9N0_&t|(0g2KIQc z?GjuDAg3fUMS_k-=K3x>eRW=yYW)&P1_t(2utBm6Y!5;A53+-gr)FSaWMGX29k!az z^p%Z)fir_Wmq`=(@{`Ug-aQ<*{%R=g96tF(8<;%U_U5vfwqRQmogn? zWnfU@nhJ7N8Q7XsuFD`(%fX!bGzM1C1|s$)N`zfX! zAQM6Bzu8ZN4PoFa;$mQ6Kf`nyR5&t1g8M8axEWXtc^Mek&oQ-w%wGXApMx0`v89X}1RdiAI@Xt6jQI#?#GUKC4g&+bII}tEY-Fx9&@mGd%ooAY#t$+_ zlKCg-zznWr5J!p`ZWn>#wpf-X{QUjaB0WnD(Y!Vj(>vPcAE1Jx{pyODW*-e;FKuxM=U^j&tWeG|N zW?-)}a(x1EEWjKl238r+`Rta=(?Pm<*ln1FKu0WteQpcY4EDJl)E!+~3=Hh{V9gv{ z;9z$Eb2u4TZ9u8qk@*TI1A~YJyEAh=Xg#qg*eDmUQKBt!3=Hh9;J_6HEl6Q^1AAK( zwA_>39qe$?P>=;4U}rF}hJliUC$k(E0|Toa=qx!u<{B;r2Htiq1_nM5!N9=+vW1la zlrIHYXL2zxh=C&XAQuC}^e2T?3W9B*(2-_63zK<0{b6C1usA5wGO*qO9TKn13R;~E z)+RN*P+U*Ogn`u!6x%wiYM{fBtwDz)gCdjSL6|4_H2drHM`LU7}R5mbhfoc=> zD%L`7P?-v^z?Wt$4Wd(VNvz~!sGi)T~L$2rB^pAsPtmv zDpg=$sAunC1r-XMT%Zky?7gg@LdS<|BB*%n13NK*D+1)ley}BhT-!h)H37^C;yT2^ zz`#Bc?66?2C7|$`1m=V=u!`z2FtAT%HREAm;Phgj#`+2Fmg&fDsh@%581|VEw=l4t z7hzyvpT&9*q&t9pE~^dbEH-eM%tO{aA6fGPh-R)!pweU^#3Kx>jiAdB7P0;V9URyR zO3iB^G04uo9(1&CJp&im*bPu)yVMvM*f+9zfT}_U*7Yn54D6d&LwFe&I2GBqvTg)9 z16&wxV+9w6+{p~=+gT@qwgGV$F|h9dGX)t~1wb{zPSzHXMlbd~tf12rAQtU~S_F=X zeXR9}s9@g@@c;v>3CQ;cSoeZ-d$S*51)s(TcIHuJ-N%r9e;lHj3+%cRVApvuus#J< zA17Hs$NF=!v!7wj038?@ zAPQ{ zGn+vfRS9%Law;gRgIEk4EFibCZsBEMV1L4D0y-ht6QlxM1c21@fd~dxH&Ai)hBXwV zARjb?11Tgxg*;yl69WSuIAU36gOq({tp+J;1DOL6W&+jWY-}K-SnEJ_iXepT4yr1| zz-&%7c6Bx;&>1w~@<4+PR30#Jfy)C;unI;%5KEw1F{6v{A4!|R zlnqqQFmZuepzLN~4l@HQ=oS-pb2dH!(21-v?AC0HK}Wddlw>oo+pvL>GXs|-s6e%4 z^8}rg%yk`a@&|K-8CYdN?g(Ie12Rd1J(#ToblfA@9U%~RKuii{s|R@r zHdM zlajeoLFHa78>m7MWMDlD$}Mqh4T1~|A~Ng=Y|NmOij_cVB@rCtqV=XAKPQ0$N>mCI zP|08$M0-H>MhZ9xMB6}lD;4Ys23AE@1_t&tw!I+taIj~v8G{ZcT?H~S6P!*Mxa>eR zT^3k^g@JFJ5aD3YW$OkxL|25No`F3NoLC_lI3FB3ko;HzPG8_2 z0(&VNsD~g9+Fi+B&SnW(w#6C`s%JV1NLUNPoP8VGK(14Tk0WU$PEtARxn3^8+24MdmEUez`%MMRO5889RfMs zfW3=N9&}`~IVfXvgAEc-En;Br0jp+U^#R3JFWWzmqdtNTrJBTM4mv5>U6_FZTmbNa zSPUF2AX7LM*z0Gq?H6WX-~ydhz&;DiX5e}PYT?diJ1We;z`~^fDx2o8fwm-YaDkS; zvCn0@2s)mF>m`T~Q3WH8c z=3wasol?vKYVL5byygO3OTYqZuW+#BgH9u7VFHuWK}Qs`XbUqiu>8NE!c_-~ zy6YfLJp&upK~Pe=!Nv|c3z~uT7U+(ln{2|M8>S9{nwt06%0w6#cqf3)M+V2{Z%|l* z@(nmZ8JNsf85lUgw=_xQNii@eaOi^eQ3%Zd-F~45VloI-g8ZWoVzUT2f!g2(QlO*w zg|zEI=Rg~RE~VfRng%-e)Cj~D5CX+EhcT!zA|m7lI)Tds#Fh{OHBLE9L6*x1fmS?o zn1PC7IR*}v*&ye$fLzJM20GZ!93&vf!(kHvKK#@GbcYV8d}k0URAyk{umiDKg!IKg z4zLFq$icvL0Hn%6TaOYg$fraQ_$5 z8Rp~wb0D2zPEMrGFeewRGt4K>z`)7P*e}Y!z`+7ChEssEg0U5JAh8PQ^v_DL5e!_P zRlvtdgDhp_>XT$(;H-w4x0RJ)dT4ExAtTfD_S!17`s*NV&0uYOT;H_7hf9OB@iVZR zfgIk-cpo&F0TNmWszE`+EsPATs}#V;N`r)1yJQ#`I6awniZL*VfocoTUJ^*H2#Rk8 zrV7w;ym}y|{GiKR8Mrz?n>7TMf#!nh1!_S{z6E~BgGOa$X@X98UM&t9@_7PkatXW? zU|?Vq*sH+6z%HP~%)r1Q@C$Srwm>HMSZUDl#oPj*g>5_n0#XbNyaL{8pkt*YR6xf{ z-&X@2E4_)0fkBXg$x0D)tTd7%_JU6J6sTtgbxH+5Jw8SOULKGm+?7C%kkJMW=`lT3 z0Ua}qr0w`;&@t0?v&`n4T(9pT5BEi5Q0NVG)8Ye1_r5GP(S%OC0!nG>pUb8dOFzFa_!}FmSyIkYHet0iTH-13Izx4u1D6Om>05C%g4`ntmazd>_*`O)ps_Yv zu9wq~HB=e=5uL-hIr(_%Jy^lffBbo zm~)=%706!-V9tFm!Ra22RqEPYATbq2(6F04qpXM$_?&DIFP>2r9PVo1;j{USvYV#Q zYOK=q3sPoa;L>6QjU)y!$!3Fmpbh2)Gsy~pY|~)`jVy*R$%1-TT)JRhD3k1BJ<#dx z;Lr+Vl9d1*aBaYNcDi6wm6D|r$Xa8@0A|qH*|K&D;Ip$qyl5s_ZBWiI1qVwElk8`Z zPt6!X$s&PCcINb)rYdR66(C1gf|Zmq$#Q~tR$yKklk5*r`mhG`%9&(mfe!Jt0rM)D zWD}`?K`p~|OtQ7p6`QLxtw4=UE)THd_c6(WPAKB? z1oQSY$=(GW?(GFO^8l0VLQtE~8_YY%B>O>hdP{SaM*VCF1_stkEDQ`>fs9o$pwh8H z22|_FFfi~<01=>LBpEnZlE8AH3?it*opDu$fk8+G+#&;I2?in1l4|ZOP^MuKdJZ~t zI2)vdL#P~dbZ-twT!R5zXFdguKY+?YIR>UMP6kZ|?%X*t3=D!dxa(~}r!9kaUUN4< z44nyTt~7$!OhTd4Lt3h=>#KD@XKaIn1cV`HY*&J+8DYp7+b!TTw(~*97I%ZPg^17z z&@pj6pkhc=2y}QEcQ1%7CNvdvzH}dGtX5nIv_ze|KUtK4K~Cs6=;+D`pv)#Ov>0@> z@I+8``zNSTAsGSDH^Q$Wsj6xskfx_3Ir(0ZY2T?Pj386b9p&^^%U&@(~4 zZ4oK}orydvPn3aSgU}RN&>7nxL$?U2b22b+&jnd_MF^DVx#xlOUKR2L1>k(pNai(2 zp!tHDv!Fn$w`E{52YGM72N?zirq`g8v6m!+io#;hwE&>H72KI(VA25{w!EwkB-IC! z0u9GOqy%laS2D^oFbLU!;${^noEU`UKxZ7U1{FVyLUEu|{nmik>_Xb0W2e`GoX9K0 z$iXn3r>%;=9;919=qkv!8`$L;7(|3YCu@T&mk;Oe3gV23YGioP@%_Icc^uxUi#AXrV07dw25SxvGNmT-L zrCz-RsLlf&_s4w(6ktq;LBVht%uE2q*)1?L0~EzSK{`2kxLFvFfzHGSwK=(2!E6Su zL!kPEjS-YMS-3<%Zh^EaIJmZgEQOTKoD3W+prBv{H5#}%89U?|)EGE9xw#p|K!pLQ zEyN8ekQun_LE3o1xsQ?S>U8_|D#d!xZY5UG#$9f4aMqInAFn+LRCIKJ4$+nei!yM5 zmauZGFoI&5g=-fmHq;qGs_t-I2StYl;|xUxh6h}pAUA7*tB@zMUZAw3!w70#urSJk z?kD5c1s6aZjIt*|y7U<9LFEw-qwFD2VCXY~PKXs?l#|v ztR2|%sf@B6AXDramFg8h$7{>FfO3Na*ur#1Sr*Xw?~aUTR3s|m(QT7AqbZ>XYC5oUkw`Di$gU{Tql?R=YfJ8 zpMd7aZo`y0Fvx=r-R1(Ff$R)As?Q&ko*0B4fsS|#0I`{bKywy6fgm=E&{rJ>2A&{L zdSMfq3Od|TBp5W%#3KZn2jB_0%gDgMuW)I4L1&euX$9zbzX*^%9!3Sw0(YKBkUe~i z3htnzOQJxDSdCEubfpweG>D_lsK7jZUuTu1nJnn|)Ob+9YcVRcfDZOf2Px2IR9FH! z&M+6m(P2~ojid7vfJRt!85Q2jPUr2aQmqGd%XmsaDy$h5gg}Q1ma;N2FxW6MfXinE zP!|dmLQL!+lAVEx9dy`ZB`8SbL5Fkqt1vJKeb59Q&JAKR2%Q9-qS*$z_mD+M1$5M5 z2Pmlu2xWl$-vufOM1-z`PM_`uiPxJ5iGx~jy&wq-A<%sgJbfUE2q6{F1m^^hc#P0> z5PKp>yhdmR=;YAJAn^tv7SLIfQ$XSigv3GYX&~_>LLWhs$J0ULM}(9>=XTBliJuU9 z2byb`4HADL1acxz{XEb-2<&ujki-|ET99RnKpK81FoKS$T?`VJU{nAN7V<0w#h?tM zLOSS>*_9v}1x5wXsWv>|GE#+6;TK5H`cUxU+zOx`GS5a(Puqx5VJGN}%1xklQ4*s9 zXw;UcejjL9s)$hm)CS?%4;q;+W>f%mpLh;{BD4gQcwe(JFt9CEVPF7Za6B+EaIkX>vuQGZxlnSnu&hv&+5P-Mh{62MhZMrRNLjWP1v1SLQg1}1k3Tg?;`N|gv3MSXCbBrd-8r5oAiE2|H4@Kr5WA3p=?Cb9%a@N-7#NtQf#UTe zDACA+PUr^h`4S4$Wnkd>0tycXA<$_nJU>Ap$RY%)!Fhgz(zS{Zs0Qcx17fQQnQDPf z=mxPh)P+8Q65c-$M@#6rHt3{o5L<`K3zV=Jz%3p;Ys#w7d zTvM(N(1EL5;KIh5%N-OXJm3P-h6{R9H>l`z;Mxt6;RDOKaJhieDL*4f#)Hclbke2( zSjLA-6XY^MaLF0K1*)KVM8G9%2-hbG28MbbQAUu5OSnLFJ&zdJaTQ#k%AQ9Y%&Fqi z0fmJGBk1Pf8d(m|0mPDwciBKEb<1Xfjv|#}1kLBM^UHdJPOO&!>*C^&88}!#X@m_F`BI?qDNv@CXJBOm9Sdu~2)e0&wF2ZqM@G=7Ehp&s z?j@iW@KsQnUIGde&=8)1Jox->P#R<5ik&{QugbXI15_@oV+5%ddg9r}2+AA`T$eymupP`1-~w%f<=Fw|C~)P1 zJiZIeG2nU#a@B4yN5BC*RLZj#+#n9%x;{O+ze-XAG!n~m02~%E;E_t6gJ4c9moq4i z4uLswT&2_J^jAsNgU&4AIR^42Lka`y9gr`NGadjrvw`O%ql6{{16LO)>7N3pI|i-- z(BZA8!CfvkF3?44JZHchcJTNk&snfC4ldBuNjw+9R`GE?1C=h9z#M)qK2RKA0V@;W zQmkiTVBon4mJ;IvjV1EjWdsdCi*s!Qh1flCKuIvLUIJPBfU!q|fq~T(6xpxAdSom> zXL`$PGca(~f%4NQMi85U3)Jc4`OK&a>WOoSf$aFg2x^^iaLoZ_h_7J(@^EoUfXmHO9@;`zKaO)`MoXc+8nVh2;Y9TT=U`C- zoxl#tF`%QWp@lf>cTg!7!(^bzz`z;Glg>0B6nUTtL7q&e1E6h2T(zJio~;CSkt3Hm z$V)k3qn)^pfD%P66X@tsXRiL~Cni-X*1LlSPIiIxRDxA;g3jgE)L~%Y>H)PPW-@`; z3|v;A#>*@w&|sw;*9VX}v%%q{!4&{X-*dqnEv{Xls&*cjqr)W$GGIQKqX!<7;91DD zS{rnfY)nQ;@)dWS}5wN@r_^j?zpvGP@D};Km|*0~Ch;nQrMbFnF-Yc7o2Q zW?_Dy&%ofrA{z`kb()p=gFfi2Zdq1C@LAoUdhQR4>_t#FU7d9@1Y ztZvy_Pz5B!3~EnSu*vFyaLtJ(z zNTWHJcSl^79TZL$VBQ09S;OhkQ>!%V=Y!m2!whN?JQtU}0g5+UFz4`6n(bTMtSIUSQX=NXUXNL+9}Z2Z@S=>=97S-~-mECL!AfYLfdh%NT$T z`IeOhr4B!49S~1Sb~Z?*KQpLwe4#8W0xFvVm_e&B-YCl|fLa1UU<*Ge%LaiQ6U+=M z-o7czJ`e?!kfC5Jek#j?hU|F4z`S3|vY@3RJmFy8Z)MpYQ2a!I!{U#!>?%-o7zyV6 zRhHcjDkh_tL0u{a71@QLA}bm!$D<-E0!m~tU>>iEtOKZ>91B({pd!15i=iHL$hVUL z_>gZlP}}?#Xzmx1&p22LKv!XdavmuCLW>x-e9*bppcN(%RcrzV3=AL)mIoD2QlQlk zETB?}4OCKr!U!zK&cFr|1ceKf&%si!0lFj?)F%S1?E?$5FtBa}6@N+0?K%t$OcoLh z47^rO3=9l{A9-E63>X-MB0-}Lt{^6Za8X_g1Fu`00RzJa1~w2i3+A-<3`{e?Q$(2t z3=Dz^eDY^N`)ey0_!K}42H{EuKE*R2uPX>wG4LsY1RWUIN|_iK?!b&-XJE1hUB#%p z6lBB`K2-zIzSTqqK6Q|42H_+IK8-We9cNUDCV>Q8gg_VW@)?5IDZ=gyd?p~1S{Rs$ zr5G6a%$^%CFerj<`en>z1}#7<1D~F$Y{bBzv;lP1crG(&K#Va+xqyK&ml-4uQl$bK zBxcNKcAdUsMwJGCTLlAyI;f18Si!(>!Em~uzmeEjJ<14y2I z`o@`6V$G(js)=S=sXStaW_19YxQFlcZcv>Skdan5$QD}p&7uF(3c$G`yE zYzjF>Rt+>a2sRwFP8MYN9FXBg^>ZpfopsPDrW%aVjQ$#oF^r%^k)S9A=>|usD1$c0 z0>%A03=E7XKr1R4{J@@{X$j z#hjYS^o{-+qSK>hR|zwMBSp+c2fUrV6P#B;F~1pX*E>@N23>Ia=me*aeGCi?x@$p4 z6Lx~r$bAL|2EB&q2WD3(==?K<1&v+;Xd+|=*eu2%g#EB^`erg+aZ8o17N|P|3M_F` zNMKD2&|r*aE_x3RkrD<5b}6R%f^O<%C6N_@Kh+$y#dkmJC?s?4Ab@|5B-P_X_32dfv@tDrrR zkgV_zDOmr3gEf{BmKqqCp{W7kE70m{Q0!MvFZ4AMo4$T-m9XgE3I>LLGmx)9kU=Y=N|+6lDzBSQU$C}H#6=TyP`$Mw*chfF22c{7=)l0B=n6W=5Hw4{ zz|aJCx~e72=@KlEETs1ww4Pdu<<9ij`BmadpnPm<2}>A=K!Z8H!D9NsO;x&_pjjGF z^e&u!W`30n>(vSdhJ(}J&aaXN$MoarybG#i!A!2{`U|R*&@#Rca>fT)2aalS25pf0 z3?e}36_oK9K(l&`b4o247z_&-7=1v4ql`gD`4S8aj6NVy#$dyo)I0`8A5bHSF@%AG zrP`8#K^w#~cnC5j36wQh89;l4=j?_WlZ0$c60$K#AdQS6494}KqXAn$%?yzK6wu19 zIVLs?3?|^>wFP8AEh7Vi>3`4x94#PSpzCQ&jX}rDw1Q+Gfn@KoGcYi=f@Jv=nHU(1 ze8dy%uImAD z8O&1!85kIQLF^D_1_rHi1_lNf8(2hHfigO1|KPmoXBSqkTUg28+zB zYzD?9pj`-iL5bK(gAud_fq~>yi}~@&ZUw4YUagoLWJ1?4UGfY7NT!IwEQ@u==79 zlwT_t7)q@n>3G4SDjDSm6$}iW){q3q;lQ9a0j7E>RP{-y>Mx6`Wb9s7FfhD;ss@#{ z(ToP50++*qL0yWGf#FL90|S!{$gpTe2Mxv;PzW)ot1&V#{I6hOP@e9$xJo9Cs}iID zbms&E1Gppxg$6hs2{34bBFn%XlmhO6V(<_+@fX-KFc^Ug$2*X;Z&JX(c;}`l1H*e} z1_q0g5(dV5pzsx7VPG%=$Mk*I=@%APsmpRYjTu z_Z~5Ff=?Jf19tvjJ6PW3WQ4e17c@J}$jJzr6$5Q?&;ytByx?W}OcNdSz$FnMBeWy} zCmE0-xO^gJ2X^vwwJlZZB5JO%7>t0%psyVyz8jZT34^nC?(~^UtE4qS^;{68wO0E!V3}#D?xdt87UN2 zJHSGr85#;o;8190oHo61S(PY9ml6X5V+Z5v>3z$p^cBHD&;t#E2t;8FI%gdedk3Z` zh8c-X|FWz~SW2{#f#Iq>I1C_VG3aD83 zp3;b7g_a|+j?i*MfB_ytn&9*esg@HKRf&V9o0Qp24lX0k-xS+}ay( zYp35@Q6&$lKPS5^tLT2?YJ%$ z#dQl@0NrwfWxYbA7FQvY^7M&os?;Fuo>C@gX#-D4aBu7aTP!;L-I^+4Yf$`Ob%lBZ z)L?<+IM9~Iz)A*&4-hGkAjpfwEDY+Q3=9mQ%qTP6W^I)^AGneNZOjAtDR_F}+A2*} zP^nTheg4`iDTp+5!SQ$Vb+y;>X z34%SyfbifW_vyB4VZ{y1hmsx;vwhb?n|>A^;L?*#6SNUfWqQN6LSSW}R1b=0Rxhwtkg|0Q3=Gje z3=9$oAyBmo+R&|y5W300z~E`az+ev%s%I)@CuFC^; zQ?elvAZr*I85n-~GBDIbguwa*86hs53=?BvPy;oCTKpLp)ODbe8;~STK||c2i?M{= z7@?i`3`R&Np1~WEPE^eHB3Lq7?F|ansOiTxRq4pbRx&Ugf(Ss= zGpK>?-(m(8R@(18rVDPa5-|aVJfzO$XJI^6H?=qd*M_1z)gpKpC7t9pqO~+2u1m zXA7+CDuC8lJs{mi;O^XNUvQq5QwOC_P?vN+*pO(Zi7pK43!v%v{&eoGRnqkrAwddl zZWu5?2Tec=XBi)ZJqx;IhjC86Kdc6O4EF44PDo~b%nZt`=3ER6df+Vh6g+mw7y|Zf zy+1qyO2g_D6R3M9`GGt(ed*RJ6L2eV?eu$FtHkO-QE&t-6$J?=2DK{CR%lNK26fOa zMxYGx0wT{`)XoSl^jH|w=Q1!bfVBRHNWru&gJ}ibj0MuF><_Xvin*vCuJt5Ts})E} zh7oSxas}ds>HHD-F8qlSHu9#2q0gwgT^Hl8MHycq<9u|D}W=oWP{`c zsQ_5uIfBcw#az%5N-F>!Kp3h2r$4AeUM2NpKE9lq#URgg~w{2?AGu^=kSI3=El-3=HZv3=9mVpyquL*s<{ZrUn|5Yy_!@ zV_;zDtz=-Rf~f$t%9x90u`;NGF4+SWZIfYApq37!0fQRoYAkRI29(o57N3HsU^LWV zjAmt?zSm!abNc&WBfffd(6wlw9P$vN0+y6O{R(jT2I(iYfyQXpfV&0Y4YYH<2g5>V z4LEdM;i0nzC3H4`Lnn=!0jW6vD`T^R8K!UY*ASULe^-^TGsur^!O&1Z_z~1p0M(N7 zVNx(Zg6;tW`w`TQ0{QV;Fr>)l+Fd1_1oF~bh!&WaYM~jI!8Q#v^t%Pz^aL5tIHx`Y zR%CBMY1wRnwrmhF33Gcw2*k1}yQ_rjK`mEE)&~z*-Ukg>G8gS&Wni!c-RjJ^7MvU) zc}_VL7I1691!fC8;MPJbBXAo9qzvM4gx#?Ek0}%!O3=t;V3>X$R2zeQED4c;Xhg0E z!AZOb)O9@ucFQhs67L9udHWdHEsQ~s2Hi23OF*MQAVm-Z5iWrh)+-_Qfm||um%j$j z^ecO+WFY;4G-!GLG87U}B73W3TtUSpcNp09%tik}G09wXf*I6VO=; z3Q*$(G0+1lvO%#N9|oCb=-yi;T|cvufuRVZn$eg+6I7ZnMepK*2mNe+fO>ycETC2h zXhx24&Vz86->qOnm7rzUj5aKwc@pM{4Rv}?K?8v>{)0L_&|+^!TNcn_Z>EV3T7N;S z={|&G7DlkaO#N_BZr9}kr7@7t1Hz}DonIx+=?krDi>A-n2OY+oHGSW{DrM+6=d*oP zN{lO}bMCK_QwEt2E~f+;v_Vd`6$4%7bO`Jb$fbd8)4ldrc`&k1pS-`yQv@`?+7=0O zlRaoS>Cp5K`>SLbA57;vP$kRsFJijxfhrjdnMhd2@*@kVW68$Lz`&pe8sh_JDsYFo zf`K7sdf|a8BgT!>mmH{4RR)cF*}eufc;dk>@B=r{+oEAfI-X_1^fw2pB*5dm)1qO{ zKqMSk5*CO81r74BAFRFN9tBA+)d#DD*}jG|FqB12-*~)AYWli^Rs7O>D;XHNqo4`s zJ|lzr9tH*mkgBaXp9}B2=@{AW+V^qiD4k!H>uwNMsr=QqV zrHV94ng`8ZX)%!Cnspc&TvKAE-v$NO*~3+Q;NV&bF@m}1JtJgb0_6KkU{#XS`Hxg_ zfrEo#y4(?1S02=_00oD6?DWDzRVsX}&|ZM11R_l49jOxG1-Tp?CbA6L+0*wQsgh)z zHvQ(2Dl1WT&~%D1co%elN^WsF1EVSHwCNg0t4vZr2az&bg11h8<%0&nvUpe!Sb=8r zK!X=yaj^91$O=lI9H2u~tw7TkAlVYQtP@yP8Y~MMmjI10Pnv$v)waMEP21f_a|+3IMU`DkrLh80SnkKT#zomINvsh1g&d5};lm;CPh;FP=4p#H$S3wPXec=7|&PRf|$f7#L;2#(=g_txr|SYG^0J3=RQny$v#04K!*7 zE*M}{SoZXWQ&mQ+ptLY^`u0<>?5_w*>UuU{-#$x*j**%`W&=R}0;dBF25pd>vl6Ir zoelOpsFDHocNym#nI3YwN>4NaG`CU&-aQHmC~&|WnLhn=RUqT;=`T-L$ui!Y&VHs! z*5`W)%*}JbZU&#xsSa{DsQ!>j1s4V&Bf!l#kUgNG00#y&(9xq{Z-M%Upfntn3P}~9 z0UnUw+NUo&Q>6h(({n*d0aUc793&)El+2f7zXxj zPzEd+sDXOUV5fpc+(1sfGyUV)DkII`$qWqN(!f51w1Pn+XKJ8z0$|mk8;?P%&C($S zUgEhb8CIc028P<{P3NkdAc-7w9tud&UZ|oMFh#7>InP%)L%c5wi(0YiIp?cnH9&3y zMcBpJl{G!`LX{(9?)2Fgs$?0vr|$$&E2m$-P$g@7JQEhr+U%f2KO0oVdi>+e=4bQNNF)%>JFV?Yv3NUps1_r$& zpzW9&*baiuoto&NlE}cgfeoaQX`-`A5`yCe4v85#@VJL}Wu$1_qbu-j}N!AZY=#Kmr^bV$)Y&t`e#5$bn{aHb^!HxgDG~p8f%KbZ$B?oWcl3pUzw5*%8fYuX^8bs8L6pz#_|aGeGR7xTo;^`P*A z@pduS>n)$|c%@3!60)oy1Tx2Vo((eU9Rm(ekd2VK12I;l2g=f*InrEEa2hK7tYlyS z&B1HlCyqPENs)wlpjdFqlN`AWP)hb6w&YB6e zAS@4({kpDJ3G0KZrm{S+erT5EfXqaOFsL1Y4eWr%zCn3%EmY^jt5w31Af50^4LX1r z!@!{3Hl6ocm83{*0Rw|_IRoQIc2L8q9h3xHrdwUBl4S+8Z)>N=T&vO$0cSxj4p0_^ z?bjBN1N{l(vRc=&iiGtP|Gv>2T1f8=taeKWzs8J*} zJ^4nJlB*Eta)5rY6w^d^dr(HmE`<4WBDlP`0&4ZEb%PGwt72eKI{|IJslNpkd=(4~ zhYBHac>hL~7OOxN1H;|vd^fAaAUPtCiGcx{BYN*uNr-regLfOJ-@RES4W3QAJpJ#@Dp^Qk0+lqNB*9e-afscm zDq)Ds38+bqP?^$ORl>?LRSXQF#gJrHtjeJF0+zJ?LRC)%s}`I7;ZBt}C+JS;b9oF5 zyQV+9Riywi)(YzLUtooz(^YR*$*_VH$xnB?U8Ml=c_~N{C^q$`8_ca@<;^L9mIay& z+A-5N+^&-JOfHATp&x2UXMb)px7pAmOPB3Mx=af+~7@w@QW$6rRt@rt{x}sY-&XQY!~f&GW0Z zKvSaTOppvHsKuuD-m8-I1?3Uj3!prq4;sjW4p07rhqgX=cyzuLw7bApfmx%#8u)k1 zL4gGskNi>&4k$=ri8LGn9v%f50xsI67_>n)xt;`Vnm@s$Rsp|nTU(uxfx-2ZEcm`{ zJCHc2eZ;^37H7+oVPFWZfTj^n2DfXV)ljx^6$}j8&J|`14DPo;Cpkqif_4+TJAn4d zI4mU{4jj;*rS{AEfH0r6CoAX}4baIH-rgM&3=AOb$pzZw%)-FH8|?W{k%8f# z;&hJ(RWh;<1sNDXn5%`+>opSt0|;}iVD!pRWnjpd-uR$OIP$U@0|N+i-DdPUE6BhA z!u(H}yz)dC7(ke-mCgt;0S zy><#PFzlTE_Cb}lsVL}V70~waCyZVW5)2F=%=L`XE0LRl0ff1pGkU2AFff2H*HcDM z&_2b}(|sRS$#KuqW?%qeb|>EH3+wduOt;)!>9@V%QB}4N_)hWZF+PTT)91`C^_jlr zvZ=)MH9m&C+o$VShp`~tGp=b;UF$jh5a^z9GsN}cg$>mrpzFm2dnzQDO)L$-7mzcV zn1k;dXErf20Shpjm_THhjV;Z=BGaO4C7CUaO{ORMNeDAr8XH4yBsVrRm@cTBCc$J0 zrOnO3d`5H7#pNQ*MkdB!{`3#E)sjqx7SloYGaDL#O_!LyrM_AmtdPmTV){j}$wtOt z0Y-!A1?u&pOa|tl<7*|EEMZ=-n0~OfT7t>Q4C)di)9H##Wx~vsMh0LLm@EyaGe*}+ zFj`Ju$WkT>a+m^BnFx!efr%05^7P}=&oeU0Pmhb17ubHQu{vLn$(UifVScrkAnKjz zh8C97izZi_G8#>{Pps0MesOZO7L%Fj^!Of@nvN9JK(%Wh$b zByV7WtlGd5APyu14}0sD_&XDI0Giv0qHL6t1!M)Z$=ZV1!EB zBe8vu*ilIAG$i&!B=)@NdxdMn4R<059YtbaL}EWfVt<~_DpKPv=>+Q4L0u7!#7>!> zDpI2?*@Gms5Q)8R`a+Q!amkZNLido^ucu!WsZp*M2F-Cp4c9}!oLVf9JG%PCf1Lt;lGu``j_p!2Wbp^GFw4T-%7iM0;Hb=q?y$6v1 zXS-KO?C(fyX3&lH(7@9~VtXO63y|3DNbJc-?D^oUxuFJaL6SH){i#HawInmB?E{qt zZQ_TyQFXedWR0?&61xY9Jp+mT8HvpSy4N0Rjsg-}2Z+r@Knm zcpH9zaTypG{vfeAKz&}QvF1o@m+1$kYsBm0k%Y35*b|Z1bCB38kl0(0*awi~GUGWow%2L5CE>j9mm8VuhNt4vBpZiTxCb{Thk=5sCdB ziTxLe%?ujRg__R^VMD?WIpZUHM;f9C9Hxp$Y;`2IE)v@qiEW9*wnt*SBC);2kuz@ZNE|3)N`WQ+4BNF>R5}Ow^&kGF%X(YBL z5*xhA1FFUqNjz8@DG?_kN#rB3YmwMnkl2Ti*cXu4_mJ3ckl4SF*c{*;cMPDNNem2P zFb-%FBNE#PiS2;I_CsPPBeC<5*h`Vv8V!J}wptUXxK~N4T|HUG)GmzNDNbEW!_9P_s{OPP} zHOi7_k%S&0vENU3RI5=|6<0u%ILb(DOC+}2^iH)J>-r8PA<&@%u+Uk8B)$oWeE^Al z4vBpSiTw(R{R4>&IxrSyzK9~&iIBvh1mS=Jhrs}eZHL76L1ITCu``g^Wk~E6B=%M$ z_CX}}Q^jDgE5H_iM3VT6#O4GI%0lB^6p5{f#MVV(TTK_$sM%kysEjb$6p8JK#P&sE zMaGEDPMhy>WLN0HbUk=S>U*e{XTUy<01 zp!Gb^@Zd#agSQ<(#nn}&U(&3Jt6zg8zaNQx8i@_Meg@{o*GS^uk=V?jB_>d_`H|St zNNf!xwlRba2?Tct2kh}+Bz8O!I~$2zj>K+8V)rAlXCtv!AhEY1u@9+E*VC@qRNtnC zNC{Jr*o%ePty z79a`LPM@k%qb#`eg6GHiA|QLv5Od#9ll-SGOix zRT8uU0xGSF#I{CadrbeUTl1SYO$!k|#nV~!YqF=;=-2QVGJ`I;f*K)+#I`|V2O_cK zrmxknu~uDxB(w&JeGrL#ZaS|)O>n&xXca8f27e@W3=+EliCu%l2Az}wOSWr}#CIXF zPav_cA+eu8*pTG;3Bm!#3p>jQN;U=thISE4b^)KiTwe@2A^5Lz`*bm$^rSG$%ui0 z5o#z0hz-@O1!6;8Z3tq6r)U`%OpO>AgrRH)kT_J09}+tP#0KqYW?*251+k&((~Ll8 zCO|ngAPK0&tw`)XB=&R=8*0#85F4uZEQk%Y_zH;44e|;D!wrz*pzOyWaj2SKAT~JE z>lqmMjFIvshz*(_XJBBE1+k%;)sWaWAU4#Yu1IV@Bz8E64K*hg#Dmja1H zJ!uGHLqo+C#D=Q(Lt>|Z*igH2A#6x!l|eY5m|>^^v7wqLAhFkg*ig$hgV>kl5Ww z?1dmU)XY^#?9DJX$p1S*9H^l;kl61*Y^ZO(f!LsxTnr2hzs%t`nuG5ggca?=7KkWQ zMq(Qwv28%?E^t6II9h;eOQ@kwBv7u^eL2S^X zTLuP(CJ-Cy<2EY>24NWn2GF55GeP20AmeBZ^FbV_qQy`}pyiF*K;lpf_JG(>H3y(- zelajGTn33l)!YQJp=$0z)qwV(d;p0<)qDf7p=$nHfoe-AN7Nco&dVXO)sff+AU4!z zW*|0HuRRhw6vT!m-Z&(7Iug48#0Hy_%)n3v;y?}RLSj!wVy^_Tp@wckV(&&`9|5t! zhB7dm0Z8!EmV#BPUHO9wz4s0AmH*!MwfsQ+Fdu|FcQe}UNTkfMVD zbniXX962Pm4H7#PiCtz3DrliDss%}aR`xS6Ff`gSFbG50Js@$YnpsHfr64xcXRAPL zsG6Nf>=Q`rOCUDr%rOQAhU*|U$b3*i`vAsaU|{$LVncoWABoLjhe(EkAU4z>aS$71 z5Ca2)0utK{#DBe7kO*y$iPG?43aKpd!sY9w|S zhz&J#G7@_whz)i0CM5Q5B=$iN8>;sj5*u`A3L{jU3v^w*5;UzUfH+V?HIdjxNNfub z8>%@RiCu=oo`%HU17brxb{ND~hNS1?4h#&!Q1&GUq_lb$qzD=;k3ejw<_}10c1H#V zMyMJd5F4sS48(4PSRf5zLoHB2Vw-{3P*2*!*r2rP0pl<*Fa(0wP=k^|Y^ViUAU5b+ zJ_ZJcJVyowVJN#2Bo0;60%AiQ*9l@n#it{&*MZnjHJcqljRL4adq5IU_Bjw6>eA~- z><38f=O8xJf_EUc8pQXXK#qg5|ANG!YB-z_At#Pt*E48>I8a3vNNjfy8){Gh5<3mV zhB_`EiCuxjt^={5dgmdrmm{(Fg4nE}@MmCPI0oiGd~hC#eHFxp8uT5BE#}O?zz7vL zMPi2_u?s+KsK?4dY;}nF)y@nI!ccZwJxBtoXd;LWjhh8X>~%=&%^)^Z{UIdwMG$)$ z#Db?FHq@NgAU4#p_fU&LdyJV~AkhK#KWO6}BUBNu3&eGx^O+Q(ia^GygV<0t+E6v1 zQ=05S;!w+6L2RfRKO}Yvhz*UhTqJgx3qvxzzg`29fNGwD#9oTT-VI_y4LX9vK8wV@ z3}QpgxdUcT-*!<)tDei1fdS@8RS+8*iaH=RXz4Wr1A~Dp1A{P>Z4DBKstE$Ip`J_w zv7zFnNbD968>+V#iM<%aW@VTj&14{3zZ=AXD!PWm{)ohubz@*)gsM?PV%vb&P|v#} zvHg(PAs{wXZ!r?P2Ev{meOX7gehG*JHE0!x4b^Z2iG3TyhWhdmhz;5i&cML%%#DEo zbnH4PNqhu}L)H98Vsp7e(iTXK4u}m^V+~=0lN^H=hyyh=7>S(;VnZEQgv72!VmE@= zP`z`I*xQlVkCE7Kkl0Kfpdue?0k;RD1t5aNmIAS%7FZ&&13+x3Z^A)rZIB-s7@|EG z7=)qhG>|w{O$ida3C0HbzX!zWg=n4#Vna30LSkE!p>|av*!2t(Kpd#gW+Jf{A+cA3*ieIZfY?xj&LFYxBe6dtvDv&B z7#N}IC6U-VU^XcH85kHGz#K>vL?W?skk}1K>?ug>xk&7dNbFrm?88Xxn;P*(M^zqIm8inLB4^qUx37+YCeP5P~WilFfcGe)$k&*l|gK%Lv@hYrbujS5F4zw zo`Jy!#DTgl2*d_UFfhb`*ieg;L2OHi3U8^ne>bUug;RkIF> zy%)rWjhY?@ae5#YoB^?+7F4-MYcND^B?Y|sXE z1_p**AU0I$)PULG@{fUG5{Lu! z&1@w05+wFo5F2XHW)K@{&=C+D8cnA_Y^eB45F6^C4@*O&8It}OazGrYLA4+@ z)Hlr_HdK5Ohz)hnN)Q`#{1XEM!`eUw24N_B2S^;M<}ip2jhYi6HdOo?68m8wsQia2 zdWIzN0mN>C`0^`=4YlAO5?dq)(Oi>7Vyhvs^+9Z?Ii?^s)EqlFyPkm|9L`~2NI+s& zBeAC-vF9SOH-p&Fpx%STK8nOX4Prwrz5`-IL-!Gg4eIiN{P_{Yfd1B5BM=+v($`4rFG%daAU4Pl zP^g45Ffc;R5dpEGAu0u8L&Y^gY^Z|_LP6y}=&()Da*a?124N`M9!Zfe5<41+oeE-u zPB>#=V8{Zop?Zsv*qtCY)B}@{*s~FAd4?q*4%DDkAU4#X&0zNQq{lj1^-n--sG3(G zHdGBy7y|<%l&yfo)I^vAPi+M0f|G^Y(iomLSkP+Vn0M;zXq{Ehk7tDFnj>9p=SOJ10_-@hd&%q>PaB6 z6_MClAU4z>0}vakHxP+kjKrRe#6E;>= zhz+&=IMgYi`!8;T#Gz^)g4n(c!Qd!*3RMI;!|x|Z0;=dghz&J}ITGS0(3%YKNQ9qc zL2RfRH86Ynyk|Oc^?o2WG+Bj%*ic8ug4j^?Js>vJW0OH_f3R~Hri1K)vKN8Gp=#EG z*ig4^05?V-Qg(fy7osVrzleP;(4oKm|P1AWM)0l1GP*OiEV_$wg9oAnjMkY!5}tNZwwMU6^Y#lVnai* z2gC*)nFQ+g#4<1lhl0YNfq`KONCFxKn~>ONkk}VNY^Xthk=UYfh~hvB#D=O-1+k%K zYJu2LaT5?5bWj-s1A}Efhy!(zZ5+r&44}LI7y?1!P|e{WHdIYCR1K){kq;7wswoAr zp=v6jYCz`$_JYKrY9@o&P&Lz`YU)8Zp{)i)!U=Rj#7#I$LB%q2eAhGWuv0s4Ll_1Rw3~xbfsNRoI zb3i8?{sM_Z&EZU7U|@u*QAJ|wf!Os>2^SCt>H}XSb{G;n9>j)PoC;z?_4XsNcOtP5 zA+c|O*iiEyBC+dVA#px{*ib`-6A|rZIS@M%;$x*m1_og$+YBTQO*hscHq^&%AU0Io z8^nf+hk@8o@l*&KlK)B|9Iy?|NbG4KHdOOo5F4ub5Qq&Ge}u&5NH(#sdWdgqKx3pJ38)1&AU0HyLlQ&{=;odfkT_IL6o?H~69-k316pDW z5{Ig(0I{KJYM^RBt0gCZ#6fC6{+|ZoKo!k`Dgw!^1Brte3=9lgKy0X*9Z)r^7#JAN zfW)C{E`iukHP@hOK@P91sU;&@3eOVkGuf5F2XfJ|y;W zB=!Xm8)7KK9}pWF_v|SQ42+CJFbACe7_5=l4j?wv zpa3Lx6o?HvI1aSu5X6S6nF(S;Luej|4Yh0$)MC&;);5qhRL!1x5C^L008|m^e6cGa zaj2qOAU0IZJ*XN`+yDoAWA5F55E+8N3LY4Jf~ zhl1EpUq*x2P=h*<*b|Z1i$QE?G_65mZ$)D71F@lIo=OFk|Inbj3X+HeIe~%UW-0@N zFqHikBo6iEA0)O$8lr#-LSiQ(u?vvc^+@bKIJ=&KVFri;I{KS|fnhF)4Yha~5_=Db z4fWYkB=$KZ_H_^&YR+8{8*0vXBsN1j0|O&eTnxm9t?7{maiA7xAh8WWY^b5;AU0HU z9TK}8i9Hv@hMKbsiM<|)y#vICnpwXO#DN;hmVs~`KN4FJ#D*HGg~T>SV%vb&P(vd? zY-qG5gV+g>Xid*xU=W6~t3l#ZpaVQz5Dr+?OeFSlB=#B*8*1ow5F45%jv=w%BeB1L z*iiL?nTWI^4Pt|CtpKgq$^^Clp^Cgg5>P_}Ky0W>Loy+*2F*%kfW)C{@<42;nj)wg zP|vOnBo0;617btfOn|BZ9pJwNBo0yoDt}giI8a6Fpo%~ZoKh7%w*RLvQv z8qlJ`2Ox2%nr9$3RLv`>8qhJS|3KnUH7r>S42)1U99f|9KY@V(bcdV_NCK)z3B-mf zQpUV&6t$KLN2JhBABrv7yoW9mEFTT*<)j8{`=%n=KoZCP3j2npFaEpgt1=v7wq3 zL2RhF8i)-Q_eWw!g4m#gdl?uQ;y`Su1?foaS`ZuRfi@&|zX}p(28azcXdZ|SHE7fH zz3Daj^{zP#42)1AKO}Ynhz&J66Nz1f#GVIYL*2d<#0Dio&=^V%1A{P>y#*u=RdWc5 zeHO%q<|$^xXYc~Cp%w=tu`@wzsAr0h*wwk9 zU8zus7LWwgpe_&_YS7Z@yqPuP^|z3O6!I7t7@^XdNNjr$8)}>f5<3uy9S&kc^_C;C z8<5!3Ky0Wv^C4_Vl3D@bfPK3T#D*Gl9>j(Q&MgodH0s2_z;G{*fk7C`{sa<-rn>JS zHdH-RJ|d6>kl3OiHdKv#KB!2`2iwb_3zC2u704JgM8Ng@Wsh8miR#Lh!vmxI_)Lz_Wt zXsGmo*q~d385kHQ6)-ReL)mjd;!rg!Kx~M|>KWF8I8cclAT~sTVK0ac6+er_zKg_u z4q}5Yg=Ju1cmrZX)w35O;+_Y@hKkF8*w9f>RSOq3Ux$Y^X0wk=S)e>?t5NG(_hjv6s~&an^&_P~RK|v7v_ELt;NiV*doOp@xD^ zv4*XE;VweNy$Fa6HB%bIhMK7YWrO{11>!&razMFbG50Js@$Yn&}`mG)F8)Vy^+Qp=!2+*ibclK|^A{vGb15RPbAZ@T_2M8lG`nhp*igNOAU4zkR;8fwAIb>; zNkD@r5{aFJ#Lfn>p^hsAv7vffk=T7m>?I&J)XcR=>}@bMDF5vTaiE4C1+k%q-b7+Q zLSp{_v7v@CmLcMv3yCcZVnfZ81hJuJDj~5g%0T5m)F4NY1eEQC#100rp#~*@*ieJY zL2Rh{W)K@H-h;$m1Y$$gtVUvQL9pu?_JTN23l4+WP=juP*ig;SL2Rh_2P8IIIl}k+ zNNfotwjziPHD4XXhMHplW`n|?fq}sZ#DQAojl>Q?V#k8mP=hi-Y-mC&0I@-1Squye zCFKkZ!ccZSNF1uB3&e&dzO zLt;;=1QoE*#6Am2VjdEE84`OH5_=O8dm9pa9}@cz68jVq`y7l7^8Ym$2UMjXu^%C^ zpCPf|A+bLpv40`4{~@v2st_rF3yCdQ#lT<*+gU7%Bq58$RzzZJBC&P1pDe4nU&(l4 z`pOSA{){Hme}brv>7E~J{Fz>qPoMR%#*fip`b!Y^M#XfiPc?pwI@3Ep)%Y{+nSK*Q z`ApaRT;tCuF})H*wM;(=qFkm+eyQr0IvqsjE0Uuygr3#M~^1uKmNQ7fje z1W_f^e}X81>7L(e{25cG&je9hroRMH3ezpW*Z4CwOz#9yCev?%D4yw>KWh9LE2dZe zsPSid(lY(jj~YM5fa#JyYy25yre}hv9n*J$D2C~rziRv$bEZdvD4ppmLDYunKS31B zbkE;l$IJv#9MfNds3p@a|J3+1I!x~bQ9GvJ1W_K-HUHN5GwMvQ1W`+-p9E1p(m3J!}0LHKxw2^=Di&^<}L;qsMeh##(>I z1JgS}l*#m)AnM3;O{Q9ZrVlfxS25MjV|p-ax)gJ*AEU+eOy*jUTXupdj_I5%wV)u3 zWU2LMy0dWlDwbM5Mw{tBL842hd$QJo{5cauIZS^EqFSa~veo)Ca!l_8Q7+SOveo)C zU0E|-i@ny5v158Ad#yjC!Ss_LYRPm-j#_`l71J|8RLu09AWC35Cuglcw|O{a&7)he^@dCJI;F})VV z{JD#P!E?Ic2Y%t{JH%=QSe^DWFdUff_=#V5`UA0A0Y;VSAH{0bS($DzFszvValeqr z^vWw%{7hG>r#p$)s*{o!e2;prDZ z!UoeHf`om4GB7Ak=ar~cX3U#zC{e4Adg!D9MB3r6AT1roIatPiyq85*WP?BEif zK0~5bfH7nGN{L!^#>D9tLDY)rKS5OBbVbQpbw-xyo*=4adZA>k7Mr1wshOq0^om$GGS(OW6S9ef7%E$n}aS3U?~%3F*h~? zpRxaRx*sc}z;wIa1xDNF#MG8CgO2x~=TR#*T`QrMi`m%Ha=N}pt>pB8gj#MU3ybNo z3AI{`M$yS=BR`F*~PbaEU5i0$+%^E%dXn`nMg7c z+Z99V9E};5OiymFGpJv~x|M-}fmepzn(Yl60|S3fNj3w!4cm6m)vkPxxEL7NZP}_B z85jik$~hSr*zMRrm*PqAIrA_uu-mhN^h)trN-;37JAgUT3|y)r3=Hg!Yzx^K7WZ1X-G0Ku)BfnsAqu~Wto8$I7J``M59SCnaQU+_Ft7)(nX-f35zMw1?v42*UjqD6uCxsXo*dy5LK}LzQN3s0^IV!U#n}IzVtb~DY5<3F} zdkouoa7cY)WME*AWs78FU=U>B3J_;tV2@)v$?}hOl91IK+ETHjF z_AT2ZI_uWYVKTFvevzq6n9*|jLFO{i=^kqJlHltem@UoBra!E&76IMO08+thX=VZy zFah5T!DMMR{Xu=TD3h5X*a&7zGb8Zj6(9k{>CzHRW(H6RQ;X>f)$2u=Od$5tk{eVRu7VgY7TOOxsOf9iCmuduA=VX|bH zepbb6*$y#cd<1;g|O3iXQ9_gd8p zFd9rhXH{>*WN0~^$GTpd*}{Thx~^iq^z=~cdNn3v%jvb&^$v`N)6ajcli)>MWnp4y zG5xW1y&toQrTO&dRdw>ygKg@a7>%Y+v#D29Ft$X#yTQ~9bX@}c@&t1;hUo&D^`g_? z*wpLQ8=zmcU}gxq=>ewN4CT5BGw^j2a5)p?t0>G&K_qaGHy8%XEdM z4egBT+gB`YP+(&W+;Z0G&nz|AgnM3{jAd~GHJ3nS<{ zBAyM?wf;4zC<%%&FfcQ+JrZSLVDS=UU|=Y(-E%fn^s+u}&%j0|Sd7D+2?wE~q=m(jmgYz#;*<9EpPk zWGAbOGzTLC11AsYaz@T2p!*6qk8v|FFfl;n*`zE%(jP&mKXI~yr3Kg+7??O+L2l!0 z=3-!A;hZ$x=YNB&{BzJb+??W~An8RQ+Zk9^b2Bio*|{(>Ft9XE@A%)K!^;Rd)t|Ev zWCds6^n?E!WR2#7&cfk*0J@%#vy%m+8+7F?Gv^+VTRAWCF)*-l#_=#PuyKZfN*M;0 z=&1sYVire0cVlqIaDX((@-Q$kbMEH{xkeilT%4feve`IqF)=W(b8h2fVBp~V#>T+F z$@!CGYFwjOy%{G1gAga^!axyDHf9C}QO?&q3=CqNXL%SH#5qCd%}a2`@i8z+a)Rz{ zkm9uEWnhrzJS4=xAj5f+gMmSolR=z;;XgE#*dxv}F)(m023;o4S;fl0z{qI?_TesZ zkh|JAK}m$=s3@pJUBbk`z)=qleD=iuAZ=UN%phHPptQ!oGL?^kfxU7M zAaNDm37~3r$|lfVZW;{Cj7(k}pscV7l*k#TS1~opa72O9s&0KEUXL+yf;A6bD#y3mwAP!zh!C^ms$g=y$*w% z!NaQqa`p)jn~#BI$8ur+^AgN&jWI=3dj$fd0Zex&0s|qJm3`c4&=o5 z3t1T$_~ls`7+BbUd;qyT3lv&EK^c{Sfj<;f;IRMW1hquK68|9*0#0lo9W0D0Yzz#7 zU>R0Ms1)cvtQ2-GMz-Z3xs2)FERAaQ6G4{oF@mCBKoE4o7&|}X8CC`c5y421R|ObB zQ7a*+0`jXMBS@!=AUJ-6z%ns{pnD40g~6Nz1};z}ZD(U(;0DcZ+cF3+34xp=!FUN| zCD=KVFy}l6WrBKkImWkeIeC~|04Oi9t1xn~!+fC%lR761GEs|B87`#_l@d;2|I*FQ zz##G%6jHygvobJ<&I2_P85ltUDEb-HVqs$hg_-DHkP;C_m3lS?22m+cq)Rb^+%3uq zN-_#y_ll~3a)uh%eWF320MG$Dh(W9f)OyneJ3-79l&wq{7qf%X=t_15260f%l>jxf zBtR?%HWrYhSWbvBFmNb>!iQ@=I|IWlc5oooGcd41ix*CLZVmI69a<+kNGE%L?;^q1CIr$bY@`SmjT_O$793I z#lXM|x_+I!NkD8;|MB~8F){FbUT5H7B&X{WuT@#8;`3e zNR=x{l^a+U1Ajm0`YImJB#?xe00RS$7pSmiVBlvEU|>+>@vR0)xQQ?@@c4t63=CYL zrbIUvIO#DkC@}D!6973NXah*01;{VKpdy%ocNHH415XIZUn~s#d=9K2RpD1bs=kX% z|H#oORUgjHz#tL>a*YlsUPLB?bQ^%eQDm(!0|SoYJfq^F!q4;z#s!E zqzi-@7-Siv7>#8aqd{|(43f7%Hw7udi~(Iy$v6j8BujzP1)~y(X$4w=3cexULuCsG z=mO;h^>T?t=?sjjpzvUxxT0Pf)I0#$B5%mRz)&sBz#z#3wh1H&u}hXQhN+l=K?dZt zmg#|9jS3Oqo1bi9cKd-Z>%GXsz#s)md5pFo=6<-{_NZ1nU|J12&;n%j+UX~`8l@Rq zreEZ3l#^j&0i|F`Q&4aP!R!L9X=I$^HC>*&QBn=n;7|;MWk9V-uxawsYq=Xm6ld`= zFvx)eBn_mOX<`7}|1zMnMp~xN;c1kfewMpYBvFr#fk6tCFBpqJ%sNJx))J6b=83SN zEXA-^9%K~AKU{oRf|5glLB@=MfdT9;x#)^qkL#C=tjKvpil#q7@#RC#yJ*33=EKb4weXK zW?)d547xb#J*dWJ3|2@4xfd+Q7$OZyK}&@h800~jXM->U!xO>j4X(5Obdx1t_#@*9{1sZkOwt{SpnBFSTsH6__up+oPVPeGav5W;Q zjf=}MFenLvTqn*53qjDf3dT96!VC<`5!0Ck8&%K@l)`IZJp+TP85;uw#|b76Q2XFN z7_gsWXJAlu;bvgqILVX%5(fns0|QuG%|?`g0fbrA)mT7n6Hx{RUP<*JF$M+@Rs&s+ z1j5`_YKr^}3?R&>s3yhAzyQL0a%yVK3=AO5>7&*z%E!Ra&d0#OnV|7Zgn<38fcS!8tNNi3}Z3;C<42i9S#5PA_J44u@?83m{58;3VC>n{Kj>HBH7s3vUte?(V zBP3G~weA3ts^>`Tw@B>INbH|T?Egq?Q0o2XGQIb^qqr>>H{xtnQ6#nk5?dRIZHB~loW9aELwWifn^2zmT#z`pz0JS?8j=!* zvTH!%P>;8P*r1!}L1zww*ibc7kl3q0Y^eGzAU3GC#lXO@gPVat7|K2j5{Ife3t~$^ z7ZiN}aiEHRBC(}F-6N>DJ%|m}>pfHpj0TPF*NdmEZ4MHLs&NFd zp%%D-*ii985F4t#3W+@n%m#%&0|Uc85C^K^1c(hiS^o^kGAR2xNF1u>A&3pNj0M#A zfvVv}V(TKY13_%4-e?dT)K6z%V2B5e5`e}YK{1;Jl7K2I0kNSLOb4-{8Wte2kAT=v z^`NdQ>~Q=`0*F)p?;@!IjVUog&Ex_N5ePsJ!4ZaXK#ovHVml$R(?D#fWd$HMX#4`S zgi4TsK^V%e2Z=+~bb{DW%lbfUsQ7Fo_6kAJf>NmFjUWjq8+=16XgHpMf#Cv39Lm0l z#C{55L)E`SVuNpJg{tQTU78AIiy^UPKy0wydIknd5C`fyXAm2D62H3;;@JNnkT_IL z42TW&8K?&jE6Dpm;!wTQk=WZnY^dIYAU3FR&cMKM6l6Z5$n)vMjpo2>AlH;;=B`(B&JNa)k#uj zTsD1TZlk#5MkJZ7NbEh+59T(CPu~#`nlOC=cM|LLweOp>r{A&5<=MU=uTevawI`f` zL1KENsDkkH4;_sb(+dhpSQrhaUjzv_bT(SBUI}MlP?@eMrXW0hLT97Jbb-PWmgxmz z3L?`VfTRT?K>81Yqz$?nEm$=oK*|Nh6@;fZfcQRO`9u)^LRX{3^bLh29MiXmD+o+i z=x(%_R#d{ms4|^VLP2l(23KoI``h<^dBeIbZ1(9>wa`XYjX!C?AF5I+IL zmxyFwNSN*@sUSRkLr6HIT65^v0=;>P#oP zrmvdXsK&T+`o*b@>WmYn{{&GA(-o&R!WVad*HL6lYn*-pWsXxOzG+=7BX~+%6trUF zW0AnI=@%Fo<)+^|Dkw1BZ%={1^m|V#9j3>5G&*cg+t(DwB4~g-Cu?A6!7yEMSChi@ P4_u6_+kYKux)lZh&;lvM diff --git a/tools/sdk/lib/libbtdm_app.a b/tools/sdk/lib/libbtdm_app.a index fedbfc45da44377d07e5aa74b3874cb91182d806..4150f046e1b1305a5b762b11e6f96e8c454af7b9 100644 GIT binary patch delta 27417 zcmeyjk>%Pd)(KK22*p!cf!Tui<*TWb{ zw0{%>LueIlTz`y#0fhTrF))De)I|&oAUyjS1H%G228JbW3=Au(7#P;9g5d333=AN= zyN-cj|0V{8!}k~%P6$D8{lz8*hO6rs7;ZjdV7MoSiJ!h=V1VJ*Nem3g_{%Z|1~kmb ztHl7uN_h;7$XLsXfl)6D1M7nYEu$D1iNljOFdA(B%2>u&pP3e)nU`6@P!ykZM} z-#LPUse0@+_H#C7{084|(0vr;|Mg|s> z*W0NxDohUMP-bM9EYB&vc^=0FrpZOzHj}q;+e}`-%~Efc$k6!V{{s#N@hm&V2mcq| z{eST8|4m8^3(g#9d<_ymc>BNNo&P-C3TFcnKs8AuX77xjHuQkyxa~{(ytw&8&_hBMyd1 z9IQqjtdl$#j5ru4aj+P9uuSq`G~!^I#KCOj!92->$&HzTfnh}vPYw@v<3W&N9YqT_ z{a4~(_%!(gk5|2!Bg4io{}+Dw-}nb4srdOn54Q#rkCaBx111K=5C2y(sWO0Q!}tF^ zm>S>z*JL()|G#|-a~lH#0}qQQGY^X=ljEEJJW?7gN=j)UJum-vFg0oLKHy*g(SlG~ z3`DbRTK=a=!;i-c#9``q@qj}VtVk5hZ_*Hcz`@|bvVwW?MPAv-^SRkUuH$inxJH)$|5X+%BXU}*gEe+7rwslSb%|MRTw;OMA$z`@}5`9Fi1Bg4}V|5X`4 zfP;Yn#Bclu^0e#+1`r=44#H-R44_y9d);8M0@Q-<|0gYAnB>8r%EG{q`et$<-&gZZ z3qSnd%iQ=Cy zQU=51TK+sn&dqQ5IhpDeK=Hu9z@Wjvz%YZ6fkA|Uf#C}y1A_nq1A`9}0|N^K149Iq z&S8ScA7El&;9+23_`$@$P{Y8$FoA`EL5G2XA%PVlzk?N`?*uDE9Sa-8{54RzfE^;v zz`!thdIIm{P9cMO83qOhMh%ELAUhcu7#Iu~7#OS>7#Nrs7#Ok{7#Iv07#M^Y7#QX- zFff4X5G4i%hGn1tV_;z5&|qL#!N9@L)Obp-%2T6kh zmw}-k;sX!|?0XFch8QMDEPxb&LLTH%kS{@OnB!`oF#~c-0}}&-4b*Xam>{7B3ZZ=< z1E7w8#T>{HXP6imG@#taM$AaPII;BX+PrLbo1d!5$Vwe1B(QU;v4M4En(W zZZCihif08G0|_lqdIP0HkU=@DkRS!=DPd(`04W3csgjj}fgkFK4ps&RWhi?!NCC(L z8Vn3;SQ+XWI6*$sU|@hHUXY=CSQ!|&LE;Py49Af)fD$$=n$93ue1(;PK@F<@7n1rv ztPBinAaM-_22f^zC3XciNJd};#lH?4B=v$^9l(b0eIOeHgCf+`MQn)REn#C|kb;W$ zu`w`!3h3=AMPD3CyUnHI56 zPV5$*{(+g1eezi`oyksZs+0S2xhFe{FP!XmN<$g6N4>CmVto*#t#NbLNO@cq(a%C2oz*sVJL(0K@>>71zPfe#6jjw1W7 z1)vbqK;qYf1ZTntel8ln8;w5?jlUjRu0qlX8^cy61_n^6Vh)Xh!wB{D;2?R- z1TIFvr3fev-!d^Uz)BAg|0fdz1FUoa@%fiR&6pV&V5J5~y+1Pp1E_## zfI1+J8Io~lfl3aLf;whMK?*Vql&ag985lqr4^$k1RoTryO`MtFJW^Wlc#>t9Dg(t6<PR}V zwbwynptkwsJ935fkS+EAQ42+d@2crQq0|O(}0v!+= zszC$9hFYcqVncne0Alk&ES3SWL3IEF1A_#J%?lA10kNT$@qpN%N)Qx6AU3Gk3QGD6 zAdWml!yhIF21Ypu8`Oqjl!dShK;lrJff`RRhk_bgj1mwvpcWr2O`HI=eW0G%0Ahpk z6sU{`v7w#;H8mOQp{@frW}q5C<}pGwfZEcqC;$n;EC4l%M4+uZ7X}6f5F4a663Pad z0c!7p#6dN7F;pDn=~^fo6u|Y9pd63`E<@QMmw{>&kmfZE3=BV^;vk=Z8owa%Ees3{ zqM*h;69dBzP_RSUdl(oPw4m$*3=9lbQ1%f928Jdm8x%V0A?$i^kKq7>!!U=Df#DRC zy?_x?=z}aLEc_!oorhz1rr0qc_mU}9isV1}3jN=wa9 zHYojoicpXTKhp}88ISdS-Vl)TJ1{JUQQ1%iw28MDd8&m|h zLfN3Ac`}p@5?=^qgNpA*P&TMoe+y-AU}IqT3uS}q0iJqxh>LcxF))Zj*`Uh82+9U2 za)7cAurV-rL)oCpr5(x!RX|-(HmG6(HHtx@1*(ideQHKwNC5?E{DH(lVjwoRFu2pm zz>o;d-=G3xA(RbjqJlcWFwOU&;vg{)8>AUzEF(0#g35)7P&TNs2kP^}^zMR+gTz2= znBG-P4E5lW3)I)#0?ke!HmFYuYQHrwGB|95ii5;JY*1$kBo69UGJ={W3=9nA&=d|5 z1F^ZG;OhJV0tdJ!5F!78L9tF_1&Jq2fLuHT7B$7lHCPND)X7#O8*I2Y?hoIoF_SKw=;^H&i?Vqy`l63=9mfp=v;4^&k#6R3ZkXNEc$zcc>ze z7>Lac6;A-E(SxWFgJxZj7>Lac6;A=F0d@O84H>8!keCb$0|PfyTmvFr&j9M;8$dW< zb_Pf@G^mrI;vg{)8y37dAT`iXX@aT&iGkR#P$>YZ0S*5!FfepL)quo6Y;LId4wiZb z23RUR3RMIePXMuD2HgXRLq^;fK7!ax3=E**1ki8+ECGTF9Z>Xv#6WCV0t8j>AaPIu zRsd>QnLt9W30f!>fE0i@+)#;`PzjJB>!EB=zjYIc4XX4R7#Kjq1&kIDgKmMunIK{y zHaArK0?0B;h?>VxH6Sq%n;R%#vov!=m8Z6iGkR#P>hF)gN7VH7!)dfYz*}bDxlUXG%h=!ia=r@Hcaybs5rdA|1N$z4Zn zChtp^-5ejWgmLq1y=JD#(@$tjjx)3YjdLW_i%p(q!^4^(&cNU?`LLlfSp zOy)OIXMMxYz`!}#+DMu4&E$9^b*2c;$pKknljj);FixJl-bkJGG$#W?!{pmW%B&BR z85j;sW;Rx4_2vSJX&Wo^E>K}$XkdYidGSoAJB26O_Mhkt51$=n)}0 zK_kYXbO^E*#O4Oog3$3DM$q^r0|SFEw1x(?qd;tKs5of&lM&h>0u5w=%mImk*xXQY zShoQb&LC}!(2i9M#7s8uSbfZ7c`NaHkP?s)pr8P;xuM+|Q11iQYsr9U1J4A2*xVq+ zpiTm)`vdLefT9Ux4ydOBVsk^qLFEx6Xow!vwT7Al5-VX~VBi*Fn7q|Wu)Yc^4(iQ- z*s$yb>d`QQ9KyiB02<~1nGX^JvALn*psIyY6cmsQ44}ClkQ$H}h|LWZ2i1p+Vh}Yw zP`f~4AU3xc!(>-$L3qarRF!}_QQYDX^`L?r-X(%`F8Ugl1p>kFkTsG8q^cRzVek#6WCr>B)B-{U-ma z3Yg6ISA=oX3hXT!tzZ1VjAb*5(wlMnn=V^U!(k)mRf585nFPuP#((Qs9_8;kX*pT*k>8{;9Eo z#@7x^wzpF@I>F4qa0@Ak!lumxzXfxb{b44cqZGJ z$bn|apz~u{?2zdz*$<7sKxKw3a*hPgfPtsE)Tyejo`c~o>sgk)%<5U3Ynd8q6It}&%jUsQUTQrV#73pyaAE| zX$G;Oni)Xj>!30LpHf&Z8lm$RiAic0)067{oSRn%%_W^0X0#X6h3}VAH z--C&3FfhQv4y5@FXw(DhXi(1wqzvR(5F4f!)Dr@WYcMc?!y8oSfeJrRF9@nvM-pTj z)M6b_K7&?nCXAC8`l>-|w-Ztd6qp3b?*p?S1c(nB z-vI?POg(5^2_g$_IMg$MI*>>L3@;fN7(hV_8ifN{@B=0ZosD3Jh89Q|WC3X4NrDkF zUjR&`d{Js*3IkXgEC?BR2CV>L zfXJ5@WtOBu6o5q`3LvXl($b)c;M}r$&@echi>x>gMQt9$NQg>MMf(q0Prw3|5!#jj z)#ISb5ERHDHmr>SsuMxtpb`Ppwt%)b>KQ#4u2Nfrv+7~ts3aa2lKqGe`K@bPl1OZjWuqFsd6G$^i48(>t zK|o~?%;I=xNPxsZY?#HM={=BMP*D^D%DvER2WrZI#6e;ipq>LaR3ZYT2-=4MX#yz% ziGkR#wh5^Gf>{j8fFLy>F%TPO@noojK;;-{RRpY^0%|*e)Pux8Y*0G|WIwo(18b-( zf@%gec0g=yXafdR_`xg&wRJ%Tfy6*;n8nATdO>9%Xp|S$fB}v6fYgJ;Kx}SMJTovb zYypiN!CEk&1~W(zXh;~uhP7Zo1t-kn_fQK!Vjwom;;&F~PyzY`6pGNs45$PEnF$gD zvALn*FFe8&awJF%sC;5zU;yb6;RTILF+w=p@{=9X#i#QNG1^Stf0TQ2-%$%_ z-z}UG)&OHNVVn%@wy}Xm=0cb!Z?I8f%3z%AFk1@L1_Lo46sR#~Oy2)jooO++4aRhv zaq@)OQlJJH>k%#nhLFkgZI#)CK|`dBlh+g~u}N?3skxwaaGRqYwV4@pC%3yG zX%A?XU^X|in4CXDBN{Yf#tf-lK&=8{P<`}(f#Hii1H=FS4F4ewa0Z5kTmSzjIGHjq z2td0OTaK_WIDEC&arkPV;_%g;p#d}`&BpNm|Ih!R1uZ-dU+pJPJP`w0!^Y#JpCqc#;^O~2td5K8L2IrenGPs0M6x(80CQMC9Hz!qAOoDZ7!)V` zZ(IRlPvT~F3&_-oASOrw*wkEz zf+$cJ2PttVmP3tIO5td12dM;^oBF@86~qSV0vnqE(bd=p5``FB4`PB8s4^(k3kHV6 z!Ukk;M3Z9De+5<0@-xjA#pwS$CLljBIkVK|_`;K`)u``>9H$ZSt09wyCTP3A_<1dwu2S7Y)y zk303CRv;*8Gk{VysD?zspvFIV0Us!le*X{YD}W-!n88@E@gpcwcsRO@8^3@|1bI)R z@e_zSiHm_jNwD!HQ~}7B9g`HF|5wle`AKs!$a0Xq44}0yAj@SOzS^sR@(crmf{4Rc zdssfx0Oc7)8x2sO$?(m84dxX}54ae7xggdAaWN>q_zzhRngmM;5C4BtW8`54$C*Zv zfl9PAgqZSlFgF17y_^Shvc&+E{3Qu zhET!8v!K|l&t=LAJ)pplQJRoY8a9nX@f=9E29tOalbbpNn;b(gTUTh~MUdZXg3O=$zi};y4T{20hET!A>HoKBG9A0{zwP{g#knAz8cf$et>h7Md-Wd_KcJ`q zM};uBK4yWGWe#8ML2)#B;t2~-yfl6U83{@uFa9^a2eCoMgHy;OXaX>9d<7B*g@{Ju z3lI~ULT*77fP$uDlH!g33LOF<5}Zzyk~tx90W$mI|HeB|jap!{PlL49gOlHNkOai= zs~{%S@WUV#JRDsh!<&>i6c0nwpHebM;~9`Tkh#16H=Y8q;cnjc|C=UL(*lMrV@SL} z%mqga)ZDcQb7L4fniSXlSI_|EFwJJewf}j*wkb0}lDbkdL*q7(@k(3_h70~TZUM2I zxEQRI7?cDJXM+<4vlU1SD5;i)G5v)_gLu->$!9#ICM$WYnS9T)Z}KWnlgSIZ%Jo2l zB%tX|P~QiXQ$Y;_P-6?!(z9SVwv3 zftCz_I>8?q7#KjaW+1jcBV@@Ms8tK^qF0>69a=ORQx_@O#-wF`G5&B zTnke39!dNI6KFLRL_ZTV18900RLL^1G9&C#124-7fGoNL1sbTy3|e#tnjZqS?Lnae zng#;3{Xn4tTBZf+6o4%2WM*Ih4Sa#v3z#8Oi6Ay3%jCpvwaIJkdBBUSKt_P#Ko#2m zbp)4b5O;wF5kaE}AZ?%pbD;PFb=pDk1?m!joC0bPgV_uW44~d6XkiJ+DWH`JpuP%7 zF9*mHXn26wpz%a-z#{jxL2Qu!KpH$585lsVI}ke^Ni&EIG8}|6kz%V0H1q`x{9}v= zf8S+<1T4s$2aF61poR{J{SItqJ!DZShy(H^$WSH_0d*;e4eBR@G{DxRfsz%74eIKG z#6c+*7Ahb%s3Qdm70_}9(6AxMo(W7046x7zEj5EB+iRd@xu6x$AcF*vqTPs@fdSOp z0*PlLiFYwW7NCN}H!wq@2*kd`j94oQ$~rIyf!Lt@0&S#P>KQB&tSsB zzyM1!o-Bx}y9p`B512Nygv1nT2~90BSGg4m!K2gNFg4JvwhVSP3R1_n7O z8Ku6$iy0xc|lkS(^kZvO#J<4$FY50Zkc{GeVaJfjr#-l>j+nHk1u2 zjzDXaK$<~GaxGLGRJt67vO#)53spgCKzhGI#X)S)B7cxLD9K2G`jSxJYeLze4laWi zjKjdd5Cvs}a(q6N4YB~Vt`}qw$k2sQaS(eWlnt6R04=HjsR23q4pf|jnStRAlnts6 zKx>phYCt0@|CvBj!%PeeAVs{;r2wEQwnQi!6sMpmeUJuFT!Tsw5F3;R%8=AlLfIfS zp!KC7HK1ihJy3CwIk43jAT?8<;ufH#fuITnqyd!pmO~{#iSjU%4O(>pTI2vy16o}H zTMPwSMDYZw2DA|36_gEHH~|_9f(;~rMnS-Op)2!X<48WBK?Z(E`U5X+11SOtf(A8V zicUdOEU1kDD#Bofg7_fyATbadrXDnC1XFVxsuv^%V#Cyc#y~-OL2V5w(0&FG2h_k& zgC-nMY6Z1jUQ0avkQj&!Q*#|^ zCa8s!1F|2c;T}{Xhk=0s#D-}A4X?q}Jcp_QiGkQKHJ~MeAj?2aEzlGqOg%p|<%7gP zY?yjbs{^8@9fPZ z0we}v!_>cosIO-LwO&E%&|n%se2@l^7>Eti09qLj5(kxHpq3(R_F4{_??GZ9HaDnc z#=yW34;2SBWI-6D7u1jiVGtWs?nHo=hQWqbH$ydmTErkWY-sfeXfZRi#yfz-1}&n2 z)p(%gM6eo<1*8U4W`nW{68jHQE&2n-29-ZwU>pVph7U+=P@@ZG0VuJ-*r4)V1iEz& zw8{s>2H6E_ufW)upuz{bMms2;=trF_ul5fB^Hwgok;L2OWB z1Z^S#u|Z8+P`et$1|>iPP*!Ax3;;Sp*&uVmplncjN`bOLW`dUmvobJ%)PTwpkU3L8 z`F}c85h#IxcE^AuK(5;h6$fd!1Z9I91ab&S4JdtlgNlPv_ zvO)WVc0$=8y`XIuFunJo;vt~ECTJ}iD+2>4EvZ1+pfsilW!HlepBa<`Qe+8bgB008 z*`U`{wt%uh4g)ntVTBcFt^lML zBnD!`3M+7{7h1G~#s@%ZKw=;^Obw{XCIVU-2S`}Dh}#zgGxl0`s+|}kQj&!Q(q72xWE)WhAIMyf!HubU!dZkjyN+kn}Ny* z(DVt&XP`1d7%C3RexNB8kT{49npTFHuMSlM5(BZh`N8d91_n?Y4W`H#st6sf?7TxagZ2@4Ks5K$bOij5~x9-87>eT zrl=Jv4jLH%wGCnF7emECVjwn5J!o?TObvJg1SomgGwh5Uj$m4{e+5xN;%Lb2#{|;#W8621Es1 z584{S2y6fUhH3^0g4i%cpxqiE&7d(A(3TOH&xD~xEJzH*hN%Z_F@dQ8HAX;sL1G{_ zOpPv7FKBG00yJ;}(*Qc_0Hgu59|gpQX#g#Xhp7pIY6gjc*f2H8P;pQf4b)eJsn3Rr zgTz2=nEDoI2!Yxk4B);TD+2>a5X6QlYK3YBjTV6#kT63*BSs*Hg2X^5p`gYH zcwY-E0|Q75#D=K>?{Q&eU;vFY-2wIgKn8&fc@DJ<#FmGa;h+&E5C*9MjVOUIhz+V} zK*Lb5rdttIJxC11hBe(TL&ZUZKj0PK(E8#9RQxB41Oo$TC<$aJsB9O5mh-BtlP_q? zPfkvkpDgr5Vsg}zuakdAv@o(vzVh^2A}G>fTeLv&0AquK1IC^L3JU19uLVeK(4Hfh znjJ{upuI*g@e7mZ-xsfcfh79{i47Xwg{cH3PZ%4tQ3%EcZ3u#~L7jCN8`Q^!u|a)l z7#q}ohOt4d5Ju2OcTg;X*4x7*DnLzBsFzxh*b|W0pymloJ!r=hjJ*X(%>g9#86@@% zB=!^L1jOD;P%{H&5U7~}V}qI#FgB>w0AnkF8r@Kb>L9T#kk~FPlMg(b#>B`nIiXr? zvRyO}Ta6$Cg9!WNfM_KqQG@6HW#O!O8ju#V5;Uaj=$gGBB7-*3MF9S_N8?t;Y0}bNU5wMl~i`uE`sW#HRB} zFbc4iD1qkrPiHB!g>o@41h7ng5TnF)LJ7>2$yQ=o$~V~|TaDF%pMhb*Be-~G1;KD40m0W*UIlLhk~VZ#^yH@^69!MyM#Sfc3xGeaYIW@>>k3r`GB_F87h z>=aK7PxV@6$U1Hhrj7Uid$92EELy<&fQ7+>Nr%frD#fc(gP?bMLYrHb0B&Vq~?=1xC|rWNP)HXJeye(7cudI3x2(&5)Bo2xy(D*6L%vTT} zgO@yl*kCh3Ga;ZcQw#!5|clt@1ETDRATa}XFW_ZjPL?L zgPnnag$Y~$1TcaM0LFmH>oe6^0~i??u1%gFEe^`>OgfyCvecN=m?mpvsWB!`_Rmsh zn#Tmr-;CEL&(Bh4D&U%YB1?_!9}@$E3nM67v##M{U~ri%ovqB|!~)LMS6D!~Iy+mL zHHD3V;qc_i*|1z~VY&H0_69cSE(;6G$pReWoBNAY;UX5316n0EU#XB_fvGVEix_-3 z#<=-Xof8vG7^F~g^W06>88`DZ+aQED2efLiK#yD7T-O=J1=V0_y!pZ89Jr|_lLJ~M zH|Nd}MiG(NykHIwT*MTt=IjE58nej_o#LDSFA3y?nrZ=3BeA()9YU8GSl8T5$hshQ z-C*3ja)&h&)NzyfI3zbS@7~G|GXbD- z8iYaF2ed00#0FsyAJl^Yu|XKb2SqH14ZKH(| zpmkA343p3lfO-W;3K%w`$?xB6e@2s06|{sj6SQ0vy1o-_K`LZL>*NV%CvH|c_lA-2 zz-0al$5{o~85krc``0K>{&yjS@yz7li?B3gX|lQDVwQvycw-6DVtm+Ad<%1E&0#co z;T%n-KcJdJ3RG(}{{27k@Ba>trW@RoGNfcbKnzG`U=R@c4l3RlQUt!+OF-EPP#WYv zGe-u)@8Bg9%wm^}CoO20&XjBT<$utE|4z)z;UWqPKmEVpBFG@(z|gr6w4jHp=1YT% zL4b=uLkno#M<-X{tNQ;=3mOh6FgT?$1ittmq{MzQn=0ZTilGZh%_f?KMva0gyXJGlZk{^w}{xj2;}aQ**93m8B?1=(9~ zg=Dd8<1#dhYd*t0>&elcR2n$8!NZINEGlLVWlu`YH|K=j{jU5o9 zkixmB9MD=}(7pi> z`ziwi156w=bOSor10)VQ{s%Pu2V#SEcf;189Aso*fQhp*!OwRJ2ajx8K^sz_2?>}5 zOPLrLKm`WKpeIO+StOYm7=obcL7h=haR~AxsFwlq7D#;_^W=rTZzrE~(3_MTlm$Oc)g0$w!D2JsVUG!CR5q!*M7 zKx~j+@IV_>Zysm}3aYms$_Cjx8$5{)l>ns`nC3H3MW9f43T1;V0PP|JsR3yQHSj=e zkT__p8^i`#>Zm z@ebmXpG_2C^#`pNn*4jBG8<^RJ&$?vhiE0X1?&tAD$J98CMhu;W1bw4rN+oO{k%A% zI+G>Kae}{{KK>^(E&twI)`*}eJb%8b#gGw>* zzG^lZc2J2p`Nm5XSj*OMvcOyM&C;*l!kX-shMNW6zGo7LA6W}&(!pADpl0%9=H1#M z4xsV}X{|m#csnob@K6m7@IqtwVWOH~J}4KNIWj2z`!D+e#0Hf|W{wOC|NiIc*~`@U zXY#(U^`amNP)-8Tpt2Q2>r8%_AU=8HVTs8Fdn6_w6_RiTiGnI4P?r&ur$FU7sMiNF z6130{#D=K>_4L4O(ApyKq9@4OEVs#qdqhC%d_a;QjVz3l9op0<_vOxzhmM0YfTS21 zSixuef!H9s7#Ub6D@w>uzR;sI`JID6J*Z0xk^^nl1MM6Gr8Q9AhVenGHel`q$%EE0 zfQn&Iyny(isX~zTAPn+3(wV<{$q-IjI?}1ZY3cF#NJj(LgAN^r?>9qQd<8m_EEnyp zVURjx%^Y0fz@lE<^xC^BnD!03&8fh$ivPnm>eGw!V3yv$SxrUMiy{R zi!-!gbc5|cW&@4wwJ?D8zc5z8wjeXrFif8DR}DlR_^ZaaeX@R`IxA?akOFKAGHU<} z1A_r*2MjAeBk0(I)rHEepo0nyOnz^x%yb^S5t-8lbSf5T73SppL-MSkr9kzQU%yB6 zfS`S14tP)3?#nB9PuFO&z*`AMgUJ(%G~-Wz%66n&1KQz|g4F5&<&Ho9jhK|yJU0CO zf5oIGWrmI!4>%Ysm{&|PQs!z}z}V!Z_<)(g@az8$=AMWSjvk2z91J|nMovng3^%#; zzZK)m$p`+6h|X&K3>ws8`~Uxr$i|od7ry*|Xu<5sFaO6*XJce^3gqEvf@lFn83URV z8vlZ{hFLN2Fv)&^Y$H~G^~v$;f5UJ8HCR?m)|m8w33T-EWRE3E%!&_K7-T;%Y;R;_ zbY|q61UZ(0?f-v}d#1WEYAPi%+!5ON<^RI3{|_zL0olmF_WwV_9p;Vi|1W(1|ImV+ zQztSC2kwHbW@r2VzwyQY87DkFA|o_2EGzE(RDAkha|e%*l82JwtV%{=b(| zgGnRl0Tak(1|<#)9?uDr6cq3MpX6b|BYZ%C!IDY#!}NSoIB2vEWD$rB z@;F!xbT2X3K^hDUpi?qI9tEibja@+3Ix~cVECM-BgMk4QSRA0yH;`{Yi@-n*0Lg;} zFF>IS(hQo-1ce~TvI>wSNHgewLq^0Z;CV1{4F(2K$ip150koMM8X9{T85lsF1(2Db zWf&kDWZwtSEGDcYpal|zS^#3hEY@R!tndYC04Z1Ft#A#ToGcpTxna0$Mu_tz_B2hjoMEZv)HpGaQVw zK<#W$fPhB37(fHnpil<2Z9!eDF6dDnph0U8AGAOWtQb0423oufiVe_KSRn=uhV{_h z@}PhL@%J(?Fu(!?#6JaE70t*1?!tl0yT-tf1U|tQ6fz(M??9`R85tNrc^08P^$tY2Fj2i zHb^a~-34NU&8VI1|4Y0cw3-Vf1foHQu7KDe>!yMVVkXF50@w+5AR2VEJ50?=BsH+* z<{%nWCWF*~yaPIC8N>#86V%55u|fU^caFhJ5*Qd5K=~9T0VBcaR3q zx$(hJ2~ZUXDrG?8plS^?tN~(!l0GQ^!PuZH{s>g)L#c1QiE~f!MG;_IE)YWRO9i`tc!D5r_?2G!0^dGA>9Bs7?e`d5q9eAaIYE ziGcwm24ZtV#S5X)0jl~ytArRqO=xH-2r>sG29o23h}SdJK{bHt&2vyTs49c4@&~a& z^&-q-*qUaL7>EtC7_?>vWC5tU+XBjLpkXKm28L%)GeKe?HY~LMfyL_?7(n&l4v+>= zj|6l?IW!%B#6U-+!h#DtO2Wjz@PUzm0aQ7_G8<^6CoB_!Iy10YF;Ei+rUn%BFg7UK zV3`?o%q9aP>+}@@j8XOAEXT&c07?g-f*sVQ2Pp=p12)LE7tk3jAaRhIwV)_tV_*QO z0i_X;IEV%v9s**6)Eq=oa~8@5(V!|8qz2?L=$Mr^1IWdogF`?PAfJHx{vbBUhoJsG zhz(jT3ObGp#0G@|XmkX`HUXVB4hmAx7J0_$DuRq{_29!7*dSLxfMzyf2^e%J6G#t8 z48(>-3AmlW23f!bTJ{Q44;yR)iGkQK_2Bjc8v_H#GobPdrXIZA1vF9z5(IHz8bB!? zWHG2A0jkkJY|zOkpsmXwHYi~RK|KMg-9TjuNF2llVGtWs&4Us=hz%;|L3|L~j*)=@ zocKWp-+>BVhRIj7y{CH%F$%MRh8h{!HbpQqO`ff%0xS7J%g$hl0#qu&*r0W;FgB<# zf(^5PR)4|RpaoelHh75)s1?G%zyMw%17(Ak$UxcPB{ER<_J1Ob9E^V8B_mKF@RAWI z8@yx$$_8~SVb*|`j6lUfdqH60;1wgNqd!bhOo*9YUIqpi7SQkyQy&v(rk4%09cuyS zY@ov<|1g8*ec8^4FfjaKo(x*f@sT-2ABF- z3=A$faO@-o1`y6(#=ro=MR5!aAY8GCfuZIW14APd14FAB14CyT1W!K3zyQKCtQZ*P zC*&9yknzPd1_pHe{vQLw z7d7nozZe4pVO*4&o>@HkmyEVZQb|f~d~$wXT4s8DdTL30ZenrvW?`msM)usy_{_Y_ zlF9#=r5N)j-%B&uY|kRiJo!9(%H&{gW~=F3-A0tc<28nC58oO4m7_0|A2$x;I03PxBv5SE1Ws7mZ|YM zNT~7V|AW{6^KdtuX;4_C(D)c6c8rmMfuZpshzTJV>{3{G;eX?Ou*f|Ssd)CkCKrg1 zQatltDT}G`*8d0f91M!5{;yWV_#31^@zZ}E zZVe_LDUF~9Obm+e|F2|HWdPBJ@BVu*HNN|=$!z%UfBO{XHU?E2E{-BK?pZ|GQH)$|5X|O-w zU}*dP9~9H6pZ=>dfB*+P=9M@YWIr%~QUXlu@Bc{)7?d&?8vp#C&Tc@)+ee^9XV>)w3`#FepIr4h9AW4F(2=6^slFA`A=+EKCdx0t^fcF-!~$ zAaxl~x`qiNe}Rbs;!I`+h8B=M76t|b1_p*2R*3i>R*1ectPBhwul!(zn7@DxLZ`4Z zOzshOoqXUv&-9D6FhxPxTQ10-{#85tNFq2|nCgqu^( zund$Vpay|L0pxp-gLW`Nd;*f*!^ptk4s{SS$W>7Fu+Rdj7hyuEiAGWb3rUcg1SUwR zfTTeo%fL_%@d1bf3T}|19B34P6oG;rL2Q`gdZ5t)a@+(aNa%sopJ9T88YqO$ zfdrrqg+&|4{5wnx44P2Su+}q!jE6XagPDQB2O5ka%nS?`AT|R7Lk}|pgEv&eb!LbK zpt!xs%)l^*fq?;JSt-c%Aj=pS7(i@esQ3z)xCR3Qhz&|>AV*wafrLao$OkuA5b-U{ z%D?~;16d%#%D|8YHK>Xe;ZRs&0~yr8%D}(|bzC1S1A`(|{dy$z8(0|_I6-PO7#Ls) z6r}e6D?>d4H%Nkkf#Ecg23YC^DZ0YSz#s)x^A1VP2bjeg3=E)D4ok=)Y>=D)@`M5# z0|O{wf?~pj4dF3YHkd=}85q*o5J8&32C)njq)luL3?M^6?0HZ%AT}r~fx-fmCO~YE z8jwTxAX$8Zje$W8=4hy1P>6nDV_?vQhL9{f1A}oQloP-X$@d@&64)UQ0x(D*CR_`A{gpi&hS9W0>oT9AQ_;Sv)A1E}Cp2geB$!viJ; z23R2jijr4M3=9WY8Ng)=i2sd=fdN*IfcV_Z3=FXH1H@NhW?%r76%A1HteF`YKv{Se zlpo9tsfz?a^#v%^Ml(aQASjQ649J2O;~-ap99RwIgF+1yLak{0el-3ZG(H2O1)I!( z+ze&`wSgz!lW`YD7KJvBryDXciflHQHDTl`E=tTxVE_@6v*Z*f&zJi)`6kos`m&7V z%=n_zooA3xmAGzyKiZ)gwkgCBJ3wqu9l*fAum!}1nzI4KhMKKHf zaj5{3P=-jzfY_i415|Q?*q}Nb6g40=sG$m~AV6$+hv1s0?YObiT+P~U?ZNQ_Vq zfErYcplTb`MrDL~xSoOG2B=X3RdfKv1~n`}ML38J^%Omfa zMGeS}F!i9^26LP^$V1T9oHK}B&je|Chk!UtkhVc4lnpW*)Yt{JBSF<(GgKVZy6%Ot zK~W2;8bNA64toq02RZmFl)Z<6fq@g$ng^9Z3=9mQhA&9{5e5c^dR3^z2~e{i%09!u zz+eSsUtnNh@Pe|hFfcGog0exO1}gSJ27wyM7og&67#SFDLD?G^85r(D*;^PH7{ozc z22eYdiGe{1!melFU}9j3vrp=<#r28LuP8`NShgt9^LI2p8? zVL6lyN&|bK><%UdhWk)9sL}fp%D%$H!0?f&o`C`6gBwf?44@Ja#0Dj%8O#uI5oQL4 z*-$nQGXujsC|iJ;fnhC_Ey2vdumQ>jCENp0HmC?c3}u57_Z2AnJ~IQu3n*Iy)Y|?I z<$$urA1E7~Wmq7N0A(d!C>xZ;B%o|i){}*@9heyyl%Z@;R@H>EL0Q-e$_8caA}G6& zg@K_NRC|GZ49fqvp%S1b`8_BbR7gCBvO$H%S121)sQiVp_kc<@R)|AE1rIBfeSn35 zfeXq86;1+Bwiqh|g9?;=f`y@;!4Ap+m2BNmHmJm#24#av!g)|OsDxYtWrLdbhoNjx z6aG4s4JuwAK-r*TSDOvuI8bqH4rPOi=}<5mRQ|IuFeHFE3=E)hJsHZL!N$Ol4P}GM z{z@ntR424U*&y+$P__UY1H&~a8&sb>gt9>u&1WbZTmi8|9JB`1Ij{vO%?4HIxmi`Rbr-P>l#`WrLy;R11PS&Wxgvk`dGx28n~jKx}TPcpIiL!nq5#eATbb|8!TSWzz~C^=p0lLNDRb=C}Lnp0I30$!3+!xAj?5M z1Brpy+)(ipkQz`|ih+Rvl*d78Kw=;^H&i?Wqy`!VuR(T!%72g`hyx3v9FQVCh^s$> z6frR{fW$y-Zm4(xNR2*34LdX|g2X^i$@F7$UNDRb= znez)I4jS!XU|`^7g_i%IafK_OCK0q%BL^)&Kw=;^H&lE!R2)?JY=*Kyz0++VwizUZ zo`Kk)ZYu)=!%GmG3DSf83}QpoXh6$@dG%}z42Dn+Xbivvi47VzfceG-Dh?6@v0=Um zhKhrR2|yT>=s?2+5}*buG(>BlYCvKjHcW2|sQm}h02)h>LDB#!`9R_zF%TQ3;R4hk zP$_pA$_5P$+=sG3V+o)!2biOuLB&C0AU4b#kUEh0vg{1?37h z4jPj`VpyHrXu>y$=s;d}5V~Nlq0!GKl9J==y8>Y*vGw#^V@6TAm zxS8D`o{6sklomj$L4#c^(;uia<}poUpS)qR6046m1B1%s&qm6OXC{jqt1}i%wl`L1 zeE=FQnVfB`%=ln(zp*-_&*c0%@yX|m1sK~W-#1og-OtIu&@q|YM45GgG6Tbz$;Kwi ztnOS43^OK2n<%s8s4y_hV3`~*ZM&2s1FO zn*7^Dl>;_$F!@2f7_*U?>Ew;OH5oZ3XPXAAfF=#zgT{dy-yulxELOF`aBiJ8I$`0 z12{p=TaZy1lYg6=PtI}`VCoUYITCm2DRH67#Oa@I8gpaG(H!o@P~?l%v40< zg9bUE(%@m42sHT;RK5^HH>v=`^2yAWnJl1A>gIgQ6voMKtoRJUZE%n$85kHqY;I6Z z104%u1P#73Ffe#RYe7(Q@SObLUEJ0mDgqim1F^Y516B+S453hQP>6vvGeY}05m0fE zSj6OdYw>!J3Q!IJc@)IvhW3;|1MZ9l3m=78j0r>?a24ZtV#X-#;Sf_6R)Etl)h|Mhp znogL!|HXR76_eLbR%R<4|6S6P&-wB&-kDr)r_OYTVRAv8*yMe7 z0*vC5&)cap`7=&_FiUJQpS=Ln0rtrX_G+x*j0_AmliyEKW;(+@xxikHaq?vAsp@PX zJ2o&*R`6G11$7b*O?LN(XJMmBbHq1y`xi4Ys!#qOs3;9eo9MHP47sVf#i=Emt%J0g z8TBTohpIxSgeUL&BFSWIJlW7eGv)}Wq-TZ%8)#NVm_dL+h2g8c3PXcEIDig8@~s@YSBd;j6ul!&mzhhp+YuAU=3diH+g^|DXSP967?S%BW&cz>U}VJ zqm0%A7KSrfPK+!)B1TS{JiKRlWu$qc8lQm*A|4(YX&J4?Cm{C3tN)D_F&t1}=-}kx zHRw<{puo_{d6rj3TgIyKE_kw0rizD0M!WGgNOj|>{|nE8oZ`VT@!Wp{6OeLC4hzP{ zqyG&$4jCT(-_Y;{WCAk}hv5;Bx=t=I*YF^i!wlkpL_9bR_rtVv9#CNL;56KW#^3qh zz(n9cy#j+JSOFK0G1NLPqa`5sT5=g~{O`07G^OUr+!NWSnE3C1;~$XJOwg<@186M&tGx^;m>s@?qDesn#0E#(e|rruy8)z6@oWA64yF|v z54adEe*WLf1e(d?%B4vr3s2cRj(hmZbmybBVY!MB}rliSb# ziueCdtiKHs(F6s72CsrbNm$UIws#;Q4ZiJ7yLg0-z5fpyx&S4Z253TJ0Vg6*0+V6* zY7g=mCX(Sgwilikdhf(?VN8W^F_)`{uH}rvQXrm$vW{Sljp_tO@6Yr zTn|+C&R~R0ErG@(K&2FDcmP!DF)%}>Dv!Xk&ScgECGdbUD8GQTg8EFL`e7LZ0|TfF z1R9i@3X%l1AT$^lU`B(cTNW^aCj>w_o&jVPDCdEuWI$|?wIDU1k#A7*9AqXtXru~c z4hSnZW`%$Q@)F$Pfkw1`r!m34nwm zKm=4A#0C|LAoZZ36tLqM7#KioQ1t~8uLG;Ehs^E30tw{m1x%1?5F`&8KLHgtAPxUO z0w4=O-eYC}PtJhUgGMqy)g{Oippgtvi49T;8jXPIjb&zF0G0M2b3nb40B95ANGNpV z85DG&m;u!dAVa@EhrB_C{$OTcfEg;l!oUDCRFwr`s0|AP18g#DF3a@whK%BqdlLEU zLHa=EfoPCbAcskVMkb*SfKBUyLLXH3gQ`W4BV!mKc7oU?pgI`janR%@0|Nu7ngfZ0 z=8{0}1L^Gn&saewLqT;LG{h%opK_jDx_;qgzf`&D2ZR}m>Y?L@AbD`h22|OC(w;4N zc7&M$+6#lrJAzpd0@Nk|g&ZvH2{AA;fEpAKSx9=!0ZpMXGBAMBFi0NMRM+sRB|9YEpsNpoU>HXebKA0T~Dy zhX%1h&8@dk&7k!90m=p?ksnYtD1Wd*M`S>4JkazZNH3^_lYokY@+WMh7t{tbhl+#R zRPIoAJ*e>nYQ=ywgBnSdPzg}$z75KDVPIeYHLO8uK)zWF6$cIffYwcb#6e}^ZKyaX zq@F_ApdsMzP&Q~-2((rLq#jgcalnRxKoh63pjIyv1H%zU1_li%8&uwb%0G~XGoZy6 zP;t<>vlon+AT^+&B#@z?)D0?B zL2OW}2hIM0*r41n8LA#MRy`le28~bGgGSCkia-O`+o2K~%nS^Fp=?mL0xbaosR3m- zR?tWa69WS%8-m7^K;j@ZqEK;=8Yw6nlx;PjY>*mlC>x~40K%?k0OfN~sSPsd1~UT# zY)lDMF2q9=F+5;qV1Nx`KVfEIsD+AyM$|#Qc97l=%nS^mW)6t`2D&5##0HgP3!%9N z#P$G{;-Kutz`(E$G!z9=1QJ{a>gqrx!0TT?H7WxG!!D?1kQj&!>u!NcU|6^9HdGBr z48(?Y+dwlsu<4=aP&FVi5F2a`DF1(fW)D#6WrQXi5F0cZ0&*OPEsZ1&n)e2YgHpO7 zR2)>J2SM4O$(3v<8kk}ugY*2;%lZk<$9%K-RV+@UNP;CvuAaPJ_4ZP9xZhB5Pz4RbAibap8iYY?P*j5|b*MS@4F1r#1POxJFoQs) zAgo9R#R`lKDmG!oFsL|%6~my~Tm-cIg8{PU1;hpw!=Q>3#0IGa6=Wbbs8$En@*?c@ zkhLtJxCKdoED8k06KMR1fq@|&$_8l$kDjwLFn}y7g^Gh5Qvqdz^wvVzAjgBcydX0{ z>OrkM5F6Ay01f7X*dRw(fXZtS2jm)%0Ei9J0Io3D85l|@|Mm)CWZ(Qiml?8R4>V4} z#K6D^^(iQgz}PZK;-C@~CJssiFt!7d8XqJ!C@sO%q#%hGAhCr&GjA|OppuZ0eey;g zy~$2J8k4`(XiVaj^13wN*Y_eY;51WB7h&wr#^<=|#u*f)7|J)-+P`9Zxnlc~w%zy+F254a|Ctd*PW)Sv=dQL6a)e+N^C#2t;s zPyaW5`rpB^@YDY$4c0>oTEI&^J2>uWG`{}7@ij>14Me8(0S5z53{N%>7i64`Cx)k* zhpX`wsKeU9wDHOR4h|lkMGIKL2Iz2gNPyJ$@OblZH9mr>xdT>X%F_i_vuGg$M3Icl zY921onp@Da(~Vcaig=_Ra4={v@n~rXJzxT@6x|%u*u}_bF!^qiy)G#Efm)%UmH{YL zfhrSFaRi$E2DMT_BSoN9P$2f>$rq3%31l$}6*R!}|$Z0%cGBH(P3R zzyb~ysA3Dt%?V3%5WL9=OC&e1UBQne@}OR9^Q|>bTu>dBMw8}9Y_{1R0#{uyC3vce+Ys~~zXJHCb_hdg0T%8$0-OHm0b>^T^@6Appf;eG1%|JT0Ttw(J-<+`I z1LNi$*KL@f{@5J1bMt#m#_2+CjJlJredyVo`0*_xOhtUwO+yoS)lkH4Bw?Ecn?1ZNd)5!7rJQR*XH<1FRTDM0*=QgNjME|NrlZY<&5D;miMr7W7T8v|@~%zRQMD zlh={qj?l(0{}+D!e`vw#=^tzuMe5f;7R7_Kuxxzwf8neDhZd}D{0KEB@x}j+W1eo2 zVVY@{Wp92cKK;L9n&vjeC;yF<7>txTA22g$Fs+!Tv4}_5$W0M6&Uyd82Gg8F8ccJV zz(uYSn+1G!P|Efv9|fD9l(P{e>{X#Rm5 zz{8|2CFS_@zv0j60oII?+q0}0ofvsrAu}~>|NqN=V3?k1%NWZ2^}l-Z8P%`<+dlrE z{BUiR8K{5)bq_&w19Zd*)KLPpKmIU+1{E0?K+6|FB{axJPzl?>0A6#8GV}pTBA_G& zG6&Sm02T0{DG-ntsI&%`=+Ge%&}an6ERZ;e4Kfo{d4NV1VCr)jAZx`z;yXc#p~E8} zHgx@OJ;OevF%gg_KFnP|%WDm?K0$ z3Zdd4HcVUtNgTv>0JZQzuFF7@0I^|%N41QIRnFj5=paKi7#Luo407BAP?r?y2~Zyv z`;swhE@Xafm?%mFpZLF=rb(Fa=H3L5G118L}GLJVUqMbZFb zgSa4rKp4IU11)OG=dbJnw)sbcluE$#;0PSXaKEZVq{=r05!Zp_OdWcKj6$bs~(gI zW-@^zqvr||XW91Ng_JgDUX@{@GCWMlyiC^0ZFfR+=&3<9-<3Q7hbHYmnGTLwUEP*DUMz61FLHhc&2;UB04Aesr;!JE(e4@Pj7KL25wpQUDbP zt>y%+`Ui=F;%+unyahCD3}u5FBs&j64kQ5*1hHW= z*C2%;aZnWnu1!Eg_Y4dSpgDSwI7ke{hN%as1Brv8Q~^|gK-I&BYe8ZlHcWjvXu&K< z1E@{|btYg_?4Z4bAaRfwh|LWh(w_*8V^C2w6^RY%V1U$v#6h_o#0FJqpsEk-O9lpp zZ&39hF%TQ-h@8T?g8B0@DB+_XUZ8*ia1&Aax-1ptSJ>$(QobCVbxyPkmo!~u=#f(!-KfuK5$Q5KxD7%qbqF))C{Kx}TPIBYx^RPAX& z;}}$386dGitAAnU7(>NDVjwom981tBDac|_VgiqNK;z5_ssSVhV#9m`+W7%e531fk zG%U(sON&8bAT}(@=0nW^)vKTy305e9vOB1}nI7lO=%WOh=K(Fn0;vGi8z45QOAE@6 zAa)+R z$T0nlFJso`XS$h8py4x6V1vhFK*bYiody#F1I(r1;TV?f9|9Pq7$zXpYnI0d^sLuKZv>Y2e90M9FJ_Q<%VGR&uV2GLA zzg3y(5i_`hD$4@vpt6RtFfcewe%`Chx<-hBAptxnGnIvbVFfd+kIKd)4B~w7XyPKsDT6W5-4>-X#m&zAL9T3 diff --git a/tools/sdk/lib/libcoap.a b/tools/sdk/lib/libcoap.a index 5832cbbb44374e1e4b061fc3a516bd22283d2bf2..5a05874c2dcfdf2ae8041828f71d797075b9c048 100644 GIT binary patch delta 1280 zcmeA=EZucjdV(~&k%5t+sgc=6C3h|;+i-IM*KA=%i|Gq>8IMh_n<=;XgWOI=CJTni z0!$*C_bbQ=!xT;~;1b{b+jx}=iooHDd-9Ct(;L?^i!d3Of=$_6H}fbHzbQj}d|GK< za(ujssiC3y^z*WelAE*VNU0!c7u&q(z<&v-fYIavF0sw~ZrTLbTQKM)6&LFzm8Pkf znwS|d=oO{rBg5-dWaj4;tC*UYTB6FN9L3ToXod9aAF)6kWN+>G8?=DXH9VQ#Qpwu{N)I+CSg+lvyJReYw02C;}TnL=$aur!2N zWngIuW=ub@mRX$1+z^x$o^OA%j`=N%hq)n=(FPXgNIXMRWJeg9nIOp-SX!d+47V$8 zVa`Z_IcfU@36^!1OlDvQh%$oxF2ZOsy%FR-V>6IzM3{`hVI#t51Q9j>bA_1=ERD9` z3SxQ33etWmf<-pW(g?{eLjwb3o)LErnzoVPkPK#A17( z0_%cqSm=V&9p4&OX;`UYy4~P7tC|3#8ORNG)9r#;Dkj&?l;5s%gEgCx(QLZn308^i z8*Z{1azl+Un?6B;MST1JC#SXg{8qpC3h|e+ro5n0oQC{Mw96abs3LMuA3>h`Ged}MkW)6 z$pTCwoA)co3BwdlF5nX1{M&ey3yQ$uihJ^m#?u?uGK(-77=lgNTsQM56Tcxte0*AI zUUGcAim9QY@$~bujFOwP=SZm_X&2kP=)ivosDRnz0xq%5`)=9<*PAftB^4LzC6%VB zn3|ZHG3XVg<|OJB<)7F z0jV=FN0lk5EJ!U@VKFr^G2ULQ%lMv+(Rg~U38T1 z24t(JZ!lq$;Wss7Kz8Z$+a`?ij3(QEn=n3#M)vXcUlSO`QNm!m-bzM$0TeY|I~j|` zp(5s!3%De<%Uoo9vxdzLoNc$k?Z8E#-c%k2ioS=9s>jX-X&n{F4(QZc!9ru=rD8?4!kj7HNH zPq0dC-*A)FkQ-`*<@5;>EaKb$KVfyXfTbA=WFN?}nX@n&Om}?4DmuMaiH(QRVEZg3 zHf2~)LG|CxV!LcM{m4Q#VHOih3rldcG8uvk8c0YSSj5)MB8!xUK*|syVq$4&yggw# Ho0b&-q3wr& diff --git a/tools/sdk/lib/libcoexist.a b/tools/sdk/lib/libcoexist.a index d960555239df38f65794ca32ccc5b77964ac7c3a..285847d363957b6d491e91843da7cd227bcb8ac4 100644 GIT binary patch delta 79 ycmcaqa;ap344b8~k)eg@Mx_EqNeELx!9W27Af%yzftktX)r|Irc%+$){n-Hnp%EJ3%AHKFfcGPFqklafChsRgZ}1?HhWnn zFLF>2GIL~5SWx0{pu}K9N#mdY4>%Ymr#Swd9O)#mInn736C=}PJJ)zdrpfbMwI}~| z;hB8aMN@!*fq{jAfkBLcfq{vEfkA5WDPHx>CtXb#tuTCo=2N|#%#zfi#2h^gg`1zd z=`adn2v5H4E`>$(x4S)~#bj%b%E>Rp1t#whJ;10wIa5r2GKcsBM$O5UV)BC8Aiu&f zGlTBrQZIc*{>e+d^cjUFU-gP-6q#)5t*wBp6OGFfbS}FfimXFfa%) zNKJ0_mJgI+_{G4$z`?-4um~(F$H2=7;fsR#3Jki8h(HlyP-5_g^0mP7DhyGK5XXQ5 zPLM%k^Hpy?G82XZ#9~H1gn^985H^TpRGKW~>u#$GVlyy+tQTQqVBleZu(_e)AkQ+Y zLDZNqFff4BfW$y-Znen^eD!%z&Aj6~yIupL-W#NznSnuqfq?Lac74LzHgVbxOfHXiOwht-+5(BZh zq2eI7FzQTJ@E2#)nQY;&%*Z==fv+4J$p4H=lNn5@t@78H`yUTTv89>+E|cb zEDQ{_3=9k)0~xg^7X*mcqZkQM33fjV0|Uq!5Sv>EBHju$VIKnn14xKbA0j>hDh?6@ zvALn*Goa#opoxtUYS%2NI4A+ugE%mMfg*+xWC{ZV!#b!UkQj&!bA$ybeAFQpAAza? ziGkSMQ1LTR@h=Pv3^pM3P>at)#X({qHn%ndH`pWxkRqMQ69UC~q1Jog4<01*I_%8x~ZcGz1H(ET|fg7>ErEDsU_tPj(0vmo$dBsR62T z4g(~1L1`cuZWqYwFf*q?Rf5DoY?zrKb6`0U6m}w@@&a18Fd9w15G>AX1X2URjLMV0 z1YfU*ihyht;e>=Bh|LWZ2dPCd6BKlCGeNQp48kDya6$Bf*eH5UA!Kpo zFvaLU`L&5UYbYZF1LI_SQ)R~J$=0UojH#2gqt!JNpd~UWL4ype5n^Ci0nL8=&>#i5 zxO#GRv^rz|BAmM}u<2O%Uq%O`)1R@YpFruu{k149ZEM70Q#>I0LV zW7IWwqp8*rXJGJvx(8IXf@%todu~pi9HXvz1x0K!bn3=Hg0F%Y$wm4N|NMS$2K3{nH4ML_uu z#DL=4tPBhhP&U|pm_mML)THx93R0Pa90Dq*K@J3kj3SzW#%v4>A|Oeqp)m7g(9A24 zhNuIX2dYU}7#JoWwH9S{=VD;cntb0{nYVI-TI0Ak*Cz5oCK delta 2396 zcmbPng0blU;{=&{3v){|a{~nh0|gL3CKVJ+EsQ{d3JMAdTnr2hvJ4DNUDUxgP7DlS ztO#S^q$lf2OK-eCgK_d!CVfemYYhzy3=|aLq?y^~zfAKj6>&S zyhMh9fq|KU!Gr+>G#GRkG$$vrh;HVwUBNQ>gX8DTpPlY7F)B^I;2O`UG}*vSd-HKO z6UNQn9%77>w|c5G8ce?HSvi?cLSV9(7n2uM1sM#- z%na(2`z1st=lDo5@=k8|(PtExyxk|BQE0NbufC!P!*&J+1{MYe1_1^J1|bG9h7$}7 z32ec|$3NUknTk91IK$i@>5X47`jGU0Pti9D@ua#6plsf(%NVulw?W z!c1BYq=}ISA;~BYVS`9Uxyf<JQH_-gn60V;(c;a(z#ziRz#zfEzyM-%L&ZVSz^FR;UVykHG{B0W zDt9n2FeorEFfgi3<_i>;RD+n)gCq+wf>C|4U7)zCIz(0jq#i^tFfc5EsswRCY;KLo zRe{Qk+>_@8Dl^JWJ`||TC_njG;Ou&kFBupZf{0|UfHh+Xke zagZ2@&5gwkV85_1Fo4_uVsnES3=9mdP`&#Y7#Jo6vr1}1jGO=!)?r{^0I|8XC(8wk zdqNGK1(gLQ3lJM-At(kIp$4ymssV|C*f0w%KmnsXxh_~-QW;{`8K}xH3=9l5AX)Xv z>w?7%p>{cdM4)EAfvN>O#T+Etf~oOGcd@3RI);nB#6xo6$i;OYEHHb z5ogo{1^?vA5DB!TGA|@M6dJ`oAXC^ONd?5_hKh$k#X$iHPBu`thC#(aVjwmwT)>G( zV{%-mcsx_Dn`NG9j zQN%&A3=Cj1LB%rz0|O_>9InZ$!izSWM07GUa!uYBEzZb0nbBB%asdnb=7N|EM#le> z1C8Y;2bgj&vQ7?+Q)lF!+-R!KC^~szoVum}v`_)XH^}$~0S1N@43Lt67wTwG>7YIN zW1Kpp{bb2_bxkWYJsN@x3`-axdO)QF$WtIa;gd7t)is0ARG$%IU`Szts1`!9pRJoXRL>D*V3+}Q zH>jwBx%&{~IuL4D28-6sNN?Fn|ge zC>QJ%5W4`X8^i|T`K*wL1F=CE*ejUU87K&813+~#F!XaWFtjmER%k%5t+sgdzSrKvFH#(i~~ra9&e3=B-A91IM~#lqqY4D2k*4b=h+ x3}2NP82EEbD;Sg;K}-gQAdoE6J4OZu<+ja*T1R*oFHSZy*JZr0ImNu82LMKz8k+zB delta 103 zcmaFT&itgEd4e>%p^>SXg@ySMg~TPrbgxym1^rxF)-@W7c(nVF~D&>GKWYu%UU%CYTz6TbR`JmkbG?jWz=`Y8B)NC3V!(!Z;-nZ*@B%vq z9vqnW^C1ReaXmhTd|zKN&=~8GV!>qfIm(;US=5A~8Q5_81ARs@R&zsh1B1!y#nl;~ zY`!kOQ$nu6fRTZLC%3eMfuj+`WMJT(&%nUIyoZT_fun8nIs;h+@r%}pYzzz_%zo9{ zfRlj%ggGv3eiR@sz@Es%z`(@Nv?)=QiMcpGd72#Ss?Fz;r)n`8PFEDv#*^>YsK^!JO8S1~a*us|0vGC&tG#?WPAh_1#ILyd(YLwZ4G zetdC3W?oKyayE!JdG~DD$$w@GnPb>tVTopid})7#LX@z~CK- z%>iaI*t0M&FmglKvp{S<2>UgNEeK(|u`)0)3PacnL2OY7`wxgM4q=D0F)%PnLf9)n zY-tGlB8V-+P!Hw_urn|)%7K{-{UEjiguMgAR)nytIT#oil_6|BP6h@>RS4UVi-Cbr z4Z>aqVrxOzqTCD&j5-ju7l^G3VON6K`VjUp?s^6WMnecklZSzU(HO#>#mvAU1Pzr1 zP&P9I1H&>Xn}>mcVGWcG^7JMs8|3aCP&UYY`=D$M1_p*BP__vJ1H&mO+Y;pe3s8

wqT149#(9nQeO&;ez~ zFfcImLD{to3=ET?Y*5H81+k$Ca|4tOa>Onu8|3?gP&UZ-$DwSH@6UqS^$ZNo3=9mH z!5jt#P_W;GvLhH6816&al?)6FkD=^p1_p+2AT~4?fO3zJASBqiSs55WY>@9oplp!E zGElZH0|SE+lnn}Lje002k%56h56aGDU|=wTvU3?27_6XdknioFY>@8*L2OXiGB7a2 zK-nPQr$N~u-{(WwAV-u#*&yH7LfQ2oS2RO8AV+jU*&s*sL)jolOog&Rj+hB$gB-C2 z#0F&n1_p-hP&UXB2cc|`BThltAV*w+vO$ix!OBq2ASBAb0CL1Vs07FnPoQj&BVIw- zAV++FvO$jc0%e07!Oq6OAOtONgrIDYBV?d#kRw!~Y>*>#p=>))`C|;_fE-~7WrG}H z4`qWK;R!L6P7u3Zl7Rt~{U(4o zl90qW4ax>tHV4Y?XJBAh0A){PU|`q=Vnd74{ZKZjygCYHgL39cC>xYc?||4ckizXb zlnruR{YNMVvy`0hA5O z1y)ctD4jY&*`PAO9m1|>aAII!@P%*~To@P_f}w0r1_p*mC>vyPJd_>Fz`&3SW!Et< zFl0m7O$-bSg-~`o0|P@jls%n+fuR=4p2NVv&s>I_n~Z1=)Quo9Y6`^ zBa{Owh`vMFpt%1FW!HcjOdJdhLW&FwEes3{oKSWT0|Ns;l-&m^=b`Kgps0beXMoCi zD0=~@n1`|#fr@z!Q2DROz_0{V&O;^EFfcG!LfKmw7#QrK>}?DT46ac24h9AWZz%f! z0|P@KlzoDMfgu{oJ_U*op%}`34=VrLKpbejJ`u_W1>I~Y8x(Yl zplndkt%b5d1;`F48x(Sfplmk=28I(*HmK%22W6)+Ffd$!vNISM7;b^t^$ZN4^85jq z!@$rDs$QXNP>{ZXvL`bzFnoftmoYFf{D87SzWfJepJ!lTVBut75K?Afc*MZKzy)P9 zGcqs;K-p}J3=CpWwj3h^gG@b?qr%9*paf;xFfuTxLD_bU3=EbaHmEfLiVi3n6hfX* zHajTSK-nswTmxm>FfcI0L)ng?=zy|8A(Rbe*ZY974U_|_@5`a=0tN<#1}M9Nfq|hD z%3jUDz|aq6gM2&{%D%|Jz%U!izRAGAun@|=$H2g_9LoO4z`(E;%4TF_VA#wFD*sg( z7(l_Y6Dpy|$iT24%C=-=U^oh8gF@molfngRS0|PshJ)e<* zffveN!^prO3}tU&WMGhlvQIHGFvvsMXBZh6RH5uEj0_B#Q1&%O1_m1tyB^wdbq8_O zAdLt=C>vCUM?%@A3=9m(P_`8V149;+4Jt7Uplnc-l|k8{21^Z;-3V$~LD?OkmKBr@ zO5pW*DP)WA}%JySmU|0ub2QV-&Y=N>trQ0qj8&taOgR%=57#J>s*dW({`V>$$ z$kETZLFK<80|TgteG8QU6|tY8Y*5|*6Uqh^8vmhekOiDP3=Bes3=E*MK^V#gRaCN2 zHn`$}vO&>d0%AjZSN2dgGXsMWgC~>&azp@>4RS;nlnwHI43rJ(7bI+-%*~k0$M|RZ zcS%NnMv>|6QjGqLCDW&as4LT-gD8{f=F*J*j0>i>gD9Tq*FjXpbafdFFTKWcqdxFpp&X8Lsn#^a1N)8{KPmNTkM7gu8RXZ$lg9Yk%Iz8yqG zOlMby*Z`swrY{FkEYrV(s29`SRlx3?4x;`{e-5H%OgC3$^k=M@-VUM`Our7Iu1r@~ zWAtatnO+W}woE?`qEe=dt26pD-k6>aqDrQ32T?z!vuiN=GpbAv2T>f`muoQYXJ(u+ zJza;XvdWmIPLnJ%x#sLr@zx;uzE zHa%aDQJsk~dHM%acCqQ}^cV#gEvN4XNxhl=97KJb&acm?&cyI_x`jTY8spXJ@%oJF zj1|+{LDY`v>-8D6paVxnpn)SPCQGBq8^qNZk8D>qV9eLE$pKY&%qs;L7}#>nLCqf? zK?Vl4Vo+tm!@|~(11g3=gGy|TASMF?A4rDT5~QeY`?)yA8+MHB)0fX>T*`CN=@uIU z0|>KS*d8&DQC^BYQ5-a+B(gnV7Jo0}bbmQkkLmey_`{&XOa9aOWm&x@2PCpjZz$l2 z+rDf!qpbUML1rdNMsqMV-TyPc)bxc5*d&-u&5WiW^yZLYHZwAu9{8DGg3$o1gb_R# zCC+SWYB~L35G#mbHvJ*U2otb+CQ}p8Xq7mNsj0Eabj2_H5{yP5jS|eJMn+)%sp zW>Zt}AQwoPfys2i>&)UzCYE4zpkc2X9tkE>lgS(VB$!Q2%pvBQn1H3H|7Bs4o-V-5 zB*|=IY`EQzm8pSG*aCG3$kfEdWcov4Cb@bH33IgZBU2L#wDBWT6H9bmrUoWx7ML2M zjZB%E8k(W2F*2IIicLTe!x5&&7{-}k7-xdvP-C>gG*eSEbSq6PG0d?vjY4ymnE|>Y zGxX6tQ!^uU%gl_>9b{%=H2oL5fHFqtn^{^+PvjIZoSu-x!L$9gD3krRdeDFjXfy%T zO=AO%kAccW&>#10 zv}@c5VnchVCqQgy2a+E&Bqj^$3o|eR)?tH31VwP*gU)p42;?kc07m;tv0*(85kI$)!=dv8&t1?>T5yJSey|=gR2k& z10!gl4CEjX8&n@MFfc3zvCSZAzJb^l5Vof<0|O(diNV0Ya0A4)fruN5FfcHJY7hnn zh65lrs7hmCU{DohU|f9128`RLNg0hQ1?Q|%+gn@yf4ax@9%RNvwsBH%xHe+RAn8m=rFas(M z8i}6=WiJ8s#g;%hpibZ_D0>qF0|R($jg^66J80wqD!!Y6fng7neT;#D;SiJ!>g=6> zvTrajFr0(3--G&JP_{551H&yS+nkYs;Q^Rk&%hAP$iVOn%wb@tWMp7?17*))WMKFN zWiMf5VE6%LgWBN#pzNcJ3=AxwK_ONKhO>+e3|vt5RYnE|Q7HQksLusuKLmBTpzK$S z3=EL5I93LRzl_kaI93J*Rwn3J94i9@9}{#ej+KEyfQf;@0jk-IiGcw$6b>3Nc4cB< z@PUdaGchm(LD?Bh3=9!ab`}!@LmZS{z{J3i0%g~iF)=V?K{-`S3=9QOb}bVFLm8Ca z%*4P@17-IyF)%bi+0&UA7&@TrtxOCIeNgsICI*HnQ1%NZ28LNsHXAbo!vZLqgPDP0 z8F(y?m4ShmnSlX3sK?5{Aj}LM)MI5}kYr|H*ay`h&CI}X1j<%mW?%ph@Ub#5s4_D! zT!4yeGBYq-gR*s*85r(B*#^uE43D5}Q)UK+7f`kjs4e^s%86!XU;q#Bu`)1ZFf%ax zf{K?iGcf#vvRj!M7z9D1RM1jV9Lfe|QCTP(lzWw-Y*68-31y2hFfiyt*`NZ^6vPJg z#X;RMYY>N%fdN#IIYQZ>^28m=wg-(^LD`_}8VqGefcoB0HYmHsL)oD0nhIrun#kEu zHfa2&5XuHMm+QeJg`5lwp!RYtRAK{Y$O_5^^}oQQhMWuxps|*IsQ76H28O9n_H9r< z9Lj#cz`(E+%6`Sbz_1?5e#^kXunWrm%D}*I5W=o!_|Cw~6K|?A~_F+Z_274&`G{{g_DCayQ1A{-5{eTfV63NNH@RX5( zAq6V_ixE2d$jQLK%mf{MN| z7{Ie$^+KEs4E9V63{#;JeoPDuv!Uz+CI*IuP&TMwSq)|9GBGf0g|bVT7#I#f*`PAx zIFwz_#K3SC%5Gv}V7LrrPh?_XxCv!XV`8Xh01r`eGBC_xVqka%mDs?t~yz8%U|Vqjp{3uS{E zKL?>~kO#mck4|v2;fPn!tNDLlv z6kuQgwFAH-jsgq}prI4+h@$`l189;EJmM(8zyO*=kO7Tw2{15B1;K2plpz3KcH-oW&faTkXvy% zB8Uxb!|OoVAj^!QY>;JkP&UXiS122l&;p=r&@5IslnwG&ER;PLHn1qpP|pC0<4mZ; zSLH%fuR)2{=mS%Pzhy!VqjqC0kJ`KC<6n-bSN9-IPjpMBm)D;aZ8}$AjhqO zvO(SY4Nx{{u4fw;Xf8&Qfx#Qpu!Ks0CVLJ**~y@JS`ZuBYqU;xb~NrBk1 zkdA~Zlnt^BJc1|-vCIf64zdh9fGEoVp2Y$WAj&c@fVvVcP&J_T0ca(HkSqg36axc8 z08|_l9bw?HI9Ub;P~1mBB|vcx9!&)G92giFDnR1$kU`>lC>s>Ktxz_|5#3NWs9`b@ z$_80570Lz;w}J-~q20R8AaO;one`0d5ky6Z&kjH(K!zTJvO&e|87Ld%vrAAmXnyVn zlnt5~ya#22EPDcFgFN#B$_8~#euLQ1{v;b{d{4O^>N zL)oAbP#Mb3XJBA31F@kUQ%5Kp6lESzHYl|Gplp!GLZEDr$D->~&plp!OIzen`k9Z1{4RXY6C>!L6g-|xg5zC?MdeG{FwNMVIcG?JK zXMt9afY_iGDFXw;c_!Ln7f?3HWAC7BP-6T7WrGsqFCNfb zj3%TcV&G+95YmJsMiwX=5y}P?MD9>F zC}H|S*>#}uKN!jZ)nMUJ_9ReU4q}7qP*6bxWrHlPfwDmsw?o+=izh~s8`KQH0A+(F z1Fu2ZpkDADDEk6v{SK6Ug@J+L1(Xe%CVK~E-(g^2sQ&`x+-G25_yuJ@1kEb)F)#?} zGBALOUOp%rRP>5K*`V4_3d$B>WMEK$vc*6XiBPsQBLjmDlnt7BG=j1fKr>Mgc0GeW zBLjmQgu`IS$iUzOWqUF*Fa$x_K8y?u5m0szBLhPmlpPLg8AI7oj0_A}P&TMJUjk)= z=Hcp~>@r3Mh88FrG~L$42P*${85pKAGB8YlN`U(Mv!U$uj0_CRpzN)T3=A8f>>Z2@ z4BMdW3ycg5d!TI4eA^)?`vxNe!wD$+79#`0IVk%sBLl+~DEk4Z{eKV2dCbVb@B+$y z$;iO)4$5X^Vqo|JWrM~BenHuwHa`PDB$^bN7#P@~Y;`6E1|BHej){Rm2+DS5VqlPf zvO&#!IeySwj4lI1FcSlV3REJJiGe{2%1&cqU@(BPGnp6|%%JRYCI$u@C>zw~cY?CJ zm>3v5pzK~I1_nPUdo~jTLkN_;kcojI3d&v&YX2udIiPla8kBvQiGd*p%09`&z)%Eb zUt?lmsDQHXFflOHLD{cBgA!2o8&GEk#Dc26T}B3mS}42T2$UtD91}(chAt=@l!Ych*`OZrG$G+QVeR7ZF~ z*`PYYAIb(*PEjCsy%7TgsDqdY;utY7WHT@@q(j-DVbfeF8#Fpv3}vqewT7W=&{TOn zl)Z<6fuR-31}!e?hO$BR#Y89@G&(vR$_9;&*3X4<{)0xkp=?P;28NYTwgw{u!+Izi zG;F#R%64O9VAu_1dowaH9E7q#OCXLz*|m%e3}>P2UeIt3lnqJ;HzDkLhK-={90-Tu zIA}Zv$_6c0cnxKPO2dy(_D@CzhVM`|sAT*LWvehTFfa=-FbEkjFt{)=FmOWIF-!~$ z{7`lt69a=NlnolxlokS&|3(Z9Q<)eT6rmDpnHU(HYh=W%AaB=2c)PH$_5oapuVAy zDFXwjv}%QlgZi4?P&TM{HWA7O^-rcl*`V&jY$zMlieCp}g9iT@7#Ma!*&w?P2!YCf zGf1g-3@QO~)EOunRO(%VvO%jzZ$R0g35|PDHfWW>6DS+Boc0xz4eDOKgR;XIAZxaT zKuseC1_mBs1_ltD88rSc4CR1|UP&k$!JmZ73V$2tz0vvBfJ3`r@#%BnK4Kfh4N(s!ahqU?Az#Ik!P_P$5*_NQ*50q^KnskD)LGAw*C>zv3 z?SisF%U>oy*`OiUX;3z3Da;%w8?=;e5tI$87gp3mIiN*g>!57VkjWM(8&n4Dg0ev? z2@gQo^B5QyjzQU=rF3VYY*1VB0+hWHw161I2DzSrf#DsL4H~=t3T1=3bPT_t9FRIj z5e5b!8_1XsJCqG-&+|grpx_mTvO(*(B%y3j?I#aqgIc|+P&R1!geH^?8Wpnvv7xhL z?joS_-wx6R^Mgu&(m^DY4N3w9Ih}l)adN zfnf)fy_A80;WUU1O0A%!_E0t```rbx>m4B3?*)kC0O@qThq6JH#8)UAR7d=VvO#qO zqbLJ|kOKpFB@;W84eG}8LfN3iC=6wT77a^6*`V@97Rm zFn|_nPJpsOwbL{x`yT@X!yG6Zv~F(^lnt5}SOH~&=J(b?+2Wu^2b2x!gzSQ{%9EvV4}WxFymFua1Y zK{eqAC_9Fcf#DmJ9nZ+X@CV8U)sReL3=Bd}3=El|_CE)d1L~>pLD`_Dl?ap#YFbG_ z*{z_i7L*NIJg5R?cQZ0Dn1k4$yvo49-~?rZa+4>N4JzD1plncXiWUQv|1Jy+pb{|+ zDgnw`xllH!bSs9kK`FTs$_6z+>Y;4VkZUWHeT0F5p&QBubxbEh*`S3o)1hoo<905T z{Sj3DFNSj1L5&V58#KqW9?Di^WMJ3|WrN~uHeYFo1%BQJjH6$c=#kGy=i_WrKXr2W5j&uLzXAj)8$e3d#m8 z=vIKTL93G0plncgT?fj(1)9o-vO$U60?Gz8+wDA{91cbX1{WwB)SdQ%vO%dg0LljK zWebC{ofsJyVxVjnMh1q2?epIK3$s6G!W+n9?>*D|r5WX?-(q3bV0<#2nU&d} zF=Ki#E3-eR#ybWE&DrM8ASO^XXaw| zXN;I045A9AF9uN;rhf)e2GgCnnf)2JOrH#*M5aFmQ8T6+^Dz4}%1mztQ908ugQ$k- z%Dl|S8P`mI%?p;Z=3_2r?3lip5A0lKerC{0xnK}wGkr0L5}E!PM7^2rEWqr~IA{7~ z5alxcF^CeFZY;>`&-i6}Gl;5~ei=l?Ojj0S_Gf%Ey%Ug-jO~X7*>an4S!x zQl@VPQ4!ObMZf_b459+2F9uP6rhf)eBGa8knf)1KrcVY@Z>B#6Q8m+z#lVhe22ncG zFM}wb>B{2F{){2hi$PS&^uyxJ{!9$o+eIXp+gKPEOrI^oT+X;-y09#>KV!r6WLf5N zMvdvWLA(vqwdKGOQZ2^}T4}djj#-&eX8LJ4W_89}(?82Gt24E4onD~FC?-_L&A+Pq16yy?TF*Pn64nmCBbZJYz!7>HZ?W^GgwTG48SYqKr8YIh44~L26Sn%Zk&Cr#o7*3QyM;W8&L> z;W0B`XT2C`vn8nDWME(bZKh)c6`auRXRytgo}kT^pyfxP`8Lp^G0=7&(A*7(4NV82 ztqY)H6%_CDL5stn^EGauHC>?Y3IhW}HHZ!Bt}rk#tOBv+Kn*em28Np;4yf+}+WiAs z;04_yV-8|NXA$Or*r54N1_p+&AU1Sh{}~@*qoz7&u@`h${0)c=9nFpvL@X2&0IlhQ zj`JP{bqHZA#U_CkbwSrK-v_awONl{C=0NLiKt5B4E(8KKnZR2ZSs55W3q8PF7+Dz@ zKx;cJp=v-K3eXl;kX}&t$Q3FM8t?apvNJ&qv_L2a)QAg*vfCIK7-FGp&?r(OlnrWm zg4bw4qp1!g4&9Im-puFfasyR(wMx zK#ln=P&TL)3f||)0jWw3K*d3hI|gNgn#gCMY|xzTB`6!TVB`jr{g{D);U1Lzn}LDh z36w3y$WYJl3d#XhckiHVP-PEVr6>fN0|)gWLF;k2Asq){C>zvLm4vcEK9h&CLGy5` zP&Q~fMH|Wn&2Sh(*`Sa%2ea!L7(n|KY{4AJYJW#48#E~p0%Ai`eiW1qiu(j88#H~N z4P}G+>fj|*{0t1B1m6G^2kn<>gR((u>wBQ=Aka=z@a9Z@1_n@{c?MJ>4m67ZWrLmCb&%gj0u2hFgfZE`CP&R0?zy!($jYe5P*`PMK1C$*KnoxkUL6ZVr zP&R0zPArHGEv%BEY*6&2L)oAXDMJ;A11-f`p=^+%9w-}>(56G#pmCmgP&TMlxdh4v z?TuIkWrG@(8=!1Z_Xxa?QW&xcY!6f%6n%$4Y|wxJXnyom$MaMHJ8??0Q4U`S)HhqG!B|xhgp=?k{gZEtuGcZ^)GBDJG zH(m-eFo5z02s1E%x-X#p@*v9!LEFio;?1C?jZijd3PlOZUJhE?2xV^rt!#v{ zLF0QSP&R0K1iTDN7_!323nE_6@Pmo>MTrhD}g*J`)4O9`J%NVFrd4CI*IM zP>E$s3=9{bY|w1PEhrnb%<&174O-?1-e4)r!0>~Kf#CyG{4Wy&!#5}!w94@hlr785 zz`z7rY9q|R09vWY0cG2Q7Ub|jIZn(B3?fi=ATt94cv+J$149@y1A_uoJdK%wK@G|- zV`gB`fwJ2`8(pC6Y0L}^7EtzFW(Ed3D0>kz1A_~c4LVK03%of~n1NwCGXn#7xsxyh z!wF^vhA^n28_Wz0F;F(>;D#h9`!h2GLk5)1%)-Es2W1PhFff!r*~%;o3{_AzsCI0C zvOz1G!TT|V85nF?80r~%pc1|;3=ET?>>w5fh8a+H5(@*vJSaPzg@IuSlwHokzyMwz zCCtFk&ceX30V+P7g@Iukl)apVfng7ny@rK>;SiL)kp;SeQ@Eai0knG`yn|DifdN#j zf!9q5Gca6Zf$rcGhO8b2Z{QSWVEDkozyMxCB@9^%{0eF)8)#iGhz%O3Wnf@n2d%*o zhg4dEP&TN(5QnlsZ3S7-f>6-5a!`9$11bS3Wb~nIP;b=~$_9u0rbqC4@wO*b<*`Os(AE0bd&G`+=2KDFvK-nM@d(0c_=%ciGcyU3`&xL0aWG(g2X{> zFVJxnP&TM4PlmEVRe2_q4a#Nt+@JwLX$A(+-sNJb1ZZ}l4aA1_RC=InkU^86Y)}&$ z)Y}EEvjQzvnFkfO1`QrV*`T4htspjN!6pL(!)_=WWX?e-TLjepKMv)93_1&CgA4+1 zs+5B)_5v?)g7%PJfz&|PXo0rO2+2d*{NJGBAanje*&uU3GfE&eAP0e0J3)I_pw&+G zLJE))3cTD&0b-CUXwi-W0|Uq)&^{cH8jwNyP;rn!P9Qe4YX)BW1X=^`O~P@X9Ae1_n#efFOA3lOiMvz)PPLA*Voqmp&;%#^@@bnoB|RGEg>X zn7aka2CX#hg0ewlcN3s&(CGr;Z99}>I@N(s6kY%@rM62#S@9Y#V* zkiOi0s5q#lrm)K#TY6Ma;P1Y4O+SE z0cC?6?FVJogE|gNn}zC>zvrt%I^bGgO^WHmGAd8OjC?9?yfa zK_%%5C>sbSE#U{jbcx09w9u7^(;~sB;d=292fOfU=)}I+0NJA5bR} z%4PtK$3xk?j0_APplnb{`VGnkO&0utvO%RP6KF||G6RDYXmdUXlml8n0bcr~%)p?| z$iM(z`lQUj0Gc2GFMU#GU;uSaz)PQ$85lqvRyC+zW7yIsWd;T_Mg|7((kEpG1`9?8 z1`DVf&?JH#lnolgbpf&Kl^Gb^85tP7KpbTT2GBC7P$(NTyAT6q`!O;wq(j-DUQQmA z4Qi@`mp&;oFl2(-^H6cnBtjdMUCqeAFcHe`WMp8N0cC@BHPp|8au$Hb?-j4O-#!5yXZrm;3`|gGxYV&~h17 zhI;VgT|Nj0yq;DR$_CZ<(oi-iVah|xYh>Y;4V8q78*8|0uKC>zujp9E!t z^7;%Y8`Q;{2W5kD#1bfb1E~C81?7NBs0~mysK2)j$_6d;+XH2Tma`v%vO)d86Hqp2 zrr{iv4VrVg0%e2xhqs_?&~)1aC>zvue*#_*rp~|sTIly3Bmo^RV*;(0(S#H};H6BO zkZE%fs5mG{rJ-!ltfd;14H_@fg|b1X0$4!Vp!NRtP&TN8>k4Jx1(pBaP!7nY;AKsk z3=BU&6ZTMX&?cc&C|d}$9R|t<^=b>DY$-+thH@wy)KUU3chZDp-Daq`4kH6YCzK7! zy8U2wJp%)1U|}kl!@vN_X0xGe(1hMXD7%D_fnhn6UB$@2uolV&EqB@sW%n>LFzke~ zXEHJ{9EP$%z2mb`_GZvYB2YHy;EucC1!0;D44{>SkD(Gb85tN}LfN1tPVb>?UM2>H zpHQ|mX!#3hDU2oq184ytFO==T#K0g7WrJE!l2EoU69a=hlwHKcz@Q3c*O$PSHEA+1 zfEM%_LM0|MF))}z+4Gqg7#yMO6-*2a-cUAZ=}aJ$eUyoTAr#6!&cwiw0b+w15TL_& zplnbUt%9;aS+qeARQ_v2ror2w5}}d*`P`ND^ND*FrHgbHfXEd11K9b z+W8F1-path@CM2TO$L5~vQL5z@`18JHQqlc8&sLGfR@YDYcnu_Qa%TWqs_no+CwJ| zVuM;73=9lvP&O#&z$=q5h1@w1 z8@dqmCX@}D+jszFg9goCL)oBK(-vO&FL6(}1tuB-=TgL=mnP&TM{>;z>`0+s(BP!4G2Nf49`3dR^H z8&qV1S1jo>Fo3p77eK{9&8aFV8+3M71C$M#nQnu!L0fFVE0**b7(gL67bFgyo&Jcm5wC>su2Xp8{orq9zZ@ z21N~c)sZn|xV8x@4vLx{C>spF#`iAYL;zR?_fF1 z&v;?_>**~1j1tqWXRv^#pu0iTjOn*Q)RO7iGgIsgs29^ugQ$S%(z96n88=MN z22l^D?*>r<)46A}_%k|8j|Nc%(^rG2JJWxID4XftbHEyAgD8jTujjD%GclZ>ZZns~ zk5OiN_gof##x>J#gD9Kn+Vfca8COiN22mo@PtRjH&e$-0@_d$Z#s|~67qIv<-kBZ^ zqUKCr4WewO{{~SZ)4dn6fX;fE4WbIBzXnk})2$b=fYu3ggQzFdZ-Xd{>Dr4~K!@2> zgQy?VPlG6)>C#JBK!?L*gD8#ZyFrxAbnc}r{){Hmqd}C$^wl70&h+0PN?^M8G8WLZ z_-qixvHkTjmT)FUpXtskS;`qxrteey6_qn zb;geA)*#AxdNPPwF}-^Yi#luY1_p++)BV5lsZ75O5-ym|yp{!JzFUmN($dIu@;Y%1 z#)j?XYgy`)Y;r&;nE4ei=r9`4P$07gALuX|P}#`M!q$)uJK>nE5yWI*;04Jrhkz8d zZ8yBYQfaJw(Gs-P8HCv`Sl#4gU;ttEsjOCOSs55Wn2mk=S!Pxa33e6%&{X)WNr_V@ zPe|h1UN6Ji#0Z)P-zLZU&}90?U{(ocOEZ(njQ!$FmL}k{jhQVC4MBWnO9KdPVF{79 zumGu-WU>IAa4gPfG5z2*W(j5!3p3CZxdgL?5mdPuls1LZ;3Ja7nJvI)B#Sdy7=q5Q zkpR))6PGQZCoWrn54n+GHn%X@ej$W)A~%zf;q>GL)}DH_lUqzI&<|5FvA{Tx*aH2q z7!wOav_of1EHDmFw!k<%*}~MY9(D5F#KH_T#g2SZvxPa@WWI@o1*QnvSuQ3PW@zWV zm{?e%d)3mwkiiu7SZGT_bZwSq7}`uMraKz2N=&y(VijPsWbkoyaYn2Ln110gv+DL~ zNvt;})h`E~(G03KL7P)SY|ywZ0|SFNXc++LOf%39Sr8k#x%ecA4VwLAU|;|phYDI# z3d$&rpydH#AQt3wBu3DooS+R3pxgu+{{>Beg4m!s2XsUmhz(m30Gi}rgbq~cg4Pp2 zhi!I%*r4%Zkb^)6%z!E;kb^*M&>6^}k$2E?0_Xv9ppA~OGny?y%LYLEzd;9}fY_k@ z-wX^4Z$WI(z!U=mgAXt0j2O`H3TQzDXl((gp}+vy8N&z~j%Q$C@CB_c04<{fozV

peDfsCwNc1Zb8AWEp7xSuj)_)QXFQvfqKagz-=gXp43#lnol%$%e8)Lpy~~HfT5pG!+Cg z6toVs7Ag*!Uv7r7JwRPQC>u1-*$-udrjDmV*@=t{470)PdIp9xMh1q3U=9NVXa@{v z9tmUtXvyYUs5ofJ=4L3nl#zj9ACz4V+6M+@gU*uxpZmaV|*f4t&-#7o_U|KI@r_fdSMCbbzV>rDgE>GF%J{^`HT8@BuSikj=&517^4w z7(na4!3WH6F))ByV&DU2xFE|%zz585F))C-5#aM>xEL5fJ0QX5%Wy#&StU@*Kn>t_ z5F1*4^g`L7Tre4YMvMRh18CNMCR746p*A1N1`WzDg|b1pV>Ofw$^{#tY|v;v_@HP3 z1_n?^XfIS8)K&!_8ZE%U0Gb550uqN7T;MejLZHy9XJ7y?f)HY006Fj(R1s*n=?#<( zDl0xg*`UF2@PY^-NJxMeLA;{Ra2xw+r2oiGO zH4ycn$pz3NQjmlQ$VChc;6tNDAo1q{6$iy1_@HPJ1_n@h6$ljvZDiaX zLIl#b1uudSVPF6)2g!u02W8`YC>u2FR9_0^fF`&qp={8mQt*NZXn77^5FrL}9C$&5 z7{qZaLF&aIi3_|4LJZ*5|AyshEUC*o|y}X4Xw?<$GJ#B z925o>2bKAWP&O#aGN5cwl;uI$pilv?Z;)bO$N`oARZs~~N2LME2K7hUplnd@y9>$& zjlzQ$J3y<^6(DgLh$GfR*&s*kg0ex5I0$8f905MUMFtWopd(!BLFaITf(3kriwq=K zz-PF~Fff1|0Y1V-26E2VW2iwOM}QYTKqtFE%LqZIUW4*9c(H>VBx=BG9poTU177PO z$G`yEhXP*fAO|j2>KWufv*>b=MNx(zHnbgJ4rPOCSX(F?RFgVG*`U>8o=`Su+f@jZ z4O-j-J~UbZvRW?@Dh?_qa-eL`aBw-84LT!?fq|hB%z>dMNopwSAkDqQG%>#s0J?yP-0*JjUP8bHG{?#K!*>4X5~OFnLemE zsFytj$_A}tn+0WqO0)$~HfU;T8I%nQ_BBv8XfOo4EVLB4qaWrKY49Lfe|p|?;rC?9`@vOziMCzK7!HUFV(P+7tXnjlw!3?Fbq*&xsG zgV^;dkTC-#5C_`2)rGP_4l;qVK@PHqvOx}VgR(&m0wanN+ZHYghuT6>{vP^}1FilD(z4<3=Z43z+Fo4yNWgF3yBp=?lGzJ#*xFfcH@ zhq6Jtron3wG$3mde?!GVdxya55;P!-EI><3LFYSzx+k)r$#N}7iKzl!5}*Yst@NQ1 zpx`xwvO&RX17(BuMu5+5)`Far6g+Q-)nWrIq(PAD5x(oKP~K@FDKP&TO4TLxu=c2cf|vO$wz zJD_Y(bL|k64cb`;I(elYbXqlN2>3Eo0yK&SK5j*a0a67+#X;w^zlO4}fsWONvOx=A zzC+odQQ5yx_80Iey9^8<^Fgz=;PahzASWyFgC@mw7#P$*OM*qA98l>d4P}Ft1S>+> zj-Vshplr}mP+ce+wCKeU$_@kVumQ25{XKsu8x+*wbD#AfQ4Bu!Sr2j)7X+d`@ye5#X+O$x1ns%bl^iM z8&tYIg|b0itsfvZs09m(4$!2y5hUevLD}^np9w%Ypa2kqvOx>lWuR=(s4Vz+79$1* ze+C8y4X8M%@u>%8gPPbTP&TMzY6WG38Z{13HfWO61pL929Cp={7Ld~GNjG{bKQWrGelHHWfyftC>1LOFXF85o?Q?0t+348BnIIYtJC za47paBLhP$l>M2Jfgusf1|4t;UY7u>>_G?5fW*xpQ3+m`Ui=i4oak&c02E`@#NES0lT!N2eF=Jo=#pOY$8cL=oK>t z22dP>k6tljU;qs=fRA1=V_*QS+yEcFV#dG#T9pSndPT^LfdO=YjS6U@-Hd@D60~R< z$_AadVGUw~#&tmDzax|bDsWt(Y*42s0>lQDFrX9eplpzu6et^1FM!uBSV4Nw;L}sA z7#KjU@@A+SP_5kuWrN0)WvB+p>Q`*`T>c z@DVH43=E(xnal#)-*B?I@iXq3ZY;^>&v{}yq=hqcy1gp9{Pb0lY#NLv(=SW1fu=Q- zrP%yA@9cndHD*q?59X1dK1+&CgHvKBq)MAPy&oj@N{UT`@xXLpX*SRn$Yc;DFnu$K z+A*D3hRvTbVR|r#x-oq*h!U9o8AM%}?kvmZ&sZ^iGKf-`{uo64m~Je`=FiwMy%|KU zn0^^V{h6*T&jy;cDF#sv(+`8Fgz3TxZ2pWc)006|#`Mh~s%JX0BHM9Bndzq$*+4To z(n@UQj3v`2E3tu2=zk2NRHhp%vw=?GZw65&(=UUloaxFcZ2pXUrWdQQ`7<$GoPI=w z&5zM#y09vnKO@WZWDu1yeKUx%n9i&QHZ2%L9hkltL>-y_8ALsq?ySxRnuwYVq7y*?XgGh(tnn>u6r^lp7NbtaVwklB}0`fLJB@e?4k zFQ8)`VOtDA&9&*%nGM*~8JA4g22ttLgF)1t>D2~o>TKNe85r_7rwb@BD>2qgKMj&O zGySsx8*Bo`7<3na7>k*?fiZXj#$|iDA)C0kTmxu$jt{iEki8MaWMJS2^&*&WGcz!- zw{4%}!4@UYb5R3yvM>mJxxk|Rlph=bO z8!Fj8sZDPTVU=JqHwMq9Oy9MD%?vW(VQvIEq+f#B+|XqD#|3QAJ0i^ujHe%5$R@#P z2~pp*kgbK$5G=%GW&)v2O}ED`Vk_k^M<3@mGe@5bFf&IxNZ-WF!e~0@YBu@lR;$^} zqS0l|4bUel%+U{~H!(Lvx7QrwB1&^3)9I&Ivl*+K8>3rcW{N)XVs2u#U3d-K?u7al z(3AtHJOQ1N1lpYl>Pvu53Ot2qr3JR`ut zzyPW?K)X~yYCwl|7DLs54ru`&SI+@ir_l-(2Q?|dqx~EV44|XvXF|n6@}d) zAC!F!H2ts@$^p$?z_vVs7V@8lih~-|SD|cBkb;kv=U`v}O;>pS)K#3 z9S(f5JO={!Y2Jp%99FT>j-~oP)dPoxke6&0Vi60|RK` zrx=tCiW=~hj~omPd9Y*VIT#o~tJBn=Y8pVtP=naeT;l>|gDP%sC>s>)VNfzxOWde;NL(2?a@Qy_2O`G76dC+|?pc5dVia-`9K-nM*)Szro!qkDX zL5?qQ}R z6q`UCQOI#+M?q}REDQq!!v!cCsZ{s&qX&lmogBmKVwfjrs{g*`Njfl2A5i{!$*w2JO>Pg|b1@k=jr;XeTmw zz+N0O(q|482MtZwLfN3>>YX9%dIr$p9N@bn#Tght#bgvn0=ktc70L$rJ_pJM`5t@~ zq$DJG!MhVBA#Laus2Y&(!2|Y^kSLn~6$kl#8k7whXPE<@evo8f0Qr6qR08CC@Tk5d zWcGF)R2<~{El@Vd_uvtJNe1x2{oq5|B^ek%z6bAYl!W;H3{*X6G4LfQ8+7&#_!>z` z1_mxr`F{s00qXO<2eF}hYJNf4ARmKA_@yB?d+~sVnxW?*3q#qUu8bs<4eG?nL)oD0 ztqNs>mQHI!*`QGY&|rVPkTe7Ml0@)mzcgf!6g=85&ARc(h*@QX#E?ii1-1Iw%{oHEs)(4LW#f7nBVe{XGC>gQl~NLD`_Ov@>9KJp%)1 zEc+6e!@vNF*BemwQP36$C>!L%LG_n2xDh}F{{SC?n9dZ5#$_AaU z1iFz8w0j9O5GM>8nua!THgF+g7E2JU=Lp>;{>!1>#N~i_O230~`P&Q~^ zHFy?4k%0lUQw4k#B(y089^r>>o!JahuMF|bPAD5>KKS-WWd`t+_FSy+kP0pgZ=8D8RvQi2JmRVIs*f!&H#`0t3&3kz@z=@kgZbS(SCKv=CDAhp`cb! zG?Wdhnp2@{PzdEi*`R4F@Mc4G$g~yc!X_bg2JpG;-5@pf>X2+U6~s|z0I$!T17(A{ zM9ZOUQ1J=AsZpJQ0aSqOfQo}gdBHa|sxvTvP60j(6$c&WbOp)=oiYjDRH)9t5D42; zsLsFuT5@0i45|pUo#hRb4cgA~3CaewYJNc3U7#iulnol|VgU^`t1~cwcC&zY9;!1i zfOf42K*bM$_Vqy7pvI~?hz)I?gU?ylWRL@2Zf*&c0L8aGlnsh+=k39g?31|}?@WKL z!Vc;no2#;e7BaSjD1qtMK~%?dbv1T>CWeOT6>98$j1|+5tFeRDHHxdVgN7B-LDYlk z+d)*sbaoAPP|r9VMCD9h4x*k+{|=&Jrn_sh`!jBsJ{?4{On(ldDyExjvA<_LGhJPq z-Jj85dO3*ln0_2Y=}Z^bVfSZzFg+baO_{zOM0reS*JTHtcoYtzHcVd*qHLyr2T>=c zyX&!oR-H}Ao9natGqy}`2T^~fUk6bo)71^w{TUs$mm9FVGcz8UzTcP~ z)amCpVJ~O=FumP`-Jelm`gIU>XS%v6yEdc8^k7qVWyYTA<)-ZFj1#BNH)U663W$ev z@9&wi3ov$1e-Dy6JYC$3U7b;8x;=;ro}Lb(zD(~oV^?QeoW;Q4#184rznFd>BvUb+ z-JBhzH!r^3-<*9Rr(6T5VZa9J!m~7jm<$Z;pw<@)XnikB+jc%j_FzVyi=Y`2PzQ{G z<-&BqY#!0+{YN;txA!`+OPD~f3p4=@5s0%I8(LVHfNu<3v;BP;`y5G5F=lq71^?YQ zYfX<3TF4~(Vfx+)?6MqA$qYQw3X2rBKbXMYCdhbba=xzk^twgtPZ(RKCog9I z4_)7x%+J8UnhPpjn5Tf4#h?i-(9uSqi4N$|Mj$2w0}n`s`5;J9+xB@&*qMY_K}*Kj zr!UyXuFAM``mt^7mW(^6ZD*H|-Y?9+z;lI{fk6ed8=et#8W?znm2r;rbmQ&ps-mq9 z3=CW%3=A5KQA|Y)44R+pi#kY4FjPx11A``L z7GQz{#0XH)s|6a+X1olx3{-3~&Urfh%64`?uw7T68p{|MG(jV_6Q-N*V3%d&n;yD@ zJ)C#87z2aiX8{HVMlmM7={t9@Ys!5TWnfS)N-bt!)L{b6fP)61)j>AQc3@!GH*F`o z0^c$R1_pJ|K=?)n28QR;^>(sL*Y5#MWT}H%ZYMyeDvE)e7tJ&=fI%O$eF!A04mwN@ zw4z=KEE&aA!oZ*pTB`*%u7#0-0c4yvM3R*mH2bT;7{dyxnHU)KkAV&Y2iXfcx&oxI z9HtNy#v0R4>|__@0-2-u^v65d)foAvbM0a`)dvOaM~HH!QU(T1&}}y$F;EFvAN)g*U_GcZ8hpbzTxfNcQn2Dvi*;Ujj- z=@a&_bE|>WNE`=U&dtESLY#rYARBa>a4e`u10`M<1=9_7v#ZE1kbs*9>ZXCr zQwPmIUU6Vx2%28Fo81}W3(%w#*baLp_7&6r?`8*$KS}IiSCjOVgqr|&5hzK3RYP3_ zQUi987z4YdBm;xNMbOYq4$MWMDSXB`hSLx3VVBe}lwx3D3^tSyW?(Rvf*XzDxX05O zK?j*7oM#uC?y#4g70sEB(SxGXh2@D#fpA7~*6C|oo_O*n|JBtY}=3=HDe85kHqMu7b$%D}ETeZoF=2}a53 zEBCRh$V$q<4aac)>FI(Mj2hE%Ip1EIT~V5W!2q=8kFf>jbkLLq;~azO6Zf+R%R0!y zO$YVvKrU1VdA7z^*3w z5@9YZNWfVfVg@9Ifz*I?^D(gBlx1Kr5Cx5hO^3M?lm!^)G)zxC$S$eUAP0}nHaWPH zVF98EPHgbR%QpS)L3Va2u$fyyXK~GgnF%VW8Rz&;|96mGO*U2@ZV=3k@Mu$-?s$mZ z*#cBbS;~X5eH0|WFld5e9$HXAg&;8qG7an-9tL*b>3a^bOPKO2FfgcsE@xs~y+(k6 zVLlrJ12{#>E5I#=`2e0>UV$vOHv{#XL6-l6Sk440B0>FUsLdcg#9EM9U~9P<*!ic| z9cGtcd^UahVRkjSX9!y`yti9n`ok0Kw$tkmv9mgY?75_X;z`iTG^kZDPqO>UGcXuL zg6_aP1Pe}3T4tOxV|v^Xc5%5Ginx7MtO&91!Vz{>Ymj~IieURd{?J7C7dt523_xeg zGoFUo1R4@zoZ~fJ;3&JeT$B=Sn^cv+HU+4IMm9h;St=oH0*%E$y#=xv5`rMpz#%Be z!0x5Qz+eyrTC05(W;19HJ>#65>6ebOtI5?Uy_+_b}I+zbs+kkV60|SGY3dqHF(>Ls9XF)6ZEJ3bi zoqpgrJBJk51#dw4=sC;gu3l4nU4? zRD(DkRNsOI7GRDC^?umBrhh!iF3GrjI`=7d4cX=DaC0&8xZ(7Lry$iV>-2<6?5wCs zrU@kLYy+}ynmWWjYzc+kK$d~Q*aWmSfSVB(TA;JE8Rs}oS2)cst>UNwFEiaWFkAx( z8l*CF-f4DrX|SQnptB5x;D&;Bmw|G?fz#|3aygoClQ1Itn+7;N34_km0S6?gKMe{< zcTG@0T1=mRhMh|ZE_ZkNq3#hTnesg;ES$6IEB9OsRpcxcRMvypY1rxkYny3YF z8K}SoO=H7cR?NV_UaawwRuGk)16TRKpz+W?<0Q1G|N( zh(Uufn$eI!9W-wPa-=In0ur>Epz$&^M}k^~#$2H7J85u7g2r_j=SWV!c#+*iPSODG zNLb2*SM$vJAV)g!gB=K~EJE}l4qS7IoeLrZ8jJ)veJNDt?rF6^xIj&%4ZCCGr=vkrtegbZ3JubYWy*sGhEKh24iSV0z^hc1r_LmQFVW zy9iPMGiU}dF)%jvb3LOY14FAZ*pG}34CnlxTX#TyS_2UR`9XaK=o%;o28II&F-_3CX)GjlF;Dbh(_oBdEoR{OFQvg4 z!#okR^@5G%g)svI`(7bvGaD5C%HVv*#lZg7n1R7K2bApY!D9|II?Fic%=E(R>`q!| zOkv5+Tocrwe#!`16RMAqPY#(t0u$8K1bZ0N4g+~u*mQd0eRexxQ1uL!0F9f2BvMQv zp$zKQGU$Uc3RoI669SUn3X!$|`I$izGi&Ypco^q&P2YEmU4l`3`t@7vispwbU=>y-6R5&EDhzG!gCroC z0Mq3n79a=O)`JUTB}WDZBMXq*q8SY|7-N_?|7$SDG8!)Y)7N_vhA4Emrs11k{Y5a{$d z5CasI{-70e>^akA?yyTT&Yo^|huuPUwiWIeDV%SXt_Iq_6adOTmLRW1F>xp` z=z}~2jwz5kK{2%lq(N*t+g*0yh-gO!hO1!3&~V^TU{D9SE5(t4;S*RQiqQ}p0ve1l zjK&P=pkd3ciBbELE-2KRtF15Lk4xwX*Hm5 zj6#I{~o)W zaEUD}n3O()My1v>@lDUT$L;|s;$Z^?OROQ;5!BWM2MnkV1_jJlYfuWYkYHc}UH1(d zcL7U-wzz?$-KKB6&u%%rU_U#nus&${DOeV?J_95>9VF|l3`$sAZ4g0&NLW8X_YI3M zFx;9h{(xP96_hZ3O}BZ#F3k$cyvoyK90XCVvbQoxCoZjV;(7v?Oz~VW=oi9q8gEh7b^SXu9J{ zMuq7Y%=y%}$9-cL=3+dwwTL61k@3*fB93Sd(Cs@+4B{-4855^~4gr{6FT<)meZD4l z)AR+i`E94?&*2Y)uVb?Xtz!cnlD}np4lBoLuF1}6f`V+!jGWpGjLeLj3Sg3Zd!zt| zyT~k`VK|@nb`?twF+nCH=&AZ2AgAgZOc!Kkl3+GA zFa#a8FV19SIsIV}E9mrmQ_vX#AchHyVFX$%C(dMQG=1WAW+_Gk@bUUghL&J?7E?n@ zu+id7h88dpbMOiM;!K8S(+_%cNHUs1wU~l!Wi*_=@C&~r6KL_BAeT6ksp0g63)m!> zO${Mu{j-=F8pDi)9Qr@K#D~M25n|}{!#*4`(=UDImtZmkpHm>tY-#{=y#dS#1{P2g z49ua9GBAgUfKN#fXE8M}GunR2mqUqhx?d;{$MigI9EwqOX%Q zHN^0_p(TccEYTfgguXV?)X2aR?KlQgBlM+^rbZY(Gcq-weqNqKLJ;L72U84hgV1#QO!vAIDz#6bHr z7#J8p;-Co>&{7X>(98tra0jS3sH+az!NLvN&IG!65GoED>H?jn!wp)r0J=sCBF@GD zs&;p5pFEAjS+5>+IuawO=w@JG2nJot0A@6U62WUAK0|Nu7wFq;>X^;feC+9&HL)o`L;!uO0 zfY?wAJ|VHcgV<2@+#(DNpoLE$N6UcNP`yeZHgv_Fnn*nZgD{k12$Fy*vIeoC7JyDQ zVuY#z9b^P!r-IZ#)q}221Kp?qvaCP^5?Y|tQH`Xg6Nxz5+?S5sBRgy7&vGXbzIZ0x?KX zgJzGHg2bUgw*kb4h6?B&FIb}62~{7=#K5o*qz0<~B!~@Fe-6Zkir)mWJ3z~EL5rS1 z9H)UEhz+&u1c(h?hk6F& z0WiCsf#Etx0;=dChz)h=GY}gp{uzn=7sLkTTLuOOCJ6=xMzBE)4BSX;MGzb62rVSG zF%sJb#IA=LP(>#}Y-mWF1F@mvH$ZHt_+1biD*hbA1~rXAM>T@jPz$~y zvDqaV7+{HA0K$eiRT9Dhxq(3m#D*GV3}Qol;16O$EsF%PLCs&#H9nFI44}IiL7Fo_ z;!rh3AU4#Y?6V*?)SP=D zHdOr+5F2XdTO{^>5F4Zh9DsH z1A{P>9R?DIs!0H`p&^k9VnfCAr9kCBRH6h)q7K9c9mc@Gz|ah0Lk;agVlM)*p$=M& z#NL9$-V0(w%{d2RL)Bjau_0#GGu%aR7~X@}P(?qG*o@MMgu?}5Lk*P%v7zeCL2Rhc z96@a8l44hB1_og$I{+jORTBkbcYwklbQ&&*1C_`@VwZu~phd)>>$N~^s6j1A>{%c- z)Der3*lUp3TS087ImbY3sQNSYAP&^ft4QqUAU0Id2PF1SBsP-_0|O(}P+<@os$L$% zhI&R5#D*>})|Fvk5QefXK;k{n^4|%>fu;j@5F4sF5X6Rxhk@8o@dOYXDxL~rL&ft! zY^Zn%hz%951F@mv%^)^ZyjKQP{)3J`2eoEF5>VI8Mq+OSv7tWOg~UFL#6AOJL(RDh zVnfwG2C<=LzCmLD1F^ws>KPc=Wf6%>0EsOLVnYqp04V*7#EP)CGA*pU2}0O5d&aE43}8){G$hz-@y17brRG!4XtE_j|L z$G{*AWiJJZL)EMYv7w>61;mDm?*p-+;)mrxY!gpY-V{x8sY)5q2|bf*iiM#AU4!Y6A&A8WGcx2Rv->k!X3m0NiZ-lB!k#c$K`_9 z&=uH)@(c{ZP<9PS9IB=b#D@B;8^nf+PX)0-_q8xEFw6q6p?Vj~gUWv>XD3Jk>e53< z?9)i>DsAi^g(RU+DuUTP+(vXhOp}y>_8GwMIInF z)CayGHdH(u#DYGVJV0M zHE0`%4b`v*#D*Gr7Q}`|&1Dc9D*gb(hKj!dv7wIp24X|ksQ&`_7|Lcp>i- z&qP3MsAf438#LGpYHowrP|Z3>Y$p&K>QHYab_fzX7Q}{{lLul$)t7+S>d^AP1IhvA zzj+`w)DbH{Y|um`=p05x1_og$dpk%Rs^%bw4fVh=5F09f0mKF^9AIEzxC&xJ_1;5b ze^CUL|4HDtT*U}ANKgggdvOpOYN!Gd+X%#l`q&zY?SjPi z1+k%K#;JhHf2f86kOb5>RUkHKnG5Jf92EuzVJN#3Bo0+G8N`N$#0(G{D!vHBhKer- zv7zD{L2S@0END|Thz&9mRQ~LTaX?uG#D+TP9uoUG68i&)4K;{S6%i`zAU4QQ1_lOc zB(@=l4RwSyhz(lf#lXN|ugbtsFAU{)fh3@cLO^V&4h zY^XzBk=TAn>~IhpYEA}-4OO29VnfYrsz>6?0I{KtSPWu=_JT1mFf3PNU=W6~H-W^V zYW9NIP@f$Fv7zE;L2Rh_B@i1beh0(`4Ky<_FgygYO`+xgD<}t?|I`r)iW7+q+QbCw zyGw(_p$6%I*ifGtf!I)oS|hOoL2Rg+C?s~WI#T(c1CoFmS_@)BH8g|RP(!C9vDbpw zP@nApu|bpcpb=Ei&MqkXI7l3-<`Rev4VCL4Hdwr#f#E5f!@%$!#0DKL$H2hw1;mCL z^cRWE4_aCXb({neTM>z^1!6U}|Mu*D1v5g;~rG5~a)ng#=dFlb@`bT|S? z0;;G8#D==M9K?o-H-Xqt@pcd!Dn1FshKf%Iv7zD%LF{aB1T!oHv7vU=uSen>1+k$n zJ%_};j>LWdVnYr32x3Fke+RLlhB9a}Ffc;dVjwnDjXV-t1HuNCe+&$UAP&?}ClDK| z!2`sG8We-XE&{QkKC1<>K|3WG7#JEg85o42>>iLfRLyh{8yYHeKy0Y^Dos%N59MqD zNq|;YF)%Rf1hJt89YSJX0kNTuyNkqrhQxjkVnfYg&_d)U&~bRM5p!9PIB4+^$p4C3 z3=F~`4(OmSkOb60`XDxFJt?Tk3{nGS+kwQPYCJ(~sL%XBY^a(fBz7@~4OL$SVuL1~ zKoy%7sQia=IzbXpMN>d*sG&1KY^a*GNbG$eHdOsd5F51oh=GCOEXbiy_6?9YRLx@$ z8*1iP5E~+1&+s3_0WG%zP0VXEFfc+j^CGd8L2PKS>madBk=S-1Hq;z{5F4sK6vT#_ znT^D52C;iU;m^Rp&`S-V0(w9drzdeIAK@1H^`! z^Af~{s(%k+L(OE>Wnf^0vSoEaE?s>?KI-bs#oq13Ci(!)6d0YUmy$ z_9YM->gd}@>?cUCCI2C<=r>L9UAk=S-1Hq=mm z5F4sK6vT!)G!BVf0%Ake)arxEe<-I7NunRbh8ns6#D=O_24X`E-H*h6g2eud#FjTe z^!2qsY|wIc1_lN_0|o|R5F1qfSb`*=QQ!h%L*vF1#DkRKq3^8!EmX#D2 z72gSBLoGOq#J-2bevZWc3t~ePGMf>kVFF5j4E#_IsPL5lv7vFP31UMv=!4i$%Pf%C zejqkfO*j%e0g0UnVnfZW0QFvYM6`;4*ibWNk=Vwj zNaeo`NCIksD-zoe#D*Fg4`M^rq=MK`L-UZ>Eg&{jO)nCA8WMXxhz&9ml>at>I8Y7S zKy0X?mq2W2P~QcyL1zJg`tGI-48l(OFnt>tSoPj|Y%FY6bL)Dam*s$@R zDi8;%s2jwFDw+mjgD!XkO`U)Yg0h!_#Gz_7fY{I|*a~7p#rK2Qpp9w_3=Bs=Y^dI| zNbJY;AP&@*Z;;quk=Xx0Y^Xu}7Kl_W3SvVIHAZ6lAhA=C*mX$kc~CYe{V^hz(lg$iTpG-GYHZ7|MPG5{IgJ3t~e<9tUy)1A`EV4HcIGu|bRB85kH8L2RgHT1adM5E~kbo=EH(NbJ2JHq@MJNbJu@Yym6K1|NtgH9_ops0Jqx z2g;5{V&{O^(4|=oAU5dWG6n{QHV_-Cej$hr4XrgGb~wa>4OR>c!cg{ZkT_J$F%TOX z1@)&v9H_)K5F09S8^nf+KLfF$;;%t$sQ6DLHnTMY10(2eXV8hBAU0Hu7!q3%#D%YPFH2kdNn5F4t<1;mCLs1_ogWyPjbRNCK*8K8OvC z<0T+ARD2zX4chGm>VSgS5X}sGkl2?%Y^Y~$Be9<#vEPE&P;>r)*r40!K&g(!j)8#@ zYA7!fTN%WL8mfcDHbr9Ff!I(({XuM~`cM!XYGyGKdlHBZ_1N5c5C?Qe0RscWLOTWq zVJLeINF1tYJBSSpl|3LfRQwbY`wEB++D**Bz;F}9hMMyTiTwk_hB}TBwEc${I{wcE z<$yv$7{rDeqyl0?HE4m@P(zK8*q$IZR80^PI~s|d0%AkWECsQl>Z|QRbPUV+5k2x3DGJp^Jy)jt8Tp&|4E#Dy><$bJjG#jdK;;h)hy#_7 z0I{J(tSpEP71so@q5V2b5F08Uio`BOVmE@=pp8VJq8h}8s_#N#PXw{+p%PO;94LDZ z5_dpQz&H4=Lh5_=mGdoL3EAQJl|61)B^66Y!s`z8|m0TTNO68jAj`vVgDI}-ah z5}U~p(LiN`utDV?0|PIF14@4kf=Fx$B(@9^TN#P1j>OhSVjCl|t&!OFNNhJpQ27rH zb}uA}KqPi35<3Qooq)tnMPg?nu?vydrAX{r7#no-V6zbluWuYWdi5%x{glu; z-xPGRHgrcr1c(jYh)@k;Lsv_KE`ozCLI&N_#t2<{s{^|56T0}c7{rDwxnuyHV+uQ! z8+6PlXmuqh=%YY8re#4{f`NenbTTI+bPd-LkOXvrk~rujZs=Mc@X7JeRWKVt;?PAZ zpFnKr(hN(`SrgEO2R$G*blM(t0TCl~vRVYR;~qMH>}U>cMp z?}0ebVOP){9k9X4d!W7N&~Exv(0*2ESB*`Ofq@a)5eWvdp?!%05F6S={|{nAn`~!5 zo4}#9=X%hl6=*#Hx~;pO5n2lBvoJ7#t~dq7jVY83+5`zc-kTM2ekJ%KP*%wKmEem& zSs}MkfR6eG=>_c>0$&8m3OPJC7HSSCz%rn0P+;Uk*-oG;p%lsiZO5&KvO$BMjZijd zuTwje9mc@G&@V4`0`Iy z28LsxTdbh!L04>jg|b1LQ$RbIL1uzZyJG~O(9O!g@CkI)E$AR?Rt5&pk$1dM_8$hw z)(nsa&{40FP;t;vukuhf=m1<*D4Ug$fk7L}mSJRIFod!}r{|eN*@lb^47N~qJ!tof zJCp-Dr_UG4_F-gT2!^sjhxNrm*`Ql%z(&@D7j@!g=iTcK>w>79@ZLRlFYK&SG7F9>C2U;rJ!2fiSbm4QK&iGcxpK`1K& zgC-LL1NeeaRt5&pMiuY{p{xuHrc4YB;0r=o85nGt7#P48gt9U)_%Sgs9EMs3+Nc7$ z*%;)YP$mY3^HA|9rg{d3t58lV69dC-C_9gdf#D&PUBSe_@EppnVq#!;3uRAaVqo|T zWrNNH{0U`mVq#$U4`uIUVqjne9gfY)z;J+xfq@&!KElMnAO>QC;{Oa21A`)n!^*&L zfr)`Z6Ux5C#K52nW#3|AU~mAjp~bTslnu(FK2SF3w8sD_8&n8_F9?Me;h7+D=moOi z3qrXV7(nXli=h&reSK{pHng0d2xWr~O`QQ{gX$0P1)=;544@lkmO#aQ85kJAXOHtk zE|A&{5{K?7IR<5e9C{YY2AO#S!mbBjU3(wG0iRP3z7$lD0em^aYp6JAr3U!yaX|(K z(CQuVrJ&G?2Yjr!Fara~P!Z6X*1`;+^N<;&plncyt^j2RGcYiyK-r+e(Hwk2H?-Dr z0!ctmTla*rL57Av*`PWj8p;M$8Q_aRMIjDNhl+z1N@YXYph5|Jd^ofw>;#F6LmUb| zGF+U2ffH2z&xT5Xu2%vd6E4oc04g%U$ApVRuD1mr6D|%pjd>GPJ*bs_6vT!u>AwJF zgM#`xlnwI0BPbi>ftOG=$OE9$!0Ux1AwKvDl>qtRCzK8H0qi(%P`w}yI&)f@fdO>L z4)|VAX$H_uN(`XWPe3PqgDOb_s2Upv1_m=I8#K*q17(96!cI{3bWr*40p);hruKuf zLATWgLD`_=z*9kN=)&{@C>!Lnawr>=Fk#1jgW|gxDh{eI!1sO1GBAKnY?}oVhqg18 zg4y+uqny`(Igq&71Z9JQYX_7Ks;c)u*`S*GJctc#q}+nCK@NHdWrG~_9Lfec2z;-n zA_D`ciSQXJ4yp-%f-eYFgt+cMR00$Qte~@~6(Kj1azojm0};WOd@3?9fSQp?AaQ8x z2z0Hw5cHsI6R0@IK~_*U$TJR5HmJ?w24&ZSjtB99azNXM1E6eBA2S)mhBmqKplpz# zrBF7=m(@@<$d`>!HprLlP&UYyy-+qN3MNC@plm!7c0xC32iAP31gOql3T1;fm#&1e zLDzrm0kNU&zT;3fD7Ay{_*92P-xa7h$j7&!Y>2jcKQ0Z0#WrG^46;L*4Aw?aO4caQ!0%e0rx(+BCbpIpxE>Dne85kHqC*cX1 zGBAK{2x0(V=4lEEBJgFNrjX|IevoEU$lVi1p=?lmpN6tQiRdDf4T|sUP&O#OZ$sIj z_kdKu?Y)~+O78O9*prAH| zvO)3c0A+(b>JDXtu8;7AvO(({f}!jJQ28GT<$&7f@lf_E1_p*yC>wNYVJ4IfYHrtn z*r4i>fq|hN$_DwS56T8PXbO}Kiu+kmHt4LIc~CaUV;eziTTuPWz`(E_%zq#iWlDrC>V04i8T zKudCjK*^qgfk7U0W26HlI@F+SP>||C*`Odbg0ex;X#r(}x`=jAHmF+&zJt>Nl7l>; z;-KljXb>CP0ZoIl!54()LOCGIilJu2A+z(}g za>ODK8_8SuTE zZVU{d1}FI5O*aMxP}Tz9yXgk$D}wLcbYoxu9m@v3cN2QL2Ke4hH^_}2)=)D+qjG*A zHpnLo3=EM_HYiObfY|jOkoe99aXcW|uL#NpmGiYwHmGuHhq6I&2|6HC$OGcg*-&v% zyI~QO-3e-vL)oCCH`hVgrx_R+wm{iuL0htSK{+=W7#I#f*`Om1k3rd>yJgNm+225$ z)u3$95r@~HY&O`vo1nx2>iL4iy&$>iE0hg7lH@m(4H_h61lwPDOgog#&d9*f z3uS}4){~)Z(B+~tp={7)81tcQ(1C_aq3i)q(0%UUJ3GA?7&bC8Fo5su^kQHD-R}y%v(t-# z;R7QB1L)4qdXO(cr+tAh?et<`5CHXRp%&;cF))Dd?DS$_a0m5jq2iz;Cs_p`A(sj2 z)k4{z6;Ogub_o*$gE*Ak#KgcL3uU)5F)%1Y*{hfs>KQbloTE$(4Ej*^111IrQz-iv z69a=al+Dk~z~BgFt1>e%xI@{Xl}^4;wjMJBLok$W$jrbH31!azMrH5hxo}0-lGmLG}GLC>xaT??Bn0Lg_h_ z4LXbN9h40^g69jA4H|g*1!aRy7W@ZggHGua6l7o!@&nbs3=9l1P!6b60v$;Vk^q&} zdQfptHEIfFgD$MKhO$9*xg(SfDtz3bY|z|=HY-E z9m;Bu1a$PW4ax>7>V>jF4w?*QgB&yy$_6#P=R?_`@@FZO4Ql7FhO$AW=SCpqy3)28Jjo8&r9KP7Vb*2$ay$pyHq= zS`L&ADoTr>>^Te!3>8o|sOi=WWrJ$JE+`x1`w37sC}B>6uK`{ryVF2C6xCqJy zofEkN$_9;yu7k2c$3$*{vO#y6?SitU7#SE2K-mh63=Bu0Y|vdrpp(vppd;XqK;q$$ zTKA<8sQeFywE4e4B|us6Hh-8=zhg9bFrq3oNW_NOhB1FCkNq3qWT3=E!7HmKt9hqA>P85lyLY|zb1 z(NH$%>gz-(8+0~rI+P6>#s!_C1#&3pcBW#ecrYUaL!~eSLp?|Wbd_~IR3eU%fuR-3 z&Shj^=!UXE71cy28+23CbSS%rk%3_@lnpwlaxs(*s)Uw9+3Oe?7VuBp0%-s>EMGyzLHmq9K-r)|<_nY!8W~|1VPFt~ zPHYH4*`VAc31x%qQUSA_Ax$oAFb6X1W(H-0N;g|58??{B8OjFb0#7I#lnZ>fH`{Z% zi!yGQemaEHpYh9d=}=C8MwRK=ASz_~ZVCbp)`fLytGW|7(S~1-^f)jMrQ#XhznSL8Yy_v2Z$?4CSGQAo^-I;zGM1@S3j^YGe zNtF$vGN$haQ4gkbM|1i!noN%dQER5J22mc8nAM!}Q-E%452BBBwuN$@JNYoc>HKtkd5lavoz`Fnx0pC+Nm&=45cd z1SfNrGiFRb4dOkRE}g>Z&v;~dHi+_=z8gg8Oy^GJ^kDn3K0ILR3 zSEio^Q61BzGeO2mOwY;W^kY0QeRn3OKjWL}+*#lNj|Ne5rmqH3BGZ3^D23_X*DD8(I{uxBMOqb5%RA-u_Fg-wE}+FICiEOl(F4`# z1uBeU({F(k{eYSz4VpzoGKoiRx&p{LtwK%#CIz+W2CsR=g#6JI>8MSA@SazEdUYWu zKa+*p^a~(2HKQpCPy;(-`YDh}DQeR%XfTQiZAVj70aYYb#3{hkqc%MOeB^+dBg1X8PiCPIV^UuIXpWIn@{&rhhKyRA;U22HmzLU%{!&xMR9=1*baW`RUmeoa#)j zTOfDht*YP@U~1R`x$<5KbR03ra46m}{V_<(h3VXtoa#&h+oqdTa;h<2nI2uqsm}J| z1OtNw|MY;be9F^TS8}Q|3QWIT$*F~Wot@ZrsVYuxUBevE;4(Al_FSG~P^*iVg{NT- z3j+iA=6jw-5R-vH03^fwl97Rdr)_)Ka?Xn~JQoc&Ff%ZKFwceU#z#1Fe5QX{$R;^` z|3Wq?M(~-p64TWdu}L!;Pv02KD#2`KY68Bdp3xM{XEHN_(uUw0?U~Jtj3+bpi!+&8 zfR6N)03GT3Fo;!R`g=hx>FIj}xuhA5K=O>HpaXd&nM}dw@k%lo8-hfcObtLs=}Ivg zZ|@W0V&i2pG@8C~I;X_s3$yr`O%2VbH%{l2oPI-|OMuaG`b&8(RYr^Hh95aarvH=Y z;+r0+z$H9=KMxoCbZ-SN0VY$1=@)sp#HW`ia9J^0Okc0SAXr@0*t2H<&?OzkHZr{z)LQv>4!e^YA~j3 zpZtKd`wkB73{FP&?TSL&f5h0GxEL6i7+AIk%;N85#60+UA?QHplXT zbhy=W>jjaP0BL~O&^cz%@(o5%kClOeVHHT68)WDO)!31UO1 zk3pAv!zv=1utZQhDshtoDY1xS*`RK&C5X)jiZF(H24^S-WPvA?4QitM zL)oBY5ej94d=?F5gQ6)B$_81S4rPOec){1&^D!`hrv3_{;-IK(0kNTpv63{E_A4A!owDuCp26cwO_uUIJFn|Wvze2@9!TTG^23f`kT{r=< zj2+4b4Fm8(*`Sl=grV$u&;P>@6fD(2Nlnn})A}AXa9TiYE z=q&m=C>xYhTA*xD+;>6Qpy-$YWrLz)8k7y%m@x;+P6Cxbi=Z6Pus?Vqix2|?Xd-hR zR2-B$wm{jS?79oe2HkRa0Lli19C)#d5Ca2fK;#Tm95l{+3Cadd8GskQ2tf|yz6TPo z7h+)8!N9=q1jG@7tRs5`WrJ>)_yA>t#uL6l*`RTyUr;vaRv7Ri7*L)BEf)i=-hi%S z0ksZU-BtAOO8;-EvrRiSK9h}LUEIiMglgt9?P`OKkgEd~Y#TPPcJnzu8Q4NCd$ zP&R1HG77{N1LtXm1SlJnrPH8n&??g$C>vBt7D3qc44|R@3J8Y*l+D1aX2cl4L;WpK zaZt(F1!aRA)CXmQ&K+L}VuQQ_I==?W23foo$_C}2%}_RI`d}xN4O%3%AG`!eoB^~a zo&mg?Mx22GG*omNst9yY+eIiFG-3u`StHKC0GjH(3l#?q3qFRjL4#i4RW{-b44_;C zT4f_7&cFaVM;*M#Mx22Gbl>)GsQM3}1O-|d3sMBS<((b03`CrP0krgw8_NFAz`y`r zaRXiIqXH6_gyb46C>xY(z^iX085lsh2E6)4l7RtK@qky~NHTy!8oc^Ol7RtKd4d+- zfR_M)idFFH8%YKR(7KiosG*?B1GH2Zv`h$;g%Y6RaiHCqP&Q~xF$c;9)g47pHYi6_ zK-tqkM}R=tpfTzeD0?$#2)YZ(0R`OzC>u12It|JO&BDxqvO&koFM_f`b5kpzY|sMA zbx<~FZfXmZEdm;Qg0i(hLxfPa6(a+~F)+KHfx(86f#D38!@%Il$iQ$3%8q1YV7LKg zgBCvCgR(Oi85o{G*`Pa!UqRWej0_APpzKME3=H3(Y|sqOA1E8NAd(5xHjrds0Nswv zQ4i%@U}Rw6gR&nmGBAih*^d|*7^I-=_lyh-3Q+ccMg|5oD4U0gfk6k#=3`=DFoLqB znHU%>plod>1_nDQ+k%OK!3D~$w_;*o@Pcwc(>&lMK#~j$;YwN5 zN)nV^$i%>q0cH0vF))Ca2}v?A^fNIqlt9I2GBGezLD^fG7#JF$Y|w(pHt-T4Nd|^P zObiS?Pzlh2$VpK4IVJ{%8Bq2WCI*IiQ1(qG28Jb2HfXwN6_ovyiGg7Ql>Lf{fnghz z{f>!&VHcGBfr)|PEQk#%Y(VAzWhe(!XxxOdK?T`;C>vDxJchE(7#JA7f!NT7=r1T6 zq?Z@8js=vjK*cbW4HB1xvOx_hc_7PLq&vfSv+@MS4Cxa-J>5n&XA7`|g zzIr3KKcmO=-ykYvy7wk-f5th}XM?Ce(_e$Afa%tox&0YuOz#F!Cev?&D39sdTev|( zjMX42V)|(iwP3pRR&IYro9WpgDq{L>5LGapdmGqE(c8F>GwztKyqz0#iGA^Q?sCSK z>90Y&AJeUOfCamEaBDNVP2awQTbYq%`t2Ru>Wm+!Gw1_nKUp_r+C$|8j>h$WJ-0F-QrY{CjOQ)aS$*s;?u!n)+3o8QyXgyry^!M`2(rh#1 z85oLL!ME4*@}x2_IIu!iA=pf}S74TA^qHQ$iyPKUHw9ffFUD$OXl`LJdA+zg%JGH+)LEO#yghIhe+d)pa-P)fv)^*d$w*ijG3XWL zrzDmn>cz*WmF6YK$E%nc7?@1I$jKwZXg>V{Cyy8-m?z3;xLufwX9*jl$@CopJVs0w zM$_L2@JyC71NCE}T1_m?Oc>w>nOK?|Y@aL06Khbv2y`JKsKw2|z~Bt(-GORM1_lPu zQgvAG&JEPN1GOC(7#Kj!PDW4y2Hn>I>fM3r7|^NJkRBa4nD>F$pqib5f#E-h4b3ll zp#2@734PGQ5M~AjAy5ktq+>IL!vM-KJE3gQ@X&rJ8&tm?g|b2RorbbOnfM}<4KnvS zlnq)O0Gg8(Vq*ZE5ytQsDh}#3yo9nrOTXTO7GZ%DfpYd&sDus3_fR&dAHxXh_pmWA zfR;hAL)oCt6fczR56baSHmH9i31x#;B7nBofXoNgnc7fs(1d~^lwApG0hmKMAU1f< z1sekcXim-#Bo2*^5GWfILQzmQD1;KAY*6fEL)oC%DT1;=m3sx04Vqf1gR()5wia*? zkduJ{v_7f}DgjzII|0fDO`}YMvOzP@;C&XHkmZcaq2i!+^F}BebcXyMC>!LNV^B6| zQt<+m4Z0ib7L>gZ)B<<{<$x}&d=F)V_E~&}vez*%Fo3(8kS-$w52&xh2WkI+7WE79 zK_>JhpyHskq6}q&LP8J91{LZiP&TNXwgR*3AqA}+n8UyTiq}988x)=l3=H8=HYnJ^ z+aLrWqmtll5CRMgAj`npAOs-2NANZX0Z0Q2ybVHtfdP~ltD)wAmR>eO*`O$B2loI4 zAhS=sPzg}Kbvl#{>bEY0vO!DNmP6T~#JCp9_5f{lfwDm!*a>BWCW67;O##RvL!A_p#lsHplMEUH&lRu0W`r6?uH6LMhn2(AOsk|`)xpr?}b3& z42mXbw*(YgJWw_${ep4;NDZjvF98(?Wn(!|{s&2b8t@uW2~aED2+9TpoduK)DnRX^ zY*3vEy2KNt7t}5Bf{KH>CE#rkLJSO`HDO^;aZn!_*7XF1N-jtoQpZY)}#bZ

XU;t&a=}>V{8+tC34eFjQhO$AcVpl@h zpswnA5W8LkvNC)th$8|iWWakUL?DR~+^rO0U;q^?;5`%~3=B~W3=Ef{>Orl6n@~1r ziWIz^LWF?<6qVrZ6e5u518=7gVPF8As{IkF9(0jOJ!m5z$d_#l3=Dsv5}+jz%%DDs z2m=FXgn$#u2DRk*q3rpf)e2Dd63{`gP&O#*Dni+y^_%KYHt2F+T__vW*f)l->%pBP zO9+SI6zH^AC>u0a?h0jJV_;zLhO$Ac)dHdH$Dk|BW1(zNk02S!{>8w+kO^gj zwo&Cn*`S_6F}MdP!oUDp#?}Us0F@G;xX*!Fx2sAkn%FDh|rVCqZmzt#}2>2Gu_dx1k(RPyHd34Jx6YL)oB2^cKnn^;swptZhGHfS(r zFPI$-8FV=e<}fgT23<}<*`QPk-s~X@>CIn-ih~ASZbR9iL<-*cASK zl`XHgJA3nNW@D_F{ymV#pK-->_aGinTYWl+(wY7oM7c~i59R?)p0|UjJ=3p)D3$^&Y^vxo8cGZst_2T?rJmxHJ$)4zkLp6Tx4JpPPZ zrcVb^7So@Ds6EroBY6B7O}4j3@USy6T1@Yc;sLeU??>^JGjdE1kLK}b44J+hLtc8W7$;8O50W}L{W*x5GMzt` zN1ah}x;cpAnI0d@qt5oyn}J~y3%JqDIA{8Lkj$Ow*JF858p`4zxH1+6Fq)l#5xAGD$n#0HhopjCt*HfV90DO5dZb(uSe%>k-C7#J9W zARJIl$Pfu-gA9s?vOxx=LfN2lJQKN0SXm`|fEx#!QSg)8EhF0j-a*pUDI2 zDfWY?8`JO4GHFA{28ZA&j(Q-rthE4^PbUX`uaIMpnmHAIXvZz zTc(%K=w@g0|k|~+~eLjyCn~{N$ zp{ddI`}&OHEEZ-Krjyr+YcOVP&tAY&rwHu~%1AIUuoZ9rdXVR~4I}&Zi~o3f_}M`# zO_>-BKr?vP89~!^VUq(A*{3%Y@OXoIh|}a)S8eYR*^@WrLd0Q(<$CpvKp1s066`0{5-hA=MYS zZ^h2Q0BU2cg{lEf6KsaEcQG(9?1i#HHP#6z8`Q=+4`qX9YOX@rpe2a6q3kE1j@d&f z=OqIJ!*eM6F9QR^TPPc}pc35wVrO75XJlab2^9}vWMKFYWoI%nFffBU4(tpJ<%|pr zVjwm&`edMNP)P=!2IPV?uQgafEe29ym7 zp?Od?Xi$3zlnvU3xC+V!P3>%evO&$?ZBX_y(5fjYdoAcjXDA!AN*FXTF2q&OzyNAl zfcsor3=E*b?t4&0pgDslP&R1J;1!e&Y8HQhvafxEfk6$*22J1TK-toa3=H7D7#9PB4kH5t zxG%=Vz!1d9zyR)xaY0T30QbeX7#KZ_ z2kmu;fm+bc$iR>UW%n{NFl0d4{frC@c~JHgMh1owD0>q+@NeJ76t|%DBFsKfguRWj$~nAh=8&SSQr@MpzMjD z5vLR=X9EiZLl%^Mn1z9%0Llg(wowLUzhGftsDZLU>kpcsY(7>7h7KrOft7&)JSE7* zz@W~`z%T_WuEom0Fbm4IVP#+d_uaS{>KQ--JmAh77Xt%mAP3xe<6>X{4cLG?Z(Ixv zJ**52JD{5TSs55WLzxhM=qn%KzYbLy#}o7#P6whM*k5#=roc zH{@bq08MOz=MA|S7(f%);CVwX28OF_3=FFo5Qo!P9_T z3=AIZ3=H6DKrRLbP$wTe4G1cH*clkW(|}wI44^|6z|(+S3=E*?1y2KlTDa^C47;G_ z?_g)BXE*@moM2~w%mZ>UFx+5=P6Ki=F#KSLP6Kj5f*Cvw$i={*&B4F`o(AM%U~u7p zP6Ki=Fo3$h;AucE28I+4=rkY~14AwcbQ%y;8gei&fTsaL2 zLfPQj5$GB6Y~GB9X>^1l!-149KP z1A{SC5vald&#v(@Ff0cxSb>Uz>WDxndpjcoLj;t)hmnCH4$6MU$iR>SWrOO7EGQdP zN0dU@tV|3HHBdGesQhn&azInG9ZafU6~jdc0k!-ptEnF>3w?K-1*}Iq+7$l%zudxB+E@j;Xo_WrJ4nJ%O@8P4-t%wg4*w!v`o^6Vw#`2Ic6pGBEssvO&|DOrX8$ zybKH>tPBhsPyl-`ZAOa8Z^8KX4f+?fcj(i!5jt#P-*xS$_5Qv zzl5?u8?OI=*wC|%*g^Z*g&`eQJ}4XH0ZAwud^wa2>R{AC*`UpOolrKY zvoQh6293MVhO+BHW%yDkM~{(#VGWdR4BGb$WydlyFdT%klNcEoPD9yQpcOh$HmK8i z1Ih*!;h?khKpq1X+fSh4>lqmsUP0MAK`V4X`5&a{7-)$ORN@LFWFa$1{0Soi0|#iY zx-bL7E6}POC>ykCS_I1e1zME@WwS9cFn~`85N2Qit-jHRii3)FGbkIhm)Zu()&rIQ zPEZbLGqnel4Jwks#{~#8Fo2F73xSGHVPas2g0exYX~0JZ2s1E%7R01M#koKw9h42) zCk;MDK$wBS160sK#X;Mf>p*PKZodXlNeAKxGcdF;Gca^O+3m~>4B#ULpu;N5K;qE# zglnN}P@>xbWrGskekdE1=uSb|pqZ#EP&Q~R|2C8j8o#f92IVXS4LCsAphm=JC>zwn z{Rw5?1+5@}vY#?AFmQpkp^HLR(TPIYpmu`-lnq)qrw(O<5}huT%?PUQA?$hvPDTa> za|nll8`NV3v7v)Up-?txd@2UY1`P+LL)jo77ed*fvrQ_XY|ui1W+)r9TNHdMfH>q} zo+(gq&`idB@Ua8p3=E*1+bf|Gpf!XWplr}I#cn7YR8Aa)vM)0*Fr0z1K|8uHLD`@a z0B=CqplMt&G9D-!)PNL*vO)1J31x$3 zndG5t(4>wklnt7J25;tJUGd%50nj>2u_2t)j)+0lnn~@A}AYFR98URAP3cKKYWMRo15{d18aSG=I*PW`WV-!mpmuYb)8+LQSGHLpLT zz;yRFy#9EA)TKhxbm^7=FWm_Gd@uQp@j^ur%{l^H#zKmW+9&NyW{|0iB` zrjq%PVQ9ZkyaJ5tr^kQdRcCxYy&Xh#OkWS8^rv43QD3J2|HP}#ws;i-gCumaWzTf~ z&%El4d#0Cv=0zEXW;HW2FtPwowyeSki_JgK50e^@RlMbV{N25=k%`gB39wgEtmQf;SyW zFd3R{=S$+-%E4$h{YVy{QoWH8>e#l4F~&w8V`H?jZ4+Y?&>||gP(SAoPk+Docoh?4 z6Z8#3#-`|deT*@7_86O)V;F6Y;UIGhbSGL^O#VAt*%RGL6GL>pCWaVlFg$ExWIlaj z4xjLJ{Ww0h>B=uTg{JF^G4V~m@R(V3ds+^kPhvf2@(Z+s05n0i5HxWH9ns|m4b(%Y zg|a|w=xQ9$Ff=15H#0CWfSQ@GrD3446h_dTF#`j`EzrO|bYk5ev}6oA2|feF1`Vh) zFff3Y7%<8}2j}xZYsNrD0Z0P0W(-smFfcGI0kJ`o)eH;_pi}P{LBqlfkd>#5pdx~S zfnhyp<^Z%lgn@zK1BeY;G0woi0Gqu7dCUPcf5irAOMz$dKw~Qmpou)th9EY`zHsnN z9vh^eoC4JV+Fy|kWrJ2;fVvx?=|Ru}r*fz`sAUKmQv-=_WME)uhKg?k9Y_ylg9dv0 zp=?l&n+j!L01Z8Z`YIsJppy_m-4oET6Uf!uK#HK}c1RB{qX9U?>~ZR0Z{UKx#nC z*u_9I0nju7>i>YI4MC+mXd@Yj4RRcK9~KWJL_s5jAaRi69H4qZj&p;ub3u)BA1DVj zCjy?B;bC9^?eUL*ice->V2FdVL3=Hdplr~9Jor3eXu@m&i9?r(fzJ?zE)xT9x8j31 zXeLw*$U*bL?0U%3&ZS@utp_>3?eHv)%oR9#-;x`~O1t4kb6O;`agZWVp<$!je{DZPVD{xpqqx=GpL#Q~Q zY|wxVc)t~>0%c%e0PnGaZl}=&sS$!$YyoA1(uX~i4e~K~ZbgWJ0kkCsG$aaIOjQqB z<_BK%CIp#^0xx!HcR6SVxY6g>KPa~K?Cn%3=E)V20xSy>O_e` z*`Q4!(oi<&JP1W78`PXthqAYW3MeQWG!bVEWrLQBfVWJEL6(bv=SrZZVJJvVy#yrT zfJSeHK=Z?(Yc@d=5|D%go)eLPBpmRZhy()zDB*zTL?j?Pm%wu(5)2HW{0*KHk$|k? z0?&y^K++I+Ym@|JP!GI54O$G>gSS0NK^y^IlO_d8M4%C2At{I>j)NQ|1#tvubQmNK zT1E(7hb9F{P~dfFQjo(+!RyeZAX}rr>(Hbir)PuLp-C|?>}6nJ053z6VyI^TZFK?- z6@v^t$-uzC2pS8QVqgHBUIsqn7qoH-w4?weE(39>8k7x+SMV+-8HhtIpyHs!1sY8j zl7TqR3n~suTLDluC~bv-2j^uVsXYcN0ZLp+P&O!WfwwftKvH`pNE}*Gfp;s(K^)W# z6$d#8ynIX!;-I-uagc++NBqh$Fn~gCJybjaRQ_*;azF*nZYUeHdgCCJJ&A#V;W(5H zI&|hNlnp8mE<@R%9>q;48?>LWX7a7GRiH{f+;a*zd4 zf1!%@gQ5d8b}k3;y$Fa6t(xVbY*1bYtt%5!fTSBks5mIETR_<$-#bIuAm4jI*$JTX zKLE-BmHA;%HYg-OgX|zfLDg##R2)?PXF%DYNm%fDGX;nTKvNAM^$!^s7^njY9N*+4T$zpp(!ifjJBe*`O&yC>u0A37&#bU|^Wa$iT23Bo1wifTtIf zAaQ>XDh`T!@Wvt~NZenBii3O)8pIb;g2eq(s5q$5dksDlSP4?&eS}JYeEA*92CV}4 z3uPZ>U|?VdjfE>QFn|&!CzO4ifq?;hRg4odJS__m7N;lo$4MA!U3&2wiY7h&iLluG6sn3P7K?^GuL)oAMD3?Ro zprHrwW*=x9@F+-J1LA=*P&O!Pu0z?Ngn19jHepC+V0Z%MfKuiQC>ykL<2Q&6ZA`L( z#=o^7hJvRZv>=X_fQo|*1#kAzf|Qcr%|2R?_}1M1{|28n7h}Y9?ZCdIeKm-xnf@C@*-ZC-#s@kqXf}wN zG5s}&DwuBloX?-pV0t%*S~2}Lh*FrY{elm)F{kDe#&KK{){5iyFt`~>9;{t z%yjLye4y<*)gVe{`e_h#VY>7?uwXWbD%rmK9iKZhW6E^qPki95MryqQiOl@*Ni&$99g%}t(azP8*S+YRPVo+azmxZID3Dz&? zXaq4~{qj{HMQz&;=<)yX=DBDM%G@B#abfzADttGn<;3Pk$K13Sod(v6-5g!bHG*eUKFR^biok z2-N!*XEHULKJhxUB$Jr|)D%I$n?lYd5ob0vg_&<^HvOPChXk{! z8N~gJreL#JOifJ(O0mhCU`@YG#UI0s1OIQ!@;=o1veh zVrpiAZjQO3xd)p6%+UvFOwG;EooH?j+W&?$kYj3YVK{vqhk&A~xh2}Li>ZYnDCD8* z7fme;(Y0C_T23!WVpZEN!6|T#dwP(ffGG!Pg%<+@gT;1bQGs}6Mv>{w76R6cD%1B{ z2#7OkOuud+pf3r^^`Ie3ZqQ%=0|NtSCyvNu1_p!a@|FUi(J^yN0e41=?e&%d(HrUw zK;tZ+foRZi*B~}%?Ja0c8Hf$-cZ-6?R-k8En1hBppq;@k5F6SL+Ye$xyFj3!J4R@a zqZxFL3bf&W3dDvstwFQ3jB?Pim?qGnSP`j*1~VSPEi;b{H`*FkBO7U|DJaW`kA z6axbzXcaXB0|R*LA2hl_*Dck9cDI4rMX>vpKr?}``<6ga1-owv6eHjv5mp8UP{?P3 z1`b#mz-z?8N7JxEc0<9gSOTri1`jlVuF7FxU;qz^K+_iZ1R4%-%ch#6&HvN+Bdijss_}r+685UrhmXk&_EOH4Ujl=P5FH&8`K^H z505|xie7`o>me=5k6;dD2itcj8#F8X7s>`*`UGBw%EQ0_+PK6C>e%x@YJTulN<0h< zpe_?=nV1kXr+|k__`$wp&;hCEhivOJg0ev&Z2_7n2WbH17V!Q+e#pK)7pNjorT~wj z@G~%gG6HygDnA1QD8Yl*r}9Gv5n`a~-9bBMp={97{|qP_)bKBcvO%raDk!@iv=RqA zp282=!v$Wq$`9GY1zMj5avbR7TJYEkKcv$DUc<@{8KDBNVdaN(^16zz+*A|kex4}1#KWjpmnI=u@!y>2GAT7XciwNew%@T z0kqH!#C`xe&ID=@XnPiDb{`}T+MWd-f8l3f0G%8ITK@(T2hDkdX8l3z@1RqnK!XeX zpd&Eq85lUA9MFs%XgL5#5g+J$1gN+KXeJiQ22FB-mI;8=fDVBLuV>|FU{D2Jg#}du zntHZ|vh^7m7@VMN&`nq#P_{KA1A`xkUC+9gBG-Ihq6~PGBE6evO$yHN1*Jjj0_B?pzOVj3=9{b?6Zsv4A-FS z7mN%Hcc5(08m31Oc0IWH_yWQK-^cY1%9aH!2ZFLynIOyjK*0{0=mwA1@G~%2g65Dw z0|)#J3^q&*4B%sG_!$^L3uA?$;+{+l4B%sG_!$^LYn8yq)bKMffUe_G1&_smQa%#{ z1NfL4eg=k0CI$xZ01rQ?tIEItKBk7BfuWNLdQ1&J0|RIwEqJhppMe2%PZy|*0CLKLbM+GXn#7pa>L-%nS_Rfg(`IF*7iL2Z}(U#mv9}9w_1mFPN%l z0FM;$GcYV*W?*;?b;M$31_sbb5hxfpGBYrM2Z}&J$IQS09w_2xU;u5&X9kT@@G~$x zU}j+8gtA{SGcfQ&*&mo07{Hqp`572MGY`^GaaI-v21PKto`Hdfg@HjG%wb^QXJKH_ zg|a~>y%|H?L)mj#7#P628u=L*KobVwU5)$< z44?@E@TNvkam&KM0N&Kd&%gkx9l@I#L7~OMzyRLV$j`uViiLpzys43&f#C`Z0|R(d zBPfA`7D9t}HS#ksfT~CEu1061m z5C~dM3W_q&!~l3xBR>O!0V@LocvB;&pkrlV0B>sKXJ7zTWDh}`+dvvXyDPxE8bKu; zD+2@gIxBt#22d>pzRn8dQqbLfP|G@485meVLnZtS485!j4B#8A_!$^Lm6RY<9CXGS z=zdR-`Ji*vWTE1q&Fv~s_FC3@1_o^?XA|h+KPVeiV>yA?(3Y+*lnrVrg+SS$21PuS z4QgA0N1uckz?aPBK*d2bPvAALLXdf$3aB_}u(1xr1|7}?n&@c)afBcfJySt!XtR0& zlnt^NJo*IMN6f&$uofx~vUoF;4Qg9%hq6I!%TpjWv`Kyy$_ANp2g(L{p#C|O12X6x zlnrVGe}S?=Ltx+|XvDx9Tfj$sfu=V=`&z&wRALMapl#hepiwC?$XGmR?hd2|G$;%n ztrCOWSSbfp13I5w3Bs;txB!|r1#v)4AO;2o2PhllQgu0Z7Y}8F z8po+nHmE_I4P}EG#D!2cXjf%9lnokss|GEU22Fv0nn!&g3209Ryf79zLjhhG3!R}@ z22}%c#2P3Y)V$vWWrIQsyhv6Ga)`k`s5s~_uR~Ba=rXdaAU3FZ4Ql^CfO0@S2Az8h znn3{h_$^c%WZ7pZ8+2^LPbeE?@qZ{AbZi4FHv1# z3YCpeHpoGsQ=36!^q}VaUZ^-|sP!P2UC+P(x`prxhy&{4fckq-HpsGPP&UZ2k5D$q z_rIZRQ1=hKo>d8S*$;F*s}kf&MPbmwN+n1-kc6_^85kJAw_GVfa*AF(R0326fUmhy zVqgGm@3M!AgEo=7LfN2`4*a2P(BxkflnvUcmjY#jX0!63Y|zTCA}AZQva1!u26ZAB z7#Jo%*`SRY4AY?;&@|;DC>yj7cqNn#T6MPt$_5RCgU*u%jopI|nE|g)Re|(`!0S_0 z7#Kj)-0=)Y?pu-teAZ>N<`cxGL2GG3>uc4NK zwvT~!V}dMGXJlXiUwNg%z+k}0!0;QY#t1Zw30h#)WKt5 zU|0xcgA7^$WrGsqIw%|Do1IWLXv_h0dbW@j0|ThkI|&sB^#iX!*`T!BC>xZgi=k}LhDz`a zRyvUL5*wl7pdxk(hz%Y8nGa=y5;%CdsUGA`n2mg(wK#g9NqGha@Oo1{$SFC8p&CGQ z^5FHRdXU3vu0q8@dsgm1*`N~b5tI#@$9(~1gGSBYLD`^5!7orYXz$}MC|e7(P!e>< zsgNE6gCipY0}E);q#gr~gN>DaPjUAK? zQWFSbLkGFSp=^+vXi%$4$Ov*#ZyrbjRPlpGv!HB{BJkQ%V+ID$?w@XuICNBO8k7xE zGZ)GRCCn92Hporup=?kcu@%Y&EhGRhJv9L@B&cUN2$cXOuH#TPC=s27vO%+vm!WL% zo>nLuw5RnIhz%Mn0vO$Ae-=J*Jc+(#!8&s7rfmU&vF))A*IN<=Z>mh?pd|(b_ zG)n}^wqamkkb<&7SxW)R2Azte24#Z|LePP-K?&0c$_C9qT0q&L64MUK2Cdq4fwDn~ z*9&|aZ(&~0QJ zplr}ZFx#MP(7?qWC>yl=^8l2c$H>5NSpZc2Lx)rEfg~&-1;tY+8I61yue^LOGx|xeka8s?-@6 z7|fw;Pztw$vOx}VfwDmk@`AEKX(a&42A!iA24#a9nK4i{C>3BPK%GAVgRtuvKu6NrLO2YdRRYdXHfR{l6Uqh+qxnPGpeyh~ zp==9A28L)T8#JVr2xZ$bGBBh=*-nfM47pIY3nK$VF_i7b$iPquzMshkawsdPD<)*a zz>p5Qp$Mv|2y{aclnvTaJ`u_W-9|qh$_8xr=aqGH23?tV9Li>9VqiE6Wh*iiI28R1kwi6Qr z!(%AhgNcFR8;A|cGN7e3pj(XWAi0bKd_R*Nq&^mgN`MlS6qF6>P%1##p#Gj3lnv_5 z=s?+^n$QT!1}&E}gR()pH^CQ7f!gB?3=AP4aR-RS;7g?-7m?O8fNzy@fHaA~w@NvH z+GPw3xlj$DVikO=lmq0zv2v(5XrECRhz)Wj0|UcUC>xYh=0Mq?oC3Zi$_ZlrI;c3P zp4$Ru*F)AzfNzg-f~+Dr0G5FC*N;Kjpbi80A}J>Z2G9Y7m!RUHeM~o?Y|v6T@TF2t zkk%3SQYj|}22f=NzEsKyau5#qQYk0MzNg=yjWR+`3=E*QJsarKCnw0s4FXU$X#I^8 zlnrXzgKw2`VqgGuq4l8RpfcYG$_8zSbp^3O0{{#R3;|F!C{)6sY*45qLD}`7_|AlK zK*5p^WrKRMrBF7gw5o=(LA$sbp=^-v+o5dG0-|0h8&oz-hO$9b_Dm=n)H<3EWrL2D zSSkW4|6LduK(*6qs08TFwT)1=JZQHTlnuI#Y&Vn*I%xSEhz*@Jy9s53eE9&%2Kn+e zlnwIaCny`#nfU=_r+~`;e^3s{mn@))DC5XLa2TclmiN)nNT(; zh?YRvpce3IC>zw@+X!WY77TBPvOzOnd!cMlfA27q4cg6j63PahD1RQx22Jr?hOp}y zKucGjfjH2a&W}(w$fZA^Y>-Qt#UK}gf*i^PWrG|l3T1<;R~aZ9yk5 z(GtW44T~@^Ft~_;+W$U~Qpp=C0kSL%$_7~$3uS{W%Yd>$p^^_}gDk6pvO&$YMkpJ! zh`a~N1`TLThO$8+F%!xLAI?4($^k8l+W=xi=XQ5P*`Sa(1Z9I9cNWS9IqnLS4a&Or zp={8g<1;85=T1-C%2GG3RKd1!Abu8kL%R50Ug}9(>&_)3P zC>ylGSPaSrU9TtuWrH@!DM8twM6Cg3b1^b7=t0>+j0_AWP_`r^Lp_5Pl%vMTz~BI7 zgX(@aC>u0w<^yFrGcqs)LD`@slo3!i=oZ2_DBB-2g9c@Tj*!WMvO&8&3!rS!u|j2F zc0FYMWeu3az)%R9PJ^;R^?e7F4XW?^pzN893=C7CY|xC@EGT;uBLl+%D0?R(1H&>X z`ygmG4ax?!12#d~cNiHMcGN>Tpc|C-LD`=`w@X6VplzV1pzME)3=HR>Y*72)A&3nc z>SSPGcmrjF(#mHj8M z17(8}<|7arbU!O-p7#Za6U4v}!N|by4$6*ZWMKFLWv4JQF#LkDK?fi)NHQ=81u-yy z=6PA5Y)~Q<2eCot|1mHyC_&kvUa%&V4LY9F1j+^t@zq;HIiNUmgt9@Un>&;ZYWW00 z*`Sm4qM__&1_p*iC>vDwr$gDGA~qMw1}&E^hO&1vFfdd?*`UTtJ%nA)06Mm#6~Y0J z{dGgxperdRLfJfw3=GquY)}C*7s>|RR=OC<1|28163PZm)31lJLD94o$_AbCu^Y+; zMcF|~Q28IqzyPXVk3%IuXHcDmvO%{vT!yki1yk; z{3DbNioWkqHt3>CFx(8`SaG2W5j2-4Q4o)GRv%WrI4V7ocoVv+Np_4XW7g zfZ6qsk?2QY4g&*dG06)k8`MU72W5jgsb8RMP&NGv$_8B)3_4FvD1w0jG)lrI&AMV83|f2E}5=u zEa=a4g#}_;m$9G)69en?1Dfn&({F(|HLTMOG}y(aYncdIFl}I+o}kJuHoXeOxxqU9 zf*hmR^iv>?0^78AykgU(Oa(2NQrM<9fF!a^1uYm4OkZp&=+DFeT06}sHl52%(1OW= zeR_gEyV&$75T}EEx`Ph8*z{E(&KGuw1;5M$Ef{5{zt?6LpYCNYXu;Srz1dvQpNWSP z5)iM<1ud8&IHx;=@`z2hvJe!2afHf2=azuBML^aQGQbpdSqKU+Mogb=A?VMzX8LOj zL4QpdE(V4FAAmf;Wi4pIBqKV#A&f_CdX%-G1?wD928O8V+&8(Dr|+^B)L{HE z{js$m=vG~08$o|o9dQPRtJCF0nU$xnvJuo^WSM^1Mi6vyhqA38=tR?E5OrhvVOv3e zrWz@Tv08S57EFJnrl;5m`Z4*)KrRbC1rkhva-{49EtpE6oGcKhLk4`i>-1grf)Mjq3W9DjZgv#(XF8z- ziKSPLf)

)0LeBL7U=>L6pt(!yu|>y0Eh#=p5r@XHa}=Ojpoj7n^>{SC&!(pq&xfu7dtd z9R`paNxQRfN2ASBLtf4MOJjg0CM@Lmz$sf(-i~owX=fH zKx%fP_!V0yEgpgPkZh*}{j&?;9XX&%Gr1@eqy(_ewi&@cptr4Z;)B4mqf z45up?vx`l)au*a}@-YO*ix7D2ERsnH5Y5xOK#EEriUhZzS=TZBu)CnT<_tr~z&_NC z;PeS%gU<9pws^&KVGludrX3Lbh2%iXa*?b&0kLIzm4~1J(;Y)_kO>B%Df%#dGsp}9 zqv_xqciYgUHH;v4!Af}w3NSf9741S(6aiI~1yWQ1;RwA$Q`7+wpS}yEXn_$Vl$1a# zhLN1S1tLD3%S%vz>4XtD0)@cKijfrEfQV0z0x5c71W6)YXeRxEh)-VyQY2suxt4by znj#H|`1D^OMGnT`8+V01qABu$h)?(O1{FO}&Ma?msj}Kz(4Wy^`fqPRe@*u`28IGq zeGG~!Xo&)1+JRO)gBVb}eR{Evpg-gC>4!lS`*dMnL4VfpB@7Jq+tYmoPcs4lxP#Jo delta 92444 zcmaDg&vny0*9p?>hDN4l7M6w+m1^scF)-@W7c(mqF~D&>GKWYu%UUT0YTnAaAR=%Ps=6Y$yfD_lFNpkOMV!(!ZV&5^K;01gP zJUB4#=RO8vaXmhTd|x*)&=~8GV!>qXIm(;US=59f8Q8*fy2Dx)F;;U!GfT6{>&4X> zA8fuZzEeW3&VZ4DfhV`Lf`OwR#AIOLozK9)z`Tcvfq|oC^Ev}r1@ZINiEIoEAk2Q% z+JKXR0fafuZGIFWF2Ekk!@$7AP`4>jm1%mzO-|nF|84mkr^m~&MsL29JXMR)V0s`6 zllXM5L_QftOE7!#**>%BhkSV@CO7xXOlIzvVlm<%i@%j!r?UO!8K(PZ+0 zSt^VMllK>iPX8m%#RpO}`R6S6XcLC`c(+hL=MYbSzxa3+6JtX&bP*#sVQXc4AY(g!1_p)}C_9FMfuRe^u4Q0g z=!3FBA-533h9=B4P&UXB+n{Wa@ApF4Am1N`vO&H-31-(bFgPFfeFA*_jLs3!Ma zY$zM#h+-%kz~O_kL5`4svO$hegt9@7(1fz>K;@4L>!0>E$K3$Y>*?0p=^*Ns-SF;BU(Z1dPxQbQ1y$aT1gb zvTO#F-Os?lFbB$>$iTp`3B-mLrMsbQPDb)P#q{6lnczDY*0G2 zg|b0qfHQ<$&)~$sz~BktFt{)jxvYQwf z7;>TPb_NE9Vkmn$0|P@Pls$)mfuSDC-pjzi(9B-Xz#t^Yz_6czfngd*0#ty5f*Q&O z`DPK64f4$jC>s=#YoKgU^|2qshE`Okplp!dD^NBlbZm8nCAeM|B4I@OF-p3RALPS1A{4)y@i2+!5Yfm#=yYf2xaeJU|?{EvJWsYF!(~* zCm0wQ!lCR_plE`!&oMACWJB3+7#JAxq3rjd^1lhhf!6E2P&O#&rbF4FpqmF}gMw}) zlnp9Cwm{jSklP1kyD=~@9D%YyHRmZPJC%Wf;R2MM!N9<94a}}*U;vfpcfcG5hHg;x z3T1fpS3geKC|>z`(#z17%k*Ffg=2*{c~C7`mZs zkdG%q*%uiY7^XwnHyIch=0e%`7#J89L)jl07#LPU*^G<~4C^^T<-aNe11MOwLM0R# z85nj$*_Mn93{E;k4AM~c8Ab*MMJW3UBLjmflzoknfx!aAu7|co%IgG$UCC>s=IMNl@V!BPQbH-cJLP<98XWd&t}5_o+Vlmn_% zCP3LMK&2s+y^(=|VHT9VnSp^}Er<=ZL zLfG{Tc?=8;&mkO!as~#5w@`Ki0|UcnC>vCs|AewZuKo{YgGxG9ZUzP+Ee3{}3=9mM zQ1)yF1_l`r8`}O?g0evl)qt|O7#JAzK<$4a9R>za1I7d@0V>9=plpzSJ1EI0~i<>HbB{+(rp`*4JzGsLD_{23=C&MY>;a}eF`WW3Z200=K$_Dv90?G#U3u3lU=VnaiWBf7wwK&(Vub3^llI(G5xjz<8j7{>5CN^%NZ4>ODi$@Gya&K4Wiae-wmQdrgJMpYyeR* z(^rEihUvdS)RXDnDqwfc22nqzzXnlLrdz8r`ZHEc?*>tGrr!op7p7~gG5RxROs@t} z8>XKIQ3=zf)fxR6uT0MdQ3ca?gQzdlxiuL585O2SgD95mt2G$+Gc!(^o~^^^&&V=; zw+>@DW59G{T}FS#H`ALzl*07Ox{TV4iPQhB9Pq>P&yWOt;ZzRAakXz`(GWWBLU%b|uD=>D~H_>Wo{aZ`Nnjf({;;O+Qe^F3xIX zZeU?Cd4sqb70|Q&OIcV63N05Pmtq@cV@vyMf{N=Y(WP8Uq#6K6Ixh3Ydknf_3a zOMJThSAN;)jm%7vj7DJdnM@7A27+j?1*YH;F3IT)%uJF@CYB&Yl8hFhkuC`)6AP%R zCgu>+i=vAuv-@LnCxGh88O5LPi)y8yigj!X}_xkKryOv;j0zQ!{iM zOe`>5VTtY=Q%iI;W(MevFf%ldLUXB^5xRrSj4jaBU^vLk9K&c!lj#RdS%s&s;S`XY zo~y#av;DCsll``O(5Mb=N?KLZ0Jv@Tr?VuLDY zP^B*j8qhO>XmAu_U|X9`W?*0hwNn@v7_NZW zpawJp1B0#z0|O(d8e(8z*aKpN>O}?y21QW@21Zc#m4SglLyUoe5!9{$Rp^I798iS` zk^qekfqLek<_44vs(ekLY*3|d1!eOyFfcek*`O*AJjTY#zyRuP`as1&ff@v5gZvNy zWxIkr2_Dd6Wnc(pU|>jrN`U%6Sx`2p;x2%)L9N9yD7y&M*oU%97#J9uplnd(-T`HU z8i?SrH&zCQSquyeQ=sCYvH4k0_7YHsZUK}7>PaqxvNtg>Fn|Z>SQ!|$gN84l;=36b z7L8H#DObiSjQ1N6Y1_nPUJA;XVAq2|KVq##3g0c&k7#I?u?D{e$ z28J{!r;3SzAqUE?Wny3`g0h>L7#J#`>^>$2hB_#FIuip!3zWT;iGiUD%D&0Oz%T*I ze!;}RFb&FPV`gBO17&kCGcYUy59qNnFz_-nFn~t}Ss56FnV}pcDNFFKDO>T1pB-*`O>c31x$FuRN3u zDjZdzY%vA~25l%CR3I9H*q{zQs844O;&3uBfC@5OC>vCsI78X?pkXg48BSO{gmVqjoc4Q0P&U|`q=Wq)O0VAu;` z*E4))U|={5;V}GSU|={2WpgqzFr0_7`4|}(u0q)&j0_C7p=>oq28M@FwjLt`!*eJb zG!OtDspMo}01c0PhKdI;GBEsvvV$2J82+6o zkfDxH&Ur=#25%_)0V8xclaqnrDI)_z0#y7LBLidzlaqmgnF%_C$;rUL!2}(`3vZq2}l_F@UGe>Ol#_o{52BB2>bUiGg7{l%2rDz%Uoe zPG(|YSPo_9GBGf0gtAMS7#Q|I*`PAxFqB=-#K3S8%5Gv}U^owDPh?_XxC&)YV`8Xh z0FQHWGBC_xVqka#mDs?ppXv2gJG?vB#83y5jvO(jn zVo)|H`zb)#pc+yO$_Dk*4Z!Sr1_nLQoC%o2zyN9&*g)B!W`Prw4XW~eplndJ9R_84 zF)%PBK-o#4aTX{WG&Gh2WrOD6Ks_Fiqd{4;0xAxwIcw^noGJzehJFwm+RT~?WrGTq z*-$p9?q3FFgX;LTP&Q~teKVA;#K6F?6UqiPe)dAyAP<0tGoekl+aPfP28Mc&1&^Q{ z&~U_CC>zxH0S{XWFff1$AMmiH00RSPq!}~NP&TN%Q2`I=2{14$1Wji_C63#svOyub9LffT=vpWn)co2E zV%G~XFo32kcY-)V3=BC83=I3BY)}F@3}u&rhM+-gXcPM(lnt`%1(Xf4>>ZR1vg`|# z4YKSPlnt_r0W=&Y3bCu64axyo#sy`AERzMXp>22#C>vy%K9miz%nHf|S>_03gA$q# zlnt5+3x={m9*cys=fXxO#Tn`uKyjQ3l{gC;`G>M!FfcF_LfIb}7#K>S>`x2~3>_dg zs19XdV3-VLgB%AQd6Z;e06A^}R2<~EWl%P#hrb5O22B`k;sTZbk_-&qpoS$>0yJZ^ z2g*(cP4vxMct}zjVi|ZuQksDQWEprwQksDQ6zt#;NofWKP}u+;k(6ct zk6MC9B&8V`8bIxTX3#j9Gy?-@N=gjGmW6aM6rpU8W#C~*S%_tNP;roD;893f2JloE zcob5WfdSN&aDb`-wGTkc8H8jR7@`;$7<{1Opy&t!59rA`%FcHcIjoE@nB%$59^&oLYu$lD?;9*Eb zh|l&wB|wHAg0exy?FlFwOt>&Szj?Faoim9aCE<8x&?0Lplp!OilA(e&ssrjXpeXTlnrvk zbSN9-h`CTU$PtU7?0V1=hLunbsCHTlWoLnwpn%w*7AXS*!)YiRWauR*8)WDWC>vzx zJt!OGvnNnC$YZadY*1qS0A+&`<2N4AgpMYpB>DrD03}8SUIqpsO$G*#FNHyDXrCT5 zm?)$Ti858FILHwOP&UXB=1?{$uiHY|pn}L5$_6D&Pbj+%RQ~%zIiMOW7|Nams>?xa zP#p>?h@fnc?<=5ekj2eVHpt>$C>vA)PJyyRK=lHY4O#}X0LljSj#q)$^|}lUpc-!r zh@;EEu!@0!VHcEr2owcSHmEi`24#bq;b)+1(2U|GC>zuZz5!)l04)N7vac{OFg$^> zL33@dpzJ%KX8s2#=RN}i!#61VA*lS}V_*={WncgmysOS}dvO%?<7?dr*$iN^2 zWs8AkBcW_*Mg|5AC>u0=sRv~%fTpt`?0N=$Mg|5a2#3Ltk%7Sj%JyVrVDN*oeHa-S zLZIv*Mh1o`C_5a~GKR9F7#SGSplnccz5vPwP3BcW*=39j3=L2=XwI&U4^;l^GB8YK zWMJrlN`U(M)1mD3j0_BmpzN)T3=C_a>>Z2@44a_r3ycg5JD_aPq}@I!`vxNe!x1R^ z79#`0DJc6cBLl+)DEk4Z{eKI}dCbVb@C3?!$;iO)3d&|=Vqo|HWrM~BzCqcbHvb;9l9TNisAC&FP#K0f|WrLdeQv9F^9bE>7U?v6z1*k+M69a=9 zl%2-Jz@P(VXEHG`7(vK-s-a3=CdS_G~5wh5#sgArk{b z7?iyp)c%iwazO3;Bq;kZ69YpAlzozkfgumdzQ)ABPy%J&VPasYg0f$M1|^{EH=xc8 zhz%X@n+|1zvhHjs8`OPR2Vxt5>R(Wk8O&i|0QKDuK-r*<#AzrSG|YDu$_BND??c(3 zcEd9$8#KT65y}Qt<-eh9&}<~D00V=N0RsbQVE_-54Qlv^*F!mXK?8(PHmD1&4P`$C zt*?NxUotQ-*hAUxKx^utY)}>rgt8SG85p9WY|tWsR47}Mk%1u}%GPCMV5o$$>y1EJ z0?ILAWMF86vO!s>2g(NZh$lhWplOg9P<9a`1H(Kh8Y*0440%e1S)NVo9&lnjP9zfX) zObiUqplnd@_zjc|8b$jAWh*f;F#LeBb(rcI82&*ype`|sAS9k_m>3wiplmlL1_l8r zI|!78pzIJP1_pHy8`Mz*wF97RP(lMu5D6JU+7m8NaZnxM4P}EWr!Ww^-iUz#)Ip2| zaf}!kvKbf{lA&zSuxTcgy#}-n2FhL!Y7Il#p!xP{D0>eB14AQ}4O*ep4rPPti(V)j zG&(vN$_9;&*3X1;{)0xkp=?P;28N|jwgw{u!)hoSG;F#N%64O9VAu|2dowaH?1i#H z>nILG*|m%e3@4%NUeIt3lnqJ;S0U_rhK-={90-TuIA}Zv$_A}@cn)QQO2fBM_D@Cz zhR;wosAT*JWvehTF#LzIU6>dcScMoEKv59G#K6D}W#=(5FbG1~pg~P>AyD~m#K16> ziGe{DDzTP{fk7F{-pjt~(nh9cq5(KFH$%k@4ib|nuP~lSzWrIqqMkpK9*KCKfLA|qHC>zv2nG9uv zx)0N#Y)~tH6^IQQ{AXZb*a~HX?Ajv)D*w$OrQRW^1jtb*plnd7cMi(71MK-u#c7#I#g*`W1!C!lOlTk;H)y%Mwv z8N>#;o`Hek6_gDcyZ#7e*MkO?zC$@6b$_93P%XzS!oVP81L<6HLfN3;<%hCCi@`*p zY*6hd4P}E`y^2saXbpxclnojcvjDN7vt!O8pz_}ioDdkipc0^T5DI03(m@QA4N5yn zP&TMNp8;iqx?p)wHfTVq1j+_24yuB(L8EI8P&TNU-v(tjgWCT+P!1?QCPCSt=$HXz zPh((Umn;>?* z10?%B0dX84ozB-#HmH*L2xWuni0@D~sE+sxWrO;J%%ThoLJp8_JSUV5N{swaHfZIs zD3lEK1}*-Z2W5li z1(rbBp!vO3P_{Uz(E(+HIw9MjYeYIH!^ zpr+ClDBF~gf#DXEZ3}92K-sR03=GepY*0=32Fi|MWMKFNWydozF#LeBK{ez*C_59> z{$~+mU=VU*U;y=0xS(uM(@Fr!1~sk3pzKyqR}0Dptw27>q$|P~V$@fx!;S z2IVGKC>vC#1VGuK+!QVbD*s&=7(gXr5>x_|wKAb>Q0bNrWrI?3DU=OrfK)@-pdr^r zDEkNl14BEM4eFToLfN1-Gn1igP~&zcl>HGj|2rSbVP|AuSPEr>=6F^^*`OBfMkpH; zXWOA{P{VaMlnrXQo&&K#qYVrU3^$={knbNr*&yG)hO$AG;U_S=o`C@r6o0`S1_saw z2#YuagOD3!@PP};2BlsBD0>|P1A`cp4O$g017(AjHY-8dpzgW`lzj^{l@Dcu61xeM z4QjSqc|bWFj0_A8P&TML?FMCoQm+q`4cgrn1Z6uhGB89y*)EI>3^Ci6zh!C`W&AN+ zo0-|4(P4Tuh`KQSG>Ed9F3rO1&zLhk8$`uS-wmQ3Oy_20_Ge6)9u1;YrmqH3Ez^I4 zD30mgY|Q?QJ=14{s5jGJgQ$Y(*6hrnwQt=ZDrEX?5Vd8xHU~3k?OQd7Ix+n;h&nS} znv>a|@y7IQ5EU_fH;D3>&dtT_&loa28bswxUk#$pO#cm{bf$ZAGy5}cm_8ds2~2+t zqNYr@=3(|{l$hQPqB5r622nNBwRxG3Gp?BanHMbQ%*R~L*fM=LAK1Cv{LG-GbI~Bm zV)|+jB{2Orh8Hh+{h9t~ZI_W?ZewAb zGkviPb2;Od>C&>y{){!#vt^mf8C9k~2JzNRHXzAU0Ic8->iRqW+nAI7t zP5&*&tj^TD6|%C zBpb_iAqEE4LQsLv#ll)A1DaX|EvI9x2Qe8KctA2N%)$%|tS#GDxijB1=Q;2Ekb{8% zgjvr`@2_XpV`SaFubx?7gk!M?XgM7#csbqj{3*%bJcymZG zT0)k{8Ciftr5H`OzrD^}#KmYZJ>d~^IHU3O9gmp9RneDb8Cjrhtu!^Vw3zPpm{}>+ z5M9RD*cfdYm$3=@3Nd3-^rc?L1{mg;gUm_EEGtekp6i$0&V{RO~ZiLpj|l7tqhEy-Ub5$ z!)(wxFX+^Z6DT2pdL9f64CNp;sOP}|N-yC3nV_}?1H)C21gIMV+6@F+s|DRNV+>+L zCj@4I*r2IP1_p+YAU1T2{t+KycG_o=M?zyR96U=Bd=8W4I5WrL<%zd+fb)(Lpk6F&n3XuS?-PF0AX0lY+q4YY)YpMik|v{ebp1~u7) zplncUT7nJKx8rAE0F68`jVk+P~VcF48(z!VvSHXNKprr4N7Q}p={8Q%`7Mz)IeMSWrOxg zEQ7K^?ZY)tHmIiq-d8CM*%Y<|Dh`UieIPcdZx5R4J_6zhGcbV0@J>P5pp}dlplncd zT!XSf^D}p#Y*2JOg0exYq+USTpdQdWC|d%wFcHcIg*12{rZ5A8H6y5P4O&7Y%)kKJ z|HKAmgL)#M{qsV?3=D;!?PXB$X3#1{C>t~zA_rwJ2dz?svbTX2DMHzxp*jO78#L1a zUeP2BS*+v+5wB z+cGgQ^h4Q+ObiS&p={6u#bPKshlzn<9h9BV#K5ovyjfG2fuV(of#DETVi^+y!x<p zD`~K=1Z9^oGcagC*=@`W z40=#D=%fJ?D0?n51A`Tm4LWJS0m|OQ%)sCV-mEFiz_6W}fdRa7Ntl7*1TzCe5L6N9 zw15aG`yDd_LmZU-nVEqh1%bU-CQwO}8V4O)#n1Udm$NW1?0~XCYlXoZI)xb+HnKoBbPCrqFdSrIU;yvv6lP#J#sb~ZDGXT%4BpWx z45_ie8#;v<7(TEtFo0J>2{SOTure?_gIWMu*ZUL1hPHy3LCa~xA(a*{lntscgrRIu zTR{@EwiC3?9Mlk2fl7c18Eq&V)bTWgvO&Ws;MGmykcA`8P;pS>!WYU04Y5T)*`PWl z9?AxdY^Fllpu#E}%B}}hi-k}QXhCQ>lnt6vCZE(5WlZNN29HfUGrCMa79wDKLiwo8(M0aQgEgGzvc}H2DEks<`!bXbnkM&vvOyymeo!`OmOKK=e$BwZkOXCerslwVEJ2&~ zL1i^~lcgjB1E^mQ-ef7sz#z)Vz|aKM09wV`17(9&u}*`sK~pTSRZO6jtE-{nA)v`; zC>ykR9lWnnl7RsI z292_91hGMDFBupZwnNz__w|5|DgcdGH$cTfi$>d^Y|t=V50ni$ zZ2-K|Ns)m8H1i2w(FE;7f)_L?LDzPz2We1(xEi!sNJt6Nm)i{$2lW>ZLfN1W#&IYc z)LS|WWrGT$%TP9Gg!Cqq4Vv4z4`qYa^gM;KLA#4zg4cE_K~}edS2sa>wd|l}Hp-Bw z;e)b4saFKb2BlspC>zue1+R2ch8+B%4;2SF)C$T5EkbsIvO$jag0kyD9gI*Y2UPyY zL)oC9&VsT*#b*hW4JtmXplr}&Q!A7W>X`OJ*`RUYSx`2pBwYe!gQ5exqDh&70aTK1 zl^Ga7E0Oj?6@f;3PC?nAVbLp4_7hMi63YGq>O?}>pxvU+pln`728K6KHmD^1 z1Z9K9{eM8&pi=c8lr06?tj_{k9;3{_09pzGUd5!$z@W~^zyMywq|Cqo8tWH>ssVLQ zz^j;)85lqvRwbyoF>Do+G6RDdBLf3?6_YXpg9Rf4g9%g(Xgq$_xzd zj0_BJAdWHv187B4Ae0T7D2RZv{TLY-lA&x+FDDDi1~t{etC*A-7%~|d7^qMh1p6 zQ1(Gk9RX#7b}xY!D=9NDfEFvg1&KpfKK_8RK_%dS2)iECXJp_4ErU^o%xnol*`WGf z9LfeIOlc?^lmPWWZ0IU_ zpc0@%d$OQx&}?J@lnu%$)lfEQIb{=+4RTNilnv^N_d(g9ygmiW26gdfLD`@ju>i{6 z04o2NK{=ojY7LYP>hEoWvO#P1c0k#nmFfGSY*0V&2$T()G&luigQia|K-r-F;Wa25 zG;?+b$_91aAAr|(sWUKu*6e)-NkE6o{z2KGAO){V(uB-_3xHO^XhNb%9LfewKq^7m zpz$J2C>wN2fC-chTDoryWrI4nj!^bpQ2Fl;<$zoYUZJGP!0-b!_YM^Y?e|H9vV}l9 zTcB)EuQnITmSSXJD2B2@EhX^EB~3`y1+SjcWMI%?WMF88ssUx)ZZNx^fdMqIFcHjQ zU;t&a=}(B*`SaEZB_;?&jp1Xc)^h_B;=DS9ppZKS5{Itoyb5K5<~Hs?*`Pu5=TJ7N z)$|TD{x77@z~BLjC#VEyjP@6l4ce2z09x&$&%gkxgxH{L&`>N7lnq)eA_irHddCV- zHfUT~3(5xdj!mF!Q193d%AN!&|6QOQ&>|8)C>s=v5l}X$$OJDw(q~`*?Rw6Eii4U{ zWl%QgEUg+S8#Kw>1Z9JE%YYXj=`%2ZLT)BV96HG{Ul=sEZwP5*E`>^fHjRN778x=y zfZC$lq2i!!`Ccd+)POt;WrL2jI|*fj#thCw*`TF0m!WLXaQib58#9 z2T@a|KL=3@rkl@X@n=k!-VUOkOur7Ie5R| zMCDB14x(;MXP?6YntcxkQER3z2T?ZDzt3UuXZmw)y2o4=KSqh^)914IGp?Ba97I`6 zH=oDi&$wiIJBSjPetjOxamJeI^XIdaGv1jlzJLWZZJ!RJW=!7>qAaGfFJu8tPltmj zmg&nuRL=D8Ac|wU`yv+5GJ)wJ>cRBqAj)LA`C=B(;Wq6c>dW-&Ac|wU`VtnE~Cos57}Q1kZy{=Uc-fz*s+BehrH{W6N}R5M@6-A4DygJ{?5)Pu~xsWTrm{Q90B3 z*RsH-z0E%%IH=Y=xjwkeh|AE*&&o z0-F71s|PU|7GiU#eIOR(Ami=va;%fUC&5TC zS(;6s7{V&SXgOVh6?81Ir2*u)Vhc+!&1f;5v6e@I*~G#Ebk>UmlZ83t*kTJaIDIgf zRg%#VtenZh6iS;wY3S+47Le1AnJf%JXU9k|S%A-%5ob2BFn|b{gHNmxXE8CiFxdVe zgmoe}lcD+a;sn;7db9&xOw7@bO);@BKs#E+!~*>g7!wOa3^f=hBU@mcjBH_IUXMB_ zZ(?Bvnq5aeblJiTZ3f=N!W=`y0&Qi0iG?ZJDKaJ&mgru!ury~dMLpr!(g0nXr5U<5 zOB0jnfd;G+lh4fNO=Y|xl3 z0|SFFXbAx5d@}~fF%OK;J;Fyp;-HyN1_lPu(Ws1|kue4ahFZ|l0MN`hXiqAL4LYC` zv`+zaWDIER7c}_^VuR`%&~a@bwj8KA25R(x&X0i(QfY$L5ZJHNQagaMevoS*K z3=ANZ8P97*5vUj5RkWRffk6ez2F)95LD`^+%mB&;?Hw?OvO)b*TPPbeZR`wXgN}djgt9@~$o!#f zPzx>;%6;mx6|Ma-rg&p`2nU8?>CW63Pb6E!RWY z9-wX?lnt8W?1r*I)5a5_>_kQe2GF#T5NJ9ujgf(2E>r@vk!3NI4O)4*63Paxyj%}u zmohRi?1Hk(LEE{YY|ya~;4`4v85ls_#G6oY(CSR^xzFqj41J)U9#niH=nzSmt3mtA zzCtB-z|N0hXJ7#B3j-er&CbAZAGA;kG!xGbnNbBF0u9Zgnjmp52JpGv;B%k3Al(Kt zs5qzvXai+~(y|kjT@M=k2A>nd1=%AEJ|~8YfdRCP8+=X-7Xt&R6$U;hh6}QE1bj{m z7Xt&R3jsbRhKqp#w2={fObi#KfmHyt0Mz(x2C<>#M<RMAD75Ms7{Ci4gcv|oCj)o^gb)J*XsGE0R0F82cn4*J2ExIMA%q|y z0bUFt1nFgg2DXHRAUmqTiy?#<7(l~GJfN9)A;`G40F(_1Iq>?2dT8;f2a*s0xrl)Q ze1NnFB>o(r;-L5g9~v#fzyK<*e4*l?ed(a%@r6Vn7JwH(h(Ox4-~|vO3=E*9AgNIG zplqBCWrK#C>Ih%tcA0tYXE5Q8iy0xy6NV_=v9I$jr|w;o(tffqoCF))DokLMr~44?xIG7v|s zhO$A9*al^T9I+S51~~$J5{nEZR6r-O)Pv6C1`TwAk7AL51Pk~m78wQxkR!k+vB*G< z>$(p$2;_)QAU1TO>o1fI%G2P54swvF0k3nAgQO4eItMuh2GDjAG0>#B9JpMmXOMz& zK$F+HAU3oeU<_r0YFJAs8&s3pL)oB}Vy;j&X!leAlnq+g13o}n0kTpr7Ag)ZCo-UH z&`@wOm<>AW3)Ff6a~K#v2c0!T*`R(U=)6hLWEf~l2Yi^c0s{kR_;)T;4QL=_F_gU& zbTToN4XR$jr>`h5Fo5Paz$dOKFff2dY7axzfW|pbf{%JpU|;|pWqckg0XppYDwGYX z{q95Aph3)+P&R1V;4_pBn&JhoLr`E~099uHq2i#*j1@Eqt^irp!wqGFwg?D9+4Z0; zc;Zk_Kj;7>D0?30)L|$aG$mjHVndr{_E0t`zTKc~P@)TjvO$Rsd}y>10|Tf*1zv}s z1evP>AEu%NS`Q|Z{ z4a!0O8s27*1#%z`v~{Zq zWrG}K0A+(5WDRA59OMLLgB%22hoA<@)8KUoYLJpH1gZvfs!kM?4VsHcfU-f&yL#9m z(4cJ^-~|e5kg2)?s3Oo@L^FsDZEp8L*`RDW70L#Uu1`*pb2pu1_m|Ia$rFy2UNO=L)oC^z_L)bBj_YGC>yj4R1?YuEqKv|vco_d zWk76bf6p7r1_gBxlnu&3;4`50ASZf(*CgoGL)vlqAVts)BIq1Z(6)S#=0>PENOL=s z4N4!qP&TM3JsHXd?JJ!LWrG@`^Pz0eO01<&HfVkFYA74Do?$C^Ie-BJ189Zyey9W} z5gmoHL5&XZDJupH44`e@7op;y5%ud(HfSpFE|d)_-5x^Opsv;z5F6Bj1w{vx4e}Tp zXhPhGfuSDcGae`h6aYd{HfS-s1e6ULkp-W!V#L7U59%L6#X*fvEhrn*#0H+;N|^VdY%fqB56T90Kwm@IpjBBPq3l@DJpmwgy$J&Y zXiEPth-1RQ0P2}CgJ#N2Aayw>lwAzEC;-X^P4A0B*`Us)G?Wcmp{odGgLc!aL)oC& zeO)LUbWW);l)VeI9M}@d*~7@dU=L;QV`O0PgtE^uGB5-~+1D8v7$TwU&x{NVu~0VX zoKo_<|1_tm6DrS)BVeknmW(*9VGb6z#sF*P@fZ`Z@f{Gaf189%|e1eJ@ z0|RK)2KWROGX@6GiagK>Dne!q44`vpzz3+9F)&1e7EFUC+07WhM@gE4*r0J8Q2B2Q z<$&^~Ba{v5^n`%epb`djP#u&FQj-8>gX#tFx&>rAp=?mL1RsK84Qbn7go=a4 z46Z}jpmO3alnq*?`54Lu4O+c~vTHyc?e|a)Xm|BjC>u2I2tFyrnt=hdv+_Ux_CK6# zZv31(wlgq*PCl49{d@tt{PZkIHVwuj(X_a}oWgXxb!RK|2;6*hmy z9n+gt*!-FPT$p}Eh0TxAVY;#^n?EDN^kNW|F#RxyGMO%{1~x4jMD3Zr8AKhJ&aBSn z&-h?^Fo>EleKClVnf@6>-I(sI!3MejVKRtvnEn_Q)g_RK3ktnok?K= zWVhiheKrB6=n3Fi7D3R8WzZ-WXp0pHPo6Gpz^2Z)V7fJkN}iq!qHav@Hegd{W1r8! zkjDwxY*;b~lvx)sRx@)0W5~>l!}fARHgR#eI?yN_A82lcy&lA5VBiOJ z7MO1{Gcd5XY+vKS7A4PfUITOvFbK1s+b)#B*2~WhIwp^ap%`frlDxp*XXNxe<6$gV7v(*CUgO`Sb}PtddOT;M4iV znN7?r!ILM`cPwOUnSSXLzxZ@MK`t3a$W#oonW^FS!bNPQ9IEK!`etV6WB+F6Cesxa zxP+(6t!9&BG@7oxn$0~LeeS{B0PW~^6LUj!qsZc*Kf9XESk%lE zL(0TxyZRco-3j##pjiY^5dk{A2(;M{)I9*5lnpxT={}SVYS2A}vO!&(*HAWS@#04)+X-}dz;`GIG&1lP$_Aa+1lqd+avW$F zniDkI%*Ma~TCKznWrL1Z5{0rsr;|xS*`TA9bU2guB8pcw_wW)BbtG#vrk!3bKHe;ld-)JDDtWrKngeCRs| zWCr39R2;mu3d#lz)PT=?=U`v}EkXmI`Od+>pv1_)06z1bgMk6GP84)dm=H%jq}2f0 z90GC#sKv+w8a?J$Ny=zwSt8=7kz zplncG><(pvf;|Yz28DVgc!MDq0|RL3MLbjjl;~2SY|yzJnNT)pY8t$25tq&d>{j5gDg;jvOx(`1Ih+DS_jGoS!NGnLkl7=C>s<7flxNc1L07%A*lR`g>pa^ zfOj5(_H==6b%Kh6ECZjnE({rQYygQvOSf()8)O0a5=T);+ZlX`qbS4!^Pp-#Q2@FR z7j*q4C<<1A#Op;N(+=xE98t(YV&EGcK@%$s3=C&L;?P}6m!WKs5AH$PpeT3>WrMQr zYbYD!=#Nk~C_27F*`UD#(9#6ZrY6wfK|M2QG+3O0p&4|U7L*Md$m55yLF@HJp={8U zq%@Qb+IFJ|WrJoI)uC+A#$xaoyf|d=&KN2V8f~zIvOx#Q+e6s(44`8(z*j?xGcbUP z$uN)vbZ1f`lnn~r3@97qd+<$Z%#%$H_h0Bt0XhKhqaczGZ;w2H5U zvYA2Ue*=^Q@?|%a4NBFMplnd81`puNLMo&sP;pSIUIk@?cDikVvOz~8ZG*Bw1G;;l zY|sqVAt)O(Jaz)iu4iBX4Nso~a~K#v@p=WyJ__2=0A+)G`2flW4QYZm70NO&fac2I zK*d2@tUp27pu@+1K-r*^kN!Z}ps_W6&}cKXfg=UpU?>kMG!&r{pwUDfC>yjq-WbXT z_3cwk>1G8zTmY$y+z5DEjSfwr0wp=@vtg0ev&4ZieIk%6He6x3Bv2~Z`} z0A+(Jp*AQRv`rd3u&>C#0NQv0zUdL#6ax?1LwCZg2dP(vcm{mAqcS9mf-iSeW&qDp zgHJ|R2G1rjTmsK1K-+P5L7G(|b-@!T8|2bgP&UY+AE0bd*A;v;x+=sV@CoS9HXsjZ zR9PKj4(JvmA$7=^aNxaz>I|TBi5bA-_v)ZY7v0JVa`p=?mqoCsxuLMR)`2F*l)_YSHDS;dW8ai(Wsi{|o zWV4ANjyeN)x$O)n8`S+-3}u6gPw+*I>I@8^0%QwR95iqXzKBtsfdOU9_o%V^F_uift;P;orl_sX z4jMzK22ppWp9WDO)1@`oLBj>vASz?}ZV>fgI=3b}=$M~q5VdCdY7oUR{WpjzneMH{ z{+{u~bZc#Pe@30@-5|x0roRSJH>O*gvTHNCOiwpuS7z*(-fhaR&e%JB zvnjhelTSRjFE1p;&H%d48PpL1jp1F#JAaz79oRG+heZl?lq zKwYcp!Dj60jQ-QBLDYxoi$T=<>8C-|lj)y9RLOK{b9O{OA9P*c_GEMRg`9GApjHGM zsBh0w4`MPfu!EXvETFZ$EG^rW9NB{zdCr4oNWiwSoZH^$#BN~%z4^}qbn~ASlNsdN zzd75P%h~5hiZ?Cz@4iE`k%8d>2WYHak%2)|P-$WGWPdqH)jfxe4w*DEFf9tJTe@tL+6J*>sy?zn0(%D83v z<8ADgj9aG5ZfBQ}-X+YyzysPTrvj?67(vU~!Bee_bHt_xY-d*$tp=STD8j&?!5GC< z#K52ls`T2XcWq~v@s1Z^U{D1eY|H4cCCC82YXLM=%mC8j2h~!{z@Q154rp_L7y&A< zwLl}=jF-WdftCa@&UrBX<92pGW01!4P>p2_44R;!TbM@Bu57I>pkV+WCeSJi&?&5p zb2z6L?O+e*ohHV>p!ivUfq_wsiF5k39qgKnZ>H^JmtdXfz`(F`y6jGN1->~B3=Ha^ zVe#b-3=EH^d+%hI_S^)T)=~#G`u2fXVjwq0GffO&&^$X^0h|^D01MMbmHWWS8RtsnY}V2AIA`{B-`(sgaxOlqE9(D;vlj){=*wrLmB;iKEod$}0unwrxKx)8F6JuaEkz`;n0QI05b6`#b z&Dt~0(V2d454)tMjuZm}W3ZuwFav{;6x?VGSKgDv?Mj=+>>To-9zVn~(998I3CuE3 z=7+YX22Tf8i&e5K} zZa;glthFrMa8TzD4<2)}^3x}tW4EgZ9S8v`UQFacc{~b|ffzJFDF9l+K!qSN2{IDw8y*IB z4|xU#19wn{Tn)1x6#a~IxD*%|R6)m+Fs@!Bz`!t{je!B2R;3i+?t%G<8=j?}LLB4| z>T`n}^b_JBCQv~M>U%?71L8xR0x}Kk6mAA~kc|c>KzC1WfjI@VhKg~{!|7WNv#ZHH zMA(cG65A9|L*lFgN=SgpRH)sskbw9+5@g*Wm~{}JPgaEa{1C|Je(X@6gTx`a^0=h!XnVZLvI2!ed8iSB!dZ;L^t`e~T;pg||bIj+-nkFtx)hALr%Gu$?X z>4`_#oxMRJY@!6V7;FbHxx0GjG&yb7}uwB4R@PWtrs zN7>b6%aw84`4MEN-SmQE?5zBte5MXMunm+6os>aAZ!vw(F?KGnlfslCPAXww&;-p< z!JGst{lFy&$QrPdL>So9L0iV(gI22FhdBvUi!#oMpDuWuT~ae%1)iHyRdBmbPz84} zbK^KWuN2sxH=slAp2O?`btD+)s7?QWoLx;$O%-l9M&e>r1^Lj<9#o5h!dz4p;X%-m z2FM=ttAns7rfV)Ua1#ABd>6YMciw;L3YPMTnkP2Y2dovR+?r!Y;3pFklA+RBC!l3+h6 zgYvK}+zp^8V4TCK#lWBdE8@wl zofxl7?>Nh@t(OZj5VSsxQIiqW_Fcx!zyNQL#%Mtt2`XkmbJ=avAD(5GW!y3S|5S3p*G!rpq5;7oXmLo1N8Oi-93k z8*CqoVG)B01GvHkIZuNz3L?S)i5$>6Qbs3uz<_!ljB{+K3!i6KmGcEH>q2ek!D}@U zo#}zM*_}1vZfr}Gi26o%&=gzZBG73$90kQ?O0Tx#tDxS9KE&ZAV22wqsDoyX9y%~E+(VXN zF1pU3!5G76purf+XuzQUje&syr29LvB1S_7P0%TcZ>HB=W|vS0H4coKK*dJ|++z{dwnV9*R;Vqkz~Zm1B0t~N6R11RWkO#gp{-NFQ<>o`OgsHda}+N%WB0^&31 zgT`3EK?6!uprFw-0*9zDsAdLBfcA}pB&v+S@h<5Aig$g`ihi&(XzUXteHtnaZhq^7 z7IuQAL8DF}X&GaPZqPy+27S;zAh0y(EC-NuE<`#Kbk-w-I%svycLz|X9PD342L|<2 zMg|7ZhT+M^5FtYbbkm#({xhH$qJFE;9o|#B_)2>~aQsg`jO~ zP;i4YAQuDsV`Bye;~dZ?v3u}%0*%}<&N(!F@^yA6twW};1Zb`aDi5DBf>J$b<30n} z6R;|6hY2|7gg}icumq?D1@ax|^p7{#EhWI?8Tz2=7c2`JSO>{QL1aOFR|b9X1SqIy z44Nqc$*u;;I_rTtsE{td24gh1sRV8s87F|M?bmR3gNC#j=V(n&y2);4u4T@^z!+*# zlv={T_!g{$F$mlsb})x|2(ww(VFrmPh+{$R2e4y7?M#q!ZbGD$LF>&J)Io!ppeT52 z296b`G6n{9&}<2lBLjov^y*ve>UOZy1{yD5V*y<@0xkhTP5?)M00X;$IRk?+=pt^$ z?_gJgy4au*9>zHh(;wVomtf?b{__^QqWKOBSPhlQ1gfEq3PYQ@APGng!1NE71;{^6 zY!Z$P3>p^G4?bWQ4pj&3d*7kOz~E>BaW|yYGGI^#O$XI#GcZJ2>>~A1jtmShAQ~ABK}E9xs2DS5PzMber#Uh(uv&pkjRuu$h~f=&TvL%F1A`n` zGK#4fTsRsqsDq~1K>=qDm4F1CA%i;T7#dK(1)xfBGpK{g^5doq4As-`-DOwP1qC8J zAu}2>Kx^LLppm4NOt5Cw2GID(oUG}F_t@Qpvut63r1Tloa#_#BIlb#1y9Z=^2R0@! zYr5fmcFXAw``OuqFe!dz@edXdyTwLlB4p72+%mpBaPZgILqSqv1gy3N-c0%utju zAH)C^<`7jN7HB;SBSR2~0wpxCDiCAe$ln1m;iIE`$MD3e? za3!O{^a&+weA5qD@JViO_{J{G#kgfzQhq2A!8b1$IV&_VoNI z%uUlDxUf&29xullI$f`l%@%#3+ay+w(_GU(i1Tttu`w{RF*9;%F)%VSax#HQc`(Vf zytbp+0@V!teVjjVw<4}gbOj6 z+0@V&q91ZS0JEu~5tu)Hn-7O6*o5g!z8tck<$e-OhTtO%#FHX2L2pUe2n|H zd&hF9G1X%n`EP)J1c9l68Tz#V2H;Bokd7%ZH896eV}W**fvJHd+R8pt14~u3m4T*) z=*KOX8XA~QXHMWyW;C6yp1@&Rk8Y76#?1zX#u#c$&>drFg0_;;)X)@dC8MdKDTW#| zQ?w%+ObyM^mOGjnV))$90>eR;7!I;Tx6H@@?N|p>BSSL=Wt1ZuOpP#nW@KtSy+4sd zgVAvMjzkU(Q6o#Vg`K9x1}4+{9y2R38Cql+=n;W$43$*zHDh}Ec z2Ws1JgC-$BE0#dwZjdd+ps`z!UQjn2#O4O=R{~uS2vW0_fdMr93mUQK1}$L#U3Uc$ zXJY`>yj!+!pT^;=SMLnEX8}}PgKm~UVn>45pv9C73=FZtkmDyn{>cD|L)909*r3)h z=mZE58!FxmVnf9{Ky0Y^G$i(V5W54kI16-tE{FqFbPU9X`s5VIVkrA6NF1u>K8Ovq z;4KpS6Nn8}&nCjazzAiFgV<2LvLH5e{hlJ|^jBdhM+YPURb&QYLoKidv7u`Gk=US< zi5Q{k(?R0U(8?Bpgcc}8l!3&dYFd!kpp%KfdO>p)3y>tXgV<1u_kh??LoXn)AA;CD z(?66kN!5c!o0&uz7#N{?*goP^R9qRvhKlQf*idm}5F0A)1Y$$&a}$Ml0@UyK z2Z=+~M1j~)z44+9^$d(q4araqj~EyjGC+!;8j3+|sD=s<8>+qrsvdM-*94F_RLxWn z8>(g(68kU`8+6wfBWU9tDEZt4Nq{*F439xbF4E2Qx7+)b9jIKs6izv7y0u62yjzUjeb9;-EXXV7`9~ z5{DWJx;6`(AQ>1Kq{JB*7(s(r3=9l%;tUMJP_`yW9BQU9hz-lW79b8(!U@ENTILR7 zL&XC@Y)}`Ifq@|m#D*FgkHjtnv7sSUg~V<~V)ua9P;=&r*E2A{;$|mE0&3Y|5F5Gz z^*G1}Q1&H|I8@CY5F6^yhafgo{2dbe2Z#;Y5d^v#6U2s^!zRJNzzAZ4-iM-q`viy$HRmSS z0;q=jAPK0UFOb;3Ky0WQX3#`Dl+A<076q}PhN^+sP&F1HHqR|>3hB6QvYEC^8 zdn$+xb;LXnyB^9}4&p%B8$fKRK?gx>sQ7UZ8*1nUB=#c^8>;3t68j4h`!9$MHIq*U zk+bThKpd!VR6uO#!eR{>1_og$+ZZGcRbvZcLqoy|#DHq>#`kl1TLY-mVqMPlzmVjl;w zq2}C>K`Q_6fh3@YK1X8z1hJupGRY!>jvI+B0%AiARRyu3>K#FBs0X}3Z0PD{e^~|w zVGtWs{zQQ!po&sJY^d)uL2RgaF^CNnuK=;3;!Pkn=)3~Zotz*x$WR6bh6zaQMIbiR zL93D2TVz4yKU88bNCIlmIS?Bv{tCo~TJ{CRhOSEf0rCNq%?w&a0#(BcVnZD&1Y$$Q z<&oH$AU0^L6sY{s196}RnIo}1L2Rfaf{@tJNbD348)6VcDTobK-wt9!EuIKsLsvRa zm1AHKhO!rc#9`(CDi8h&NtRP#;{8!EmJ#DM5F6^C zuSo2FNNo0cc?JeXs6i4SHdKQghz&JVAH)WoeF{1Q55$IwJAv3x@i-70>bMLL8@lv5 zN1lN}7|JdOi9^*ig4i9P@MmCPXajMe5)(jd(2zX?1H)7h8>)F85_=1X4Rz>VB=#{R z_IVH+YR&@?8>;>phz&LKmprKahjJ7^XXZd1p#@@tmR5r9R8?SL5QefXLE=y~&LB24 zYCJ$}sCW>F4HXXuv7zFLAU0^so`HcO4a5eUSW0Lw_ebJHfY?xjGC^#phI|kkYG^YO zdnSktb;M#28#Jc~I*dV)fk7C`-UJeds@Vf#Lp^X1#O?w0zZe)8PJ=k0r8J;x?Lcg( z=9@_D_aHXZK|he#j7o?inG3{*nj;NjL)9yS*ibV~k=W6o%R^wnn+lSE9(SIp#K0g7 zWtV`&p+2Ysv7tU_2C<>yy&yJJd=iKa6`uoQgBH&+Ffc3xv7u(Jg0Vs6{{avO>e7=) z>`O@O+aNa7pf?~kRQ)Fq8*1opB(|V3B2=W1*vd$39c57Y4>i;lNx~V#h8h}<#I6Og zp+0K|u|cad7#JA3l^Ga>q3mfOaj2RFAT~5qmV($&@l6PJJ;NRl2eb~Bfq~&5hz&L9 z6cYOZhz<4eOC zv7v@Wg4j?)vq5aAZ%RRI&`Aso3=EYj3=G0hb_+-xs-_RbhK9ss5F08!7j#+_tdG73 zNn#C%4Vq+SU|`q?VnYqxg~Yx9VnZEt6N&u@iTxVHhMMyS#D=P8Qe|KO-I@wYe+*(! z4#@vHAU4!>W*|0bj+=pj!Ag~ZK^V$*1&Kq|_=DI`pM`+fQ1L`0HfWVRBj|i01_p)# zkT}$wN>xz#59M@&B%rRFg2bMS#9jtsLk-#vVnfv*2C<<~ev7zGiCqNvi#90sQ2FL2PKKTmrG7;t!D6uRv_jazX|MhW8*g z)SMqkY%b6`L8#+|k=QaYHYoq8f;dov%s_0Y1`iM$YH=`#4I1kOjq_+QFbG50Ng#2k znp_YY>gXa68!BE4VnfB7Ky0XZuLh|6he}LBl9&TxXMWhAx^hz&K=7Q}`c>I`B-3}pyM zV&{U`P#;%-*q|+v3=9l4nhXrW)}ZhQb)7&GP(_nKY-p%V2eF~zOOe>?L2S@MDbTD4 zhz&J#FB1Dahz)hz4J7tMB=)O%5C>||Zx9=*fmaLB?vntqK}(Am7#L)<7#M`1Y-Nx* z)NxuMHfV(?sKpFY17%x+#Gz_jKy0YTJV9(bX!}1F$^pfA9*7OqPzqv$CY3-n8^};7 zy9Fc;Rnre*Lk*n*VnfxeKw|F%v7zdZfY_jEWCjL?6Iu-Q48l;(Wsn3^(LE3wYUl?L z8!G+_#0JfJfzCbyv7vf7v>6x}p=>!28ybr0NNfWnwk3!SHm9C}!3)HJY6t+ap$4TP zvFku=s3ST-Y|su4&_IMX1A{P>Jp&{TRkIkxhI(Kthz%9r4`PE>?tsqA1+nX)n$Lnb zQ1)XG8|t7pNbIjj?0+CO)F6HxM6MA9v7zQ@Be8=)Y^WpRKy1+3A_fMA`Xn6&24N^C z7bF2yQ~_c`eb5DBL&c|n*y*5@!oV;S#D?l!gv8zfVnaP}5Q%*XiG3NwPKTENPe2@~ zhF2gq)KCUp1_nkbTLQ#}Izk!5c7r%VU6+AD7|J#Ri9^-cg4j?G_#m+ZL2Rg+7+ui# z4^&Yil0-I$4LUUf)M5d#p%zpkvHL-6sH0~fu@@q-SAp12b9RH+Q1u5vY>=6t^5+zc z1G*9q#D*$*iNyYd#QqIpLk;E8L&Uuhhz&B7fq_9AiS3BQjs&rxzE9BumH(hwM$nX- z9s`3glwFLZs1C%2hEOwz4b?mmi9H{Qy%NL*?L22-U|0uYL(SZd#6AmRLp)i}a1Fs> zxR1ns0b)Z9`Uzq~G%)-Jv7v@?=rb^YH!p&Ez92SKjXDzB0Eul0VnfaJ0`4Y4U z`W#3RRKraW8*0!!5F0A~62yjzzXP$M;y*!bsQ5n+8!FCeh-kv|f!JVs>lqk?3?UYS zZWfmYNkBEIf!I)kv_WjBxEY8I6}JYlq2g{JHdNdP#0Fcyzz_>!L&toQL2Rga0f=1> zl_&>spc2(k2Z2^}w}8Z<7W9MIPz$Dj*iiBLAU0Hd35X39Uk_qK#kYXiQ1ee9vFmRl zaULPDe}LG~l+0*^C}g;h*uo$-G%i&@Y^ZuI5F2WlF%sJo#D=N~g0Mm59|J=)gaaaS$7-UKYfLnxlrqwgIuBYFuG#kpKN)98lXH#D*H00b)Zn zyhDdCCB(^USI~>FY9R$X}zz_psL-l5W*igF)5$t+~b`S^Z%Lz#AnMmwKAU4#{ z%^)^Z{Z0@YYUm*(_6-mls^%dQ`xO%VGl-oG3V+ana;8Wr9K?ni3hGM3f=d%54mH#W ziEWLOfx!aAh8pCE z#103sp$(m{5_=aC`!I+NHS`LI z4OM>&#D<#l4v8%V+7kg4cLTA(p#?fE8pHu@>}OzL2sLM55Qef7K;mFU3=G*IHZ;y* z68k2I4fW+CB=&10_7@NvY7VOfB2jaL*ibVyk=XT4NStUSb_o)D3KDxR5_=gEdp#0+ zABYY0@ktOn6kM`1oV8$J5QegEfW%?r|Bpc&Xt2Bhv7wqjgV<25BOM?%$T9{7hUp+SG_)33f!hD!5DS)BF)#>2*&C4*?E$f&QE(8%hH5?oVnf9* zg4j^;J0Lbx{2_=96@QP!{t05ogYB(n_y^)Z74cXj3LBMN1T_AtL2S^%XV3_REdzrvl-&gqhpL$hVngG27KjZMUjkx-Ry>35OaQT= zdN(1lPk`89&(t$8T!eEN7;Yi4AA{IXgT8>+U=0imzd&rLq0Dv+42)2=B!~@FqlCoP zMq-K^&+-H;~xxKy0XQz9X?2>=B8P6U2rZBn4ta)hmG5P%|}= z*!CbcRE-CO4J!W_7y=<2u#=)dY^b5xAU0G(A&3n%vduV6d#BUEn-1~n6Pkl1S+K;=Kw zvdu^m+mYD&k=Tck*r$=$=aJagkl447*pHCd&k*c-hPMa~!$&0c4k>hhz(nk0Xk9zy567z#D-4SgDw#QO;Us6 zMF4bcH*~7l6?DlDBXm}@2P6TV^ScjXL#N?Hco-NMq4PnxAU1T0W)X-Dok0QJ&%y|u zDR~4EhfZFwf==3jP6POW*w7L6$sjgpJQ|d2Zh<(^;a1Q+8?b@MTc8c)(60JK(5_Wz z7mZ1ffdSUp@dvS?eTWp{uv&99XkQAndH~(FUC#(D3AI5dTEo%- zlnvU}2tLo76>?xD_%csc$bpsM%RE^jH%frc_68kZ4ca0EzRZ)A0etaaB-9*GfTcj$ zpuot6vYkN9hC(O@w1uf0$_5Q~)U;v#HwiPN4+I+to%&v!A@OKc*VPF8=hXpyl< z5`2LtD+2@Qr~>c>o~)4DN1j5}fG)3p4P}F_$@&OogZ89+hq6Iu)cplt^2y4;@CkHX zE$FmrRt5&p`7)eP_8-uRZ%{VqY*$ez8+5j-G?WcG@m3MaW@ThxP=~TX$7|?9*`PD; zjG=5pMg|5;D7zlC>%|$$0UhG!31#~*GBEf<*`Oo#BB5;1Epp(q!&w;^@);Qzz-NcE zGBAM79>|8O0gb$Zj`0VjiB*gY4AoHa-Jttdp={7`osdgDSs55W2ke0_`DA5a03ECc zzT}gYfkBjsfdPEUCo2PkCKCe#_>xan1_sau74RjWtPBjMObiU*OFmf{7;Kps7{Hf& zvNACEF)=Xghgt^OpaQy`804T(CI*JnQ1K`xP_qrnNo8VSxDI9KF)=XQg|aJ{7#JQy z*;Pyo3@@SViA)R(@1g8DObiTPq3lge3=F@a?46)J!l2WzSs54(FflN&L)k}|7#KjO z?F)gn?VMp^V337MTwr2gP=&HDF)=V`LfN;N7#M6oY-sW91Z9J=s0WnI$H2hg17(8> zLGUG?&>|ds$tUy@SnwsETnr2#_4WB64O|QipsjmNAU3p|?}f5Kr=(7SvO#ABgD?5y zXJ7!`60-m*?#sZy06uJ-A94xQc91x9FUcV&8|2WFP&UZSD-d=)xS+TV;eZdO2Vd+d z2)Pa6IaD09LgO`*4O+DWzSt95@o<6;t`=qhU9rj_0A+(5Dh6ePN^}`0JD7oiK>^AJ z6^_Q>Be|iqmK{h!6mpiYE0hg#X#kWBsx!i&Y*3W}zRXh;;?QKMIB0=XI+P76l)&eO zLu!K~r%*P?1EAx->xCpCKKKZg0Qul6lnwF$?EG&~ z)hP@*SX!C^e9aE{Zcb^?ag+=Us!(xIC8+~tgSM6$LD`_`WeX@9)c&=DvZsT}e-|hR zbi1?{lnuIZ)(^@Co&OCwLrMs`AUy{pE(-}p@I{@n3=E+7hMn^bif{1MnX(KFp!x!Q zXQwO!1L&N~X&}AOcE&<5yB-qXE5ICxq3fV*P;hO5vO!h#4k#N`Q=bO0p^cPlP&O#2 z??Txi2R(+eK@I}n&8f)10BRzc0!Gl`(~1lXpfjD>p={8R z3*d`76&V;njcqxQIJ9*Hx*A;wdNQ^FR2<|WGbkJ685<}Y)Mjylvg<*|fOtSTpu=W- zplndzG9JW+Ho3B(Y>=UaP&UYyP&OzV+d|o(Y#ab; z{|kY<#lXN24U#a16edYfHt4jl3@95^y5&LHpvGzmlnq)yQ3Yj#wum)A*`SiH1PnEfDFXxON+5=nP!7n|;0rlTAiC`1|_1iP&O#O zFGJa&_`VKhgW~%Yhz;$`e1)<>q4kHGfuUZ=91=H7pc^2~Ar^B$*`N#Hd7x~NkL5vZ zP%wb5Y=W{ujy8m{LGfw>WrIBG3}u7vi|~Z9LF*g*q3i-s`5y}9fZFHLP&Vi)+C(TD zbpBu}lnrWbSAf`{9t8sfLo<{O@=X_%4RX)~C>s>_)1Yk7SuwMqY>>y+g4nj8`WJM% zGMEF&e%qmJP~4vau|dTdXg>jz4YKSSlnrV^-GZ_~2PeD*v7vpx&rmi<{ZA+xr2a3I z4Jud#K*M%Ipk&X$z#t8}=+OZZ9ZFC(C`dJ+Y*3KuLD`__G=Z`~T|_G=8#FHkzDLsm za_O%NR2($x7Y<@WJD^EWHu#dyOehCrSw55vvaA%!23b}OWrHkhgt9^X&UPppG}YV< zWrK3WJP;d{-$0|MP&O!PHbB`RyS9NZ`E+3bmjQdA5+KVCLD`^wAn0sdAs5Jf4&eJW zT_6pXOHehSVdbYFHYh_gFfe?8vOyMnhq6IY$ppIG(T#xtlzzciXSy*k*n`S{ey9X! z86WuWOg9Dwa3KQ~2UWX@P&TOJ2s(gL$c+JfMjrU?Oz0sP;JY*3ApJmdsCv-hJYFC+ z$S0s_K`0xPCSpMBdJjl^r-L{iknEQSWrOm4C6o=SoSLC*P+WrV%k*Gi0JV&#L&ZVu zhIvpn=*Yb#P&Vk~%vDe}=+2l8Q1)5Sp!hZ@=OzOK!yYIbbbjF>C>wN{%n2wPbY$T< zC>wN2;Uy@W4R&`XC~+__FuVqddqHy3M<^R~>d1E}8#HM87s9S*0G%4i47%LWi-7^u z66b`nLDyXJL)oCFANcM}F9rrsHdBO(gBm|NP&O##n?c#2hK4Pa4N90EP&TM!41%&j zH}6F9gO=@hF))BGYfphnfX>g(hO*ByFfbHC*`RAyYM^Y;g)_}iHajB&Lno9C>RR_h z*`Ol`!FOtUL2kd84HXBSL%0yiE&yH0vmDB4WMp7i3uR9L-8c(ngH9ye31x%2*88Ds z&`lWNdpErp7?v_JFo5sf^kQHD-N_EVchif3VIw001Nh!eF9rtC9j)MdH@z4bJ}@#c zfbQL_7Xrl@s8;S9n`CZvO%XtG72y-fb?d9dbLnCXyFqtlwHEa zz#t4|H!(3VNJ81IObiV2Q1&V&hI$57DCZ~>1A{h{{eX#q!4S&+#l*m14rTK*Gcedf z*{aM849-wCXn~U_l�iz~B#M8!|I6ghJUi%nS_CP<9wI14AO14cfNH%)pQi<}fhS zF*7jaLfKQ885oM8>{ZMR43$v!3D8YKP&Vi=%vLBHbVy_;lnuI;Zw`nJ9kN>vWrGT( zbx<~_P}*4!<$#LY15h@o1UwC8gX;TBP&O#v-+;0~_5EWg8+4uVD=2$0s04(vK?6_U zpls0Tfxn<^(9wLnf(#5oexUjnwBZEG0hLPfP&TNn23-LGQUt0-4WZ&zpgaDcY*1Zp z3uS`}A7?1LiGhK^9m)oko>3q+sIp*SU`T+nL3X7GGSo8&1wuNM@=w%a>4N}wz zWrG~l4`qWKG!@DQHN9s;*`Tz%5XuI%^Or-}pwe?Klnv^PZicc;LFNBWCzu;xeH~3PHcP(WrM~6UqacSa^*dg4LTh3Gl*Ru z#J~W$C!I}*fk6l~B*DPIAP8lHd@liIgM2RsWrKXL0%e1IuLos=(wYU74Jr-oplpzj zU7&2x&LA%+8?;HgJ^;#T1)YWhWrHe@7$_T*(2}5RP!lZ!$_5psc~Ca!!1@v>8`N~G zhq6IaQEgB*$oD-^HYj0Eg0SluKtVAB!eIcN4LJ|W1|0{v1j+`Dh^~UNIT#rjHbB{+ zOU$-G*;0%Q411t#1x5yj15h^Ta-z#1HgtOU9+V9V(WgS7@;@BX=Klbd0As z3FUyQU3)0|H3I{KE0hhYc)X!(aYhD)Kqwn@)lxW=4Z6M>bT}5sp`hb+lcD0EVcbk8 z8+090K9n8I$iPr43~K*}L$0H)hDyXSGB7kk*}04i4DC=hsG{nHvOz}+PlmF47#SF5 zLfN1LD(6Glph{>ll)a9Tfnghn4V`#62xWr`Qic;y4k$h@L)oAdehbP5HT54r*`S8y zGbkIhz4#534Ju?lK-r*?5oQqv1|jIg1|O6S%1xqBHpngoFxwf@&_2T?B5`6D<%w@<}`s5jHsgQ%40|3TE9 z>Hd*m4f8?Nnd$FAl*@GcC{EBF&ix=NV)}g$bz!=GG^anK%Jg~=HD~&H5M?o4K8Dku zv1fWdh|-w8A4Jtm=a1#|XY80B52AKVUk{>QO#cs}Jf{1{ar!f^m_8pwaZG;?qLxgz zkLUDfESTO8qHavT52BV#*H7T|XY`p~527Nbp9fI})8!L6{TVH$=Yyz}>H8Bo{h7Y7 zOczMvJjOU-`t>AEf5sEj)sw*iQ=ZIO&KNQMJ&1Q`h5^3GhIKG z)1Q%NdVMOVKhp=k=@(Kt{g{66Pgh9e^kb}pem|2Fbl;YK7C6A`K~&H5 z^B{_4x_ma+$@w5EV)}j%wO~4b4yQk($MpCdkTJ5;H{@_?G47jwJBL%5amMujIh^W@ zF4NU>In^02O!o&-KGVxV)RpP;L6pJt;~*+w`g;(?GhIB7Q=QRdx_us}I@1h==?6+V z#irNgaSAZzOz#Itt(d+YM72!6528Azv*&ZFGe%6;2T>cQhl8jY)9XQ0!t~`J%4Pa_ z5cOgDcMz2_UA}-*ovBB4`iEI8V$=fjkKn>jR0cnLZyRb^t1N4Of)!)B8bU9_rIS6mg18KL-+vnSQ^RQ=KtmI(rGHI%CCj zeGt_$Jsd<$nO4*CC z4TYRy)8jy50@L$LIn^08rtb$STL%)d0I}7XJT#_(!u20W$YVNx8K*jvkH+)^Gg!o? z`;~DDF#1f7FXL2a^qJlcqP9$5U&g7<3fd7>H~n@Qr!u3@^#33Uq3P=7oa&4lr~88_ zlj-Fks($)>5T!HycsZv!)Bn!tAIdq^7z?J0S8%Gc=65qN_)T}N;8bQ@F+IJ4Q=M_| z^!^G?btdC2;QQI8pR3>$V9c9-A0)MGI(sFjI^%)q`jwpOO#ik{kErBSV>~jwzLHa& z?b-unQAXlEV zE@G2m1fP^D!DI$L2UUW}%y{}kK`seKv+0c2nL!s+E%?kY$z)7ZT!<1s$U*G5x0?mo%fnbjL(K2_{oxIDIgfRRVNcte_y5#Psz- zTs+fH2ea}qn^;;GA!7$yBhf7=x<=jpaQ$u5hqLSqJ$p?x=rvH)W5@0l) z&a1$s%4jlu<1|i@=_^4(=F>mC6aC_{6tOA4-7Ri zGc}lQrpP6aembj(sS(-{peCm1ho+jC8e2^7QRGr$G@8C%kxNm{9PMOQ6Ej1!14>QI zj7+C9uVGVUF*7q}m|n=uB_@yRNi$1BuqV?CGV|k8Qj3$PJMLl@o}4g8XnUy=*Nn6Q2OOD+|8#;omkIJh%78Ckcx3UU7t!LT4k%jz)G+OXazG=MQ=n|n28`M&s2W5l$h2Y!O zq0zA&B+dC$_D8@31x$pc$|l_LBn}hSwIa_ZUzQW8xOqHf*W$9=^KzD zXdHinvOz)j1Ih*k9TRBkotJ?Dv>1gK$_9<3i9^|-CcPY#4eBp~Z&c@HU;uT#OhMw1 zbW_h@59NR?aD}o#4M%S%8#JvO2xWtO77k^DqA3>223ed8WrGGD!MCgPF))B8q;jF+ zpr~vBv7w2y4a|m4O!j~|kdd)TP&UZo8BjJT&gMbcpeg(%P&UZoRZzAk0|UbbC>zvA z+y-TXrf~K^*`Q!Q0A+*9^2?xw2}000{F@*N=*{W(p=?lEdkSTPn&{wb*993EKtsMC zq2i$6{SIY=Ec**(gDhi)PUnLB*p=?n`1_tnz?Sc#pl8g)t&QNjCN|`Va8(JR3fbWVIf~4Lg zs01isXF%DYfXRchLD5kHWrL0`uY$5cIR$)uyAT6-(76pN4vLN*C>sS` zb<i{S3+mjcUJvvO&GvPf#{! zwBs9;4Z3^;yfg!pCqavtKx+!1t1G})yo)k0fYzpfuXq;)-Hyz_0KVc~lz{;hqV=FV zVL`XogMt)%$Ga#bPlNAx7iD13VqjnZ-|;TW06s<C74M=944{!T@D=Z3 zphB2|AqM0KF=(_x*`PIV;OpMSAmdPZ5b=5j&;WD^gu?*JX5h6PVvqr7@ZIlX3=E)> z5q$T%7{ozcQ1ze#ujhi;Ag?emFf4|$L1oEGC>xZ6)YsLd8LYRrjH6&`=C`?T0u611Q&k z)_w?yGcbS-^9C>d5NBWjUHkkUs{R8gL4nq5f)s%+8)pVBP7r5c04+#khqC{Jj_3uk zp$kwHplpyY)u3!pt^uzJkz@efV8#Gm6C%mL0IGPvYeFO$z#$D@6C%mL0IEDeOG3a4 zQ$WQkcuj~T1L*uR2GErZpamu1=1-gt2qy{t<3%(Ox zl7Rt~BTArZrZF%uR6*IGkyG&X@RH#B=j$2Tpc0^<>w&UCV|$aJY|z}m3@96PuK7GD z8#H4AzBgVHvaAnu3opnKpc#`5P&Fc;5fLa`3p8*AWm_>aFo5rkmjs3wcpzMAo z28IGCdnOYDLm8C4m5G6&2FeC4(`y1ROp#<@IK;%j&;gYIEz|3Rvd=LwFie56uP`w% z%!0CSGBGeLfU-f87|WpSr%VhCYoP2`ObiU0pzL={3=G?#><>%~3@1TsP+xwe+{C1rdzM$2Hl?C4Wgz@zYU@crfaX~_Ghe^UJarq zOg{~xR!o=P!0pe-F+CeZiA>)Oq7#8PgAg zs2|gXH*sn7>DoKF)tS~sOuw+2MQnQ3PHq9Fml5F0(FH-xMbMpSkXnj?L2>$Gkd`&m zPlKq1(?5f#oaxfLxYgOF#xpP!vqJji9MiLRajP?WOrN}q8`dwk1og|sSWOJg&CMpS z7guMzv7LQ4cRm+S7AU%Km}_)FGQVDY1I{|5^OM7~vPYL~K9t zmRnYa$=qVP;wOG#W&;C*=@&V9L_nQ!2o2?%ns2w~;#tDRXfXYW0FM!~xdp@Y`5Zi= z)Aa;-YUNBp-PW|yyyWvp4s-3f;_PX_47a%+JPF@3=9nRpiUg9Vq{=o z0Iic|gfzw(oIss8(1jKZ3=E*wB_k-Ef-a{3b>cu(2?GN|Ii%wT4#Qm_HmCw;U|{$S zVnefq7HD$;s87Yfz_5}TyapFk(J?Trhj17``C==S4Vtpv4P}F>v4c=H$iCxHHYl&2 zg|b2BUWT$kGt)PrY*0fGG$9CD@C&NXpF+h!>yBQ7Rsew{KpFTWR01@q^Bu|tbyxmE z*`PHz%%H9g8v_HV&%_C3`-3tzlnv^}h(g(*X>ic~4v_hvs!<&(4jRqYg|aI_{x^nl zKy2`We>MgN(1ef|NE{j+0Z=w5guhKaM8#Jz81!aTU zW)0wu9w!3>XmL&(R06bUvj@rsjp0v%vO&|I;6?tNkhOG+q2iz=5Nn}q(81+9plpz5 z4nf(V8Lcx=Hs~&@Yf$z=& zLD``6D*|PM(uzEk4GIY@C>vCE8$j8h;@Aw#u7{MTR$vY!UVTAqP*z-#aY7#Ki_u^eg+Xx(2elnsi4W^hMO z05bK_36%hKPbWj!pzi5hC>ykHYB7`zN{lO^Y|!eK^-wk_VQz)8L9>wHUZntJh3j#s zI4D}rLfQ48lzAD-0rdvKy-fkg8XRzMQ-Fa1G`kG$Z3;lTJ>WI?0t^hG%^rV1dO_g~ ziY9390~A^uP&O$2@!YBJ6#1T0cwovLD`_7Gl8-}<);;t4eDz< zK-r*6Y}}x1P`?|z249GQ0kj|~2r3Th3d4Gspis#KiGy4Ks_4OM@I@FHK!ZZ1PzjK$ ztD$UA95+JQpvt-($_6D7@H%}F1_n?zn+z2PEli#XWrGSI&^6{lA`A?mC7Da1;-Jxp z)gX4g2xM9EMi57YfdLe+;0635ki-b?J&HiaN5BjCMHm>O7#JANL)C*S{i{$mXnqd7 zmS2Q{0Th+swfrKG=mW3i7hzxk9p(HMsvdNEMm=a38OU{Q3=9lEp%S3^_y15fXdr+U z)GZNVU;s7PL6-}G)PpV*5`>C_u9_5wvO!r_7Rm-K9#n?1LD$x5LfN1;y*`9p5AFk* zLO2Yk7#J9=p={7Zts|6u4YZ^I$_6c!@`bV=gR&@;4Vu4=gt9^VdE%k$UknTksZcg( z4^K9f4eAi&gFAX63=E((R81fWP$|K{z|a9@gHkeR6jDeG(np>H6$d5wMNl@Vx48n! z1|>%D1_3chv~GfmgR=2a5F1)6UVySe^$){!Cj~Xt!f3KY>)>eplnb=mV>fE<|}c42KuBK7(ktTQ;-Cx4h2O4lnv7C z2xWtEi#wDJs&;*$Y|ubo1e6VOXgrh+s%o>KY>@8@p={9o+vQMpB&htag>pbC7Peae zw6?YrDh@gax*y60ov=O?$_CwnFdNDS)t2BL1+okbpd}N_q2i#*W-XKry3cPjlnokl z*$HMxL&jG2gEB%69(E>1lj*yoct8`}+|fMcj4aceqj^B>^~)g2XS#9> zk2d3*>HaZ1%8WMCi(`1y8DCDH9mAu}6yyqNINyrl5n$?dg*2Q&6HCYq=cChwV|mmW zCrq~nQKHk6K@`XI?pPjmwx`|<44YUW4d)rtZ-ZoROlOYcK{T8Xl(CC5nORJCtm4#U zOxa!@$0H)ZVZ;JzBmZEU%$Nwj74ZhBq3i`Bc&Goj($_8mygt9?(fI5^7Dz9~+Y|ttx z(9$+gyAHI>$r&Wh0jfzrSEoTZ;QdgcP&UY*Xeb+GP$HBKYAmKg*`U#-au6Hp&?YDw zlm$DXY>?wX%i@H%AZvC(O?MC*H2A*)RFZ%=E)3A-G#3K{Xsi?5oaSO+01Z=to6}qj z44_RO;N~GMIzjn!AhMen61-rSn-U5c}q8JU}JkMZLbVV5)yzyR6@0NWYg z1KP$79R;@rT{a79Ycen}d;+ndBd5Bc?cLCd(*=|yS)sWZ+yi5UBzixH1UP3Wg4j?8 zfqPx-kVR~{P;pQNSqx=^ng^9oHmGX}-gC?jSyA5#6$fqo>V~pGjqQoB2}n>AZ8}r} zRLOyRVC;}e4%`D{XJ7!e#8yJpfaVOqTdvt5_1aFTIH+Db0%e0*VyB^O(6r4(C>yj& z?mCqH1k`=I3+23IU|@I*W&Z^oZUkk6*8G8cY3vLP=8OysU!me5j0_B*>!5|$85lAd z85sUU#mgBP7(jb~LB$lP(3Jpn9k?K&3!W3?f;7TaSV8R)E=Z7qyKh{OUGLxtLM{dd zP*j2E2e}|EZ#Sqxptgt)lnn~@ASfHu@r{A9L0yD2C>vC87C_mcQXRZgnhV^&t!HS0 zN`N}Jy-+r2Msy044GN)IP&R0UdjXUU+9|gT$_CBztbwvYjpR*G_A&+rh8T!^clfdSP10Qbze7#Kh!-?yNOKobZLplr|t!ZRov)OdaaWnTrQa3~wJ ztn&wy4O-av56XVez`y{W`{QC@_{hM(AOLFdb1^W0R@aMxcBX*h2{eBv1CaYVPs$c_t>}?7=joX7{EO?F34teaF30PfuV$vfdSlO<6>Z_ zVubFR=3-!|VPs$c_t>}?80taG@gtxXv@l`>24#bm?AJiqa~T;Jz`Lxu7#J2YGB9*N#g{NLF!Vv$%NQ9LrhxmUTnr3r7#SGA zTduhn81^wTFo3&nT##XT&`}(q5W3CCz_1Cb`3EBd!wx9>HzNbXJ}8@)iGkq=lr7K1 zz;Fu6c4T5;xBz9lFflM(gR;XwJL5q&Sc5FcU}9i+1eE{{r@w%*LBr|qpzMWA(B2yt z1H)z}P%+8C0MfgkiGhI))J5Q8V7S4=z`z4#{{!uShqC3E85ks>Y)57W200MBo{NDY zj+uc$1;pWEV5ntgV9C$%pzM3h3=B3;s zxEL5pSs56>T|6!Z2GII|El|zqTVqmz+#=zhSwE#5k0G>DG zVqgG`JAmg6xfmF}vN14#=MA|S7=E!aFr-1%|7BxfC;<0MxfmEY*r5}Ipn`>+fuR+u z2sA_ho)hF^U;s@vgXaXfAc+h-C&Y|u3BUMRc%2?GPeaVQ5=Q=Nmdzc4T`+=Q~_ zK-;LGY|uu7w@|hwBLl-1DBA?o0D-bWtLwqjal8x+$&3sPpc|h-p#qw^1@9l{Wnd^~ zWMEJM<$sVw1tSB4K4^N47gAw>r`mWK7?y)puRz5?b%ZaJy`7PPAq2|a!^pr81!X^D zWMD{uvO#r38k7yHBMPBxRwf393MiWkRQ}gNInqoF3@uQ$8WRIUKa{P(#K15W%GPCK zV3-4C+kuX1fwCQ#7#P+<*{)0s3|pY=FwpTVP<8|p1H(}$JC=!o;S7ik+8GNvhUGel z!^^->06LNd$}VMMV0Z#$w=pp=yn?bjm>3v7K-rT)8`hxgX-o_ZOrV|5ybKJpnHU&& zq3m5u3=ASrHmIVKhqCX1E;I&jEazolcnsQ%29;oBW?-;@ve`fz(4cG;W(Ec?C|ie_ zfgu3O_GM;Z2!pbNm>C#ipzK0s1_tmRb6y698fFHD45;`_W(EfE9&^yn*k#NN4B$=X zybKJhnHd^A}<3&Gz$a6HmC%s6R`)%Zed|yI0R)c zWMN=90cEdaVPH51Wp8F-V7LNhgWCAFplndH{sENzlZAod8I&!+%E0gj%GLzUOMHTI z^g*X0LD>$h3=IFE>=0H41{TnEYF@}eL|jmIB`X7i0F(`CMTvBODnZ$x z`3emv`xq+&gB}m4{m;w5aD$bB!2~Mtij{%E3d#n}IXFPspt%J%C|iMzfx!pL2A!rB z3}wf%F)&0y*@~b}f4LXit8WrNCgQ79Ya0U0P8v~Exx$_DMWF@&voW1H%d^+ZePp7s`%hWMJ3}WhXH*FdT=n zvp~yrplnd5^9qy=YV(7Rdjoj@RBS(himzv6V0Z>)?*uK^0p)*?qGO=-I#7u#j0_Ba zq3kE1H9DXz)WQr5uRu$5pzIHzB|1>{FVGSlD4UImfk6?<1}(+WhO$9LyAhNP+U{!s zW$S^;e>*4#wBOeS$_5q5;2rJ43=E)?u>zptQ(i-sYc3}nv(CU~Zs5lp> zq=T|STY147-Gvz#JU|5l3zXf?%)kKN^$s0Y zSp*V?E-qXNWrGsk7APB(=ypTdphR~J$_C9>U4XJdBmUQ+Y|tow{Ua!6A!xt>$_6ze z-b2}-9`08t`z~mm0hIlefq{Vyv{PCXvZPKB$_BL?WT0%&DmrB-8qP&Q~dC>hEI`8XHK1|7dq0%e1i6VyZ5paT!U z8`s4lXU9x{ii74mW`lRei!(5QHWx32N`Mv=u7R>alNsBgY|yyPK`8q&=sG4S8?@>8 z9Fz?@r0xoo4eG|rM zZ&4^4G#4ceWrL=E6rpU;JT-W~xg-MvXhzloBn}$OVPIgegR(*6-7W$Q46#DekQp~G zs03)nEda`v1DzKGWrL=Rlb~!hP~ih*gMvK|$_5qHB~UiVK^5D--{JMk^=B-ZzWD=hIb+9k?T@_vj6bGVgQzdlPk-dqW~`n5{Ufh3qsw&ZPrRV{ z73WX9>P!Xm!2{GnpoRx1@qvcaKzQ|h@a)X=RiAhT7#~mH4bsvw{V|Brp3eQ5SDp8R z4I@Jd7bFtgr>{3-mu8#4ih)5AGCjk)1GMAJp7T0KI2af} znEl-Ld%Aq@c-hs!J5!`4B~G0@A&GB#{Z2;k6i>?ZdRbN*@R0ZR|F(QRO4GsHg-i?~ z+lNdHp?v7JA`=4$-`H|GXgd*;vBh*nRwi*K6XWR@Kk-X2n;4scG=erOC3}pEg73Y4KRipU_2e9klDo82r2-!S(3@nXuDey-&PJrqv?OL_>}4mEl|h9O^h*i z3>h1vjfa~U8-tc-xrO>Uhj{w?ftF|)n;4^;V}ibE$k@~rU5!~ihS6pi4l*}E*Jgns zVu|h`69aSynHZp(Y+`7vf@ZV{MtGPQ8Bf2+&L=#LgO6={WDeiN#Cp)o8f><1F47Dg zJ7}yQI_H!IVndhxfJU-Gr(S?kI1gwJ08}7=&IbXpL6g%A3=G#mZ0HQWHE3-bbhaII zf+8bmOrC*(0koEZQ3g7`p9NZ+1}aTJ5}?ItpwfhafnfoN4Vo1Pohb~OWB`pUgZB1- z*q~B|fq`K)hz(kZ!oa}r2E+y}iDzJ7fK3g8911%10yIqsD%HT#glv%Zq#t;;jt#Q= zITSR5#s=wXCqUVt{Tk^|HfV_lXbux(5NIV;F;pDXxU7V-H-Zk6fwH$TFfg=2*`TrF zZYUd+6(>U37eJ%eQ=uHtd4J16Z0NMgCMX-^>YY$FsC+*HWrJ!r*fb$%IQ<$_9OP*5 zlpz-b1IW>jq2eG%zl5?uXUc)559>jrlc4inzd|K8gX(Z78`RqU4`qXv#S4KZ5TI#7 z7Rm-W4zw{1G(QP)9C%+B4Q;5i)7!XwZUAdq?ih{fO)bpjBJL0j>J z1RxfJMn*wwkj3wy>OsReU%<0a0+1aozn~JJr9KRx$pHb#vAir$HfT%-ynhRt<-mKk zpxbjaL285`7MnoXp!8u4WrHjRPtQQN*nk(;2{AC#gVqy*SJw$aX0yPn>x3XJ9`Ncq zAqIw{prt!dgFwe6f%k6-F))DE{?~xSq4~ZY$_Ay0J}4WMCT2p}AP0e`XG9>mY&B?p z544C0bTtTgPDX@*0puX?oQw#>LEt$V5r~71Kn(&p=oFLwv(I`sg2NUazH z1E@s|8rub_0Ug^3KBQKRfdMp^rw>&RT9*Ref+Yr7mja${ftH4WAT{+8kc0!CVv&Hj zG#Mlz0ZBOEX%z`baDk^)Bp4V#2?so_A^}M^;As^J1_n_622ZO?hY*6AV1+k$O6?pfP9K=EGP;roh!0XiH zAP$-d6$d#8e2}diB;-~@#S=i~|3)YWRN!ofvO!Bj_Cnc{7#J81L)oCCRZc?Lpz`26 zlnv^XT!pehD|l~1*`TE)520*Ox9vHU4XUW#vV+EVHFNdyr*IKj-6oW;nsK7zzvwQyCc;R)fT$jS=t+g%Tw0_d>-%aSz_8 zqy&lk^H6b+@4*uhN|3mJ2o(qAn&;q?ZxIN(>D3pdKlB7ZS8- zWe-xM0`VDmpFr85#UI~6Y-nSW2{eSR1u+ynbD;%svAWCQYVGy-s zy6_7=e@2<<$slUV^vy5$-ZSz{U;L5}wBYbFh-#Vc{E82>7IHF(x-k9mD?WdwKRwe; zUi0}ePMO~Pn$Mq6XZmFjl`>uV4WB<_%k*LpB{2Okh?+B9_${A5W5o1i5Y;e!Gl-Iy z&iszgpYhD}U=Yifq^3%v?87*3&bo0we5LXIO>{U9dM3%5EIq`2c6!<(X#!E9{&$-p7YkA%nHIB z=cfOt;y06EWwib*#J~W;92cxPm>3wq_~LfAYJPKh4s&VH8ccb}GBnhkO5xMvcQg8L z-!PZoz>v{l`@?hm<&4u`f8*rYo^pYIk0PTfXakez^hRbT2}X@Pz#?u%2a!4?lgM0eo%%)}#z09U& z-~&b^n9R%}hW%k;l3_FjvzblJ!2NiTa$``39>g#LGnh=xCO7s;Fq@iMf|kfhLe4l5 zXErspfbhYlN-{zWWi~Z6oBmLc3nXtk-O!sug2~hrY!0)jsR_horY4{v0*UE~LR^x} zrl#Nl1Mq<+Aa^sH8X0Xb|H`i*$Y?ly2AhEA^i~ljp?b7lwy7!l(158a`p|%>sR>#i z-_+Cu!yHqz-nyx&DcbOXsi~Q1J!)^=)YRM%Lj-N5o~fw?hKMDGE=zPZW(H_u6{coJ z#thRxvJ1$lqC3?LeeA>3%+zptfhd!5J-S6^=x3{#npvQ$F*iiFz#Jn?&CM{>n1lAn zAq~lxnwy&op@ojQrNQ(o90H2U76zcug)Uz-wJ=22Yhh?QePJlO+V%iWfpgr`+4u!y zr%Q_nNK7wR5fI*-Xiv4sWCjL{>G_rd?u<6uw_6HCZ>R@NBr<|VqCrP8gGNk1%W^@B%0O&r zuUQZ@G6Fr}!WcAI0qx4Qf!NSq)NT+P+JOO$$T33u3!tSyu+fuaplf}g4P(%BEu$QC zB&7~?We>E8b`->hHdx9)%QB%={C^M|S{(<0Zry>_oS;LD8KD)P3~0F~sElJ^U}y!g zLHh_mm)wGuYl1dBFfcHvg4m#%kAZ=~2{cm92pVx_U|@&`Nr3kCfsR-Ku|XjSnneS# zL0kM77#NO#)_Q`vTnr2hvVsf@jG#q;pzGm5Y|ub40|UczAqEE6eL_~CD|EKrIAVw^dl!P(pp8fj3=EgV z85kHr3!@nr7$hYa7#Kk-5kWqdL|hvgD#gIS2wGqbI{p*XTZcwB=t`h^(2`0}s|I!_ z5NIk8G@%R<2SpX^P9RW>fCn^KA$yBcp$35h0JQuHq#oo4*fl_)h1=CoH6XWw2Q;8* z3w$082e@5Q&j3DL_CL@}IY=CoDZnEj{E!ngzzbCQAqQ4~7pU?>h5#a&XjHmG5c z4`qYeo@G#WJ!mNocr=6`vegST3o%H{)2#X{Kmn$7A!x=N$_A}y-3(=~WMp921!aR~y+KR(Kxt(wBLl-RsQ6w+ z28J_G_E|>A(ms%y7mN%HH=yF6MNIb~?0Rrx@d<@2JoRZ{0t1Bm9hL#aZe@&2JoRZ{0t1B#Y*5q zYxo%$Kvza7f=5z7DW8df0eol;KLbN069WTyc!nR;(PUr%A6moDz|hGAJ+y|OfdRCV z7CcnL&%gk>OA37F5I+OMJSGMPZ>YtKnHU%Xq3n%J3=H8=_CY4d`a)2sT&QPaU;tl0 z1WN5p3=El2MR%AO7(iF?ffRvOG=Yb3_!$^L2TfE%)%;{)U}%K0IhYw3z{5G9vV@s| zp%*Hyz|6of8OjEox(y!M0fizn1H*jqND4m#g9$SO!&0asTV@6Z@Hh`Y1A`kg0|R)N zho6DLi+%XJCk7h7R-aGcaT^GcbUMc|f7a%)kI1<^hEqGXn#7 zmC$jq3jRL3=H7CjQk7?pP3mL#G&G> zEDQ{?V0JwN0}l%WgEE-Iz`)PKz@Q0bgLdERL)jWE3=H5sj{FP^pxgGWq2i$V0q`D2 zeg+26-Vg8|M^I?7Fff4kID!%#3j;$iRDA{u14AT~UBSY@5Dy+n;b&j~o!yoSl>k+h z*-$oU%LaJ!BR>PfQWgdV@a9K;28Puv3=FkUHK0Y#pyi&R&;r$n;JuHa&|+a=0PlSS zm8vWZ4B)+w{0t1B+7Z0>5tP6|E1|)gANd&=KsVrlH$U=2wqt-dKk_p$fNDGN=0|=8 z2GBY$@a9K;1_ohP1_tonM}7tdRaVH_QjjA+7uSLJKJqg#fHuv8_dfD7Fn}sG@ZLv$ z28IC8qGiy&H;{$|Rt5&}=0{LT$I8F}zH*75fuV|(f#E&Wm!O*RE0hhYm>56<9sCRo zpxqVVTbB447(gqhd7etQ1)8ZdIkn{Cx#Gy^{ zi%>SmoEuO!$OH9{p&XD8UP0NQM(_tH8#I6gK9EKXyt9Sj4^$kqu?0N7BnG+Ii~}^L zBnBBt=Yz6AL%QIxCNTyE(D`CgP;t;1;&KpnJ;MditS5*A?J(Ft*&vrXL)jpg`a#(s zhlWDgppmv{C>wN^R3elOY7nPG*`Nk-E|d-0a9Ipxg9gsZK`W(&Bp_pdT_6eQ1Os?w zEOdSWyfPL#zpx0Z2IPnpP&TM}zYfX^+oi%fP_!70L!#{2R)4W?*1o1g)%;VPF8Y0okE!P^f@c z%*sIaPYOfDK_MXyzC%a`((2U$NkHcaOrdO$gKVH|kb~TzY*6pX56T9eLlFXHgBqDp zP&TNMnE+*jTF+@vHfYv12g=?88c8pLazLBR%Ajmef7#OBN*&qkahO$8p zS_ox>LTEXZ4GNXDP&UXxo1tt_bABh34H_uj3uf0dFo15#y8z;Vx;UWz9+VBT>=Bd= zvg|FC4f6eWC>zxK0WWA(VqgGu|G*1cl_1yt@q<=YDnZhLD3smKz`y{$iAf2PQ?%-# z5}+~wd=--t0|RJ(mo-!zwAb7b$_5>X;0E|LD`^V+Ll7upk;R(plr|}Hu#n$6$S>-Sv24Usw$A4 z5O{&A3IhXZk{i50RRuEN2wtG7!T{cf240}5!oUDpfp?n+bccirq^%BKpsK>a0J=Ni zIn*-H{xQ&YOd%Bp26aXT2Jp2^Dhvz;j0_Clp=yjkD=0xLE1_cp;KizHkZu=vu_|<= z9(*g48l=Po-^!%Mz~BIC|AVh(QiB|x0lt<=4U&bx*D|R=Zp8#&%cKUmfX)qS8K^Vr z1!aSJ*RdcrbWkD#$_Aw&@U2W5kdb%rtxOsaM}Ti-s@H%VAp>49s{y*zh=E}eNHcUq zV=j~pGH3~u4N8owplnde-wI`e?z-9yWrIq+qfj=eA9w-E2Cb~P4rPNzgz6tcIiSNS zpF`Q8vphdS*`NaI50ni`y=xZ(!Rt-+Am>G{ z^%xlZKpRXzY*6rk#&)1=P&$x>vO!Bo3_xs9iNwIb0KP%V5E9f@P;rnNUl1EQ$Q2A_ zgUksBwf}^SAeYHzfh0f`KWH=y$_6O{FFrM9U;u6ZX$OfzN5v*V*&sDDp=?mXTmof- z+_W0X2GtQ8p={7H0PxyV6Yw&CdWOAF2~grX3}u57(Mc#9G?#cD$_8(0g|b1LTAzW~ zpur;0Dk>-&G`I!Yo-JesIc(_%R2)>5{DZPV=b*5FmUNocLk63;z#Ik!P=fYP&Vj{1Pv$~lrZ(6Y|#9n36u>gF|D9%(6U_zC>xY`-N1JUnL#Q8 zAE*Rq7Ci{c1})u)fU-e#L>!b2Iw&Uv$_6b=$bzy#BPInY|yICJy3QYBLl;E0Z{o59ZtOklCXfJ-iJ^&C_z1kvOyW)EtCz4j?YjwXkGA6 zC>wOP(SIl#)bwTrUDIO$*@wUlWrM1FK`6TgRQ`)XIiNPV28azx1Plxe#!xmWg*&qkGLD`_R;sa%aPE`zovO$f^2q+tr4&tC}(12wMh+S_58FtG6ajX~^KjabyD)Q?u zK{=q*cn8V`o%R8~1<3|-boV=`IB2u^4=5Wn#>WJ@X~%|v0kjE)2g(Mmz7U48k1#MW zfG<9>fmHDtP;pQdZvu1S77JzDF)}bDL)lJ@3=El2whJQzLq3%42D(KDe20(?;=| z+W)Z^$_Aaae;CSU1|2R6Wh*iiI28P>Ewi6Qr!+j{*gNcFR6NnAU zGN6SqP&Oz%v4HOovV+ve{Gcm%>>vvn#Gq_Yhf)U02KD!pplncYMgz(Q)r5LbHfXM(#WJ91)R0G(5K4k`}X$aDqD1}$U*Uwq^QX&r$tK5~NGPYAyF z$O&>r4*23DC&Fq91nl{hH79#nv&LOGyd$%e8)J=sDi z8&q1AL)oBhT(wX($oI`qHfZ@zCzK5;8~UMakY}bs*`U_ZY$zLauEatSQ2Fn|zyPY9 zmO~{#_kyj3vgJYBwV-U!jal2FY|ydGr$B7bJOn9Jd(DFOb!R8<}phapDP;t=0G&v|6 z)G$$jvO$~Jw4iLzJ|hDt8+0g&8Hio)#=rpDIAjCjxG^w*s$(Z88x#^AP&UZ-eo(e9 zXrC~Y4Jy&1pllD&K^IWAHzNZ>A&3ns@Ie!rP&O!pnxSk^2-WvNIiMh#3T1g|b28Kc}H=&=k*k2)iD<@bnRg z1D)x73uS{``UT1cx%5Aj4RR=(7~}#=kV6HbY*6(o0cC?6DhFkQ9I6CmgVr0Gg4m#8 z5e5bZ2Qg6l-v?4ExkDvDmIXoCAj=}5Y>;IsP&O!3vY~8{Wo1w{sJT`PWrLQ0cR<;o z0gZkr8x#^#p=|I`?K7bq(4w|AAU0^el!1X^JCqFyiG5Hu$Z;p3Y>?wFK-r+IdmG9I zwR|2y*&xTgfU-d$@eaxcwI9ETfmTxbF))DU<$ggWK&}HF;t#qz60|OeO&oIByj7 zbP<$&5Hy!9pAj0_B0>Y*Ia%}TqV>`$N@5TR_)KG0)O_CH1jhEq^BsC{r3 z#0Cv@GB7Z_fU-epJ!#M*`RU57APB(&AOm$P{lI=$_6b1o(5%u67n1< z`w6K0Uj*fVQtt{V8??uB9h40^-E#|+4Vo9;1!aTge-A*}pu~F&$_6ddJp*OigJwXX zY*6uh1Ih*^%zGd<=nhfPJns__Cy0R|f{}sY6_g##$iVOc%1&WqVE6`QgHAyD17(Be zc^M=b7=(ft7(j_s7{mr04G3y_L)oB32dYpu=oC)_C>u1yS8opGfa1&+$_ABg&QLa} z<>L!wgAUybhq9X)7#L!qY*5{w3}u6g*i0xJwAeWx%H9pS&I!r}HD0PA?0N>!xgCuV z4tVUZ9m)n>P|*uz^Dr_nOop;S1;|V&8+4=Qd?*`qp4d_-8#GP78p;Mm(?%#8bj-(g zC>s=IdqGzXDAzV?ZZzfyBO5|{}1JqF)}c)Nzu)I|gNgI;Ll!Y*4f85|j<9 z*lvK?^^lS1dteR&186bH6DS+hMtcQigF2}nplnbz{SC?nU1<9U$_9;+FiA5o2t_b3 zfD#%9lntuP_@Hc1WhMe;gF2>CHc$?za8Q7FiK2cWFTn4w1#=Q0!Zg413?SM8`HH71^t;+Sf;IH5t}~AP|#w!l#!ss z^hY387KmkJBxu28!ZICvD`Jz8parAF^xZ~+psPi>jRpOgRKEf`g% zTbl~{Pv6ADEHQnNsh|bZ5w__UK-xcnWLc(bn+f_e+DxwoQ9aX7n+f_e{a}X}HjAHG zV7imJpa!GD^lWoM(4zI-AWC35w}qfTQw-pW zMS_i>1(2Yl0YEAk7#L!vU$zkRXWTGd*;3G-QDJ(qrJy>~9-iqA3qZcG6trLrnEo0h z#WCI5O3 zOnx+2*l}; znJxgj4fK;e*lpSlg8pnNvJ4CbjME$LaVbq-z22l>ve}kwA)4iPq{TUOc&jwK}(_e!q zj_KAeg8r;L+6)Xi(|6}_Do@|!BB;SwG5xlSpg$9XE+|n78i1CPBE<;D^k7#((C&f7 zu7dtdJqFXk7ngFm2?{VRFqj@Ni$zRm22=~^fICn;Zh?qTj{+$=VF124RS0x^5hyvp z6x}eGo&dTtbd{T+fYuWO$mx+F-5|^YB0w0lWEFIRJ%|m$hG4^{{{m?eFodk=1Brt$ zOp^(kCLKdakbAic3TQbPLPq658bBDP33S#FvhxBAA<;R@T~L521!98G95j zK|KAIhoFGg7emO^hal5I7-mBbnkEq=$aSn*o`M2QI!4nKN;$=ZKxg70JHrL4s0ySg z2CC=^nn@)P@#&{Pih3X%Ar8 diff --git a/tools/sdk/lib/libesp32.a b/tools/sdk/lib/libesp32.a index 6485746cea41c452ff10df7f55bda19a4b824718..9b0b78382db4480459fd364d2b3329b53bfc0307 100644 GIT binary patch delta 81624 zcmccgQ|`kDxe3zsMg~TPrbcE83I+-wfJ`bV7#kTHfkYJ)61W%`7@8OuL<1mLw}gQK z9ZwBmU;yELHy9X*#r0SeGUo6wfbmxw21X>zWVeO^E6)DHzy!h%uP`tXz|6sO7?@Kd zAb4s6Lp}4<1_n|vOGFI=98YOrU?GH0e_&w2jqAaZtc^YlxG)=I1Ov%9?F$1N3?H7s zz=jihVwYsM^k5)>Q;Q4Yi&IPDlM71Y(~43HC;!)!n%u+`IJtGd&}LcYcdSAn6$OcT znaT0xDJAj6CHV!Lxi~*FGwJJ3X5`hKtjp^wm7HIc8lO^{TcDS(4@zi;CYF!{X*gM7 zo%rT{(P!-J2mvu>Gee{4f{DzU;xmL87#Nrt7)%&IK!ZVvL7qW|;mh>K6KtZEA|fK} zW{wPv3=9Vp7&o(tl(&5V0gg6z+(lWWj`=5K-6i1WHdP@>(7y&&ez1q zH96-o-{dSgo_aAR1_l<86$~tl35*O3Jn~Fn9-LreWXod$JB5LPS;&}yfq{vUqYOkb zu{wb%_PGoU3@j|HnRz7)%y&V~mWl#Nu(1CIQ5>x285tOuIM_KD85o%585tN@L^VLF zKvvhY==w7-FtDhj2(RaO?n?c>&57VBoj{;$MXFIT$!tL1tWHtYWBV zU|?ZnXW*y;30#IKU}R(9NC#=S0_C$ZFmOHx*>II{Hv*AQJ-vqY_99UvgSH1EXm@$oc$+ zppao;VBiC3GMUB5z#w49$iToLC}$U12qglp)keZckw*2?hpHgmLzgHj)esVtNc9Mjju;B@7JWlN%IO zO+e8C3pEf8!`Q?Xm>3wC7_Ko+pV-JedHRIqtbUUd0_QOo=O<4V3>2O$qikQ#3epcs zOyHEw!o>WZk&~H$k%f_Yc^xMo10ypdCpQBlCl><)BO?P;oh>6XGe{9LBPS~ZBPTmZ zEIX*cjJ3hI<2U0SDiYbQT zjQpY!1yCL=O)M&jFR6$xPs}Wd&rHcl1?$Mn%PaviQj+rXi%a6u3Q`zK^NKUm^HNh3 zk~0#Ez~$Q`K4EXL{=9sKiju?}upy{!Ff=ppWhlsjNnVel5Uyxc9 zUs@brP?XOwxlvqYdQBw@hXtqvjnB=fLN&|CmjPK1x)F&51=AnyVl9}wj-SgF?qGhUA>={0r(f8}$Ro%M%CVr* zje&tdnSp^pX}X*=v;5>uYNFF)wy|hTZrIPlgY4Aljp@u9tobR4C5e-B)RiYsTy%SK zjE2MX340g=rY}%obeJBnhf!g=z+Ogy=?_#G1*Wgr$s$lM%fJJ*8*F`yX4_k*%Q6o{V)VlXf;fQl0#25trhShc5@j2XPLpg;l#E{Fk1 zi-@E+`KG1=s9XgVK;R6*zyJyHb;FI@3>gvZ(NKFfiyaKrkc6^nzVXTApkmKY(f?28eNtAO}F*1Y?VW)POw2zyOW~ zMqY>?Kt(o8jpp>=iR{YtE+C~)BLa}vu}JI`Bz86uy8ww@jl`aW#GZk~o`=L<0%4nh z9kvR>0kbzEv5z9LuOhLZPJh3ZO}w5JREa>{E{eofLt+~tvF(xAK1l2!5E~S(3=9lm zj0_CIP5!3=9liPz|7{oDGox`(p_bdkcsSHE0)z%??(=un(jc z%03AahpM@T#D0jxev8EZ!RWxi0Ehny( z)1SRyl%3pNz%%)N0ek&pkToDB3=9n1AYD)=eqdx^5Q2*Tgt9^2{tsmff(jW>(}0bE z0n|(o1+k%erJ-z)dQf{#h#ivRK>@)C%~qgn!zjRjC>LN7prp(Q%_g9%$q3EE;Pec2 zkO3%tuuV?TR~CU0!SXzJcH&W`{~mkF{w*h zL4_PZPGewT*ul%d0J2nJa3(@U?h z2nvDoJV+FZby%hcEMOM1I)G-lfgl5e4K%<&9TS-0H_;3aVVS;Q0khb2u?5Tm^*MqJ z44{Mp@}UUSK#&jLplQlsVPH_f;=|`qJun~65oBNh#W2V`P+1Ri#1E)>AiF^Rn83!s zu$&28`+~R(44|eo2s4AS8Uw^pAQ^Mc$s5*)3Gpy8FhEl-NR*+7bMgfdv3fbEYOojs z1H&p#1_o%h01JUk1TiGR-4X@{m@_$q5QzcQm4P`^8_m33oD2-01O_q#gkk1^3RD&b z1~IsS3PKQtAb-nFk8fp_W;5bqU@&2vB&)=m!Og(1fsuhhk%56hbh5szG^+$J14Gs1 z?Ivolj^%WN_e|o9X44gXn6#Kg5+`ez>d7A6yl5iGQV<3?5biMn1_qJoj%h4;lb@P8 zGCrByXlgw<%1p+=%#mRtxVyQ6vqqw!OW=S4LnkLhWRWIA)9U{av8GH=uk-;2l;q)p zbwnpunaL_8LWLoM5c0q(K}7}zgkSzglol{3JPt5WU{FX7U{GK%WMD9OF08Of0iwy4 zYtaHm2y@fn?>rI;P6``5nkOCpIiYECLyLm?3=X9Qoa$0cX;rKcRSOvy4l*z-ICFr9 z8zP_Lpuk|H#L&`X>ww3|XMu04mV= z9N@A6j0_AqpyUS?=M{o9qd=Y7X`s%$ITHgzGpK|EnFYm6jBNSb;9h(d7Xt$m6KggH zh+=QzW?*23^x|1sxfmFjrGgn47?@btZ`Xrp4%TWma5p}TnSp_&A2e*B>j8387^thv z?FeG7=3-!A6;9y{2^96}AaDZB5IS&~a7&t)$Gsr!+I2jnYIN01dLEY~|ObiTc zo*>&9xHUjV_<;&M76ukEb_NDEe^4)&1(dkig6lvv4+~2!XuLoS6lzQ??2kDa7 z7o^@6#FpT02AOFGV#{zRfz;cB*a{2+MWCiDqaKGxC=&w%cRDu%1BWMw$-u47#lXPf z1!6Y{E&+-AD1r(UMnQg_$r3g)M!_5m3_Tpdi$MBjfQ%0TF&VgLfQ%0X8PCGa3vxo( z3J}Ttf^~A5jb8m9kTgf}E0DH{Yzzz>B_JjP_gat@rC@Cg{4AhI60YWEVEDjM#AwFC zz#t+F3gt3JkOBsgRFKAM#%wkQ1{RS%kPL*wA>zlwz`z0F@QCz+oK*|fBOu}c;?&nO zwy-iVh=^E%OlSm4Nr>oyBBvS5krD9*scT`}%F4i?AR3=rz`)VQxPzU6K}CcIO^bVMXT2K0hC1|mtIfa?R>VVrF2-;Fv6E zr(XXTB)uIp^2WpcALNf6AT}Rgd{P<%$Ihcn3=9I?UqEVhfr49tdlAT@y`X52;T8f# z=0VV)n*#SukWUX!WMyDb;bsP@IeLJVfkA`Yf`@^DJq3M=FS(Nlf=Mr732mF?if(8-T=8FfLjEl z{$?iw149V+VUYL(5k>}v2<~uD>^}nK+!$_!$(r^?Om(c2W9_Ha^MW+UGTN{(FbIot zGcfRQC^CZ5jR-igDudY!BCH@UsDNXRMI;R5ZdGuAaxn0-fI^v{MTL!lLAZ+LvpaCmJlnA+io+ehgR(4+B37NV)JG z4hDt*js(UPAaiU$A(;${_<9BgkqnUD6h=_su!u|pMQAFR!z1DeQkMqih={xZg+V&l z02vWgkW2>HautzMP~c{Qm1&4f2bq=y<`{^~1BGrjm}4Pw0pzS4Fvmfp3Y1H787CJw z#@73%axgGRcY<2a(hZ8TtH3_Q~23=9ms(hpb|82F^8voSF6OP>U{pjd9QGca%_ z{9tEbkYWK<0h~!EK=wx0gBl{zhgldH7^Oku08G-AoD2*s(%m2@N=I-pFbGJW4P9e z(w(3@ARWpIYSu9^GEL%OVPN3W;Zo?Ce8Nelz7E7w&HzONUuG%;mkNl4u|N_G{45}kD}zd2Mo=XKX?HWuVdQ3D zP}vO{OciDX6?cq5s-XTrrvL+kDrnqeiU0$HnjHfJ!+Ze-26e_LMgs;04JlBQd_Txs zP%n#dP5=)BgXSM*1_s9K^;jA=b!)sgBB=w&k8Uw zgmJ@+Rn=!;V7LKNWXiz6@EF7Zb+X@q7;X#<3_n5IK#e9AK?a8D5N%Aw4C;*0te}L- zz@PeYi}HzLb2l`t@9Rf1BkAOpi`bQ#q~1_lOD=&H7ZI<0~X4641Lo+F4cnSp^p z6~vec>imEh^BEWztU-(w3=9lzf(#5=pdMe4AOnLN57-~9++eqW9VIgPzpG;XG0+SF zXwX4J0~A0%K_LbjcVL`T!Nb6ydIx65BT!ovq)wZGm4SiDk$E-`1B1>+&{(?jY90m# zUA;^OCKph`XJFs}r2&v2xN*nAAOTXV{|S^1R>0c4jB{@BGB6m_gKT-rz`y{S^k7`K zj+cSK5XLoX;bCB4n&@Esi-CawH2dPg%fMhVfro)X802A4vSb4lji6?%t12%8gJ}yF z1A`F*1A}QL7Xt$*QW(sQiWnFyL8E63R7S!(mg|x>4J{;lG2{lEA$@4Hs4SE29oCyjbsd}w> zj0_A51Q{5<^TESIYb8{Siyth;Xvm-nnqgcG3cm-83=G=@85q>Sa?y+i3|gQ$IgpSg zLg)`81H*nn1_mFnP!yvfgBA-D1H&mn28MWq5D%yjzADJTP=pYRU}9i+AjrVb2@zst z1|?GlEl_jswIBn-T!=6eM+$>#2@?aucR>aQ%PP>=1_!8a-NO%UP%tuRy09@YFnWM0 zC`h)q4smp6V2l74JD-?9gDf`d>p?ZtKPFI9j-!W@f#EkyzdD00sPDyP!zRGMAn}@? zfx+e%D+2?!KBG8D08}N|f(DHk{XrSc_C6>_1%R3BSs54@1HsH4AQuFInV@bGV=$O` z9;6@yRLI&2)Pr(*D2UAglB*PeJKy#cXs9x*MSy|9E>nPk!G1n70|N;28rpM#syq$` z21Z|p59|yKAj~(H$^JVx0|N;2E7`kqF))BIQ?P?6D+2=v3n(+%M{_VRfUw|k`@LKY z412li85p=;+6!|qFn}<>rah?h0m4F(_H)@87(kd`%6<(y0|N*P-?evRWMBYc5nX#l zb_NCz7S*!{wN*h_Oxhllwm?{1%U+v4*|Cj$cr3*NIo#mv9} z!kjbhH*+&EfUuOaBd8e(!uBkn-ZV1uh3V1kJ26FsOGmF)}boOmvc9V9)?f)Jkb0W>!HH zty(a(jKZ5Q`+70fgGw_-Q2ozfFdszAfa+9+2ylS_n$2fqU=RaK+k?szurR1F28l6( zOIWZFsN@9+F)<*N!Nic1fnqKdY?{G*5IvXC7c{&Fw=Ij2fuRa4k1z%%hGYz=7(-VE z7MuLiUn>VTkO!*aKp0fZfwDQMT85RsU`Im1Hyic3=ANBHK1|;q>zDu zK^!#Z!f=ZfJhu#*Qr;{WIE#h7s3ci0gMn%C%Fr%e(4;1Kb%|aE1NUUZFfpcXrpcaR z){>K%7@3)%Gsr>=AhsxYrkQPe0VAVWxHRvRq5+ zIk~{1$&EElY|N}+KS8Wy<`jh3 zGWk!qJ|q8Rod~t*s@-e?_3>#r`N`SwB@C_+A@QzZu6`kg@gYH;?hN?_@gNz7_}t9m zWY8>gxJw9lCOybC*fj(^^POIhnIE5$TAa)PRvKTzP!W({R1#d0SX2_6oROMRnv+_@ z5TBnHpIVVw5}#OMY1G0KCd*FA-+7hBtJJPzPKc@B$Xk)$i!m$ z9&IMch+r2_|9DRqAJ=$KzYvCa&?IwWPJB{n8e*;;G>;9QnFeVtDq)DvNlGiutV(5w zPs>S6F9uJ%mKSA~q{e5KhcaL{*bqaN72z3mC`5ly0 zGV@Bn%aFj+vhle|5SM{v3X;M0F~rA*`sC-OGsNd673HMnf$T3yWe9Tha&-=Yy0;`H zzjXS>N|r*y__Tuj;`kDV__VxYhWO2!Cr|k$&D{hNvwoS ztv`?Ebu3CPF3l-{&$%$;I$qZ?wdC8DqtV~I)WQflMah>w>a~R_DQY%V8Fgjxhjxk^z>S{QUh~!PyD4?gXL~65K(li7D}}ta*t^IjNKV zV--P}FEPE?h#@|{EHS4vl_9>sv>2STKuZ7;3zER=roIWV&fwEg-2`GaaFvNqF zA0Q=3NWzQHW+=`nC{E3p?3gPe93NkvoPnCDC$GtspWLutygoiTC%-tAp`bJ;r?dc+ z98xk^lEmU{0ptRspeQwYvO$#naEtALJrXa?4GE zB{xv~2F1HZ1b7Cyf>LJ+1ISfHsi0(@nU`6@kd|MNng=m2H$RU7RJ2Zh7$s#1PHyo* zu8zU}ehj&ZnR)RbhcT3eBo=48q~@f8VmrPVl)vJ^Wg-J8Wtm*hhHUQ!WXT%K8yoWbB8;OQS9GW~)i ztBV+@Aj*ar1gAbf7LCc95;`7te;!7BO9i5>%@{&r^CZC9rnH(4`;S--(9G_f~ z$Pizgnwr9Z>OoN9n3$IWtsaU~Q?tPZHM|J~s@aQ6Qc{bG7~(;(JH2QUTifJ1H9H9?(<(N1aCp+#Fo9v%z!wG8Gg4(VQ(+{p=l&%N0i9uWt4QkGEXfS|RDS$?dK;owv z7#KipVkHI!22lGKrUt|YO^Ack{0EH?fW}rq!_15f48EYHatsU%ptdqhJ*dqL8fOEk z2Q~J=;tUL43?L3@nH0zZ&`KWAkPV0p8U;{=8U*U~gO+`O#G^rdRj6e#&?OQe@tVmA zX{&@%a}xDRQY%XIK*b8U_?cdq%PuzADE-Cs35tvglWQ~-rcc01NQ<)M2KZ6M< z`k@wr-0#fe~iZe#02RMf~KHB9$*6H8>oRG^Tok@i2dLY)&dJaRDcv1qVa9f z`2J}8cr<_B&eiEE3+UikI5_r zd6NqYq*XzyRzNfFpo|V$qyh~!Mo4Q7MHm8a=2DNnzx#LmO0GW|mYo46r#Jx&Qo z)&k;n&`>2KXb}11 z3|gSg8jM;HMIcu*YD3r{cQJx=F+is)bSD)l*Xuzf!3#k_lUSh1Qjlq&`2z+9@DK`U zmI9w&1_toLQP30! z17sNyBh;Mw8jzu&c}~#G0f-G6T4!Kj04>pA1WlDNFff2ul-h%gXJD8EQUfaY7#J89 zfY_jE4F(1V(B=w8sNNeOaqxgT0|RJEfDy`m01|hHm;fq?Q%KL)hTOUZ4#a3=9l^Kx#lW2S^Gu>;zrZ%)&T1qBy7?6cHj4 zkd==hHa9dWg64%l;-Ix?AT~ENS%P8=Bo4}BAT~ENiGtQ6ihwFK(4+}yaj_(1l?}+% zAaRg6AlHG|pjDM1kBNY0us{ZZ2E9NMpangk)wUou$UsoK1hGNI*mkI)AoqbPPmnk$ z<%1T$f!Lsw{~oFav}6$EZxJrYxEg3W0;C4KvJkWhM3R94lp{hJK~u_-3=E(p4M`vg zF38XrXnY=|0W|Z|4-%JTU|7SzzyPW|LE<2XU4n{(G7@NgDo7lZVV*(7LECG1m>3v9 z;-HBmIVk%GC__NmCqN~bKa>N?VW6RNkgGvsxuLlaGzSL~2jwRan;WD6y4oHj4vJFH%KLh5Xto4VAPG?30I|72iGhKE0hG@` z;-I(&vALnS6_js4;-Fj$VsnFRg63S1I4BE%FgIwE3zPFn|_Ffy6<{7{rE&gO+uJ#6gCD*xb-k0W`G-5(h0=1+lq7u4Q0g0L}D) z#6iQKAT~G1>kJGGpou>b$$AC`P_Y5xa6_{^Xd)1#0aS#5*xb-!1T-%Q5(haF#O4Mq zFkxU|05x7f;-I1h#O4MCAp--$E@)x|t;Phgxk16iz`y`X3n2BNBIf`o{<)#$&Sj7W zE(Qir>b?eIOG3&b5F6$=P;mj$3@VmDY;I`L1j_v&@d*qJ3?Mc)w5S0M7lYChXwX>; znlM2{7l_Sm2b#eKrADX(s2l^ejJTm?nFUlFRHlL0+@J^r&4oh6LFF509)TNL#zjHJ zL1i6?4RZu&6dB|QP?K~9R1K&MoWaOY&%g~W{1!tcK)wR8Vd8s1;#>?2pf>DbB=#{V z83Q!Q68(N5hT2&x%P+gC=5XP0yKm3WV(GSlfvZcDtptTNAGr5u2 zG9Wf2t>D(s@in63<6sSAy73y{$;>jY#b6 zAT}ueL2 zg`^44^r?6~NCK)z0g0^zVncnb2h{+YNVNosL)AMWv3)^osQN&tdQh9P07<+ADh^uL z(hn5}r9Xy6AP#6T3>w_oTw~I@H*15>@Ap%O74-!xblk?k^8M7u&Zr5ilntZrjUlP># zU5cb~B~)eSWbO{*dTxG%8K9koFfXVhiCZDDeUaD+NbF)Hb_)`_3yD1siM<@c1_vp_ zUJwWB=aV2dv@?1O#0K>!K$Sd*4OR08iOnOxzyK>LWRch!NNi&ywjC1NQ=lH9IRr@} z9*JFr#O^|3_aU*TBC%&8u@@k*mmsm%z}O)FZ-8+a7#OxAv3Db}44%Oluc3~C4t zgBB9o5Q%My#I`|VJ0P*$C);<6^9Cb{gip@zZmyq(Br*$$y%34L6p6hCiM;`dy&Z|Y z8;N}YiG2i#eHy|}1DB2GAsjIK8WQ^!68j+%`zaFp4HEkU68i@d`_Jb1o*c&M=d+k3 zrl(u8NKF3S%g=aXI)4P4xD=?E26gvfIUCf)gEkKxvYE`MOTT24nB3jxT>l)j3JTf? z04*tp)%C%kHB-=1=o2dggAi2BA1E8tfn{TZh=b}TK`0xPi6x+H(BeoLC>yjjSs%oP z)M^Z-5OzHS$RKM7hXFJQ?g(Xr`mXL!HmJMj4P}Fxa&aIw)Nv_LHprYTC>!LU0w^2Q zb1s9jL7n0nC>zwZY+|ctU=ZSBU;uUNI-nAuj!++z4eHlSfwDoJ&sk75s6V&>$_8~{ zmqFQ}#`zj38`M$V1Z9Kzrl3`5AiF^Q(S1SI2GvO)dJw@@~y_w^ad2Bm{PP&R0kg^3;FVNi9=!Op-?53&GM7xO_S zK%Gp`R#%WXsQ#6Lii4_F1t=S|!$A$o234W@P&TOAG=;K3ol|Ql8`K|lgt9>kK;5Bi zJ5b-z56S^`Lc^eJP?Z=1WrONG(AFT3gFvgIGN9t1j%Xf~4O;nB0%e1jH$mAIpoQ~L zHmFAIfU-gBGW)>ndIkp2*w7R(hk;=#BLl-MD0=}T1H%F+8?+L0HI#jTk%0lUw+ZAR zPzM&Y2?xXmbz1j9)qpy*N1$v_NA(nx4H{#*0A+(FZm!isIiQ7_cc5(03e87QHfZqa z1(XdMe0m3E8!$02e1WnZm>3v-LD`^jD9|AUAP0fQq1ZSe@eS&S@<7?3F)1M^n-A0> z6@zk0n5GxxF{w@7Hz{@c|2fR^)4w?~IZke#JYhP20h7dJ;VJ1%EjE*Drf5ypGZ2}) zYl;Bt92*7(mC5I)D6@fvayS?#|Cpl0dccN(;mBn9sme?djFSyC#3tv7aBzXLC#WQZ z2niKJXQ@zyC$E|+z!))k_f+-z7JJC{RnV9hD5rzgr-Q~HLDNp4c@)r87|6U5M#xAr zhz-IZbs!qF=@Z0;4tFqYv4;#OgUkb&1Cj&LpnZ5C^PmGn44_T*lE|k@fE0ohfQElS zG|b`)j0_AlliQ~$vx+!?SnH=LGx@Mg%Vrdt{A!v2Qv%C$2M;DOp~s-1TabgGIDuvQ zhEgW6$yU<^m?pSR_L;8623kHYC^WfZx)K|UI|Boc(BuWvm6!y@Cm)%vrd1@xzyQju zQ0<^G1Td2yv_k-@FJY}coh>9OY_YF2kM#m%^47arUr(a=NH!=D|1U*c}6dM8g+*@J@FJ28RFjfBygf|M>s^|MH+oWyZ-5r8Fkry0Lik(wirk zCfD9nte=#D*mm5oYSDs4S0NjB7cG7PVaR@fo|5%|gF#J-f7617MGK%>Kr7rAGBBLw z0_{n5+7SfNpv$$v8oIZ5)gm4Vbt^_5j$M;y?SRNaPu+54U|7r2$iOhU^iEPe_^_@A z91Oak4bcY_7-n#Q_9$C|w*Fdzm!xBLmj)o=y9?uDr1bmq%cu!t1MR36i z1s;utCV_^{%@eu>C(Ke%P+&<=5^U&HP|yGcly-v>h-y$0Xk=i3lM5Lb7QpssgTgmy zFY|&0OE#amE5XFrHu>p&CB_?*IUayEHYhD*lKlWCHupSGVPw2EdE>)qz05X71|Ci~ z1_mC}2h6rX;Nm5FQmjz&hl$zG2Qn2Z^xZ)ju`o6fh9Sz_|4#~zI9z^W#5J;~9W z$`6_J0d1{zvvgg|4MOpF}AI6=FwSsmCJ7+4xWdzK|Z(+w>BpnY~ypjkL34%Yji zg2|GTfq_j9w7!9bmxqCYT@+%b2BjTa;kGPFz|62b2BjTbJ}w=FbHsZ zb2Bgqa)O4dggA{rr=D?ku`@7;a(>`pU=ZW{!^6NJ&dJNmz#z#f$;-eX#rc|@fkB${ zJQo9l0w-vN$z+pfYW2<>3=A3!Ec(n044ex<%O*I$KH-vdVPat5GzFcx!RZ1TRNxHe zWnf_9OyXr=VCF33Wnf_8Y~W>JVC4jjb+B>H;{|zSEicF;dw3ZbI5{Ih8ypx|Oh8-y zRKJ2Y&VWtkmdgN{dVQ;c2+X5$nZ@T zd@foKY7jGUf;PD^a)LI?Gcm9vfcA5kEC%f~g_v&n4`g~9sG{X;1`QE$y6}VCy$ECy z=M>OB0!~d1@YcL7JPZun4riGd7`Q;^J;;%qN9sX4 z`#HaZ_V{sL1f?}j(9j<%1IrT7PEIvZ(AH(H=NwS0 zhjTMC149EhXpcSvBlj^-D~XBwAE^FjftlOj4l=g`RC#mCae#XMoGqYT1DtBCAcNIF zfzJ7v548RR;u5~VG?0!pU>!fefwmNs{GkT&CAEU2uYr1boU)(+8BWlKOeO{%7QP6^ zepUts-uvtf41AG{pyfX-OmYmow?W&@q9A<6dRYcu&@N2AXsCb;11}pt0|Q?SlrPP| zs|PY57Rr}m;ML<{VBm{`@+BE~4=^z>@Wn&<5)8c2APW+pd~pWe|Dar!2<3}0@bZGp zOM>w08ATa*SAz^lh6pfy}Jt$Zh_(2U8W+f1t zMF7+RW>yBVIruYE8JJZ-Odf$(pi_@jL2LnmHK0Q()Ie+zfs@P(49w~vwuHcCP)61O zv1J56W2VfSAhv=4=tKx+Ef8Bp;50~$HmIc4U|{)K&&a^QtTUUHfr0%U$QKHXs*Bke z7zAQL3&+$zOa=iq(7c8^sM9GR2-@<^2)2QRTU0{uENI&)*b){-5edQ9ps@q6JuE^@ z5`v;2joKh^UGeK-ud+4Rr`x4s>t{<7`HdUfBSUw-$j-13s(3T7*rUen7Lkn8UpMfpMsV~ zFo0$<8Rxv=U|^6`1-W%MD7r!Wj8&^aY2zR$6|n_PW(l6mA_>|7T+et2Bm|nKRRYx> zKlm6J)Ib5n%+J7Zfdgy_qk#%zG!sVygA!5P8&A^16d9Rxt#G9%rI~sox{h&P|u(TE{AS`3b1@e1_nLQZcWBp zpyKK_BLjmLr~m|I4AACo#{0Lp85j&+fZCU!rIkvc&OA8eKwGj|3Vl+4MGqfRG2f)0ZkRkf;PM|LYfsu%nS_5pcK;tO-u$147$rf#nA;& z3mBx)5$x*%-g*WGNl?R%@hT|CEnsF~FkQ^WzyNLqgB;5M&LyDGQ3gdxFT_ArX3#nj zP}1hO22P$JBUKn&*%aUS&(aFYd}fQ4XpGcGXn!?h?{{Iq!3)ExPwFbFEay!6sS-Et-g{4MG~Vo zSORonjX5X^K$74n@L&Wd8Xr(2jsf8%2175oH67H%Hv^T&5CKc@u5Js^sUd9O zken|Bszj%N<{d%xjXHzXGL6|R?(Rv>X z0|N;2Eo8LW!ok1*!mJ85pxyBx%)8CTft7&)gjrRrLCax4m~SSdwGQZ50#MWSB%=-J zxC9X9@v#YEWMBYco&=lQJPZsV%sbP@9JKqNkAZCq+W=T(Nh?tNm!A=Q&^vyfk6be;Td)SwJ0m(v}sn* zY13j*S#EVnPhrRb)#6Zj@B!2kFnP$H>gkX@)sjg2pv4&&q_`PD(hLmJ_6P|E1{tVc zR*WhAU`?bi@1;iLI`whH3NepX!Etb5@M6Ka%U54leP-d zCT&%yM(8=%@U7gS@KB%bc#K(EKm*}9&<<|R$vj`B>a}FiPTAH5ow6;%&A^}oVt~%+ zV6>M6AD+$a2|kV+?i)QM^TZh#^!4Bh)g{{*p*zu`J~sdv2HJye2v@}l3ij#Q$C!ER zji4q$!^IfMP2f~ug3yHK22+r?J%vpqK|V6$W(*YvdDtA;00ssNB;zF*7%WX7yW*ii zWo0t`4>K#L1SGtz_0Y}>x0&qx?Ls}M5e8}tF)~Df>K<^Dhan0?f!ZI8;1!mjVvGUQ z76VO@u`xtVW{I8*DPurK?=Ubhd4B$2sNG<3jUC>$hj0{1bVF}O_5+g&9AZYC! zsB~rs5@%#!PzE!nAL(Nfob2=6!x*%TmxbXoW6*pMYdOS35CuA_03rcmfmZS|G6aFB zb<-8su!v5+^PQU?qy?lV7_52SD{H2UuAQ z+DOm9kXT%tT2!K!0Xg9lbOs><1M{27^ZzF@&X~%`*u(f`Y9C`${7vwVbY}3Lb72NX zW)|@Nb7oFa2G9xaNT;{&U_>0>4%x;ofTR_)f1VMvo1Ie>bgVn<$oE6j1sNHA7%zb+ zsp%DrjC}PU;JTQ>8|qm&g~40rr!s=J-?K0>f2!lu20I6|-JS)!Wu6gCGJ(uzW(4bk zY?g`*a?F32`~M$QOnu+cmWjGV&A4qeR1$jmhTehjG^DoX4CB@ znKY(fV`Hq2O06g{j4w~jPAx5n&&^LsjW2=h!1N3CjW;xe>>CDc8AjXC47ye%Ehn)! z1H6|tH$NplH4p4Qkc;9AK-}qT*%=e3%WyE-tAZQ=ad>%RHbXk-u!G#h;%tVL%=CD; z`1FMWj1tppI2cW)ALd{@YY*D*8SLX94!Lk3D8w0TesNA}D&+PPsG~t1V?g#rK~ZW! zVo~b!Q=E*RTqXIX$rMIh&j*N6JKxVm}zxw?QI2ilF4oR|aNG#cO% z?;j8X+JNcr<^~o49gqOtMhXfJh(D5H_XHq9qBy4jtUACY-o@Y7(bF#;9uU5+z6>c~ z@8=YNxAMkMzs$`jEC@0$EwQ*HH#HX;^iR1NRVOoQiL=BP<>yXU=3(@kF2u_yBwm~k zxuBsqH3t#RM&{F7co;RlV7t zbovoqMr9e0|C}9t;*E{G|&U{QHD`$@_AA!gyHK&{KF>1(ylOkxR zGx&%Fkmo@j2W6$Sg3{@^e2jV8=(}Gbn~Fh)ag=AKWkLdp0TP$f53FERoNmC+$U8lN zpHasHcG3bOe2k44VEHv3Y70Wr&;XQt;t>fI=8NfT`5BuuArZ`wTv`NnH8|CwX|V8h zF)}rqZY{v*##@x13n~^M4xHW~z^DX{+~S=4a*!Xv`D*e-7Lm!bS$L=46JS)HF3iO! zHoc#lkyR8F5TFDIQViO(`m$QY1=!NHZElapT# zIC15*PU!vRedfz*JGQiriYLpq>7 zDM;LyadKg*)OKHSMh-?@kV`=>1GRuai@rb#KrJUw_<+PgY?$~uh${`&Gm32AD8YCJ zawP;v6=<4UZ+e#$5l8qQLlWdcPv0 z;`BQjObXKz5|{)MHNaO3ft(83W5&qf&j1=M0`WmZ#7qpJF((iYf|(h#7@&Kh7(he3 zObnn^XAn6M$;_a`0Go>k4a+hy=uBr!WKz@z4ZwgDfZBpg44|Py5D$Wx8H^Y}kpbd? zTE~nGe$y8!G1^ZL*v%*~y#Pc^01+E@Gdl6tf>eQaRD#>NzS9$x8Re%>P-aw^Zm@?@ zVEP7SMhC%As2T{x%n&|ZP?b@Bx`QgC&~zysR=(*0dl)Z(uS=P3u#-_>`Wy`=f$4id zL876$s|w@+K>kl1!2(e4rpH+hz-IZK4?1=hz&}? zLJWEgpv`$8J_v*4xj=(%AP#i1E9eF&C>Ok=*90mL(yzpz$KV0wgVYExFeEX=p$ag7 zR&s$PK^SB~Bbq$uP-T!D2!rHTK;=P=aUljHhNDnEO#bp@>umXY&{8Xq2q>coF_ls!;6@W&`gcxiYKqt+C6u|hPL*_tyhz0fxpp%h7e9*w55Q8Iw5O_$10X%vq z#NfbpR?s&}tR9Fz8$!5C>Wrq?SPHCboijkgn zf*ZQ9jnQf91r~AeML5tz1lu7Ds#6$28G?ZUd;D2MJt1H~;P zXwVJjLg;ogP<_P+DvY4cVg!|b3=9m@&2$(g>cKX`d*uuaFj=r)KnwR^wgf`7gKdGT z2b&DtH3zDzVEzSFL$JlgpkQJIog2!)zyKPZ1fO@$z`y|V7$Ymg^xhn1E<=!I43Isf zkXnKPd@~6nv~&Zlu4N2^*bgEZ6{icBuqxYv#9;vlI;IpPhZImCE+cpj3*1p>V1$*- zU^QSPRB;&rayC5NrxzHq%E^I43aTFLb7U(WAjUxx0yr?BNRJVaW(ouT#1o-xP>6%-a*)NKX+n^v zKx|${2JkrmAofzw-bs*p4h9C$G%jdOBuE_O7$ulEXqp|AnLxw+&}<;01BoAg(Amr& z4k(B~OVdGYkPkp91H=aT4CD|H8{}%xk|h`$w7eX~25lyWu|fF;#s+087#oy%LEBkD z=>U|T!Q!CR;UEDp2YT88j14*<8O8?97=bi{E&&5=eS)z;Z9Nbh zJ!oMJXmJ$-18m1HX#D`l0+35VY}kfh&|YnjgFrPhXx9Kp4akuoHf+N$$Ppr-gaKN5 z0ZMfGkkA5|0}==2CJ+X(L7~L~ihpis0S(%+1Cjs*9f-{hiZE!)5hMRLz0ZfII+7cpx??qb0G~nx4qijZiPRuAH)tsq0|R)d9Ha*1b5Mm3 zVuO4Rs`5Z=kk7$IwIO5;JBZB`Vnv4+EqI6l$Pl(I7RT76gdR4T^LI28M1>lnF5~fI#U`0SV1+?NDp{9^DjOF@t0hQ0#%&Aj?3P zzk%2w2c?3122~GQ_zDsSg%CJYBp5(9DlmW+OoEPe0d?HL9*}^PhhR@iK=w3ffYY=D z;!p?vNcmc6tz6W^%q!(lnXwXFjR6Kwd8iS(A0ursD=->ujvI1*XNHKth7wW+y z5+YIz44~kV0%?$foY4MbFm2o51jNFoKXxf4K62i-CS(ku;RDcFhw92f!H8lf!N%j@*n0n zSxB=3u65N1@G{s$@qTI2%4AXP4`U{#?@;>y;Q7rZ7S<%skMsHjJQ*#K6D+T3{^< zWiJGo2W5lCn?UBRVPs$cVVGXf&4i4glmt474Wu5*-igEp6$p%=WC^N;K&g-sv>z3A z$u5))Dz0GSps-*BHItzYTi8)-pvDVK4X6}@u|dNRFgBF3;zL~r+O7&y z1WK$hHt4iU7#p-?AI1h<3=CsWKr$3`3nEM$lz3t6MM!Eui5Dtf&#(?j0<`H7D!~B0 zNf_!l&{kKN_%S5)XOP&SBh+AOZXk)@Lt;NcV!sBnLE#Tt1rA!*3AKy^iOq+^7C~Zz zulj(h2i;l^vlujh3uEgbsR!+;fr(oniQCm9aX_QHFh!t!vM_cMlA25;b^{U{G|~%G z--9GR35h)uiM;{J2K#>-lmn`D_8_qjBe8EGu^%9@pCPf|AhAJ*Zo(Y&14;Zp5}S*e zp`HPzNC~v|5E`W53y+{|JtT3^a5GFjcry%CjRTSzcO-Tk5<3NnodsvtGcXjuISdSC zNNn(8NT>x(Na7tx>^>wmXhRUpakG%bL907q;>(c4*MQjdPzyGJI8gQuB=%_}HfTvE z%%JN?;&+kQkCE6fk=XB%*k6&@^}mrg;Ccz_2+-YZFw6Ks^%YcH8Hufl#MVb*n<|bWoctK!p?c0N~L7SXl?Da_M_am{-BeCy; zdI2yE?~x?_BeD5GEBv9pmq%jjBeCs~*#1cDcqDc{61yJ82Kj#ii~~CJ3Wue*#B>!9FQW= zEs-!oSwLHNpc({_*r2`nFkgb^Q()@NL25t^O3=Bjpbb7ywi}YTKN35F162M)6=i`W zpq7C*CV_hP3=9ky+A4XQ>Mv`ih!23>8;2vuVO5{I&F zLF{@c#}CATY6t-vR2?QaGK2GAl>m?C|M1Sl;+P8$TxPJj*yMH2T%VuP+Jh3N&| zYX@UjBB|*Dv7w%s0%C*u(V%nnKpTOCp&ZZ#3`Qs$w9^sB-UreEnwer?U;v#w2wL|H za@_?a@#`Qq)Pjc~HmLi=z`*bnbW$Od{Q)EnRr3qP28Ad%|AF?qKqc5fY|uzI=(bYO zk%UmTC`cTtMjgb4iW?xYtw3z38t^HE&?E z&1}HN9jc%jKo0LhQUtnJ6Q*V+NE~XxY7iTw7}VECV(&#_p9Zm^7GDFgp<@%bKz2!i zW;Q^n6eIyv1lsWrE8D+<#Gx8kLHlx`YWP8H(9{}emIZWrAe1c!5{IhM0I{LI)CIAj z;^rVWXss9n1A`4OsQia&b_Gd5*+C#S)MtqxHdI3vhz%8Q1F@loP6V-`BO_Bm4uY~5 zfW)C{R)g432WZ)62t~8g4_-Y3l;EAHmC)6p_YM0Qyw9y ze+yzm&HM&pL)HI6QqKn3y;=`d#0TO)6-j{DP>Vq)E5gQe)IocgpyN44NNQ|BY^XU- zAU0HQAQC$k#0E{NGcYhDf!I(r^?4u;XnYbh7zAQNgLf*34OIj_z!A#ch$OxjiG31@ zeHDp)6N&v0iTxD92A6*fZy_8|PGtCq#QurI{)@zB0qyvQI*0>_Er7%Z%{ju_3NlFI z3P@}Xe$Ww&P=i1lsbCsRkQ7-UvF(xA&PZ%8B(@(CI~0i>iNsEXu|W&;Qehkh28LWD zb|DhG0*PIN#BN4nwJE%B#zz)j3iKGU!!y9G}cubmi zy2w*TWzd8sD7Aq${=gax;ITSrO9iwn111g{dxo(=Yeryf@Ypj{J$URH$_8x!W`x%H zp!Fj#b~tFj2`XM6jl==%zl9B47lXv1wIS%JbC@`I7!E4lfuyDfi4D3q2Bv;Gk~nDG z7$&|HA`Z!R;DKYPq2PgIC>uQV24(MqXaEHkcu^zFAkZmuFg9q%FpLd4IS0lD-Ch7= zgEkt&*x;kmVVoaG7O;Z`hoBa7Be8{$*kVX*@X#Any$X`JHWFJOiERmEgZys`*r5H$u&Nhy?+uKd1yTd8hCwIS!Nfr~55w4XNNT!}*nLc(ZZ}l(EF_6}NbFTe z>~%3}%DEpMik^JXQyl04*JbX@~$T0;f5KR3tWN zIVnsHc&HAlw+cy3I}*Dai47ixgSIc0fbUs`a#n*BLD}n(*q|NJuxXe>AaQ8*3?7Dq zvaceEKSg4Lhu)xSKpUoE=72}oWTDM2PS79|R1q%{8?=!cra=KoTpfw6jl>4+uZF1) zKoSS-pN6#^l0o9ownG*RgEs?AA`eNT0*PIN#BN4nwj()49VKC8n!;Fgr(q=0;)DdZ76o*t8z#5DHj10Gf~lwf#Y{4xa0Q zCNR*%K5PaKv{nQb|DbzWgr%k*2xC-Mg$5$%^exzA8E8j5%#WZG@r323m9vXaw=QSr znI5gn$ipZ*T_K!NnHO4dff{g(9FsTn$xXMr$Rs`@xGIIR!ATBUwS!Xu)R*8RouJh%csLR| z_A&!BiU_Se&w|*{Q3=plV~o&HsCNbp$U*Bk&^CWqD2ReakD&FM1&9sxekh0y^*(rL z3tCYB2Z=-d-2@s-fo5Xx7z;EX>VZZRpdMZfV#`5C3P8isup@x^SRlv#f@bVRplr~3 z6DcSg6sMs415ytf2~>lMg9iC@plncM#|X*>9iVFgWlskk#{y-8Rw8+TMv6fOfu_HM zp%S2Ft>I8M==6##5E~lQ1yDA~ab-|8C?rAo3UufxC@`9!;-Gm{(AiiZanNFnKBzco z3Dy)SI~!DFf=H`+g3B4Q)44`(-6Q~4eYWzEh4NXu?pc9!vCq#i3 zPC(h9^aUC}2OR?oN+P0AaZoyyhO$9D7ey!=G?JtaWrJpvb)jq_8|RRQiNN*`Pcb3uS{AlqN&jpu>~Xp={7WrGZT0%e1ihrNQbL5}+XWrHmE z24#afgWyB7`572Mj%EU#&dd)v?3M${23gDpW!Hlia0)>=pe3-NBM5~+Nt%IyK^r74 z2niKKC>!Jm(4kr&H6TZT57!oiEQRy~sezUyAy78R15r>mC>tk3*`TzN13KbRNC>hJ zt_UgtTBuh6WrO0o4$20_cMFsa>Zo)<*`Qiw0+bCZe5XO#pg5ibWrNmnE`zc`s}MIp z*(*Wi&n_qjbW7I(C>yk#;24w*DjPua93Y2+j^Y9zoGk>oGV(D<4Rmx7d_cAcB(%Om z#X+I<7s>{e2h5;@ltmyO<^-`bL>L%Ai+DlD$O(x+HZ_0`!Up9l&=@L6ktoDa&^(8b zC<6m1i5Nh|LH&AX5E~R13=9mOP&O#oL1&E#i7_yM(rLo<`glh1deBUUkT?T)8(S4f zsW@a!9q7bNkT@u(wn4=~&H|km2@(etu5&@+paKq5G(p)QYt}>Apy9o(P&UY~`=M;m zVnon{g%D_UB4~}*d8hDgsS#fY>01N`h8AgE*kIS4vPtpa9f?vO#5&8I%oLCT9a> zgVsocW;;N7LF@Sfq2i#va|DzPYS6?%*`S4nDNr`(<|NQ02uSY=P-z321p#r^GcYie zK^1LbU|^_%vO$~XdO>Vx1v(kZ2KitnlnqJ&^Py}|UAz>^25DIhWrOP3jZijdBxpP6 zfJPxH1_saqzP(Th(DJv#P&R0J_em%lR9~HkvO(+aK$j|k^nyYKbg2@E4T?(8rAi<+ zX!+bzsCv+PydNMowAKfm87U+UPQvvJESwAsAP%U2zueo(N@wP6wL~WrOxL%!aZ-Cr+&c zYX+5kps`($gdD`xyP#}PJRN|tL0RY+lnn}rQ&2W^g+BxAf=p1$1a?6tC}D$7ZGvt7 z0_A50h({UqK(#G&4J{+o6wrcn*yWg@MW&3P;UfmfdT~Zj#KZPkf$9v{{wh#50Zn3o z24tYio(>DaLh=XQEK_TJ-8chL3G$;y?*fB_K@Onk48ql%z zuz|S-BsJi1C1}GAydDwC238~U~CsqCmWQIL4)$(EG&g9_>mz}Vm(CDfoF z5DlQnWMBdHBB9~}NNgD-wgwU#bhI<%RM6eRWnB=#C4_6{WW5f~fPSh)b^Oiu`9(VwoJ$>;&=i-Vf3u)cT#sCx{pXL69( zpcX1j4X9NLV}n|vFgB?531hE7(hFWp12q%W;Do8E2emR`qZ{D9IJBw&9T^N0{{S)w zDh|4O1tt!{0W~HWLER1p1_n?A61F=R+@}Zi7Qhh;CMNfpDo)os&muBC zDT`5Lx?LfYphhHQ6+38y2x#v+XzL58SO#^xL443y5lFAk^z~Vc;+CLV8l(i&1ON$p zAZZ7+UqEso?ciY*=&E^;x`OHdvlzuEa~TR~B}77cSRflg1tm-i=)N0d8(SErH{>#k zS%KPGAT=;6=R`6vfGP-(es<{oTacBYb{Mk$1rYt(BL_uzP1(^#fJ3(?FXQ_b-Vx*9CVFcX~A`3bI1f&F} z{XrBWR0XF?|6`SAjF{e^!zgYES|X3EQYIR*wF6`ksBH|A16kCDW>L)a`#Fr_lAse5 zKuTa1X+%R4%yjnutny4LVCPJ?`_C%C>ky4_gZT9Ou`JSz71Qf;8O5zYi+qs{sfk9! z0jRVA$${Jeo=8CQ>=ef78?qS1ESZ=fdn#a#ID(`f)Ch&?HwRTGNcwkx{a^)J#tTvc z)6Nrv2m(+x1<8S|2i%#bJCdF^;2U#wH=9x1vY++#lpIi+x1cX5fL39k7 zfd=u2oT)e6yO2?u6?7u7-}LN4MrExP@sK@ZAnQPFRgftl>n5OB$H3sjIz6F;QOpuF zw*gWEb8bum!gNr393%(Q4_-}-6rK~N$44=X*MrXN2PuJRzmfoH@q(-eHQPaQAnl;L z0FaY1sE!03R|4`N2!qst=-X(XHA!S(&|qR<0GS7B6ob@(%zF;;jxhtsjUbJ0*cccb zK{kLm&|(7;bb}&BF{^KA7R4kZ(h;c30J8`@TY{v&hGTj|5u@02vtmX8 ztrN+Jj00beHbUkQf7+F6{ z3c}H#PAW(aq#rb>3-Uayw*11uzyLaX1sXQsV+cU(*(|8#SV0N{1L%r1P-ug8-@wcR z4el~BFmQwSWP&s<;hcV;m{H6M)VKpFf_W$;m4N}&%>Wqy+SLY<13Bmynuij&rVErX zidlU{b3jZQ!b6}=F-$+G3xn*TC0vlys{p$90or{8x$8t4BK3kg(lGr|pq3X>guIx( zzJyWSDilq-Lpmb!fYuAbw1cj=K(;=Cds-=@m=$Q?7Ni8``!DH;=mec`0+IvyeihVq z=&3mjQ@E!GlroA59bkoQE`$|}2e_wC$YB%{x(QW}B)*`OQLO$gR2<|}5PrbTzyR9Q z0%C(O$UYGL0?k`084L`dz5pmzKtoF)bs%^BM>7w!&S@s7vIiLg>f1u;Ul8-^;bmGz z4gMLN$RXOIZenc`#of87POQ?z#d4!%UDNAWcZ>Bth5Hz@wL+ zfx)JMfdSMw1^Fa&di8%sX{G|z=?3MDV)dFRY8e<5+8G!?y-AQ#&^QXnc#x-^(Cn5_ zV_*P{#6qnG9a|4(+M=0vrvq|HJIFlH;33SsP>6Yu{tZay2{i_W^PrX-h=b&r05k*l zbTKf1mbHQm1kE483`~R=2tS5vx&Z@25n8N(5+k^GzyL{c;B3t40J^eFs1$U-I@E3u z<>COozN{T;EJz51YaAvAtQE^`LUYxTDGUstp#zYsK!YqWSAiGjgY-c$k0S$v3#h#d z<%3)VV)mn%H)kqD9mu?->G7?s(rf`93=DJGCdn%Ce(+;p0CjjkhjTbg)|ZuL4G3jm zcre|%l2HwIFWK~fN+$8`^_7e*lF`pqd^i{wK$yE*1++H}gt@+|fUZ3PVXoV%plKiw z=1OB!72#xH0Aa2sMitQA7$D4bUL}HufdPd17ODJXV_*Pbu0z}7CNqkvFc}$5@88ZS z!DMU*r7a+|0aV<;62dn$-Tr+$V-q`*q3LwRrHsPU`}Q*`G8tP;-?*RA7Nk3{fl+(< zg8hvAOa_)96(Z9e4lpW$%wMR;Bs|@wfl&l1Z8Uvt1Eb>hJqH-CIzl~dJXv9#`1bWo zOd>2iIUwJ#9ARN#U@hK$o{h=K6-AM}50jQIOk{gNCDYAPIM3ic6C*EU&UT|eOg$=0 z#)jJuC@?Q(1-Z^gm|1drof>no6-+Vc`nTL4zxyP&TN!91UfI7T|$e zRUo~fWZyHn_ z)O(!+WrM~i7eU#enhG@315zK$z`(E$Dh@i&VhiY!B#;DXjBgiI0<@;>0F({7KlK=t z4Vrj817)veU|_feWrNNk0u3C2%mLkOcMmEK8t((Ogh1k;rE8!;BoG^PYZRz~17be| z<=|i2%jYn&Gcxu}ub<28&$wjz`MJ!;8GlTlK9AX-(P#SedCcXE3De`}Gy5|>nZABL zb2($jboB+y{){`OmxHJ;(~mD;)@J-a{qq85Wk!|h;tQG888=P0U&yS^G*bdp>`bp) z$SlBkWqLnIhG+VA5Vc|YeGnxxoqZ9rI^&7y`iq#=*%nALFhnp;l2u~-F})rn{$l#_ zMa)`AsZMPByG6{b0&)$Y%O<%&mkY5qf|v{pJfMYv%%GkjTibTQ&CIv?c`n*HGBGfK zFx!RgKMpbT8%dZOW4Qy-*vM?V{8#2Cc1E-5i~cZcGnpH2KmUjMUj~xJ;@e-Rvb3;> zL$cgVW(EfKTyT>eG=t7wyuB@pB}RnNbo=8vmTN4GrrUQlvxv)~=zqVECCD5qVhYMq ztR`m0kQ^lJ0GdKVx=}HQA#?iNn=Fw!Jq=&%mo$8_UubnBU;*fcM9?Vj0Y--Z|Nr-c z%J&HkU+gEaf`-}|8m51{$>IUJ*9&w7BPip5F=(%T&g6$e!iLD^fXoG%@&Et-dayE3 zatCc!U|?VXE%^YsXT{`3Q}gNTZn0Rffw*g!CO4Y;ZMVA3@|v-JA_K!l2GHGxn=&O2 zC@>t-1l>Q_um*JZ;i60-9!{la!u~K$#1wy07-Nq0|Ugy zm7E6@7*I6uaDWY!{V+Z6E{nqSNB3A#w)fp-31QsscAw=7%XGh|EQR%spi^NWwsmr$ z+rI;B|7?&CW`Ybu;X{n)lKlX>DhRYJ;sOH$187$_Xh;Qg5g(}Oz{3bRoC~x|+klaQ z0kruVw9y*0sT#C_S`oBc8niJQvBpb2@CsgL zh2Ia!!{R2yz%c#s6Bc(aZx^El;_i!Iu4S4WZ!WFK_W!?GBZJJDjSLKH86o#YHYtfb ztKbyqSYW}y#>g=J)>9S($qJ6O%n(_)p+-s~X~LD$m7lSw@r$=7bHgRrn5IWQV=)&8 zZ3l*i*8>jdt&(C=4BMAHW4Xk{*f2f*C5!v?v<4=L>DOMe7%;kkuU(V`B_tM5tBD(JpLMm9+>#c_-s ze9t1dIR*+eW=T-d%W`G<+gB`d_5Pq6@L1S2*g>};GO@6Ow&O7|a)8$8u(2!xou>oZ z%+CV4eVIiEbRHiIXwNl^F6bZ=7SI|7mX)AYFdQtPe9oE#nhN3M1-YFQ+~EaPK@3cs zpc~LwIM=a)t`c0x4!Y^E9dw@+=Sw#h1_lRCQ2aG;fkx^X7`Z?<|1mIeg@a~BKo{46 z4Q>bo-NL90>Hu(prui8;kAv^6vj$(<*S`J2YnBv7#;May-?F$0c(XGwaENaLhm9}; zpZoN#w=A)Ipsko3a@HWX@i1~s|N54tRiF-}QU|P(nU8^Q<@Bz1EV2;&`e0E;P6odJ z)3<{}KZ0Cu1QumtX5f1>{mDBPU&a^Hjo!2PG3HEfe9xl8cwqXv_bhW6cTe~Ez@h^& zCmyVW5$ukR4=l$8KvxTLR6|5%82GkLkN?OL4H0cc5l^$UwKZ$C(;7^J<2CwIE( z7Zzp4`stBhSmGHYrtkd1;?DSWI^$OsW!qh#YX;YV)IH#-0C|2bi2a181;kzlV!z-y z1Y)lTvET4q0kJoL*dKTvOi%pE;^NK8!N9;N0lKY0yb;ucwPSSRW?*0j5fa4(42*V+ zAmt29j7;Us3=ER_prm>OB*dJ;&A=d)nZm$y6O>vRq@|~S_{yTdxM;iJHx?5{#+>PH z-&tJhRU$z>Fi=^+zyMlG!Z=6O1k_9iogK))0Gjw?oHL!5fkCYxnSs$6Y#Hd(KXs7Z z5H4e|0%*Xom79SfnwNn=kueH#e+`2IXiRz!Hv>aHM3||Ffk6Q@hY3;&+VrBx7&ZO- zcNV#N(Af_R44{)!8Rt~-F)(NdgI3e|F@i?SKnu?`GZ`2Iz;=VmE=`bAAY9Oba7~a? zAly@+3!gwuB+yvBDIWuaW&ubt46OAtBLjoBDmUZ=Cs3n}F`Q9_kAXqQ47A-0B+H-# zTIm2R6F#cw{d5j&`X3Ywc` z07V?*9MIwyV~~*`pMhox8Ech5Oj|Lio9aPx=nM=dVxWiv^>V=L9T?|S^D{7*o&&{i zD(JXe#voIE&?smsNSrZP0n`-*`OS?VY7VFlXHWpmF@l7nAi|(K*c3p)1rh^o+TzM+3hs!33}c*QJ{jaD$Qi_-LYZ;Sc>x9n3vm2q zf#a7k$TA$XjxvW4B*Pe_S;4@V%Lwv0=m-kUN*E7xriA4?(1?5<<5d9$2Ih$k^$MUx zTOOdBK1BtlNB?Azs|PLokpsE*4i5u^0%&3!W+pR1lOw200veEG zToWP4z@QJ~f|KJKaB|d2hn`L8AjH66Jpq)iH-Vh7pNWA%0aQ(aT;44R4NeJ=9tBX# z4kWxtkf9!u{Y}8)pmj_j@trW`4q)L~3=9k);R`U~0I)D#e>AoLc~~^K_{;;C_IFQz!RA88YWO4l6%g;zz`_Lz@P+*?#a;X2U_!e$%yANdrHuQ?DdQm|Wyn@AFg^ms;w4x@0C@(S5Z)FFGcf4e zfmTR?_~4WP+AP7qAO~uAfCB_n=IBuW3UCE1+tY<3e-(!U|;}^k1@{qEW*H` zmY2`KxRucu6vUwY9_ooHMIZsNiNO}2C9Ys;1_s6u4e+)okYWY~koQ1^(ROfQ1nOMd zrGN^vU0^<_zsz6*TF}M_n#yB<-j1ju%D|uwvhWgE6=RS+SkF}u50p_J)TA=r^(g2@s^NgW=2985q+*5m5 zB{*FyK#Qw67#OxLWi4mQ<3_p6Ob_XjEpE^jXMNaJXa*(>hQg4`z984Fakn!{DsVF} z7{TxH;#SAFBFtEp!4Q1GSOhnyMl}Ild}d+_y}Ao}SC<*+b}sN`WUT6l3&t22%wgB9 zfsCDgj+s@=6m*vu^s+BLD{gBj*9vrBm=(7*)I4h>t~djO&GduEm?ar)r^g;+mX^1J zN`kbCGcdsJcVqPw23?QlFkP^ZNyf$z$JfQ}aP=P+NkLAs9q~s&|+ahz(i75DXfd1r=e848aVb z$zG6Apz#7wqGDtKEfNHYFo0GC-q>Et&YH`}xM%un4pwi*hUxm8tm4!CI9VkGLG1&O zI!I~E!0=^yIwxyBVI{`wq2Nos3_;_6*WlxSlN0`VZC}sB>dxe`1b!zJGbcCr`Y8y> z1!jY;=wjpq-Mq!jDFzmS$O@BE>=#q z>52lZV$;_Muu3p;O+PBY+Q`ZS(m7pGkX3BDsvxTnh!Eyyh8hUEM~sn^bNW<4)^5hN z(-nnSWf-?kw-aKmW4ttduMn#egjhuxd$xZQVl7}52Hg)(keHX591pr73Vf~0 z^!|P}mF=AptWTJP(53SWrsqhrezgR3AwjVPN){j*)U*fDppiWg4N6HM8r1$prURyT z$*`7B*WAm>GhJpKBhPeRSyrCu;EP>2C7C6_H@-~%CC#(lQ8$dsbEex$GxJP8vW`(=x~BrG4JRlef%LdQ)Gd@}l?VjQ`+~$^G^o`M z${nCe5M(B(VFy}i17d@+2gu1FH6S*q>H&#^auUe9Aodc7*_>jGJiH)tL25yA@zedJ zn8g`|rhmv_7mo$im>|{5pr?C+*r4_csG$vFgBmR`HmIQjV_yTE+XlVm0F=2v=74Mg zWin882GaXxyOttrD3f$fW=U#MVvZhqL?srLOs`dDb(nrnnbltkm#X}N>FbnP4W=ox zvTnCmVU1**-k{9NB2kiBQG(UP!d!Og=^Ip8)uuD5u|{A^9p_b9&9_IYu`XboY^NbN z{S4@)lnaWC3iWE>6LdiV3tE-M!~j}$4dOvCGlK@WjtB8TohfYh$bh^Jk_Q!WOrV2a zK^!Os-6I2C0t?K=tbuqCJYBAcUC7yt0d&A4 zNCecAW&#(-ARYuWGgvTyS|K1FsPoIj04hd7JP2lHuws}oeYYm7JU=K&fdoMf2S$dF z=^vFC4X4}vWES8B9ViWw0hOan)9sZRmH9#A^B|!Gptd1H&~(NY*ptg6sgF1r4egpd2tC+y{jV zFf*hxfTjsx0-&*Z{`VHlQ>Ln!x zI|fNm$bj}gGcYg+F*q>jK=~kLAOm45JwQ!sAqF=F2Q+!mG#*GTs8K4!;K2Yo@)X1e zl?Fl#UJRgR#2`MXU8yR>;KMK>18DRVqyW^a6JiKpI5S;am$l9mOFm^N zC@pc#D=DgENXd6fOwKMTN=!~=$Vkj7@h{0pEppB;n!ZPuRf#1vCAE0^25UC4>AZTZ zmXhcuaRX2BriwD!>SxqyiQ4jG%ylStU08gFdS`qwlmf7V*i^T0D}V z{V&i$5O$3T*d3yi1GK~^cNg$XzF#20=r{eq1t#(7)`uB+B%xM9Tmn)HNf(Tw(-&-H z5{F5HwtX>zdhM_U{=(BQcrc4kuQy2zo(-*vC6rVnu zk%h+=G+MyGzyRI_3-t;}9n6cMx(v2d6f<WNWmx`7eve$Nn)bf z@-Z}kKxr8oC@AibnjT}!>dqK4eTgxvyDGBbP)otS18s`}*$6UF6BHMoP-DSXKw}MT z1t=MV4y6XEgf{8G(GC>{jRA{*YFDTl5tHc!CalVgrqidGu)0fv>RQl|I-pA|K=mvG zR3J9UkM&_7$6GKkfYLT--wH?qUfll=XSq2J25F2C}Xa*R>23ZDH53PhiyW&6xbA!}_(xHeI zLp=jX1E|dnk^pG{6=ondD2hOl0b+w(3Yt9zu|W<6Wn~Z>6a zMhsNCGBALBYz@hxAT~ENJAtZtkb00qL2PbNQ-%SuEfXXTax`d*CRjbF7zf9VHKfD> zv0)lO=81qZFz9?MP&7#}Fo0?uP{Ia@gB+>`61Rb@Ujo$=po8~8X#fD$qTc*tAC z0b(lHI}Q-%fl>oV927YqZ-dw%d9bq`AZCJ0U<6kiusQ&w8dfrbRAVa*ahJ-V)Cz4T zFp5qOc)=*f#3(wwVJ5rS^mP}Rc&D$P#V!FWSV7GiM$zd4pfd}g`anCaVU~l2=wWPd zV1Wu31_lODFo-xpybDgFju7vH_L+$&LUJFdNeNN|@(ie%31Wjh1HKYU5pv@aXt)(5 z4oZggpkZJT2NY(Y5oC}-AR3&d9U&PA#D?7;11@76A=}_UY;I6Hg@FNbRe~dAzW^u- zxk0N-V0URKGBAL8J)qKlc2C^Td2$bVMOQ>LqKpWga zia`A~(B@~58c?DGvAID(#lQe=VS~g$6)~u_4ZG$CG%^no2W^`JvAIFP#K6EX8r3t1Tjb)lvF{%1!98=Pf+Fru|aVR8Z-v6L2(Qk zDF(4Y@d_Fw0kJ`D1$hj_1{E2gEgm2?C|iJzoT>+LKpA!x$aTsL44@9dToBs{vYQ#S zAsD0v6djX?D-0yzxSj1qCGhum!k;=mMvi*_dl22gN<*f4QWt_5iZ`79S|0jP2W zv0-Y!SxXr-U&FuvIxqp`I8ZhOv0-XJQ4TT(JdFY7I59AQ3 zAA$l3WDuxu00k@T79h}s1;{ecd1UXPnn4>9Kx}SMr3N}c10)VAAYk{aI74y}sBjTc zVPG(Yr5k5RDGB0>I78|i(4|Zuwg4#qgMuE!0c9JIk3eitwgFd!&X5ui#D*nCP__f9 z0VP-v8|E8OsRyzclt4j43?Mb2oCRXT)PQSvXGqQhvAGjL4H8&Nc7|M70#3-m~;`PpuQVTTZ01JLlh=_pnKx=xK13(Qk5j9913#!&Z zYCw%D5F2(66}VCZHEN(u4-s_+2GCMau$k(R{YqeS)EU5IDd5e7AVr|K1t|ovK@}&6 z4`PG5BH&t39pX)}K^l;_2D3ruFEB7LfJ;|5NIC(9oQNAFZGc)SAT}sEL1l@ECgeIC zP*YRHjUgC(LoSE|yYmYauOJPeGy`J8uC)SnvOt%9}7YC=bHepehf>25;;JMF;}}1E^GjiGvy!Fg9q~ z3C0Emfv^rF9zZo0h%Lgvzz*&)G3tPC@6mx|22gHd)R|tei%FkX2U0VDQXQkt^aUvp zAy63%!i+l8IY3wL=rAyV`~<>`I@1q;uJ6%-)Yf1p>p-sW(P3Z!jckE1qYmWy9vub- z(9T2I@33}vg+6CFff3MB@l*fq6ZBk!8Rs?#(`jmbo~T% zRYB1Y@-OIm8IYGj%c4LtUm%Zx`r{xrw3-90uoH%|1wrbeY|wovpdbR>15^(pU>1Yc zbTNXebp{3o&{7*=C>wMjBa97Nst3|+!pOh?!Z5v{gNk6ATtQ3ughA;WRCj_bhO$A+ z`#^d@_W*$~qYik%F#`i=rz319ENK0oFm%2Kbm9?=4O$Zj(hRx?2!t7Rrc1c9f@2YK z#}5Moqt5gYs1W>$AD!tF+#$gXI(!j?VJ-&mrUx~A85qE$V!}{1_~src8???4Wa$w` z1_ls@=>>1N2lWsc7#Kizq6kCT7eT&-vO!Z-AiZ}$x4wV~m}c;pNNn(JHc&O- zqcfpw@X?u2HfZ@O%uLV?HuW&hd?bUwM`S`ZfN!dSvO&u=VCo+tssDh)2H!#hRnG@n zI0j{dHkHEk>LA4H8DbF}hD;=ODH6L8iQS9D2CYYj8M+ind?ONjFA^KHc>t#VAy^y~ z{tOHZpj`qmiT_{;P|?f406GW{CN2wF4hQuOXs0Vo9DEN8RNMb-;{eh<#BXJB{*=P)pQLt-<5 z=FXv-`HEsakQfqM35l(T#I{0WyCJcIkl1k$ zHYERLK{((%SBAuHLSpwJv1cK%mm#q?A+f=iOF$ic3Q7DL68jOC4mhFbC3{J z=@&42dO`r$kQNZ7KYc|2t3IRg^cx_a@$^3sN+FO{8J2Q5K!@N%2h(^!hu}lm!XR;| z7okl?P*CTd33QG<)F5sU z8)_Lp=yZSRO}X+Qai|(q5F4t-42kUyVnaRV3t~gnq$9CQ_(12|LlsqnB%r=&1hJv* z?^ck-Q1%og@flEYP#1GClK65Y@eLqxs6)4d*ids0g4iItKsg6|H2{diz`$@GBmr&5 zUj`WjWj{g^e+Cr?g%_B3l2eF~Sdl!lQ2*ie}{{&(~&EXPYV1UiVih02S0E5@28uhO&Qy#Gz_91R+Hx*#DwX z4#@w?NNimY8ydW3AU4z>D?x~%ps7?>Bymq9@gR^mRBt4R4b>Y9RRbD-N&_wJhNaR1 zkRqstQV<)ep$)`_`mzVahKkPxv7zFNL2Rh_77!aMz6->Lik}9tq2d=oY_NDe1H&T_ z2P*Lb#0E<+F#H6uq2m8RY^b<^5Ca2jC_@ayhKj3$*iiMlAU0Io3dDwrJA&9y@dywb zy2*ke8N`7~}@eYa2FAPa6p!6XMVuJ>~7#J8Ng&7!xp==e9I5cq?BC*{-Y-qIlgV<2@!4SRm z450apI3$TAhy++X8zc_ZTm)i6HCH3Cdq8Zc2PT2oP&KoW*lR#+sG3b6HdM`FVWjf^ zB$C7>B=&72_8SlzYS1ST8*0#RBsPx-B7J}kqJ>>0EDaKes@DOrLFRz+pAm=ym2d{J zp~2_{VnatZ{6rWSU?U!BNaFcO>;@1Us<#`&hK_9XgY-h#OF-h#5Zx|u22~gm8$8$n6$fpqgQ+h-QUlr~3=;n?Z6RoZ#6fJ3|3T-g z!6eLJ5)2Fspj~V*aZe<1&>kq5cnFd>XzLauw4hH1i9^}o@g`^zFGdnC2VcnoRRq4b z18lZx)!JAN^dcmi-LD`^fVlXw}tCykTpbcVB@p=aEAQn^t zJctD?Gr@aRpzOOKM?l%&!7V8J6_PmkY8R+DXjc-ffMx^@89~KCTY6wux{H9s)j{D8 znnVI~!0C(uw6z@*~H)^vYI zMseE)Bq8v1FVMmtbR-(gEmM)yfCu29YF12N@5m^w3OfD_rgS@!QqTq^nE0vb_Z=C< z>%n)tKy}|iQVKp94Jr=WaRj?N>@!FWw0!-A#QulG2JJ|KsRthp3so--8c>6>D?EZxTn|6Wapi}Jc(7J9-3Q0GexlZ8PLo;?BrC?EHG^D z1$^o+pxy-q4n~6`Fw7f!NR@`yz-9O(>v~#9)D=3>qkv2Te*aFfasxIM7t^ z8N`MbV4pyPqtL=89W-7E4WSkg8yYIipwT;MNPx#Ep&{V|Iwc3{`yePAGzt+0WrOCW zGhoN_fQqU-kOcJnpAsk=q#txI6zC`&(7GZ}p#frprs~_EYCyBIu(N|e0WcRN4h`PL zP&UZol~6Xw9MBa}LYxc?+@Jz;D^vnx(0(Wz6k;c#Y|wQ66(}3zQP3%gAkCne^!re8 z(BA$}AT~5Ae?ZwFi$P_E5I1CT91G~K6>bLb<}ohtg)H2VNo3IQKS&X1WrZS05p<1% zDwGW}2z0u%5HwBLfyDVC=gEUkmjj7|q(IXGAU0^J2k5{<5E~RDVNms;Rj;4}s6pbs zph5X0s03(M4RjhcNCLDJ4|Jy#h+PZ1z8R_pwEU+E$_6d@se`gXIbb4)4Nauep=^+& z=R(;a$1R4kK}ij?&p_EALoY$upmcBp z$_C9i-h;A1=@)#(jWA@{>MN)?XpzMSC>vCSd;?922njPVfO`6%V-i7Z(0&wN&;={d zrll~H4YF7g$_5qXpnK#&7jA%74TFwI1hGNOH?*N@Kp6*gzdT4Bls=q5;-C}?I%OZq z2Hj!C;0NV^$_LP_3+QGGP+|m~n+RfqvT_1c4JcuzLD`@(F9*s71!*~y4eG7dLD`_i zY@jnYK<0o7+%Bj%Xr0*vR)%^8kOXK~ykidl8fkTA;WL$_ACDdq8ZE z%NQ6KjzZa>5IPBEgL2><5F6xT1_p*lP&P;n=!iri8PIVQ^$ZN4X&?{>luAEA6@gYB zu!1g90eKO$k{-$iX%>XCLDSIUP&TMA0ZkPN$w9K29!MNo^n=dy5R!-F6f3AWDBU=K z*!A*|_0Db}jywYcsEgzUWrMOxEQk#XTLuOO@Le{F5Q9MTPeO_e44?#`4^;!oa-ie? zK;ocm;P@&lfWrO;GptAr$YCy|7>wBRRpk-p910z5ZpcS$+q2i!P@WoIzsGa~Mv0IeMbopT5h2Q>@4pyHsWKme2tN~B>>HYgi|P8$NL z2dytnhl+zjB@fC5tu?KLvg<+RKlnBrWd;V&!c*{VILZtRpv8?nP(`4U4s`b!$WYLN z)EQ85&|=5MP&Q~0BWNlSqz1Gebt_aHv~F<^lnq*&dK}6IEh{+34!V#_nSlYcQ1uE_ z0gM1IkMb3=HN_Hput3P&OzjxIo#U zs02+53u!VifJT%8pyHsljUk+%@?R6Oni13lgWZS%Y9cX$A|AT>5q8%LsPcl{^#Te? z*o`P4x5I8k0WAZC-G~Cp*038IXjk{QraM+V42 z*5K30V3*8*8U(N#8A0I;N*^GDKt(6)ju}v@1YJ4;5(jw^be1HD4XXG-J_NBr%POH8 ze;7HSzLc2WU&b!33U)lm)v)_zpj)0mQ3>-@$aMKTOyc#RI*<|U2S^fzc>z?oGD5uo z?n!_=&cMI`?lC~U0PZ+Jy#VSUF+#lnzD)+|1<*}&A zF|tk%&}CPa1T`E$D|A6aI8ZkD4jK081u2ZPr=Kol<(Y1*$1X8FcnQ18^yd9+5|W^b z3$!5+G~@tnU`2r0)3@wrQ=Xn)#A=`lif#r5h8-YrDEkN!`vRCfeNPdqaw1e3bfX@u z8wb8@7Ah_Q>heI@;4uPFX#+Z45hM;}gN|;8b@ewNyD6D4(IyMx>1|1a&V}njGflaAx0T~TSybKHspu<>TLr-xC96gHE4=X#fueK*hoL#6a2Lg*>3z5EN6OUL2GSYP~~;j~GBLb{HGf zN{6vQ4Rc0i22k0`zyQ7{2C5l+PYjd|z9$CC2Co8wvX>xPwgHI^z9&X``ic@(eMXh( zH%eIDVZCASmw zAh8V~Y*34jfx!mC0T&k@AU3q94MAdq&P|5(^T9_!YfWx6)th{7rO0%>GFBhXf=I~H z?yTv}WvuR;HPD+;vZh}Kai>6UEyk&>K`hc7h5in0C+(c4X}WjMEdc7{#o>2Rb6@--6_3 z(4a3&e>$3*H6Z$hz?ZTk`Ne^8`iE>rvFUCR%mTcBq8Pw?@j;G}m_GX%lQb*n2+^MD zyPq*BYrTnPU;y2#1(F37XfUh5D}0fRlwkrJX|*5Cs}o`orh^JTn10X#USzN4Fin4u z!zgA28qx=;fz~bz4RMf;49I>^$q14IB^uC~9mx7in848^qz5Xzk=#|m1i4^G6YYMI z8F7&9M<8=S1sTj-e>DA5m?j%&hzW&4g+a{`P-27%M>9coF`x;fU$HWUX?g=An^=7U znj_xCL3Ztd904kRV2-GT+6GJdpaZ}_fe*47ghA>+bOoAu0`ZW8+d<}mN&}EOP+)=Y zCj&K#VFrS#I8c`jWC#d@6oTk}Gy@&tA?+2AfuLa_kUEfotI-??svn{CILH|IRS?Ti z%+q0DSP&21CksAF2-Jjw8MqhCKo4f{-4@f2TZHv1I_Uu_7@ZfF)&mlAVLh(4u+X04603$%mYzYyjP7v#uJ zkQ(qF43I()2h^+pv0)awBqA&Z^}s=LAd5j~nu836MZF65^bMd(G6K-9DtV9yxnu+6 za8OGTrXPGU9a2cl;RcsU^`LXmL26+3zeqx4RL}-_kQ~VVRd}qyY;u0MrbJ82}mz zMGg=i9&osV+yKTPbsz@lSalE^=AZ+~h>8Lv29g6g=q|*A^$ei%eLxxmco-N!Llhu3 z2!j-YXi)15#0F^w@i|f$7(iDXf*c5HG=twDT;^d z85n9(85ls*qaXu8t!ly26FI2jt>MG0>U75AUYY%z=|A1c?X)h0jUF-2cD@w zGB1T6Ts+l-&hG`OfqC#o4x(M)2aPI_e$XB0$Z4*EpMe2%gaF75APh1CL@z{h&yySm z22f`U5~L1f-bqM+al_Nx3I6FDN}0s0KsP#o6u}%+l8Z|p>kUO^h5 zxIl=3Ap_gA3vw(AX+S4&=WisCl5# z0FcJ#)(i|+IKU?hgSZS}13{k5MN_!j1#}sMP#G&|qaZ{ni2UXPx&x*j+#3S%p;*tA zfdMqi3gv=L1+kmag6+v1$h}Y?Z-b7Pf;n?4)OL^_5I*M0zyP|a62t~!kPAUH=$KCy zP(cCn_lda>g&+gdA-BTV`7kidV+Gv`b0?62VFN1z185G&8+3IFh2tW z2n)HZ`0+6?fUr=wN*pf(0|*O6O>daYsIYz3eAZK}?0Z0G$}{YnE;y61YV!X-&C@4D zvcH}lFpJT4`-J7J4UF3*SF$=v>6@FIV!3C++{6%@sImFQKVe{CFavcmp&9=gXc7@>7iiIf5a{3<&|u&rs02v=3n&{j`|u9R z26gG#>$F zgKjR1gR(*QVWvRYplzn0tJgs0h}JVQFcd%~Ks(_;V<8|3(3aD7kT^6tdZBDkhhs97 z4Uz)ga|N2a1@#iG+YKMWQF*l^R+Qh3DA5ksI&xW1~rB=pyD9k=Rw(^J^m$7Ht2LF&}{%9^`PY$ zpsU?L^S+>Bsvo3A5Hj)&8Xy8q#e&2)gTz58oq>U2XFU>UKa>q}HFyS61Txie8Y&J7 zUeNLf(E3);*yDAmI4JJ#LfN3+D)ia~mj;K@ia28JR~5}Xg!P{qK&uoTJ$HRD%9*`S%mjZk(M0|Uc$ zD0@C=^~(0<@2t@*j1trD|7Hc-|AFQF|FiltN=%;*qGG1M2T>_g?b*s13#M*o^Jn}rot=@*pD|>6 zI3t@qBO}Z7=}c_?j5^bwGqII3>P(MkX7gvvnZ6!G1x)|X%%;tFV7fL7n=+%ubbl5$ zbw;-7=cr-P`h>HQ!o zVfuCuRWSWND;w-)CDZ8wY-|#YmeUh&vS>2i*dENrwuX_%#Kc%P-8eZh#lRqKJ2wZL zF$)*yo^2k`rD*)q*q9{iLHlEwnb-xH85o!u*+8pUS-?FEAyBKEnUNz3v|xsbbrz_} z09p{kA_*!ySmHq4cPVh$!NCgJBG1gh4w|B5W&w{`F|)A02ARmhevb)cFh>j<=mr#W4&V`#|*`2WU4Y6UT9odpN8> zqhcJOB_pg1ENP&&w;E`XFEGFcJC<`LKkx@txV#1;?$ zWj{`35L-l`8YHd)VoL~srq?)CL2Ma;57QU$v5C}!J*EW`V&M~F;1LD+Qya`>6lCB5 zO%ZVFfVs?k3_L49_US^n+)!`pfw_!aP;cu)xSR|;dqGASfVoWU3_LqPTtf(#m4Rn7 zh-p6eG4LpHO!pOJixOxA zC75ckFry3ukNNcNf^5+c(N-i;B_Wt-KayxKTy!Rq=no+_13}Of7v~nRs0<4O4=d|* zOJO#BM*ZoT!ff{SpoOuV>Y%N(3<97reNJ;VW(Ecifs>#kgX};{WqkzRg5t#q}5PO0^1}JNlg4k08R6$Kh z&icu$3=A_so0J$hJO8mVFw7AEtrz5+3|d#SK;S3Hg1Ml*+)D&N+sZlTfi$lW0A0?> zIUmGcBk&ZYW&w!3LEsR`#|uI1Edrp0Eu4!$>>UCZK#pDvV($@P2HhsKWH)FY;(!2X zH3a8Uki-!IZI07pnC~9SA)dv2!O7-;#>n_KM?Z=C75tp*K%mcAEfY=`dKwU7-jUe_HfeF)(in3|cCxMJOa1?YQW)3?81Ei?ra{J23 zz`y}ovc|vxJ_&#Wbp8Vq$9GVf%mG>e%EBND>Z399F*5UWF))aM8UxIHjG&7O8N_EX zGcYjS0NKN=#l^rN0lx1DRQfYWf)AIRr@n!jfuKT@agJX1^p8?( z>h++7K%576aWXI%1c4&?5Qu3AYT1D>cbefDCI$u&=I}8DZKD8Tjs!zc+XaMq+>Jn| zr+}~_Xtfjw^NJZ-vN14#Fkhr0sM-Nx{&>Taj0_AQEKp|%TJjCTW?a7w*Rn7$fG}UY zVJ;&B0|*O#GOl80U;tsE9u{NJRtpdoWMni1tvdX${j4-wC>uNIE?Opr{OOKdtgk>< zb^1+C2%I-L;a}MF2W@ON&}%(~r!Q7vo5;wq-BgwBG4tf21>)1qG}$}^gF>9+odZJS z-GW>L;|lHjf=iO8eia-rf1_lPu3J#Ds$ZN0*UO_!D&}t5lIB4B1Xd(i{26eMQD?31J z&{8PSb`TI7G%*KSWrMnCnou^#5&BTJDQI566v_cD69S#} zBE$h1Y;c5%gVuj|L)oAKRPds14#)r|s6h%+4>}PEG+Ym2gLZ(VL)C-2Yv8rp(CBLc ziE~0au6?kP4bWiI6sQEK(?1W&230F7plncYbsdxq8d2N=WrNl#?SisF%iRt@*&v64 z*Ku<~&V&T7E>c!sK3a-zyMl|15$K@fq`KYR5NI`DQH~|Nc=qm z0|Thn24a6@U|;~P(E+i)GcYimf~p4{5eHhY0}_{GWMBXfyKpfus4+4yfQMbUAg8>6 zhh0Fkwu}r6FTpF(xfmF185tPfLJb1n!w4EY0EI26AcC?%*-0G4h88liP&P`(~gJe1D>Gq+_^3$V|*fbbz zrZ*?C`7^dmznsM8&m>|oT_u^#k8#HI;$$|^ZO(^5)Q0K8DQy0Xd$uR1fLb&srdOx3 z`7_o`Kb^|v&!l2CT_%mqkFjBTb{cr(VK<0sna-Wg=Fd21dNhbyF?}_N+A{rjI-5U} zgu`^747M`HnCXWz*!&sSOc%~%^JiQ!Jvoz2n=xd1eGuhNxU6dFY!l&QQ zWK(9Etp%EYm@bvYCctz}3p8jUv>VjO1C^#w%%?p)U_Oi3^sFp40mcc_tFzeD8U3a& z22mfTpUz@aXEW1dV7SOMNmhx8!*IGxHk%r&gee2V&FSvhY_JIcv*`x!nZ%il&8B}` z#H`6!uzh%wu3+0PkO7gWNWK9;#t60|UcNC>yk8?=h4OiZ0mf0chnZ=t?<|q30MF z7=A+4fC>okECDn`g+S#jIPWkpNI==(4OMbb4rpjn16zO4EPwp2R(vk4EPwpCozC#4C+C-85GpuDFZ%8 zW(Lm~@G&rehMz&bV2~QnwgJ!t4v3w`z`)Q1wE&c2!LtW^kfX@K)gd2f?300E7E}#r zhtL8j8+2|mXxbWNPBmzNehpNj9aM%w*`P5nP~QurXgUJ}18Cq1#0HJHor9_YU33es z5BV4vKv4raqYX4p4$8RiL2978y}m-(pdt=59Sl+fDk1-a#p^*GTm}XqP#FqM;ovF_ zIU+OM(pG z%ZQ@D)tDgUP+ahyB|!%8y=dS)OM;Ln0Pk56WMBXVdlA%7(DVd&WCy&Aaw*>#LffJsXoT>pTN z2>@w;;w1Iy0SlPLrgI%<6JYF^E`6L$ovBNG`how9V$-cM*aR4lOwT?Js)e)|7;Heb z5M#;o-N)I~8NW<_d>lTUZU&lxme{Uyf^A|cyODvBp{Ws6=#DMBWH}o|XtMk|iS5E$ I+4r*p02~-B8UO$Q delta 77210 zcmezHLGIE|xe3zshDN4l7M2DI3I+-wfJ`bV7#o>dfJ7A(61W%`7+M$@WRoD+)?--b{;Yu?GCJ=rv#=t}X zGbh|*sAn#k#Q?^O_AxM%h*?s1F~IS{eGDvw@J&4i7F1l1BEZ`EhyfR7WBtZJGR}@- zV1wb~zZlpsup>4>gc!T+Dh2|0aw3zYKx%P8d~s??d~!i)d|FXz;p9rDAftlP_~Mep zoE!#_EJ&s_50#&p7oVS;5}%TqRGJ>2o1c<8**8OG^1nsglQ%5k+x&~^BJ1XR9G{pc zpXaHSOe)GR&&w|@(aYBdr$|E+OK{S)m|n=pCeC7LX=X6FfmfqmgO!1Sfti89gaHIJ z7z7x28S)qy7+64D1{TH+1_lNmJw^rwJFox)0}~^gJOha0;A3Q9U}9pe1M!&HwL#{v zux93!Ffg&OgA_Ayur`5|aIk*|DPdui0r6PaRUs5FNRXM4qjs_(pY-HAE__T3BGV_b zG6_%4=Tj6c%`47K&r3~F02!E*pO-%Q7r(-EI{{YS>AexmO4ALpS>!m1GxCc{6f*NB z+XWX+el5#2nJbic`r;)l!rUNT#hF#9C6xu!8Ba31$m{9DLnN6YIU})%0c5BGn8?g4 znVuNQTsnES!0hQ8Rx`>?=UdMxF#XqjCWYx$(aZwVPc<+rOt+F@5}3}_$Sg2DZat#_ zFAoC)!oM97#J92Cx7gh<~0C?AILaH28IcfOGT8KCNfQy z(-E7zK}3M@%;bY2>Z~lx3=BOW115bZ;fsAk!xwwF00RSqnIl6Z z1A`_9n2`Md>BVIl*=0R@H?oJ|WD8@dz@C@?f-f^;IO zT(p3>kq@kP(Si>UO_K%1}6zN;Q7Od>>N<4WP1$q z!a5KkWDH7Sj2u@%6cej0m|`~vnE^?s%zhwcQc)lY7IsBYvgBax0`WN5--D#GK^Z|* z1H@!wWMHUg(e-CwU|?kd>0nh|#lXP8c94OAL4&QBfq_AaErXGPL4qw2>?Ein9gyX0 zdLU=AEdxa;+YXTVY%Poo49slqAoCfRPk{_I0vX574{`(_Bl9l?1_q8ukWxOze2{^h z3=9nQ42&)yHb2OqImV0(3|wA}3=E7eRUm;N?m`g94aDJ=1c|tVm<*iZAYo9RWdOOJ zan1=)$kl)pD1sF5wt|>ohcfd$0Qr@Hfq@Ssrdq+sz`*|&WF=UlUKb`~HxVu)0J7>H zBLl+{Mg|5!#wbPu1_6*OUotWLaFfa--s`3eQPhWYJO=$9hIWm(MOGwD+F*5U6aa*&hODb?P3NtWpurfdd zJcSt;I429aC-{dOWH^>Fz_G*7#MgF92sr~20mFvLt#Ni zA+`waNU-_*tPF<23=9IDO^l3!jE2G>I|aL%7#Wx(COSzlFbKgU7#M{07(fx)W~QK}{eSRq@&;2aPdZ{*7mA77f8S7K}wU&2tDSX2_9 zm(LIp;^-6a7#iZw0FttZFM)^{nfWq+s<-&uj4Ch#wa{e%*_D}>SrVUVW|1plh$TiQz6|N{$O_{Nit@pZGcqyooopXmFx_tni_+u+ ze9Ds>svCXmeoN+nP%z`(!&&iY7v zBPbh`0)-ej7`&l;Pzn`d;9`h@@<9|xe-?-V#UMUB4)l^I-&1m!JSkmN3K5H-I7JTC z>APmK$xp95$;wj?Dk&Hk7(iw)ia`uyW?*0t0Tni&@(#)dH9f%MAO|uqFo3j)@Iy*| zPymA1Al)EsB5dH+3xhC7FFykV2Ll6`%`E{^!N6bv5@&-1yep^)1JVo%AP^f|N-{7o zfQn&|ILKijHaFC9AR~m?Ar^z=Kx~oeg=(xKlQWA|>e(UX6R3=01UGmX7(n$lBO6E` zq!JZ|vMoW*g0evrBPT=+$R&)Rh7bb-gCMBLg|bCKY;K4eSr8kfkb!|g1;mD`k<>)u zm?5!kr~eIM6R!_I5{gA)ry#LG6&%d|0wnQjB=#gEHmGQZsh@`=z66QA9l{2AlYwFH z^jZf-@%obxF|dcuBeAa`u^%F_-yyMoBe5AlRT-$o3aT*~85o42YyprsG+bnn*cuQv zDEl!mm_RsSM_7T_5GOL&feeDOJ*PVgvy0cKAW4I2bx=Hll4LECcq3FBC`nF25?_kM z-hsqE31UOtcm;`lABp`K!d3>m@fCyvX1_yXgPh99G5KG+^7NMr*@UO77&6J$g9JfM zbx>eI*`PX_5gI`2K>DHLa~K&IgrMS!plp!mmOV85kIzLD`@t0mvtepj->h?2OP1jx5eI{b3lB`1FQ;X4&a4J6X&p ztLte@Z%AOa;9SGQzyQkC@{<{N%1?igz|1l^pkHKq!vtml&LcdKydgjNu7><{hr=u^ zlTCz0reB!AEWj8r{ow>=b;f|nhQi|06(%wZfaMwarz`q0i%j>N$js0A0%r8|#EH!E z(;pmWVPW*2oTwo@{lQXp0Zj&8a9hq!G!xKYQz z-~bhELDCJ<1=9`AKTtIw>H`ADb za-yypQjbi6#mvCSU~(g`I+IBJJkkppK;5zj98hx60w_cF0|SFuB9sGBype%n@KLD11q;9h!q}dZ>2?IB%1<2;N31lGy%Qa301~&f}AkIz@GZ-|W!^6TN&dtEUA*KWB zlCZF+u`)35{$OQbkl@g50~yD}#lXO!4`MR##b+~c7=TP>;bvfCfU-Hb`Ch^~JluM$ zlNC*L>ia>B7!FfWCI$xX)u3v?9Hftdn~8^kfx`mCX5o$pS!@Ynb8sJFXJFv40T!64 zf~;N#lJW#G8MtjY85lUcKYuCg*PaFj8E6flS|vM?}kR5NC?F)*-*1b|F|a5zLh zf&vD@;So6vva1%XM?k~@6zcW$j4iAT3?d>^K*lwKr6ff3Kn`pMb7VvggVeP!Ze?X) zP!NsJEnwhiW8A^cz@Q?+3zF$zJju?$pdqpa#OVU-(GdX^AsoG6j)90D$ml+>JtiU# zL5`cic%Ges!9t{)k)fV}V`S={;JbCMW1 zu7cd)!Ce6gyc-}l1aP~7?7i8^z`zi~eFvoefe0f5Lj*TF$gW4AtQ^BVe=@g)5t9S+ zWP6Kg_2)sFWf^T)7#M^fgNiH;MaEP%1_lvuVpRsS8APf<0jdIyITn$-AdV_HKsgxr zSwNx8&!WP{z##0w3CiNOjGI9QOaobI2WB&ffQErM?7*lgh!sAT186D5RY@7#J9(+dzY5((RlK3@p+wKn1t-I#2;B%>-(LNIwQSRyu-{ zfq_$c1v3K!m-KCR1_o~F$DmPK=`>JMmHxoOz`!RxiG_iIUwR`Ks3wLY1Yu(>8IAeS&PGHHXHt;3}N zD!=Oaic-@VxD+!$6(L`4X$1q95{S*h-NnVgz@-dgbMR%RGH|JYm^|F|3=9lhsvx!i z_dJjiH4s~byNQi~flD34mf!~U|F|?jY#Htfb_ND6O%Pjwdj~561D6(vt-@UlQm^d@ zGERemC5(xIflKErs0uyL%)r3?bq5mz0}BTW0|WO@FmnQ^!2JtivX+BH85u!rSpjZo z#_yaA3?ltp3=G^dj6I+pxM*r#3In$+<8)9Iipa4tFmTH;E&`=3-!wi{M~jU@~M*;$mQsFDuAnU@`F{7gQ`7f z@VQigfk6Y*U}+Elt6(%>V9-?MVqjog39hetoStrH7z_3VwfgzC_YM44>G&5JaHiIgtZM+twR*ivyVF!o-swL|W zgIJ*PoO2-Uo(v2OHw73N7D2Q#6@#40$_#3UGpK>a=RuNtkR_Q)7#P$tq1vvY%cvGI zFff3^ToqKufjTFuwG0dl??IL}gT}6{KrB$P%qqyhpbBco2!I%%5fN!Y1_rea3=9nF zf(#6SJYfI8gO8P2V)8XR#rkaw3=GDg&Xy)<3Wf10D7a+6anj7gz@Q51VEqDFafyL} z!5*Ye`yVJ#I5IEeVPMc%&dR{R3xLaT2(Z3pW2LF9U-?J;;{33=9mQX%NO4J9!xx3}IZOejWw}ril*5ub{n_U|t3W zli56wp)>9zOCV>iX(8v~(M;R{zgE`0~1`Cie44__-0mv9og$F92m^^2K zlz@z4umG6@R-yrNrI#Q$l$j#J))|>$iNT`iW@aX28K9L+~|SYBUyqB z4EK2<+KLz$EI}}<8gOou6>lgzA130j5 zfmA@kDi_q!1}X7az=tEOKvOi3usRGJ zrXmIgwYiK840VDG4BY%6u_&Ga6SZ8UyKa4w?WA* zBuapR!OmWQfx-SfHvkWMW_dVZJIxhvke63?R&>$YNi?%D@1^_2O$Ce{(S~fUx}|1_lNY z7Fh34#Kph>!V+wZ_A6N!7(iIyo}()>0|N-#zhP!z0AbE)_6lqa3?M97Vn30MfdPai zJM1;MK`n6x2BvuXR&E9c5SCc%FpH6a0fZ&W813J3GBCVllf@VB5 zHrsf0vrN9=*CCdin4FQSmjM~ggHC;ZXPjK?Z|(P=k&&4RG{wox$SK4CVhe+3L)pM2 zH<)CD&1}MEMprU|CQL!ord*sLg-l?Qm6Ll?fVeCVSP#S$K?X)#PphB^4_8)P@hO>Q@wxdanQ4{a3DNX|%>4M2)Z%1@a7S;~(13VP zzYqrKT9#CX`1rEKoKg^7oHqGlh)8{WQEFleL#Sg=h(UZvkf%FCe0dRQHZ?x6IJqP< zH#I(~G>suXxvV57HIJd7G$*IDfFU?MKFBrLHH0BPz9g3+zC5|Os3bo(sTj2Ws3esk zJ`b!Xz9cukI5n9eKF7=?5o`=-VN!8wNohem*yQ5M;^fH}BH8M53Nlj};&bwov%xdM zjwL0D$r%jsxurQJ;K@R;i{evCa*`NA+zrBALgIrXgW*mnPtIUSEGPgkhAJ*eEGkJ& z0ng2579_`m<`o&@(=u~X8RGNv;!`U!OX3rY(u*15lZuPuLCyEXf`a;Z@UUilZcQoC$)&dH6kS5HO$p7#1Lv8D137B^B7VEiVNaP5{t9r%Tr3gE}ncmUA8_s zF((J)mLl*nF9QZtz9B<=Zf0?Ed{Js@UI{~da%oXfYFw;AG{^7C^T5Eg?Y6YQAW)ZF6K5{CG+ zyyD3ZKf5Y{X7#~Qub0dapPZ9loXX(o7ZMa2?CI|ZNhg!{hD*pGj7l#}EJ}e`1Mx@6 z^mSWV#p>gWOHwlPknDsgOwCJyDq~12DJfzA$FECjPHIUiC=BC6Jbhi`!yJ7)T|hwx z_nm7{kbe+EJj73lMMa5~5G%pS6C873DTH-`pujE71LXv$eUlv`B>2GDyrd$&xID8Y zIb*UCXP-hQF;)yRXEru+>fTs-53WqQ{ z?B?m?$`Bu4oRXQ6nU`4)imaT(^kO51g2eRH;`ow$(6We<)Z`L|jQpIG__X|@_#jv3(4b(?FxU7HhWON?qP%>t1M?Ddz@>ilEfQlz7*?#H5^5 z2KNA1=JWFhCyw~^#N6D(cu)pSPs~MR-JJa7L{Kr6R+O5WlUZEC5D&H>9&9dHIcWBU zEe~8&fR>TegJKz6qCiV-P(UJbEhtFx3*sTE2{jRd$~{n7oRgm(pOadaniF3FD#gKt zI4FgJ%5ZS$l#*BpPt4(tL4FJ&?uhb216%`?f>H@6+oTp1feZmv1TZsllZs0cOHwCK zjFPO6FG|cyiO)-|fTaXT#AKE*1o(%$2Ep9E76j1Ddd|_h20P=8tDZBths*XTKEU0b)7e@^7 zNjce&+9D~jIF-R46nc=7Homx|s3bo-J|__r)wxMU2p2#KY^bud9R2)cP*Q}2fTy3E zKSO*xB!59e803{A6AOm&%)FBL>E|Sw#Z93>osw9R2rh0wGO+rEAuYckHID)8L{PP9 z5DzU*CjU;CmiKjZhGvc2Bt(4(U&b}LH&n77RQ5ykg9_o2%7WBlaN{5)zdR4zDu}O4 zO)LVHjbI;#IK%R4PEr~qJTmi=L4|z^Jbk&iI)%D3gt!}mbRY$2d@(46<)-E)7gRFD zXBNjNS0p+y#OD?if!Y?JN{}HwKGY{aFCDyi47{!kl(<240&E3zJf!Xhmu{f2N=!)s zFX+kxHDKa1@=J>#4FYh8fRY2KK~tU#YtVq|cF>xn#DW5lsY&_yCGm+VDMbt^`SH*y zFS#VYs2CI$;L-B;r zB$lLt$~*>8l@b*18WG?b)-(7INTTF|f@sGkB_mkCl2YMsN>gIejJDS41OQ1=2X&cI;I0OEjF zhk-PJ1_aWe%i6?2y;|r9kpvTH90#)8&4OvVp%|0+bOixs&B?Y2nUh(TOK^hPYLGJU zc*1+g^0vG;%mUMQMKdc*W=m3?zzZ5$0oe=cO)yPvR8*dvktD)+WpizkHzVWx z>4N#}@{C)i@0DQ^2lcGMYsx@9e2^AUkO(pGGkgJYpcvHc2X)DyT(El3LLp?nE+dQw z8vbTr@I>Q77GXlvfXoBUYA`S`Xn{pQ0$petCZO>bPG>A&mlp)Bp#kfGu7$fkT~wG+ zzWx`QYS1tqvNAPLbbv-g!GX@tU*SMtQ*vXu|uaCvISrufL2Y`~Z#ro{510l#oEP>mcWV1};EO1!0hL*+8il z#DRu_G#XzWjcS>g*gli44~me zM$kYh0|NtS69#PI)B=!|Q1KNYHdOr@5Ze)A7vqNMbF)~*!Rvm&W14C57q`eV~=@j35HE^m_W)P8M-3(7q5x=)x0_D;Ys!@eGjVLyVxsUZ8m= zkkNXR*JUf$gJzx>7#P575A`92hJa+Dt9d{p6pV%taZo|R2pU9YU|>i9sR7N+GB7ZJ z*C&FkWnf?c&3rJLLe%Gg)PUAGGB7ZdfY?xTKuc{HK{Jt{74qOES)d_q2FU6nM$kG> z1_lPuq6tRmP#I{*o)NlOXAa09&@e9p1H%On8>$ynWHN#Wwiy_1fW$%TLKzqsKr^y1 zanM?MM$mi+0|Nti-IFJSIoPS7wG@n?f{THH;SESLbcHQ=X_F6F3Ak_qjoN^CKNu!! z}=hl+#T4XT$w;-I8{9V!k=>YycIAaPJqe*+pJ7vW-H0F9D? z<_JI%EubNFMg|5D8OkU>3=E*W0or8&5(mxA zv_r)~`2@5A3nUJzDHcP;w}9#q&{#D{Vh;lY!)>U<0S3_UA;b|!7#JA1nILRXh60Ua zgB%SSxCUX6UQp%&6-6L6D06|>+|UdLng#=jgQ66~<_0l9Ap%OfAPI0>fGh#6-GMGY z1Brvu2582N8&caq){jX-78!$rm>Zf!K~rWR^`NW@VsnEGWPnW8fW$$C1t`yPL$j_k z$Z|>W(zkjB5QiHy9|&4}0F?l(+XUrcm^f(p1IQpyx(Bgg;-HnpAaPLg2C=!JB>`w! z4I~aK5kPEiXsH02Wdn(W%m%T!4M5?~z`y{SbpuI&iV6^$8=B2QlW-t$P_Y4GgBLL| zFff3o1IT`m1gM+= zB^YjKS#uZ^5?l-npi~T+qyeb`l|LXh%yFPN2Z@8qA`qJ!l#QUp0!SQGEP;v$Zcvs2 zO_G7q78e5ps0AhkVoNeG)Pq(-f;imJG7B`11=0*EyFhGiX!!+N)C>{_m17__H?%AR zt#AQ}gUU1zn;TlLfu=D);-K;k#D+Nnlyg9d7u2fj2hEUy6oCr9e$ccNwD6k_bseY> z1hKiH1tDmT2&5U*3|tLW11cOrY;LID%}{YrK?!1WgAxq`0|RI!1IR8=h=ADKo}f~& zo`K;oR0F601+lrIg(x31%Yh105StrXph`o{CeW3rOs1NNmswSD4X{ki=ggu|FcQ#Xyr>Vho_! za|Q-o2nQ5143^3BJ4~Pvdyg;jUVOtCqgTz7m zBN-SN)`QqkS8WBcK{X@;1H(=(1_og$`v^!}3{eR6ycTH3lFy)J!wbDjY_r278bMlmY^eErVQf&TdL71LU|@KF#D0my{)EK-jl^c*VPJqc z0<`BA#uh^oR|m17AqQGc4Qplx@h~vd!!*Qz6hVV13B-oFG!3-O0hGxZ7#IqX#H*0l zEg&{j?*t_F9whc55F2XdF{qhWKgV<2Zgn1$905qMb1QLg;(FU_Y;SX9_0OCM3SVA>`CKg>l;!q8~NbCp@ z8>&7AsvguTt40#9hl+!iYs^9tUkhSGdnmgCK^&+-hmqK4kk}89*v~+0Xi&cav7vfD zKrM4%ob1;qCJ9=O!N-S48bW-KKyaR1+bGT$FnMaDGGo-_osIg8Nt0hT>Pv!Jh)a>w zuY{_vm~7Z&?8(EAFi8Q44cfd3OFwQ%;*m(~EF^ZpL+FO0*$z;FbKeFBMn9*KP!iG2%+eGiHK6p8&3iTweI{Y3y&;y~l_H?KI-)ky61NbGG$>|IFgLrCmnNNiA|Wn^WTti45W^Nlu7#_6$cj0V$p zhOlw7f(pqUlM_3{8Lvz~7|bTl=rDO=hr;x^yICYApX`XPKh4U(0Ne8hUgij`7HmOF z9-&3aHCDv_w+B!*sFU^z$_91JzCzic?D_}F1}!cE?Qa0>of8K&`q&s4grMe2LfG{T zAcN!~90t%Bsw$KX>gZ`h*`O|#A(Rd3tb_K7fD8h)?>#``P>1?K*&s7Rplp!iqM&S0 zCq4nn26Yb8*yI_yu*`OX`9h41fPPahWp#D`Clnv_0 zO@OjNowsRFHmJik2g(NZ(H243&7i!u0?Gk(#z05ffE)xGF#v5O0I@;cmR(Rapnld7 zC>zw`J_Tii`dSyDY*0VzI+P9STY(m@gUkUn$DcvPL8A(9*cceN`m&8&t>1L)oA{nktkH>X&Il*=nFZ zlp&M@I`Y8+$_91D9H4AakHHPf232A{P&Q~uPY{$1>X1c1*`Q@RaZomBZB7c54ce8O z1!aROw<0jRo`C_hAP}^a8ssz3SV$dMf`I`v7SaM`gBJaP7C3{{fW|^5K*d3wxoJ=~ zXmQ^hC>yk@ZxNIY8X^I$%m?WO4Uw#aioa!KVAv7}<@{x2VAus^gT_k^K-r-2l4DRd zsB?A($_9;{T!OMeowRFEwgJ<0y+kIp$pO8olF*z6>Yl^KPC?ymMvlqndapBbPgc~^ z18)>%%CMfS*004V1KPkjIi+8KwZWQ!!De!0zw-16hgnz{|9~a7^b4@=v1VXcF!^M^ z@^p_C>=Kg`L^vk%OyGcUbS4Nu7$Fk`SVI^Y7$m{kY9!K~kWZ056dK=_*C60=zwTkPW4vLVt#lxF9&$YmySvVzJ42lhjyQq!<|9g7vMLB*2ssK6&3HHP(+( z3=AG%!9SA(nC3)G=9{d>YAMYC*(*8OXR-j3MdakT$!e^H(hLl@rx$)^6rMb1vH;tO zNCt*8%#$}wR$}#0W?-cb4NnIgdSSAVkK6g8$Pv6IWD zsIiI~FfhbSUN}XWcSkG(186S>CJ8{n z8;+WjC@Od~C)Ce^sE`GnWCK=1j4_s|#&k}An*u&*CrwBVc8pFV0|RX5CQPX21WZKs z!$fWHuE`akZJjVtxH=1%i0lV5M+P1y&?!5NlO`LA3A2I*nnFOVde8t2s8k9$G=j$lYA-X2 zf`-r-gBZYFbVe1hn?V_I&Q{R48d!-6R0(?;Xc4A9=y)BNhZyHDF)}4EGB8YEc$H0R z@`5=mlOMQ9Oz#h6=9w&ek5`oqwh$C@VhlUzAQ$kdGTffv!(bdFraMVazA#VR8RR0E zE1+X5K-Z%oN0`6wvZ5(2^}qkOauNdeaj*m_@-Snt_BMCzi#>Pv_@g7MondFFyG< zU&-VTvYbNj1qkqI{^^1~Ou~{dD=|(t15J)saDqw*P`GJ;Cd4yA1AL%~Mi31W1yu?l zHfY2VH01#bb+EVwWX=aP%necxI;IIM&H&zg%m5mX2dM|e3|L%)fdRw@C3=wh_n^aB z)F=OwSDda8z$5@Wj%5b?P%wq*d2g5vrb~g&1It>#WB@vZMPT~B)hq_};tZh46OgGO z*9bANGJqOqu(Sf=g9h<#0~#;~u|cytprfZiY>NQ0h!iG-4J3A6dr$nfm~Z&VfP})QpC)LBru7y)M%y z8ZnDZu3XO#F3$o%O?FmDG=u78SR(@DH%1TvJA(zv29-Xr&Oc~10&FrC_3JMy~L>SCy&?Y1p8#J#4Qx7WBLFR)JlnqLCprZ*vnnB6B11b(m%6(8aC@D{YvO%dA zw3`5=9u!3LpyIDVz5xXnDBq#6c^IaLNi*|L*G*tnnLf9lS!Md&L?&&}aVC?02#HL; zlE^H=s5SkeF1s-3s1iZY1Rtoy2nrLBNimZRg~bIyQ&6CMiz3SC0M^F%9@I3n1qBKy zn}bq4NaGt$1_n^ng326F*n{LiDFhT?APYchKo}I*5g-$$H+*Lm&|SlY&;}|5VcOzA z-UF$JV$dmXmp~0iSy1u?se)OY!_B~8!N>qE>^P?f7P5i{CLy}Ym>3w!K$=8By+veK zykTNsFqj-TMFcc4iEP>u9tH+bsRZ%{$oU{S5DjZ|LkwnMkYQ$EPyiWi3z}mCse-xZ z2M+@SXu=6(0;oI$$$?A&O%fwJ!G@WEVKL~4lIa|J>;gd!ypY*^kTy_p2-61Ys)DqE zA_`>reHI3W29N-V0}Uh)7u0nH(J*!KY~XWAKsgK)u29tsv)G``WYKF-%`llupe@m0 zAAwGF09g<7kqRHAP8G>y;Jve|j2Fthl1(D);Gl@;4LgZfmiiwG(@#eVY_00Un49J4!($5 zjZKX}N2DlNfT~%f#(ok*JcA3v2Yb*Y`TzU>|4;VVA29jCehW~Y#2^7a!cqZzoTUuI zS9_TU-|QzV>X}SVIIwtnel8Q+^raVA#5o`>e%TM34xVP3oO~p!9(MSNE*GpNjnoK- zbQWfSdI;cdK}QCA1}o%jlST%HCJi=mByLB>^b8S*A&WFYMHJeJm`xfCpu;mc{zFWK z9Hm(=fx-pz9&j*(buqw?Y=ND%$-~jf*eTe^z%avOMZ|(mg*6@P2rg zalt8tO&TnVG@!2J;a&?pgGG^n;Y1P-?|}nLb_lLug!qB&|NqVZkMc7yvQ6ecp~QG% zveAhO9;Jm$vL6^AjzoRd>d6)-YPzIe)h`ks?)5|af^dra;)Z7^NOk)3OL z))HpE>3>QXxhCH_9mcqJvf-I#%}_qX0WEEymJFzqe1#dZ00ou-m^j$QC*M6IQU4LN zg_emOGy%l|T7bq1UJt><$Of8SW&xcN$|eMwut|YtE9gKL9nioS3utpbyKWO` zNe2t45@)vr)jdosto@*!_AKn6Q57Z@cF;i&tSrw!y%r`$4$#JIRu<5bMfT^Q&Jd`S z;*bC>P+($Yst0XJX8}2av+@-q0|Vy`P|42u7&O?)$;{2bz{L55m4Sho^FJ#C0}Ce? z=sX!tQ8tEp1~yL6jyZNt(9k0Xrx_aq11BeF2Rs+&Y|uVCYN`Imu#L7KA^Gy=&9Do!RBom1nu#m>N>!N4LqdBHicj9O56#n}Uz;^G8tFlORh z#RGEqP9BiMPw+4>uyS7KVPIh6e8$7Tz|IMp4CCNr;RU(-FX(^(1{NLA*#N3vL7QyB zLBcJU!NkD8nGPBm<=hRLLuOz}nJjl+Ou7lwhT&WT8u|rEGB9z13TP1tl;}9S zL5Edv7IT2Y2sEG0#hJ{(z`)H}Qx7_6g42Z)6uHNk85sCD3t1T$_&L{tPQHTK7B9xa zz`(f|)WYCA0_p>Du4M*!@Ga;}1Wr@X5g?oepp!i~K?Af3oSBRa3=W*N%nS?-++RR# z6GrX_Ac~25DTrc$nVXl#QqRD^3EG~?z-a~!f>~gLx3hq}(E&OIgmW`H1A_o3Xkb=> zvy%m6us<)zV9<#P42;~fGb05`aHKFGnTASq7Jj$KAhP@9m66SQ5Pg%fll zFb5~-{8|BqdLA8S1#QsDMWCZAm=!@I1Pr{Oii=qZ#Ae~U!NkD8tPEmv@MfkmFsp!= zJba*0V`fzlTYwLA<_NPIh%Lf5nVErsSslcd;FIQMU|`k&v1R!DKxtSL#8%)t4m$Wr z3&d8b=L0o?n6*I#i3S79dC>TV4#@TFpz{qOvCXFgI$DYI3MhecmVtH-bAnozOq?0u z3=KNi5ax3}lU7y+2F?$lW(4OwP^*D+D|jG*M}bl0BP#;~pD}11wkn9pz_$-{WCf!d zs3|DGKLb=!fE~`lEh@p!4O;X8b~_8Bhy?#pkSy5wEJ92Y{AWS3U>~qBGD`3Vf@b5j zK^|gZm6l-;I0UkUje$WBbW#Bm14|gl(K;Zf34w;^nfMr))j&td{N}1>U|`~71n+kh z0WBwCb^#5qGdr;{Fo=T2xS3r*g&BjGDaZ!UdM^f0XPY~h%U}s>ESq`#PfDz=;XwX7>&~y)I*k8sAGz~2XUig{^k^r?M zzA`W{$k>5&2!SO)%^O)+P{4^XLT!|D1T6z*%mkYVax!QIBjX&9pgd?HBV#dGr+hr9 zFod#afJ}t4L7fz+8d*nB88(3tq*vxSD7>eGO$802F$jPXQ$IUALKIejqSJws8M^ia zv?iEw4k*%8XH?>Xd2B-vs+I>){fmZY}fM%B%=QwaMFsPS+{1LzjDzJhe=7AOnsBu8_6*Dj(3QVuX2!PIiQvs#Vjcg1ID$^Jk7(mgc1R6{MMNbgKP{_Fk3`(H7pPP?? zAr&IbXuzNZ>U)auF)-9YgqVsLlo_KL4H#7afC7jQJB$R%VQYI)p)CD=1ZNff)uG z;ANb{!o|R#dj*t{wt$Kl&Ty)~dH0xhfrpTWymKgSMqmJC=`21pfK&}5e2$t)_M z?lRal!l2dTplU-$50q|p!|Z@KxSNYi2j2xb`20`MNEj#tK;3%AIiTuR7hG7J2NgRK zj0_CA??74QJg7_oO^<1U$}Lcgfljq#ymFt5fk7YCWZD2KDpWwdFdb0Hfx4wQLJri6 zMTA^EgMuQc?Dz)r)=p5NJ?9iR1A{K;Y$C>Qpg>_}Vqnl!1{HzdKn+kLGJNn1T}s@d{AM_I0v*AO9s?EW%LIZKcK@bKqp2qI6>2q z0Rw|h38-v1>H=~B$bLxaQ^3Q(AkhJe;!_|`fwpcKfzGXJ05$kPO%F&;0fmez$alUF z16i3t=?a|3PJ>e>$Sul@v8>FXNn{2F0Z>yJWCpk{(qv!<*<pKybZQ%80wcJV4Q5dM52{o2KxaxrvZG=(C~cd9Mspwn7T^O= z%*{Y!XkdHi3xF!QDZC5}_26JpXRtJ8XJBBqna|6>zz#Z%melIUs*#I<0fbo4#R@ucj(;a_XhXaXvQ%gCg?o|$x=2QfGcf2){&`PES|6ksLnJ^f(AlPp3_&1j?R3GvOrn!dJ>=#GX#uGT z25VkB`N=~wDVSK$e60F5dp_F7$OCE|gU@hhh>V>q{G^a^&UDaCIn&>CF>*|v@kBxh zRLp{04r-5q=>H6pFFjFXTs!&a6aVQk-Go&cvx8bxObipJAN(FQHds9;_{Iwm$p|)$k&^{1!UUFuob&=BSvbYOB3yzD zjGW@2OE6$_uFEFxdSk=5W%BnoN{lZiOTCq0-3>ZCX7au_s*@Am3QzBzz{ttV!p!`w z4&*ErM&{nhoo}ryA=ZE#$_1WL1(nqBi#fi5OaKWpvw{4@!pwZK4#Z_)WZpIT&)amy zlao{4WicL|eEyvSp(7NVPyWs$f-2h;k`5?@8p>G8jKGnx4xev3c6{- z%p|^q0kogEv^X`{sHh})vhN2oF6fCT@veT;9aY$bEu0;FJmW2VU5rf4z?-~F3m9N~ z#N%E4ASWF7h5E)DnKKlm7G>tAKyJJ6o%}yUV)FkF)|1^onyP?~qX1vU0o%t8+3yWD z+t|oE9(2jZn3Ds^5$;<~GEK@XjB8&QD!*60Nt`Q*ylViRqOrHBqdh)?<5|dwl zQ<=>3Rcf;KcVA)fnGxU+H3J)NVcH{2I;(Z+>7{Hz_DauSwPb~t6=wzuMY6_sBMr?3}qz2^e>C?}zXH}Z~ z`IFe>er9e7XwqPS9vlO*2z*Y#4Z zY6?Qaupk~3>fq~JCfEJU;{YWRa6)+fQ<@8Le9>fqU#3E6r(J+N?ea_45FS>>M$l6` z5|ax{Ghq=43PnQ$2DmCi!^t~;HSxH32D|#jLu{D*lSyuJ({GK*JANyI;)WF*g_9?; zh)n+X+hB71pHyD(o_o-I1L(-0$>;w(<^`oG$f*+`haCI6Wb(X!;=IK;HZx9)`(%|K+C3Ol9HV1kH+r3fO?jXa9#!kC@EFGrdZPm1n8}qr`OoH*7pp zZ5Vl`uL6nKF!D^Dz*sR|{2iOhb`C~H9meSkm>3g0K|MiG>lj3X`m3OpBdAjdnqvmB zVf|PT8`L@nbx=WUP-hi1?FwRpDvj9b>r&a3r!h0~OrOBa_-FdY6n2a0K8%b4)88#* z6xsfQh4Bm{c#s3szXG*gb*CR>V?4lAl003}pGjhRA3I~*bk1kYJll0S7_FJ6ALC*a znV!qV7`go`7o!#vi;1O~!E|L_#&?iC`tO366sC6>vk6S+3uY1mk4}QZ0pub^1}_Fs zuMors4cIVEUnt5f%nOdcmBp^KmFYs zW~1pM0*rowVIVm;W@d<({(l{#JZRO10Q@R90nkwc;H%ugm*@mc?+aowm_9FuU19n+ z1y+UWlLQ!rz_aflb3ol>AqG|OG9(yZi9wYCbj&)455l1C8R*Di5F3O+{6ioH6odGn z;R7faJS_&=`-;p54dQ_Kpo(0GK{ttk8`S9pi9lCFfDS%{a=`|G4rWK@gC^KPd{7HO zh(VtLbn6$04;oMrVlZULK{Ky*a%GCVA!t?`qzZ&V&Rm10Y8#Xf>W~XDm@r(Qd^1J9 z{yS6@6zM_?W(-oG^bA^Zz`(#D#9+aoiN?2v@*$>JF(g9yppLl^gAGG7ln?433o+O+ zEQRtx-A*9}2Zp0iKGc;C47Z>HkkE2s0IyR6$wC852;3850C)X_7+e@EpnOojONha3 zda?*(=wzX9BE0eN=||9oh(DPOr@t3r^qDRo##rx)bU!1wjzz9AK*b-d&V@=Mm4#3d zP+2m4A~&Ph_Wfdvos6K2%?KJ=0IhiejRe4Q1BeY32jx}RK6Q|PVCuoS12h5wJ!J!Y zoHgve7f>)kJ*Q?&)zx%;MmVECXc44eUGt(E4%M?sw3z2W-PT$dQbo1?3D344_hn5!6*> zfK0{1HoSv`7(tisL0rZFvmWeA(6}qimr!;+*o~l3445}Ti+RvAgSd>)COp_6@UBvj zC<8$Y@S1NA9Y_EhiX2Z+*MT)d*`Vry5$aITI58u#L!t2vHV3L69N$nj*c_<&ps`n& zISQa*ahO41&7h?hph-ed!hvcA8zejZ-4|x@dQfixmc~Fs*|5-r+7Gq|ssOz)ItQ~)JB(3Oaw0WJ|Oi1DC$6UGK@ zPyn$(-T-Y12eCoU1fNR4$-n>_7X=MC!NfrmJ0Ld5WuR+FL2QuAKu5oT*dW)~f;J&* zK_-;zouM3%1)%k*AVr`kh=huR;t6yv3`iVQ6@r3KgcG#li-7@D|AE+`O1J1jGjU z0F>B3Y>--zLqKehqe1i3Fg9rGJ&X<74G&|3vM-Dc$}}*xAIN?YZpiT*pk2W*3D9aa z7#p-6AI7c(`4Z%91_sawIRi*9X!#*%gCUF!PEFhl3?PSrDshlF$T8q(h1vy9DBKJT zfuMmTPy+#^2xKYfz#$MDWGQGv3WyD|6tw;X#0D)p04GsUvV&e$DWU^OqM#Wf5F3;} zKp4aZg%*g-?FtGj1_m*Z2Xr9EYk=6Au&wN1m+CMufD#CZ4ci6}ni>JEYqXu-S-~z{ z4>C(c7ZOt-Hj25rkTMu#F3ea^;DFSFVi3fJ84DVd5CLryf>x>^HYmnHYCvp|*`RO+ zu|a+S2c8~7J$PX!s4)qX02M_bHpl`{sR3ex`~a$pKx|O50W~r~Y*1PTH8MeLP!a+y zC%K9XndZ5fdRCOAEXB45pYTnU|>iE zB^M9|Nq~F>nw0~wLB0Z=t^hI!l-59OZcrj)U|;}E!+_L)n$)0^6F_P}bsLBcJFoz> z7y~2@$|xW<>|BCfP|tv7e?SFSJxCF#0t9hjhZKNDkU-)f`#@~iAqAiVkU`?0=mN1} z2NQs{CV|93l_ZGG4Xr4_AqvXEAWK15ACj&?(I%n~PIL9(3noDvP;v%^xQGzs?n6)~ z0wfNKKMtNii^h#6jr;)Un_OmCLa52NdR@rCuP*KrJUI8+;uKXrLS_4oaAy z869rV=~+sQ){>$~RvJOlJjBZB`;-{P>!CJ)QlSVa))^SUw+xGjK@tn-fEpMZoWzYG z-UJ0JNIfX&gMtji2KffG_!Gni`52TKKx~kUKyeOYgM0=KIx$F@1imQ`WC19`!9gU( zzyPXWz~Lyy0G`qW7vo}(Lu5c_`he7fvJdE350IfC$Aj3gU<5@GNF0=%Kx|krf`Uav z9CEM|IPaQ(@(2UOryvPXY6RtT7#ozrL`)z)29-%5Hps`IY8=D{`4a3i6G*^ zAYXz~HHZyz9B9%V#0EJC?0a#D@4=IzAj?4g6_6$n8#M6>u1mxrc@flw0EvTEG=m%n zVuymRdj>_g3FIg%(8^Sp??KIakY%7k1H^{;9-I}$A*Cs}-U1!90ult}a}iUBFF|Z> zP}o9Sv!GLqKqV}wZvkS1LI<>R5yS>L2-Hmmu|W<1SqNf-q5_<5Bp~;cgVKcvNCE5w z9W#hsAieb<2~d!NHJCwy5gbHj5SN13+@K~2tP+!iT$%uOkR(zFnL(-pP-t<3;s@pd zP=W!46bPF`ECxGNnt>sUfuSCJae|0BIKzT(7!Z+W0NB|>2Zh|fT22*d^@IuK@5m>gHE@2LP$395z}LB>N% ze$YG?NH-`|ftKil*dXV^*q|T)nFew?2s0{7j|*qg=T%?;-%1PGo64v#J;;U?ECedz zL6}itdLL8>w88;|85O3VvS9_g15{vxFw7mGVRlB4vl$o|K!-sIL)jZabuE+)TIvLH z2WTw-2s0{7|E0mGU$4Nx09p$U!Z71NMLKAL0^}9Y0XV{-rZ58o18DgQj18(KLB@g3 zuK{70UeN3&BPi4uAm`HvL)oBdLKqu#;UP#bXz5Hnh=6J408O-lvMngxf$k!OvO%{Q z3PahTCMHO;3?l;r2*dP(wynaB4Nw8;1vN?-AZPpwL)iu(aRtb=so<+q6`*AoXpuJ~ zC^vwPfdeUmvO!zEgrRH?khlV5Nk3?%Im}|vLSsfyp#(Z&3Zw?g2DPV!p={9hERdr? z%lknXrZV(Fr&isTUwBq1Fhx2UTnW%G^+)51ZYh#%%PxjxnOM2>QopTG&abn4hnzJ?LA1ELFbvm6zL#|8zHel zcSXR|*dd9#BC%tT*hxt2OeA(gJrW0W&MC~$9whNeNbH$NY|sIyF!kGz#P=Yv4o9RH&`K3(uqz?4HIUfgHB?YF zCP?B|%nU&cFoPVBB;1kMpry<(H7Q8qSxD>xBzD>Kz(`i{`X(eH@B$yG{e4K{Q;^u8 zHNY@y79fd(R@uPB*C2^+LSln1qk*Y84H2LIJd#zg{yKyM3QLB&NbJW*?3YOF_egBe zVjY;Fzmdd2S8u|^K?`$WY<|$1H>f8;SF*tiS4|`deI&Li65ASy?TEw%UmyoH)E7xS z7>ON;#7;nBr-Rm6!(3O5B+-b(ZbxGGBC#hUv1cN&4mBp!vtPC#N8vobKa!ZcJONq~-`g^Bke ziO)h}FGFH)oxV1oRlNQ(lF%b0HWO%38Prdp`%z&=OCgD?BeBhq*v?37PY@fln*cP1 z0a_*vWrNOlfhQ%<0WYwoavVqzs2Re*z>o>j40QzPT0}-rABKT}0d%GdOnnVhJ!r6` z5lMYFhz(T_I@1NFehO4QsPQoqbbt)ZXPZD8pqA|fv7sX`dqEnY>=Phys2b2!o-ha9 z0Et7@+<~eG4OBk_i9^+c&TE0G{|FKXsRt#cuTTx3=HM@o1XKg)UQw6^(0MH|hl0*% zfw5IUi=#okdQcymoq++g=o3^dfL6f4)Yya6K+W_`)SdnHI5s%9G!`!I+NRdXG|u4j0F;4pwL`GvXqJ4hVVi)LV8 z_zkiE%4P#C5QJI)I(v{2Dy|L^hq4Wj*p47JRJ}Wh4ej!Hb1*OngAVTk1y>kI0;(th z#D@A9bOkERL7)vMFm@|Q4b-4cutAXZ*z=IY7eU2AJ+|#g;=7^Zpka+Opb=D9=L~eL zC8%=->VVw@X@ENDF^COy5cnudsKtz+)yGh_1QJ^jiLHgiHb!EDE`bKw3rc?sz90!u zPnv;&AsEDl8k&a02F*->G=M^@A0!TS+)NM~)Ny8DV3^Cvz#t4|gZ5OyPVd`@qy~H# zCMauwj^*ZLsAph=a;}0DLD_deY^VjGo4;ZGP0)#%us-HjBsKp*Y-k9vf|mJ1^>TyQ z&^{(V=&VX8TM8r&R#VTwpabGSB}|dnpqm+C@eSTP0P6REN->Z@P<8}JJ(Qh@#4ZN0 zp`NKhVz(l(!3S^FgI&SEFbyOD?TF3-Spa1(1&Kq|fKTCs`f>}B_&yLDDt;WqhUx|F zYy)*}LFLRXkT_J$0}vakrv4=o2Xt2*EIL>~3!8VsKquQHdNdV#8w9NlNcBnyg?kOL@0<2)er?@Lk*3CS^!F$pnYaAN92Ok zK-HIl*iiMLy^5gTIcRvI3nUIzGXcbgs+kEsE)>dH4U&NRcncC6e6%N2{4_`$>QK;? zs<5v8Es*0t97r6b z2voL%*ieIXL2RhFIfxA!<^zpQfY?yIu1M@45F6@&L=YRQJ_~$YC{&^iBmp&aB8Ux| zw_;#mmI~Bx+ zs#%J}-U!+<1WU<#kt9wcv9BVrZz8cDAhDkyv0o#x-y^ZVA+di!*n zGgfOIXiR_t9@fkQP42+hpt&3v+jP3(b5`p#(D*f|{sdKL;2|bZA<4kN0Gb+riGy~a zz}TPzNnmWyj=vaZi4iC0-A0oq=W)VMnTf_IJT5Q_ykiFg9q> z6pRf%CIM8~F)%QI7i2@(pmA218t`~3sDOixr^4z<&=@L=EeRe&g(?D%KS7Irnd!Nq ztm2aDps^09kRcM=bo$&-R`JOiWjytuL)2lTr{F;)sB-Y;A}AX)pb1lxjATqY5<3rx z4IWg2>IDxTLD`_ANnqxH&Shs5V}Nu9CQtS)6SoD8Rl=k}+mv8z@bD1S2+$GhF!B9J zR-T+(TPAJ@y6hDu3myxC>UxBv5_G35OwHTL3(LgoL7SFfW5Dd7Aq!}wA&kTZ-wFg3 zS4I+7M`9ZzvCWa#&PZ%`Bz7=_4bG+v;Sdfe%`$+tO~D)ly6FbS1|2;DV}owIfw5bV z^mZVzLHn&>YGxyeFG6B3V*>3gh58J%5eueaCz2x29xRyn86iV#_13m66y6NNn)v5Xc|~2Jk&Puu*m2>9&`c z#OotKN})9;XrC0UKFS7(L+cUHekquE9g;YB;0LN^5|TK0fCnnR3P~J1zylTE1`&tE zE@*od%z~2;32;nbKw^Uqet@X~59B}%`iZ0lJa_}G5?dUJt;hnJW`HVE zMUv1#VjCc_LHUtU5qw6{%Y|&h(^X{IWv5?_V)fvG7Ez#?EaB_oy2DJ$)4x7r zm6-nWFq6deNLhC7>32fdc&E2|Fd9sc-NPb0{e%ajtSZ!3AlJjnThOu{n6E%bi!q8! zPcvjyo}5@J>;!f*)cqhg!}1I0BpFy90o?%uV}q6r!;&g^mQQkelP9BcJ=AlcB^!)T z_B>DufR3%~2C+f0#K6EH3yL^srL+pfhE_+qps^lkf4mCBhIXA7gV@k`Gy)AqK>Ks~ zAU4#y^^-sxXqRa{hz;!mfrmJt&JW*HuH=pnd6oplr}8Xg1LJBgkSu0=TLxu=rmPyEY|zTVZYUeHfNv6%4O)#j1Ih+1 z+MCD1z)%nJ8E95?5mW+H`ELcWL1E6ozyKOe6#^X?!oa|A94ZdVS!bbaP;$8pWrG@R zH=%4$UjcMv2}m#KB*UjranJL5`RXWrG|s8_EVbVjYML&EH#~Y*5zP1!aR`@Bowz zikf3kHfU+m87R9Rw2bKzlmlAMa0AK)WvzQqHYjU7hq6J7uRcK8pfyY1pls0mEcmo> z0R{%p>O0V&vycD-18Aud2k7K#0R{%pu>gEfHs}B&5zvwzkRnin8Z;UWVuP|G=-?j^ z8?;;xv`ZPp1}#+6f@%gWN&p>;E(9&n+(F_(kdO<6vOysi4rPO~Vl0#mN{q=+wi{^B zA|1*B`LYVch8B$tP&Oz?+n{VvOo2}r7iIvT6EGJf4lO+wL)jqp%b{#gsSG|a9F$E! z2l|7=MIjD72V&QYGJwurV7LO}h(Z=ufzCh^g04h+02K!@9k1IpP&OzT9)Ymy!FQ^i zf^ZntgKo@&vO$Zs=W)=)NRu-6{S2CYE?ZCV$CR?49B@jz^5P%#$=QX~mk9+e4YgM3f`WrKWB z24#a5Kh;3lpfalg$_ABLlR<1~O%FP*L`WJELi3^GpxOa+o)SnLWaerPP&FeBS$nqy zst6P;d!cMljeZ!)2Bq_pP&O!?pNFzR4NTBLI>=B^?fwKR4r*DxhO)C57#KizLV?tP z7M6X5ikE__8PG8;LZDI;w6vO&fdRw@MSQ1Z5x4os*Mwb7bnFi}=7TQIN?XlR&P3 zx*8Nej8IpD5<1M)plD!(x*F^_kk=U)7(nYfVU7kn2py~p&CJN*>aN8HOzLEj5YLyX`)EO8UKv|O!>KRZ&jL~BHG7Wb9 z>8@W`4W{e5Fjq{Un9b^82&(2lw^f2V{ZRG~BsL4E6ABd<0JEp}B{PXnzZ=GAAPLIN zpnE$(;!t)0m_5DDmAQQS+;B!4SjPa|2L%;bpdbOY%Asrz5L;yWzi>uz5ojr&0}_I= zE2bw-Vi%X3fFv{r#D#s+s1 zp?XE8Z&Y9ruLpPcph6a)o&qSJgPJx->;NQo3=%s7iCu!k2DL6>otz#daZrmACcXqB z4k~RJ7&bsSpcrP@gTw}%_z%+nK3@mwIMBKIu-?)eka|$!WME+Ufy8D3b!njD0!VBb zB(?@CXov%<$OK8k0g3H{#0H)I0kb#-NxT4wU4z61o&N??KLsQXEo~RT*r3XH4VW|i zpF4}bB($)60TP0;L1!K^N>5)E#Tc9j6#`GAL)oCKQDEIc&}}F%Hh8uiT8e>gJ%NdX zXT_o7pxaGg;-Cvn7-go%MKg-?f|`J!nL1D>PabsT1o$vtnF-7yjJne&9%2!mu42G0 zq6sP`KwWB3IRuKk4?&Psw4f{w+PVmm0~I0u(;E-72v0vy$SPt9S~(38hw0%6M(6>F zgD^-Bs8j~+zl3)67;2^)>a&Z>f(i_f5}0;{U`VM0vXX7GqLwfxOv8lfiU#cBlS8xw zG-HAp7(gWsND-*p4>AB`2Y5ghx*8bd{uN+5YbPdx9AlK*boy0U(QECV=i_K{kO0v^NTD0%&b4NEOTtJ|PHyf|{!!Igm-9 zEnUbafR?AuG7(yXANZkFi_KQM~OptKkSjs4 z^a^S;EQf(Eb2$$3zwJ{r=W&EFFo1F@$OKSd7iI$Z*gT}*Uc$t{P(FEKzwmU0HS8>w zAZ4)NC<$X=0G&$+G6K{B0m*?J0bU7+WP}V014GAj$22Ap&>7hvRWK7e!XYPhgG|t# ze(@fYFla>+C`=eYm5(FH<+9G8qfJ4_vw_7K7!E`*Fn}5&AWgc{Gm{ymSzoY#&JIe{ z5S~6KnNdL3A`-Gw5TpXs4g*;Ua@Y(|RgL5@P@VH1WQQ&2JWY@)n8Rj7f-h$QUk47F zqyou-OqdTf0on#)5MX0qaGd_}HKVX7Xb22Bi-oW=Fo18`kzI%8ffdn+pf{QRF_Z=2 zYf$G%9OR;@8EgW&A~A>r4QfTfT)_*fLy`Oe>MjX`bjgBR4gom*b@UeryLa8 zpw=Zw4rD?rnk!FmFfi-{n*eHjfK90?C0)*o0<63nv4E6WD~c zprc!n(!`25gfBp*!c4e}X2J-pj*;BZ6Ax+Rf_&jJU9g@N5v?s;3=D=KhfjB@XBFUeNI=Aj+w_efm7uy9l)iUx zF)(O>REk!xq80~FxEL5%rW;nViU@*Q9-whFkOl?@h8JAZ<1!ejxr1bs0z#sM7(ZH=%jGB87qB zfDpty(0&1!d50n9Axr=r#@sr&aFVd-HHZ|{Kn8|BIR*x&>4BMy!nPODOt&a!U;s6z zKmiNtH^EGQhGxVCCD0{WjGDr>57A8MsbyeT!U%C6Xk$LigkNYT6exp23}gc6+C7je zScrix1wR2b0n}9j$$>%)R9=CS2h1N5Dhv#o(;c%Ig_A(zWFTcQBYre6FwEhEI0AG! z2uKcO1n9;-kP)Ef56BotT?U3=M38}|jKNq1)YOA+UjnI{VhujeUzd%60dx>ANCe?~3=9mm z;KTjr_%kpBg3`ito*YKxBlRV=+vYH~NJbx1@!?=#0AcQK70})Y5azm~0vdP(VXj@O zpt=u)xm+1lL4AJ^=1OE#0iC-G!d&ZAB6t`WK$vfl%1<^11`y_2xLu}=QB;M=z8_gKNyP43eb+kPgPdA=ZAByXxXi;c^}jqO`g znJ4kFe+Qk4%^u1va{|f+ohx$=$_5?( z0GcKS=>=USc?&8I%6Opt0U&YE9;P=?anNP;pP=k#pse<7yJbH!J0oMqbjJzI{)`Kz zPn^Jfobk)_$cfDUj2_chPGl};jG3-DiP@j=!SupO%;k(N(_eykTc%r1X7*?NFuij! zvo_;zaGpCcnOT5QVfxL<%<7EmrZY}qR%e-_Gp?Dw5F{)i3AzT4QB!#O1CZh)(?5bl=SVUzM1U^NWBfARaVoPq>k}CU zh9#f^XL`d_W?^X3vj8W?4O5v}1?1`;gHG=NorBI+4`MPf@PO9vFt;%>FtD|3zr2+B zHb2jKJ4Yr41`uXDw|&=EW_}|HGfOPjb{HEOZGZTjxrv?8XnM+fW^E=j%k2~2Gyltg zTMWugYa>`%Si~V&ZYDDW1A8`TV2lMcjmKWN-6NJIMugFD`_e*|Yb=b0+iS{L#N|-* zZ=AvsWDXUv1bKzk#Kh1PeE)}V2WadIbQUWpGcaf{q%kB%Vb48V^L621)Ww4*2ciV0NM|DVEV)+R^jP;&azmrfmE(xnyjej zx836$%WFo@Mh1q1;G6XhWk?=SVA!M~1iIF5HR!I8MHxao+#s~W)YJwgdr;>X zLCx}bT>CkzY>Amc!Dm7sd z=|%>bGaDHg)3aNvA}|(ZTha8EC!Mp9BY};G#e?2qzP9{XTHUvCLqzC z%mX*ojfr8p#Vrq6DwyNbH{D}VR}%zX?ZC(enpj|BLMvuTP;ta^VEX@iEOLU@pj#SP*hSbG7+6`DSlDH!>)mG&3-VxRU|`V!Hy=Rz z*;sTz^(hNze+bJ;(2O$&3n)3W#)CqilNXe*IKi8hK*cZv6DMfP1Pdo<=LrXAFZjxX zgz3}nv&ic@Lk3--+G_(rcYA=AN-=PPcVBQG2c7TFX$|V?a~5xZbe|=Kk+E^Q`$HC2 z0dvr;58|6Z<0*{741C7Z=R9PI<@*h4zRFpHT)^{|eLDLimR14K-5eY`V3o{#417(~ z=R9JOh3MA@i!yRD@V%aX5+r&Tq~8cE%EZjTcVqguM=ZXKSEjo>X7OW;m_GS2iw@(O z=?5OO%w=3YJ?;sM4#b>zunvejW<6m!E>H`)H=-IMD#O6HXnNsOmS~7*E0X9PxM)9; zsQWXR+L=hAo1U@QGksv4{`ncpc}DN)ho7@3^9FzdAWQsxBdw3$JyT4#jX3UU}9t{2OT9H&CbBUbOR*BoWjk(AeEWIz;qLo1{tK; zLF+=mOwc$ZX5AnLY4AoS&%(( z#U)r3H0{f%32NCgfQJ1U=d|)NFsKzIGcam`-2pmrNFC%X2$wNf0W@3+vdNQ|fkBZm z3UaJ8gMtbJ0|UtX*y)UKScDl%ri;E|QK<**1c#if#yBT~kAXo0Gpn zNL|SEPj6UM>p{nVFoFt21_sbV7REV~_!$`Vz@7*Idx9}Y-x(AQL5v_7#vsiK2F76U zj0=s}7!*KFE|7b<_@V9v&7LvHfi{GLgcU&J!61efOdeE&G01_Ytw7PD04jn& z@?J1`Q0>N`09v{M5>A8(gNj221<*kupp;O`&%jWx$QZ>`#K0g2nu~tN!@!^fS{4S< z1de{tay149HWpAq6am*g{0t1DAOpl13_uf$*D-)>W1OQWz`$Sz zG82?EKtrjFwMrnS0O*hwP}(ekq-@a22=IY=44~;?#yKkm7#J)-Yc?2DSAquPf-JxT zn5iIf#$W|dhY#ex5&=+H*GI83gDQIl1<+6{NW23q9>rA5z@Pw1Zy>Sx5HVKf10XBq zK=ynCwP@K`Kv850b}#rCdQcV2IOl{A1A_%P9nApc1;!vta59<&Nkx{Ri*6x`m?qXc zSb?VO8JB_rH<<|}O(NPykH}fSesF2=ZbSD>LYRZ3YFW(H*>9U-u9m?k=a^AV_Zq{tY<=))kV4w~rXXJAkO1r$iT z4@4;|^9yi%fpP=rasmZV4+A8h1C!^d2U)8Cs?9;-4G?i~+=G_BgT$so#8{a@JJ}f& zK+9%8!s}qd;P{XOwZEjr7#Ng5DF9R$Lh}^^IM>_|g60}F26OPXaqy9!pm0xToWmmm zOD*@2Q_Dk0YLTsAV0;9M*-Nm*0UDnJCyuw)!VC;XFfKT8fK~`IFvx-08Y@5n0?IZZ z*G5lQ_{1X5SUuh06N{MEBw=t!vNE@T8V7Qq(ghSeasi+_yTlk6Kx3BRSld0l;S-BI z({17D3qP^Q)&GX+I{?zB1ad#JSFNXm3QN$XnUK@d80UD3Ffgd6*nrpUPGgh;bx|1@7(i=g80YL2VPH_p%V%Jm#%K&ms{+gn4C;v~ zMIZsNiNSi{nM9B@0|R4-26(Cm!mD9sU;vfaGr%SG3T6fd+W^pb%xo|pv_z7@8nkkS zaWg29fR`UJ&UpuNG04KrU{#Dkc3?f*Ks?Yiti3j9E#@Jx4p5JUan5>C1_t$_WCq4V zV7D^{X@Cz5IK&9b(V*Ss8goE3!y%9f3<4|+40@+Q!32?K4Ar{^Dx;vhFb7b12U;Kk zia5p-jNqCVRNz&KGBC)4bHxK@P~=5}3vJN)2sKcu18EVM9{q(yEyQv)Xlx)C)Z~Cv z-{2H@K@^$-)fp@gg51;iP?UiIqJaH?C1V#MNNj)mg{7RSo>g5E{Sp8@)U)>Wp@-{(PU4qfU@(B*cfgHuaeyJxA^zN;1;R#< z8v_^^j7=B}!FM2-=rO=A9Z=wAU@!$;LooU8JqZCbSq4M!RR|H>pgP4IbZNnK-5)F* z%9!W-gRTy+g1QJKD?YtpC$sEy(47JDwoq}9OT`%&>=0ZTZUzSX>E|1mWNaLeEMsM0 zaD*!2_7sL(9pI$L0Al3vG4nAnI3qZq>jkDWx-toG*Zj%C%v2Am3M^gJ@83 z%m}{N6jX&WfP_G28Zt73f)?R`Zz^E`w`@Stpd1Yvuwi5XRr(+i@X5cR_8J=lGibBM zd=MMlR%8eUQJ|_4CIw;}C4q;JgFyovphAq1AsB27^e`{b-LZ@epyOr0q97++-G28s zOD^N|Wk;DsrpNtdu@D5cB0)e7v&8?4XrLOboi9v8`*2 zkV^%uy&ORdukFT+tnN&VE2ke~W;J2lGW|OU*>LbC-z{tkT2bLFw9`nz}z{trnJ&}dAar!1!RtZLq>8Dv)8yR`0 z`?9e*@`8^1XXXT%!N|!meKs3wH&Y+;^mUy~(u~ulyRfs?F>aoIn4MKg{17wZ%5_EX z4FRAV2v%?Z!_Hd3I$g1vS$KM-Dx1Le#k{Ofn5NGXVEr&k3>? zO!pFEm0lMTXE$je^gHjHtEem2#pYF)WC_Vk{J!YQi_eGgFAjf`tiL%;E*Arvq z0S#<2fb@fs1gJ^_=>h2nHG@EGP$4cf`Q1|SL{Jg~iGV72m@KGPhp|CbIgAaezhP`p zf`Yjc#0HrIs#QUW473seWF}~VDaUkqaaQr|@5ETGn5J_}vhq$3l4LcU{#%k&aeA{P ztN(U>Db{Sp$t=qyrf-yHRh#Z1!)h@7jx=lV_6ix+1&q_zuV$2=UM0;WFdcOMIKK+` zSW%G0Ag?h^cl^pG%n52%f`p`|7s|1UbAqe}arLK91aU!G48(Ptz7fO)O}2r!!qYFx zv5NBRGJqydKmwov7N+SJMVW;;L9Gmskmqzkc~&=t<_F9w0~# zyfu!&2Xd16t_4g2)9z7@2<_#$kY{2kprN z34ziy=uGd&APy9Rx@NEg&Oz;HrFsTC2GEiYkUXgI1Ulp!{eW{&iy0&jPOJ=044_?i zAU-I%g&15IQbBY^N+fJ#rf(&-B8n?80CjAO(w=#2JOB_ibeqpWbQ6 z#4}x2i&cdel;IelCvvk-kJDlmHv|O?ban~0YaP^;V}y>-gWSdlI^Gw=069`_`aLN| zaRJa;CD0LaAR*AG{`8GA*c7HmhOkKpKy`weZQ$d*K~f@&5(p15YD~{t%p?w5-UnLT z0jkzPHh_AwFg9o?fl+um-%K`fNvQ8Zt#+6+sAJ10JpGh4vobGeaU=uupJeUaD zw+9C5|Ll5@^ zwen%opvE`o$V`w!K^*}Q8{~RWZxzG_75AV;7a%qdXo)%K97j_~)&%u*K;j@TfVznw zHmLUw>e7SQps)gs0D#z_XsZWX23q<6?bC}u&(8!kMnG(kWuTS~hz+s~>>y}60mKKL zRta((s6h*2gVcl40Ei8e2b(Vfx+{Qz0c@r@#GxQIH#?}!4?7gr9CF4csI-Tj{0r*% zfeZrq0L12orc$u)%^@qKL2Q_MkhBPN2`|VT&{?j@(Bt_);vk2D){%qQAcunc93VxY z;0Ni0u|ZR`AVnY_fQINnY)}dT)psB^D0o3^n1eukkT}SpAT~FM03EUjiW)J<5`B>SX}9Z;_o%wb?)0F_`MgFx{FV#5pqT|5m_1KP<0VuM2^n$l&2d`W0!zsM95yi>2dPx$}k~N;DL$*Id-vn zSQ!ASOkr$rasrQXGJx+D5wU~}?t}aTVuNA{w8mOQ5>oks#$!O@pojsrltFAz#DHQM zqz2Tk1)mge2}w<$VK0yx3D8g!IN?h&Fo0-KHxwiR3TO};cK$PHcN$0>SruYuHn(m99?O9kK*B+0-4YU6?0+aNWd;swO!W(RdIp~W3Y0yK*N z3P_k{(5eZLIHNH53%AT~@5Xfp~(4XANh z53(Pm2$cRnY;I^J0xlXX85lsrF(5WK$lDAI41FLUTSCfb5F2JFD7ZzSZ7UF)8(PtT zb2`YY&{9*x8WNSD5CXA5=ly_Jpo+*bFo22_P=^L20g6iy8+M8|*dUNAK@I?68;C*R zv|9i`TTsygQUgk$ zAT~G1#S9D#paBVxIH>9dv0)(!sz5;Epo7doY}gU-p#3i(anQ(9J%|I-0IE?zmVsOb zk_0IN)wm!wObuv=2qX^5=O8vr9MsVT=>_==oY!q3M+Sq~Fg4)1PXUr$LA_ZKTZVe@ zT0;;ArU;amK?Z@Eoz2iF0PR}_v0-XJav(LJ=m3pKf!LsE0c|)1ISv%RAT~@r_%v=? z$XYoN8z#OKRMmkrgSuRxjb0$lpaEVG8>R>(2T}v-ih(v)fz*J~42TU=1Cj%&0mU`w z01c2DP>Bj+!_f2~gq#vB44y3=E*41c`$>H6S+ZAbQZS zC&)5T|Lzqugh1^w5Sts?$O1J_ML-oA>;!H*NDcxeS`kGC2GC9wP@=5|DFS61kN}7c z$~K@e3J@EVM?pakVuR{VkdHuYP=yLE59}bdJ%|lUj3E6WHJ}^>V#7QG&i9ItQ>j7C zE|3}(Q2qyTV2Z%Cu^nWK5r_>F2W1_Q29S$EY?wGGCxFC3Sq{X8rEt*TDo7lZ{XlG3 z$bk|v$oC+RfXf5B>G#Z8#U3kLtX^`pQsvO!_1#QR{v72sZ z!75&F$G`x}V&DV{4SrCFh=8&dbiE?X0pMs+h7>}eQW2yE)cygnxuHgbN>LF|IlurZ zxI|PSmvw;6RDrA(2b-h90PZ~3gGx(~B2e6dh8{p{P)iQP2eCm}7_^!f#0Hg)V1ra4 zMKhQUs=q;_(4e&B2uUZPkP~r)6zd>=fY_ku1bI|Mje!AFvVzJa5l04h@Sqro1FI`Q zRWL{cD9wP_+#nag3Mw_oY3`ubDo70|ErHnF-b1U61j@y*_7W)L!q}k93S)yZC5#O! zreJK)ni3cr)a-$=LA4Bw4Jyu{?CHtOENRm%*D|S0f6L4wF+DS!NoBew3yZ|`SQ}QA z>8T*rOb}}!h;MZF3HLwAqk2I(8gU*#|X*>l~lqa)4f<(l&5#vvZ_p< z$jTBT1Fca&Lj$l=D!|8?gT$vZvau*kpSYe$Wx6XHi-aVoTLs!i20E=9$_Af6EALo;D$`BbK^_CK3fWmCWI@Ro zw0RC>Hk7>+&Yr%Eokd<2)MWte1Of>|*%#sL>5tf1l59b(1K2J^PzHvvLG>Jr4QkcF z*q~kdFm}@PMh+I``bJQv6jZ#x`o2&$XkZDZ6dY|(aZrN*CcYU-FX%i5m^i3#Nr2@NV?kEGcZi49tG0Mh_ksS0C*kBf%t^#V<|K-pnPZ18c>Q1Lt@ zaqvMwAaPLj2tF_3t?A82A9Dh@tt1?l+{9}*k1 zB^=}%P*kcRi5nrY?U2}BaCSWdLl~UHz>tK*&O>5XA+g(#*prah^N`r9kl5Rh*oTnV z=RoXwsBdn8I8gR8B=#pH_CF*x7w8mGsCqFZwh|Is4~cDs#CAhs*9ReS;*i)`NbE8s zb`ui24~Y#rLlqVU%aFu3A+f>dra~Qk3L*}fCb$OSfTEA#5fU5J+=Uq`4LZ#es#y(* z?TW*0f|EuEeElo zj@XLCK7z!)jKsbHVnfZj12q%WIsX6>hnn*f#1?~A=6{hC@q*5bgenpSv7rX3AhAtB zY^cwyL2Rg+P$YH|hz(Vf31UM%QvhN^yCfxi^$ZNKTUzQt5>Q3GNbDsbHq=3zkl5Qn zY^eI8{3??8J&-sw6rY0F5Hsr;-h(($%f2JA|AN?{9u%l?C&0iU z3}p)lFfcGe*`Pb}K;odpC5+|^i5&)FLwyhfVnfxWBC*RrY^a(V z5F4td7sQ5&PX@7};&Z@kQ1~-2Ff0Xgz|}s(HV_-CVGoE6)o>JveGSBhs<{JVL)AP* zVt)g%p=$ns*ibdRB8b+qNIi%Hnj!$r8i+732t(NhNaB`AY%dTS8U>*sHfYobv@`&u z7s}29i9Kqk^EtrBDvY|7$^PsD>RNHq@YfAU0I|D2NRmEI0|W z7|MPK5{IgJkHr24Vnas`eu30O*+Qa7&2CvyL?TiGv7rX(g4j?;7=hSOaR(%J5Qq&m zG)$C%K^Qvp6^A6A4`M^3qZ-5ptFLEZXn}JW7$$<)P(>R+Y^Y^>Ky1(`9|Hr!MGzY* zeiy_B&53}H0t2z3;-8S%f05XXVu-kB1F=J)8n{3lC|eMTEsDgJL1HT)vDJ~-+FRo_o(Pa{LH5=cASnVZUV%w~udRb>Xhu@gj>HBnxP_^ogd`5yWdRch zEqH;k*C43@9iG7mYYuKll0ZHv8nizHruiI_nyX0cn@H>jNNn)cVNef%HfzAl`HrOK zA9!pBstA0i7?cg#WdUm_flrWzwx;Ak!zWNSXp0m~4QL+*jBSRb#ukYU+QkS{16t4y zKG_FU$c2CuL0U%)poRFbdOjT_4y^;g14Gc%UyLMPj>N7*VmBeNJ3(xy-aZf;Y9?qL zi4$ho%;^*NGKtrN)|A79z*mkz)$T{q2Oe93ii5|Nprt2xJu#Gh7o;A_29G&G+2BJ; zpzL=@YCy}!85O|?1~M>!Pnd=(0pq~2imelzE{IYS3h(u>ACMN0`KzgcYV= zie?Q4p8x>5HWM_W53T3G>lmR<0^PSNtTx?Fjy-t#*%(&1)i$6GhRF0fJr=R)0kN#S z_0S9rauPg)g494=1Dd!2XI2IV@ET}XXCwxs2HG(Jt=43OIu+!47#lPR3(HU76(`Vq z1DaojwZ*32iDh-1&UutcxE?$y0(CxkQUuDj0>uDm5di2^J`fu^Gyy*695fFGY7TdQmV5Kp5fD#%eKR{!N&~N~cA42`> z0vacT`ZpKEhWaZ9Gz19Ex(`8YXrt*Lhz(80plzA3>q!@YM(&`V^Z@U)hx*bFwEG=; zoB5c*0QCSsIT3VvGB_`Sj`;y`K!$<_r$KDc+%RZ!1BeX@VbDM|hz&9bbgnmu4GJXC zY4IR7C^3RghzGGjO%u@7fFL$#VZv>Y<2WI=lfMJ8K?Z`ZiU5tYgN{!ISq#d3AU0@L zlL2~sGAOj!plnd1iwnvI%>{!7xj`osgF;0SBn~|R8GN!eH15GCTZ8rpf|h53)bKMf zfTX}DTl0e#In^_OkGAHAtbzd_ZOzXBK79dnBoOFyW6(ln@X6Nv3=E*v4k=KBKr0-; zCtLGFRyKf7w&rJG04>`ApKQ$!S+-LJRS(Lipeq1{potN51)vb9%Lnp3=ng=T1ju#s zK^j0?wHO!}mO|N}B|592Y|x6u^-wlw3il9*4N52s3=E+2357%;XPTaaii64{&{>5b zanQ=ZTTpS(s+tG&P!1@eK7q19rwoHnvxYVez^7S5&*)_a9hoc!IfDg!nza~YwiWT^im{HfRY}Ae0SS=M@fRgBGAgL)oArC=bMjX73Ux8x-nQtPJ%GpfhGc zQPKdF0IgVPgR((cya&n#MZqK}8??@A29yn2Wi=1V21UmbC>yi@VI7nWS~as1$_6>~ z2$Y=x%75pe98iL~31x%Ie$e?bAjg4L$$$?30kJ`=WZpp4fD+mVC>yl2jtz9IGAK_n zFfi~#*&tsEL)oB06MP^wv_R7ViPy_P5)0^zeIYr>5-ZTYZV(&fV;hhnImr4Ae-Im# zCm9$RLZNJs1<_D8XrVwNlnqLcsZcg3OM?!76aob&0|P@HNL&G8Z$0QFNRR}mU;&>_ ztpM53209fIBo1=yG^hqpDLW6!2K956LD`_L${HvewBiZ0i65lbhJk@$2UHxia$z5o z4O-NE1j4Ro04)eP1>rD&#@#PK*`V>FYfv_*P6OSc2r?A3n&|~p928BTp=?mpfUZph zsR6AF03A~VVuKbfv4IX+R$yQNtp?zMvO(+2gg^@sL5e`r{<2UB(CQ}8eTpD)(7ZDE zWNQTm2GD{eGpHKSqBHPm)(Q*^phZZagAzdMK?~6QplU!<{UJ~`Xzn=*$_A||N`SJT zfm-7!P!4EeQ8|bW3TFlehFT~a6vxd_HYgEwLfN3gq#w!#Ej*bDWrMcMfF{X=pzD4X zL&ZUBjaEb1pfySxK^H%Q6oDq`w?idB*=8@44O)-{y08(X2GsO82^9x5H_k)ZxeN>p zSD|ds`ktFmHfRR_4Tue`jz2-!AkTb*vbjM+4xFHqmO;fIDBD2UAVr`lJRudxZfbd` zILMda^Q~1F7(j{H1S$@)1AL}6bj=RvvPY0!P)!KBXad9rt(^6Rss}C02?n$4A!qDI zf;o`oNbyiMXoo)N;zy8XP-&PA6$h1ug-|xAp;iiIgO)LXZn6*p)y1GSqablrNH&`S zWrNxZGoWlxc3m9+;y_y?8=-8F??E?33aLR>LGFW!gR0;oP&R0d#VIHol(o)5*&fr6 zIB}_Otr^*;Khj{=XJntgEt)NU zI%hJI4KK8r2)=@eclx<(R`KaK=d-I!=iJSv0&A^<_GL4QOrQ3ZRhbuB4}uQJWE7j8 zmBVVS3KiM`>d-;iN08VT!0hR#a#)q&`yW7!RcIx|gT$5qv!@GPVsf7znaj!(04>5R zK;lp~Xzwtr4Guny8B{8Q`T-y{P&T+f1udPofW)Ef1Jf7oXA+kKpUezOvkVLj;FFo5 zZ192th3T&@G44WGEZF9stS)9a0Hv!GjM-hKhp^NLHM_Ess^7QF;2aJXZI5 zXnq2pS`1}_Pc4SB!KW5O*`U)uV0|;t=^rpQc&{;34fxbzC>y+h0LliP^apEKgAXl+ zCjIGat}tn;LX$Q4=wc`vd~`9C4LT=*Q5|-e@T7i`=?;6?Sf(E+U^U^K06oq$W%}O& zR(H-h(4$aOru!DMx^r%Uo=2K8eJ+R#I{OsVs7{&wwvg3b_XA8Z0|NtSO)qGnA1JRK z0wqf5&JIwk6;v50fDS*D1(o0+RnQE;06MJ{l;c6=9MAOLAFR@hYo<5qvx`qZ@Pk!A zHy{kM8W1E6YUG2of-C^95kj)y0s{ks2gm|j&?YdDDwqW`!WbApOHM&1fGS>)9LNL_ z&`1%I2@;?aa6l$#g6>}dse+kM5Dr;L2r>aw4}j!ACKybA`GZy6RvV-d)anL#6x1gP zhnxWkQVwbwz?6fIN&@W<1GP~>N#5 zWMU7<$+p>OZuk-oITjJ*22gatOz1}Q^aarIP16siGm3zQA3>^MZUCK=3feXYG67V{ zf#g7L0FUe;xj|tv<8E==)oAv2M1fYGGcbU3gYq>@H@Fx=(yakHyB6dF(XVJO(_vy@ z0G~oUeSsmnfbN1Q2Jn_g4=^>@;?nR zAtki4cp<`~AnTAL2V{;M$YHXetK>ko!2;$>6r`pAxkP39MjvKrR?tZmQXs|CIsUK; z=t@K*5&$Uwfpmj{E*k10SONgu52p{(W(!&{22usH!y_7Um?X#!P`wJ01DQ~SW&-G3 z2RE<@xuAeVN`$bJXh9}``lT=vKz1Vg^A8gP1NeYhQSj|^NFfOtnp*)jdoG&UBG7|n zL1u&cPcX9&pt%loJe4QNgw)+=CNw|~uLYR^S_BO<;VRSwP`3{hXDloX44`od5F3O+ z>Oii42~`IRNd+zj26K>2wolM(+7QFQ0IEenHi1k9nE(n&@Q5UmZ$Y;TmxE3Cfo6hF zEaV7VkO`nA!!Q%T!<7sS44?!Da@z$i28J523H)fM0*AygFo4dK0hs`5vcpVJ1l3$f zZt&q|V3-az0sS=P6Y&fTpo|AH0W=^0Gr=CsgeTk#43HuPG^7Ml1xryCiHHmd+Cu}9 z1BCpsd@z;=;Yl*4Pje9G!rs1 z7#Kh^G9VK`W2-O|5?LTi>fz-sXyM1?z$qf&@nldOK(Plu1H+BU3;TuZi_whs$YNjs zog@u18nhV^W^@;5OcSabM1ju2G6GeQAP%&}0b+vArv~YPMf!<61_lvfNNoh#_z02% zMfx;|d7yR$NE-t~kU9gyU(g|%qTs`$AcA1hUz>r!5ORnysA&i?0cQH0Mg|5@4<6)N zP#*;(2Qqyp#B{KB5YeE|z_0;yW~S^GH2>ywFff2>Mvw_%(-YGeg`ur>1_lEIQ22w+ zw#j@vXfm@{0@hs(?nQKv+Ot zrJ0L?0fdF7FPO!uq%=+CFh2tW2n)NbfUZpjVc~EU&>B7v7LJ-;n8czmeg9Q9#qFxI zSy!^MgVy6RF&v+M@E=RncK?N}+RW@lCCPdj42;_=masZY>6=+%I}g>&%oNKhsb*$| z+h6Tt!53=H6f(9jWVGf)(O#%viF7&<|0&_E&s0|U5U0-b-{ z2oeXic|k`;g60iCg9xA_gF$R)M!gRj6=#FQ<5LK`9+Y$#UPCwxApIYqY|sED=w~ z%fZONkPa0G-SLx9x@}63g$2{fZB=KP__jF14AK{4f1_Clnok5t%b5d1yv)I4H`WK_1Zxb z9H2A~9yu3;3{0&Ase$H{Js>tHr86)v90F|t0L@r{G@O7+fLsk8Ef-+`A4qcrDh>+X zTTnKrX9pfR7lBMhfJe?jC!2w;*@CJ84c~u)vOxtlXvz;{7bqQo?|~FyV5kQr1n@9A zG{1_1#(AOFAA;K7pj!?>eP>0eIH(t_4rPOeWI!j?gVca}JH}9PP`||-$_Dj7yg+Pd z82~!_3^XGG@?;qJa!E1BY*h?Y5h!Gmplpzy94H&q^(%w2LAxqzplncsv!1>#{cl^KY|!D=;0q$f z7#O-hqi#@f&{o?c+n;`7jb>p~nC|$U)t~Xr^obzKXZk}Bb!WQa4_1H1km-#eDq;FX z5H)AI;!jq8#xv6kf3m)3?3teUi`AboVfsc8r7)fGH>*Em%Je`Gl{0gra>0LA0Y-!A8~?MaGxATr38D<9GP0?&W}87P>8TEE0*s5N2C}I$7EG;VQ)hfU zbs?KN`$C3eRK}&*45S9c`_e=^jJj=|%8qCPRz|6r8I*Xl|g>^QF z$HES(%$Ql&&w&l*uw(-rvkaP$WSb1Cl~#j}T^4m@2xMSj*~Y@az^Vgo_b`K$>4KUE zETEx%Hi-?OZLN$U(tkl$34-oeX5f$lby+w-(;7@1pzahi154iY$sBAp z^`Mz11`g2muZ$d^Q<0fCKsPHhbAa}fv2cJ&c2))!P%Xou23q~a&B7`CnvsEl2h@7u z6xj`OB9|Bg4`@3Qrzn`qD9XSCy7iq?48j#*;91GWz`!XE;R-YG>}Lm^4h-h12rx77 zurV<(a7u#tj7$tXprtOHQV=d90}l_&^de3+{d&;!6{j4?at488ARY2xB?6#rRGbPR zHiv){$Yezjn@50&g@J)n3B(o<0A*%QWe{6L0Cc1~rwWKIApmM}a;k#ZG6D}kW~zbM z3JlyVoSJIPFmGys1nXJ&gcx{0MH8nsh|j_($iM@-Fr8Be%w^_d-~r9haOy(1+|W?a z19KUzu{stVC0!D%grXss50G}n@xvNVtNKQn*l^=5LhX@Bm+;!^cCD}2K8VA zBH^NXpa6>ka~UNVctFe4IHMt4aR#1OAlVoQ7Z%B}5H2i|;~-pEB*#Ozut-h-bK!BE zxEoacvw$OcdIArdogmmbnP63HQVcvF*{84PVT%%I2E|1+SeQ|Ufro9nBrjVuM6?x2 zv;{8Ok0kmYE;VVSKoGQxmU9bOREC9t=ON4V*?esJj6Bm%^Re02J2EpcaH@lL zLNN${F2v?E2c-cI0nlJAryXe3m5;zdP`ucKOb8GFP0DdPfY>1dUl;?f)jm=pIVz&sC zgMzRK#O@FPH#v(z>>h!;AWxQn*b@Z2K(0Uin`pK*e3^N2k6((orKUM~Y zIRbhhMUz3>@)ihy?#khu3)+geM4%t!n|UD3D+KI7p)w!DUL$Y_B)$N|-XH*~%QzQ; z*jog)g48Smv3Cf}2RV8%h`mSP5{SKIHv@wp!vTSNAkI>d#1VmC?9*omuvvwIMs_$? zgT(F#^n;FrUjt%45CGky!?_m3ej)%GZQ@)9V!sf`2KjtFi2X(Ybet~d1`zv$0BByE zb0diTMWAT9x*(edWA5|-K{nAGov)k>3>=_k2@D*dmM$X)Xhka%2NN@>yawIq&cYxH zx(1e+kCB<5i-AE5bOjDGA0uc!m_Z!0s)y+Y$Y5qIE(Qh(@bTrK(w{*R)c$4!&4+`U zl?;q?q*A6|6l7D^nhWY|>w>g12Fpwb4G-#pIU%44c?L#sDFLc9WZz6z5@M@l44ghk zh)qHO)WTx)1vSz^tpg>2=|_avdKo*W2MM#O3)p}P`D9S3Kbet%K_+E;r!X4_qax^v z5k}AiHG?5&%zBPK9|MEhbC8u=Kup=j?VCi{#2FbkPd_EfX28fj{kJHa9OK^UQetdM z;-Ka|BMaj!P*V?7oq$Fy=ICWi4;Eunua^Tw*1=tz3=9TpAm$+u(-73E2Vw3s!xzj9 z3?R(mW4MQrfdPa$5)46&AQ0wpH@eHnzyQLApvDad^NJaYu`w`!Fkhsh0V4wg2=m7q zf)?L`ut1$5Xv_zM&A40)L92E^m@nQCv|bp51wR>kvNJG%uuu<+F=(J3gasKH4MBZ` zGu!pW*+SXaK{pC9F=T`Kvadj=Z}LuFAax(a@S5(oki`SU;+@W-z&4GMar0^Mo03?P$^a6yFz{uVzQK@9T%@8TJ~OYRI6glu4J>15X5c$r zP?fD>`eao$4ff=M;*$8(yy*v3*&a*eRnmXGWww%P|l8nsB6S*X(A5mu$p8m*;O-Ld$4`fy%Lt;*1QEq%remO&G zUSd*C>U3!hHb;S?lH~Z})ROq*g3|c3qSV6a(Hd;g)42qh_@>LVGmB2YtHD+Uwj?6N z(Py$Cm+1ClO*SsZ>6^OQM5fQuVw=GMG9f=Nr*gZ!Hd`(`;Qpz9eyYuy+@+8G!avOyUZRC|HWHUteDfTj;Y7ej;CAUA_@2WZ#; zG?d1`z@Q3ZgWL)_j{(F6b>$cs7(nZCLA^(i%RmFkLa?*lK-m(K>ZomML?iV73?A)(7}{f zK;=G2Gw5`&TTl(4u?WyiG)NrO$^|bCWQQEP_64d2)F=4?Wfy_AGl4qM(9i;pV{kya zk>GI*4#>(ORj3+}BS1sELL3YXrl55$hENI6DlKy;8`QbBg|b1*P28bu&~g*-YCsMK z22i04+9MA#2y_@sJX8&6^-nUC4eBF-SN%bw4>VK@8d?DL=0HQV^&k#tgax9JI&+)HVmPK`TH&lkOlk$f4jBfSe2rppG_p z1t2HH(cl$;oZ$11>KVXG068JE4d5k!oRFm!pkY#wK}`${44{jbKy1)yCZN6vhz(kM z@d@f6(2*CQD~&Hv_nv;P6)JfoivO#C93V_-5klO-9z#ImKZJ_h` zKx}9V*N3t}!DS9*gF@04$_6EVXDA!g_w|IbL4zs&P&TLr427~m!xf;aR)`C7>`Wqf zIDw0S0hG|vp^89*#ko*6=nSA@C>t~YRtaT;u2qBS1+|V^q2izr0^JG%vH&!ZKMg7l zTEaXB%HGGoz_19)uD=M{+63i*rryCz1GyL&K&Lltfr`IpU|;}UrT{YZE2u*a75~n_ zz;F!82DL8FK-qGP3=Ef{Y&Av(2Jq@ZE=ZAgA1ZFn$iVOvyv`966pRcEFQF37j0_Cm z!46Q^f(iss?;U!fgfNH=Eo49!_6hMovY9MY927MMAU3GL03C-4WrLy*bX6Yc(h!i5 z-XL*4klyV|QEaQ28TU*-8_VX;$TD3vj?JIZXL@cNn?KVX^XdEI*!-pkEM;ezE)dV= z!%k54A&7{nG#ee~P zJUwWLMj1Tx{=|fV;p+54kcK?F;K>3r#IQjFlMwit7^2d1;FW0R}f2ykl5HvsmQr`yJ6Al#zt>oMXuF2RK80IlBFn|}ovoSD$Mp8~g6)gs> zM})H1FfcH{hW0_x^$IEuItC6lntzUgfdO294`tU&F5oas00;#%z1o;?r z!O&r-8c@`ng0ewZMS-hCJ_ZI*)I0`>gHjym6ay$56x1J~Y)~l&n%4sjn1c$*-(c~2 zP$!asfe%!SLZ^GcwHkClTM8-;(x3okgOq_s=LI2S(k4)GP&C;=*`Psn7bqLlK=FdI zL9HavEFEa@98`IQfomf{$Qf`kP(`5Ox+EwY6a^VjHYnJ^i{AyojQ|Gl;&(v?2GFzs z%p6c^2hCl9EC97)CP4Lq(i!OLG>|xGsX2IEyC4HYJvi8*ia@~&uDt{q7*@h+FF^)| zb+Fn?kbwcz2mmj57i0jRc77eC7g`>G?mZI{0#y(U43DAWpcnyHQbLgB=Ose{Yi?h=gDseuv0*yn9yWi*j_H9Q>dy3qAnL{Rk09#6 zbjQ7H@0tD>PdD1f=ErC=y>TD7YPkraW=vPy&*sm#WqRR$w&RRF(=89M`7<7w-g$tn zobkYP#)EABjB}<3f+&UQ3lFksGwMMqp$7-q1Q=&b|9Fs1owZ+{fgxr(V>pZObb~`| z0*tSxJ04$XrcMhe$7r*gb*Pk0PA&rj1JgnQ1_t)r zdJyv`h*|uBfq{XSg}q@lBLf3pZfOMrdn1U+z`zfZVUiVOU|?_Cd_A;Kp68-#2s;A< X2(w?998#*p$lhFDy1l%V@u?sHe1alm delta 140 zcmcc9$9AWWZGtqrp^>SXg@xHhrCuf|+jR3brcMhe$858kb*Pk0RxSer1JgnQ1_t)* zdJyv`h*|i7fq{XSg}rVyBLf3pZfOMrdp(HBz`zfZVUiVOU|?_Ad_A;Kp69%42s;A< X2(zD?98#*p$l6?9y1l%V@u?sHmX9Ko diff --git a/tools/sdk/lib/libexpat.a b/tools/sdk/lib/libexpat.a index 6121c722e4b7fb7d2913a5e8d90dd1ce3213838a..171c1636fc62ae9c78677594a2282a15f86bdd2c 100644 GIT binary patch delta 229 zcmex!#rw|{?+McEMg~TPrbZSUl{~rFAnfUX`GmxqJGk0AxER|zxR}~IxR~2JxLDdd zxLCJ$aItw$gK9FG{*O;cy#3<>w(TDmuos<&3R{4L#o8MRINBQuINKWvxY`>ExZ4{F zc-k8Zc-tEa_}Uu^_}d!_1hzL62$s)-YBSpYk54F+1 cCOJceOhBr{x7S7s>FFQ~iETg8F0>^H0J;K6TatZEq;xYi}svZ*M3N*xpbeSUwM;3vAT%0%4(v+n4eStz(8d#T?|6<=YuW k5JDCpA@S{J#f2t0LsdbAYNLhpbf7{IKWsnIF0>^H0JD@#X#fBK diff --git a/tools/sdk/lib/libfatfs.a b/tools/sdk/lib/libfatfs.a index f72ddda6a9181bcf7d8cbf13973cd0705fa74530..9643f9008ae2e617b0d0e0a97bb719f26d181b09 100644 GIT binary patch delta 569 zcmZ3|EV`swbb>Uyk%5t+sgcP>C0k}F+i?248_eRHYnjh8^5iHoFfg!iF)%Q&7H^JV z4Th-)s}b9LLSd(%uqA_DQGQBdNupkIS&5;Fv5|$v<|#(InYb+(-~yBN86`FsnQjzD zwnJ>QgXau=CKKbyA1Xwcj7=tgs1Ri|192n_&EbZ|$ETI%CCA6Bm{^({Z8oZ`U^6yh zfD4)$7@8yVjLaB{<1=#$a*7e6AdQpn)+;fY7;k25xMU7>g9*r=V$C16Z~w5J@uQ;% z!ph|05@RD3QzH|L?O%T~+VgW+FeDe3fCS9j?KqjX+i@~So`;%Zyd4x;HPau4u!u@n znqoTJ)WX1M`hpM^5mR#`EV5=sCJcH>#l?C_rD;Ygre>zba4v{vv|T%tWil6!sSyKQ z!Sr*MEaJR~ATTpBnf@-G#hTG{x>f>173%9>kPOb@hW5#GKmfkkyX%#YxZ+Wz7@%N|bvzZ|fz delta 557 zcmZ3|EV`swbb>Uyp^>SXg@yS>C0k}F+jRQ88_eRHYnjh8@?QgXau=CS%LVA1Xwcj14A#s1Tk0FoZ=!(!kIdZfJabT4`Q#e7uT@rJ2QMqsj_4 zV*>`bpeaZx63@tpp*TJ>w;-n&p$4RJ^4)qRCS%LZj18B}p>8k-`BSX5t6-+;8 z$s*2+@Ti%Q!Sr|WEY^&M)3p*;E>2C& fMw7KLnI34%BD{TB0*mT&n7_cGv;D<)mOY*T=PaxY diff --git a/tools/sdk/lib/libfreertos.a b/tools/sdk/lib/libfreertos.a index d9a62b717b228b734f049d61afcaef71fe1e09d0..f8773da71c7637a70f31fd8b4820934a49ac4179 100644 GIT binary patch delta 131880 zcmcaLMe)`$#R<~vMg~TPrbea{l@jV-zhYoO!;Aq&3>Y{sjDe9{d`gXh5eKfvB|)k< zGjARP8Mq#=DD41OSjdU&%pbCv)!c^gh&z{(=N`Lb{qJ6yyehf#cUwX_eb zc#a|i0|Uz;W(Ee9Tn!L&A|nF>OY!D=3dKHf$f#CrM1B4X2#uB!RVZm$W1#4M0pDoa3l1^BLsz4M;0dH|GBa;K;^bKY#V$=Hy z7$qjJDluTR<6PFt9Ly01KlxD+2=$h$#UgpqPn;-H(}p zfr*KIH8TSPGYe~GUI_yeBbz8lkdcECL@}}M1^G-JB+SBf0c6^)dJu<$tC*32fo*pY0|NsOS0PBz9uQlA zft%$r$SKhvq5U8xrx7Cq0}tELIJnU#kc>VFG7W0{TGg zu{bd@FtE3PZ0C$(VqlPAEc^sA_!Bb&17qWN8soFUU6x3=DE0yXMSbVqg&5#md0ISi}TkgCvDM zGs5|d!9ryq|1%ab%>_9$MA#1`SpqgD7^GSR2NI5Kp>uD->{z#u-0p`L*O6tki%pumV?Dq)adjAklkkYJ2qDrI1hyvo495CIOT zD5fG7kSNGwa(@{a7(Rm1Daeo?6d5HLV<7?zit-E$4Eeka4C3ZcoqKWWD4P-w<0w@;eJY|C=^L5~4 z&JD`Fe?h5m9XP>gGr^MW21ZbB^I>9OPywgfjbNh~L%_-ID;q4?iGykpQ0&*S;S9&E z^~eDUDmK8eZw8Hl?YMPrL)K^mjRA2FXuw~AXauL>7-+zQ0tFPc;6MR66BH=*3?d97 zAg@c=g1mYI>=jUc5da6uWOi7f+yDnk4if`|>QRu&TZ}V6K?=^tx4{9@3lESxU{e@_ zj~m_XJuDDp8dFr4OPU|^66pWIL* zQm?=XbIJ>_Qx1aSM;}xQya2}!sE!ma07dO9Mo>+{#LU1T465)LA$$d91_qTjkgr}d zg3MwJ5q1Hoe#5BE$-rO?QVovnw_wMIg7_Cfg%*Tg0xGD4!G#h;U@1re*!S})EK3GJQ^rq- z2~1@S42q!Y>>4Pq?Sv)~F;1|@nJ7#KiVlYyH>jgx_)UIbJXbF+XdQ*a6b`3sbS z7=#!^3^^GXM7MxKa}liW-~ff)oEmNh1~qWqu?SRkaIr8jsDa~b5vbLnmPIKzSX42M8ma0Dy`Wyd!lF1S)y2C5@?SQ!}9 z!F9rN5EsM(XU`sPSZrv33h|?`Lj17|7XyPlj0-NqjafknQCu357wZ|kxxj&gSsXHP ztVAlpL9GRFCN_m=WN5~%Zxxb0YiJ%;bcB_|kx&DUfDEW-jKXH~S|k(VVJ4))BE0|_ z>90U0Fh+smRlJ6QfdQ1QS-8R8VJd=Fc?{w!pp~5lOol~*F`BJ}!NpBQQKBAFBZ|Y4 ziVai|C>_C)isD5E1_p2`ew_hYia&w6ARD1v@*gy{feIv0bqY>Spojq{Cw>MIP^!^< z2ueVn;KBe@Gu1QBspnx}5CSJAPbN@mVhmCN$G1AsoVm!0eqN1>X?gI=7S@A z77r}K6**zSA_8^Pf2gC185qP3p@FT>0}d99u&$3`<_c#*3T;pg4UT6A1_lODF7gHI zjAnLlRbdeKh59iOEEvTEvLcj$f#DG^14AiPtcZa@F&dG}T6q{4MBv#A%WsFhEQLH5-M%rscp)vj&x}IS|w8A;vw2*1QPgw9c|JFn}=AV(keG z3=AO5*3YQ*kC}l1gqe?O3$QUTfH229cCCrb3=AO5c~6Ux!kpvF)%QIFo!RP z_6Jr51`y`xVbMxpWMBYc=8OJX=b0E7K$!W0_8evg1`y^r#G=IoYVxjls$82C&WnE7BF zer`qv1_3?B>57a@;--SE5GhtqVJ2|~1|cM_1OtOGR3lVYM2!Jtoap5BKcsoZpmN-v z!b}oVS2C$jPqbi`u9t=ivw8~4a5FH-fViH*CX!4N3=Fc|jG^L;!VC;@vW$kpf{a3J z5!{iiAOU%9Mi7^QLBWK<5bP4g&L&0%K}JJi1_mWYMo(doDrH3mPhov-1_l+7saD+9 zAa_YHFsLH9W(*8!P(OeiCeFa14wZy*HIS_41{tcU$7nA(`J%e0kd_{Uy`+s~9v>vI z7#OrC-*0KxwFG5Vh9D3H>M}4hlxNHbm7OrG36>8AQ4WmL4Xl_&w3R?9m>~p2fwV9& zOaxU>Fbxc#x`vS<6ht{pzSQb04^qU)0O|yR)qsj-kadhuTPK^eX)`)ZPG}2fea*nY z@O|>0HXZKo3=9l^!1hFKe$d9v#KQ=7M-YhOnEbs%9yA&Nat+T%u&NLc#WC5U(~9xs zXhYV#1uY!uf(_oXLK*~WFqy<#mF)mNrNihj*|bZZkz;abmp>9)nLUx6fq{wP^>hajrpwa}cCu7Y&u?b*ntosg zJL~khyI4G@?`&oantZoMeERJf>|E11cC+wL{@-IW*|S$!CAGL9KDj8rxHvh#C^bGa zuS72cR5wn%WM<-I1Cz`Qj4Vvd&+9lr3`XYJjGSzf zFZM0wVP^)x^okwpo1QI!390{Gt-~)Dq|XqEt^8h6?AL)WjnH zJlBfMlIgOu8Re$`>R{yFd}q>Hrp;5Po@238W?*0dr3O$(08|!(*m{f%3>;8#P}80b z%C-S@=%H+f>5k@1>YESEieXfRnE|SXKwVsr8Q&NXW`JUXZMt>>v;OoRD<+A}U303L z8I7hls^ch(VFzBa{!57Y3L53=E(IDa4@6pbX`MDn=m&RV4;fr~piZJ(LeB+JzX@8KNdH zU+Us%$`Bv#7V765;_2@fAFpC;WNC~hVr+;mVq|WJuExk{vdOaN)8%F}%1%~W{%f<+ z3JF$5v(46PcQe-CXJB9uQDI;JEt?Ca7o-5ny0oVPs%91PUSn1_n?n z1(gLL^**4^4g&)N%$p!NkT@t9L2Q^eZ$k8%F@TctJrGBOfdLezAU4dKFG1o03=E*8 z{{zIs6#;mi-K;lrn^FeH=-W5pf9U!(ODEt{1 z81{iUPz}eC*f&6IsOE=AY;eB=YVmiFI8-kKs8tSSb0V>&Ky0Wv%1CTuRuD&W@`-(B z^~E42RBsIuyA_Guhs0il#6E;;RUhfpgB

q2h)}Y#R_8s>Tt-hN=k$v7u&$L(K;@1e1}()7cpq z>OmHRBnm(hP=iWAY^df+B+X4Aaj2Ru5F4sy3WyE0cs_^?8aHELU|0;&3uUhZi9^-w z1hFCJ)HCb@ai9_>L2QTw!#NNeDt;5hhKk<5L*ru{tOHZG9V6ALLJ108ma?gL&eQOY^b;mhz%8Y2eF~zJ|H$!JRHP^ipPN1 zQ1LVnTO5++vg<({Xb{za*wBR5io~7@Vna2|2C<>)mmsmXg4j^K`;ge@Ky0YqDhZ-si;y@MYf!NTvG)H2)f!I*Xd_Zid`cNcx8i)FeD+d%aGU$Ky0W(mxI`#@k0g%hSfX_48l{KLnCK9^zF>;PxsJrXjl_P8#C{HDPd5l=Putvg;wn=;wCVN-G^_+=gJumG zp^XuKP=5r<7DHl7A+bTTiZJ#1NaAKlY%3%-Xx0&?zCHj+A{>bwjl>4`#-MEl@a!0r zT@F$MWrL>6!7U;N1_sb99*jK^NeyVe1|~iSA`Y6RWMEha;eg|B6A~LVKL@M8j)KIY zmD!oe|L=&~foAJqvQLp@!E>`vmEisylnt8AgQ;g@p8V#Fl`Uw>4kly{>W@H`Iv}xK zkl3IpJ(&8)$;oGx>r0SiE0EZrxjvZ6W+d@0Bz7MX8#EUPQ@;{P95g2g6F-b3ehR{d zqa0L33eYkKn7AYhsQiUW zfM()g5_(7)Kz%rvxFwP}XsQk-?vErMhQy9SVuR-LVCoBC;-J-FbL zG{=FhfkyN

&62&2vyc1zJy8ff~}#sv{7@hL--!%-~rFNb2E)a6l7a;JFkb(5e?u zUj`};su!i9Y|!E$(2xg64ag34s5q#O)P=G^tqaib2S^QQ!t20C^$|Dgp8YX#4{t4sv)BR2*awXki;j95gOl2@;2fPz#g|3dn9K8)V-!C>yjQ zW-gQs(z^o6wgvfrJ(Oe5z`(Ez$_A}xIRa&a1^`b(*~ttH3>Tqn(6W&0P&R1M3TVhf zh?9WH}qi##TY&D9IB0A&5y}RQr=~;M zpz+jPC>u2D3|g-U(hFLZQwbKYXJ8OwWMBXd$bcji7#SEqnHI!WVPs(F1}kD<0F9}F zCfq>cpt0GhP;t4I1wUEj9tE0kzf7K*d!U7#J>rE#_um z01YIA25mr!K*O&0po+X07#N;F*`N{97f?26pceZJ=zBW_KtX!MHC@32=f}H?m zgT|B7pls0CZw{0l!~j`1CB(7{W%n~MFr0z1L8}BotFJ)nLAmAzRD2Nw1H(NidnqW&pzMtd3=FTJY|u#h zJ1848lFrD+z#vo)Ds4auRzVyANWu|@vO#5w9Fz@OkD&@>gC>X!plr~@gcXzx3U)^* z+ns@d!5zv5t*G#YvO$X~f}w0sXw^qTIiRWccqkjRxFQwGZe?I#$cC~fGB7X{LfO+8 z7#PZ-Y|t92S|}T|{Gu7k2Cd@lgt9?pNk5bg3W=!@c0B_qDCR;q;7Nt0P&TN8yBf*{ zO)zYPvOyCGpcQ380t^hGiG;mSaZvej7|I5%*Ek7fKVx8EI1gpNVPIeY4XAeW)VP?8YY$8&tb6FfjapvO&4yACwJ>8Wwg21|cB^22dTr4`qV}^TeQR zP?;|SWrLPkC_&kvl@=OMwkv3vj2@H&T5VwjWrJ2(xPsUq(-{~TJfUomBVs^oXf>L^ zzWK;aJ60wRo5?Kq{g`xYCWqYjV{)*ayyU(g(;C~!U+()c?XaEf^1zSD!*24F2YyTz z_LHAH@MGFzKiTA=AJYl@$t@3$F4*K~Igf%E9VWkjq|D^wFj?fW8q*Ty z=?@MuiV0nZPFI4Q4{FXGah{y=SdEE=W%`AEjABCH(WDQ!Oy2TXjZtLs?Z@g&H(VyO zJW*r1!7_cqPiC>{_YN`&Fs*T$9P&hs=>h9>fiiY6p-?6U@CtUA@hP5@mpoCMEcH}E zs0dA}!fW!ECu&RqY||H9V-phswdp}?-(fl@cujVBs>YPSHobtESxo2_sDT4o91U_b z0|P?|+w=v;*~BKVdMd!w!8YB1iCIjD57gK}QnP?0i z{_tFh^+Xy2!=B0FFO*p)s4_5wO}2lb%=Aoqxeeq z!GmGC&M`(Mrk1?PcV4J5E!3IJ@=}fIL*8Vamujq>h71hfr_Xm~RAyo@om}%$jdg-0 z14H@bAQKe7c}It2m3Xk&*di#RU>f zh8Ej5@-u#AVYHaOT!b-D*c@%5*2vUk`UZAJk?r!LjNc64jstDh*lz5`_z1RJ1MFV0 z?M8l#pBZ@|8xBBCMV8|2h5?KmGBAzX9da0NvejpQ0j1YvpdAT0#-PmsH$ht#azSk~ z(B=ftOdtoypUjOQCTK$eC=r4-12DG*f!5cvFe@vl$pTS*9>CFz^^M zF);9h76maIGJ?9O0(zh#o@2^2CI$v}P$@cnMlqwi&s~sp%%CNm!k}IRGng+T3@W=J zYz78VQ1giS9W!Y2hS+k@T8(#LrUz)<{yWgF1o7h35(egX+qFv=>)06Cx38*V+{eus z3SP*-#9TYQu#GWQWph1@52hKJA2NVeORz9AZ>a|}7@5yc|JBA=s`3Z2MuLgC7OHY4 zBUk}5^Pf5}gORyy`{Z^;c3wvF?X#yawzD#tZ&#kh_)HfX!p74DPB2O^nHx;5lh$B5 zqcJ_?1fvq)ZBU8H0GUz0!#R0lp5F9(CmCfXAIOt{Fdj&7z!*GW#&iKbmV)K?PBJor zxIQ2PuG|8|GXW7E+m+5Rer9B3pDuQe(NpQpXCoz+HHQ}+5`b*BNt059?6iS!+gKQ; zcb#KYn7;BHqY-1-^gHJm3mMl<_dCxh#khWY=6OaP#(mSLoo7^GJUxB>Wky-1MQ5hp zI?pK2cy{`}%Zy4)i!Mx;yTGUy!<43)eU{Z=vx34R=++%0CBZqD1GXXr(xhxrZ02TQ zu$VMw@uEX25T~R`$)d4oA3m*0MkZLF!;^x1;}I z%(g@S8DMN4CfN_u!!9!VGa5}_c9GHBv2h~_awohD;-iNpphXfrkhwasCs?K4xH;{^kOsyy#j+s1L1JV3w~rHT}jFMtNgolidy> z!from*qJ#pgcUJ@e7-1iy4qF7U`C(mRaY718GWbEy2{vYHxo0s!VWV!DGAI;0clz` z3sc@nN#G7dayBURq8QIl-*t`AobloGPuCdj89#w|W{k_H2cBgVo<2dCnPa+*Ff$L+ z^4%Z_rRiI)Gb%DZ1+f*Tzdy^!w*Aj_Mj>X#Y18>{GnO;E!F@vF?oK2x~8zo3slt!gZ6CQ&|v`W24nvUqL|oSIT;vOpnJongSG$&f|hhJ zGqPE7GB7Y*VP{}q6#})-nHf2PIT#q2nOJo}%ezWA7#LWkz(#Sf>aa2}FxPXigBD6K zv#>gWy4o!4pt&_x7G@Uq?;t)ShYD!p6w69bb;1N1Nn{fNwS<^JT^cq~&{{PnLC|(7 z-5iipGeAay>mVjyP`Q^2vWlsP4YZvM)aT@2VQv5|Y2(ZVZzp2}t+Qre-~vf8odK1Z zZJ>r98_QPE+7vg?av1ilp!JwM=Ijg%>^mNUf`w-mD+2@jPLMDQ&kj&Iy$i(V;MvH* zz`(wHGN=IOdBVoPz`h5>7GPjw5ocszU@``6<=PKoayv0IFz~P+T?Fb+LX19vWb{dp zaZsaAf!G`jObbAo&lG~zeI_$AFo>{U1FfL~Ra*?~H?M)6#RS?Pb_*oT!UO8Evfl=o z&%waPk_NKA8swt8Ye6Q+gVvdGbc=v0pnA~uM2=oiyP1Ip)Pv&a1386-f$0`20|Q6@ zdyw9276t~+2#{}>f|wZ?IOD-gZ4fgJ#N=gR?289gaW_Fj!xO+vPSE7uM6lD?SU_V1 z+!0I+3_gq4K(EIdu15uqLsn}f5IfpL-pNHq`02aHpm zfYzz<>;a8COa-x3cn*V_Y|}v|TJW%fOql_)(1zzWsFgDl#CG6m2F;Z%_{qe;-~x_z z#uaRgpf(Q|NSdvlB^9()F%_g}6_^QHlFYd7Kd54M;Q(!w1EmgT17-#W0q|BiPz#5F z|2!yp-328t=167+20_qH1!gc`NHCrgv~3O~$G{*A-jlb89UQ<63=E*I0^^)Xpg082 zF4r$&2XR0#DEbWKgC$_4j6n=+EL@;H7EK_pxPk>iispfQKSzOufk6bU-<2K226g&G zz|-ok?4Wj*6KEL}cm~sz9W=Hw6|@uxY`i2BctaS2lqXaS%4d)UIa3i_BJl z(!&)_kP|`~85l&tadC|kWE5kF7|22OjMu>i^)oUs$biP3Ktl$Q?O_t2akK_S28M%R zXGO6xgN6tsVcW?h8Dp5aZgWb)caw>Orii*h{sA@cK^lMI)_4c15#$#JaW@7A2Cz=h zO4b?73=E*LP)SD6204)bCk99|#(>teOJy=JFicYfg;Eq#i3(_csue2(gET0nq(LDd z3mPs1c|i^|Fd)Ss?ZV2yAm0y4?fsx(J_gXJ2;&^kFoXg){_6X|5y%*%upX3_``JNK zjKNYMzks3y6_OMIKNlU}l8HE2!hnI0sbniP(VL#>^40-#{uEJP!7(Fq0y3DAy| z!-@jKL5~3m}$;h=MIGf>;_V76)=kF(atJ*$#?%uyaem&V3Bpl?=+lCqcD5IOZil zpj*9%h8rGjo+8$0%qa9w4X2JBopZy%`0;THBZz7{Iv*l%8}r!JYvZ2%vy~r36quRlEbrM61Atg6zuz zXVEw=1_qJ+p!itD1d8}2%nS?);KhdZ5CO(uF=bFezXq)FC}=YsC?xZ^V7qzXSp&45 zL=v<)3bQa=$Am3wfI6+9DEJF;HChzZgMyN4J+e;F>S0h6NVqaEFq~p%U{K+L__qiY z`iusWj4_Nx3=*IrSCF|O5Lq;H!N%@GHZ~1f#zNu=KR0(Ko*~10yT%2COSY;!AWo`_`w3Lloa@2@c=H% zj(`R^KoR?n$&s6ZK^eve7iFMR6&N689%ytCT;?${XM)th_+WLQ&B6=}^lv4$;PP9x%_ zoE7!XOT66dIlhk;whl^-)~UK z3mQoV88H{P5f_k+01eKAjF12|Z9tiF7ephtkOvJRgKF_xP%&`Ag%lg0l0xDj0|NtS z3it~TLp=ki_=G4ZWnd5o?Nk9*1)$Ufswf0`!GQrP_QgLy>j`mCTN|tjwA>z){Xt7q zKn8)T7%4^u29TIHR3}JG1JpQIVql1eicNH2kN_Pm@f6hlDuxPz6k0JdFo3)RT1o;l z5Y!P7R$^dS2vs-H0n#X8kO*L8U;x#{pmiZ2)kO>p60wX74Dw103@4$gL3J1?oq(Kl z7b;f5z#tClOq>JN{}MG&2meCIN_9ZRK&FDKM`=*A5?sxJ@&YL5G6*tA3-B>8$cKW; zwNv0~4%CojoYTn1zyPVMPC=@TAPLZ%E2w^s;{%5#xPF!bwT0@7A;kw1BnrSqJ2<9d zLB%VBB6wZ#D|jUas!tf_u<|o7h=8lcSKwM|Ix7PMq@H>MwNMqjO8YIiiepq&1Z8;$ zhd~0=$pw{aU%*bOk76{GWQ+!vYOF;J9RH;lq(H3@Rj_Oncx#~IXHff17hHsZ%5+dy zmvPQMkRzHwe%A#TO*=r205`kz!73Sp#NL9kssXqt;bwytCFl5IMG3e_uLmXi9)57B zV9TmT$cY}-+z|(bGiXnl6sV<(5`tilfQVQ|18BPhWFt7jBp9SYj#kVB6?oMw;F1>9 z{sm2ZFwQwG2rFu#{z1OK#J6Q7Er~S!43_FYl7f#0NJku>Rf@!1W=oSaTd!=0R{$T z7+)Q{z9k&N2UX3CpjmHl_<@4&qyWy~Yh=MzCBh0iCP7I4#}@ES$T~4fI%`3kRyHGR z1o;A7Oo4_cKrQeHh(@L|1_lYxj9ERXoT`8dBIkip1_p^K&~j=LiabbWEwmr93?`$( zAOV`!TC2#wunQ_y#=sy2s&UMfz-|Sf5WxnH9%)cqL()QhB&dDF#tKdh43OPAjB}!e zVQGPl6_ge%I2afpanHsIj{9IpY;%D1!D5?}6%pH9tf1KD;Dp9D$UsQ14jkE_$w+Wy ztJSkM3o$S#!vr9)9g5(CV;eNb1&{5`LSXM;i!&ZpY_SdM27r>u8*Cau<$nw_7eBI2 zkYm7+2I>QYB8^iRY$dpE0nLSi>JBBS7&y)t4HzUkp;2N6lTcxh*ulWS0E!YXs8|UD zgA`~u0Tv~tp!yG7iYgX^%Bbn!@C21H72xL26fsylOb5pUXq~VKxT83o71UAG2DK}} z&7bM4pbD#ii-AEQ4Ai=x&I-wukmk=!u(_ahwvg7&ELK=+r~V131e?tY8gY5S1?$Sq z0mt5NE@BMS;Ii;V0^H; zM2Nb2kb!})W{nA39Y`UJ4^~(LRtRs_tP=sp1-9s)ha8C*t(xapHA33I^O1GJGP^iv znjG9X0j;3`r65gFoOUllHX#Ytq5=(#fNFC$h(>S%0;Q8kRtAOyuvk5)iUC#UpdIs| z#Q{!A3=9&W)d15J85nB8YND7xom5b|0k=6o2MmEEXTc;@7{nhyTP6~qksVM?za1(G zYEytV#eu|5BZ+|)xv(oSFx20N3W8cBpam``a3Sf|@3vCJflC z8PHZpGeT0T1S$q=nSdK5pcD$O<3t#wL77JJG$<3KfGc89b^;v}#5ku^oPj|ETxF*) zfr_8? z5~%GCDIwh0KqUld0XL-Nc4GsV+#!&X+XHM4V^BS$qV{A%6y08IprZRB%&Q<9AYKI* z-Jsk7F1q8{j3gKslwo{G$sLB^gG+AE4t975B}rh0P(4T}hMCKU4O`I-tEgvV(FxV) zi>wjk7;woAYNCNk?i~<~;8s6q_b@2qU4n{%L%JT+%#;8f%K^$#&tOsl3=*J`JW$#F z3o2I1z#z4Rfq?;5c7yal(wY&dc{m9iprEt{TI9kw=Y$k2VkUtjCXJVY0W!un2^=wu z!Qg~e&o~9FaRDy_10*V@LZSj(E>B|vmCK;>p&)Ij>ENij#0yP@AUlwv2DCT|95rj% zPDwH_D8u-Ws0l^z!BGRLR6*@8P|@~F5)__T$5>|~hcK)O3hyi$OX1Ww3t1yPYC!ga zY|H^`tjB8QY-F7vZ-65eH24aN)K0KY(BLeC1gPH#iqyqWF>s`U;}o=@5fp#hp)#Pl z7c`^^i$74=EGXfvd>?=>---bb|aN1zLU%Dkwqa9%!UV z8kF6^g&)XDaN#G$Al)v_z@S(KYCPNqyAtFdP|!2Z36z2P=Qh|seqjI9gOuI{D}{OJ z9vf(YF(2k3kUmHvgL_C>2B(J}V)YMbcotNNI6yRl{R3JP_!QLtgnJ0=_9jq!^exyy zAh$!}f?F2m_P1cSPXN0eUL0E zfKuHrh)%HEL2&^}TX3g?MzA#YgB*dn8eC_bGh3E{K><8={s&wJFb0W&N6PCFUgx3(Dt{U0Y?g;56cB(pkhTT&{idQq6b!RfQE7uPl1~JX`EW1ITw)qpp}D+bJ!FZ7(_OJ zQb-ynXpA}x6n5a`ngLeI7$pT8Isqkna6!vx0vZf9U|>*O2+~*rp2`D72dE@toZ}BN zQWKObN;pBsEtK;!Feqq(GI$BZ$Y8O0a6&5sYdi%yzC&>}$aT}e0w9w>{$iZ70&dbY zut_iBCQXBx1U6^}Sf7mm1A~}1D3oV{gDe{4a78&#HN6Y09b_p-)u zjB~Q#wjBrCb{@2>7m`9xf|Y_S5Colw25C(~hsD4afCh9lK}Sr1Fh?YZRs<&l0|;wp zFflNIFxNe8USz}rFn}=AV$B>*1_lu3 z@a511wdFyW!;3nxIit5atNx&;}jo1;R{AG}p5*Fn}<}^#1>hdl08t2_g=3Vqg#gon|Er zJO)hFt(L^{2 zbUcAjNGf?vlq0EF85oexsA6Ey-oAm6={F-UXyAyEAqYfGW0<~x zhe>4m8D=JKsS3~nMuyLf!Sg{Z(99+yLokS%HvJQJ?_|&>?D!3{hVY zhiQRTF))BmzF+|Pl95=?*3U=xEj)Z+W}X7AIfqyd6M6;Oe1j?kKGh2xXrT28V1?O? z3=9RRLLhPQ@)Cw15GA#plby+w#SUa1BSR2~0xfQWL<5NR3v5Xchytx@he&`}WngoI zKvV@de(FJo+%Yl)gDB9MO_2Bju|TI+Gcp8&D3Fm52@nfBeuXpQWWmufF#tq^cF!;| zR5O5RkS^r2(O4N67_t}`rVH>e3Dkp(1r1v;GK7IBPyxZjU^pK{gY+RCmjc+4p>XKRW=4jn?JIbg*0M5A zn;s|3q|Vqgy-tWppRr>4Iw7X@*aVx|4fq)tm>8U=D>gA+-rVqCh;h1)2eT03IJD^< zVoULpiMputf2azfqBt%J#i)t#-r22#hE%8uS|a^ z&XmH~Kiy4&NssaL^il~X6Q*XS=^wAMh)hpVVB(m5T!P71jD?ALZ#^du10xF~^HJ~$ zVP<|#uIVh2OiGONrmIUbS+Ra#Vq|8W9(amHe0r@UlObc@^!1WVCQPeXL1rmVk5*vf zoh~fJq|bVkm64fs^8a4B>APi__@{@-FiB1ClVY-nW@cbyX5r)mpVh_+KCA6xH77sV z&M7RQCC1F$oLpd87O?F7YN(5rLuA=OvMfx@m#R6Lz`C|T#I-otrvH^<3Xox8Vt!x6 z$pMy|#0oZ%l@oN<8yhFj^jK*o8OBr7tE8Ds7++0aFU_RHxOTdsFSF?M=h95JtiL%x z-YZaK5}R%>!(_zE%*K4Hf>Q!)*8b^rGE9|>ZPS0qFsXrL&Xq%DPEXgCWy)op&dtco z2J^CaJrmfYJYbTQfsvULUriJ(UZr zh8IjSg3SS|VP*xXWQK@94#0z$z{trlJy(v&2oxC0OFR!y zj87ome<;Uf&U%ao+54h=EX-`o6H1}JY?&S=&lJrxiFdMmzv6Ujc_!ZJ59OJJK_PLd z1ghrZbVdaxPsUTz4=ON8Pft@|l4rfm3o_GRfk|@uVg)8y#E(JX)r#Uen*i>hVjevpNdRYjMJu@C^1~(A z7;B~{d}R@zzW*x=$Mh7CK*jV@U8ecdd-RxiCdWj5X5( z^_bilE2b;zF^O;ApvSa;Nf)&E2E3#TTwFko=mS;3pn@7C4yuDet2sgJY11DXFiCHp zVaSxhSPz=;1POwMhGFLff+yji=lp@HEYMIlNDb(udC)X0D0hSEFVLzlkT__z8fG}C zQU#S=AT=O1sAUXN1FETD;vhCuy&VIn#suvx1StXyy}}fM*r1VlkT`e{0qURz(1i)0 znF0m|h91yih0@a(NV4;6e`3tEgQ*_oR8ZXkGYP~7ommeu2{eukwVDA`g2U8+*f6Jp zYC}-b1@Z!@x`L?(RRo|_Lm+cNW6mHNgh5Maq2{Q8PgjLG8&rqF!Yc>K*%jLz&6$*V z8BHfEERbL_Gl5V>P-;44SBjaT#bm_=;!I|S-~$y|jLi(prZc)SNltG95yq}e{?h|B zK>JrrP0c|P5=c^x8TI&4Ymr?Bc?M7Y!`87 zy2Z{oZTfpZCiCfL{!9{}S`B>M;t7!NL01}p*OU4(fDVNNc@Ts_f%Fn84_fOa#Nf~H z56TCvMG|5NWRL+35`v!@LE}6^47m)TRc0VQ2!nj^8EOD% z06>T#p8>Sf79DG!4R=T7cmjW5Hhu#%*ZD>JuR4NCa6r8zwr&3t!Q{-yTL%hI$RU@EEz>W= zGKtrN4$y~gMq-4rLqJ71=#X{L@!=pgR2(!($k+@q0<<=c5i|e|I%ONA1~jt4z`y`n z^vVd@CJZ_^5+n}Q3z}4BY=P(n4bi~tVguC?jBVQuqM6#6Y@zN0jgP?;gVGaBF=#h9 zj19_p;B)!mj-Or-#UvgIbraaF&=do9D<~tt+zNFc*sW0afmScTtOUCiDh_e$_6c!J zml+w`rsp&<>rb~&U{Yah+rA@#DV>qAZM#Ae(<3HMkU|kb28OQb+^I~>ydZCZ8psf# z*{Mv*aiAIy)WZ~sWncg$Y7mOGQ<2W}j8PS|%1cBFbR`i3187kfj15{71!997Q?tD}lPR3h5LEMm z`oJJ@P>l)N%OH}(zyPXhKx}UCx^4yrQ0En-=E`*OY$oM;P^Am%-GP*XhPpv)n14WX zZ6KwfN*dJP1gQbVDu~Sujb+dn5=afm98kvvqy`k*AU4b#kbamNP^}1314;#dK-=|U zia@)RK@y-O0b+AQ;|_GR0Z22bwif{{>P~`ex&yIcYQS<*4B$op_@vk*$nmQnHa9d6 z=s@*?76F3T5WV#b44`{%Ko)}%8;H#f%^aY!twG|Tga=}CLlY%vnH$JKpcaG|)KJjT zwIDV(Gy{Payn)n!S|6Z}704V=LItt8p$Ru0q&GB)fdQ0iK^%yS7#KkHJxBv61%ueI z5CU~{LE@l93Sz_5gN``{iGxxrh|S%$eNHaZJ61{1RJ@2P0|ThF0-CD^u|bt<#`eX< zO#F;YZy2U;DPdA#1+{EuPQP8kq+JhEx*C*>GaxAk#D+yRXtp0@1V|02PbreY0Iq02 zY?vECJ#3hoGf;Ct$qK}VnFCrF08<0%h=R-kB`fgh88Cw$K{bQY5{M1+Ea=1xkY-Se z>JwBAC@q25Ff|}KkQz`+3zRNF7J!l!hz&~)pb-*~IB0n?hz-$O&%gjmS0D*c`3Yjf zk^^Wr5=b1Ben4zkasVwd09giVnSmOiAT^+*1Y&bT%P!Dz1CSa}6AzTcKx|Oc&jOSL zG8n*D-GJEK_0R&&87cuvS0FYl&3Hq_L1_uZhPax60hF#l7K4%!hz$$HB&d2&QUbAI z>hqxDpriz1!^F2Il{2-nFt$y9QO(rP*tWf*hG{huW7~F>dL|`qEzk)xj3EDm?ydqY z&V#ajk=UR{7-Pirgr$ti^-yW>xlN$p1RaEdq;w_{8?@4#5n4il&XN&^vNt2C0pI2Y zH3xid6V!b0QB6?s%Sh_$?}0c_2~gV&=Jt0;;-5imsAYeU*aD#8f2cU^DX4}+APK03(@1Pk`w(_kFZh-ms6k&r zYM^?5gV<2LETBmbC|d=I4LURh=7B_zIOr4?P(vKlKm?tq3JS0SkOb7npue`9BR&S5E~j=pfgQidO^Da>lvXMK!=pT*#AKq zpqjZri*G=)7z_*yd~6I1!cev(NF1t01;mD0pb26_#Z5qLsJJDF4Hb6*u_5C14B-3h zpc0@%N*F<<4Fdy13`h~wGSET1Ad5j+ItNL-0O}x+cqK?2Vkkochz->{5yXZ@*(@aX zDiAvW6#fhh3>!cksD_~l!$M@Z~%NbLVeY*3bDgqoucnzVwleL-xfCqqDNVNhf< zFhtaY&boziz=!NY6%~RMLD@ARHq>X0AU0GSvsQ7A-8mO74L2Rh_H4qy# zcg4WKa0_IwD5z}#I@KN|0af$?#D-e-6~u;$GlOQ_plm@TwmcGB3&e)%)d#Vm>a9R* zsJK0d4Hfs~03GD&4+#oCkOb6q@gO!d&N7hL6(BZLeI1AmRo{-po`A$Y4`M?ty9HuH zkF>qV!N4F4X4f+?yaY)=6@3A*p)LhoHw6n`7SNO^RGbsUhN=f0w+}0bBtha}Lm3!! zk=S-1HdMVQhz;u3fx7&l!(Qv59MIe!%(7&VBB*5egT$fi`u!jdRKrma8>-x1l72nAPI!F*Iu@6b&3=$iBEG<;c9VGGRAU0I|4Tudj z6tvV97L{zEgI}R)xIt{F8c`4%bZaWe|8gJ>)Hh0?<7cH97(m;Q^pM1jki@M);!s1u z$KFEqdO_8I7K(>~)Ii0fki?Tg;!wSL+@K@%p^A#2ia^_y>OhL1;!Q~6-5_zO=4l`{ zRLv}?8qn61Wk}+yki<8G#G!h3f!Gke^$e#$9B85dpQQ_BKLLq@f(Ue)7Kjbe!0;J~ z%>p`>7OI{Xi7g9aL-i_y*igMXNNigWn-diN3=9lzU=E}p3InmBnqxq0sOD58b{-NN zbY~Z=eb50ChdO8mhz&Jo9*7M!2egcn5z5}pgCuc#`uoXD;`RTKgg_^^!PH8F&Txh5 zQ$b=|AhCUr*a=8%@QJrjy&Xv6;Dc(R;@cqNkPtZq;ebQr9ugaTkStWgZzORwJ_ZI@ zq6e*?V+8GJWnf@14K?R05}S=5>H(1d1wkCp_%;IrgD5`(gD{k>01}5< zpbcU}Ee6f)!F+EA5{Ihs1hJuN{6K7|cm#;;2M%0@SP&a(ejaEQ6D%!(R@lJU?I1-^ z4ZR>XRKqkR_IxDv6%ZS0*?kZjw6~Rkf#EU8Gf?(BkT_J$PY@g8(0Yb{AP!W5QvkF( z2;x#c5F08kgT&TCVp|}wU69!RAU4DTh7b@NYEB%84ceQ*z`&3WVuMx@f~?CHU|s*%Lok;J=^#AhLiuLiN9IdTgU`v`~)wfGc>4GopcpjABJJ<*^O z{Xh~>&2N#|e?e@hW@ga-DX3;1B(^Mw4b`iL#5M!5p?YmVY^YvWC>xai7$Tt@ke@4& z*prdi%aPc-k=S=YY-sR42eCnO2cY|k1Q{5Fq3mxUai|*5VdStj44V+BMFy1+5rSq3 z&=e37TMvnC31UOz)egjl>h%DzL1PY}n|DBLsKuc|5J!Oa4Br^3bS85jzYBue2D z3=Azu;!{CvXzn~U=W6~t3l#WHT7*E4m3!+L2RhRG!Ppq zJ{!b_iZ27Pq2jASY^eB7B=!*y8>;3chz(V91Bv|@#D?|AUw}AJMV~=zsOBFaHdLHR zgn@w(bZ!~wgdGqY>KlF$h|fTKiKLOl<&nfSK;lp{jX`XvUUL!9B}b|Z44}zSXCw)C zsAiCO07x9FIU2-L-p2!*igL_Kx|N&0Oh}#Fb)F)!%7ev z>dW;YHdMn7B=$)V8>AU@x+@a<5r_@d`vSy<>ivks{)NQm2KC5bWxj|g0|Sh$0%AiA z(gLxe1{ou<-I3UdNbD>mb{!JC9f>^~!LDamg5WUhKw_UkVn0A)e?ek%h%qoQLLH}s z#5O}>+as}qk=W^AHYof-*#pc0m46HjElBKDAT~4sZUwPH_sKIbFzgg#U=W6~kATFX zYR-e$(D=RrVnfC6gV<2 zj!*%yp=m-FiERsFL)ANj*iiL8P&U~Ap->LU|J5Ki)DdkUHfR+)0|P^sI0J()lsy$B z4pp-N#D+R_DToaf-vDAm#kYdkQ1Qb^?2F<^<^NqIi5DO?RP$R98>;y`hz&Y&2jo%- z1_nl`gIGWpjA}A4fM#6;e!Qs-_gghN@`*v7zFv zAU0IIAH)Wo2g1O>FayMfI&Kccq4f-)O*$)(B-TJAz~VcQ#P=YHpGFeD17bsi{V5Xr zD~JuX_&10RwU|YUfq@aq7L@|E|Dl@YKoU^49*7OqYyx6KHP|At{XlG}`fwz6I*1L` zn+sw?^_C&AyI^ck{#yd$FfcIeKw_T*v7y0u6U5eq#PMAz1_og$`vpiGs^&9@4UK{y zAU0H-O&XC_1VL=58Zl{5j~uE<0VDyM+F@W|PzAA}7MOw9P+!_3vHd}8sQOS48>&7I ziCu)mo(p0_?OFk1>w`U0&#*?Cfk7C;Vb~6mfGRo!Vnbbe9K?o-Uqxa+0I{KJo`Tp= zHSa-eXRrkfUqEcA`K&UCN{$cA28BNZ1A`oh1J$4cVna3PBC#Ej*x?{H)UqTH8??fT zfq@}ShJisC$}R+nL)FxP*ieTyg4j^;{(2-#{#D=POL}G^`v8zFBs9kL!c0K6WZcz0q$G{*AWlsf3KouUO~M`D|T*ig%CKy1(fPz($V4)P2P!cew1NF1sr5{aD-VT02jLn(*@)zFE=UW~-v z0%AiA+7Dubk5gn|I1I83%034YhpM>=Vnaja9*7MUe*I|BnlJji?y8|42i zkOWjwDToc#Tm@o7#XFGLlR<2#ni(KARLx=#8!EmM#D3}qiyKq~*w zffPYCUk0(Enja#uKY-X!&EkrPGD8W(2DQBy7#P$P85o42Y(tPZ)EpZS8*08Ihz$|1 zX9xgspc-;OY={Iy0TR0ciCu%lZbV|YBC&gr*b|W0(~;P-!E8|YgD!ytb08JQawPUT zB=#mG_D&@BUL^JrB=!j;_IV`sWhC}36(r6*B=$2T_N(dBS29`Gb0{G~oCk?5g2a|U zVk;oARgl;^NNfWnwgnQ~28rzqVS`T0WngfJaKItukHii}Vn-vfyd-{U4 zjAqlT_AnbvzqNv0V!PKWrdsBD=qzR$=v)&h8+5=SBXp9n5+n{~Hz2WFkl3KJ31OGU z%>s!-r|uRav6mvTK_?Qz)YtDuk~oCKK8D0Ti^RT�DK@2s7w8lK4j?_E#kKA0#&D zz92?X=pqHsxq^()`8_evDhMcB7KyEh#0H(I3sbL;ByNVpwnAe2Ah83G*x{i2ieLss zBT1wpvBBp+K^;_pBo4kO3@Q#f_z-3e_&zYG_(UZ2;FJ5H;^6frpqV&OmIN(0fz9uM z?k<9{!HZ8oiWnFeKxZAo#7}|@g^FK5VqZaGgV&otClj87#G&kWNbFCb`-)&wAmGI( zP(`4NBVgj}pyd}(ac(3w_|h<_IOx72n0oNuTc|kbP->Vsc;O0E9JFu+D$d6Mz62U7 z;X3{N1}0_3r0M@RFo}DDZW@9rV<<$j8gy(kOuQCJ9CXnTOuQ3GeCG7{jZEUIOOb?D zBC$6hvA0a`-^iq_3OcqJX3}LO>03zbd(*FPWKymN9exN?`Ugpx8MM#?>MhV^LNGOg zNaCVMY#AiB0umc^u@FqJ9+Eidjv+=VX#TN8k^mj72-Dz?Bn~=A5hk95Bn~<^5he~= zKMiAp&Pjx^JCM|aPLYG%-aDHW)TDq;`GD8XK-tSc8lY^@iEp57;-F#_ymkgU!EzX+ z2FeDnqk*z7B8gu`V&6exKY+18`3H0%5X=JbS{tZAUtx+E7#Mycu|bE-!PN7ER+vE5 ziy^V4kl5fgI8ZejNaFfzpe6-W!Wc=y7KshIKnP};2a>oC5*u`e9Bf`B2_z1kw*X&^ z4Q1ydiG%J5f~rqq0G(J4ydRRcZ{AIj!Mh}ScK zZwH4;NFyW|l#tkJNNmtye6YzR@a5ppi6v){8YmllQ8<(xh$J40#0Fm!t_%u)1_p)% zB#A5}b{-PD6p3Al#BN4ngI85SE$%}SpM=DogT!6{I$Z$fo8?FntC85?8^@uBg3b1y?3GFVE;ddazG{dYb5q3B=$EXHt1YKm_guE)1j6L zgBCYI+2TlSMI^Q=5?cp+D>+ny0g{9j5*xf045|in?*`0b@VYRlcrcRsa3ppd5<3Zr z4LY#_Vop5+LjjURITE`XiQS6C?nGjP*N#CQF$GC{9uj*I5_=^Qdo74v57oRK#DTJR zBe4%5v5z6KK}R9NCXK*nZbK)K9)r|C+2HHbp=|K==}`7pBsKMakT?vWC0S5KTu5v_ zB(^9LTM~&4I*SqJAblip@B%idnN~>RE)e$g*4<2k_29*9P({HI2~b*Oh(%&2BC!jQ z*x&_kP`%Yi;^4(^Q1Nyo@opscWC$C4W)Z{m>FRr!l^vIUUDLB|lnruEc7;?PMkT_m<465ATVmSV6+ za3G89pqjm=f8WQX%o~p+ojhHAKa(<}b2=ww6K zR9qHF95hn~O2vgR4g&*2DH6LLiQSCE?m}YsA+bScBf>0Lf+W5MiM;`d4LUEe9;V?i zk_71BM40$BByrHO=rHkzNaC-N*zb|p-;mg#L(^e;K}Q5KLT1qF89-;FLpcoMphbfa z2?l8-Hh9$|R2;PG5vJY(Ney@fBvcLP%sxiwq*f3}4U`>;#Eu2CLE+E9zyLbM52m3Q zECDXo8LE)jbx3T`!Fr6)iKZzaaVUE>5_>)p8+6njO#N0Q@jak(6=4zwkR&dF*wE>f zYe?+7NbHA5Y|wFYj8OI8k;MNYv6(vM z6eRX+BsO^2Ce)mjNaAbZ?0N=CLco_Q{lA2pc?3W-mXqJP4 zf#EF@`wJ5L2NIhJw9v60s(}r}fwFm#*n&uGX(YBh5?c+44PGw_H3xLO8zYqMfTYF) ziCyo5!~vcE2GbCaB%X%E&O&0BAh9cu*x+TJP>Y+9#Cwt06CrGH`eT>@;egT>!yF_w z=#V)^=oHK*kT{gR6N$YSiG3c#hR&{BMq=MWV&6kzvoUN>Im*PvRu3K%hHjPwT|*Ds z3djr^(1Y$b%K)*V+r*}W*wEcwpzFtB`;x$SJU~b5CxAwrpd;~jL2T&IuMlWJ13G#O zy8IbFh<5|jBZjWq2KRiS<7Wn-9u;(y3EYQ-c7nq|EpljA;5&$o+#G{8HfDnwC(sJc z1XP29Djfy}hO;0xw6x>^*MiU@(iv1{Lrb$d5F0v4y&S}b79Q_FY-o953MycrlbN7f zD`0uP8YB+QdfPy3XnObvVnd@5TnK@p3zP~#qwhk{C`e>xU;wc}=V7En*`Qd+g|a~> zwiH6ypkpLjKy2t{Nzmv!=w2$2-U(1~&=DxpplnbK&VjN)v9ky?2oBN!8mk43#DmzN zSXc*D1UfTx3zQ8Cq+L)pXk+^UC>wO%#W5%wn(v^x}J zR|06K*b}HkGH6EzlnvS{{SnFroud35$_DKN{|#k>Za?A!U0V+d9?*7VC>s=z@=!L& z_i9i!NSPs&4LbD20?e*wU;tgH3%WKL*%w0z42EWyA4S{UyIWrMaAgZ7q!)PQ!S zhe5@2L0bx;>_X5W36u>w1rM~f6tvRMWYU)91cp)eJw8A)`cmRkX3gA7^+WrOr?fwDpBcR|^pOmqOs1|67i1j+^-hHxFk76gSq0|Ub& zCZP z44~iz%?NOpylfq?-u@Gm3^2|3UPS`ZtQ05?O`fTCb0lnqLN zpxeHL>O~nCK!wy%s065xIt^um&JYI82!IR%Wi!x>0Ei9BS}#Cqpv5X^;9p3b0W_`1 z@C7Oka`Z1K8+3#eC_X`IKw8*9H_wAk4`pCrsON%mK=CRIVuMl;0|NtSv|mU9Vkl^| zAH)Ww2`i`?P?`V@@PoubdflPopaRhs$_6ct18u$qsR1oB1`YOu*r0Tf3Q_ih%)CaBYQ(g9@en zP&Q}@5@^&Oqz07LFS6A$Fn~Cq{UD&BdJr4r2+*!v5F1nwy?|;4C9cmVh&iC6K-i#c(6N#HQ1(^^1_scGJjhJYCOkQ)_$g5NuL9+O7NLVK!38P0!N9;^ z1{DYGyt9F_L5F*|LfN3hJ^Y|-&;~ou7GRKG&_N$jP;t<~3kgs*=un0wN6321b_ z9;5+ut3we~0(6^01(Xds+yit%D@ct3BLhPVR2+0(W*3wVI&1+nIuB9gOPz@5tJRo$iM*FN(@pT3%Xr*3seHM&2JZ!4LW-Rbiy!55$GU~V^DF>!5^UE zd5}2h{wdJ#JctcCDD*K%4Jc1CFff2d;e})%iT6EJ9F&GYTaQ8FphZ!?!Q%A{44}il z7&#aiKoX!Tk`>AZ-AE+?VuO-80|Nu-bYLMlh@mP_aZuLMfU-du#~Q>2rApB5KPVei z;P^t>pd19c?pR2kfdOP}BxrCO!~vB7p#8}pHmIsig=zq`N3x-8(E77NC>yjQvmD9> zZ7r#WvO&cyXjEMYlpPot7-oXR6(NpZ0A+(50UA69si_CK0yKIK;(+w*fhq!Jq2o|C zC<|SLvO!tsHk1v@LQkMnG6gJ3Q+a}&;leV8+79W=)Oge`t=M93`S6K(3vR~ zP&Vk69nc^-NX=db&^^BpM_d7oC3-;>fo@0ggR((cE)m3rHZnn@;X=xgU@V4;gMzUR z$_9mE2b2xcG7-uKH3O$Z*`QFI3uS|f@WmiDXmA^};s!M84YDAffq?t*`V`#K^w0@=72)9 z{wY)fR9d};vO&T19?AxtWW&V8z#s%|V)H`TpzI_9WrK=jc_!Ks&;j}&N7RB&p@NEoO3y4P8+2<9XwVy^ z2ITuPs5mGM)j-*x8#|hyY*4!C2JO@aX;{I)z%T_W0oq_R3(5u^u(JTl2A$Qj49Y$V ziY6%gBxpG|lnpAvL8IUxGeHOJ9D$014(>SxWrHr@xd3Iq0r}t>lmj|v3bYj*q#1N0 z&m*Wf=ujQdkT^)3fsujX9aJ22#_bm<8&tOcg0exyIjB?vsRtG3pwV#<8&quba6_UJ zR8$Lr#&SUtW{eCBpy6>48+161B2*FRIvy=38?^h$0LliPb7KZ&gAUfQfwDmd@i;-* zpkf=ejT~eq=*Xl{JeAgG$C)C>vBVHbdE<)=?*v z4Jr-$p=?k?V=|Nt+7JWUIxYk5ml8twO+4Ye2+F>vUQYN2;vO%f$I+P7c zy$_&lQ0fH@iGvIUm4}Kz#=;&^B)n z2h^ek4UdD^RiK5bJPZsVHmG$g17(Abl zM$tiPK;{2*s5r=%pldoo;-K@77DL5B_fD*YvOxvcdeH5fAVr`P&9*`%K*zN0hO$9E zJ_u!l`hG{DY|t$&H$ZG?KmIY44XSEiLD?W*f=1DWbRp6D4Jr;w3V)z%Jy7}2z{|h@ zQUpp+prLaiP$~n}_aJe7NYJT5*&su;p=?khHH5N3Jt5F&IY=+4cMKXW2eCn2e?O2K zP(9ATzz_*#gB%LlNiS4y2uXmTA#x!@h)Z*zia;(cg0exK)G{a=YO}-vO$fMpCC4Ll!S$kfkDU|5{jTpB0+4BU4jttdT=ucH2Mva09hsr zkzfFMP8rGuS)d7Jg9c4Oqv9a-pv?~sAaPKy1JvY#vOzxcfwDn8A<#&;kR<~HsHYYN z6$f?4GC}782!Tw5j)a5QAkCnWa1a|b#L@=R0IJAA2ckmRAT^VqY)~I>29yozrO$)1 zL2bh&P&TM7xeCe#^=;Nc*)pK={~(A1N+}Es44^{=glr(ebrvcPYOP*|vOx~I31x#i zw)dfIP~-C{lnrVGzl5?uasLOzh7LS|M#6<`A?9=NGcZ_zIH3BQho6A~#0H%w3K|I) z0%dy89wCsp9Yh1@Z~~AxNWDJ)c7^*)*Z7&1Oql-T9g`o^i3!s^-ZS|znM|BM14KJa zoc`iHlh$;j&rBlI<@PZOutrQ|V3;u7`U8_P%QJhr#CIk&#vRk`zcZ;bNz9&}0pjkN-Vfrc%$~jj z#62+mK8SmOdHMrSMzQH~KbQoVU>r9nr+}GRYRA^SunlgHBYa9lvyhlf=oR9n@O4J z0>|_ZznRn+_e>Z6!=%pigJZhGA0{=%AJfzSFsU<&Oz#JYYAl<+10mcq2zA4OVj1E)PnbjFhrus9hGrpKw&aBQ@F?Bw(I^%??$C=fcmheyg zz^umjWV$#bvpUlb{^<^k%xX-3woT6f(Kq;~PhezLV-%Ub9VGpOfBFLuS7$mq6SF#_ zz;t~OgIA&%6rUL@g3z(VJ7_WfL6Q8~gB=$yN`T>v_%k+GZx_=<864UuvnAMp~ z1g9r3vWQLhV__Cx4457d5=#*TIb3Y|Jdjw+^z|UI1%lHXn3%<;zhhw*VA>-%jg?uA z>4M<&1;^RMrrWVH3otzqoF2f+ti~8Ky_}UuO5|h7Z%F*+42DF)#$kOm|^pR$`j%H9dokS&hl!|MUqUdb9WR z9U$6;Y5D^;W;M3mJ`4;d{L^{ZnU&aFSQ!~)M5ddtGb^#ak7i)_H9eZ0S()i&>huP7 zW;G_2w8;WFV$=7rGYc@qq)op75=)Sr{sTn2q)%7iU{+(=BQ@OvM2D14F96Xt4bx|E zFsrfN>0)3wKK(EUvl_dRfsvu9k@5Bq9L)EGY;r)IE@sfWK-OGPeafuP#K6E>47%r$ zjfJ%V)RSP(Ev;Z+Z3HnH7&t&O%oo@g7+Bl3bICC0O7dJZ_{hk>0K%*nrZ<~1YcU?3 zzRr}{lIM~E7YhRe2(w<^{@IjS(|r1Dbyf)`Q{(B5YOE5>rbgz|19O=rrk_)1m0~mi z9cnJYY+`9Py>SYoIJ1d`1(acC31&=h)?k&MzC(jmlG()AaJph1vjmg50fe?NgV2@` zrOYOVU0-P(J)ezbI@2xg=?l16f|$H{rYD?YbYi?ceLg$O;^|%-EH0BDNU%)5cal+N z@_{@B42A(rL;}Xp05N!`-{WNQ0kLGJ3$U@6fLW6tNN|7{BGdVJSS;Wy2apO2rg~10 z)oF}j)8BKmgfoeAgSd7IA)t{p=<(8^Ne~bQof-zB85kHECU4BMV44e7Y$XIbTni)t zJ*Tljm1p_}E*2-gP|#33)Q~Wq>4MxWMNDn{APf2?AIQ^T@)DYEaEeiksYYn>gjZ%l zi$Sd}sB(~TSA?ej;bw6YWCb;rki;dnXY;c#aWk?^&y!-2kx*)Q&D_w-(msWM!E5FP zYgrl@7#?siv@uQJB*mh_cwqZ=DHbC}=0nT>Pwsy&HvN<+3(s^t8I~~rU^a+GLk0$e zjs*u47%Vu(N;0f{Mr#59=ZBwb`+IJD&IMh1q33=9y%AtbVOvLB|Omtj$x zZg`zhnBz_|Sj*4p0i(-ZVq#HaJiu~^EZ zsxotg+Ik13W(hDj@IkFdHmZm~JD(B3F+V3Pu_Tf0_$1xhXOzf=$(6 z+EauhaF#uVcmZM!ghcg&A_Id36U-d-$y%WBU913BIsKagOEROv^e9D^=;%C=acRM9aoF4vC6&0bFig)=W|7_Ar_Az(i4Sxo+yMm! z4W=+7&SS3AJJeVan;e@8H<5xdB-tG8+<1(+l-j)Z{PEIRvq@k%6HBnl^bj z4k$1*C55taFihX7$CA&~rZ!zopT(N->GULh7H6FuOdGc1G+dE^L17Uj4nU0UC-qrW z85z~5zc*k>QPk`>GiQ-ta)u~lVq=^>p@30ux|$V>1mlhA_Es$AOp_pT z+s|3Ca4<3%L3m7YP}&VbPnWY{QDM3rHr>UB#lliXl!1YTg*7v;gn^ln?Vkt(1Jhjr z1_o9k&}1YtBgb|j1_ov(R%_4&OKU(isu-vSW?~bbzSV|BS1v`Afq`8Bbi6w=3u_@r z5onT{T^%IC`g)oziyV`Hz;p#$78%CQ>9)2kUW^;3ci6J1^D+oBFmM=vdRH9WC#UbR zWwB(eoBqv~#huY?x}6=1t=cyc1_ln#Y|xb)+zLVr3>;n{c7vd)C<6nBk2&Z*5=Oxp z(-+#Y$TI$zzTb`|o{33hx`I86n1~%nNh!!|76yJ6kVk|?r+eA67&FRGud`<{<^xT( zax^o7RLF>&pS~X?_CtVyfuk2JW+1YDngfd@6;x{u1TAVFfj0NC^CXJ{)m8fGjJ$_*$g62rY~_~G1fQ=vd@n3Bxr;|WGy!X z1BX4B!zR)t%)r3m0A9z%BXVi_eXO@+Wk<(*cSj?ic`8XIDn67a%FfiwU{K0gWlYxOb7c@k|bc~mQ zfw>qoN5sX#+|a|pz`zG;r7<^xm<$Y3AQ`4)76u09Hqac7Gz+r=<7N&929XA41_oxO z>F-=vBp3~+v%9ibFs4m+aAi^E-671tz`ffPbO#Ohq3H##ESijI(`UJ|bnt@CK4XyG z30e&;dv?0M8;dpLvFX`vEbfw^(-3)hrhvw;xf_KT7C$D7?^rNt6@4o)x1DEBLhPMBje(99tH;PLeSAoOF=$j;Jy!9_qAdl2Ll5OH~5I~ z)%KhW3>@6x!^zfw*fQMOpzGw;g06Wq;1&lhQd%d-&A?#74H{WtTwf0|6SM-Gfq`*D z7zYD`2X`CDg6$v;KHQuj3wD5lG=SR!bdK0Tka!69F3{ScLm+kpwc zD?le>ohj#GU`XHwpOklpjhTTVMbHwoj_3g>hC&zx{Xnan9=7u^Fhnr23tk5q^?dpw z4;CY#SD<4|nU;bqde_6lz#!)^{h0@gyw+V%%rigZVPH`32bCOPzM_J@C<6mCn9abT zBm=U#X1cy7i=E`NvjYd@q6TG;KvM#$MXyf4C)mOjQ(JQe}dK)fEJT5 z1~Y>qlR-0tk%57opMgP3jDf+GVOuBzgBu?MgEnI{6US0*#u%m&1_mwAjN-vi28JlG zOcYZQ2ZI)9f(Rs*2NRQF(CPq9frU=r?!}@kej}8DVFg5vx#$T4gU$)iQI(<7KYFnw z*Mk;yF))A*;b)xlil2c&1)K&~@`C)X%*eo?yNHK@0W_)zDoGeO@q!j|>cRN>przoT z+x{3Bv_PYI??M?EKnpju8Kd}%7>rbk7?g}uKtqHKN(@?{A!?9kw-*=(Y-*~e~)q~_ft1Yz|qae2qGw38iwIGBTRQ*5+3Upv9_!2}0 z#yQ3U3=E+8M+U~iGk*3WWyL39tuo9n9L$sf0a+0F&64sgJ4i90bRh! zv4E9<0c1DlcLoLq9tMfm0t^gBk3mc6ia|9b14t#~oEd^Je-|@>Qq^uo1_m{7lom6A zqLeXM1-v=9lnIo4zcMl~sAn=TmVwpEF@d7nn}>k`)Y}HfcOz4kAOnLQj1P`)cd&I@ zpg9ubFb0M`L9pjR-ZKDAKY_#;j6h+}$TIz*FN>@(DC;wFa)8PO1_RIlupP)lMxg7z z85KZ98+e%t5dR8HGoB(aq0A42ybHm zi#i(@=s>+?)9(eaNOCOWIxWJ$pf_Qs1%sXoBLf5Io;gt3xej*n z17-#WV~{W?g|8H4U{Ki&T6TJQ`olmL3C5e#e+9CrbG+dCD$2m1w{H5vZWiI`HbE?$ zjIXA<1+l0zzMh^J#G;b)g9{YY5iAT0dS4hJx4%Hl`31H-8+uik0jSIdIaTW(0|Nsn zmZyt>V-=cfbZVFw7@!di6=KiDs|8l8VQ;xg;4FI#?JOR9Zo+ zb5C%CG6m?O3Kei-IypTxm_?28;q;zh7G=g)(>DaOs58EuegjNR3t>^__{I%7p-=Ay zBw+1ASU4GfO!o+3k&^_u%1i>;Ra&6shO%MP>qA&%qi=B|WpdD*mIkQE0F|qaVGIn- z5RIUV(X~LQ!+`uU3nB*fj}~Zg7D(wjh%mTv00m2L*!1rqEOPR_VGIn9z;e+bV+iyjDN9$EX-wvwIlwpf?~Rlm4U%r4^#&HWd)T1 zj6vWc9Tas}q^567WD%V%AI`$+0SbPk+Qy6v)Ep4v@PQ^rP#wlNM_HPI!5lO%%P7JD zGMq6Av`dxY21wSd4&<1t({sXEBn7W>fZVbW?w0G*r-ieqG0BEa-xtmzD}0*+DP%!O zMk8$cyKojswm8r!xlPk~BUmK8n|MKHJYr>FP(BTEOcO7tu$N(DU{C>Xx^LkHwQxa8 z5g`RtD=)}NwQLLw2B3lw>?kA9%2dXg(+eY5M9pS`4FsJL0BO(6rYlCWNE%K6Yj_IRFbS*yv~*DA6DTQ7<~zl~z#z#Ei>WEovm;rg*<3)rW}n^@ z$s!rY&JXfDXu%*P+j8=Q0w*0bIcN47)I5{~D*%=7pq?w^9BDaNa+3zjz>=E`KW1{1 zo6a1?V#TOB-7bnn$^)FVj5tB9jq9K(P6p6QF2*^aWNZWK*)U$`2eBE0ROW(W>lWDf z4eSgI;4}=<0ZOcl52h~w8TxAa?I;#y#y8XdN3kgDzUTiY$H1TmYTkepA*X0iie%tt znaIJwU=#-mJdx@C(JZ3kA_5TGz>PHUidN7~d2-XMqgj+06{gPzQA*PfN3*Cis!V?! z%_3C~O3Ihy!Nn4|#s;lQ0DDUHBPc|L!AUw86lilI6&V;HZCzm&Q0id}QUf=ug;_w& zYQ|tt702G3Kq@_S*j)@vw&x!GsVD)JwBSkxv>;|l7y|>J64+PFTnUT}TA+n%Bf5^+il3})*<4VIT+#~^%lRhfYS())VJ1WG1LI2jlq zy{}hHpx)O#P6h_GxuDASH4{iJV+f@0^@a)3_ky%l>)%2et6|FEp4U4jP|pjr$PUuG zdd~!E(lbqDfP~OTa9h@x3l>11z-|iUVqgG?f$y)(Rc2sN0r#l+!Cf)X`Zz7n2stPq z+?Bxr0g65?PNFg`f9f>zcsFu*hG!s#0lS)_GAjh=m~;Gh6CY{1=0kk}=t zSdk2amIVU?11M9!pZ+6}MMjcM4XhjzatvB?85kHqL1U%{37V@cNI?T~0Vrq;Kuc)B zxqJ@;0|ThAh=G^_E;d2e?SeK7>wxa6gl2b;1SCK~p#Tn0ZUzZZ&>4k;I+UNl0s0!` z+c`@$7#Nh7fCBUri|1+$1_n=V1_tHlpnByK3#fmZ#m&HA4(_jhVFC4Z7=txtgZejL z!No0u%1KZbf^b0Fpj6UjUS5FZroI-sSVppgU6Km};K z57@xFFay0<4}o;U_~3}$3!V>ywkH`FK21N6%p#@m134NXO-cp^EhA`TX={KZOW`N7 zDv%#Rkp<3=peRj&sH*>ktO~TD3akp0>_IWvqJfegz;2UgV3>^}Z157aY8=!b;s?io z1SrlVKtpgw%%IVuFwnwZ2GAls#yQGb3=GQsph6%F9Ij5F69iPi(HFrAioTEB3=EJ6 zjAR9s2auxMSPLb$fI=698RJ;BHK*76vxxJ6)^LJ_N?HA<8>F%*ax}0OYceqCC4eJH z7u5U!%lEO)1_{IX;9v%=uVi4*0$uG23Y*i@3sYI7>f>0EQadPg!9fEWQUe9e3r%p) zFcmW}7=ZS7fnrz-RHlJqm{kiT84XJ4T40;x85ktNVo_iXO|TFH7b_s&fpY;Dg9Ipm z%x;4k!S%CQL3de!Y7Ed~N5(l~+6)ZJ_d#{ZY;Yr8oQHwI{6A<+Z7x_PV~~n1s68@| z^|}}X!yF!16MjCcqBaA=E)X9)qOkznq_^jVR*PoZu&{+U!?i%212#}lywHLqrp3r% z0cy{H!vYj2ps--oo_->YMW$Xxn}I3=)}>xA|{Kz7g41_d>^$uWIbA`8#-{B#zn zdI3;eGk|X6WSnzP7Zz>;Y@jlE4le_PGI)Qd02`B2&CI!6WzABPoNf(`?No+mg3TEd#E zjP`6DAYm9EoC1qLoejtkB4|?}$n}i&Y->R33a3A8VUf{xX1fC7bwG;?u&!2wF3|o4 zu&!XXAJaExun13=Pi0}%16`gA7GA=ppv%Aj=YzE`25Se8M}p!yKo=6%Vr)q19#qYP z;~G@6gTlK&cREKVi=1Y!E-2i=U1lxNa&u7nUkDb9Vk%`|(9&dt)GP<5`)9I<@fd)v zOa;{vI*yFf4Xaqh>Or9eP8k9W5}+tDx&{hj(8*~G3~ZouJm;rA1A{Vn1NIJZ#DTWP zLLzDxIHEv}KS*18H<%B)MhRTLgET_wFmMqI8Y}<@!X368Jq8BIpzQSN!7Ti|@Ot+t z+XTJo1&J);R-hYy!K$CJ?EtBU@xehR2kMzX;%O%|CK$i4-2tiF$uOOiOwisRXm2W1-7%25Nnq{M z^K)4^edn;h0||k4q=1xwwSsObg=z)u#{r2mu3{H6VqnmN@xkg0L34Br@D_%f5jc$E z+L6Nu-oyZH#sKxO(~M987!(=*^cfhcAj05U50r30DZLLW2AZw_E#L>G^hMKc@>nG5 zLCpPN>1d`R83r9tq6781wc#@u3=*L77+jCMFk)Z;$Bht!#0?_`1|!hYc1Cy5&;Fl*phhy- ziZu3jAayW4SX~xa9XvMVOu(^G?~5}wK)Kq^1SK{=JEH#SGcW`}gu$^9!N9-(ij6d= z7$`PCd%r+YPz4qP7vu(@ZCs#2+TbiGy@LipLD$Mp|5C>ykO69+t1bd{c#eaH{~6lB z?ei>C1_tohC8&L;0@~8Wcp5y!Rx8NBU<~SKgY335h2@DG-~qDfAW1jS{2~JbgQO{B zw(l`7XvSdG^o<29qHG}7>Y7eJQ^2Ck6lyyCV*!hL{Z7zm1Ouou$~b4cDFXwfL%fp* zG=j$%WDFV{0pYc#3=H;@L0R`B59mTXhGU?%DY$X76g22=20krk9eDl&T2^PBtNE2?x>$O^TqILr|9%oG#)xTg{+h3gUy)MKH+I;A)4L z0kk6lB*B=+xpKN)5sQQk=%xTjXQi4G)L8*tTV@REc!M&bk~sr|$^}qQrk)ejE(A5c zwLm!$R3!47gA zqR0`?aoz&dxrCGqH6<*Z^@$wcK|-LB2T)*wWA+U^W*I;uj39BwOb&TV1_nJCAFS>_ zLLF#VAy{1jhdW3ej1N`^I%WV`?t^Q1P$n(l$OfsK&Qi)E%TdhH58}LnxXYoNg;P77 zV>?I)v{4XbF4!DZ@aji!VFzzRwsG8^UQo&+As7Q2I-J7sAEYw|9H)8(FyYx8>Q*2R zK>1(;Ex-n9f%of#F))N%fm2?681f)KXd4x%j*(8YSnt3eG`VQx^CYZYc-fOKO; zxk0&pzc4hHSJ+H%s9+Iek>^ggp8mItMZrLYyWg6DK@W7&0X(!XfddB|+Mw;cAaO=B z?#&=|@sNm0C}-hhw&T7&J*S*S0^BuYw*iM>h&b{D8A??R3PE)nln?~j3Yx#Sh6sZy z2LsUY8K6)FmkOX@i?*5my_`iW4m5aabQIKC4*&#ANCupitUz0iz{Md0tcGUH=B@y#gYm)Yd=ctEi^V|t8Ed)c zOgF4#QRHalJ^<2iW_n>ci!eAuKiGmp)I0=lhzi)Dgea)&02QSUc3{oZdn#FY;foQp zK+XXLX)Ht&IJ`ldFTvprs`^2awRY1bt621+SJ^?^IC2aUpinl-2Cbi&0SZc>=}b0VLb~R);+MW=5YWgLXMT(YWDEJmIJLp00+rBZauXpPIV^bi92pq&j)0T$ z^xZWqoHkZGW*{NZIRT)M2AdH8HUr*S@pVKAQcyP=6r{C|;2>3yMV>weP0E3T6jTL* zRBeN(@=!%q1=?c^Rt4&UffCwfh!voK*8*)J28lg~ih(LwP!S4>Aap>v| zE)EqLBtXG#77iMJ4Fm@xsNn-T5rA<{v@-*PGI$z15IhZ@Cknda1ym#k@_+_v8G|9g z9}L!aOB9;#LE0cywlQccH0UIXeNGI}!PaO{R4Ow36lGx00qt*Akpu@0$mNJW$~z}W z(1ap;8eZ^$#-u<&qwWk*6^5(|J`4)78dN;GJ5PUH$D&;y1#Z%UmN_xb`3CYBXrDM^ z6nL&zTnsjO90hLKT8J?)sO<%%#3=COF=L3@InaPz6ffvAm$V;*OwEF9rrsRlqnW!i9lB4eW>vup=0Q)WGxC z8DJ+c216W>0d;^5sNay_JpE}si=vwa$UcVK;9RrXm4QJSe0ZJ(KdAp*DF$obSn-28 zr<=r}jRlYapd`xZ$iK;jfk96Yl8WOSSU6cc`LDT5?+<1X=Ycgz7~}YVP491DQRGbF zmvd!c(Ax+pAec;Dr(bMf5%u+PMfR!|NFONGB|wD10}!AN5-8O*K*TtTz^4&0D8Yt4 zE`TzaJOjgY*XhQMENb<2{ICK6v|yTX&M7yT*XqDtdkyzm1K4X};;@;eMzGF<;?NX$ z%MDflz%!w=8;Wy5g94y5T*9Cg z2yL3wLxjP;26dA_zMenbu!%*UaohC3CKfd>kdweUPMkpkB(W zwX;CtjMjqHAayW4SRFSgT{3`|g@OFk?>=3xnMJ|aMG(}@0yzfMt6-cH@4>)e4jxZ- z69kpFP{)9}Xkeqg1>a0>Y-Um9@D&vBU|`Ubha{-I%`BXp{(>eTAq!}t@%EVhyqQHU zIZ6<;CKqG{=&T9GIV-#v7?f9mx@1v;ptzTlU|@hWx}w1TkC1>hx?;fmNfHbU=DMKO zT(Mx27=yv#19wug;O*%JEi8&0X@dVj_Nzghw5ElHlOsn^*^_}m&mJOlp@oH$r9sf$ zbNbyD76q10!EDdzjIAu&5lR!e=(4YiI$WGAs10>0(Ld6*$2yO$ZOND5)ZfD`-_#$`kfz;gwn!2fTKn1E6s4)qO^|z?Yar^ISv%(ZlH*r*Mm_I?q7-~ksv~&hp#L5ghrU4Rh?_m*FC-ljefk6+(2Zz0;G{}YETn_8KGS&%+`GJmT z1czpr1S}6V3E6>!VSKQ58-#YyNjKn7ZxKoZse|#s>OeP|G9Vft)BM0q3vVwWq{;x^ z00FgoL0M~?A2^_)SxF1DiWL-Nry#=MA(L~^+4nbo(--!zi132uO+e>Jf$AQa=?}YE zr0Q#s?EoF+2C8rjRG@uW154OqMeqm>YUTycsGE6%I<0fSVGIhZJaB9-4TQz!9B^zV zNi#4ggJW|JI5y{i_@LMfV4NcaicSj|1_m`Ih*2QTuvX4IaO4)rFfgcqBX>SHa@T

fFKDV1iLFKj3a*&Pys0>&KKWK&%5u?|q8}_hB znJ-2TY?KHEjW>M{K#5S$eg{xQsRx2ngUJ)@?tHB4~{M-VNhP&E(?twkU^02DhAF|>9D*fC2SeQz@V27 zi7(Ky=m=%uM34~Z5HL`@fJ5~vI8?z};WeF_a3@F|j1N}#0-+9c%oRvKqnhwqkh%vD zD?mv?RbTijNC+iK{03`-n-x6$U>}P(ddz`mk~sEqGBBJ8 zhW2wM7|gGMS~X0JdxBw2QS(WliF{^8kV1$%&B52+u^@|V2gN)qqeuu$mlS9K#(Xqk40NZCB0=18k!8{(Mgq=|vuG8EIR915%oBkJ6I`c3V!qrHDX2;FJH}?o3 zE4%<&eItvc&>VcNkR0Qh5C(>Ni0h?5O;>X@P$HB^Rtdg-QGxL)!V*wDW4;*FSWrY# z2p(_BiDTFff2H(-x<%+zbpLEI8BY93KM%2s2-DDqv+`0Ac3KPMg>n7(kd;%vqM7 zfdPaWZ%p4fkwwzQ33T8Q2n%UAEf8g30AZ%Z&TgO+i@6vWgkxBoK!f-o%(T`SG+P3~ zj30TNKl3s$fH32|?fjEi@|YR9x7ST&vF4cmc`l0)WAJpfc`RM3pn8XqAp&&tn>(ls zVgSwZfa(_p6GjFGh-}n!FIFbS?T_cNd}d@kGo61ii>NAiB@06ksO$taK^Yl>z?v8s z7*>L=um-h(8KS2DTfhR^&wG)PNp!mQLKbeu*V8{TGl@?3S;(TN3>t+5on67m5Czi< zqCpFQ7#V^`Y@I!_ne$Ravj(vq2bdh%kH>5LZB ze=laS=LU5*K)Yla8KS127i1C#Z5S3<%p&3knnYn_2m%#SAZwAF3u5jDFm-w0BJVOiQ)zwmRAjqg{bXJD_QQd zs9psd9|WR6eG3+b&x}FyL9EXZ2@quj2@L6VEGmpf(;e2as3?Qn2^uIxat6qGpvD*@ zLlB6H18Y(P4W=_P1cNBhx(<-}!Sg{ZP~(-6As9r(F-|wIVir*q2fHi;M1fR*)P^9b z4FRj2{$d@AC1c!lrS&W-g2s#t3?QW-FGFO**Rv=pgU)FI&2^x;4z!nsks$~~xq)04 zH2v0k7EdNOi1pJgH?XKEf!eSTi$VSYVNmT3(gN41xQRt{`jibU@{DfNw`^chl#l~$ zgaf-Bp3Xo$B+Ko$Hn1#XW(=O*xP?Vt5VY(QWFBa>B8YC8zHtkSxFTrf5r_*)3?Ldb z6bGU~O9(*pjp;A9u&6Umnl8ANC0-De{y?Ij?iGl3+upd9C7zMCc1&;F$|B7Xs1Dkf zYs9kMQG{tZ2d}dyWUIyqstCGyz z)S_a&3#j1Q)Z?qShjJTu*H56dUU<uA6>&FN-VV=joFBSY){#)Ie1&pYE`a#euP9dgDG8C5Z(B zj4aH|dkQ(385miZm}|i_BlG#`yZ5n3GVYyzbsyNifBRTu>OYHs)V|CCt3jw;B+SVM z)_gCAlNaoeWiXLjIh=xEkyS8}YcMsZVIo_xiSU7SA*}P4>Zpz_g1@r$4Pft9+;%M?Yo0AhP&?f@&12ZEhH`pg1v!MznfW=vu zm_KBLea*-`ar(6bEK?beP0u;VqR;g|6Rd-gxqbT5gDhrB-!eJHzy?kb0~^T9DGWC7 zZ6?&f$M#3L*kN;Bm^mL7&!%E)|325S56WKJ%y z7fw&VeT2oZ{)RjwGZQ#8n3)AnmU}0juSOIbi3nTMJun03VC)f0k$5_M|cTeXy&XUFWetPk7mK4Ta({CJSDP*0` z$;iwEiY&9~Ehku{Q@SdkVe%8Kn}vzFy@C^xTYiH@7?@ZX*_au?E@fh4Zmr;y0NdZp z0kWT&jgx}`6#m>`l8u3p6Vxt)`{ENPBQq-~eThxCmto=%1SL`?Hs*)rP*WC6S3Aj4 z61$-s6j3aU%-6uCvM@2PDhEdnBl9D$2r~ybV=*yLD+eBXi62*C$yNJYJVUBY8F_$l)wZ%umapRxAUHFoTZb0!8NaGLWBG7@4<# z#Zj%8J>C5jOCQr??&*1FSmclr{DkSUr&&Vl7nMS-eZU2>hM5%{m`u#GOQG@j6fDlb z#KHs$Rd6ZE29gC8d5p{uSr)K*NOANMte%+(WGu5k*kw%2$4a58;3q`Z5o8OqE-2ED+YMHOmT0~fL!-L~EX&Le@&+>- zxNu@(eqIbRkcE+X77r)ebnde(CXCajJDg?FVWAF&$7r$L(6Wky}yxN)(UZ%(QjmzwSwKj!o>U==CUrB z$hRVBVE0TfJkKJ}czpWA^DI@2JE!wpU{PUQH{I|8i-z8LAy8WG%7;3vMG)jsW)_g& znb|;WP=T1o$pQ|-Dbw38upC#IkOz`xVFWwz16T(O6Z3>TXdTotJ?|omF;{y&L>2Rf z>8mfY$P1nq0NVtq@)?=`@J+vckwwzvZvi;{FfzCDL#_K=016fsM&@>~2s0BXd{~&6 zzZXDbvVXe9B^EpWR|OD9gPk#r9~^D