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IDF master cf457d412 (#5073)

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esp-dsp: master 7cc5073
esp-face: master 420fc7e
esp-rainmaker: f1b82c7
esp32-camera: master 2dded7c
esp_littlefs: master d268e18
This commit is contained in:
Me No Dev
2021-04-17 15:28:16 +03:00
committed by GitHub
parent 11f89cddf6
commit 5d9b98c9b0
694 changed files with 12826 additions and 3477 deletions
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5
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/gpio_caps.h
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@ -30,11 +30,6 @@ extern "C" {
// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define GPIO_MODE_DEF_DISABLE (0)
#define GPIO_MODE_DEF_INPUT (BIT0)
#define GPIO_MODE_DEF_OUTPUT (BIT1)
#define GPIO_MODE_DEF_OD (BIT2)
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)

5
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/rtc.h
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@ -376,11 +376,6 @@ bool rtc_clk_8md256_enabled(void);
*/
void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
/**
* @brief Set XTAL wait cycles by RTC slow clock's period
*/
void rtc_clk_set_xtal_wait(void);
/**
* @brief Select source for RTC_SLOW_CLK
* @param slow_freq clock source (one of rtc_slow_freq_t values)

1
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/soc.h
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@ -27,7 +27,6 @@
#define DR_REG_SYSTEM_BASE 0x600c0000
#define DR_REG_SENSITIVE_BASE 0x600c1000
#define DR_REG_INTERRUPT_BASE 0x600c2000
#define DR_REG_DMA_COPY_BASE 0x600c3000
#define DR_REG_EXTMEM_BASE 0x600c4000
#define DR_REG_MMU_TABLE 0x600c5000
#define DR_REG_AES_BASE 0x6003a000

6
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/soc_caps.h
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@ -13,10 +13,6 @@
#define SOC_HMAC_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
/*-------------------------- DAC CAPS ----------------------------------------*/
#define SOC_DAC_PERIPH_NUM 0
#include "i2c_caps.h"
#include "mpu_caps.h"
#include "sigmadelta_caps.h"
@ -43,7 +39,7 @@
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_BRP_MIN 2
#define SOC_TWAI_BRP_MAX 32768
#define SOC_TWAI_BRP_MAX 16384
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*--------------------------- SHA CAPS ---------------------------------------*/

19
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/spi_pins.h
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@ -22,18 +22,13 @@
#define SPI_IOMUX_PIN_NUM_CLK 15
#define SPI_IOMUX_PIN_NUM_MISO 17
#define SPI_IOMUX_PIN_NUM_WP 13
//TODO: add the next slot
#define FSPI_FUNC_NUM 2
#define FSPI_IOMUX_PIN_NUM_MISO 2
#define FSPI_IOMUX_PIN_NUM_HD 4
#define FSPI_IOMUX_PIN_NUM_WP 5
#define FSPI_IOMUX_PIN_NUM_CLK 6
#define FSPI_IOMUX_PIN_NUM_MOSI 7
#define FSPI_IOMUX_PIN_NUM_CS 10
//TODO: add the next slot
//HSPI and VSPI have no iomux pins
#define SPI2_FUNC_NUM 2
#define SPI2_IOMUX_PIN_NUM_MISO 2
#define SPI2_IOMUX_PIN_NUM_HD 4
#define SPI2_IOMUX_PIN_NUM_WP 5
#define SPI2_IOMUX_PIN_NUM_CLK 6
#define SPI2_IOMUX_PIN_NUM_MOSI 7
#define SPI2_IOMUX_PIN_NUM_CS 10
#endif

3
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/twai_struct.h
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@ -94,7 +94,8 @@ typedef volatile struct twai_dev_s {
uint32_t reserved_05; /* Address 5 */
union {
struct {
uint32_t brp: 14; /* BTR0[13:0] Baud Rate Prescaler */
uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */
uint32_t reserved1: 1; /* Internal Reserved */
uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/
uint32_t reserved16: 16; /* Internal Reserved */
};