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IDF master cf457d412 (#5073)

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esp-dsp: master 7cc5073
esp-face: master 420fc7e
esp-rainmaker: f1b82c7
esp32-camera: master 2dded7c
esp_littlefs: master d268e18
This commit is contained in:
Me No Dev
2021-04-17 15:28:16 +03:00
committed by GitHub
parent 11f89cddf6
commit 5d9b98c9b0
694 changed files with 12826 additions and 3477 deletions
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13
tools/sdk/esp32s2/include/hal/esp32s2/include/hal/gpio_ll.h
View File

@ -391,6 +391,17 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]);
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Set peripheral output to an GPIO pad through the IOMUX.
*
@ -404,7 +415,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
{
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func);
gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
}
static inline void gpio_ll_force_hold_all(gpio_dev_t *hw)

53
tools/sdk/esp32s2/include/hal/esp32s2/include/hal/memprot_ll.h
View File

@ -26,10 +26,12 @@ extern "C" {
//IRAM0 interrupt status bitmasks
#define IRAM0_INTR_ST_OP_TYPE_BIT BIT(1) //instruction: 0, data: 1
#define IRAM0_INTR_ST_OP_RW_BIT BIT(0) //read: 0, write: 1
#define CONF_REG_ADDRESS_SHIFT 2
static inline void esp_memprot_iram0_clear_intr(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_CLR);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_CLR);
}
static inline uint32_t esp_memprot_iram0_get_intr_source_num(void)
@ -104,6 +106,7 @@ static inline uint32_t esp_memprot_iram0_get_lock_bit(void)
* === IRAM0 SRAM
* ========================================================================================
*/
#define IRAM0_SRAM_BASE_ADDRESS 0x40000000
#define IRAM0_SRAM_ADDRESS_LOW 0x40020000
#define IRAM0_SRAM_ADDRESS_HIGH 0x4006FFFF
@ -126,6 +129,7 @@ static inline uint32_t esp_memprot_iram0_get_lock_bit(void)
#define IRAM0_INTR_ST_FAULTADDR_M 0x003FFFFC //bits 21:6 in the reg, as well as in real address
#define IRAM0_SRAM_INTR_ST_FAULTADDR_HI 0x40000000 //high nonsignificant bits 31:22 of the faulting address - constant
#define IRAM0_SRAM_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR) << DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_S)
static inline uint32_t *esp_memprot_iram0_sram_get_fault_address(void)
{
@ -290,6 +294,7 @@ static inline void esp_memprot_iram0_sram_set_prot(uint32_t *split_addr, bool lw
{
uint32_t addr = (uint32_t)split_addr;
assert(addr <= IRAM0_SRAM_SPL_BLOCK_HIGH);
assert(addr % 0x4 == 0);
//find possible split.address in low region blocks
int uni_blocks_low = -1;
@ -339,11 +344,7 @@ static inline void esp_memprot_iram0_sram_set_prot(uint32_t *split_addr, bool lw
uint32_t reg_split_addr = 0;
if (addr >= IRAM0_SRAM_SPL_BLOCK_LOW) {
//[16:0]
reg_split_addr = addr >> 2;
assert(addr == (reg_split_addr << 2));
reg_split_addr &= DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_M;
reg_split_addr = IRAM0_SRAM_ADDR_TO_CONF_REG( addr ); //cfg reg - [16:0]
}
//prepare high & low permission mask (bits: [22:20] high range, [19:17] low range)
@ -406,9 +407,11 @@ static inline void esp_memprot_iram0_sram_set_exec_perm(bool lx, bool hx)
* === IRAM0 RTC FAST
* ========================================================================================
*/
#define IRAM0_RTCFAST_ADDRESS_LOW 0x40070000
#define IRAM0_RTCFAST_ADDRESS_HIGH 0x40071FFF
#define IRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x40070000 //RTCFAST faulting address high bits (31:22, constant)
#define IRAM0_RTCFAST_ADDRESS_LOW 0x40070000
#define IRAM0_RTCFAST_ADDRESS_HIGH 0x40071FFF
#define IRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x40070000 //RTCFAST faulting address high bits (31:22, constant)
#define IRAM0_RTCFAST_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR) << DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_S)
static inline uint32_t *esp_memprot_iram0_rtcfast_get_fault_address(void)
@ -434,14 +437,10 @@ static inline uint32_t esp_memprot_iram0_rtcfast_get_perm_split_reg(void)
static inline void esp_memprot_iram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
{
uint32_t addr = (uint32_t)split_addr;
assert( addr % 0x4 == 0 );
//if splt.ddr not set yet, do required normalization to make the addr writeble into splt.mgmt cfg register
uint32_t reg_split_addr = 0;
//[10:0]
reg_split_addr = addr >> 2;
assert(addr == (reg_split_addr << 2));
reg_split_addr &= DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_M;
//conf reg [10:0]
uint32_t reg_split_addr = IRAM0_RTCFAST_ADDR_TO_CONF_REG(addr);
//prepare high & low permission mask (bits: [16:14] high range, [13:11] low range)
uint32_t permission_mask = 0;
@ -531,6 +530,7 @@ static inline bool esp_memprot_dram0_is_assoc_intr(void)
static inline void esp_memprot_dram0_clear_intr(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR);
}
static inline uint32_t esp_memprot_dram0_get_intr_ena_bit(void)
@ -606,6 +606,8 @@ static inline void esp_memprot_dram0_get_fault_op_type(uint32_t *op_type, uint32
#define DRAM0_SRAM_SPL_BLOCK_HIGH 0x3FFFFFFF //block 21 high
#define DRAM0_SRAM_INTR_ST_FAULTADDR_HI 0x3FF00000 //SRAM high bits 31:22 of the faulting address - constant
#define DRAM0_SRAM_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR) << DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S)
static inline uint32_t *esp_memprot_dram0_sram_get_fault_address(void)
{
@ -716,6 +718,7 @@ static inline void esp_memprot_dram0_sram_set_prot(uint32_t *split_addr, bool lw
//low boundary check provided by LD script. see comment in esp_memprot_iram0_sram_set_prot()
assert( addr <= DRAM0_SRAM_SPL_BLOCK_HIGH );
assert( addr % 0x4 == 0 );
//set low region
int uni_blocks_low = -1;
@ -753,10 +756,8 @@ static inline void esp_memprot_dram0_sram_set_prot(uint32_t *split_addr, bool lw
}
}
//[24:8]
uint32_t reg_split_addr = addr >> 2;
assert(addr == (reg_split_addr << 2));
reg_split_addr = (reg_split_addr & DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_V) << DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S;
//conf reg [24:8]
uint32_t reg_split_addr = DRAM0_SRAM_ADDR_TO_CONF_REG(addr);
//prepare high & low permission mask
uint32_t permission_mask = 0;
@ -803,9 +804,10 @@ static inline void esp_memprot_dram0_sram_set_write_perm(bool lw, bool hw)
* === DRAM0 RTC FAST
* ========================================================================================
*/
#define DRAM0_RTCFAST_ADDRESS_LOW 0x3FF9E000
#define DRAM0_RTCFAST_ADDRESS_HIGH 0x3FF9FFFF
#define DRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x3FF00000 //RTCFAST high bits 31:22 of the faulting address - constant
#define DRAM0_RTCFAST_ADDRESS_LOW 0x3FF9E000
#define DRAM0_RTCFAST_ADDRESS_HIGH 0x3FF9FFFF
#define DRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x3FF00000 //RTCFAST high bits 31:22 of the faulting address - constant
#define DRAM0_RTCFAST_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR) << DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_S)
static inline uint32_t *esp_memprot_dram0_rtcfast_get_fault_address(void)
@ -826,11 +828,10 @@ static inline bool esp_memprot_dram0_rtcfast_is_intr_mine(void)
static inline void esp_memprot_dram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
{
uint32_t addr = (uint32_t)split_addr;
assert( addr % 0x4 == 0 );
//[10:0]
uint32_t reg_split_addr = addr >> 2;
assert(addr == (reg_split_addr << 2));
reg_split_addr &= DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_M;
//conf reg [10:0]
uint32_t reg_split_addr = DRAM0_RTCFAST_ADDR_TO_CONF_REG( addr );
//prepare high & low permission mask
uint32_t permission_mask = 0;

25
tools/sdk/esp32s2/include/hal/esp32s2/include/hal/memprot_peri_ll.h
View File

@ -31,9 +31,11 @@ extern "C" {
#define PERI1_INTR_ST_FAULTADDR_M 0x03FFFFC0 //(bits 25:6 in the reg)
#define PERI1_INTR_ST_FAULTADDR_S 0x4 //(bits 21:2 of real address)
static inline void esp_memprot_peri1_clear_intr(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
}
static inline uint32_t esp_memprot_peri1_get_intr_source_num(void)
@ -116,6 +118,7 @@ static inline uint32_t esp_memprot_peri1_get_lock_bit(void)
#define PERI1_RTCSLOW_ADDRESS_HIGH PERI1_RTCSLOW_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE
#define PERI1_RTCSLOW_INTR_ST_FAULTADDR_HI_0 0x3F400000
#define PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR) << DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_S)
static inline uint32_t *esp_memprot_peri1_rtcslow_get_fault_address(void)
{
@ -137,11 +140,9 @@ static inline bool esp_memprot_peri1_rtcslow_is_intr_mine(void)
static inline void esp_memprot_peri1_rtcslow_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
{
uint32_t addr = (uint32_t)split_addr;
assert( addr % 0x4 == 0 );
//check split address is WORD aligned
uint32_t reg_split_addr = addr >> 2;
assert(addr == (reg_split_addr << 2));
reg_split_addr &= DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_M;
uint32_t reg_split_addr = PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr);
//prepare high & low permission mask
uint32_t permission_mask = 0;
@ -201,6 +202,7 @@ static inline uint32_t esp_memprot_peri1_rtcslow_get_conf_reg(void)
static inline void esp_memprot_peri2_clear_intr(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
}
static inline uint32_t esp_memprot_peri2_get_intr_source_num(void)
@ -286,6 +288,8 @@ static inline uint32_t *esp_memprot_peri2_rtcslow_get_fault_address(void)
#define PERI2_RTCSLOW_0_ADDRESS_LOW PERI2_RTCSLOW_0_ADDRESS_BASE
#define PERI2_RTCSLOW_0_ADDRESS_HIGH PERI2_RTCSLOW_0_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE
#define PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR) << DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_S)
static inline bool esp_memprot_peri2_rtcslow_0_is_intr_mine(void)
{
if (esp_memprot_peri2_is_assoc_intr()) {
@ -298,11 +302,9 @@ static inline bool esp_memprot_peri2_rtcslow_0_is_intr_mine(void)
static inline void esp_memprot_peri2_rtcslow_0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
{
uint32_t addr = (uint32_t)split_addr;
assert( addr % 0x4 == 0 );
//check split address is WORD aligned
uint32_t reg_split_addr = addr >> 2;
assert(addr == (reg_split_addr << 2));
reg_split_addr &= DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_M;
uint32_t reg_split_addr = PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr);
//prepare high & low permission mask
uint32_t permission_mask = 0;
@ -371,6 +373,7 @@ static inline uint32_t esp_memprot_peri2_rtcslow_0_get_conf_reg(void)
#define PERI2_RTCSLOW_1_ADDRESS_LOW PERI2_RTCSLOW_1_ADDRESS_BASE
#define PERI2_RTCSLOW_1_ADDRESS_HIGH PERI2_RTCSLOW_1_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE
#define PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR) << DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_S)
static inline bool esp_memprot_peri2_rtcslow_1_is_intr_mine(void)
{
@ -384,11 +387,9 @@ static inline bool esp_memprot_peri2_rtcslow_1_is_intr_mine(void)
static inline void esp_memprot_peri2_rtcslow_1_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
{
uint32_t addr = (uint32_t)split_addr;
assert( addr % 0x4 == 0 );
//check split address is WORD aligned
uint32_t reg_split_addr = addr >> 2;
assert(addr == (reg_split_addr << 2));
reg_split_addr &= DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_M;
uint32_t reg_split_addr = PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr);
//prepare high & low permission mask
uint32_t permission_mask = 0;

8
tools/sdk/esp32s2/include/hal/include/hal/gpio_hal.h
View File

@ -466,6 +466,14 @@ void gpio_hal_sleep_pupd_config_unapply(gpio_hal_context_t *hal, gpio_num_t gpio
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
#define gpio_hal_iomux_func_sel(pin_name, func) gpio_ll_iomux_func_sel(pin_name, func)
#ifdef __cplusplus
}
#endif

27
tools/sdk/esp32s2/include/hal/include/hal/i2c_types.h
View File

@ -79,36 +79,9 @@ typedef enum {
I2C_SCLK_MAX,
} i2c_sclk_t;
// I2C clk flags for users to use, can be expanded in the future.
#define I2C_SCLK_SRC_FLAG_FOR_NOMAL (0) /*!< Any one clock source that is available for the specified frequency may be choosen*/
#define I2C_SCLK_SRC_FLAG_AWARE_DFS (1 << 0) /*!< For REF tick clock, it won't change with APB.*/
#define I2C_SCLK_SRC_FLAG_LIGHT_SLEEP (1 << 1) /*!< For light sleep mode.*/
/// Use the highest speed that is available for the clock source picked by clk_flags
#define I2C_CLK_FREQ_MAX (-1)
/**
* @brief I2C initialization parameters
*/
typedef struct{
i2c_mode_t mode; /*!< I2C mode */
int sda_io_num; /*!< GPIO number for I2C sda signal */
int scl_io_num; /*!< GPIO number for I2C scl signal */
bool sda_pullup_en; /*!< Internal GPIO pull mode for I2C sda signal*/
bool scl_pullup_en; /*!< Internal GPIO pull mode for I2C scl signal*/
union {
struct {
uint32_t clk_speed; /*!< I2C clock frequency for master mode, (no higher than 1MHz for now) */
} master; /*!< I2C master config */
struct {
uint8_t addr_10bit_en; /*!< I2C 10bit address mode enable for slave mode */
uint16_t slave_addr; /*!< I2C address for slave mode */
} slave; /*!< I2C slave config */
};
uint32_t clk_flags; /*!< Bitwise of ``I2C_SCLK_SRC_FLAG_**FOR_DFS**`` for clk source choice*/
} i2c_config_t;
#if CONFIG_IDF_TARGET_ESP32
typedef enum{
I2C_CMD_RESTART = 0, /*!<I2C restart command */

3
tools/sdk/esp32s2/include/hal/include/hal/i2s_types.h
View File

@ -115,7 +115,6 @@ typedef enum {
I2S_CLK_APLL, /*!< Clock from APLL*/
} i2s_clock_src_t;
/**
* @brief I2S configuration parameters for i2s_param_config function
*
@ -145,6 +144,7 @@ typedef enum {
I2S_EVENT_MAX, /*!< I2S event max index*/
} i2s_event_type_t;
#if SOC_I2S_SUPPORTS_ADC_DAC
/**
* @brief I2S DAC mode for i2s_set_dac_mode.
*
@ -157,6 +157,7 @@ typedef enum {
I2S_DAC_CHANNEL_BOTH_EN = 0x3, /*!< Enable both of the I2S built-in DAC channels.*/
I2S_DAC_CHANNEL_MAX = 0x4, /*!< I2S built-in DAC mode max index*/
} i2s_dac_mode_t;
#endif //SOC_I2S_SUPPORTS_ADC_DAC
/**
* @brief Event structure used in I2S event queue

2
tools/sdk/esp32s2/include/hal/include/hal/spi_hal.h
View File

@ -160,7 +160,7 @@ typedef struct {
* Init the peripheral and the context.
*
* @param hal Context of the HAL layer.
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for SPI2 and 2 for SPI3.
* @param hal_config Configuration of the hal defined by the upper layer.
*/
void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_config_t *hal_config);

4
tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hal.h
View File

@ -91,8 +91,8 @@ typedef struct {
/**
* Init the peripheral and the context.
*
* @param hal Context of the HAL layer.
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
* @param hal Context of the HAL layer.
* @param hal_config Configuration of the HAL
*/
void spi_slave_hal_init(spi_slave_hal_context_t *hal, const spi_slave_hal_config_t *hal_config);

9
tools/sdk/esp32s2/include/hal/include/hal/spi_types.h
View File

@ -44,21 +44,16 @@ FLAG_ATTR(spi_event_t)
/** @cond */ //Doxy command to hide preprocessor definitions from docs */
//alias for different chips
//alias for different chips, deprecated for the chips after esp32s2
#ifdef CONFIG_IDF_TARGET_ESP32
#define SPI_HOST SPI1_HOST
#define HSPI_HOST SPI2_HOST
#define VSPI_HOST SPI3_HOST
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#elif CONFIG_IDF_TARGET_ESP32S2
// SPI_HOST (SPI1_HOST) is not supported by the SPI Master and SPI Slave driver on ESP32-S2 and later
#define SPI_HOST SPI1_HOST
#define FSPI_HOST SPI2_HOST
#define HSPI_HOST SPI3_HOST
#elif CONFIG_IDF_TARGET_ESP32C3
/* No SPI3_host on C3 */
#define SPI_HOST SPI1_HOST
#define FSPI_HOST SPI2_HOST
#define HSPI_HOST SPI2_HOST
#endif
/** @endcond */