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me-no-dev
2016-10-06 14:21:30 +03:00
committed by Ivan Grokhotkov
parent 668acc2c08
commit 5f3a205955
657 changed files with 170176 additions and 0 deletions
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41
tools/sdk/include/esp32/esp_attr.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_ATTR_H__
#define __ESP_ATTR_H__
#define ROMFN_ATTR
//Normally, the linker script will put all code and rodata in flash,
//and all variables in shared RAM. These macros can be used to redirect
//particular functions/variables to other memory regions.
// Forces code into IRAM instead of flash
#define IRAM_ATTR __attribute__((section(".iram1")))
// Forces data into DRAM instead of flash
#define DRAM_ATTR __attribute__((section(".dram1")))
// Forces code into RTC fast memory
#define RTC_IRAM_ATTR __attribute__((section(".rtc.text")))
// Forces data into RTC slow memory
// Any variable marked with this attribute will keep its value
// during a deep sleep / wake cycle.
#define RTC_DATA_ATTR __attribute__((section(".rtc.data")))
// Forces read-only data into RTC slow memory
// Makes constant data available to RTC wake stubs (see esp_deepsleep.h)
#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata")))
#endif /* __ESP_ATTR_H__ */

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tools/sdk/include/esp32/esp_deepsleep.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_DEEPSLEEP_H__
#define __ESP_DEEPSLEEP_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup Deep_Sleep_API Deep Sleep API
* @brief API for putting device into deep sleep
*/
/** @addtogroup Deep_Sleep_API
* @{
*/
/**
* @brief Set the chip to deep-sleep mode.
*
* The device will automatically wake up after the deep-sleep time set
* by the users. Upon waking up, the device boots up from user_init.
*
* @attention The parameter time_in_us to be "uint64" is for further development.
* Only the low 32 bits of parameter time_in_us are avalable now.
*
* @param uint64 time_in_us : deep-sleep time, only the low 32bits are avalable now. unit: microsecond
*
* @return null
*/
void system_deep_sleep(uint64_t time_in_us);
/**
* @brief Default stub to run on wake from deep sleep.
*
* Allows for executing code immediately on wake from sleep, before
* the software bootloader or esp-idf app has started up.
*
* This function is weak-linked, so you can implement your own version
* to run code immediately when the chip wakes from
* sleep.
*
* For example:
* @code
* void RTC_IRAM_ATTR esp_wake_deep_sleep(void) {
* esp_default_wake_deep_sleep();
* // Add additional functionality here
* }
*
* (Implementing this function is not required for normal operation,
* in the usual case your app will start normally when waking from
* deep sleep.)
*
* esp_wake_deep_sleep() functionality is limited:
*
* - Runs immediately on wake, so most of the SoC is freshly reset -
* flash is unmapped and hardware is otherwise uninitialised.
*
* - Can only call functions implemented in ROM, or marked RTC_IRAM_ATTR.
*
* - Static variables marked RTC_DATA_ATTR will have initial values on
* cold boot, and maintain these values between sleep/wake cycles.
*
* - Read-only data should be marked RTC_RODATA_ATTR. Strings must be
* declared as variables also using RTC_RODATA_ATTR, like this:
* RTC_RODATA_ATTR const char message[] = "Hello from very early boot!\n";
*
* - Any other static memory will not be initialised (either to zero,
* or to any predefined value).
*
*
* - If you implement your own stub, the first call the stub makes
should be to esp_default_wake_deep_sleep().
*/
void esp_wake_deep_sleep(void);
/**
* @brief Function type for stub to run on wake from sleep.
*
*/
typedef void (*esp_deep_sleep_wake_stub_fn_t)(void);
/**
* @brief Install a new stub at runtime to run on wake from deep sleep
*
* If implementing esp_wake_deep_sleep() then it is not necessary to
* call this function.
*
* However, it is possible to call this function to substitute a
* different deep sleep stub. Any function used as a deep sleep stub
* must be marked RTC_IRAM_ATTR, and must obey the same rules given
* for esp_wake_deep_sleep().
*/
void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub);
/**
* @brief Return current wake from deep sleep stub, or NULL if
* no stub is installed.
*/
esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void);
/* The default esp-idf-provided esp_wake_deep_sleep() stub.
If you replace esp_wake_deep_sleep() in your program, or use
esp_set_deep_sleep_wake_stub(), then it is recommended you call
esp_default_wake_deep_sleep() as the first function in your stub.
*/
void esp_default_wake_deep_sleep(void);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ESP_SYSTEM_H__ */

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tools/sdk/include/esp32/esp_err.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_ERR_H__
#define __ESP_ERR_H__
#include <stdint.h>
#include <assert.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef int32_t esp_err_t;
/* Definitions for error constants. */
#define ESP_OK 0
#define ESP_FAIL -1
#define ESP_ERR_NO_MEM 0x101
#define ESP_ERR_INVALID_ARG 0x102
#define ESP_ERR_INVALID_STATE 0x103
/**
* Macro which can be used to check the error code,
* and terminate the program in case the code is not ESP_OK.
* Prints the failed statement to serial output.
*/
#define ESP_ERROR_CHECK(x) do { esp_err_t rc = (x); if (rc != ESP_OK) { assert(0 && #x);} } while(0);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_ERR_H__ */

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tools/sdk/include/esp32/esp_event.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_EVENT_H__
#define __ESP_EVENT_H__
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "esp_wifi_types.h"
#include "tcpip_adapter.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SYSTEM_EVENT_WIFI_READY = 0, /**< ESP32 WiFi ready */
SYSTEM_EVENT_SCAN_DONE, /**< ESP32 finish scanning AP */
SYSTEM_EVENT_STA_START, /**< ESP32 station start */
SYSTEM_EVENT_STA_STOP, /**< ESP32 station stop */
SYSTEM_EVENT_STA_CONNECTED, /**< ESP32 station connected to AP */
SYSTEM_EVENT_STA_DISCONNECTED, /**< ESP32 station disconnected from AP */
SYSTEM_EVENT_STA_AUTHMODE_CHANGE, /**< the auth mode of AP connected by ESP32 station changed */
SYSTEM_EVENT_STA_GOT_IP, /**< ESP32 station got IP from connected AP */
SYSTEM_EVENT_AP_START, /**< ESP32 soft-AP start */
SYSTEM_EVENT_AP_STOP, /**< ESP32 soft-AP stop */
SYSTEM_EVENT_AP_STACONNECTED, /**< a station connected to ESP32 soft-AP */
SYSTEM_EVENT_AP_STADISCONNECTED, /**< a station disconnected from ESP32 soft-AP */
SYSTEM_EVENT_AP_PROBEREQRECVED, /**< Receive probe request packet in soft-AP interface */
SYSTEM_EVENT_MAX
} system_event_id_t;
typedef struct {
uint32_t status; /**< status of scanning APs */
uint8_t number;
uint8_t scan_id;
} system_event_sta_scan_done_t;
typedef struct {
uint8_t ssid[32]; /**< SSID of connected AP */
uint8_t ssid_len; /**< SSID length of connected AP */
uint8_t bssid[6]; /**< BSSID of connected AP*/
uint8_t channel; /**< channel of connected AP*/
wifi_auth_mode_t authmode;
} system_event_sta_connected_t;
typedef struct {
uint8_t ssid[32]; /**< SSID of disconnected AP */
uint8_t ssid_len; /**< SSID length of disconnected AP */
uint8_t bssid[6]; /**< BSSID of disconnected AP */
uint8_t reason; /**< reason of disconnection */
} system_event_sta_disconnected_t;
typedef struct {
wifi_auth_mode_t old_mode; /**< the old auth mode of AP */
wifi_auth_mode_t new_mode; /**< the new auth mode of AP */
} system_event_sta_authmode_change_t;
typedef struct {
tcpip_adapter_ip_info_t ip_info;
} system_event_sta_got_ip_t;
typedef struct {
uint8_t mac[6]; /**< MAC address of the station connected to ESP32 soft-AP */
uint8_t aid; /**< the aid that ESP32 soft-AP gives to the station connected to */
} system_event_ap_staconnected_t;
typedef struct {
uint8_t mac[6]; /**< MAC address of the station disconnects to ESP32 soft-AP */
uint8_t aid; /**< the aid that ESP32 soft-AP gave to the station disconnects to */
} system_event_ap_stadisconnected_t;
typedef struct {
int rssi; /**< Received probe request signal strength */
uint8_t mac[6]; /**< MAC address of the station which send probe request */
} system_event_ap_probe_req_rx_t;
typedef union {
system_event_sta_connected_t connected; /**< ESP32 station connected to AP */
system_event_sta_disconnected_t disconnected; /**< ESP32 station disconnected to AP */
system_event_sta_scan_done_t scan_done; /**< ESP32 station scan (APs) done */
system_event_sta_authmode_change_t auth_change; /**< the auth mode of AP ESP32 station connected to changed */
system_event_sta_got_ip_t got_ip; /**< ESP32 station got IP */
system_event_ap_staconnected_t sta_connected; /**< a station connected to ESP32 soft-AP */
system_event_ap_stadisconnected_t sta_disconnected; /**< a station disconnected to ESP32 soft-AP */
system_event_ap_probe_req_rx_t ap_probereqrecved; /**< ESP32 soft-AP receive probe request packet */
} system_event_info_t;
typedef struct {
system_event_id_t event_id; /**< event ID */
system_event_info_t event_info; /**< event information */
} system_event_t;
typedef esp_err_t (*system_event_handler_t)(system_event_t *event);
/**
* @brief Send a event to event task
*
* @attention 1. Other task/modules, such as the TCPIP module, can call this API to send an event to event task
*
* @param system_event_t * event : event
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_event_send(system_event_t *event);
/**
* @brief Default event handler for system events
*
* This function performs default handling of system events.
* When using esp_event_loop APIs, it is called automatically before invoking the user-provided
* callback function.
*
* Applications which implement a custom event loop must call this function
* as part of event processing.
*
* @param event pointer to event to be handled
* @return ESP_OK if an event was handled successfully
*/
esp_err_t esp_event_process_default(system_event_t *event);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_EVENT_H__ */

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tools/sdk/include/esp32/esp_event_loop.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_EVENT_LOOP_H__
#define __ESP_EVENT_LOOP_H__
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "esp_event.h"
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Application specified event callback function
*
* @param void *ctx : reserved for user
* @param system_event_t *event : event type defined in this file
*
* @return ESP_OK : succeed
* @return others : fail
*/
typedef esp_err_t (*system_event_cb_t)(void *ctx, system_event_t *event);
/**
* @brief Initialize event loop
* Create the event handler and task
*
* @param system_event_cb_t cb : application specified event callback, it can be modified by call esp_event_set_cb
* @param void *ctx : reserved for user
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_event_loop_init(system_event_cb_t cb, void *ctx);
/**
* @brief Set application specified event callback function
*
* @attention 1. If cb is NULL, means application don't need to handle
* If cb is not NULL, it will be call when an event is received, after the default event callback is completed
*
* @param system_event_cb_t cb : callback
* @param void *ctx : reserved for user
*
* @return system_event_cb_t : old callback
*/
system_event_cb_t esp_event_loop_set_cb(system_event_cb_t cb, void *ctx);
/**
* @brief Get the queue used by event loop
*
* @attention : currently this API is used to initialize "q" parameter
* of wifi_init structure.
*
* @return QueueHandle_t : event queue handle
*/
QueueHandle_t esp_event_loop_get_queue(void);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_EVENT_LOOP_H__ */

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tools/sdk/include/esp32/esp_intr.h Normal file
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_INTR_H__
#define __ESP_INTR_H__
#include "rom/ets_sys.h"
#include "freertos/xtensa_api.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ESP_CCOMPARE_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_CCOMPARE_INUM, (func), (void *)(arg))
#define ESP_EPWM_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_EPWM_INUM, (func), (void *)(arg))
#define ESP_MPWM_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_MPWM_INUM, (func), (void *)(arg))
#define ESP_SPI1_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SPI1_INUM, (func), (void *)(arg))
#define ESP_SPI2_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SPI2_INUM, (func), (void *)(arg))
#define ESP_SPI3_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SPI3_INUM, (func), (void *)(arg))
#define ESP_I2S0_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_I2S0_INUM, (func), (void *)(arg))
#define ESP_PCNT_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_PCNT_INUM, (func), (void *)(arg))
#define ESP_LEDC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_LEDC_INUM, (func), (void *)(arg))
#define ESP_WMAC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_WMAC_INUM, (func), (void *)(arg))
#define ESP_FRC_TIMER1_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_FRC_TIMER1_INUM, (func), (void *)(arg))
#define ESP_FRC_TIMER2_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_FRC_TIMER2_INUM, (func), (void *)(arg))
#define ESP_GPIO_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_GPIO_INUM, (func), (void *)(arg))
#define ESP_UART0_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_UART0_INUM, (func), (void *)(arg))
#define ESP_WDT_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_WDT_INUM, (func), (void *)(arg))
#define ESP_RTC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_RTC_INUM, (func), (void *)(arg))
#define ESP_SLC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SLC_INUM, (func), (void *)(arg))
#define ESP_RMT_CTRL_INTRL(func,arg)\
xt_set_interrupt_handler(ETS_RMT_CTRL_INUM, (func), (void *)(arg))
#define ESP_INTR_ENABLE(inum) \
xt_ints_on((1<<inum))
#define ESP_INTR_DISABLE(inum) \
xt_ints_off((1<<inum))
#define ESP_CCOMPARE_INTR_ENBALE() \
ESP_INTR_ENABLE(ETS_CCOMPARE_INUM)
#define ESP_CCOMPARE_INTR_DISBALE() \
ESP_INTR_DISABLE(ETS_CCOMPARE_INUM)
#define ESP_SPI1_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_SPI1_INUM)
#define ESP_SPI1_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_SPI1_INUM)
#define ESP_SPI2_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_SPI2_INUM)
#define ESP_PWM_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_PWM_INUM)
#define ESP_PWM_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_PWM_INUM)
#define ESP_SPI2_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_SPI2_INUM)
#define ESP_SPI3_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_SPI3_INUM)
#define ESP_SPI3_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_SPI3_INUM)
#define ESP_I2S0_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_I2S0_INUM)
#define ESP_I2S0_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_I2S0_INUM)
#define ESP_I2S1_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_I2S1_INUM)
#define ESP_I2S1_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_I2S1_INUM)
#define ESP_MPWM_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_MPWM_INUM)
#define ESP_EPWM_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_EPWM_INUM)
#define ESP_MPWM_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_MPWM_INUM)
#define ESP_EPWM_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_EPWM_INUM)
#define ESP_BB_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_BB_INUM)
#define ESP_BB_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_BB_INUM)
#define ESP_UART0_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_UART0_INUM)
#define ESP_UART0_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_UART0_INUM)
#define ESP_LEDC_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_LEDC_INUM)
#define ESP_LEDC_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_LEDC_INUM)
#define ESP_GPIO_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_GPIO_INUM)
#define ESP_GPIO_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_GPIO_INUM)
#define ESP_WDT_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_WDT_INUM)
#define ESP_WDT_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_WDT_INUM)
#define ESP_FRC1_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_FRC_TIMER1_INUM)
#define ESP_FRC1_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_FRC_TIMER1_INUM)
#define ESP_FRC2_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_FRC_TIMER2_INUM)
#define ESP_FRC2_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_FRC_TIMER2_INUM)
#define ESP_RTC_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_RTC_INUM)
#define ESP_RTC_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_RTC_INUM)
#define ESP_SLC_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_SLC_INUM)
#define ESP_SLC_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_SLC_INUM)
#define ESP_PCNT_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_PCNT_INUM)
#define ESP_PCNT_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_PCNT_INUM)
#define ESP_RMT_CTRL_ENABLE() \
ESP_INTR_ENABLE(ETS_RMT_CTRL_INUM)
#define ESP_RMT_CTRL_DIABLE() \
ESP_INTR_DISABLE(ETS_RMT_CTRL_INUM)
#ifdef __cplusplus
}
#endif
#endif /* __ESP_INTR_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_IPC_H__
#define __ESP_IPC_H__
#include <esp_err.h>
typedef void (*esp_ipc_func_t)(void* arg);
/**
* @brief Inter-processor call APIs
*
* FreeRTOS provides several APIs which can be used to communicate between
* different tasks, including tasks running on different CPUs.
* This module provides additional APIs to run some code on the other CPU.
*
* These APIs can only be used when FreeRTOS scheduler is running.
*/
/**
* @brief Initialize inter-processor call module.
*
* This function start two tasks, one on each CPU. These tasks are started
* with high priority. These tasks are normally inactive, waiting until one of
* the esp_ipc_call_* functions to be used. One of these tasks will be
* woken up to execute the callback provided to esp_ipc_call_nonblocking or
* esp_ipc_call_blocking.
*/
void esp_ipc_init();
/**
* @brief Execute function on the given CPU
*
* This will wake a high-priority task on CPU indicated by cpu_id argument,
* and run func(arg) in the context of that task.
* This function returns as soon as the high-priority task is woken up.
* If another IPC call is already being executed, this function will also wait
* for it to complete.
*
* In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1.
*
* @param cpu_id CPU where function should be executed (0 or 1)
* @param func pointer to a function which should be executed
* @param arg arbitrary argument to be passed into function
*
* @return ESP_ERR_INVALID_ARG if cpu_id is invalid
* ESP_ERR_INVALID_STATE if FreeRTOS scheduler is not running
* ESP_OK otherwise
*/
esp_err_t esp_ipc_call(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
/**
* @brief Execute function on the given CPU and wait for it to finish
*
* This will wake a high-priority task on CPU indicated by cpu_id argument,
* and run func(arg) in the context of that task.
* This function waits for func to return.
*
* In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1.
*
* @param cpu_id CPU where function should be executed (0 or 1)
* @param func pointer to a function which should be executed
* @param arg arbitrary argument to be passed into function
*
* @return ESP_ERR_INVALID_ARG if cpu_id is invalid
* ESP_ERR_INVALID_STATE if FreeRTOS scheduler is not running
* ESP_OK otherwise
*/
esp_err_t esp_ipc_call_blocking(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
#endif /* __ESP_IPC_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_SMARTCONFIG_H__
#define __ESP_SMARTCONFIG_H__
#include <stdint.h>
#include <esp_types.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SC_STATUS_WAIT = 0, /**< waiting, do not start connection in this phase */
SC_STATUS_FIND_CHANNEL, /**< find target channel, start connection by APP in this phase */
SC_STATUS_GETTING_SSID_PSWD, /**< getting SSID and password of target AP */
SC_STATUS_LINK, /**< connecting to target AP */
SC_STATUS_LINK_OVER, /**< got IP, connect to AP successfully */
} smartconfig_status_t;
typedef enum {
SC_TYPE_ESPTOUCH = 0, /**< protocol: ESPTouch */
SC_TYPE_AIRKISS, /**< protocol: AirKiss */
SC_TYPE_ESPTOUCH_AIRKISS, /**< protocol: ESPTouch and AirKiss */
} smartconfig_type_t;
/**
* @brief The callback of SmartConfig, executed when smart-config status changed.
*
* @param smartconfig_status_t status : status of SmartConfig:
* - if status == SC_STATUS_GETTING_SSID_PSWD, parameter void *pdata is a pointer
of smartconfig_type_t, means SmartConfig type: AirKiss or ESP-TOUCH.
* - if status == SC_STATUS_LINK, parameter void *pdata is a pointer of struct station_config;
* - if status == SC_STATUS_LINK_OVER, parameter void *pdata is a pointer of mobile
* phone's IP address, 4 bytes. This is only available in ESPTOUCH, otherwise,
* it is NULL.
* - otherwise, parameter void *pdata is NULL.
* @param void *pdata : data of SmartConfig
*
* @return null
*/
typedef void (*sc_callback_t)(smartconfig_status_t status, void *pdata);
/**
* @brief Get the version of SmartConfig.
*
* @param null
*
* @return SmartConfig version
*/
const char *esp_smartconfig_get_version(void);
/**
* @brief Start SmartConfig mode.
*
* Start SmartConfig mode, to connect ESP32 station to AP, by sniffing
* for special packets from the air, containing SSID and password of desired AP.
* You need to broadcast the SSID and password (e.g. from mobile device or computer)
* with the SSID and password encoded.
*
* @attention 1. This API can only be called in station mode.
* @attention 2. During SmartConfig, ESP32 station and soft-AP are disabled.
* @attention 3. Can not call esp_smartconfig_start twice before it finish, please call
* esp_smartconfig_stop first.
* @attention 4. Don't call any other APIs during SmartConfig, please call esp_smartconfig_stop first.
*
* @param sc_callback_t cb : SmartConfig callback; executed when SmartConfig status changed;
* @param uint8 log : 1, UART output logs; otherwise, UART only outputs the result.
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_smartconfig_start(sc_callback_t cb, ...);
/**
* @brief Stop SmartConfig, free the buffer taken by esp_smartconfig_start.
*
* @attention Whether connect to AP succeed or not, this API should be called to free
* memory taken by smartconfig_start.
*
* @param null
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_smartconfig_stop(void);
/**
* @brief Set timeout of SmartConfig.
*
* @attention SmartConfig timeout start at SC_STATUS_FIND_CHANNEL, SmartConfig will
* restart if timeout.
*
* @param uint8 time_s : range 15s~255s, offset:45s.
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_esptouch_set_timeout(uint8_t time_s);
/**
* @brief Set protocol type of SmartConfig.
*
* @attention If users need to set the SmartConfig type, please set it before calling
* esp_smartconfig_start.
*
* @param smartconfig_type_t type : AirKiss, ESP-TOUCH or both.
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_smartconfig_set_type(smartconfig_type_t type);
/**
* @brief Set mode of SmartConfig. default normal mode.
*
* @attention If users need to set the SmartConfig mode, please set it before calling
* esp_smartconfig_start. Different mode should match different APP(phone).
*
* @param bool enable : false-disable(default); true-enable;
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_smartconfig_fast_mode(bool enable);
#ifdef __cplusplus
}
#endif
#endif

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_SSC_H__
#define __ESP_SSC_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define CMD_T_ASYNC 0x01
#define CMD_T_SYNC 0x02
typedef struct cmd_s {
char *cmd_str;
uint8_t flag;
uint8_t id;
void (* cmd_func)(void);
void (* cmd_callback)(void *arg);
} ssc_cmd_t;
#define MAX_LINE_N 127
typedef enum {
SSC_BR_9600 = 9600,
SSC_BR_19200 = 19200,
SSC_BR_38400 = 38400,
SSC_BR_57600 = 57600,
SSC_BR_74880 = 74880,
SSC_BR_115200 = 115200,
SSC_BR_230400 = 230400,
SSC_BR_460800 = 460800,
SSC_BR_921600 = 921600
} SscBaudRate;
/** \defgroup SSC_APIs SSC APIs
* @brief SSC APIs
*
* SSC means simple serial command.
* SSC APIs allows users to define their own command, users can refer to spiffs_test/test_main.c.
*
*/
/** @addtogroup SSC_APIs
* @{
*/
/**
* @brief Initial the ssc function.
*
* @attention param is no use, just compatible with ESP8266, default bandrate is 115200
*
* @param SscBaudRate bandrate : baud rate
*
* @return null
*/
void ssc_attach(SscBaudRate bandrate);
/**
* @brief Get the length of the simple serial command.
*
* @param null
*
* @return length of the command.
*/
int ssc_param_len(void);
/**
* @brief Get the simple serial command string.
*
* @param null
*
* @return the command.
*/
char *ssc_param_str(void);
/**
* @brief Parse the simple serial command (ssc).
*
* @param char *pLine : [input] the ssc string
* @param char *argv[] : [output] parameters of the ssc
*
* @return the number of parameters.
*/
int ssc_parse_param(char *pLine, char *argv[]);
/**
* @brief Register the user-defined simple serial command (ssc) set.
*
* @param ssc_cmd_t *cmdset : the ssc set
* @param uint8 cmdnum : number of commands
* @param void (* help)(void) : callback of user-guide
*
* @return null
*/
void ssc_register(ssc_cmd_t *cmdset, uint8_t cmdnum, void (* help)(void));
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ESP_SSC_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_SYSTEM_H__
#define __ESP_SYSTEM_H__
#include <stdint.h>
#include "esp_err.h"
#include "esp_deepsleep.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup System_APIs System APIs
* @brief System APIs
*/
/** @addtogroup System_APIs
* @{
*/
/**
* @brief Get information of the SDK version.
*
* @param null
*
* @return Information of the SDK version.
*/
const char *system_get_sdk_version(void);
/**
* @brief Reset to default settings.
*
* Reset to default settings of the following APIs : wifi_station_set_auto_connect,
* wifi_set_phy_mode, wifi_softap_set_config related, wifi_station_set_config
* related, and wifi_set_opmode.
*
* @param null
*
* @return null
*/
void system_restore(void);
/**
* @brief Restart system.
*
* @param null
*
* @return null
*/
void system_restart(void);
/**
* @brief Get system time, unit: microsecond.
*
* @param null
*
* @return System time, unit: microsecond.
*/
uint32_t system_get_time(void);
/**
* @brief Get the size of available heap.
*
* @param null
*
* @return Available heap size.
*/
uint32_t system_get_free_heap_size(void);
/**
* @brief Get RTC time, unit: RTC clock cycle.
*
* @param null
*
* @return RTC time.
*/
uint64_t system_get_rtc_time(void);
/**
* @brief Read user data from the RTC memory.
*
* The user data segment (1024 bytes, as shown below) is used to store user data.
*
* |<---- system data(512 bytes) ---->|<----------- user data(1024 bytes) --------->|
*
* @attention Read and write unit for data stored in the RTC memory is 4 bytes.
* @attention src_addr is the block number (4 bytes per block). So when reading data
* at the beginning of the user data segment, src_addr will be 512/4 = 128,
* n will be data length.
*
* @param uint16 src : source address of rtc memory, src_addr >= 128
* @param void *dst : data pointer
* @param uint16 n : data length, unit: byte
*
* @return true : succeed
* @return false : fail
*/
bool system_rtc_mem_read(uint16_t src, void *dst, uint16_t n);
/**
* @brief Write user data to the RTC memory.
*
* During deep-sleep, only RTC is working. So users can store their data
* in RTC memory if it is needed. The user data segment below (1024 bytes)
* is used to store the user data.
*
* |<---- system data(512 bytes) ---->|<----------- user data(1024 bytes) --------->|
*
* @attention Read and write unit for data stored in the RTC memory is 4 bytes.
* @attention src_addr is the block number (4 bytes per block). So when storing data
* at the beginning of the user data segment, src_addr will be 512/4 = 128,
* n will be data length.
*
* @param uint16 src : source address of rtc memory, src_addr >= 128
* @param void *dst : data pointer
* @param uint16 n : data length, unit: byte
*
* @return true : succeed
* @return false : fail
*/
bool system_rtc_mem_write(uint16_t dst, const void *src, uint16_t n);
/** \defgroup System_boot_APIs Boot APIs
* @brief boot APIs
*/
/** @addtogroup System_boot_APIs
* @{
*/
/**
* @}
*/
/** \defgroup Hardware_MAC_APIs Hardware MAC APIs
* @brief Hardware MAC address APIs
*
* In WiFi MAC, only ESP32 station MAC is the hardware MAC, ESP32 softAP MAC is a software MAC
* calculated from ESP32 station MAC.
* So users need to call wifi_get_macaddr to query the ESP32 softAP MAC if ESP32 station MAC changed.
*
*/
/** @addtogroup Hardware_MAC_APIs
* @{
*/
/**
* @brief Read hardware MAC address.
*
* @param uint8 mac[6] : the hardware MAC address, length: 6 bytes.
*
* @return esp_err_t
*/
esp_err_t system_efuse_read_mac(uint8_t mac[6]);
void system_init(void);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ESP_SYSTEM_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/* Notes:
* 1. Put all task priority and stack size definition in this file
* 2. If the task priority is less than 10, use ESP_TASK_PRIO_MIN + X style,
* otherwise use ESP_TASK_PRIO_MAX - X style
* 3. If this is a daemon task, the macro prefix is ESP_TASKD_, otherwise
* it's ESP_TASK_
* 4. If the configMAX_PRIORITIES is modified, please make all priority are
* greater than 0
* 5. Make sure esp_task.h is consistent between wifi lib and idf
*/
#ifndef _ESP_TASK_H_
#define _ESP_TASK_H_
#include "sdkconfig.h"
#define ESP_TASK_PRIO_MAX (configMAX_PRIORITIES)
#define ESP_TASK_PRIO_MIN (0)
/* Wifi library task */
#define ESP_TASKD_WATCHDOG_PRIO (ESP_TASK_PRIO_MAX - 1)
#define ESP_TASKD_WATCHDOG_STACK 2048
#define ESP_TASK_WPA2_PRIO (ESP_TASK_PRIO_MAX - 1)
#define ESP_TASK_WPA2_STACK 2048
#define ESP_TASKD_WIFI_PRIO (ESP_TASK_PRIO_MAX - 2)
#define ESP_TASKD_WIFI_STACK 8196
#define ESP_TASKD_WIFI_TIMER_PRIO (ESP_TASK_PRIO_MAX - 3)
#define ESP_TASKD_WIFI_TIMER_STACK 2048
#define ESP_TASK_WPS_PRIO (ESP_TASK_PRIO_MIN + 2)
#define ESP_TASK_WPS_STACK 2048
/* Bt contoller Task */
/* controller */
#define ESP_TASK_BT_CONTROLLER_PRIO (ESP_TASK_PRIO_MAX - 1)
#define ESP_TASK_BT_CONTROLLER_STACK 4096
/* idf task */
#define ESP_TASKD_EVENT_PRIO (ESP_TASK_PRIO_MAX - 5)
#define ESP_TASKD_EVENT_STACK CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE
#define ESP_TASK_TCPIP_PRIO (ESP_TASK_PRIO_MAX - 7)
#define ESP_TASK_TCPIP_STACK 2048
#define ESP_TASK_MAIN_PRIO (ESP_TASK_PRIO_MIN + 1)
#define ESP_TASK_MAIN_STACK CONFIG_MAIN_TASK_STACK_SIZE
#endif

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_TYPES_H__
#define __ESP_TYPES_H__
#ifdef __GNUC__
#include <sys/cdefs.h>
#endif /*__GNUC__*/
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#define __ATTRIB_PACK __attribute__ ((packed))
#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2)))
#define __ATTRIB_NORETURN __attribute__ ((noreturn))
#define __ATTRIB_ALIGN(x) __attribute__ ((aligned((x))))
#define INLINE __inline__
#define LOCAL static
/* probably should not put STATUS here */
typedef enum {
OK = 0,
FAIL,
PENDING,
BUSY,
CANCEL,
} STATUS;
//#define _LITTLE_ENDIAN 1234
//#define _BYTE_ORDER == _LITTLE_ENDIAN
#define ASSERT( x ) do { \
if (!(x)) { \
printf("%s %u\n", __FILE__, __LINE__); \
while (1) { \
asm volatile("nop"); \
}; \
} \
} while (0)
/* #if __GNUC_PREREQ__(4, 1) */
#ifndef __GNUC__
#if 1
#define __offsetof(type, field) __builtin_offsetof(type, field)
#else
#define __offsetof(type, field) ((size_t)(&((type *)0)->field))
#endif
#endif /* __GNUC__ */
/* Macros for counting and rounding. */
#ifndef howmany
#define howmany(x, y) (((x)+((y)-1))/(y))
#endif
#define container_of(ptr, type, member) ({ \
const typeof( ((type *)0)->member ) *__mptr = (ptr); \
(type *)( (char *)__mptr - __offsetof(type,member) );})
#endif /* __ESP_TYPES_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/* Notes about WiFi Programming
*
* The esp32 WiFi programming model can be depicted as following picture:
*
*
* default handler user handler
* ------------- --------------- ---------------
* | | event | | callback or | |
* | tcpip | ---------> | event | ----------> | application |
* | stack | | task | event | task |
* |-----------| |-------------| |-------------|
* /|\ |
* | |
* event | |
* | |
* | |
* --------------- |
* | | |
* | WiFi Driver |/__________________|
* | |\ API call
* | |
* |-------------|
*
* The WiFi driver can be consider as black box, it knows nothing about the high layer code, such as
* TCPIP stack, application task, event task etc, all it can do is to receive API call from high layer
* or post event queue to a specified Queue, which is initialized by API esp_wifi_init().
*
* The event task is a daemon task, which receives events from WiFi driver or from other subsystem, such
* as TCPIP stack, event task will call the default callback function on receiving the event. For example,
* on receiving event SYSTEM_EVENT_STA_CONNECTED, it will call tcpip_adapter_start() to start the DHCP
* client in it's default handler.
*
* Application can register it's own event callback function by API esp_event_init, then the application callback
* function will be called after the default callback. Also, if application doesn't want to execute the callback
* in the event task, what it needs to do is to post the related event to application task in the application callback function.
*
* The application task (code) generally mixes all these thing together, it calls APIs to init the system/WiFi and
* handle the events when necessary.
*
*/
#ifndef __ESP_WIFI_H__
#define __ESP_WIFI_H__
#include <stdint.h>
#include <stdbool.h>
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#include "rom/queue.h"
#include "esp_err.h"
#include "esp_wifi_types.h"
#include "esp_event.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
system_event_handler_t event_handler; /**< WiFi event handler */
} wifi_init_config_t;
#define WIFI_INIT_CONFIG_DEFAULT() { \
.event_handler = &esp_event_send, \
};
/**
* @brief Init WiFi
* Alloc resource for WiFi driver, such as WiFi control structure, RX/TX buffer,
* WiFi NVS structure etc, this WiFi also start WiFi task
*
* @attention 1. This API must be called before all other WiFi API can be called
* @attention 2. Generally we should init event_q in *config, WiFi driver will post the event
* to this queue when event happens, such as, when station connects to WiFi, WiFi driver
* will post station connected event to this queue. If the queue is not initialized, WiFi
* will not post any events
*
* @param wifi_init_config_t *config : provide WiFi init configuration
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_init(wifi_init_config_t *config);
/**
* @brief Deinit WiFi
* Free all resource allocated in esp_wifi_init and stop WiFi task
*
* @attention 1. This API should be called if you want to remove WiFi driver from the system
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_deinit(void);
/**
* @brief Set the WiFi operating mode
*
* Set the WiFi operating mode as station, soft-AP or station+soft-AP,
* The default mode is soft-AP mode.
*
* @param wifi_mode_t mode : WiFi operating modes:
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_mode(wifi_mode_t mode);
/**
* @brief Get current operating mode of WiFi
*
* @param wifi_mode_t *mode : store current WiFi mode
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_mode(wifi_mode_t *mode);
/**
* @brief Start WiFi according to current configuration
* If mode is WIFI_MODE_STA, it create station control block and start station
* If mode is WIFI_MODE_AP, it create soft-AP control block and start soft-AP
* If mode is WIFI_MODE_APSTA, it create soft-AP and station control block and start soft-AP and station
*
* @param null
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_start(void);
/**
* @brief Stop WiFi
If mode is WIFI_MODE_STA, it stop station and free station control block
* If mode is WIFI_MODE_AP, it stop soft-AP and free soft-AP control block
* If mode is WIFI_MODE_APSTA, it stop station/soft-AP and free station/soft-AP control block
*
* @param null
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_stop(void);
/**
* @brief Connect the ESP32 WiFi station to the AP.
*
* @attention 1. This API only impact WIFI_MODE_STA or WIFI_MODE_APSTA mode
* @attention 2. If the ESP32 is connected to an AP, call esp_wifi_disconnect to disconnect.
*
* @param null
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_connect(void);
/**
* @brief Disconnect the ESP32 WiFi station from the AP.
*
* @param null
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_disconnect(void);
/**
* @brief Currently this API is just an stub API
*
* @param null
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_clear_fast_connect(void);
/**
* @brief Kick the all station or associated id equals to aid
*
* @param uint16_t aid : when aid is 0, kick all stations, otherwise kick station whose associated id is aid
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_kick_station(uint16_t aid);
/**
* @brief Scan all available APs.
*
* @attention If this API is called, the found APs are stored in WiFi driver dynamic allocated memory and the
* will be freed in esp_wifi_get_ap_list, so generally, call esp_wifi_get_ap_list to cause
* the memory to be freed once the scan is done
*
* @param struct scan_config *config : configuration of scanning
* @param bool block : if block is true, this API will block the caller until the scan is done, otherwise
* it will return immediately
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_scan_start(wifi_scan_config_t *conf, bool block);
/**
* @brief Stop the scan in process
*
* @param null
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_scan_stop(void);
/**
* @brief Get number of APs found in last scan
*
* @param uint16_t *number : store number of APIs found in last scan
*
* @attention This API can only be called when the scan is completed, otherwise it may get wrong value
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_ap_num(uint16_t *number);
/**
* @brief Get AP list found in last scan
*
* @param uint16_t *number : as input param, it stores max AP number ap_list can hold, as output param, it store
the actual AP number this API returns
* @param wifi_ap_list_t *ap_list : a list to hold the found APs
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_ap_list(uint16_t *number, wifi_ap_list_t *ap_list);
/**
* @brief Set current power save type
*
* @param wifi_ps_type_t type : power save type
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_ps(wifi_ps_type_t type);
/**
* @brief Get current power save type
*
* @param wifi_ps_type_t *type : store current power save type
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_ps(wifi_ps_type_t *type);
/**
* @brief Set protocol type of specified interface
* The default protocol is (WIFI_PROTOCOL_11B|WIFI_PROTOCOL_11G|WIFI_PROTOCOL_11N)
*
* @attention Currently we only support 802.11b or 802.11bg or 802.11bgn mode
*
* @param wifi_interface_t ifx : interfaces
* @param uint8_t protocol : WiFi protocol bitmap
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_protocol(wifi_interface_t ifx, uint8_t protocol_bitmap);
/**
* @brief Get the current protocol bitmap of specified ifx
*
* @param wifi_interface_t ifx : interfaces
* @param uint8_t protocol : store current WiFi protocol bitmap of interface ifx
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_protocol(wifi_interface_t ifx, uint8_t *protocol_bitmap);
/**
* @brief Set the bandwidth of ESP32 specified interface
*
* @attention 1. API return false if try to configure a interface that is not enable
* @attention 2. WIFI_BW_HT40 is supported only when the interface support 11N
*
* @param wifi_interface_t ifx : interface to be configured
* @param wifi_bandwidth_t bw : bandwidth
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_bandwidth(wifi_interface_t ifx, wifi_bandwidth_t bw);
/**
* @brief Get the bandwidth of ESP32 specified interface
*
* @attention 1. API return false if try to get a interface that is not enable
*
* @param wifi_interface_t ifx : interface to be configured
* @param wifi_bandwidth_t *bw : store bandwidth of interface ifx
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_bandwidth(wifi_interface_t ifx, wifi_bandwidth_t *bw);
/**
* @brief Set primary/second channel of ESP32
*
* @attention 1. This is a special API for sniffer
*
* @param uint8_t primary : for HT20, primary is the channel number, for HT40, primary is the primary channel
* @param wifi_second_chan_t second : for HT20, second is ignored, for HT40, second is the second channel
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_channel(uint8_t primary, wifi_second_chan_t second);
/**
* @brief Get the primary/second channel of ESP32
*
* @attention 1. API return false if try to get a interface that is not enable
*
* @param uint8_t *primary : store current primary channel
* @param wifi_second_chan_t *second : store current second channel
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_channel(uint8_t *primary, wifi_second_chan_t *second);
/**
* @brief Set country code
* The default value is WIFI_COUNTRY_CN
*
* @param wifi_country_t country : country type
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_country(wifi_country_t country);
/**
* @brief Get country code
*
* @param wifi_country_t country : store current country
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_country(wifi_country_t *country);
/**
* @brief Set MAC address of the ESP32 WiFi station or the soft-AP interface.
*
* @attention 1. This API can only be called when the interface is disabled
* @attention 2. ESP32 soft-AP and station have different MAC addresses, do not set them to be the same.
* - The bit0 of the first byte of ESP32 MAC address can not be 1. For example, the MAC address
* can set to be "1a:XX:XX:XX:XX:XX", but can not be "15:XX:XX:XX:XX:XX".
*
* @param wifi_interface_t ifx : interface
* @param uint8 mac[6]: the MAC address.
*
* @return true : succeed
* @return false : fail
*/
esp_err_t esp_wifi_set_mac(wifi_interface_t ifx, uint8_t mac[6]);
/**
* @brief Get mac of specified interface
*
* @param uint8_t mac[6] : store mac of this interface ifx
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_mac(wifi_interface_t ifx, uint8_t mac[6]);
/**
* @brief The RX callback function in the promiscuous mode.
*
* Each time a packet is received, the callback function will be called.
*
* @param void *buf : the data received
* @param uint16_t len : data length
*
* @return ESP_OK : succeed
* @return others : fail
*/
typedef void (* wifi_promiscuous_cb_t)(void *buf, uint16_t len);
/**
* @brief Register the RX callback function in the promiscuous mode.
*
* Each time a packet is received, the registered callback function will be called.
*
* @param wifi_promiscuous_cb_t cb : callback
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_promiscuous_rx_cb(wifi_promiscuous_cb_t cb);
/**
* @brief Enable the promiscuous mode.
*
* @param bool promiscuous : false - disable / true - enable
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_promiscuous(bool en);
/**
* @brief Get the promiscuous mode.
*
* @param bool *enable : store the current status of promiscuous mode
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_promiscuous(bool *en);
/**
* @brief Set the configuration of the ESP32 STA or AP
*
* @attention 1. This API can be called only when specified interface is enabled, otherwise, API fail
* @attention 2. For station configuration, bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.
* @attention 3. ESP32 is limited to only one channel, so when in the soft-AP+station mode, the soft-AP will adjust its channel automatically to be the same as
* the channel of the ESP32 station.
*
* @param wifi_interface_t ifx : interface
* @param wifi_config_t *conf : station or soft-AP configuration
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_config(wifi_interface_t ifx, wifi_config_t *conf);
/**
* @brief Get configuration of specified interface
*
* @param wifi_interface_t ifx : interface
* @param wifi_config_t *conf : station or soft-AP configuration
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_config(wifi_interface_t ifx, wifi_config_t *conf);
/**
* @brief Get STAs associated with soft-AP
*
* @attention SSC only API
*
* @param struct station_info **station : station list
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_station_list(struct station_info **station);
esp_err_t esp_wifi_free_station_list(void);
/**
* @brief Set the WiFi API configuration storage type
*
* @attention 1. The default value is WIFI_STORAGE_FLASH
*
* @param wifi_storage_t storage : storage type
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_storage(wifi_storage_t storage);
/**
* @brief The WiFi RX callback function
*
* Each time the WiFi need to forward the packets to high layer, the callback function will be called
*
*/
typedef esp_err_t (*wifi_rxcb_t)(void *buffer, uint16_t len, void *eb);
/**
* @brief Set the WiFi RX callback
*
* @attention 1. Currently we support only one RX callback for each interface
*
* @param wifi_interface_t ifx : interface
* @param wifi_rxcb_t fn : WiFi RX callback
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_reg_rxcb(wifi_interface_t ifx, wifi_rxcb_t fn);
/**
* @brief Set auto connect
* The default value is true
*
* @attention 1.
*
* @param bool en : true - enable auto connect / false - disable auto connect
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_auto_connect(bool en);
/**
* @brief Get the auto connect flag
*
* @param bool *en : store current auto connect configuration
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_auto_connect(bool *en);
/**
* @brief Set vendor specific element
*
* @param bool enable : enable or not
* @param wifi_vendor_ie_type_t type : 0 - WIFI_VND_IE_TYPE_BEACON
* 1 - WIFI_VND_IE_TYPE_PROBE_REQ
* 2 - WIFI_VND_IE_TYPE_PROBE_RESP
* 3 - WIFI_VND_IE_TYPE_ASSOC_REQ
* 4 - WIFI_VND_IE_TYPE_ASSOC_RESP
* @param wifi_vendor_ie_id_t idx : 0 - WIFI_VND_IE_ID_0
1 - WIFI_VND_IE_ID_1
* @param uint8_t *vnd_ie : pointer to a vendor specific element
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_vendor_ie(bool enable, wifi_vendor_ie_type_t type, wifi_vendor_ie_id_t idx, uint8_t *vnd_ie);
/**
* @brief Define function pointer for vendor specific element callback
* @param void *ctx : reserved
* @param wifi_vendor_ie_type_t type : 0 - WIFI_VND_IE_TYPE_BEACON
* 1 - WIFI_VND_IE_TYPE_PROBE_REQ
* 2 - WIFI_VND_IE_TYPE_PROBE_RESP
* 3 - WIFI_VND_IE_TYPE_ASSOC_REQ
* 4 - WIFI_VND_IE_TYPE_ASSOC_RESP
* @param const uint8_t sa[6] : source address
* @param const uint8_t *vnd_ie : pointer to a vendor specific element
* @param int rssi : received signal strength indication
*/
typedef void (*esp_vendor_ie_cb_t) (void *ctx, wifi_vendor_ie_type_t type, const uint8_t sa[6], const uint8_t *vnd_ie, int rssi);
/**
* @brief Set vendor specific element callback
*
* @param esp_vendor_ie_cb_t cb : callback function
* @param void *ctx : reserved
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_vendor_ie_cb(esp_vendor_ie_cb_t cb, void *ctx);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_WIFI_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_WIFI_TYPES_H__
#define __ESP_WIFI_TYPES_H__
#include <stdint.h>
#include <stdbool.h>
#include "rom/queue.h"
#include "esp_err.h"
#include "esp_wifi_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WIFI_MODE_NULL = 0, /**< null mode */
WIFI_MODE_STA, /**< WiFi station mode */
WIFI_MODE_AP, /**< WiFi soft-AP mode */
WIFI_MODE_APSTA, /**< WiFi station + soft-AP mode */
WIFI_MODE_MAX
} wifi_mode_t;
typedef enum {
WIFI_IF_STA = 0, /**< ESP32 station interface */
WIFI_IF_AP, /**< ESP32 soft-AP interface */
WIFI_IF_MAX
} wifi_interface_t;
typedef enum {
WIFI_COUNTRY_CN = 0, /**< country China, channel range [1, 14] */
WIFI_COUNTRY_JP, /**< country Japan, channel range [1, 14] */
WIFI_COUNTRY_US, /**< country USA, channel range [1, 11] */
WIFI_COUNTRY_EU, /**< country Europe, channel range [1, 13] */
WIFI_COUNTRY_MAX
} wifi_country_t;
typedef enum {
WIFI_AUTH_OPEN = 0, /**< authenticate mode : open */
WIFI_AUTH_WEP, /**< authenticate mode : WEP */
WIFI_AUTH_WPA_PSK, /**< authenticate mode : WPA_PSK */
WIFI_AUTH_WPA2_PSK, /**< authenticate mode : WPA2_PSK */
WIFI_AUTH_WPA_WPA2_PSK, /**< authenticate mode : WPA_WPA2_PSK */
WIFI_AUTH_MAX
} wifi_auth_mode_t;
enum {
WIFI_REASON_UNSPECIFIED = 1,
WIFI_REASON_AUTH_EXPIRE = 2,
WIFI_REASON_AUTH_LEAVE = 3,
WIFI_REASON_ASSOC_EXPIRE = 4,
WIFI_REASON_ASSOC_TOOMANY = 5,
WIFI_REASON_NOT_AUTHED = 6,
WIFI_REASON_NOT_ASSOCED = 7,
WIFI_REASON_ASSOC_LEAVE = 8,
WIFI_REASON_ASSOC_NOT_AUTHED = 9,
WIFI_REASON_DISASSOC_PWRCAP_BAD = 10,
WIFI_REASON_DISASSOC_SUPCHAN_BAD = 11,
WIFI_REASON_IE_INVALID = 13,
WIFI_REASON_MIC_FAILURE = 14,
WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,
WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT = 16,
WIFI_REASON_IE_IN_4WAY_DIFFERS = 17,
WIFI_REASON_GROUP_CIPHER_INVALID = 18,
WIFI_REASON_PAIRWISE_CIPHER_INVALID = 19,
WIFI_REASON_AKMP_INVALID = 20,
WIFI_REASON_UNSUPP_RSN_IE_VERSION = 21,
WIFI_REASON_INVALID_RSN_IE_CAP = 22,
WIFI_REASON_802_1X_AUTH_FAILED = 23,
WIFI_REASON_CIPHER_SUITE_REJECTED = 24,
WIFI_REASON_BEACON_TIMEOUT = 200,
WIFI_REASON_NO_AP_FOUND = 201,
WIFI_REASON_AUTH_FAIL = 202,
WIFI_REASON_ASSOC_FAIL = 203,
WIFI_REASON_HANDSHAKE_TIMEOUT = 204,
};
typedef enum {
WIFI_SECOND_CHAN_NONE = 0, /**< the channel width is HT20 */
WIFI_SECOND_CHAN_ABOVE, /**< the channel width is HT40 and the second channel is above the primary channel */
WIFI_SECOND_CHAN_BELOW, /**< the channel width is HT40 and the second channel is below the primary channel */
} wifi_second_chan_t;
typedef struct {
char *ssid; /**< SSID of AP */
uint8_t *bssid; /**< MAC address of AP */
uint8_t channel; /**< channel, scan the specific channel */
bool show_hidden; /**< enable to scan AP whose SSID is hidden */
} wifi_scan_config_t;
typedef struct {
uint8_t bssid[6]; /**< MAC address of AP */
uint8_t ssid[32]; /**< SSID of AP */
uint8_t primary; /**< channel of AP */
wifi_second_chan_t second; /**< second channel of AP */
int8_t rssi; /**< signal strength of AP */
wifi_auth_mode_t authmode; /**< authmode of AP */
} wifi_ap_list_t;
typedef enum {
WIFI_PS_NONE, /**< No power save */
WIFI_PS_MODEM, /**< Modem power save */
WIFI_PS_LIGHT, /**< Light power save */
WIFI_PS_MAC, /**< MAC power save */
} wifi_ps_type_t;
#define WIFI_PROTOCOL_11B 1
#define WIFI_PROTOCOL_11G 2
#define WIFI_PROTOCOL_11N 4
typedef enum {
WIFI_BW_HT20 = 0, /* Bandwidth is HT20 */
WIFI_BW_HT40, /* Bandwidth is HT40 */
} wifi_bandwidth_t;
typedef struct {
char ssid[32]; /**< SSID of ESP32 soft-AP */
char password[64]; /**< Password of ESP32 soft-AP */
uint8_t ssid_len; /**< Length of SSID. If softap_config.ssid_len==0, check the SSID until there is a termination character; otherwise, set the SSID length according to softap_config.ssid_len. */
uint8_t channel; /**< Channel of ESP32 soft-AP */
wifi_auth_mode_t authmode; /**< Auth mode of ESP32 soft-AP. Do not support AUTH_WEP in soft-AP mode */
uint8_t ssid_hidden; /**< Broadcast SSID or not, default 0, broadcast the SSID */
uint8_t max_connection; /**< Max number of stations allowed to connect in, default 4, max 4 */
uint16_t beacon_interval; /**< Beacon interval, 100 ~ 60000 ms, default 100 ms */
} wifi_ap_config_t;
typedef struct {
char ssid[32]; /**< SSID of target AP*/
char password[64]; /**< password of target AP*/
bool bssid_set; /**< whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/
uint8_t bssid[6]; /**< MAC address of target AP*/
} wifi_sta_config_t;
typedef union {
wifi_ap_config_t ap; /**< configuration of AP */
wifi_sta_config_t sta; /**< configuration of STA */
} wifi_config_t;
struct station_info {
STAILQ_ENTRY(station_info) next;
uint8_t bssid[6];
};
typedef enum {
WIFI_STORAGE_FLASH, /**< all configuration will strore in both memory and flash */
WIFI_STORAGE_RAM, /**< all configuration will only store in the memory */
} wifi_storage_t;
/**
* @brief Vendor IE type
*
*/
typedef enum {
WIFI_VND_IE_TYPE_BEACON,
WIFI_VND_IE_TYPE_PROBE_REQ,
WIFI_VND_IE_TYPE_PROBE_RESP,
WIFI_VND_IE_TYPE_ASSOC_REQ,
WIFI_VND_IE_TYPE_ASSOC_RESP,
} wifi_vendor_ie_type_t;
/**
* @brief Vendor IE index
*
*/
typedef enum {
WIFI_VND_IE_ID_0,
WIFI_VND_IE_ID_1,
} wifi_vendor_ie_id_t;
#ifdef __cplusplus
}
#endif
#endif /* __ESP_WIFI_TYPES_H__ */

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/**
* \brief AES block cipher, ESP32 hardware accelerated version
* Based on mbedTLS FIPS-197 compliant version.
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*
*/
#ifndef ESP_AES_H
#define ESP_AES_H
#include "esp_types.h"
#include "rom/aes.h"
#ifdef __cplusplus
extern "C" {
#endif
/* padlock.c and aesni.c rely on these values! */
#define ESP_AES_ENCRYPT 1
#define ESP_AES_DECRYPT 0
#define ERR_ESP_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */
#define ERR_ESP_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */
typedef struct {
enum AES_BITS aesbits;
uint8_t key[32];
} key_context, KEY_CTX;
/**
* \brief AES context structure
*
* \note buf is able to hold 32 extra bytes, which can be used:
* - for alignment purposes if VIA padlock is used, and/or
* - to simplify key expansion in the 256-bit case by
* generating an extra round key
*/
typedef struct {
int nr; /*!< number of rounds */
uint32_t *rk; /*!< AES round keys */
KEY_CTX enc;
KEY_CTX dec;
} esp_aes_context;
/**
* \brief Lock access to AES hardware unit
*
* AES hardware unit can only be used by one
* consumer at a time.
*
* esp_aes_xxx API calls automatically manage locking & unlocking of
* hardware, this function is only needed if you want to call
* ets_aes_xxx functions directly.
*/
void esp_aes_acquire_hardware( void );
/**
* \brief Unlock access to AES hardware unit
*
* esp_aes_xxx API calls automatically manage locking & unlocking of
* hardware, this function is only needed if you want to call
* ets_aes_xxx functions directly.
*/
void esp_aes_release_hardware( void );
/**
* \brief Initialize AES context
*
* \param ctx AES context to be initialized
*/
void esp_aes_init( esp_aes_context *ctx );
/**
* \brief Clear AES context
*
* \param ctx AES context to be cleared
*/
void esp_aes_free( esp_aes_context *ctx );
/**
* \brief AES key schedule (encryption)
*
* \param ctx AES context to be initialized
* \param key encryption key
* \param keybits must be 128, 192 or 256
*
* \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH
*/
int esp_aes_setkey_enc( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits );
/**
* \brief AES key schedule (decryption)
*
* \param ctx AES context to be initialized
* \param key decryption key
* \param keybits must be 128, 192 or 256
*
* \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH
*/
int esp_aes_setkey_dec( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits );
/**
* \brief AES-ECB block encryption/decryption
*
* \param ctx AES context
* \param mode AES_ENCRYPT or AES_DECRYPT
* \param input 16-byte input block
* \param output 16-byte output block
*
* \return 0 if successful
*/
int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] );
/**
* \brief AES-CBC buffer encryption/decryption
* Length should be a multiple of the block
* size (16 bytes)
*
* \note Upon exit, the content of the IV is updated so that you can
* call the function same function again on the following
* block(s) of data and get the same result as if it was
* encrypted in one call. This allows a "streaming" usage.
* If on the other hand you need to retain the contents of the
* IV, you should either save it manually or use the cipher
* module instead.
*
* \param ctx AES context
* \param mode AES_ENCRYPT or AES_DECRYPT
* \param length length of the input data
* \param iv initialization vector (updated after use)
* \param input buffer holding the input data
* \param output buffer holding the output data
*
* \return 0 if successful, or ERR_AES_INVALID_INPUT_LENGTH
*/
int esp_aes_crypt_cbc( esp_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
/**
* \brief AES-CFB128 buffer encryption/decryption.
*
* Note: Due to the nature of CFB you should use the same key schedule for
* both encryption and decryption. So a context initialized with
* esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
*
* \note Upon exit, the content of the IV is updated so that you can
* call the function same function again on the following
* block(s) of data and get the same result as if it was
* encrypted in one call. This allows a "streaming" usage.
* If on the other hand you need to retain the contents of the
* IV, you should either save it manually or use the cipher
* module instead.
*
* \param ctx AES context
* \param mode AES_ENCRYPT or AES_DECRYPT
* \param length length of the input data
* \param iv_off offset in IV (updated after use)
* \param iv initialization vector (updated after use)
* \param input buffer holding the input data
* \param output buffer holding the output data
*
* \return 0 if successful
*/
int esp_aes_crypt_cfb128( esp_aes_context *ctx,
int mode,
size_t length,
size_t *iv_off,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
/**
* \brief AES-CFB8 buffer encryption/decryption.
*
* Note: Due to the nature of CFB you should use the same key schedule for
* both encryption and decryption. So a context initialized with
* esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
*
* \note Upon exit, the content of the IV is updated so that you can
* call the function same function again on the following
* block(s) of data and get the same result as if it was
* encrypted in one call. This allows a "streaming" usage.
* If on the other hand you need to retain the contents of the
* IV, you should either save it manually or use the cipher
* module instead.
*
* \param ctx AES context
* \param mode AES_ENCRYPT or AES_DECRYPT
* \param length length of the input data
* \param iv initialization vector (updated after use)
* \param input buffer holding the input data
* \param output buffer holding the output data
*
* \return 0 if successful
*/
int esp_aes_crypt_cfb8( esp_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
/**
* \brief AES-CTR buffer encryption/decryption
*
* Warning: You have to keep the maximum use of your counter in mind!
*
* Note: Due to the nature of CTR you should use the same key schedule for
* both encryption and decryption. So a context initialized with
* esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
*
* \param ctx AES context
* \param length The length of the data
* \param nc_off The offset in the current stream_block (for resuming
* within current cipher stream). The offset pointer to
* should be 0 at the start of a stream.
* \param nonce_counter The 128-bit nonce and counter.
* \param stream_block The saved stream-block for resuming. Is overwritten
* by the function.
* \param input The input data stream
* \param output The output data stream
*
* \return 0 if successful
*/
int esp_aes_crypt_ctr( esp_aes_context *ctx,
size_t length,
size_t *nc_off,
unsigned char nonce_counter[16],
unsigned char stream_block[16],
const unsigned char *input,
unsigned char *output );
/**
* \brief Internal AES block encryption function
* (Only exposed to allow overriding it,
* see AES_ENCRYPT_ALT)
*
* \param ctx AES context
* \param input Plaintext block
* \param output Output (ciphertext) block
*/
void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] );
/**
* \brief Internal AES block decryption function
* (Only exposed to allow overriding it,
* see AES_DECRYPT_ALT)
*
* \param ctx AES context
* \param input Ciphertext block
* \param output Output (plaintext) block
*/
void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] );
#ifdef __cplusplus
}
#endif
#endif /* aes.h */

250
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/*
* ESP32 hardware accelerated SHA1/256/512 implementation
* based on mbedTLS FIPS-197 compliant version.
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#ifndef _ESP_SHA_H_
#define _ESP_SHA_H_
#include "rom/sha.h"
#include "esp_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief SHA-1 context structure
*/
typedef struct {
/* both types defined in rom/sha.h */
SHA_CTX context;
enum SHA_TYPE context_type;
} esp_sha_context;
/**
* \brief Lock access to SHA hardware unit
*
* SHA hardware unit can only be used by one
* consumer at a time.
*
* esp_sha_xxx API calls automatically manage locking & unlocking of
* hardware, this function is only needed if you want to call
* ets_sha_xxx functions directly.
*/
void esp_sha_acquire_hardware( void );
/**
* \brief Unlock access to SHA hardware unit
*
* esp_sha_xxx API calls automatically manage locking & unlocking of
* hardware, this function is only needed if you want to call
* ets_sha_xxx functions directly.
*/
void esp_sha_release_hardware( void );
/**
* \brief Initialize SHA-1 context
*
* \param ctx SHA-1 context to be initialized
*/
void esp_sha1_init( esp_sha_context *ctx );
/**
* \brief Clear SHA-1 context
*
* \param ctx SHA-1 context to be cleared
*/
void esp_sha1_free( esp_sha_context *ctx );
/**
* \brief Clone (the state of) a SHA-1 context
*
* \param dst The destination context
* \param src The context to be cloned
*/
void esp_sha1_clone( esp_sha_context *dst, const esp_sha_context *src );
/**
* \brief SHA-1 context setup
*
* \param ctx context to be initialized
*/
void esp_sha1_start( esp_sha_context *ctx );
/**
* \brief SHA-1 process buffer
*
* \param ctx SHA-1 context
* \param input buffer holding the data
* \param ilen length of the input data
*/
void esp_sha1_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen );
/**
* \brief SHA-1 final digest
*
* \param ctx SHA-1 context
* \param output SHA-1 checksum result
*/
void esp_sha1_finish( esp_sha_context *ctx, unsigned char output[20] );
/**
* \brief Calculate SHA-1 of input buffer
*
* \param input buffer holding the data
* \param ilen length of the input data
* \param output SHA-1 checksum result
*/
void esp_sha1( const unsigned char *input, size_t ilen, unsigned char output[20] );
/**
* \brief SHA-256 context structure
*/
/**
* \brief Initialize SHA-256 context
*
* \param ctx SHA-256 context to be initialized
*/
void esp_sha256_init( esp_sha_context *ctx );
/**
* \brief Clear SHA-256 context
*
* \param ctx SHA-256 context to be cleared
*/
void esp_sha256_free( esp_sha_context *ctx );
/**
* \brief Clone (the state of) a SHA-256 context
*
* \param dst The destination context
* \param src The context to be cloned
*/
void esp_sha256_clone( esp_sha_context *dst, const esp_sha_context *src );
/**
* \brief SHA-256 context setup
*
* \param ctx context to be initialized
* \param is224 0 = use SHA256, 1 = use SHA224
*/
void esp_sha256_start( esp_sha_context *ctx, int is224 );
/**
* \brief SHA-256 process buffer
*
* \param ctx SHA-256 context
* \param input buffer holding the data
* \param ilen length of the input data
*/
void esp_sha256_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen );
/**
* \brief SHA-256 final digest
*
* \param ctx SHA-256 context
* \param output SHA-224/256 checksum result
*/
void esp_sha256_finish( esp_sha_context *ctx, unsigned char output[32] );
/**
* \brief Calculate SHA-256 of input buffer
*
* \param input buffer holding the data
* \param ilen length of the input data
* \param output SHA-224/256 checksum result
* \param is224 0 = use SHA256, 1 = use SHA224
*/
void esp_sha256( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 );
//
/**
* \brief SHA-512 context structure
*/
/**
* \brief Initialize SHA-512 context
*
* \param ctx SHA-512 context to be initialized
*/
void esp_sha512_init( esp_sha_context *ctx );
/**
* \brief Clear SHA-512 context
*
* \param ctx SHA-512 context to be cleared
*/
void esp_sha512_free( esp_sha_context *ctx );
/**
* \brief Clone (the state of) a SHA-512 context
*
* \param dst The destination context
* \param src The context to be cloned
*/
void esp_sha512_clone( esp_sha_context *dst, const esp_sha_context *src );
/**
* \brief SHA-512 context setup
*
* \param ctx context to be initialized
* \param is384 0 = use SHA512, 1 = use SHA384
*/
void esp_sha512_start( esp_sha_context *ctx, int is384 );
/**
* \brief SHA-512 process buffer
*
* \param ctx SHA-512 context
* \param input buffer holding the data
* \param ilen length of the input data
*/
void esp_sha512_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen );
/**
* \brief SHA-512 final digest
*
* \param ctx SHA-512 context
* \param output SHA-384/512 checksum result
*/
void esp_sha512_finish( esp_sha_context *ctx, unsigned char output[64] );
/**
* \brief Calculate SHA-512 of input buffer.
*
* \param input buffer holding the data
* \param ilen length of the input data
* \param output SHA-384/512 checksum result
* \param is384 0 = use SHA512, 1 = use SHA384
*/
void esp_sha512( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 );
//
#ifdef __cplusplus
}
#endif
#endif

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/*
ROM functions for hardware AES support.
It is not recommended to use these functions directly,
use the wrapper functions in hwcrypto/aes.h instead.
*/
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_AES_H_
#define _ROM_AES_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
//TODO, add comment for aes apis
enum AES_BITS {
AES128,
AES192,
AES256
};
void ets_aes_enable(void);
void ets_aes_disable(void);
void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap,
bool in_word_swap, bool in_byte_swap,
bool out_word_swap, bool out_byte_swap);
bool ets_aes_setkey_enc(const uint8_t *key, enum AES_BITS bits);
bool ets_aes_setkey_dec(const uint8_t *key, enum AES_BITS bits);
void ets_aes_crypt(const uint8_t input[16], uint8_t output[16]);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_AES_H_ */

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/*
ROM functions for hardware bigint support.
It is not recommended to use these functions directly,
use the wrapper functions in hwcrypto/mpi.h instead.
*/
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_BIGINT_H_
#define _ROM_BIGINT_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
//TODO: add comment here
void ets_bigint_enable(void);
void ets_bigint_disable(void);
void ets_bigint_wait_finish(void);
bool ets_bigint_mod_power_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
bool ets_bigint_mod_power_getz(uint32_t *z, uint32_t len);
bool ets_bigint_mult_prepare(uint32_t *x, uint32_t *y, uint32_t len);
bool ets_bigint_mult_getz(uint32_t *z, uint32_t len);
bool ets_bigint_montgomery_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
uint32_t m_dash, uint32_t len, bool again);
bool ets_bigint_montgomery_mult_getz(uint32_t *z, uint32_t len);
bool ets_bigint_mod_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
bool ets_bigint_mod_mult_getz(uint32_t *m, uint32_t *z, uint32_t len);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_BIGINT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_CACHE_H_
#define _ROM_CACHE_H_
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
/**
* @brief Initialise cache mmu, mark all entries as invalid.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void mmu_init(int cpu_no);
/**
* @brief Set Flash-Cache mmu mapping.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
*
* @param int pod : process identifier. Range 0~7.
*
* @param unsigned int vaddr : virtual address in CPU address space.
* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
* Should be aligned by psize.
*
* @param unsigned int paddr : physical address in Flash.
* Should be aligned by psize.
*
* @param int psize : page size of flash, in kilobytes. Should be 64 here.
*
* @param int num : pages to be set.
*
* @return unsigned int: error status
* 0 : mmu set success
* 1 : vaddr or paddr is not aligned
* 2 : pid error
* 3 : psize error
* 4 : mmu table to be written is out of range
* 5 : vaddr is out of range
*/
unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
/**
* @brief Set Ext-SRAM-Cache mmu mapping.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
*
* @param int pod : process identifier. Range 0~7.
*
* @param unsigned int vaddr : virtual address in CPU address space.
* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
* Should be aligned by psize.
*
* @param unsigned int paddr : physical address in Ext-SRAM.
* Should be aligned by psize.
*
* @param int psize : page size of flash, in kilobytes. Should be 32 here.
*
* @param int num : pages to be set.
*
* @return unsigned int: error status
* 0 : mmu set success
* 1 : vaddr or paddr is not aligned
* 2 : pid error
* 3 : psize error
* 4 : mmu table to be written is out of range
* 5 : vaddr is out of range
*/
unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
/**
* @brief Initialise cache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void Cache_Read_Init(int cpu_no);
/**
* @brief Flush the cache value for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void Cache_Flush(int cpu_no);
/**
* @brief Disable Cache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void Cache_Read_Disable(int cpu_no);
/**
* @brief Enable Cache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void Cache_Read_Enable(int cpu_no);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_CACHE_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef ROM_CRC_H
#define ROM_CRC_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
/* Standard CRC8/16/32 algorithms. */
// CRC-8 x8+x2+x1+1 0x07
// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS
// CRC32:
//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
//If your buf is not continuous, you can use the first result to be the second parameter.
/**
* @brief Crc32 value that is in little endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc32 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc16 value that is in little endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc16 value that is in big endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc8 value that is in little endian.
*
* @param uint8_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc8 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_EFUSE_H_
#define _ROM_EFUSE_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup efuse_APIs efuse APIs
* @brief ESP32 efuse read/write APIs
* @attention
*
*/
/** @addtogroup efuse_APIs
* @{
*/
/**
* @brief Do a efuse read operation, to update the efuse value to efuse read registers.
*
* @param null
*
* @return null
*/
void ets_efuse_read_op(void);
/**
* @brief Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again.
*
* @param null
*
* @return null
*/
void ets_efuse_program_op(void);
/**
* @brief Read 8M Analog Clock value(8 bit) in efuse, the analog clock will not change with temperature.
* It can be used to test the external xtal frequency, do not touch this efuse field.
*
* @param null
*
* @return u32: 1 for 100KHZ, range is 0 to 255.
*/
uint32_t ets_efuse_get_8M_clock(void);
/**
* @brief Read spi pad configuration, show gpio number of flash pad, includes 5 pads.
*
* @param null
*
* @return uint32_t: 0, invalid, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*/
uint32_t ets_efuse_get_spiconfig(void);
#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0
#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6
#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12
#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18
#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24
#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
/**
* @brief A crc8 algorithm used in efuse check.
*
* @param unsigned char const *p : Pointer to original data.
*
* @param unsigned int len : Data length in byte.
*
* @return unsigned char: Crc value.
*/
unsigned char esp_crc8(unsigned char const *p, unsigned int len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_EFUSE_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_ETS_SYS_H_
#define _ROM_ETS_SYS_H_
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup ets_sys_apis, ets system related apis
* @brief ets system apis
*/
/** @addtogroup ets_sys_apis
* @{
*/
/************************************************************************
* NOTE
* Many functions in this header files can't be run in FreeRTOS.
* Please see the comment of the Functions.
* There are also some functions that doesn't work on FreeRTOS
* without listed in the header, such as:
* xtos functions start with "_xtos_" in ld file.
*
***********************************************************************
*/
/** \defgroup ets_apis, Espressif Task Scheduler related apis
* @brief ets apis
*/
/** @addtogroup ets_apis
* @{
*/
typedef enum {
ETS_OK = 0, /**< return successful in ets*/
ETS_FAILED = 1 /**< return failed in ets*/
} ETS_STATUS;
typedef uint32_t ETSSignal;
typedef uint32_t ETSParam;
typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/
struct ETSEventTag {
ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/
ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/
};
typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/
typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/
/**
* @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it.
*
* @param none
*
* @return none
*/
void ets_run(void);
/**
* @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep.
*
* @param ets_idle_cb_t func : The callback function.
*
* @param void *arg : Argument of the callback.
*
* @return None
*/
void ets_set_idle_cb(ets_idle_cb_t func, void *arg);
/**
* @brief Init a task with processer, priority, queue to receive Event, queue length.
*
* @param ETSTask task : The task processer.
*
* @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task.
*
* @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used.
*
* @param uint8_t qlen : Queue length.
*
* @return None
*/
void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen);
/**
* @brief Post an event to an Task.
*
* @param uint8_t prio : Priority of the Task.
*
* @param ETSSignal sig : Event signal.
*
* @param ETSParam par : Event parameter
*
* @return ETS_OK : post successful
* @return ETS_FAILED : post failed
*/
ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
/**
* @}
*/
/** \defgroup ets_boot_apis, Boot routing related apis
* @brief ets boot apis
*/
/** @addtogroup ets_apis
* @{
*/
extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/
/**
* @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
* When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
*
* @param uint32_t start : the PRO Entry code address value in uint32_t
*
* @return None
*/
void ets_set_user_start(uint32_t start);
/**
* @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code.
* When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run.
*
* @param uint32_t callback : the Startup code address value in uint32_t
*
* @return None : post successful
*/
void ets_set_startup_callback(uint32_t callback);
/**
* @brief Set App cpu Entry code, code can be called in PRO CPU.
* When APP booting is completed, APP CPU will call the Entry code if not NULL.
*
* @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D.
*
* @return None
*/
void ets_set_appcpu_boot_addr(uint32_t start);
/**
* @brief unpack the image in flash to iram and dram, no using cache.
*
* @param uint32_t pos : Flash physical address.
*
* @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
*
* @param bool jump : Jump into the code in the function or not.
*
* @param bool config : Config the flash when unpacking the image, config should be done only once.
*
* @return ETS_OK : unpack successful
* @return ETS_FAILED : unpack failed
*/
ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config);
/**
* @brief unpack the image in flash to iram and dram, using cache, maybe decrypting.
*
* @param uint32_t pos : Flash physical address.
*
* @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
*
* @param bool jump : Jump into the code in the function or not.
*
* @param bool sb_need_check : Do security boot check or not.
*
* @param bool config : Config the flash when unpacking the image, config should be done only once.
*
* @return ETS_OK : unpack successful
* @return ETS_FAILED : unpack failed
*/
ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config);
/**
* @}
*/
/** \defgroup ets_printf_apis, ets_printf related apis used in ets
* @brief ets printf apis
*/
/** @addtogroup ets_printf_apis
* @{
*/
/**
* @brief Printf the strings to uart or other devices, similar with printf, simple than printf.
* Can not print float point data format, or longlong data format.
* So we maybe only use this in ROM.
*
* @param const char *fmt : See printf.
*
* @param ... : See printf.
*
* @return int : the length printed to the output device.
*/
int ets_printf(const char *fmt, ...);
/**
* @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
* Can not print float point data format, or longlong data format
*
* @param char c : char to output.
*
* @return None
*/
void ets_write_char_uart(char c);
/**
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
* To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
*
* @param void (*)(char) p: Output function to install.
*
* @return None
*/
void ets_install_putc1(void (*p)(char c));
/**
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
* To install putc2, which is defaulted installed as NULL.
*
* @param void (*)(char) p: Output function to install.
*
* @return None
*/
void ets_install_putc2(void (*p)(char c));
/**
* @brief Install putc1 as ets_write_char_uart.
* In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
*
* @param None
*
* @return None
*/
void ets_install_uart_printf(void);
#define ETS_PRINTF(...) ets_printf(...)
#define ETS_ASSERT(v) do { \
if (!(v)) { \
ets_printf("%s %u \n", __FILE__, __LINE__); \
while (1) {}; \
} \
} while (0);
/**
* @}
*/
/** \defgroup ets_timer_apis, ets_timer related apis used in ets
* @brief ets timer apis
*/
/** @addtogroup ets_timer_apis
* @{
*/
typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
typedef struct _ETSTIMER_ {
struct _ETSTIMER_ *timer_next; /**< timer linker*/
uint32_t timer_expire; /**< abstruct time when timer expire*/
uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/
ETSTimerFunc *timer_func; /**< timer handler*/
void *timer_arg; /**< timer handler argument*/
} ETSTimer;
/**
* @brief Init ets timer, this timer range is 640 us to 429496 ms
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_timer_init(void);
/**
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param uint32_t tmout : Timer value in ms, range is 1 to 429496.
*
* @param bool repeat : Timer is periodic repeated.
*
* @return None
*/
void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
/**
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param uint32_t tmout : Timer value in us, range is 1 to 429496729.
*
* @param bool repeat : Timer is periodic repeated.
*
* @return None
*/
void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
/**
* @brief Disarm an ets timer.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @return None
*/
void ets_timer_disarm(ETSTimer *timer);
/**
* @brief Set timer callback and argument.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param ETSTimerFunc *pfunction : Timer callback.
*
* @param void *parg : Timer callback argument.
*
* @return None
*/
void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
/**
* @brief Unset timer callback and argument to NULL.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @return None
*/
void ets_timer_done(ETSTimer *ptimer);
/**
* @brief CPU do while loop for some time.
* In FreeRTOS task, please call FreeRTOS apis.
*
* @param uint32_t us : Delay time in us.
*
* @return None
*/
void ets_delay_us(uint32_t us);
/**
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
* Call this function when CPU frequency is changed.
*
* @param uint32_t ticks_per_us : CPU ticks per us.
*
* @return None
*/
void ets_update_cpu_frequency(uint32_t ticks_per_us);
/**
* @brief Get the real CPU ticks per us to the ets.
* This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
*
* @param None
*
* @return uint32_t : CPU ticks per us record in ets.
*/
uint32_t ets_get_cpu_frequency(void);
/**
* @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module.
*
* @param None
*
* @return uint32_t : xtal_freq/analog_8M*256.
*/
uint32_t ets_get_xtal_scale(void);
/**
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
*
* @param None
*
* @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
* clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
* else if analog_8M in efuse
* clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40;
* else clock = 26M.
*/
uint32_t ets_get_detected_xtal_freq(void);
/**
* @}
*/
/** \defgroup ets_intr_apis, ets interrupt configure related apis
* @brief ets intr apis
*/
/** @addtogroup ets_intr_apis
* @{
*/
typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
/**
* @brief Attach a interrupt handler to a CPU interrupt number.
* This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param int i : CPU interrupt number.
*
* @param ets_isr_t func : Interrupt handler.
*
* @param void *arg : argument of the handler.
*
* @return None
*/
void ets_isr_attach(int i, ets_isr_t func, void *arg);
/**
* @brief Mask the interrupts which show in mask bits.
* This function equals to _xtos_ints_off(mask).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
*
* @return None
*/
void ets_isr_mask(uint32_t mask);
/**
* @brief Unmask the interrupts which show in mask bits.
* This function equals to _xtos_ints_on(mask).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
*
* @return None
*/
void ets_isr_unmask(uint32_t unmask);
/**
* @brief Lock the interrupt to level 2.
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_intr_lock(void);
/**
* @brief Unlock the interrupt to level 0.
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_intr_unlock(void);
/**
* @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt).
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_waiti0(void);
/**
* @brief Attach an CPU interrupt to a hardware source.
* We have 4 steps to use an interrupt:
* 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
* 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
* 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);
* 4.Enable interrupt in the module.
*
* @param int cpu_no : The CPU which the interrupt number belongs.
*
* @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
*
* @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
*
* @return None
*/
void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
#define _ETSTR(v) # v
#define _ETS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \
__asm__ __volatile__( "rsil %0, " _ETSTR(intlevel) "\n" \
: "=a" (__tmp) : : "memory" ); \
})
#ifdef CONFIG_NONE_OS
#define ETS_INTR_LOCK() \
ets_intr_lock()
#define ETS_INTR_UNLOCK() \
ets_intr_unlock()
#define ETS_ISR_ATTACH \
ets_isr_attach
#define ETS_INTR_ENABLE(inum) \
ets_isr_unmask((1<<inum))
#define ETS_INTR_DISABLE(inum) \
ets_isr_mask((1<<inum))
#define ETS_WMAC_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_WMAC_INUM, (func), (void *)(arg))
#define ETS_TG0_T0_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_TG0_T0_INUM, (func), (void *)(arg))
#define ETS_GPIO_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_GPIO_INUM, (func), (void *)(arg))
#define ETS_UART0_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_UART0_INUM, (func), (void *)(arg))
#define ETS_WDT_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_WDT_INUM, (func), (void *)(arg))
#define ETS_SLC_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_SLC_INUM, (func), (void *)(arg))
#define ETS_BB_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_BB_INUM)
#define ETS_BB_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_BB_INUM)
#define ETS_UART0_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_UART0_INUM)
#define ETS_UART0_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_UART0_INUM)
#define ETS_GPIO_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_GPIO_INUM)
#define ETS_GPIO_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_GPIO_INUM)
#define ETS_WDT_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_WDT_INUM)
#define ETS_WDT_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_WDT_INUM)
#define ETS_TG0_T0_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_TG0_T0_INUM)
#define ETS_TG0_T0_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_TG0_T0_INUM)
#define ETS_SLC_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_SLC_INUM)
#define ETS_SLC_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_SLC_INUM)
#endif
/**
* @}
*/
#ifndef MAC2STR
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
#endif
#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_ETS_SYS_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_GPIO_H_
#define _ROM_GPIO_H_
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/gpio_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup gpio_apis, uart configuration and communication related apis
* @brief gpio apis
*/
/** @addtogroup gpio_apis
* @{
*/
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
#define GPIO_PIN_COUNT 40
#define GPIO_ID_PIN0 0
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
typedef enum {
GPIO_PIN_INTR_DISABLE = 0,
GPIO_PIN_INTR_POSEDGE = 1,
GPIO_PIN_INTR_NEGEDGE = 2,
GPIO_PIN_INTR_ANYEGDE = 3,
GPIO_PIN_INTR_LOLEVEL = 4,
GPIO_PIN_INTR_HILEVEL = 5
} GPIO_INT_TYPE;
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
((gpio_no < 32) ? gpio_output_set(bit_value<<gpio_no, (bit_value ? 0 : 1)<<gpio_no, 1<<gpio_no,0) : \
gpio_output_set_high(bit_value<<(gpio_no - 32), (bit_value ? 0 : 1)<<(gpio_no - 32), 1<<(gpio_no -32),0))
#define GPIO_DIS_OUTPUT(gpio_no) ((gpio_no < 32) ? gpio_output_set(0,0,0, 1<<gpio_no) : gpio_output_set_high(0,0,0, 1<<gpio_no))
#define GPIO_INPUT_GET(gpio_no) ((gpio_no < 32)? ((gpio_input_get()>>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0))
/* GPIO interrupt handler, registered through gpio_intr_handler_register */
typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg);
/**
* @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet
* to initialize "output enables" and pin configurations for each gpio pin.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void gpio_init(void);
/**
* @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
*
* @param uint32_t clear_mask : the gpios that need low level.
*
* @param uint32_t enable_mask : the gpios that need be changed.
*
* @param uint32_t disable_mask : the gpios that need diable output.
*
* @return None
*/
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
*
* @param uint32_t clear_mask : the gpios that need low level.
*
* @param uint32_t enable_mask : the gpios that need be changed.
*
* @param uint32_t disable_mask : the gpios that need diable output.
*
* @return None
*/
void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
*
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
*/
uint32_t gpio_input_get(void);
/**
* @brief Sample the value of GPIO input pins(32-39) and returns a bitmask.
*
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32.
*/
uint32_t gpio_input_get_high(void);
/**
* @brief Register an application-specific interrupt handler for GPIO pin interrupts.
* Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack.
* Please do not call this function in SDK.
*
* @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler
*
* @param void *arg : gpio application-specific interrupt handler argument.
*
* @return None
*/
void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg);
/**
* @brief Get gpio interrupts which happens but not processed.
* Please do not call this function in SDK.
*
* @param None
*
* @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0.
*/
uint32_t gpio_intr_pending(void);
/**
* @brief Get gpio interrupts which happens but not processed.
* Please do not call this function in SDK.
*
* @param None
*
* @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32.
*/
uint32_t gpio_intr_pending_high(void);
/**
* @brief Ack gpio interrupts to process pending interrupts.
* Please do not call this function in SDK.
*
* @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0.
*
* @return None
*/
void gpio_intr_ack(uint32_t ack_mask);
/**
* @brief Ack gpio interrupts to process pending interrupts.
* Please do not call this function in SDK.
*
* @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32.
*
* @return None
*/
void gpio_intr_ack_high(uint32_t ack_mask);
/**
* @brief Set GPIO to wakeup the ESP32.
* Please do not call this function in SDK.
*
* @param uint32_t i: gpio number.
*
* @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
*
* @return None
*/
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
/**
* @brief disable GPIOs to wakeup the ESP32.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~0x27
* gpio == 0x30, input 0 to signal
* gpio == 0x34, ???
* gpio == 0x38, input 1 to signal
*
* @param uint32_t signal_idx : signal index.
*
* @param bool inv : the signal is inv or not
*
* @return None
*/
void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~0x27
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x100, cancel output put to the gpio
*
* @param bool out_inv : the signal output is inv or not
*
* @param bool oen_inv : the signal output enable is inv or not
*
* @return None
*/
void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_select_gpio(uint8_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @param uint8_t drv : 0-3
*
* @return None
*/
void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_pullup(uint8_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_pulldown(uint8_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_unhold(uint8_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_hold(uint8_t gpio_num);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_GPIO_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_LIBC_STUBS_H_
#define _ROM_LIBC_STUBS_H_
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <stdarg.h>
#include <reent.h>
#include <errno.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32 ROM code contains implementations of some of C library functions.
Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
implementation defined in the following struct.
The table itself, by default, is not allocated in RAM. There are two pointers, `syscall_table_ptr_pro` and
`syscall_table_ptr_app`, which can be set to point to the locations of syscall tables of CPU 0 (aka PRO CPU)
and CPU 1 (aka APP CPU). Location of these pointers in .bss segment of ROM code is defined in linker script.
So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
application must allocate syscall table structure for each CPU being used, and populate it with pointers
to actual implementations of corresponding syscalls.
*/
struct syscall_stub_table
{
struct _reent* (*__getreent)(void);
void* (*_malloc_r)(struct _reent *r, size_t);
void (*_free_r)(struct _reent *r, void*);
void* (*_realloc_r)(struct _reent *r, void*, size_t);
void* (*_calloc_r)(struct _reent *r, size_t, size_t);
void (*_abort)(void);
int (*_system_r)(struct _reent *r, const char*);
int (*_rename_r)(struct _reent *r, const char*, const char*);
clock_t (*_times_r)(struct _reent *r, struct tms *);
int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
void (*_raise_r)(struct _reent *r);
int (*_unlink_r)(struct _reent *r, const char*);
int (*_link_r)(struct _reent *r, const char*, const char*);
int (*_stat_r)(struct _reent *r, const char*, struct stat *);
int (*_fstat_r)(struct _reent *r, int, struct stat *);
void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
int (*_getpid_r)(struct _reent *r);
int (*_kill_r)(struct _reent *r, int, int);
void (*_exit_r)(struct _reent *r, int);
int (*_close_r)(struct _reent *r, int);
int (*_open_r)(struct _reent *r, const char *, int, int);
int (*_write_r)(struct _reent *r, int, const void *, int);
int (*_lseek_r)(struct _reent *r, int, int, int);
int (*_read_r)(struct _reent *r, int, void *, int);
void (*_lock_init)(_lock_t *lock);
void (*_lock_init_recursive)(_lock_t *lock);
void (*_lock_close)(_lock_t *lock);
void (*_lock_close_recursive)(_lock_t *lock);
void (*_lock_acquire)(_lock_t *lock);
void (*_lock_acquire_recursive)(_lock_t *lock);
int (*_lock_try_acquire)(_lock_t *lock);
int (*_lock_try_acquire_recursive)(_lock_t *lock);
void (*_lock_release)(_lock_t *lock);
void (*_lock_release_recursive)(_lock_t *lock);
int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, _CONST char *, size_t len), va_list * ap);
int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
};
extern struct syscall_stub_table* syscall_table_ptr_pro;
extern struct syscall_stub_table* syscall_table_ptr_app;
#ifdef __cplusplus
} // extern "C"
#endif
#endif /* _ROM_LIBC_STUBS_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_LLDESC_H_
#define _ROM_LLDESC_H_
#include <stdint.h>
#include "queue.h"
#ifdef __cplusplus
extern "C" {
#endif
#define LLDESC_TX_MBLK_SIZE 268 /* */
#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */
#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/
#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/
#ifdef ESP_MAC_5
#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */
#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12
#else
#ifdef SBUF_RXTX
#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */
#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */
#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */
#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */
#endif
#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */
#ifdef IEEE80211_RX_AMPDU
#define LLDESC_RX_MBLK_NUM 30
#else
#define LLDESC_RX_MBLK_NUM 10
#endif /*IEEE80211_RX_AMPDU*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8
#endif /* !ESP_MAC_5 */
/*
* SLC2 DMA Desc struct, aka lldesc_t
*
* --------------------------------------------------------------
* | own | EoF | sub_sof | 5'b0 | length [11:0] | size [11:0] |
* --------------------------------------------------------------
* | buf_ptr [31:0] |
* --------------------------------------------------------------
* | next_desc_ptr [31:0] |
* --------------------------------------------------------------
*/
/* this bitfield is start from the LSB!!! */
typedef struct lldesc_s {
volatile uint32_t size :12,
length:12,
offset: 5, /* h/w reserved 5bit, s/w use it as offset in buffer */
sosf : 1, /* start of sub-frame */
eof : 1, /* end of frame */
owner : 1; /* hw or sw */
volatile uint8_t *buf; /* point to buffer data */
union{
volatile uint32_t empty;
STAILQ_ENTRY(lldesc_s) qe; /* pointing to the next desc */
};
} lldesc_t;
typedef struct tx_ampdu_entry_s{
uint32_t sub_len :12,
dili_num : 7,
: 1,
null_byte: 2,
data : 1,
enc : 1,
seq : 8;
} tx_ampdu_entry_t;
typedef struct lldesc_chain_s {
lldesc_t *head;
lldesc_t *tail;
} lldesc_chain_t;
#ifdef SBUF_RXTX
enum sbuf_mask_s {
SBUF_MOVE_NO = 0,
SBUF_MOVE_TX2RX,
SBUF_MOVE_RX2TX,
} ;
#define SBUF_MOVE_STEP 8
#endif
#define LLDESC_SIZE sizeof(struct lldesc_s)
/* SLC Descriptor */
#define LLDESC_OWNER_MASK 0x80000000
#define LLDESC_OWNER_SHIFT 31
#define LLDESC_SW_OWNED 0
#define LLDESC_HW_OWNED 1
#define LLDESC_EOF_MASK 0x40000000
#define LLDESC_EOF_SHIFT 30
#define LLDESC_SOSF_MASK 0x20000000
#define LLDESC_SOSF_SHIFT 29
#define LLDESC_LENGTH_MASK 0x00fff000
#define LLDESC_LENGTH_SHIFT 12
#define LLDESC_SIZE_MASK 0x00000fff
#define LLDESC_SIZE_SHIFT 0
#define LLDESC_ADDR_MASK 0x000fffff
void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t * mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner,
lldesc_t **head,
#ifdef TO_HOST_RESTART
lldesc_t ** one_before_tail,
#endif
lldesc_t **tail);
lldesc_t *lldesc_num2link(lldesc_t * head, uint16_t nblks);
lldesc_t *lldesc_set_owner(lldesc_t * head, uint16_t nblks, uint8_t owner);
static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
{
lldesc_t *ds = head;
uint32_t len = 0;
while (ds) {
len += ds->length;
ds = STAILQ_NEXT(ds, qe);
}
return len;
}
static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
{
ds->owner = owner;
ds->eof = eof;
ds->sosf = sosf;
ds->length = len;
}
#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \
(_desc)->owner = (_owner); \
(_desc)->eof = (_eof); \
(_desc)->sosf = (_sosf); \
(_desc)->length = (_len); \
} while(0)
#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
#ifdef __cplusplus
}
#endif
#endif /* _ROM_LLDESC_H_ */

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/*
* MD5 internal definitions
* Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Alternatively, this software may be distributed under the terms of BSD
* license.
*
* See README and COPYING for more details.
*/
#ifndef _ROM_MD5_HASH_H_
#define _ROM_MD5_HASH_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
struct MD5Context {
uint32_t buf[4];
uint32_t bits[2];
uint8_t in[64];
};
void MD5Init(struct MD5Context *context);
void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
void MD5Final(unsigned char digest[16], struct MD5Context *context);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_MD5_HASH_H_ */

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#ifndef MINIZ_HEADER_INCLUDED
#define MINIZ_HEADER_INCLUDED
#include <stdlib.h>
// Defines to completely disable specific portions of miniz.c:
// If all macros here are defined the only functionality remaining will be CRC-32, adler-32, tinfl, and tdefl.
// Define MINIZ_NO_STDIO to disable all usage and any functions which rely on stdio for file I/O.
#define MINIZ_NO_STDIO
// If MINIZ_NO_TIME is specified then the ZIP archive functions will not be able to get the current time, or
// get/set file times, and the C run-time funcs that get/set times won't be called.
// The current downside is the times written to your archives will be from 1979.
#define MINIZ_NO_TIME
// Define MINIZ_NO_ARCHIVE_APIS to disable all ZIP archive API's.
#define MINIZ_NO_ARCHIVE_APIS
// Define MINIZ_NO_ARCHIVE_APIS to disable all writing related ZIP archive API's.
#define MINIZ_NO_ARCHIVE_WRITING_APIS
// Define MINIZ_NO_ZLIB_APIS to remove all ZLIB-style compression/decompression API's.
#define MINIZ_NO_ZLIB_APIS
// Define MINIZ_NO_ZLIB_COMPATIBLE_NAME to disable zlib names, to prevent conflicts against stock zlib.
#define MINIZ_NO_ZLIB_COMPATIBLE_NAMES
// Define MINIZ_NO_MALLOC to disable all calls to malloc, free, and realloc.
// Note if MINIZ_NO_MALLOC is defined then the user must always provide custom user alloc/free/realloc
// callbacks to the zlib and archive API's, and a few stand-alone helper API's which don't provide custom user
// functions (such as tdefl_compress_mem_to_heap() and tinfl_decompress_mem_to_heap()) won't work.
#define MINIZ_NO_MALLOC
#if defined(__TINYC__) && (defined(__linux) || defined(__linux__))
// TODO: Work around "error: include file 'sys\utime.h' when compiling with tcc on Linux
#define MINIZ_NO_TIME
#endif
#if !defined(MINIZ_NO_TIME) && !defined(MINIZ_NO_ARCHIVE_APIS)
#include <time.h>
#endif
//Hardcoded options for Xtensa - JD
#define MINIZ_X86_OR_X64_CPU 0
#define MINIZ_LITTLE_ENDIAN 1
#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 0
#define MINIZ_HAS_64BIT_REGISTERS 0
#define TINFL_USE_64BIT_BITBUF 0
#if defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i486) || defined(i386) || defined(__ia64__) || defined(__x86_64__)
// MINIZ_X86_OR_X64_CPU is only used to help set the below macros.
#define MINIZ_X86_OR_X64_CPU 1
#endif
#if (__BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) || MINIZ_X86_OR_X64_CPU
// Set MINIZ_LITTLE_ENDIAN to 1 if the processor is little endian.
#define MINIZ_LITTLE_ENDIAN 1
#endif
#if MINIZ_X86_OR_X64_CPU
// Set MINIZ_USE_UNALIGNED_LOADS_AND_STORES to 1 on CPU's that permit efficient integer loads and stores from unaligned addresses.
#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 1
#endif
#if defined(_M_X64) || defined(_WIN64) || defined(__MINGW64__) || defined(_LP64) || defined(__LP64__) || defined(__ia64__) || defined(__x86_64__)
// Set MINIZ_HAS_64BIT_REGISTERS to 1 if operations on 64-bit integers are reasonably fast (and don't involve compiler generated calls to helper functions).
#define MINIZ_HAS_64BIT_REGISTERS 1
#endif
#ifdef __cplusplus
extern "C" {
#endif
// ------------------- zlib-style API Definitions.
// For more compatibility with zlib, miniz.c uses unsigned long for some parameters/struct members. Beware: mz_ulong can be either 32 or 64-bits!
typedef unsigned long mz_ulong;
// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap.
void mz_free(void *p);
#define MZ_ADLER32_INIT (1)
// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL.
mz_ulong mz_adler32(mz_ulong adler, const unsigned char *ptr, size_t buf_len);
#define MZ_CRC32_INIT (0)
// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL.
mz_ulong mz_crc32(mz_ulong crc, const unsigned char *ptr, size_t buf_len);
// Compression strategies.
enum { MZ_DEFAULT_STRATEGY = 0, MZ_FILTERED = 1, MZ_HUFFMAN_ONLY = 2, MZ_RLE = 3, MZ_FIXED = 4 };
// Method
#define MZ_DEFLATED 8
#ifndef MINIZ_NO_ZLIB_APIS
// Heap allocation callbacks.
// Note that mz_alloc_func parameter types purpsosely differ from zlib's: items/size is size_t, not unsigned long.
typedef void *(*mz_alloc_func)(void *opaque, size_t items, size_t size);
typedef void (*mz_free_func)(void *opaque, void *address);
typedef void *(*mz_realloc_func)(void *opaque, void *address, size_t items, size_t size);
#define MZ_VERSION "9.1.15"
#define MZ_VERNUM 0x91F0
#define MZ_VER_MAJOR 9
#define MZ_VER_MINOR 1
#define MZ_VER_REVISION 15
#define MZ_VER_SUBREVISION 0
// Flush values. For typical usage you only need MZ_NO_FLUSH and MZ_FINISH. The other values are for advanced use (refer to the zlib docs).
enum { MZ_NO_FLUSH = 0, MZ_PARTIAL_FLUSH = 1, MZ_SYNC_FLUSH = 2, MZ_FULL_FLUSH = 3, MZ_FINISH = 4, MZ_BLOCK = 5 };
// Return status codes. MZ_PARAM_ERROR is non-standard.
enum { MZ_OK = 0, MZ_STREAM_END = 1, MZ_NEED_DICT = 2, MZ_ERRNO = -1, MZ_STREAM_ERROR = -2, MZ_DATA_ERROR = -3, MZ_MEM_ERROR = -4, MZ_BUF_ERROR = -5, MZ_VERSION_ERROR = -6, MZ_PARAM_ERROR = -10000 };
// Compression levels: 0-9 are the standard zlib-style levels, 10 is best possible compression (not zlib compatible, and may be very slow), MZ_DEFAULT_COMPRESSION=MZ_DEFAULT_LEVEL.
enum { MZ_NO_COMPRESSION = 0, MZ_BEST_SPEED = 1, MZ_BEST_COMPRESSION = 9, MZ_UBER_COMPRESSION = 10, MZ_DEFAULT_LEVEL = 6, MZ_DEFAULT_COMPRESSION = -1 };
// Window bits
#define MZ_DEFAULT_WINDOW_BITS 15
struct mz_internal_state;
// Compression/decompression stream struct.
typedef struct mz_stream_s
{
const unsigned char *next_in; // pointer to next byte to read
unsigned int avail_in; // number of bytes available at next_in
mz_ulong total_in; // total number of bytes consumed so far
unsigned char *next_out; // pointer to next byte to write
unsigned int avail_out; // number of bytes that can be written to next_out
mz_ulong total_out; // total number of bytes produced so far
char *msg; // error msg (unused)
struct mz_internal_state *state; // internal state, allocated by zalloc/zfree
mz_alloc_func zalloc; // optional heap allocation function (defaults to malloc)
mz_free_func zfree; // optional heap free function (defaults to free)
void *opaque; // heap alloc function user pointer
int data_type; // data_type (unused)
mz_ulong adler; // adler32 of the source or uncompressed data
mz_ulong reserved; // not used
} mz_stream;
typedef mz_stream *mz_streamp;
// Returns the version string of miniz.c.
const char *mz_version(void);
// mz_deflateInit() initializes a compressor with default options:
// Parameters:
// pStream must point to an initialized mz_stream struct.
// level must be between [MZ_NO_COMPRESSION, MZ_BEST_COMPRESSION].
// level 1 enables a specially optimized compression function that's been optimized purely for performance, not ratio.
// (This special func. is currently only enabled when MINIZ_USE_UNALIGNED_LOADS_AND_STORES and MINIZ_LITTLE_ENDIAN are defined.)
// Return values:
// MZ_OK on success.
// MZ_STREAM_ERROR if the stream is bogus.
// MZ_PARAM_ERROR if the input parameters are bogus.
// MZ_MEM_ERROR on out of memory.
int mz_deflateInit(mz_streamp pStream, int level);
// mz_deflateInit2() is like mz_deflate(), except with more control:
// Additional parameters:
// method must be MZ_DEFLATED
// window_bits must be MZ_DEFAULT_WINDOW_BITS (to wrap the deflate stream with zlib header/adler-32 footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate/no header or footer)
// mem_level must be between [1, 9] (it's checked but ignored by miniz.c)
int mz_deflateInit2(mz_streamp pStream, int level, int method, int window_bits, int mem_level, int strategy);
// Quickly resets a compressor without having to reallocate anything. Same as calling mz_deflateEnd() followed by mz_deflateInit()/mz_deflateInit2().
int mz_deflateReset(mz_streamp pStream);
// mz_deflate() compresses the input to output, consuming as much of the input and producing as much output as possible.
// Parameters:
// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
// flush may be MZ_NO_FLUSH, MZ_PARTIAL_FLUSH/MZ_SYNC_FLUSH, MZ_FULL_FLUSH, or MZ_FINISH.
// Return values:
// MZ_OK on success (when flushing, or if more input is needed but not available, and/or there's more output to be written but the output buffer is full).
// MZ_STREAM_END if all input has been consumed and all output bytes have been written. Don't call mz_deflate() on the stream anymore.
// MZ_STREAM_ERROR if the stream is bogus.
// MZ_PARAM_ERROR if one of the parameters is invalid.
// MZ_BUF_ERROR if no forward progress is possible because the input and/or output buffers are empty. (Fill up the input buffer or free up some output space and try again.)
int mz_deflate(mz_streamp pStream, int flush);
// mz_deflateEnd() deinitializes a compressor:
// Return values:
// MZ_OK on success.
// MZ_STREAM_ERROR if the stream is bogus.
int mz_deflateEnd(mz_streamp pStream);
// mz_deflateBound() returns a (very) conservative upper bound on the amount of data that could be generated by deflate(), assuming flush is set to only MZ_NO_FLUSH or MZ_FINISH.
mz_ulong mz_deflateBound(mz_streamp pStream, mz_ulong source_len);
// Single-call compression functions mz_compress() and mz_compress2():
// Returns MZ_OK on success, or one of the error codes from mz_deflate() on failure.
int mz_compress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
int mz_compress2(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len, int level);
// mz_compressBound() returns a (very) conservative upper bound on the amount of data that could be generated by calling mz_compress().
mz_ulong mz_compressBound(mz_ulong source_len);
// Initializes a decompressor.
int mz_inflateInit(mz_streamp pStream);
// mz_inflateInit2() is like mz_inflateInit() with an additional option that controls the window size and whether or not the stream has been wrapped with a zlib header/footer:
// window_bits must be MZ_DEFAULT_WINDOW_BITS (to parse zlib header/footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate).
int mz_inflateInit2(mz_streamp pStream, int window_bits);
// Decompresses the input stream to the output, consuming only as much of the input as needed, and writing as much to the output as possible.
// Parameters:
// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
// flush may be MZ_NO_FLUSH, MZ_SYNC_FLUSH, or MZ_FINISH.
// On the first call, if flush is MZ_FINISH it's assumed the input and output buffers are both sized large enough to decompress the entire stream in a single call (this is slightly faster).
// MZ_FINISH implies that there are no more source bytes available beside what's already in the input buffer, and that the output buffer is large enough to hold the rest of the decompressed data.
// Return values:
// MZ_OK on success. Either more input is needed but not available, and/or there's more output to be written but the output buffer is full.
// MZ_STREAM_END if all needed input has been consumed and all output bytes have been written. For zlib streams, the adler-32 of the decompressed data has also been verified.
// MZ_STREAM_ERROR if the stream is bogus.
// MZ_DATA_ERROR if the deflate stream is invalid.
// MZ_PARAM_ERROR if one of the parameters is invalid.
// MZ_BUF_ERROR if no forward progress is possible because the input buffer is empty but the inflater needs more input to continue, or if the output buffer is not large enough. Call mz_inflate() again
// with more input data, or with more room in the output buffer (except when using single call decompression, described above).
int mz_inflate(mz_streamp pStream, int flush);
// Deinitializes a decompressor.
int mz_inflateEnd(mz_streamp pStream);
// Single-call decompression.
// Returns MZ_OK on success, or one of the error codes from mz_inflate() on failure.
int mz_uncompress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
// Returns a string description of the specified error code, or NULL if the error code is invalid.
const char *mz_error(int err);
// Redefine zlib-compatible names to miniz equivalents, so miniz.c can be used as a drop-in replacement for the subset of zlib that miniz.c supports.
// Define MINIZ_NO_ZLIB_COMPATIBLE_NAMES to disable zlib-compatibility if you use zlib in the same project.
#ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
typedef unsigned char Byte;
typedef unsigned int uInt;
typedef mz_ulong uLong;
typedef Byte Bytef;
typedef uInt uIntf;
typedef char charf;
typedef int intf;
typedef void *voidpf;
typedef uLong uLongf;
typedef void *voidp;
typedef void *const voidpc;
#define Z_NULL 0
#define Z_NO_FLUSH MZ_NO_FLUSH
#define Z_PARTIAL_FLUSH MZ_PARTIAL_FLUSH
#define Z_SYNC_FLUSH MZ_SYNC_FLUSH
#define Z_FULL_FLUSH MZ_FULL_FLUSH
#define Z_FINISH MZ_FINISH
#define Z_BLOCK MZ_BLOCK
#define Z_OK MZ_OK
#define Z_STREAM_END MZ_STREAM_END
#define Z_NEED_DICT MZ_NEED_DICT
#define Z_ERRNO MZ_ERRNO
#define Z_STREAM_ERROR MZ_STREAM_ERROR
#define Z_DATA_ERROR MZ_DATA_ERROR
#define Z_MEM_ERROR MZ_MEM_ERROR
#define Z_BUF_ERROR MZ_BUF_ERROR
#define Z_VERSION_ERROR MZ_VERSION_ERROR
#define Z_PARAM_ERROR MZ_PARAM_ERROR
#define Z_NO_COMPRESSION MZ_NO_COMPRESSION
#define Z_BEST_SPEED MZ_BEST_SPEED
#define Z_BEST_COMPRESSION MZ_BEST_COMPRESSION
#define Z_DEFAULT_COMPRESSION MZ_DEFAULT_COMPRESSION
#define Z_DEFAULT_STRATEGY MZ_DEFAULT_STRATEGY
#define Z_FILTERED MZ_FILTERED
#define Z_HUFFMAN_ONLY MZ_HUFFMAN_ONLY
#define Z_RLE MZ_RLE
#define Z_FIXED MZ_FIXED
#define Z_DEFLATED MZ_DEFLATED
#define Z_DEFAULT_WINDOW_BITS MZ_DEFAULT_WINDOW_BITS
#define alloc_func mz_alloc_func
#define free_func mz_free_func
#define internal_state mz_internal_state
#define z_stream mz_stream
#define deflateInit mz_deflateInit
#define deflateInit2 mz_deflateInit2
#define deflateReset mz_deflateReset
#define deflate mz_deflate
#define deflateEnd mz_deflateEnd
#define deflateBound mz_deflateBound
#define compress mz_compress
#define compress2 mz_compress2
#define compressBound mz_compressBound
#define inflateInit mz_inflateInit
#define inflateInit2 mz_inflateInit2
#define inflate mz_inflate
#define inflateEnd mz_inflateEnd
#define uncompress mz_uncompress
#define crc32 mz_crc32
#define adler32 mz_adler32
#define MAX_WBITS 15
#define MAX_MEM_LEVEL 9
#define zError mz_error
#define ZLIB_VERSION MZ_VERSION
#define ZLIB_VERNUM MZ_VERNUM
#define ZLIB_VER_MAJOR MZ_VER_MAJOR
#define ZLIB_VER_MINOR MZ_VER_MINOR
#define ZLIB_VER_REVISION MZ_VER_REVISION
#define ZLIB_VER_SUBREVISION MZ_VER_SUBREVISION
#define zlibVersion mz_version
#define zlib_version mz_version()
#endif // #ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
#endif // MINIZ_NO_ZLIB_APIS
// ------------------- Types and macros
typedef unsigned char mz_uint8;
typedef signed short mz_int16;
typedef unsigned short mz_uint16;
typedef unsigned int mz_uint32;
typedef unsigned int mz_uint;
typedef long long mz_int64;
typedef unsigned long long mz_uint64;
typedef int mz_bool;
#define MZ_FALSE (0)
#define MZ_TRUE (1)
// An attempt to work around MSVC's spammy "warning C4127: conditional expression is constant" message.
#ifdef _MSC_VER
#define MZ_MACRO_END while (0, 0)
#else
#define MZ_MACRO_END while (0)
#endif
// ------------------- ZIP archive reading/writing
#ifndef MINIZ_NO_ARCHIVE_APIS
enum
{
MZ_ZIP_MAX_IO_BUF_SIZE = 64*1024,
MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE = 260,
MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE = 256
};
typedef struct
{
mz_uint32 m_file_index;
mz_uint32 m_central_dir_ofs;
mz_uint16 m_version_made_by;
mz_uint16 m_version_needed;
mz_uint16 m_bit_flag;
mz_uint16 m_method;
#ifndef MINIZ_NO_TIME
time_t m_time;
#endif
mz_uint32 m_crc32;
mz_uint64 m_comp_size;
mz_uint64 m_uncomp_size;
mz_uint16 m_internal_attr;
mz_uint32 m_external_attr;
mz_uint64 m_local_header_ofs;
mz_uint32 m_comment_size;
char m_filename[MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE];
char m_comment[MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE];
} mz_zip_archive_file_stat;
typedef size_t (*mz_file_read_func)(void *pOpaque, mz_uint64 file_ofs, void *pBuf, size_t n);
typedef size_t (*mz_file_write_func)(void *pOpaque, mz_uint64 file_ofs, const void *pBuf, size_t n);
struct mz_zip_internal_state_tag;
typedef struct mz_zip_internal_state_tag mz_zip_internal_state;
typedef enum
{
MZ_ZIP_MODE_INVALID = 0,
MZ_ZIP_MODE_READING = 1,
MZ_ZIP_MODE_WRITING = 2,
MZ_ZIP_MODE_WRITING_HAS_BEEN_FINALIZED = 3
} mz_zip_mode;
typedef struct mz_zip_archive_tag
{
mz_uint64 m_archive_size;
mz_uint64 m_central_directory_file_ofs;
mz_uint m_total_files;
mz_zip_mode m_zip_mode;
mz_uint m_file_offset_alignment;
mz_alloc_func m_pAlloc;
mz_free_func m_pFree;
mz_realloc_func m_pRealloc;
void *m_pAlloc_opaque;
mz_file_read_func m_pRead;
mz_file_write_func m_pWrite;
void *m_pIO_opaque;
mz_zip_internal_state *m_pState;
} mz_zip_archive;
typedef enum
{
MZ_ZIP_FLAG_CASE_SENSITIVE = 0x0100,
MZ_ZIP_FLAG_IGNORE_PATH = 0x0200,
MZ_ZIP_FLAG_COMPRESSED_DATA = 0x0400,
MZ_ZIP_FLAG_DO_NOT_SORT_CENTRAL_DIRECTORY = 0x0800
} mz_zip_flags;
// ZIP archive reading
// Inits a ZIP archive reader.
// These functions read and validate the archive's central directory.
mz_bool mz_zip_reader_init(mz_zip_archive *pZip, mz_uint64 size, mz_uint32 flags);
mz_bool mz_zip_reader_init_mem(mz_zip_archive *pZip, const void *pMem, size_t size, mz_uint32 flags);
#ifndef MINIZ_NO_STDIO
mz_bool mz_zip_reader_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint32 flags);
#endif
// Returns the total number of files in the archive.
mz_uint mz_zip_reader_get_num_files(mz_zip_archive *pZip);
// Returns detailed information about an archive file entry.
mz_bool mz_zip_reader_file_stat(mz_zip_archive *pZip, mz_uint file_index, mz_zip_archive_file_stat *pStat);
// Determines if an archive file entry is a directory entry.
mz_bool mz_zip_reader_is_file_a_directory(mz_zip_archive *pZip, mz_uint file_index);
mz_bool mz_zip_reader_is_file_encrypted(mz_zip_archive *pZip, mz_uint file_index);
// Retrieves the filename of an archive file entry.
// Returns the number of bytes written to pFilename, or if filename_buf_size is 0 this function returns the number of bytes needed to fully store the filename.
mz_uint mz_zip_reader_get_filename(mz_zip_archive *pZip, mz_uint file_index, char *pFilename, mz_uint filename_buf_size);
// Attempts to locates a file in the archive's central directory.
// Valid flags: MZ_ZIP_FLAG_CASE_SENSITIVE, MZ_ZIP_FLAG_IGNORE_PATH
// Returns -1 if the file cannot be found.
int mz_zip_reader_locate_file(mz_zip_archive *pZip, const char *pName, const char *pComment, mz_uint flags);
// Extracts a archive file to a memory buffer using no memory allocation.
mz_bool mz_zip_reader_extract_to_mem_no_alloc(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
mz_bool mz_zip_reader_extract_file_to_mem_no_alloc(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
// Extracts a archive file to a memory buffer.
mz_bool mz_zip_reader_extract_to_mem(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags);
mz_bool mz_zip_reader_extract_file_to_mem(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags);
// Extracts a archive file to a dynamically allocated heap buffer.
void *mz_zip_reader_extract_to_heap(mz_zip_archive *pZip, mz_uint file_index, size_t *pSize, mz_uint flags);
void *mz_zip_reader_extract_file_to_heap(mz_zip_archive *pZip, const char *pFilename, size_t *pSize, mz_uint flags);
// Extracts a archive file using a callback function to output the file's data.
mz_bool mz_zip_reader_extract_to_callback(mz_zip_archive *pZip, mz_uint file_index, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
mz_bool mz_zip_reader_extract_file_to_callback(mz_zip_archive *pZip, const char *pFilename, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
#ifndef MINIZ_NO_STDIO
// Extracts a archive file to a disk file and sets its last accessed and modified times.
// This function only extracts files, not archive directory records.
mz_bool mz_zip_reader_extract_to_file(mz_zip_archive *pZip, mz_uint file_index, const char *pDst_filename, mz_uint flags);
mz_bool mz_zip_reader_extract_file_to_file(mz_zip_archive *pZip, const char *pArchive_filename, const char *pDst_filename, mz_uint flags);
#endif
// Ends archive reading, freeing all allocations, and closing the input archive file if mz_zip_reader_init_file() was used.
mz_bool mz_zip_reader_end(mz_zip_archive *pZip);
// ZIP archive writing
#ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
// Inits a ZIP archive writer.
mz_bool mz_zip_writer_init(mz_zip_archive *pZip, mz_uint64 existing_size);
mz_bool mz_zip_writer_init_heap(mz_zip_archive *pZip, size_t size_to_reserve_at_beginning, size_t initial_allocation_size);
#ifndef MINIZ_NO_STDIO
mz_bool mz_zip_writer_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint64 size_to_reserve_at_beginning);
#endif
// Converts a ZIP archive reader object into a writer object, to allow efficient in-place file appends to occur on an existing archive.
// For archives opened using mz_zip_reader_init_file, pFilename must be the archive's filename so it can be reopened for writing. If the file can't be reopened, mz_zip_reader_end() will be called.
// For archives opened using mz_zip_reader_init_mem, the memory block must be growable using the realloc callback (which defaults to realloc unless you've overridden it).
// Finally, for archives opened using mz_zip_reader_init, the mz_zip_archive's user provided m_pWrite function cannot be NULL.
// Note: In-place archive modification is not recommended unless you know what you're doing, because if execution stops or something goes wrong before
// the archive is finalized the file's central directory will be hosed.
mz_bool mz_zip_writer_init_from_reader(mz_zip_archive *pZip, const char *pFilename);
// Adds the contents of a memory buffer to an archive. These functions record the current local time into the archive.
// To add a directory entry, call this method with an archive name ending in a forwardslash with empty buffer.
// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
mz_bool mz_zip_writer_add_mem(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, mz_uint level_and_flags);
mz_bool mz_zip_writer_add_mem_ex(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags, mz_uint64 uncomp_size, mz_uint32 uncomp_crc32);
#ifndef MINIZ_NO_STDIO
// Adds the contents of a disk file to an archive. This function also records the disk file's modified time into the archive.
// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
mz_bool mz_zip_writer_add_file(mz_zip_archive *pZip, const char *pArchive_name, const char *pSrc_filename, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
#endif
// Adds a file to an archive by fully cloning the data from another archive.
// This function fully clones the source file's compressed data (no recompression), along with its full filename, extra data, and comment fields.
mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive *pSource_zip, mz_uint file_index);
// Finalizes the archive by writing the central directory records followed by the end of central directory record.
// After an archive is finalized, the only valid call on the mz_zip_archive struct is mz_zip_writer_end().
// An archive must be manually finalized by calling this function for it to be valid.
mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip);
mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **pBuf, size_t *pSize);
// Ends archive writing, freeing all allocations, and closing the output file if mz_zip_writer_init_file() was used.
// Note for the archive to be valid, it must have been finalized before ending.
mz_bool mz_zip_writer_end(mz_zip_archive *pZip);
// Misc. high-level helper functions:
// mz_zip_add_mem_to_archive_file_in_place() efficiently (but not atomically) appends a memory blob to a ZIP archive.
// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
mz_bool mz_zip_add_mem_to_archive_file_in_place(const char *pZip_filename, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
// Reads a single file from an archive into a heap block.
// Returns NULL on failure.
void *mz_zip_extract_archive_file_to_heap(const char *pZip_filename, const char *pArchive_name, size_t *pSize, mz_uint zip_flags);
#endif // #ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
#endif // #ifndef MINIZ_NO_ARCHIVE_APIS
// ------------------- Low-level Decompression API Definitions
// Decompression flags used by tinfl_decompress().
// TINFL_FLAG_PARSE_ZLIB_HEADER: If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib stream). Otherwise, the input is a raw deflate stream.
// TINFL_FLAG_HAS_MORE_INPUT: If set, there are more input bytes available beyond the end of the supplied input buffer. If clear, the input buffer contains all remaining input.
// TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: If set, the output buffer is large enough to hold the entire decompressed stream. If clear, the output buffer is at least the size of the dictionary (typically 32KB).
// TINFL_FLAG_COMPUTE_ADLER32: Force adler-32 checksum computation of the decompressed bytes.
enum
{
TINFL_FLAG_PARSE_ZLIB_HEADER = 1,
TINFL_FLAG_HAS_MORE_INPUT = 2,
TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF = 4,
TINFL_FLAG_COMPUTE_ADLER32 = 8
};
// High level decompression functions:
// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc().
// On entry:
// pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress.
// On return:
// Function returns a pointer to the decompressed data, or NULL on failure.
// *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data.
// The caller must call mz_free() on the returned block when it's no longer needed.
void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
// tinfl_decompress_mem_to_mem() decompresses a block in memory to another block in memory.
// Returns TINFL_DECOMPRESS_MEM_TO_MEM_FAILED on failure, or the number of bytes written on success.
#define TINFL_DECOMPRESS_MEM_TO_MEM_FAILED ((size_t)(-1))
size_t tinfl_decompress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
// tinfl_decompress_mem_to_callback() decompresses a block in memory to an internal 32KB buffer, and a user provided callback function will be called to flush the buffer.
// Returns 1 on success or 0 on failure.
typedef int (*tinfl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser);
int tinfl_decompress_mem_to_callback(const void *pIn_buf, size_t *pIn_buf_size, tinfl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
struct tinfl_decompressor_tag; typedef struct tinfl_decompressor_tag tinfl_decompressor;
// Max size of LZ dictionary.
#define TINFL_LZ_DICT_SIZE 32768
// Return status.
typedef enum
{
TINFL_STATUS_BAD_PARAM = -3,
TINFL_STATUS_ADLER32_MISMATCH = -2,
TINFL_STATUS_FAILED = -1,
TINFL_STATUS_DONE = 0,
TINFL_STATUS_NEEDS_MORE_INPUT = 1,
TINFL_STATUS_HAS_MORE_OUTPUT = 2
} tinfl_status;
// Initializes the decompressor to its initial state.
#define tinfl_init(r) do { (r)->m_state = 0; } MZ_MACRO_END
#define tinfl_get_adler32(r) (r)->m_check_adler32
// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability.
// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output.
tinfl_status tinfl_decompress(tinfl_decompressor *r, const mz_uint8 *pIn_buf_next, size_t *pIn_buf_size, mz_uint8 *pOut_buf_start, mz_uint8 *pOut_buf_next, size_t *pOut_buf_size, const mz_uint32 decomp_flags);
// Internal/private bits follow.
enum
{
TINFL_MAX_HUFF_TABLES = 3, TINFL_MAX_HUFF_SYMBOLS_0 = 288, TINFL_MAX_HUFF_SYMBOLS_1 = 32, TINFL_MAX_HUFF_SYMBOLS_2 = 19,
TINFL_FAST_LOOKUP_BITS = 10, TINFL_FAST_LOOKUP_SIZE = 1 << TINFL_FAST_LOOKUP_BITS
};
typedef struct
{
mz_uint8 m_code_size[TINFL_MAX_HUFF_SYMBOLS_0];
mz_int16 m_look_up[TINFL_FAST_LOOKUP_SIZE], m_tree[TINFL_MAX_HUFF_SYMBOLS_0 * 2];
} tinfl_huff_table;
#if MINIZ_HAS_64BIT_REGISTERS
#define TINFL_USE_64BIT_BITBUF 1
#endif
#if TINFL_USE_64BIT_BITBUF
typedef mz_uint64 tinfl_bit_buf_t;
#define TINFL_BITBUF_SIZE (64)
#else
typedef mz_uint32 tinfl_bit_buf_t;
#define TINFL_BITBUF_SIZE (32)
#endif
struct tinfl_decompressor_tag
{
mz_uint32 m_state, m_num_bits, m_zhdr0, m_zhdr1, m_z_adler32, m_final, m_type, m_check_adler32, m_dist, m_counter, m_num_extra, m_table_sizes[TINFL_MAX_HUFF_TABLES];
tinfl_bit_buf_t m_bit_buf;
size_t m_dist_from_out_buf_start;
tinfl_huff_table m_tables[TINFL_MAX_HUFF_TABLES];
mz_uint8 m_raw_header[4], m_len_codes[TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137];
};
// ------------------- Low-level Compression API Definitions
// Set TDEFL_LESS_MEMORY to 1 to use less memory (compression will be slightly slower, and raw/dynamic blocks will be output more frequently).
#define TDEFL_LESS_MEMORY 1
// tdefl_init() compression flags logically OR'd together (low 12 bits contain the max. number of probes per dictionary search):
// TDEFL_DEFAULT_MAX_PROBES: The compressor defaults to 128 dictionary probes per dictionary search. 0=Huffman only, 1=Huffman+LZ (fastest/crap compression), 4095=Huffman+LZ (slowest/best compression).
enum
{
TDEFL_HUFFMAN_ONLY = 0, TDEFL_DEFAULT_MAX_PROBES = 128, TDEFL_MAX_PROBES_MASK = 0xFFF
};
// TDEFL_WRITE_ZLIB_HEADER: If set, the compressor outputs a zlib header before the deflate data, and the Adler-32 of the source data at the end. Otherwise, you'll get raw deflate data.
// TDEFL_COMPUTE_ADLER32: Always compute the adler-32 of the input data (even when not writing zlib headers).
// TDEFL_GREEDY_PARSING_FLAG: Set to use faster greedy parsing, instead of more efficient lazy parsing.
// TDEFL_NONDETERMINISTIC_PARSING_FLAG: Enable to decrease the compressor's initialization time to the minimum, but the output may vary from run to run given the same input (depending on the contents of memory).
// TDEFL_RLE_MATCHES: Only look for RLE matches (matches with a distance of 1)
// TDEFL_FILTER_MATCHES: Discards matches <= 5 chars if enabled.
// TDEFL_FORCE_ALL_STATIC_BLOCKS: Disable usage of optimized Huffman tables.
// TDEFL_FORCE_ALL_RAW_BLOCKS: Only use raw (uncompressed) deflate blocks.
// The low 12 bits are reserved to control the max # of hash probes per dictionary lookup (see TDEFL_MAX_PROBES_MASK).
enum
{
TDEFL_WRITE_ZLIB_HEADER = 0x01000,
TDEFL_COMPUTE_ADLER32 = 0x02000,
TDEFL_GREEDY_PARSING_FLAG = 0x04000,
TDEFL_NONDETERMINISTIC_PARSING_FLAG = 0x08000,
TDEFL_RLE_MATCHES = 0x10000,
TDEFL_FILTER_MATCHES = 0x20000,
TDEFL_FORCE_ALL_STATIC_BLOCKS = 0x40000,
TDEFL_FORCE_ALL_RAW_BLOCKS = 0x80000
};
// High level compression functions:
// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc().
// On entry:
// pSrc_buf, src_buf_len: Pointer and size of source block to compress.
// flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression.
// On return:
// Function returns a pointer to the compressed data, or NULL on failure.
// *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data.
// The caller must free() the returned block when it's no longer needed.
void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory.
// Returns 0 on failure.
size_t tdefl_compress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
// Compresses an image to a compressed PNG file in memory.
// On entry:
// pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4.
// The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory.
// level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL
// If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps).
// On return:
// Function returns a pointer to the compressed data, or NULL on failure.
// *pLen_out will be set to the size of the PNG image file.
// The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed.
void *tdefl_write_image_to_png_file_in_memory_ex(const void *pImage, int w, int h, int num_chans, size_t *pLen_out, mz_uint level, mz_bool flip);
void *tdefl_write_image_to_png_file_in_memory(const void *pImage, int w, int h, int num_chans, size_t *pLen_out);
// Output stream interface. The compressor uses this interface to write compressed data. It'll typically be called TDEFL_OUT_BUF_SIZE at a time.
typedef mz_bool (*tdefl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser);
// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally.
mz_bool tdefl_compress_mem_to_output(const void *pBuf, size_t buf_len, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
enum { TDEFL_MAX_HUFF_TABLES = 3, TDEFL_MAX_HUFF_SYMBOLS_0 = 288, TDEFL_MAX_HUFF_SYMBOLS_1 = 32, TDEFL_MAX_HUFF_SYMBOLS_2 = 19, TDEFL_LZ_DICT_SIZE = 32768, TDEFL_LZ_DICT_SIZE_MASK = TDEFL_LZ_DICT_SIZE - 1, TDEFL_MIN_MATCH_LEN = 3, TDEFL_MAX_MATCH_LEN = 258 };
// TDEFL_OUT_BUF_SIZE MUST be large enough to hold a single entire compressed output block (using static/fixed Huffman codes).
#if TDEFL_LESS_MEMORY
enum { TDEFL_LZ_CODE_BUF_SIZE = 24 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 12, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
#else
enum { TDEFL_LZ_CODE_BUF_SIZE = 64 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 15, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
#endif
// The low-level tdefl functions below may be used directly if the above helper functions aren't flexible enough. The low-level functions don't make any heap allocations, unlike the above helper functions.
typedef enum
{
TDEFL_STATUS_BAD_PARAM = -2,
TDEFL_STATUS_PUT_BUF_FAILED = -1,
TDEFL_STATUS_OKAY = 0,
TDEFL_STATUS_DONE = 1,
} tdefl_status;
// Must map to MZ_NO_FLUSH, MZ_SYNC_FLUSH, etc. enums
typedef enum
{
TDEFL_NO_FLUSH = 0,
TDEFL_SYNC_FLUSH = 2,
TDEFL_FULL_FLUSH = 3,
TDEFL_FINISH = 4
} tdefl_flush;
// tdefl's compression state structure.
typedef struct
{
tdefl_put_buf_func_ptr m_pPut_buf_func;
void *m_pPut_buf_user;
mz_uint m_flags, m_max_probes[2];
int m_greedy_parsing;
mz_uint m_adler32, m_lookahead_pos, m_lookahead_size, m_dict_size;
mz_uint8 *m_pLZ_code_buf, *m_pLZ_flags, *m_pOutput_buf, *m_pOutput_buf_end;
mz_uint m_num_flags_left, m_total_lz_bytes, m_lz_code_buf_dict_pos, m_bits_in, m_bit_buffer;
mz_uint m_saved_match_dist, m_saved_match_len, m_saved_lit, m_output_flush_ofs, m_output_flush_remaining, m_finished, m_block_index, m_wants_to_finish;
tdefl_status m_prev_return_status;
const void *m_pIn_buf;
void *m_pOut_buf;
size_t *m_pIn_buf_size, *m_pOut_buf_size;
tdefl_flush m_flush;
const mz_uint8 *m_pSrc;
size_t m_src_buf_left, m_out_buf_ofs;
mz_uint8 m_dict[TDEFL_LZ_DICT_SIZE + TDEFL_MAX_MATCH_LEN - 1];
mz_uint16 m_huff_count[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
mz_uint16 m_huff_codes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
mz_uint8 m_huff_code_sizes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
mz_uint8 m_lz_code_buf[TDEFL_LZ_CODE_BUF_SIZE];
mz_uint16 m_next[TDEFL_LZ_DICT_SIZE];
mz_uint16 m_hash[TDEFL_LZ_HASH_SIZE];
mz_uint8 m_output_buf[TDEFL_OUT_BUF_SIZE];
} tdefl_compressor;
// Initializes the compressor.
// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory.
// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression.
// If pBut_buf_func is NULL the user should always call the tdefl_compress() API.
// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.)
tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible.
tdefl_status tdefl_compress(tdefl_compressor *d, const void *pIn_buf, size_t *pIn_buf_size, void *pOut_buf, size_t *pOut_buf_size, tdefl_flush flush);
// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr.
// tdefl_compress_buffer() always consumes the entire input buffer.
tdefl_status tdefl_compress_buffer(tdefl_compressor *d, const void *pIn_buf, size_t in_buf_size, tdefl_flush flush);
tdefl_status tdefl_get_prev_return_status(tdefl_compressor *d);
mz_uint32 tdefl_get_adler32(tdefl_compressor *d);
// Can't use tdefl_create_comp_flags_from_zip_params if MINIZ_NO_ZLIB_APIS isn't defined, because it uses some of its macros.
#ifndef MINIZ_NO_ZLIB_APIS
// Create tdefl_compress() flags given zlib-style compression parameters.
// level may range from [0,10] (where 10 is absolute max compression, but may be much slower on some files)
// window_bits may be -15 (raw deflate) or 15 (zlib)
// strategy may be either MZ_DEFAULT_STRATEGY, MZ_FILTERED, MZ_HUFFMAN_ONLY, MZ_RLE, or MZ_FIXED
mz_uint tdefl_create_comp_flags_from_zip_params(int level, int window_bits, int strategy);
#endif // #ifndef MINIZ_NO_ZLIB_APIS
#ifdef __cplusplus
}
#endif
#endif // MINIZ_HEADER_INCLUDED

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@ -0,0 +1,645 @@
/*-
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)queue.h 8.5 (Berkeley) 8/20/94
* $FreeBSD$
*/
#ifndef _SYS_QUEUE_H_
#define _SYS_QUEUE_H_
#include <sys/cdefs.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file defines four types of data structures: singly-linked lists,
* singly-linked tail queues, lists and tail queues.
*
* A singly-linked list is headed by a single forward pointer. The elements
* are singly linked for minimum space and pointer manipulation overhead at
* the expense of O(n) removal for arbitrary elements. New elements can be
* added to the list after an existing element or at the head of the list.
* Elements being removed from the head of the list should use the explicit
* macro for this purpose for optimum efficiency. A singly-linked list may
* only be traversed in the forward direction. Singly-linked lists are ideal
* for applications with large datasets and few or no removals or for
* implementing a LIFO queue.
*
* A singly-linked tail queue is headed by a pair of pointers, one to the
* head of the list and the other to the tail of the list. The elements are
* singly linked for minimum space and pointer manipulation overhead at the
* expense of O(n) removal for arbitrary elements. New elements can be added
* to the list after an existing element, at the head of the list, or at the
* end of the list. Elements being removed from the head of the tail queue
* should use the explicit macro for this purpose for optimum efficiency.
* A singly-linked tail queue may only be traversed in the forward direction.
* Singly-linked tail queues are ideal for applications with large datasets
* and few or no removals or for implementing a FIFO queue.
*
* A list is headed by a single forward pointer (or an array of forward
* pointers for a hash table header). The elements are doubly linked
* so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before
* or after an existing element or at the head of the list. A list
* may only be traversed in the forward direction.
*
* A tail queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or
* after an existing element, at the head of the list, or at the end of
* the list. A tail queue may be traversed in either direction.
*
* For details on the use of these macros, see the queue(3) manual page.
*
*
* SLIST LIST STAILQ TAILQ
* _HEAD + + + +
* _HEAD_INITIALIZER + + + +
* _ENTRY + + + +
* _INIT + + + +
* _EMPTY + + + +
* _FIRST + + + +
* _NEXT + + + +
* _PREV - - - +
* _LAST - - + +
* _FOREACH + + + +
* _FOREACH_SAFE + + + +
* _FOREACH_REVERSE - - - +
* _FOREACH_REVERSE_SAFE - - - +
* _INSERT_HEAD + + + +
* _INSERT_BEFORE - + - +
* _INSERT_AFTER + + + +
* _INSERT_TAIL - - + +
* _CONCAT - - + +
* _REMOVE_AFTER + - + -
* _REMOVE_HEAD + - + -
* _REMOVE + + + +
*
*/
#ifdef QUEUE_MACRO_DEBUG
/* Store the last 2 places the queue element or head was altered */
struct qm_trace {
char * lastfile;
int lastline;
char * prevfile;
int prevline;
};
#define TRACEBUF struct qm_trace trace;
#define TRASHIT(x) do {(x) = (void *)-1;} while (0)
#define QMD_SAVELINK(name, link) void **name = (void *)&(link)
#define QMD_TRACE_HEAD(head) do { \
(head)->trace.prevline = (head)->trace.lastline; \
(head)->trace.prevfile = (head)->trace.lastfile; \
(head)->trace.lastline = __LINE__; \
(head)->trace.lastfile = __FILE__; \
} while (0)
#define QMD_TRACE_ELEM(elem) do { \
(elem)->trace.prevline = (elem)->trace.lastline; \
(elem)->trace.prevfile = (elem)->trace.lastfile; \
(elem)->trace.lastline = __LINE__; \
(elem)->trace.lastfile = __FILE__; \
} while (0)
#else
#define QMD_TRACE_ELEM(elem)
#define QMD_TRACE_HEAD(head)
#define QMD_SAVELINK(name, link)
#define TRACEBUF
#define TRASHIT(x)
#endif /* QUEUE_MACRO_DEBUG */
/*
* Singly-linked List declarations.
*/
#define SLIST_HEAD(name, type) \
struct name { \
struct type *slh_first; /* first element */ \
}
#define SLIST_HEAD_INITIALIZER(head) \
{ NULL }
#define SLIST_ENTRY(type) \
struct { \
struct type *sle_next; /* next element */ \
}
/*
* Singly-linked List functions.
*/
#define SLIST_EMPTY(head) ((head)->slh_first == NULL)
#define SLIST_FIRST(head) ((head)->slh_first)
#define SLIST_FOREACH(var, head, field) \
for ((var) = SLIST_FIRST((head)); \
(var); \
(var) = SLIST_NEXT((var), field))
#define SLIST_FOREACH_SAFE(var, head, field, tvar) \
for ((var) = SLIST_FIRST((head)); \
(var) && ((tvar) = SLIST_NEXT((var), field), 1); \
(var) = (tvar))
#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \
for ((varp) = &SLIST_FIRST((head)); \
((var) = *(varp)) != NULL; \
(varp) = &SLIST_NEXT((var), field))
#define SLIST_INIT(head) do { \
SLIST_FIRST((head)) = NULL; \
} while (0)
#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \
SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \
SLIST_NEXT((slistelm), field) = (elm); \
} while (0)
#define SLIST_INSERT_HEAD(head, elm, field) do { \
SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \
SLIST_FIRST((head)) = (elm); \
} while (0)
#define SLIST_NEXT(elm, field) ((elm)->field.sle_next)
#define SLIST_REMOVE(head, elm, type, field) do { \
QMD_SAVELINK(oldnext, (elm)->field.sle_next); \
if (SLIST_FIRST((head)) == (elm)) { \
SLIST_REMOVE_HEAD((head), field); \
} \
else { \
struct type *curelm = SLIST_FIRST((head)); \
while (SLIST_NEXT(curelm, field) != (elm)) \
curelm = SLIST_NEXT(curelm, field); \
SLIST_REMOVE_AFTER(curelm, field); \
} \
TRASHIT(*oldnext); \
} while (0)
#define SLIST_REMOVE_AFTER(elm, field) do { \
SLIST_NEXT(elm, field) = \
SLIST_NEXT(SLIST_NEXT(elm, field), field); \
} while (0)
#define SLIST_REMOVE_HEAD(head, field) do { \
SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \
} while (0)
/*
* Singly-linked Tail queue declarations.
*/
#define STAILQ_HEAD(name, type) \
struct name { \
struct type *stqh_first;/* first element */ \
struct type **stqh_last;/* addr of last next element */ \
}
#define STAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).stqh_first }
#define STAILQ_ENTRY(type) \
struct { \
struct type *stqe_next; /* next element */ \
}
/*
* Singly-linked Tail queue functions.
*/
#define STAILQ_CONCAT(head1, head2) do { \
if (!STAILQ_EMPTY((head2))) { \
*(head1)->stqh_last = (head2)->stqh_first; \
(head1)->stqh_last = (head2)->stqh_last; \
STAILQ_INIT((head2)); \
} \
} while (0)
#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL)
#define STAILQ_FIRST(head) ((head)->stqh_first)
#define STAILQ_FOREACH(var, head, field) \
for((var) = STAILQ_FIRST((head)); \
(var); \
(var) = STAILQ_NEXT((var), field))
#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \
for ((var) = STAILQ_FIRST((head)); \
(var) && ((tvar) = STAILQ_NEXT((var), field), 1); \
(var) = (tvar))
#define STAILQ_INIT(head) do { \
STAILQ_FIRST((head)) = NULL; \
(head)->stqh_last = &STAILQ_FIRST((head)); \
} while (0)
#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \
if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
STAILQ_NEXT((tqelm), field) = (elm); \
} while (0)
#define STAILQ_INSERT_HEAD(head, elm, field) do { \
if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
STAILQ_FIRST((head)) = (elm); \
} while (0)
#define STAILQ_INSERT_TAIL(head, elm, field) do { \
STAILQ_NEXT((elm), field) = NULL; \
*(head)->stqh_last = (elm); \
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
} while (0)
#define STAILQ_LAST(head, type, field) \
(STAILQ_EMPTY((head)) ? \
NULL : \
((struct type *)(void *) \
((char *)((head)->stqh_last) - __offsetof(struct type, field))))
#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
#define STAILQ_REMOVE(head, elm, type, field) do { \
QMD_SAVELINK(oldnext, (elm)->field.stqe_next); \
if (STAILQ_FIRST((head)) == (elm)) { \
STAILQ_REMOVE_HEAD((head), field); \
} \
else { \
struct type *curelm = STAILQ_FIRST((head)); \
while (STAILQ_NEXT(curelm, field) != (elm)) \
curelm = STAILQ_NEXT(curelm, field); \
STAILQ_REMOVE_AFTER(head, curelm, field); \
} \
TRASHIT(*oldnext); \
} while (0)
#define STAILQ_REMOVE_HEAD(head, field) do { \
if ((STAILQ_FIRST((head)) = \
STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \
(head)->stqh_last = &STAILQ_FIRST((head)); \
} while (0)
#define STAILQ_REMOVE_AFTER(head, elm, field) do { \
if ((STAILQ_NEXT(elm, field) = \
STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL) \
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
} while (0)
#define STAILQ_SWAP(head1, head2, type) do { \
struct type *swap_first = STAILQ_FIRST(head1); \
struct type **swap_last = (head1)->stqh_last; \
STAILQ_FIRST(head1) = STAILQ_FIRST(head2); \
(head1)->stqh_last = (head2)->stqh_last; \
STAILQ_FIRST(head2) = swap_first; \
(head2)->stqh_last = swap_last; \
if (STAILQ_EMPTY(head1)) \
(head1)->stqh_last = &STAILQ_FIRST(head1); \
if (STAILQ_EMPTY(head2)) \
(head2)->stqh_last = &STAILQ_FIRST(head2); \
} while (0)
#define STAILQ_INSERT_CHAIN_HEAD(head, elm_chead, elm_ctail, field) do { \
if ((STAILQ_NEXT(elm_ctail, field) = STAILQ_FIRST(head)) == NULL ) { \
(head)->stqh_last = &STAILQ_NEXT(elm_ctail, field); \
} \
STAILQ_FIRST(head) = (elm_chead); \
} while (0)
/*
* List declarations.
*/
#define LIST_HEAD(name, type) \
struct name { \
struct type *lh_first; /* first element */ \
}
#define LIST_HEAD_INITIALIZER(head) \
{ NULL }
#define LIST_ENTRY(type) \
struct { \
struct type *le_next; /* next element */ \
struct type **le_prev; /* address of previous next element */ \
}
/*
* List functions.
*/
#if (defined(_KERNEL) && defined(INVARIANTS))
#define QMD_LIST_CHECK_HEAD(head, field) do { \
if (LIST_FIRST((head)) != NULL && \
LIST_FIRST((head))->field.le_prev != \
&LIST_FIRST((head))) \
panic("Bad list head %p first->prev != head", (head)); \
} while (0)
#define QMD_LIST_CHECK_NEXT(elm, field) do { \
if (LIST_NEXT((elm), field) != NULL && \
LIST_NEXT((elm), field)->field.le_prev != \
&((elm)->field.le_next)) \
panic("Bad link elm %p next->prev != elm", (elm)); \
} while (0)
#define QMD_LIST_CHECK_PREV(elm, field) do { \
if (*(elm)->field.le_prev != (elm)) \
panic("Bad link elm %p prev->next != elm", (elm)); \
} while (0)
#else
#define QMD_LIST_CHECK_HEAD(head, field)
#define QMD_LIST_CHECK_NEXT(elm, field)
#define QMD_LIST_CHECK_PREV(elm, field)
#endif /* (_KERNEL && INVARIANTS) */
#define LIST_EMPTY(head) ((head)->lh_first == NULL)
#define LIST_FIRST(head) ((head)->lh_first)
#define LIST_FOREACH(var, head, field) \
for ((var) = LIST_FIRST((head)); \
(var); \
(var) = LIST_NEXT((var), field))
#define LIST_FOREACH_SAFE(var, head, field, tvar) \
for ((var) = LIST_FIRST((head)); \
(var) && ((tvar) = LIST_NEXT((var), field), 1); \
(var) = (tvar))
#define LIST_INIT(head) do { \
LIST_FIRST((head)) = NULL; \
} while (0)
#define LIST_INSERT_AFTER(listelm, elm, field) do { \
QMD_LIST_CHECK_NEXT(listelm, field); \
if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
LIST_NEXT((listelm), field)->field.le_prev = \
&LIST_NEXT((elm), field); \
LIST_NEXT((listelm), field) = (elm); \
(elm)->field.le_prev = &LIST_NEXT((listelm), field); \
} while (0)
#define LIST_INSERT_BEFORE(listelm, elm, field) do { \
QMD_LIST_CHECK_PREV(listelm, field); \
(elm)->field.le_prev = (listelm)->field.le_prev; \
LIST_NEXT((elm), field) = (listelm); \
*(listelm)->field.le_prev = (elm); \
(listelm)->field.le_prev = &LIST_NEXT((elm), field); \
} while (0)
#define LIST_INSERT_HEAD(head, elm, field) do { \
QMD_LIST_CHECK_HEAD((head), field); \
if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \
LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
LIST_FIRST((head)) = (elm); \
(elm)->field.le_prev = &LIST_FIRST((head)); \
} while (0)
#define LIST_NEXT(elm, field) ((elm)->field.le_next)
#define LIST_REMOVE(elm, field) do { \
QMD_SAVELINK(oldnext, (elm)->field.le_next); \
QMD_SAVELINK(oldprev, (elm)->field.le_prev); \
QMD_LIST_CHECK_NEXT(elm, field); \
QMD_LIST_CHECK_PREV(elm, field); \
if (LIST_NEXT((elm), field) != NULL) \
LIST_NEXT((elm), field)->field.le_prev = \
(elm)->field.le_prev; \
*(elm)->field.le_prev = LIST_NEXT((elm), field); \
TRASHIT(*oldnext); \
TRASHIT(*oldprev); \
} while (0)
#define LIST_SWAP(head1, head2, type, field) do { \
struct type *swap_tmp = LIST_FIRST((head1)); \
LIST_FIRST((head1)) = LIST_FIRST((head2)); \
LIST_FIRST((head2)) = swap_tmp; \
if ((swap_tmp = LIST_FIRST((head1))) != NULL) \
swap_tmp->field.le_prev = &LIST_FIRST((head1)); \
if ((swap_tmp = LIST_FIRST((head2))) != NULL) \
swap_tmp->field.le_prev = &LIST_FIRST((head2)); \
} while (0)
/*
* Tail queue declarations.
*/
#define TAILQ_HEAD(name, type) \
struct name { \
struct type *tqh_first; /* first element */ \
struct type **tqh_last; /* addr of last next element */ \
TRACEBUF \
}
#define TAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).tqh_first }
#define TAILQ_ENTRY(type) \
struct { \
struct type *tqe_next; /* next element */ \
struct type **tqe_prev; /* address of previous next element */ \
TRACEBUF \
}
/*
* Tail queue functions.
*/
#if (defined(_KERNEL) && defined(INVARIANTS))
#define QMD_TAILQ_CHECK_HEAD(head, field) do { \
if (!TAILQ_EMPTY(head) && \
TAILQ_FIRST((head))->field.tqe_prev != \
&TAILQ_FIRST((head))) \
panic("Bad tailq head %p first->prev != head", (head)); \
} while (0)
#define QMD_TAILQ_CHECK_TAIL(head, field) do { \
if (*(head)->tqh_last != NULL) \
panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); \
} while (0)
#define QMD_TAILQ_CHECK_NEXT(elm, field) do { \
if (TAILQ_NEXT((elm), field) != NULL && \
TAILQ_NEXT((elm), field)->field.tqe_prev != \
&((elm)->field.tqe_next)) \
panic("Bad link elm %p next->prev != elm", (elm)); \
} while (0)
#define QMD_TAILQ_CHECK_PREV(elm, field) do { \
if (*(elm)->field.tqe_prev != (elm)) \
panic("Bad link elm %p prev->next != elm", (elm)); \
} while (0)
#else
#define QMD_TAILQ_CHECK_HEAD(head, field)
#define QMD_TAILQ_CHECK_TAIL(head, headname)
#define QMD_TAILQ_CHECK_NEXT(elm, field)
#define QMD_TAILQ_CHECK_PREV(elm, field)
#endif /* (_KERNEL && INVARIANTS) */
#define TAILQ_CONCAT(head1, head2, field) do { \
if (!TAILQ_EMPTY(head2)) { \
*(head1)->tqh_last = (head2)->tqh_first; \
(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \
(head1)->tqh_last = (head2)->tqh_last; \
TAILQ_INIT((head2)); \
QMD_TRACE_HEAD(head1); \
QMD_TRACE_HEAD(head2); \
} \
} while (0)
#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
#define TAILQ_FIRST(head) ((head)->tqh_first)
#define TAILQ_FOREACH(var, head, field) \
for ((var) = TAILQ_FIRST((head)); \
(var); \
(var) = TAILQ_NEXT((var), field))
#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \
for ((var) = TAILQ_FIRST((head)); \
(var) && ((tvar) = TAILQ_NEXT((var), field), 1); \
(var) = (tvar))
#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
for ((var) = TAILQ_LAST((head), headname); \
(var); \
(var) = TAILQ_PREV((var), headname, field))
#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \
for ((var) = TAILQ_LAST((head), headname); \
(var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \
(var) = (tvar))
#define TAILQ_INIT(head) do { \
TAILQ_FIRST((head)) = NULL; \
(head)->tqh_last = &TAILQ_FIRST((head)); \
QMD_TRACE_HEAD(head); \
} while (0)
#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
QMD_TAILQ_CHECK_NEXT(listelm, field); \
if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
TAILQ_NEXT((elm), field)->field.tqe_prev = \
&TAILQ_NEXT((elm), field); \
else { \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
QMD_TRACE_HEAD(head); \
} \
TAILQ_NEXT((listelm), field) = (elm); \
(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \
QMD_TRACE_ELEM(&(elm)->field); \
QMD_TRACE_ELEM(&listelm->field); \
} while (0)
#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
QMD_TAILQ_CHECK_PREV(listelm, field); \
(elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
TAILQ_NEXT((elm), field) = (listelm); \
*(listelm)->field.tqe_prev = (elm); \
(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \
QMD_TRACE_ELEM(&(elm)->field); \
QMD_TRACE_ELEM(&listelm->field); \
} while (0)
#define TAILQ_INSERT_HEAD(head, elm, field) do { \
QMD_TAILQ_CHECK_HEAD(head, field); \
if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \
TAILQ_FIRST((head))->field.tqe_prev = \
&TAILQ_NEXT((elm), field); \
else \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
TAILQ_FIRST((head)) = (elm); \
(elm)->field.tqe_prev = &TAILQ_FIRST((head)); \
QMD_TRACE_HEAD(head); \
QMD_TRACE_ELEM(&(elm)->field); \
} while (0)
#define TAILQ_INSERT_TAIL(head, elm, field) do { \
QMD_TAILQ_CHECK_TAIL(head, field); \
TAILQ_NEXT((elm), field) = NULL; \
(elm)->field.tqe_prev = (head)->tqh_last; \
*(head)->tqh_last = (elm); \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
QMD_TRACE_HEAD(head); \
QMD_TRACE_ELEM(&(elm)->field); \
} while (0)
#define TAILQ_LAST(head, headname) \
(*(((struct headname *)((head)->tqh_last))->tqh_last))
#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
#define TAILQ_PREV(elm, headname, field) \
(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
#define TAILQ_REMOVE(head, elm, field) do { \
QMD_SAVELINK(oldnext, (elm)->field.tqe_next); \
QMD_SAVELINK(oldprev, (elm)->field.tqe_prev); \
QMD_TAILQ_CHECK_NEXT(elm, field); \
QMD_TAILQ_CHECK_PREV(elm, field); \
if ((TAILQ_NEXT((elm), field)) != NULL) \
TAILQ_NEXT((elm), field)->field.tqe_prev = \
(elm)->field.tqe_prev; \
else { \
(head)->tqh_last = (elm)->field.tqe_prev; \
QMD_TRACE_HEAD(head); \
} \
*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \
TRASHIT(*oldnext); \
TRASHIT(*oldprev); \
QMD_TRACE_ELEM(&(elm)->field); \
} while (0)
#define TAILQ_SWAP(head1, head2, type, field) do { \
struct type *swap_first = (head1)->tqh_first; \
struct type **swap_last = (head1)->tqh_last; \
(head1)->tqh_first = (head2)->tqh_first; \
(head1)->tqh_last = (head2)->tqh_last; \
(head2)->tqh_first = swap_first; \
(head2)->tqh_last = swap_last; \
if ((swap_first = (head1)->tqh_first) != NULL) \
swap_first->field.tqe_prev = &(head1)->tqh_first; \
else \
(head1)->tqh_last = &(head1)->tqh_first; \
if ((swap_first = (head2)->tqh_first) != NULL) \
swap_first->field.tqe_prev = &(head2)->tqh_first; \
else \
(head2)->tqh_last = &(head2)->tqh_first; \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* !_SYS_QUEUE_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_RTC_H_
#define _ROM_RTC_H_
#include "ets_sys.h"
#include <stdbool.h>
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup rtc_apis, rtc registers and memory related apis
* @brief rtc apis
*/
/** @addtogroup rtc_apis
* @{
*/
/**************************************************************************************
* Note: *
* Some Rtc memory and registers are used, in ROM or in internal library. *
* Please do not use reserved or used rtc memory or registers. *
* *
*************************************************************************************
* RTC Memory & Store Register usage
*************************************************************************************
* rtc memory addr type size usage
* 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
* 0x3ff61000+SIZE_CP Slow 4096-SIZE_CP
* 0x3ff62800 Slow 4096 Reserved
*
* 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code
*
*************************************************************************************
* Rtc store registers usage
* RTC_CNTL_STORE0_REG
* RTC_CNTL_STORE1_REG
* RTC_CNTL_STORE2_REG
* RTC_CNTL_STORE3_REG
* RTC_CNTL_STORE4_REG Reserved
* RTC_CNTL_STORE5_REG External Xtal Frequency
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
*************************************************************************************
*/
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
typedef enum {
AWAKE = 0, //<CPU ON
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
} SLEEP_MODE;
typedef enum {
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Vbat power on reset*/
SW_RESET = 3, /**<3, Software reset digital core*/
OWDT_RESET = 4, /**<4, Legacy watch dog reset digital core*/
DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
TGWDT_CPU_RESET = 11, /**<11, Time Group reset CPU*/
SW_CPU_RESET = 12, /**<12, Software reset CPU*/
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
EXT_CPU_RESET = 14, /**<14, for APP CPU, reseted by PRO CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/
} RESET_REASON;
typedef enum {
NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0,
EXT_EVENT1_TRIG = BIT1,
GPIO_TRIG = BIT2,
TIMER_EXPIRE = BIT3,
SDIO_TRIG = BIT4,
MAC_TRIG = BIT5,
UART0_TRIG = BIT6,
UART1_TRIG = BIT7,
TOUCH_TRIG = BIT8,
SAR_TRIG = BIT9,
BT_TRIG = BIT10
} WAKEUP_REASON;
typedef enum {
DISEN_WAKEUP = NO_SLEEP,
EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
GPIO_TRIG_EN = GPIO_TRIG,
TIMER_EXPIRE_EN = TIMER_EXPIRE,
SDIO_TRIG_EN = SDIO_TRIG,
MAC_TRIG_EN = MAC_TRIG,
UART0_TRIG_EN = UART0_TRIG,
UART1_TRIG_EN = UART1_TRIG,
TOUCH_TRIG_EN = TOUCH_TRIG,
SAR_TRIG_EN = SAR_TRIG,
BT_TRIG_EN = BT_TRIG
} WAKEUP_ENABLE;
typedef enum {
NO_INT = 0,
WAKEUP_INT = BIT0,
REJECT_INT = BIT1,
SDIO_IDLE_INT = BIT2,
RTC_WDT_INT = BIT3,
RTC_TIME_VALID_INT = BIT4
} RTC_INT_REASON;
typedef enum {
DISEN_INT = 0,
WAKEUP_INT_EN = WAKEUP_INT,
REJECT_INT_EN = REJECT_INT,
SDIO_IDLE_INT_EN = SDIO_IDLE_INT,
RTC_WDT_INT_EN = RTC_WDT_INT,
RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
} RTC_INT_EN;
/**
* @brief Get the reset reason for CPU.
*
* @param int cpu_no : CPU no.
*
* @return RESET_REASON
*/
RESET_REASON rtc_get_reset_reason(int cpu_no);
/**
* @brief Get the wakeup cause for CPU.
*
* @param int cpu_no : CPU no.
*
* @return WAKEUP_REASON
*/
WAKEUP_REASON rtc_get_wakeup_cause(void);
/**
* @brief Get CRC for Fast RTC Memory.
*
* @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
*
* @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
*
* @return uint32_t : CRC32 result
*/
uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
/**
* @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
*
* @param None
*
* @return None
*/
void set_rtc_memory_crc(void);
/**
* @brief Software Reset digital core.
*
* @param None
*
* @return None
*/
void software_reset(void);
/**
* @brief Software Reset digital core.
*
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
*
* @return None
*/
void software_reset_cpu(int cpu_no);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_RTC_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SECURE_BOOT_H_
#define _ROM_SECURE_BOOT_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
void ets_secure_boot_start(void);
void ets_secure_boot_finish(void);
void ets_secure_boot_hash(uint32_t *buf);
void ets_secure_boot_obtain(void);
int ets_secure_boot_check(uint32_t *buf);
void ets_secure_boot_rd_iv(uint32_t *buf);
void ets_secure_boot_rd_abstract(uint32_t *buf);
bool ets_secure_boot_check_start(uint8_t abs_index, uint32_t iv_addr);
int ets_secure_boot_check_finish(uint32_t *abstract);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SECURE_BOOT_H_ */

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/*
ROM functions for hardware SHA support.
It is not recommended to use these functions directly,
use the wrapper functions in hwcrypto/sha.h instead.
*/
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SHA_H_
#define _ROM_SHA_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct SHAContext {
bool start;
uint32_t total_input_bits[4];
} SHA_CTX;
enum SHA_TYPE {
SHA1 = 0,
SHA2_256,
SHA2_384,
SHA2_512,
SHA_INVALID = -1,
};
void ets_sha_init(SHA_CTX *ctx);
void ets_sha_enable(void);
void ets_sha_disable(void);
void ets_sha_update(SHA_CTX *ctx, enum SHA_TYPE type, const uint8_t *input, size_t input_bits);
void ets_sha_finish(SHA_CTX *ctx, enum SHA_TYPE type, uint8_t *output);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SHA_H_ */

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tools/sdk/include/esp32/rom/spi_flash.h Normal file
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/spi_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup spi_flash_apis, spi flash operation related apis
* @brief spi_flash apis
*/
/** @addtogroup spi_flash_apis
* @{
*/
/*************************************************************
* Note
*************************************************************
* 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
* used as an SPI master to access Flash and ext-SRAM by
* Cache module. It will support Decryto read for Flash,
* read/write for ext-SRAM. And SPI1 is also used as an
* SPI master for Flash read/write and ext-SRAM read/write.
* It will support Encrypto write for Flash.
* 2. As an SPI master, SPI support Highest clock to 80M,
* however, Flash with 80M Clock should be configured
* for different Flash chips. If you want to use 80M
* clock We should use the SPI that is certified by
* Espressif. However, the certification is not started
* at the time, so please use 40M clock at the moment.
* 3. SPI Flash can use 2 lines or 4 lines mode. If you
* use 2 lines mode, you can save two pad SPIHD and
* SPIWP for gpio. ESP32 support configured SPI pad for
* Flash, the configuration is stored in efuse and flash.
* However, the configurations of pads should be certified
* by Espressif. If you use this function, please use 40M
* clock at the moment.
* 4. ESP32 support to use Common SPI command to configure
* Flash to QIO mode, if you failed to configure with fix
* command. With Common SPI Command, ESP32 can also provide
* a way to use same Common SPI command groups on different
* Flash chips.
* 5. This functions are not protected by packeting, Please use the
*************************************************************
*/
#define PERIPHS_SPI_FLASH_CMD SPI_CMD(1)
#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR(1)
#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL(1)
#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1(1)
#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS(1)
#define PERIPHS_SPI_FLASH_USRREG SPI_USER(1)
#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1(1)
#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2(1)
#define PERIPHS_SPI_FLASH_C0 SPI_W0(1)
#define PERIPHS_SPI_FLASH_C1 SPI_W1(1)
#define PERIPHS_SPI_FLASH_C2 SPI_W2(1)
#define PERIPHS_SPI_FLASH_C3 SPI_W3(1)
#define PERIPHS_SPI_FLASH_C4 SPI_W4(1)
#define PERIPHS_SPI_FLASH_C5 SPI_W5(1)
#define PERIPHS_SPI_FLASH_C6 SPI_W6(1)
#define PERIPHS_SPI_FLASH_C7 SPI_W7(1)
#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC(1)
#define SPI0_R_QIO_DUMMY_CYCLELEN 3
#define SPI0_R_QIO_ADDR_BITSLEN 31
#define SPI0_R_FAST_DUMMY_CYCLELEN 7
#define SPI0_R_DIO_DUMMY_CYCLELEN 3
#define SPI0_R_FAST_ADDR_BITSLEN 23
#define SPI0_R_SIO_ADDR_BITSLEN 23
#define SPI1_R_QIO_DUMMY_CYCLELEN 3
#define SPI1_R_QIO_ADDR_BITSLEN 31
#define SPI1_R_FAST_DUMMY_CYCLELEN 7
#define SPI1_R_DIO_DUMMY_CYCLELEN 3
#define SPI1_R_DIO_ADDR_BITSLEN 31
#define SPI1_R_FAST_ADDR_BITSLEN 23
#define SPI1_R_SIO_ADDR_BITSLEN 23
#define SPI_W_SIO_ADDR_BITSLEN 23
#define TWO_BYTE_STATUS_EN SPI_WRSR_2B
//SPI address register
#define SPI_FLASH_BYTES_LEN 24
#define SPI_BUFF_BYTE_WRITE_NUM 32
#define SPI_BUFF_BYTE_READ_NUM 64
#define SPI_BUFF_BYTE_READ_BITS 0x3f
//SPI status register
#define SPI_FLASH_BUSY_FLAG BIT0
#define SPI_FLASH_WRENABLE_FLAG BIT1
#define SPI_FLASH_BP0 BIT2
#define SPI_FLASH_BP1 BIT3
#define SPI_FLASH_BP2 BIT4
#define FLASH_WR_PROTECT (SPI_FLASH_BP0|SPI_FLASH_BP1|SPI_FLASH_BP2)
#define SPI_FLASH_QE BIT9
typedef enum {
SPI_FLASH_QIO_MODE = 0,
SPI_FLASH_QOUT_MODE,
SPI_FLASH_DIO_MODE,
SPI_FLASH_DOUT_MODE,
SPI_FLASH_FASTRD_MODE,
SPI_FLASH_SLOWRD_MODE
} SpiFlashRdMode;
typedef enum {
SPI_FLASH_RESULT_OK,
SPI_FLASH_RESULT_ERR,
SPI_FLASH_RESULT_TIMEOUT
} SpiFlashOpResult;
typedef struct {
uint32_t deviceId;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
uint32_t sector_size;
uint32_t page_size;
uint32_t status_mask;
} SpiFlashChip;
typedef struct {
uint8_t data_length;
uint8_t read_cmd0;
uint8_t read_cmd1;
uint8_t write_cmd;
uint16_t data_mask;
uint16_t data;
} SpiCommonCmd;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void SelectSpiQIO(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void SelectSpiFunction(uint32_t ishspi);
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
*
* @return None
*/
void spi_flash_attach(uint32_t ishspi, bool legacy);
/**
* @brief SPI Read Flash status register. We use CMD 0x05.
* Please do not call this function in SDK.
*
* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return SPI_FLASH_RESULT_OK : read OK.
* SPI_FLASH_RESULT_ERR : read error.
* SPI_FLASH_RESULT_TIMEOUT : read timeout.
*/
SpiFlashOpResult SPI_read_status(SpiFlashChip *spi, uint32_t *status);
/**
* @brief SPI Read Flash status register high 16 bit. We use CMD 0x35.
* Please do not call this function in SDK.
*
* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return SPI_FLASH_RESULT_OK : read OK.
* SPI_FLASH_RESULT_ERR : read error.
* SPI_FLASH_RESULT_TIMEOUT : read timeout.
*/
SpiFlashOpResult SPI_read_status_high(SpiFlashChip *spi, uint32_t *status);
/**
* @brief Write status to Falsh status register.
* Please do not call this function in SDK.
*
* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t status_value : Value to .
*
* @return SPI_FLASH_RESULT_OK : write OK.
* SPI_FLASH_RESULT_ERR : write error.
* SPI_FLASH_RESULT_TIMEOUT : write timeout.
*/
SpiFlashOpResult SPI_write_status(SpiFlashChip *spi, uint32_t status_value);
/**
* @brief Use a command to Read Flash status register.
* Please do not call this function in SDK.
*
* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t*status : The pointer to which to return the Flash status value.
*
* @return SPI_FLASH_RESULT_OK : read OK.
* SPI_FLASH_RESULT_ERR : read error.
* SPI_FLASH_RESULT_TIMEOUT : read timeout.
*/
SpiFlashOpResult SPI_user_command_read(uint32_t *status, uint8_t cmd);
/**
* @brief Config SPI Flash read mode when init.
* Please do not call this function in SDK.
*
* @param SpiFlashRdMode mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
*
* @return SPI_FLASH_RESULT_OK : config OK.
* SPI_FLASH_RESULT_ERR : config error.
* SPI_FLASH_RESULT_TIMEOUT : config timeout.
*/
SpiFlashOpResult SPIReadModeCnfig(SpiFlashRdMode mode, bool legacy);
/**
* @brief Config SPI Flash read mode when Flash is running in some mode.
* Please do not call this function in SDK.
*
* @param SpiFlashRdMode mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
*
* @return SPI_FLASH_RESULT_OK : config OK.
* SPI_FLASH_RESULT_ERR : config error.
* SPI_FLASH_RESULT_TIMEOUT : config timeout.
*/
SpiFlashOpResult SPIMasterReadModeCnfig(SpiFlashRdMode mode);
/**
* @brief Config SPI Flash clock divisor.
* Please do not call this function in SDK.
*
* @param uint8_t freqdiv: clock divisor.
*
* @param uint8_t spi: 0 for SPI0, 1 for SPI1.
*
* @return SPI_FLASH_RESULT_OK : config OK.
* SPI_FLASH_RESULT_ERR : config error.
* SPI_FLASH_RESULT_TIMEOUT : config timeout.
*/
SpiFlashOpResult SPIClkConfig(uint8_t freqdiv, uint8_t spi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param SpiCommonCmd *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t SPI_Common_Command(SpiCommonCmd *cmd);
/**
* @brief Unlock SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return SPI_FLASH_RESULT_OK : Unlock OK.
* SPI_FLASH_RESULT_ERR : Unlock error.
* SPI_FLASH_RESULT_TIMEOUT : Unlock timeout.
*/
SpiFlashOpResult SPIUnlock(void);
/**
* @brief SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return SPI_FLASH_RESULT_OK : Lock OK.
* SPI_FLASH_RESULT_ERR : Lock error.
* SPI_FLASH_RESULT_TIMEOUT : Lock timeout.
*/
SpiFlashOpResult SPILock(void);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
*
* @param uint32_t deviceId : Device ID read from SPI, the low 32 bit.
*
* @param uint32_t chip_size : The Flash size.
*
* @param uint32_t block_size : The Flash block size.
*
* @param uint32_t sector_size : The Flash sector size.
*
* @param uint32_t page_size : The Flash page size.
*
* @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
*
* @return SPI_FLASH_RESULT_OK : Update OK.
* SPI_FLASH_RESULT_ERR : Update error.
* SPI_FLASH_RESULT_TIMEOUT : Update timeout.
*/
SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
/**
* @brief Erase whole flash chip.
* Please do not call this function in SDK.
*
* @param None
*
* @return SPI_FLASH_RESULT_OK : Erase OK.
* SPI_FLASH_RESULT_ERR : Erase error.
* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
*/
SpiFlashOpResult SPIEraseChip(void);
/**
* @brief Erase a block of flash.
* Please do not call this function in SDK.
*
* @param uint32_t block_num : Which block to erase.
*
* @return SPI_FLASH_RESULT_OK : Erase OK.
* SPI_FLASH_RESULT_ERR : Erase error.
* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
*/
SpiFlashOpResult SPIEraseBlock(uint32_t block_num);
/**
* @brief Erase a sector of flash.
* Please do not call this function in SDK.
*
* @param uint32_t sector_num : Which sector to erase.
*
* @return SPI_FLASH_RESULT_OK : Erase OK.
* SPI_FLASH_RESULT_ERR : Erase error.
* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
*/
SpiFlashOpResult SPIEraseSector(uint32_t sector_num);
/**
* @brief Erase some sectors.
* Please do not call this function in SDK.
*
* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
*
* @param uint32_t area_len : Length to erase, should be sector aligned.
*
* @return SPI_FLASH_RESULT_OK : Erase OK.
* SPI_FLASH_RESULT_ERR : Erase error.
* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
*/
SpiFlashOpResult SPIEraseArea(uint32_t start_addr, uint32_t area_len);
/**
* @brief Write Data to Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
*
* @param const uint32_t *src : The pointer to data which is to write.
*
* @param uint32_t len : Length to write, should be 4 bytes aligned.
*
* @return SPI_FLASH_RESULT_OK : Write OK.
* SPI_FLASH_RESULT_ERR : Write error.
* SPI_FLASH_RESULT_TIMEOUT : Write timeout.
*/
SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t *src, int32_t len);
/**
* @brief Read Data from Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
*
* @param uint32_t *dest : The buf to read the data.
*
* @param uint32_t len : Length to read, should be 4 bytes aligned.
*
* @return SPI_FLASH_RESULT_OK : Read OK.
* SPI_FLASH_RESULT_ERR : Read error.
* SPI_FLASH_RESULT_TIMEOUT : Read timeout.
*/
SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t *dest, int32_t len);
/**
* @brief SPI1 go into encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void SPI_Write_Encrypt_Enable(void);
/**
* @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
*
* @param uint32_t *data : The pointer to data which is to write.
*
* @return SPI_FLASH_RESULT_OK : Prepare OK.
* SPI_FLASH_RESULT_ERR : Prepare error.
* SPI_FLASH_RESULT_TIMEOUT : Prepare timeout.
*/
SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t *data);
/**
* @brief SPI1 go out of encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void SPI_Write_Encrypt_Disable(void);
/**
* @brief Encrpto writing data to flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
*
* @param uint32_t *data : The pointer to data which is to write.
*
* @param uint32_t len : Length to write, should be 32 bytes aligned.
*
* @return SPI_FLASH_RESULT_OK : Encrypto write OK.
* SPI_FLASH_RESULT_ERR : Encrypto write error.
* SPI_FLASH_RESULT_TIMEOUT : Encrypto write timeout.
*/
SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t *data, uint32_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_TBCONSOLE_H_
#define _ROM_TBCONSOLE_H_
#ifdef __cplusplus
extern "C" {
#endif
void start_tb_console();
#ifdef __cplusplus
}
#endif
#endif /* _ROM_TBCONSOLE_H_ */

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/*----------------------------------------------------------------------------/
/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012
/----------------------------------------------------------------------------*/
#ifndef _TJPGDEC
#define _TJPGDEC
/*---------------------------------------------------------------------------*/
/* System Configurations */
#define JD_SZBUF 512 /* Size of stream input buffer */
#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
#define JD_USE_SCALE 1 /* Use descaling feature for output */
#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
/*---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
/* These types must be 16-bit, 32-bit or larger integer */
typedef int INT;
typedef unsigned int UINT;
/* These types must be 8-bit integer */
typedef char CHAR;
typedef unsigned char UCHAR;
typedef unsigned char BYTE;
/* These types must be 16-bit integer */
typedef short SHORT;
typedef unsigned short USHORT;
typedef unsigned short WORD;
typedef unsigned short WCHAR;
/* These types must be 32-bit integer */
typedef long LONG;
typedef unsigned long ULONG;
typedef unsigned long DWORD;
/* Error code */
typedef enum {
JDR_OK = 0, /* 0: Succeeded */
JDR_INTR, /* 1: Interrupted by output function */
JDR_INP, /* 2: Device error or wrong termination of input stream */
JDR_MEM1, /* 3: Insufficient memory pool for the image */
JDR_MEM2, /* 4: Insufficient stream input buffer */
JDR_PAR, /* 5: Parameter error */
JDR_FMT1, /* 6: Data format error (may be damaged data) */
JDR_FMT2, /* 7: Right format but not supported */
JDR_FMT3 /* 8: Not supported JPEG standard */
} JRESULT;
/* Rectangular structure */
typedef struct {
WORD left, right, top, bottom;
} JRECT;
/* Decompressor object structure */
typedef struct JDEC JDEC;
struct JDEC {
UINT dctr; /* Number of bytes available in the input buffer */
BYTE* dptr; /* Current data read ptr */
BYTE* inbuf; /* Bit stream input buffer */
BYTE dmsk; /* Current bit in the current read byte */
BYTE scale; /* Output scaling ratio */
BYTE msx, msy; /* MCU size in unit of block (width, height) */
BYTE qtid[3]; /* Quantization table ID of each component */
SHORT dcv[3]; /* Previous DC element of each component */
WORD nrst; /* Restart inverval */
UINT width, height; /* Size of the input image (pixel) */
BYTE* huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */
WORD* huffcode[2][2]; /* Huffman code word tables [id][dcac] */
BYTE* huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */
LONG* qttbl[4]; /* Dequaitizer tables [id] */
void* workbuf; /* Working buffer for IDCT and RGB output */
BYTE* mcubuf; /* Working buffer for the MCU */
void* pool; /* Pointer to available memory pool */
UINT sz_pool; /* Size of momory pool (bytes available) */
UINT (*infunc)(JDEC*, BYTE*, UINT);/* Pointer to jpeg stream input function */
void* device; /* Pointer to I/O device identifiler for the session */
};
/* TJpgDec API functions */
JRESULT jd_prepare (JDEC*, UINT(*)(JDEC*,BYTE*,UINT), void*, UINT, void*);
JRESULT jd_decomp (JDEC*, UINT(*)(JDEC*,void*,JRECT*), BYTE);
#ifdef __cplusplus
}
#endif
#endif /* _TJPGDEC */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_UART_H_
#define _ROM_UART_H_
#include "esp_types.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
#define RX_BUFF_SIZE 0x100
#define TX_BUFF_SIZE 100
//uart int enalbe register ctrl bits
#define UART_RCV_INTEN BIT0
#define UART_TRX_INTEN BIT1
#define UART_LINE_STATUS_INTEN BIT2
//uart int identification ctrl bits
#define UART_INT_FLAG_MASK 0x0E
//uart fifo ctrl bits
#define UART_CLR_RCV_FIFO BIT1
#define UART_CLR_TRX_FIFO BIT2
#define UART_RCVFIFO_TRG_LVL_BITS BIT6
//uart line control bits
#define UART_DIV_LATCH_ACCESS_BIT BIT7
//uart line status bits
#define UART_RCV_DATA_RDY_FLAG BIT0
#define UART_RCV_OVER_FLOW_FLAG BIT1
#define UART_RCV_PARITY_ERR_FLAG BIT2
#define UART_RCV_FRAME_ERR_FLAG BIT3
#define UART_BRK_INT_FLAG BIT4
#define UART_TRX_FIFO_EMPTY_FLAG BIT5
#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg
#define UART_RCV_ERR_FLAG BIT7
//send and receive message frame head
#define FRAME_FLAG 0x7E
typedef enum {
UART_LINE_STATUS_INT_FLAG = 0x06,
UART_RCV_FIFO_INT_FLAG = 0x04,
UART_RCV_TMOUT_INT_FLAG = 0x0C,
UART_TXBUFF_EMPTY_INT_FLAG = 0x02
} UartIntType; //consider bit0 for int_flag
typedef enum {
RCV_ONE_BYTE = 0x0,
RCV_FOUR_BYTE = 0x1,
RCV_EIGHT_BYTE = 0x2,
RCV_FOURTEEN_BYTE = 0x3
} UartRcvFifoTrgLvl;
typedef enum {
FIVE_BITS = 0x0,
SIX_BITS = 0x1,
SEVEN_BITS = 0x2,
EIGHT_BITS = 0x3
} UartBitsNum4Char;
typedef enum {
ONE_STOP_BIT = 1,
ONE_HALF_STOP_BIT = 2,
TWO_STOP_BIT = 3
} UartStopBitsNum;
typedef enum {
NONE_BITS = 0,
ODD_BITS = 2,
EVEN_BITS = 3
} UartParityMode;
typedef enum {
STICK_PARITY_DIS = 0,
STICK_PARITY_EN = 2
} UartExistParity;
typedef enum {
BIT_RATE_9600 = 9600,
BIT_RATE_19200 = 19200,
BIT_RATE_38400 = 38400,
BIT_RATE_57600 = 57600,
BIT_RATE_115200 = 115200,
BIT_RATE_230400 = 230400,
BIT_RATE_460800 = 460800,
BIT_RATE_921600 = 921600
} UartBautRate;
typedef enum {
NONE_CTRL,
HARDWARE_CTRL,
XON_XOFF_CTRL
} UartFlowCtrl;
typedef enum {
EMPTY,
UNDER_WRITE,
WRITE_OVER
} RcvMsgBuffState;
typedef struct {
// uint32_t RcvBuffSize;
uint8_t *pRcvMsgBuff;
uint8_t *pWritePos;
uint8_t *pReadPos;
uint8_t TrigLvl;
RcvMsgBuffState BuffState;
} RcvMsgBuff;
typedef struct {
uint32_t TrxBuffSize;
uint8_t *pTrxBuff;
} TrxMsgBuff;
typedef enum {
BAUD_RATE_DET,
WAIT_SYNC_FRM,
SRCH_MSG_HEAD,
RCV_MSG_BODY,
RCV_ESC_CHAR,
} RcvMsgState;
typedef struct {
UartBautRate baut_rate;
UartBitsNum4Char data_bits;
UartExistParity exist_parity;
UartParityMode parity; // chip size in byte
UartStopBitsNum stop_bits;
UartFlowCtrl flow_ctrl;
uint8_t buff_uart_no; //indicate which uart use tx/rx buffer
uint8_t tx_uart_no;
RcvMsgBuff rcv_buff;
// TrxMsgBuff trx_buff;
RcvMsgState rcv_state;
int received;
} UartDevice;
/**
* @brief Init uart device struct value and reset uart0/uart1 rx.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void uartAttach(void);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, else for UART1.
*
* @param uint32_t clock : clock used by uart module, to adjust baudrate.
*
* @return None
*/
void Uart_Init(uint8_t uart_no, uint32_t clock);
/**
* @brief Modify uart baudrate.
* This function will reset RX/TX fifo for uart.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @param uint32_t DivLatchValue : (clock << 4)/baudrate.
*
* @return None
*/
void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected;
* 1, two UART modules, hard to detect, detect and return.
*
* @return None
*/
int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync);
/**
* @brief Switch printf channel of uart_tx_one_char.
* Please do not call this function when printf.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None
*/
void uart_tx_switch(uint8_t uart_no);
/**
* @brief Switch message exchange channel for UART download booting.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None
*/
void uart_buff_switch(uint8_t uart_no);
/**
* @brief Output a char to printf channel, wait until fifo not full.
*
* @param None
*
* @return OK.
*/
STATUS uart_tx_one_char(uint8_t TxChar);
/**
* @brief Output a char to message exchange channel, wait until fifo not full.
* Please do not call this function in SDK.
*
* @param None
*
* @return OK.
*/
STATUS uart_tx_one_char2(uint8_t TxChar);//for send message
/**
* @brief Wait until uart tx full empty.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None.
*/
void uart_tx_flush(uint8_t uart_no);
/**
* @brief Wait until uart tx full empty and the last char send ok.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None.
*/
void uart_tx_wait_idle(uint8_t uart_no);
/**
* @brief Get an input char from message channel.
* Please do not call this function in SDK.
*
* @param uint8_t *pRxChar : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS uart_rx_one_char(uint8_t *pRxChar);
/**
* @brief Get an input char to message channel, wait until successful.
* Please do not call this function in SDK.
*
* @param None
*
* @return char : input char value.
*/
char uart_rx_one_char_block(void);
/**
* @brief Get an input string line from message channel.
* Please do not call this function in SDK.
*
* @param uint8_t *pString : the pointer to store the string.
*
* @param uint8_t MaxStrlen : the max string length, incude '\0'.
*
* @return OK.
*/
STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
/**
* @brief Process uart recevied information in the interrupt handler.
* Please do not call this function in SDK.
*
* @param void *para : the message receive buffer.
*
* @return None
*/
void uart_rx_intr_handler(void *para);
/**
* @brief Get an char from receive buffer.
* Please do not call this function in SDK.
*
* @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
*
* @param uint8_t *pRxByte : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
/**
* @brief Get all chars from receive buffer.
* Please do not call this function in SDK.
*
* @param uint8_t *pCmdLn : the pointer to store the string.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS UartGetCmdLn(uint8_t *pCmdLn);
/**
* @brief Get uart configuration struct.
* Please do not call this function in SDK.
*
* @param None
*
* @return UartDevice * : uart configuration struct pointer.
*/
UartDevice *GetUartDevice(void);
/**
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to output string.
*
* @param int len : the string length.
*
* @return None.
*/
void send_packet(uint8_t *p, int len);
/**
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to input string.
*
* @param int len : If string length > len, the string will be truncated.
*
* @param uint8_t is_sync : 0, only one UART module;
* 1, two UART modules.
*
* @return int : the length of the string.
*/
int recv_packet(uint8_t *p, int len, uint8_t is_sync);
/**
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *pData : the pointer to input string.
*
* @param uint16_t DataLen : the string length.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
/**
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *pData : the pointer to input string.
*
* @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated.
*
* @param uint8_t is_sync : 0, only one UART module;
* 1, two UART modules.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync);
extern UartDevice UartDev;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_UART_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_BB_REG_H_
#define _SOC_BB_REG_H_
#define apb_bb_offset 0x6001c000
#define BB_DLY apb_bb_offset + 0x00009b00 // reg 00
#define BB_TEST apb_bb_offset + 0x00009b08 // reg 02
#define BB_TM1 apb_bb_offset + 0x00009b0c // reg 03
#define BB_TM_CNTL apb_bb_offset + 0x00009b14 // reg 05
#define BB_DEL_CNTL apb_bb_offset + 0x00009b28 // reg 10
#define BB_PARAL_CNTL apb_bb_offset + 0x00009b2c // reg 11
#define BB_FSM1 apb_bb_offset + 0x00009b44 // reg 17
#define BB_MXG apb_bb_offset + 0x00009b48 // reg 18
#define BB_MNOF apb_bb_offset + 0x00009b4c // reg 19
#define BB_SIZE apb_bb_offset + 0x00009b50 // reg 20
#define BB_TM3a apb_bb_offset + 0x00009b54 // reg 21
#define BB_TM4a apb_bb_offset + 0x00009b58 // reg 22
#define BB_GAIN apb_bb_offset + 0x00009b5c // reg 23
#define BB_CNTL apb_bb_offset + 0x00009b60 // reg 24
#define BB_CAD apb_bb_offset + 0x00009b64 // reg 25
#define BB_DET apb_bb_offset + 0x00009b68 // reg 26
#define BB_DETL apb_bb_offset + 0x00009b6c // reg 27
#define BB_MASK_PCLL apb_bb_offset + 0x00009d08 // reg 66
#define BB_MASK_PCLH apb_bb_offset + 0x00009d0c // reg 67
#define BB_RX_CTRL4 apb_bb_offset + 0x00009d10 // reg 68
#define BB_RX_CTRL apb_bb_offset + 0x00009d1c // reg 71
#define BB_RX_CTRL2 apb_bb_offset + 0x00009d20 // reg 72
#define BB_RX_CTRL3 apb_bb_offset + 0x00009d24 // reg 73
#define BB_DEL4 apb_bb_offset + 0x00009d40 // reg 80
#define BB_TM5 apb_bb_offset + 0x00009d44 // reg 81
#define BB_TM6 apb_bb_offset + 0x00009d48 // reg 82
#define BB_PMCTRL apb_bb_offset + 0x00009d4c // reg 83
#define BB_PWR apb_bb_offset + 0x00009d68 // reg 90
#define BB_BCTRL2 apb_bb_offset + 0x00009d70 // reg 92
#define BB_MASK_PL apb_bb_offset + 0x00009884 // reg 97
#define BB_MASK_PCHL apb_bb_offset + 0x00009888 // reg 98
#define BB_MASK_PCHH apb_bb_offset + 0x0000988c // reg 99
#define BB_MASK_CL apb_bb_offset + 0x0000989c // reg 103
#define BB_TONE apb_bb_offset + 0x000098a0 // reg 104
#define BB_MASK_CH apb_bb_offset + 0x000098d4 // reg 117
#define BB_SER apb_bb_offset + 0x000098ec // reg 123
#define BB_GN_TB apb_bb_offset + 0x00009e00 // reg 128
#define BB_MODE apb_bb_offset + 0x00009c00 // reg 640
#define BB_TXCTRL apb_bb_offset + 0x00009c04 // reg 641
#define BB_BCTRL3 apb_bb_offset + 0x00009c08 // reg 642
#define BB_BCTRL apb_bb_offset + 0x00009c28 // reg 650
#define BB_SMCTRL apb_bb_offset + 0x00009c48 // reg 658
#define BB_SMCTRL2 apb_bb_offset + 0x00009c4C // reg 659
#define BB_TXCNT apb_bb_offset + 0x00009c58 // reg 662
#define BB_RXCTRL apb_bb_offset + 0x00009c68 // reg 666
#define BB_TXGAIN apb_bb_offset + 0x00009900 // reg 704
#define BB_RXS_CNTL apb_bb_offset + 0x00009988 // reg 738
#define BB_MASK2_PCLL apb_bb_offset + 0x000099a8 // reg 746
#define BB_MASK2_PCLH apb_bb_offset + 0x000099ac // reg 747
#define BB_MASK_PH apb_bb_offset + 0x000099b0 // reg 748
#define BB_MASK2_PCHL apb_bb_offset + 0x000099b8 // reg 750
#define BB_MASK2_PCHH apb_bb_offset + 0x000099bc // reg 751
//
#define BB_TX_TONE_CNTL apb_bb_offset + 0x000099f0 // reg 764
#define BB_ADD_CNTL0 apb_bb_offset + 0x00009a28 // reg 778
#define BB_ADD_CNTL2 apb_bb_offset + 0x00009a2c // reg 779
#define BB_GAIN_CNTL0 apb_bb_offset + 0x00009a34 // reg 781
#define BB_GAIN_CNTL1 apb_bb_offset + 0x00009a38 // reg 782
#define BB_GAIN_CNTL2 apb_bb_offset + 0x00009a3c // reg 783
#define BB_AGCMEM_CTRL apb_bb_offset + 0x00009a68 // reg 794
#define BB_11B_RECORD apb_bb_offset + 0x00009808 // reg 802
#define BB_FILTER_CNTL apb_bb_offset + 0x0000980c // reg 803
#define BB_ANALOG_CTRL1 apb_bb_offset + 0x00009838
#define BB_ANALOG_CTRL2 apb_bb_offset + 0x0000983c //reg 815
#define BB_ANALOG_CTRL3 apb_bb_offset + 0x00009840 //reg 816
#define BB_RFCFG_CTRL0 apb_bb_offset + 0x00009844 //reg 817
#define BB_RFCFG_CTRL1 apb_bb_offset + 0x00009848 //reg 818
#define BB_ADD_CNTL1 apb_bb_offset + 0x00009860 //reg824
#define BB_PA_CNTL apb_bb_offset + 0x00009864 //reg825
#define BB_RFCFG_CTRL2 apb_bb_offset + 0x0000986c //reg827
#define BB_RXDEL_CTRL apb_bb_offset + 0x00009d18
#define BB_RXLENGTH_CTRL apb_bb_offset + 0x00009d1c
#endif /* _SOC_BB_REG_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_BOOT_MODE_H_
#define _SOC_BOOT_MODE_H_
#include "soc.h"
/*SPI Boot*/
#define IS_1XXXX(v) (((v)&0x10)==0x10)
/*HSPI Boot*/
#define IS_010XX(v) (((v)&0x1c)==0x08)
/*Download Boot, SDIO/UART0/UART1*/
#define IS_00XXX(v) (((v)&0x18)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
#define IS_00X00(v) (((v)&0x1b)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
#define IS_00X01(v) (((v)&0x1b)==0x01)
/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
#define IS_00X10(v) (((v)&0x1b)==0x02)
/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
#define IS_00X11(v) (((v)&0x1b)==0x03)
/*ATE/ANALOG Mode*/
#define IS_01110(v) (((v)&0x1f)==0x0e)
/*Diagnostic Mode+UART0 download Mode*/
#define IS_01111(v) (((v)&0x1f)==0x0f)
/*legacy SPI Boot*/
#define IS_01100(v) (((v)&0x1f)==0x0c)
/*SDIO_Slave download Mode V1.1*/
#define IS_01101(v) (((v)&0x1f)==0x0d)
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP))
/*do not include download mode*/
#define ETS_IS_UART_BOOT() IS_01111(BOOT_MODE_GET())
/*all spi boot including spi/hspi/legacy*/
#define ETS_IS_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET()))
/*all faster spi boot including spi/hspi*/
#define ETS_IS_FAST_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()))
/*all spi boot including spi/legacy*/
#define ETS_IS_SPI_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET()))
/*all spi boot including hspi/legacy*/
#define ETS_IS_HSPI_FLASH_BOOT() IS_010XX(BOOT_MODE_GET())
/*all sdio V2 of failing edge input, failing edge output*/
#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_00X00(BOOT_MODE_GET())
/*all sdio V2 of failing edge input, raising edge output*/
#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_00X01(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_00X10(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, raising edge output*/
#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_00X11(BOOT_MODE_GET())
/*all sdio V1 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_01101(BOOT_MODE_GET())
/*do not include download mode*/
#define ETS_IS_SDIO_BOOT() IS_01101(BOOT_MODE_GET())
/*joint download boot*/
#define ETS_IS_SDIO_UART_BOOT() IS_00XXX(BOOT_MODE_GET())
/*ATE mode*/
#define ETS_IS_ATE_BOOT() IS_01110(BOOT_MODE_GET())
/*A bit to control flash boot print*/
#define ETS_IS_PRINT_BOOT() (BOOT_MODE_GET() & 0x2)
/*used by ETS_IS_SDIO_UART_BOOT*/
#define SEL_NO_BOOT 0
#define SEL_SDIO_BOOT BIT0
#define SEL_UART_BOOT BIT1
#endif /* _SOC_BOOT_MODE_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_CPU_H
#define _SOC_CPU_H
#include "xtensa/corebits.h"
/* C macros for xtensa special register read/write/exchange */
#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval));
#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval));
#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval));
/* Return true if the CPU is in an interrupt context
(PS.UM == 0)
*/
static inline bool cpu_in_interrupt_context(void)
{
uint32_t ps;
RSR(PS, ps);
return (ps & PS_UM) == 0;
}
/* Functions to set page attributes for Region Protection option in the CPU.
* See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
*/
static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
{
asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
}
static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
{
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
}
/* Make page 0 access raise an exception.
* Also protect some other unused pages so we can catch weirdness.
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*/
static inline void cpu_configure_region_protection()
{
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
cpu_write_dtlb(pages_to_protect[i], 0xf);
cpu_write_itlb(pages_to_protect[i], 0xf);
}
cpu_write_dtlb(0x20000000, 0);
cpu_write_itlb(0x20000000, 0);
}
/*
* @brief Set CPU frequency to the value defined in menuconfig
*
* Called from cpu_start.c, not intended to be called from other places.
* This is a temporary function which will be replaced once dynamic
* CPU frequency changing is implemented.
*/
void esp_set_cpu_freq(void);
#endif

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_EFUSE_REG_H_
#define _SOC_EFUSE_REG_H_
#include "soc.h"
#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000)
/* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[27:20] ;default: 8'b0 ; */
/*description: read for flash_crypt_cnt*/
#define EFUSE_RD_FLASH_CRYPT_CNT 0x000000FF
#define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S))
#define EFUSE_RD_FLASH_CRYPT_CNT_V 0xFF
#define EFUSE_RD_FLASH_CRYPT_CNT_S 20
/* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; */
/*description: read for efuse_rd_disable*/
#define EFUSE_RD_EFUSE_RD_DIS 0x0000000F
#define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S))
#define EFUSE_RD_EFUSE_RD_DIS_V 0xF
#define EFUSE_RD_EFUSE_RD_DIS_S 16
/* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; */
/*description: read for efuse_wr_disable*/
#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF
#define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S))
#define EFUSE_RD_EFUSE_WR_DIS_V 0xFFFF
#define EFUSE_RD_EFUSE_WR_DIS_S 0
#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004)
/* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: read for low 32bit WIFI_MAC_Address*/
#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF
#define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S))
#define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF
#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0
#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008)
/* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; */
/*description: read for high 24bit WIFI_MAC_Address*/
#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF
#define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S))
#define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xFFFFFF
#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0
#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c)
/* EFUSE_RD_CHIP_VER_RESERVE : RO ;bitpos:[16:9] ;default: 8'b0 ; */
/*description: */
#define EFUSE_RD_CHIP_VER_RESERVE 0x000000FF
#define EFUSE_RD_CHIP_VER_RESERVE_M ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S))
#define EFUSE_RD_CHIP_VER_RESERVE_V 0xFF
#define EFUSE_RD_CHIP_VER_RESERVE_S 9
/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */
/*description: read for SPI_pad_config_hd*/
#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F
#define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S))
#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1F
#define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4
/* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3))
#define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3))
#define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1
#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3
/* EFUSE_RD_CHIP_VER_32PAD : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define EFUSE_RD_CHIP_VER_32PAD (BIT(2))
#define EFUSE_RD_CHIP_VER_32PAD_M (BIT(2))
#define EFUSE_RD_CHIP_VER_32PAD_V 0x1
#define EFUSE_RD_CHIP_VER_32PAD_S 2
/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1))
#define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1))
#define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1
#define EFUSE_RD_CHIP_VER_DIS_BT_S 1
/* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0))
#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0))
#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1
#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0
#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010)
/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */
/*description: read for sdio_force*/
#define EFUSE_RD_SDIO_FORCE (BIT(16))
#define EFUSE_RD_SDIO_FORCE_M (BIT(16))
#define EFUSE_RD_SDIO_FORCE_V 0x1
#define EFUSE_RD_SDIO_FORCE_S 16
/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */
/*description: read for SDIO_TIEH*/
#define EFUSE_RD_SDIO_TIEH (BIT(15))
#define EFUSE_RD_SDIO_TIEH_M (BIT(15))
#define EFUSE_RD_SDIO_TIEH_V 0x1
#define EFUSE_RD_SDIO_TIEH_S 15
/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: read for XPD_SDIO_REG*/
#define EFUSE_RD_XPD_SDIO_REG (BIT(14))
#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14))
#define EFUSE_RD_XPD_SDIO_REG_V 0x1
#define EFUSE_RD_XPD_SDIO_REG_S 14
/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */
/*description: */
#define EFUSE_RD_SDIO_DREFL 0x00000003
#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S))
#define EFUSE_RD_SDIO_DREFL_V 0x3
#define EFUSE_RD_SDIO_DREFL_S 12
/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */
/*description: */
#define EFUSE_RD_SDIO_DREFM 0x00000003
#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S))
#define EFUSE_RD_SDIO_DREFM_V 0x3
#define EFUSE_RD_SDIO_DREFM_S 10
/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */
/*description: */
#define EFUSE_RD_SDIO_DREFH 0x00000003
#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S))
#define EFUSE_RD_SDIO_DREFH_V 0x3
#define EFUSE_RD_SDIO_DREFH_S 8
/* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: */
#define EFUSE_RD_CK8M_FREQ 0x000000FF
#define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S))
#define EFUSE_RD_CK8M_FREQ_V 0xFF
#define EFUSE_RD_CK8M_FREQ_S 0
#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014)
/* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; */
/*description: read for flash_crypt_config*/
#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F
#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S))
#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF
#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28
/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */
/*description: */
#define EFUSE_RD_INST_CONFIG 0x000000FF
#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S))
#define EFUSE_RD_INST_CONFIG_V 0xFF
#define EFUSE_RD_INST_CONFIG_S 20
/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */
/*description: read for SPI_pad_config_cs0*/
#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F
#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S))
#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1F
#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15
/* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; */
/*description: read for SPI_pad_config_d*/
#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001F
#define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S))
#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1F
#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10
/* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; */
/*description: read for SPI_pad_config_q*/
#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001F
#define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S))
#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1F
#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5
/* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; */
/*description: read for SPI_pad_config_clk*/
#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001F
#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S))
#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1F
#define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0
#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018)
/* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: read for key_status*/
#define EFUSE_RD_KEY_STATUS (BIT(10))
#define EFUSE_RD_KEY_STATUS_M (BIT(10))
#define EFUSE_RD_KEY_STATUS_V 0x1
#define EFUSE_RD_KEY_STATUS_S 10
/* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: read for download_dis_cache*/
#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9))
#define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9))
#define EFUSE_RD_DISABLE_DL_CACHE_V 0x1
#define EFUSE_RD_DISABLE_DL_CACHE_S 9
/* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: read for download_dis_decrypt*/
#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8))
#define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8))
#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1
#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8
/* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: read for download_dis_encrypt*/
#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7))
#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7))
#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1
#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7
/* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: read for JTAG_disable*/
#define EFUSE_RD_DISABLE_JTAG (BIT(6))
#define EFUSE_RD_DISABLE_JTAG_M (BIT(6))
#define EFUSE_RD_DISABLE_JTAG_V 0x1
#define EFUSE_RD_DISABLE_JTAG_S 6
/* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: read for abstract_done_1*/
#define EFUSE_RD_ABS_DONE_1 (BIT(5))
#define EFUSE_RD_ABS_DONE_1_M (BIT(5))
#define EFUSE_RD_ABS_DONE_1_V 0x1
#define EFUSE_RD_ABS_DONE_1_S 5
/* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: read for abstract_done_0*/
#define EFUSE_RD_ABS_DONE_0 (BIT(4))
#define EFUSE_RD_ABS_DONE_0_M (BIT(4))
#define EFUSE_RD_ABS_DONE_0_V 0x1
#define EFUSE_RD_ABS_DONE_0_S 4
/* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3))
#define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3))
#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1
#define EFUSE_RD_DISABLE_SDIO_HOST_S 3
/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: read for console_debug_disable*/
#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2))
#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2))
#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1
#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2
/* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: read for coding_scheme*/
#define EFUSE_RD_CODING_SCHEME 0x00000003
#define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S))
#define EFUSE_RD_CODING_SCHEME_V 0x3
#define EFUSE_RD_CODING_SCHEME_S 0
#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c)
/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[27:20] ;default: 8'b0 ; */
/*description: program for flash_crypt_cnt*/
#define EFUSE_FLASH_CRYPT_CNT 0x000000FF
#define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S))
#define EFUSE_FLASH_CRYPT_CNT_V 0xFF
#define EFUSE_FLASH_CRYPT_CNT_S 20
/* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; */
/*description: program for efuse_rd_disable*/
#define EFUSE_RD_DIS 0x0000000F
#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
#define EFUSE_RD_DIS_V 0xF
#define EFUSE_RD_DIS_S 16
/* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
/*description: program for efuse_wr_disable*/
#define EFUSE_WR_DIS 0x0000FFFF
#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
#define EFUSE_WR_DIS_V 0xFFFF
#define EFUSE_WR_DIS_S 0
#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020)
/* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: program for low 32bit WIFI_MAC_Address*/
#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF
#define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S))
#define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF
#define EFUSE_WIFI_MAC_CRC_LOW_S 0
#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024)
/* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; */
/*description: program for high 24bit WIFI_MAC_Address*/
#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF
#define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S))
#define EFUSE_WIFI_MAC_CRC_HIGH_V 0xFFFFFF
#define EFUSE_WIFI_MAC_CRC_HIGH_S 0
#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028)
/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[16:9] ;default: 8'b0 ; */
/*description: */
#define EFUSE_CHIP_VER_RESERVE 0x000000FF
#define EFUSE_CHIP_VER_RESERVE_M ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S))
#define EFUSE_CHIP_VER_RESERVE_V 0xFF
#define EFUSE_CHIP_VER_RESERVE_S 9
/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */
/*description: program for SPI_pad_config_hd*/
#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F
#define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S))
#define EFUSE_SPI_PAD_CONFIG_HD_V 0x1F
#define EFUSE_SPI_PAD_CONFIG_HD_S 4
/* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3))
#define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3))
#define EFUSE_CHIP_VER_DIS_CACHE_V 0x1
#define EFUSE_CHIP_VER_DIS_CACHE_S 3
/* EFUSE_CHIP_VER_32PAD : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define EFUSE_CHIP_VER_32PAD (BIT(2))
#define EFUSE_CHIP_VER_32PAD_M (BIT(2))
#define EFUSE_CHIP_VER_32PAD_V 0x1
#define EFUSE_CHIP_VER_32PAD_S 2
/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define EFUSE_CHIP_VER_DIS_BT (BIT(1))
#define EFUSE_CHIP_VER_DIS_BT_M (BIT(1))
#define EFUSE_CHIP_VER_DIS_BT_V 0x1
#define EFUSE_CHIP_VER_DIS_BT_S 1
/* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0))
#define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0))
#define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1
#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0
#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c)
/* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: program for sdio_force*/
#define EFUSE_SDIO_FORCE (BIT(16))
#define EFUSE_SDIO_FORCE_M (BIT(16))
#define EFUSE_SDIO_FORCE_V 0x1
#define EFUSE_SDIO_FORCE_S 16
/* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: program for SDIO_TIEH*/
#define EFUSE_SDIO_TIEH (BIT(15))
#define EFUSE_SDIO_TIEH_M (BIT(15))
#define EFUSE_SDIO_TIEH_V 0x1
#define EFUSE_SDIO_TIEH_S 15
/* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: program for XPD_SDIO_REG*/
#define EFUSE_XPD_SDIO_REG (BIT(14))
#define EFUSE_XPD_SDIO_REG_M (BIT(14))
#define EFUSE_XPD_SDIO_REG_V 0x1
#define EFUSE_XPD_SDIO_REG_S 14
/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
/*description: */
#define EFUSE_SDIO_DREFL 0x00000003
#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S))
#define EFUSE_SDIO_DREFL_V 0x3
#define EFUSE_SDIO_DREFL_S 12
/* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
/*description: */
#define EFUSE_SDIO_DREFM 0x00000003
#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S))
#define EFUSE_SDIO_DREFM_V 0x3
#define EFUSE_SDIO_DREFM_S 10
/* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
/*description: */
#define EFUSE_SDIO_DREFH 0x00000003
#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S))
#define EFUSE_SDIO_DREFH_V 0x3
#define EFUSE_SDIO_DREFH_S 8
/* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: */
#define EFUSE_CK8M_FREQ 0x000000FF
#define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S))
#define EFUSE_CK8M_FREQ_V 0xFF
#define EFUSE_CK8M_FREQ_S 0
#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030)
/* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; */
/*description: program for flash_crypt_config*/
#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F
#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S))
#define EFUSE_FLASH_CRYPT_CONFIG_V 0xF
#define EFUSE_FLASH_CRYPT_CONFIG_S 28
/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */
/*description: */
#define EFUSE_INST_CONFIG 0x000000FF
#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S))
#define EFUSE_INST_CONFIG_V 0xFF
#define EFUSE_INST_CONFIG_S 20
/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */
/*description: program for SPI_pad_config_cs0*/
#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F
#define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S))
#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1F
#define EFUSE_SPI_PAD_CONFIG_CS0_S 15
/* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; */
/*description: program for SPI_pad_config_d*/
#define EFUSE_SPI_PAD_CONFIG_D 0x0000001F
#define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S))
#define EFUSE_SPI_PAD_CONFIG_D_V 0x1F
#define EFUSE_SPI_PAD_CONFIG_D_S 10
/* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; */
/*description: program for SPI_pad_config_q*/
#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001F
#define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S))
#define EFUSE_SPI_PAD_CONFIG_Q_V 0x1F
#define EFUSE_SPI_PAD_CONFIG_Q_S 5
/* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; */
/*description: program for SPI_pad_config_clk*/
#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001F
#define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S))
#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1F
#define EFUSE_SPI_PAD_CONFIG_CLK_S 0
#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034)
/* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: program for key_status*/
#define EFUSE_KEY_STATUS (BIT(10))
#define EFUSE_KEY_STATUS_M (BIT(10))
#define EFUSE_KEY_STATUS_V 0x1
#define EFUSE_KEY_STATUS_S 10
/* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: program for download_dis_cache*/
#define EFUSE_DISABLE_DL_CACHE (BIT(9))
#define EFUSE_DISABLE_DL_CACHE_M (BIT(9))
#define EFUSE_DISABLE_DL_CACHE_V 0x1
#define EFUSE_DISABLE_DL_CACHE_S 9
/* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: program for download_dis_decrypt*/
#define EFUSE_DISABLE_DL_DECRYPT (BIT(8))
#define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8))
#define EFUSE_DISABLE_DL_DECRYPT_V 0x1
#define EFUSE_DISABLE_DL_DECRYPT_S 8
/* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: program for download_dis_encrypt*/
#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7))
#define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7))
#define EFUSE_DISABLE_DL_ENCRYPT_V 0x1
#define EFUSE_DISABLE_DL_ENCRYPT_S 7
/* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: program for JTAG_disable*/
#define EFUSE_DISABLE_JTAG (BIT(6))
#define EFUSE_DISABLE_JTAG_M (BIT(6))
#define EFUSE_DISABLE_JTAG_V 0x1
#define EFUSE_DISABLE_JTAG_S 6
/* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: program for abstract_done_1*/
#define EFUSE_ABS_DONE_1 (BIT(5))
#define EFUSE_ABS_DONE_1_M (BIT(5))
#define EFUSE_ABS_DONE_1_V 0x1
#define EFUSE_ABS_DONE_1_S 5
/* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: program for abstract_done_0*/
#define EFUSE_ABS_DONE_0 (BIT(4))
#define EFUSE_ABS_DONE_0_M (BIT(4))
#define EFUSE_ABS_DONE_0_V 0x1
#define EFUSE_ABS_DONE_0_S 4
/* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define EFUSE_DISABLE_SDIO_HOST (BIT(3))
#define EFUSE_DISABLE_SDIO_HOST_M (BIT(3))
#define EFUSE_DISABLE_SDIO_HOST_V 0x1
#define EFUSE_DISABLE_SDIO_HOST_S 3
/* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: program for console_debug_disable*/
#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2))
#define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2))
#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1
#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2
/* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: program for coding_scheme*/
#define EFUSE_CODING_SCHEME 0x00000003
#define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S))
#define EFUSE_CODING_SCHEME_V 0x3
#define EFUSE_CODING_SCHEME_S 0
#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038)
/* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK1*/
#define EFUSE_BLK1_DOUT0 0xFFFFFFFF
#define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S))
#define EFUSE_BLK1_DOUT0_V 0xFFFFFFFF
#define EFUSE_BLK1_DOUT0_S 0
#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c)
/* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK1*/
#define EFUSE_BLK1_DOUT1 0xFFFFFFFF
#define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S))
#define EFUSE_BLK1_DOUT1_V 0xFFFFFFFF
#define EFUSE_BLK1_DOUT1_S 0
#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040)
/* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK1*/
#define EFUSE_BLK1_DOUT2 0xFFFFFFFF
#define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S))
#define EFUSE_BLK1_DOUT2_V 0xFFFFFFFF
#define EFUSE_BLK1_DOUT2_S 0
#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044)
/* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK1*/
#define EFUSE_BLK1_DOUT3 0xFFFFFFFF
#define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S))
#define EFUSE_BLK1_DOUT3_V 0xFFFFFFFF
#define EFUSE_BLK1_DOUT3_S 0
#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048)
/* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK1*/
#define EFUSE_BLK1_DOUT4 0xFFFFFFFF
#define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S))
#define EFUSE_BLK1_DOUT4_V 0xFFFFFFFF
#define EFUSE_BLK1_DOUT4_S 0
#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c)
/* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK1*/
#define EFUSE_BLK1_DOUT5 0xFFFFFFFF
#define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S))
#define EFUSE_BLK1_DOUT5_V 0xFFFFFFFF
#define EFUSE_BLK1_DOUT5_S 0
#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050)
/* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK1*/
#define EFUSE_BLK1_DOUT6 0xFFFFFFFF
#define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S))
#define EFUSE_BLK1_DOUT6_V 0xFFFFFFFF
#define EFUSE_BLK1_DOUT6_S 0
#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054)
/* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK1*/
#define EFUSE_BLK1_DOUT7 0xFFFFFFFF
#define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S))
#define EFUSE_BLK1_DOUT7_V 0xFFFFFFFF
#define EFUSE_BLK1_DOUT7_S 0
#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058)
/* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK2*/
#define EFUSE_BLK2_DOUT0 0xFFFFFFFF
#define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S))
#define EFUSE_BLK2_DOUT0_V 0xFFFFFFFF
#define EFUSE_BLK2_DOUT0_S 0
#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c)
/* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK2*/
#define EFUSE_BLK2_DOUT1 0xFFFFFFFF
#define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S))
#define EFUSE_BLK2_DOUT1_V 0xFFFFFFFF
#define EFUSE_BLK2_DOUT1_S 0
#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060)
/* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK2*/
#define EFUSE_BLK2_DOUT2 0xFFFFFFFF
#define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S))
#define EFUSE_BLK2_DOUT2_V 0xFFFFFFFF
#define EFUSE_BLK2_DOUT2_S 0
#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064)
/* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK2*/
#define EFUSE_BLK2_DOUT3 0xFFFFFFFF
#define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S))
#define EFUSE_BLK2_DOUT3_V 0xFFFFFFFF
#define EFUSE_BLK2_DOUT3_S 0
#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068)
/* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK2*/
#define EFUSE_BLK2_DOUT4 0xFFFFFFFF
#define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S))
#define EFUSE_BLK2_DOUT4_V 0xFFFFFFFF
#define EFUSE_BLK2_DOUT4_S 0
#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c)
/* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK2*/
#define EFUSE_BLK2_DOUT5 0xFFFFFFFF
#define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S))
#define EFUSE_BLK2_DOUT5_V 0xFFFFFFFF
#define EFUSE_BLK2_DOUT5_S 0
#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070)
/* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK2*/
#define EFUSE_BLK2_DOUT6 0xFFFFFFFF
#define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S))
#define EFUSE_BLK2_DOUT6_V 0xFFFFFFFF
#define EFUSE_BLK2_DOUT6_S 0
#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074)
/* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK2*/
#define EFUSE_BLK2_DOUT7 0xFFFFFFFF
#define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S))
#define EFUSE_BLK2_DOUT7_V 0xFFFFFFFF
#define EFUSE_BLK2_DOUT7_S 0
#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078)
/* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK3*/
#define EFUSE_BLK3_DOUT0 0xFFFFFFFF
#define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S))
#define EFUSE_BLK3_DOUT0_V 0xFFFFFFFF
#define EFUSE_BLK3_DOUT0_S 0
#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c)
/* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK3*/
#define EFUSE_BLK3_DOUT1 0xFFFFFFFF
#define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S))
#define EFUSE_BLK3_DOUT1_V 0xFFFFFFFF
#define EFUSE_BLK3_DOUT1_S 0
#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080)
/* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK3*/
#define EFUSE_BLK3_DOUT2 0xFFFFFFFF
#define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S))
#define EFUSE_BLK3_DOUT2_V 0xFFFFFFFF
#define EFUSE_BLK3_DOUT2_S 0
#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084)
/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK3*/
#define EFUSE_BLK3_DOUT3 0xFFFFFFFF
#define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S))
#define EFUSE_BLK3_DOUT3_V 0xFFFFFFFF
#define EFUSE_BLK3_DOUT3_S 0
#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088)
/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK3*/
#define EFUSE_BLK3_DOUT4 0xFFFFFFFF
#define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S))
#define EFUSE_BLK3_DOUT4_V 0xFFFFFFFF
#define EFUSE_BLK3_DOUT4_S 0
#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c)
/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK3*/
#define EFUSE_BLK3_DOUT5 0xFFFFFFFF
#define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S))
#define EFUSE_BLK3_DOUT5_V 0xFFFFFFFF
#define EFUSE_BLK3_DOUT5_S 0
#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090)
/* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK3*/
#define EFUSE_BLK3_DOUT6 0xFFFFFFFF
#define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S))
#define EFUSE_BLK3_DOUT6_V 0xFFFFFFFF
#define EFUSE_BLK3_DOUT6_S 0
#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094)
/* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: read for BLOCK3*/
#define EFUSE_BLK3_DOUT7 0xFFFFFFFF
#define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S))
#define EFUSE_BLK3_DOUT7_V 0xFFFFFFFF
#define EFUSE_BLK3_DOUT7_S 0
#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098)
/* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK1*/
#define EFUSE_BLK1_DIN0 0xFFFFFFFF
#define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S))
#define EFUSE_BLK1_DIN0_V 0xFFFFFFFF
#define EFUSE_BLK1_DIN0_S 0
#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c)
/* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK1*/
#define EFUSE_BLK1_DIN1 0xFFFFFFFF
#define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S))
#define EFUSE_BLK1_DIN1_V 0xFFFFFFFF
#define EFUSE_BLK1_DIN1_S 0
#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0)
/* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK1*/
#define EFUSE_BLK1_DIN2 0xFFFFFFFF
#define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S))
#define EFUSE_BLK1_DIN2_V 0xFFFFFFFF
#define EFUSE_BLK1_DIN2_S 0
#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4)
/* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK1*/
#define EFUSE_BLK1_DIN3 0xFFFFFFFF
#define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S))
#define EFUSE_BLK1_DIN3_V 0xFFFFFFFF
#define EFUSE_BLK1_DIN3_S 0
#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8)
/* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK1*/
#define EFUSE_BLK1_DIN4 0xFFFFFFFF
#define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S))
#define EFUSE_BLK1_DIN4_V 0xFFFFFFFF
#define EFUSE_BLK1_DIN4_S 0
#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac)
/* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK1*/
#define EFUSE_BLK1_DIN5 0xFFFFFFFF
#define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S))
#define EFUSE_BLK1_DIN5_V 0xFFFFFFFF
#define EFUSE_BLK1_DIN5_S 0
#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0)
/* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK1*/
#define EFUSE_BLK1_DIN6 0xFFFFFFFF
#define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S))
#define EFUSE_BLK1_DIN6_V 0xFFFFFFFF
#define EFUSE_BLK1_DIN6_S 0
#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4)
/* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK1*/
#define EFUSE_BLK1_DIN7 0xFFFFFFFF
#define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S))
#define EFUSE_BLK1_DIN7_V 0xFFFFFFFF
#define EFUSE_BLK1_DIN7_S 0
#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8)
/* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK2*/
#define EFUSE_BLK2_DIN0 0xFFFFFFFF
#define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S))
#define EFUSE_BLK2_DIN0_V 0xFFFFFFFF
#define EFUSE_BLK2_DIN0_S 0
#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc)
/* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK2*/
#define EFUSE_BLK2_DIN1 0xFFFFFFFF
#define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S))
#define EFUSE_BLK2_DIN1_V 0xFFFFFFFF
#define EFUSE_BLK2_DIN1_S 0
#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0)
/* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK2*/
#define EFUSE_BLK2_DIN2 0xFFFFFFFF
#define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S))
#define EFUSE_BLK2_DIN2_V 0xFFFFFFFF
#define EFUSE_BLK2_DIN2_S 0
#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4)
/* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK2*/
#define EFUSE_BLK2_DIN3 0xFFFFFFFF
#define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S))
#define EFUSE_BLK2_DIN3_V 0xFFFFFFFF
#define EFUSE_BLK2_DIN3_S 0
#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8)
/* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK2*/
#define EFUSE_BLK2_DIN4 0xFFFFFFFF
#define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S))
#define EFUSE_BLK2_DIN4_V 0xFFFFFFFF
#define EFUSE_BLK2_DIN4_S 0
#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc)
/* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK2*/
#define EFUSE_BLK2_DIN5 0xFFFFFFFF
#define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S))
#define EFUSE_BLK2_DIN5_V 0xFFFFFFFF
#define EFUSE_BLK2_DIN5_S 0
#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0)
/* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK2*/
#define EFUSE_BLK2_DIN6 0xFFFFFFFF
#define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S))
#define EFUSE_BLK2_DIN6_V 0xFFFFFFFF
#define EFUSE_BLK2_DIN6_S 0
#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4)
/* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK2*/
#define EFUSE_BLK2_DIN7 0xFFFFFFFF
#define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S))
#define EFUSE_BLK2_DIN7_V 0xFFFFFFFF
#define EFUSE_BLK2_DIN7_S 0
#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8)
/* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK3*/
#define EFUSE_BLK3_DIN0 0xFFFFFFFF
#define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S))
#define EFUSE_BLK3_DIN0_V 0xFFFFFFFF
#define EFUSE_BLK3_DIN0_S 0
#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc)
/* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK3*/
#define EFUSE_BLK3_DIN1 0xFFFFFFFF
#define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S))
#define EFUSE_BLK3_DIN1_V 0xFFFFFFFF
#define EFUSE_BLK3_DIN1_S 0
#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0)
/* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK3*/
#define EFUSE_BLK3_DIN2 0xFFFFFFFF
#define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S))
#define EFUSE_BLK3_DIN2_V 0xFFFFFFFF
#define EFUSE_BLK3_DIN2_S 0
#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4)
/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK3*/
#define EFUSE_BLK3_DIN3 0xFFFFFFFF
#define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S))
#define EFUSE_BLK3_DIN3_V 0xFFFFFFFF
#define EFUSE_BLK3_DIN3_S 0
#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8)
/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK3*/
#define EFUSE_BLK3_DIN4 0xFFFFFFFF
#define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S))
#define EFUSE_BLK3_DIN4_V 0xFFFFFFFF
#define EFUSE_BLK3_DIN4_S 0
#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec)
/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK3*/
#define EFUSE_BLK3_DIN5 0xFFFFFFFF
#define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S))
#define EFUSE_BLK3_DIN5_V 0xFFFFFFFF
#define EFUSE_BLK3_DIN5_S 0
#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0)
/* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK3*/
#define EFUSE_BLK3_DIN6 0xFFFFFFFF
#define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S))
#define EFUSE_BLK3_DIN6_V 0xFFFFFFFF
#define EFUSE_BLK3_DIN6_S 0
#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4)
/* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: program for BLOCK3*/
#define EFUSE_BLK3_DIN7 0xFFFFFFFF
#define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S))
#define EFUSE_BLK3_DIN7_V 0xFFFFFFFF
#define EFUSE_BLK3_DIN7_S 0
#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8)
/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define EFUSE_CLK_EN (BIT(16))
#define EFUSE_CLK_EN_M (BIT(16))
#define EFUSE_CLK_EN_V 0x1
#define EFUSE_CLK_EN_S 16
/* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; */
/*description: efuse timing configure*/
#define EFUSE_CLK_SEL1 0x000000FF
#define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S))
#define EFUSE_CLK_SEL1_V 0xFF
#define EFUSE_CLK_SEL1_S 8
/* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; */
/*description: efuse timing configure*/
#define EFUSE_CLK_SEL0 0x000000FF
#define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S))
#define EFUSE_CLK_SEL0_V 0xFF
#define EFUSE_CLK_SEL0_S 0
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc)
/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: */
#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16))
#define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16))
#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1
#define EFUSE_FORCE_NO_WR_RD_DIS_S 16
/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: efuse operation code*/
#define EFUSE_OP_CODE 0x0000FFFF
#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S))
#define EFUSE_OP_CODE_V 0xFFFF
#define EFUSE_OP_CODE_S 0
#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100)
/* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define EFUSE_DEBUG 0xFFFFFFFF
#define EFUSE_DEBUG_M ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S))
#define EFUSE_DEBUG_V 0xFFFFFFFF
#define EFUSE_DEBUG_S 0
#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104)
/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: command for program*/
#define EFUSE_PGM_CMD (BIT(1))
#define EFUSE_PGM_CMD_M (BIT(1))
#define EFUSE_PGM_CMD_V 0x1
#define EFUSE_PGM_CMD_S 1
/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: command for read*/
#define EFUSE_READ_CMD (BIT(0))
#define EFUSE_READ_CMD_M (BIT(0))
#define EFUSE_READ_CMD_V 0x1
#define EFUSE_READ_CMD_S 0
#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108)
/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: program done interrupt raw status*/
#define EFUSE_PGM_DONE_INT_RAW (BIT(1))
#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1))
#define EFUSE_PGM_DONE_INT_RAW_V 0x1
#define EFUSE_PGM_DONE_INT_RAW_S 1
/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: read done interrupt raw status*/
#define EFUSE_READ_DONE_INT_RAW (BIT(0))
#define EFUSE_READ_DONE_INT_RAW_M (BIT(0))
#define EFUSE_READ_DONE_INT_RAW_V 0x1
#define EFUSE_READ_DONE_INT_RAW_S 0
#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c)
/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: program done interrupt status*/
#define EFUSE_PGM_DONE_INT_ST (BIT(1))
#define EFUSE_PGM_DONE_INT_ST_M (BIT(1))
#define EFUSE_PGM_DONE_INT_ST_V 0x1
#define EFUSE_PGM_DONE_INT_ST_S 1
/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: read done interrupt status*/
#define EFUSE_READ_DONE_INT_ST (BIT(0))
#define EFUSE_READ_DONE_INT_ST_M (BIT(0))
#define EFUSE_READ_DONE_INT_ST_V 0x1
#define EFUSE_READ_DONE_INT_ST_S 0
#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110)
/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: program done interrupt enable*/
#define EFUSE_PGM_DONE_INT_ENA (BIT(1))
#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1))
#define EFUSE_PGM_DONE_INT_ENA_V 0x1
#define EFUSE_PGM_DONE_INT_ENA_S 1
/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: read done interrupt enable*/
#define EFUSE_READ_DONE_INT_ENA (BIT(0))
#define EFUSE_READ_DONE_INT_ENA_M (BIT(0))
#define EFUSE_READ_DONE_INT_ENA_V 0x1
#define EFUSE_READ_DONE_INT_ENA_S 0
#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114)
/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: program done interrupt clear*/
#define EFUSE_PGM_DONE_INT_CLR (BIT(1))
#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1))
#define EFUSE_PGM_DONE_INT_CLR_V 0x1
#define EFUSE_PGM_DONE_INT_CLR_S 1
/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: read done interrupt clear*/
#define EFUSE_READ_DONE_INT_CLR (BIT(0))
#define EFUSE_READ_DONE_INT_CLR_M (BIT(0))
#define EFUSE_READ_DONE_INT_CLR_V 0x1
#define EFUSE_READ_DONE_INT_CLR_S 0
#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118)
/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define EFUSE_DAC_CLK_PAD_SEL (BIT(8))
#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8))
#define EFUSE_DAC_CLK_PAD_SEL_V 0x1
#define EFUSE_DAC_CLK_PAD_SEL_S 8
/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */
/*description: efuse timing configure*/
#define EFUSE_DAC_CLK_DIV 0x000000FF
#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S))
#define EFUSE_DAC_CLK_DIV_V 0xFF
#define EFUSE_DAC_CLK_DIV_S 0
#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c)
/* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; */
/*description: the decode result of 3/4 coding scheme has warning*/
#define EFUSE_DEC_WARNINGS 0x00000FFF
#define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S))
#define EFUSE_DEC_WARNINGS_V 0xFFF
#define EFUSE_DEC_WARNINGS_S 0
#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC)
/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; */
/*description: */
#define EFUSE_DATE 0xFFFFFFFF
#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S))
#define EFUSE_DATE_V 0xFFFFFFFF
#define EFUSE_DATE_S 0
#endif /*_SOC_EFUSE_REG_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_SD_REG_H_
#define _SOC_GPIO_SD_REG_H_
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
#define GPIO_SD0_PRESCALE_V 0xFF
#define GPIO_SD0_PRESCALE_S 8
/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD0_IN 0x000000FF
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
#define GPIO_SD0_IN_V 0xFF
#define GPIO_SD0_IN_S 0
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004)
/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD1_PRESCALE 0x000000FF
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
#define GPIO_SD1_PRESCALE_V 0xFF
#define GPIO_SD1_PRESCALE_S 8
/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD1_IN 0x000000FF
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
#define GPIO_SD1_IN_V 0xFF
#define GPIO_SD1_IN_S 0
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008)
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD2_PRESCALE 0x000000FF
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
#define GPIO_SD2_PRESCALE_V 0xFF
#define GPIO_SD2_PRESCALE_S 8
/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD2_IN 0x000000FF
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
#define GPIO_SD2_IN_V 0xFF
#define GPIO_SD2_IN_S 0
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c)
/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD3_PRESCALE 0x000000FF
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
#define GPIO_SD3_PRESCALE_V 0xFF
#define GPIO_SD3_PRESCALE_S 8
/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD3_IN 0x000000FF
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
#define GPIO_SD3_IN_V 0xFF
#define GPIO_SD3_IN_S 0
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010)
/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD4_PRESCALE 0x000000FF
#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
#define GPIO_SD4_PRESCALE_V 0xFF
#define GPIO_SD4_PRESCALE_S 8
/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD4_IN 0x000000FF
#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
#define GPIO_SD4_IN_V 0xFF
#define GPIO_SD4_IN_S 0
#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014)
/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD5_PRESCALE 0x000000FF
#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
#define GPIO_SD5_PRESCALE_V 0xFF
#define GPIO_SD5_PRESCALE_S 8
/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD5_IN 0x000000FF
#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
#define GPIO_SD5_IN_V 0xFF
#define GPIO_SD5_IN_S 0
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018)
/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD6_PRESCALE 0x000000FF
#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
#define GPIO_SD6_PRESCALE_V 0xFF
#define GPIO_SD6_PRESCALE_S 8
/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD6_IN 0x000000FF
#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
#define GPIO_SD6_IN_V 0xFF
#define GPIO_SD6_IN_S 0
#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c)
/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD7_PRESCALE 0x000000FF
#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
#define GPIO_SD7_PRESCALE_V 0xFF
#define GPIO_SD7_PRESCALE_S 8
/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD7_IN 0x000000FF
#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
#define GPIO_SD7_IN_V 0xFF
#define GPIO_SD7_IN_S 0
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020)
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define GPIO_SD_CLK_EN (BIT(31))
#define GPIO_SD_CLK_EN_M (BIT(31))
#define GPIO_SD_CLK_EN_V 0x1
#define GPIO_SD_CLK_EN_S 31
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024)
/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define GPIO_SPI_SWAP (BIT(31))
#define GPIO_SPI_SWAP_M (BIT(31))
#define GPIO_SPI_SWAP_V 0x1
#define GPIO_SPI_SWAP_S 31
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028)
/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1506190 ; */
/*description: */
#define GPIO_SD_DATE 0x0FFFFFFF
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
#define GPIO_SD_DATE_V 0xFFFFFFF
#define GPIO_SD_DATE_S 0
#define SIGMADELTA_GPIO_SD_DATE_VERSION 0x1506190
#endif /*_SOC_GPIO_SD_REG_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_SD_STRUCT_H_
#define _SOC_GPIO_SD_STRUCT_H_
typedef volatile struct {
union {
struct {
uint32_t duty: 8;
uint32_t prescale: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} channel[8];
union {
struct {
uint32_t reserved0: 31;
uint32_t clk_en: 1;
};
uint32_t val;
} cg;
union {
struct {
uint32_t reserved0: 31;
uint32_t spi_swap: 1;
};
uint32_t val;
} misc;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} version;
} gpio_sd_dev_t;
extern gpio_sd_dev_t SIGMADELTA;
#endif /* _SOC_GPIO_SD_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_
#define SPICLK_IN_IDX 0
#define SPICLK_OUT_IDX 0
#define SPIQ_IN_IDX 1
#define SPIQ_OUT_IDX 1
#define SPID_IN_IDX 2
#define SPID_OUT_IDX 2
#define SPIHD_IN_IDX 3
#define SPIHD_OUT_IDX 3
#define SPIWP_IN_IDX 4
#define SPIWP_OUT_IDX 4
#define SPICS0_IN_IDX 5
#define SPICS0_OUT_IDX 5
#define SPICS1_IN_IDX 6
#define SPICS1_OUT_IDX 6
#define SPICS2_IN_IDX 7
#define SPICS2_OUT_IDX 7
#define HSPICLK_IN_IDX 8
#define HSPICLK_OUT_IDX 8
#define HSPIQ_IN_IDX 9
#define HSPIQ_OUT_IDX 9
#define HSPID_IN_IDX 10
#define HSPID_OUT_IDX 10
#define HSPICS0_IN_IDX 11
#define HSPICS0_OUT_IDX 11
#define HSPIHD_IN_IDX 12
#define HSPIHD_OUT_IDX 12
#define HSPIWP_IN_IDX 13
#define HSPIWP_OUT_IDX 13
#define U0RXD_IN_IDX 14
#define U0TXD_OUT_IDX 14
#define U0CTS_IN_IDX 15
#define U0RTS_OUT_IDX 15
#define U0DSR_IN_IDX 16
#define U0DTR_OUT_IDX 16
#define U1RXD_IN_IDX 17
#define U1TXD_OUT_IDX 17
#define U1CTS_IN_IDX 18
#define U1RTS_OUT_IDX 18
#define I2CM_SCL_O_IDX 19
#define I2CM_SDA_I_IDX 20
#define I2CM_SDA_O_IDX 20
#define EXT_I2C_SCL_O_IDX 21
#define EXT_I2C_SDA_O_IDX 22
#define EXT_I2C_SDA_I_IDX 22
#define I2S0O_BCK_IN_IDX 23
#define I2S0O_BCK_OUT_IDX 23
#define I2S1O_BCK_IN_IDX 24
#define I2S1O_BCK_OUT_IDX 24
#define I2S0O_WS_IN_IDX 25
#define I2S0O_WS_OUT_IDX 25
#define I2S1O_WS_IN_IDX 26
#define I2S1O_WS_OUT_IDX 26
#define I2S0I_BCK_IN_IDX 27
#define I2S0I_BCK_OUT_IDX 27
#define I2S0I_WS_IN_IDX 28
#define I2S0I_WS_OUT_IDX 28
#define I2CEXT0_SCL_IN_IDX 29
#define I2CEXT0_SCL_OUT_IDX 29
#define I2CEXT0_SDA_IN_IDX 30
#define I2CEXT0_SDA_OUT_IDX 30
#define PWM0_SYNC0_IN_IDX 31
#define SDIO_TOHOST_INT_OUT_IDX 31
#define PWM0_SYNC1_IN_IDX 32
#define PWM0_OUT0A_IDX 32
#define PWM0_SYNC2_IN_IDX 33
#define PWM0_OUT0B_IDX 33
#define PWM0_F0_IN_IDX 34
#define PWM0_OUT1A_IDX 34
#define PWM0_F1_IN_IDX 35
#define PWM0_OUT1B_IDX 35
#define PWM0_F2_IN_IDX 36
#define PWM0_OUT2A_IDX 36
#define GPIO_BT_ACTIVE_IDX 37
#define PWM0_OUT2B_IDX 37
#define GPIO_BT_PRIORITY_IDX 38
#define PCNT_SIG_CH0_IN0_IDX 39
#define PCNT_SIG_CH1_IN0_IDX 40
#define GPIO_WLAN_ACTIVE_IDX 40
#define PCNT_CTRL_CH0_IN0_IDX 41
#define BB_DIAG0_IDX 41
#define PCNT_CTRL_CH1_IN0_IDX 42
#define BB_DIAG1_IDX 42
#define PCNT_SIG_CH0_IN1_IDX 43
#define BB_DIAG2_IDX 43
#define PCNT_SIG_CH1_IN1_IDX 44
#define BB_DIAG3_IDX 44
#define PCNT_CTRL_CH0_IN1_IDX 45
#define BB_DIAG4_IDX 45
#define PCNT_CTRL_CH1_IN1_IDX 46
#define BB_DIAG5_IDX 46
#define PCNT_SIG_CH0_IN2_IDX 47
#define BB_DIAG6_IDX 47
#define PCNT_SIG_CH1_IN2_IDX 48
#define BB_DIAG7_IDX 48
#define PCNT_CTRL_CH0_IN2_IDX 49
#define BB_DIAG8_IDX 49
#define PCNT_CTRL_CH1_IN2_IDX 50
#define BB_DIAG9_IDX 50
#define PCNT_SIG_CH0_IN3_IDX 51
#define BB_DIAG10_IDX 51
#define PCNT_SIG_CH1_IN3_IDX 52
#define BB_DIAG11_IDX 52
#define PCNT_CTRL_CH0_IN3_IDX 53
#define BB_DIAG12_IDX 53
#define PCNT_CTRL_CH1_IN3_IDX 54
#define BB_DIAG13_IDX 54
#define PCNT_SIG_CH0_IN4_IDX 55
#define BB_DIAG14_IDX 55
#define PCNT_SIG_CH1_IN4_IDX 56
#define BB_DIAG15_IDX 56
#define PCNT_CTRL_CH0_IN4_IDX 57
#define BB_DIAG16_IDX 57
#define PCNT_CTRL_CH1_IN4_IDX 58
#define BB_DIAG17_IDX 58
#define BB_DIAG18_IDX 59
#define BB_DIAG19_IDX 60
#define HSPICS1_IN_IDX 61
#define HSPICS1_OUT_IDX 61
#define HSPICS2_IN_IDX 62
#define HSPICS2_OUT_IDX 62
#define VSPICLK_IN_IDX 63
#define VSPICLK_OUT_MUX_IDX 63
#define VSPIQ_IN_IDX 64
#define VSPIQ_OUT_IDX 64
#define VSPID_IN_IDX 65
#define VSPID_OUT_IDX 65
#define VSPIHD_IN_IDX 66
#define VSPIHD_OUT_IDX 66
#define VSPIWP_IN_IDX 67
#define VSPIWP_OUT_IDX 67
#define VSPICS0_IN_IDX 68
#define VSPICS0_OUT_IDX 68
#define VSPICS1_IN_IDX 69
#define VSPICS1_OUT_IDX 69
#define VSPICS2_IN_IDX 70
#define VSPICS2_OUT_IDX 70
#define PCNT_SIG_CH0_IN5_IDX 71
#define LEDC_HS_SIG_OUT0_IDX 71
#define PCNT_SIG_CH1_IN5_IDX 72
#define LEDC_HS_SIG_OUT1_IDX 72
#define PCNT_CTRL_CH0_IN5_IDX 73
#define LEDC_HS_SIG_OUT2_IDX 73
#define PCNT_CTRL_CH1_IN5_IDX 74
#define LEDC_HS_SIG_OUT3_IDX 74
#define PCNT_SIG_CH0_IN6_IDX 75
#define LEDC_HS_SIG_OUT4_IDX 75
#define PCNT_SIG_CH1_IN6_IDX 76
#define LEDC_HS_SIG_OUT5_IDX 76
#define PCNT_CTRL_CH0_IN6_IDX 77
#define LEDC_HS_SIG_OUT6_IDX 77
#define PCNT_CTRL_CH1_IN6_IDX 78
#define LEDC_HS_SIG_OUT7_IDX 78
#define PCNT_SIG_CH0_IN7_IDX 79
#define LEDC_LS_SIG_OUT0_IDX 79
#define PCNT_SIG_CH1_IN7_IDX 80
#define LEDC_LS_SIG_OUT1_IDX 80
#define PCNT_CTRL_CH0_IN7_IDX 81
#define LEDC_LS_SIG_OUT2_IDX 81
#define PCNT_CTRL_CH1_IN7_IDX 82
#define LEDC_LS_SIG_OUT3_IDX 82
#define RMT_SIG_IN0_IDX 83
#define LEDC_LS_SIG_OUT4_IDX 83
#define RMT_SIG_IN1_IDX 84
#define LEDC_LS_SIG_OUT5_IDX 84
#define RMT_SIG_IN2_IDX 85
#define LEDC_LS_SIG_OUT6_IDX 85
#define RMT_SIG_IN3_IDX 86
#define LEDC_LS_SIG_OUT7_IDX 86
#define RMT_SIG_IN4_IDX 87
#define RMT_SIG_OUT0_IDX 87
#define RMT_SIG_IN5_IDX 88
#define RMT_SIG_OUT1_IDX 88
#define RMT_SIG_IN6_IDX 89
#define RMT_SIG_OUT2_IDX 89
#define RMT_SIG_IN7_IDX 90
#define RMT_SIG_OUT3_IDX 90
#define RMT_SIG_OUT4_IDX 91
#define RMT_SIG_OUT5_IDX 92
#define EXT_ADC_START_IDX 93
#define RMT_SIG_OUT6_IDX 93
#define CAN_RX_IDX 94
#define RMT_SIG_OUT7_IDX 94
#define I2CEXT1_SCL_IN_IDX 95
#define I2CEXT1_SCL_OUT_IDX 95
#define I2CEXT1_SDA_IN_IDX 96
#define I2CEXT1_SDA_OUT_IDX 96
#define HOST_CARD_DETECT_N_1_IDX 97
#define HOST_CCMD_OD_PULLUP_EN_N_IDX 97
#define HOST_CARD_DETECT_N_2_IDX 98
#define HOST_RST_N_1_IDX 98
#define HOST_CARD_WRITE_PRT_1_IDX 99
#define HOST_RST_N_2_IDX 99
#define HOST_CARD_WRITE_PRT_2_IDX 100
#define GPIO_SD0_OUT_IDX 100
#define HOST_CARD_INT_N_1_IDX 101
#define GPIO_SD1_OUT_IDX 101
#define HOST_CARD_INT_N_2_IDX 102
#define GPIO_SD2_OUT_IDX 102
#define PWM1_SYNC0_IN_IDX 103
#define GPIO_SD3_OUT_IDX 103
#define PWM1_SYNC1_IN_IDX 104
#define GPIO_SD4_OUT_IDX 104
#define PWM1_SYNC2_IN_IDX 105
#define GPIO_SD5_OUT_IDX 105
#define PWM1_F0_IN_IDX 106
#define GPIO_SD6_OUT_IDX 106
#define PWM1_F1_IN_IDX 107
#define GPIO_SD7_OUT_IDX 107
#define PWM1_F2_IN_IDX 108
#define PWM1_OUT0A_IDX 108
#define PWM0_CAP0_IN_IDX 109
#define PWM1_OUT0B_IDX 109
#define PWM0_CAP1_IN_IDX 110
#define PWM1_OUT1A_IDX 110
#define PWM0_CAP2_IN_IDX 111
#define PWM1_OUT1B_IDX 111
#define PWM1_CAP0_IN_IDX 112
#define PWM1_OUT2A_IDX 112
#define PWM1_CAP1_IN_IDX 113
#define PWM1_OUT2B_IDX 113
#define PWM1_CAP2_IN_IDX 114
#define PWM2_OUT1H_IDX 114
#define PWM2_FLTA_IDX 115
#define PWM2_OUT1L_IDX 115
#define PWM2_FLTB_IDX 116
#define PWM2_OUT2H_IDX 116
#define PWM2_CAP1_IN_IDX 117
#define PWM2_OUT2L_IDX 117
#define PWM2_CAP2_IN_IDX 118
#define PWM2_OUT3H_IDX 118
#define PWM2_CAP3_IN_IDX 119
#define PWM2_OUT3L_IDX 119
#define PWM3_FLTA_IDX 120
#define PWM2_OUT4H_IDX 120
#define PWM3_FLTB_IDX 121
#define PWM2_OUT4L_IDX 121
#define PWM3_CAP1_IN_IDX 122
#define PWM3_CAP2_IN_IDX 123
#define CAN_TX_IDX 123
#define PWM3_CAP3_IN_IDX 124
#define CAN_BUS_OFF_ON_IDX 124
#define CAN_CLKOUT_IDX 125
#define SPID4_IN_IDX 128
#define SPID4_OUT_IDX 128
#define SPID5_IN_IDX 129
#define SPID5_OUT_IDX 129
#define SPID6_IN_IDX 130
#define SPID6_OUT_IDX 130
#define SPID7_IN_IDX 131
#define SPID7_OUT_IDX 131
#define HSPID4_IN_IDX 132
#define HSPID4_OUT_IDX 132
#define HSPID5_IN_IDX 133
#define HSPID5_OUT_IDX 133
#define HSPID6_IN_IDX 134
#define HSPID6_OUT_IDX 134
#define HSPID7_IN_IDX 135
#define HSPID7_OUT_IDX 135
#define VSPID4_IN_IDX 136
#define VSPID4_OUT_IDX 136
#define VSPID5_IN_IDX 137
#define VSPID5_OUT_IDX 137
#define VSPID6_IN_IDX 138
#define VSPID6_OUT_IDX 138
#define VSPID7_IN_IDX 139
#define VSPID7_OUT_IDX 139
#define I2S0I_DATA_IN0_IDX 140
#define I2S0O_DATA_OUT0_IDX 140
#define I2S0I_DATA_IN1_IDX 141
#define I2S0O_DATA_OUT1_IDX 141
#define I2S0I_DATA_IN2_IDX 142
#define I2S0O_DATA_OUT2_IDX 142
#define I2S0I_DATA_IN3_IDX 143
#define I2S0O_DATA_OUT3_IDX 143
#define I2S0I_DATA_IN4_IDX 144
#define I2S0O_DATA_OUT4_IDX 144
#define I2S0I_DATA_IN5_IDX 145
#define I2S0O_DATA_OUT5_IDX 145
#define I2S0I_DATA_IN6_IDX 146
#define I2S0O_DATA_OUT6_IDX 146
#define I2S0I_DATA_IN7_IDX 147
#define I2S0O_DATA_OUT7_IDX 147
#define I2S0I_DATA_IN8_IDX 148
#define I2S0O_DATA_OUT8_IDX 148
#define I2S0I_DATA_IN9_IDX 149
#define I2S0O_DATA_OUT9_IDX 149
#define I2S0I_DATA_IN10_IDX 150
#define I2S0O_DATA_OUT10_IDX 150
#define I2S0I_DATA_IN11_IDX 151
#define I2S0O_DATA_OUT11_IDX 151
#define I2S0I_DATA_IN12_IDX 152
#define I2S0O_DATA_OUT12_IDX 152
#define I2S0I_DATA_IN13_IDX 153
#define I2S0O_DATA_OUT13_IDX 153
#define I2S0I_DATA_IN14_IDX 154
#define I2S0O_DATA_OUT14_IDX 154
#define I2S0I_DATA_IN15_IDX 155
#define I2S0O_DATA_OUT15_IDX 155
#define I2S0O_DATA_OUT16_IDX 156
#define I2S0O_DATA_OUT17_IDX 157
#define I2S0O_DATA_OUT18_IDX 158
#define I2S0O_DATA_OUT19_IDX 159
#define I2S0O_DATA_OUT20_IDX 160
#define I2S0O_DATA_OUT21_IDX 161
#define I2S0O_DATA_OUT22_IDX 162
#define I2S0O_DATA_OUT23_IDX 163
#define I2S1I_BCK_IN_IDX 164
#define I2S1I_BCK_OUT_IDX 164
#define I2S1I_WS_IN_IDX 165
#define I2S1I_WS_OUT_IDX 165
#define I2S1I_DATA_IN0_IDX 166
#define I2S1O_DATA_OUT0_IDX 166
#define I2S1I_DATA_IN1_IDX 167
#define I2S1O_DATA_OUT1_IDX 167
#define I2S1I_DATA_IN2_IDX 168
#define I2S1O_DATA_OUT2_IDX 168
#define I2S1I_DATA_IN3_IDX 169
#define I2S1O_DATA_OUT3_IDX 169
#define I2S1I_DATA_IN4_IDX 170
#define I2S1O_DATA_OUT4_IDX 170
#define I2S1I_DATA_IN5_IDX 171
#define I2S1O_DATA_OUT5_IDX 171
#define I2S1I_DATA_IN6_IDX 172
#define I2S1O_DATA_OUT6_IDX 172
#define I2S1I_DATA_IN7_IDX 173
#define I2S1O_DATA_OUT7_IDX 173
#define I2S1I_DATA_IN8_IDX 174
#define I2S1O_DATA_OUT8_IDX 174
#define I2S1I_DATA_IN9_IDX 175
#define I2S1O_DATA_OUT9_IDX 175
#define I2S1I_DATA_IN10_IDX 176
#define I2S1O_DATA_OUT10_IDX 176
#define I2S1I_DATA_IN11_IDX 177
#define I2S1O_DATA_OUT11_IDX 177
#define I2S1I_DATA_IN12_IDX 178
#define I2S1O_DATA_OUT12_IDX 178
#define I2S1I_DATA_IN13_IDX 179
#define I2S1O_DATA_OUT13_IDX 179
#define I2S1I_DATA_IN14_IDX 180
#define I2S1O_DATA_OUT14_IDX 180
#define I2S1I_DATA_IN15_IDX 181
#define I2S1O_DATA_OUT15_IDX 181
#define I2S1O_DATA_OUT16_IDX 182
#define I2S1O_DATA_OUT17_IDX 183
#define I2S1O_DATA_OUT18_IDX 184
#define I2S1O_DATA_OUT19_IDX 185
#define I2S1O_DATA_OUT20_IDX 186
#define I2S1O_DATA_OUT21_IDX 187
#define I2S1O_DATA_OUT22_IDX 188
#define I2S1O_DATA_OUT23_IDX 189
#define I2S0I_H_SYNC_IDX 190
#define PWM3_OUT1H_IDX 190
#define I2S0I_V_SYNC_IDX 191
#define PWM3_OUT1L_IDX 191
#define I2S0I_H_ENABLE_IDX 192
#define PWM3_OUT2H_IDX 192
#define I2S1I_H_SYNC_IDX 193
#define PWM3_OUT2L_IDX 193
#define I2S1I_V_SYNC_IDX 194
#define PWM3_OUT3H_IDX 194
#define I2S1I_H_ENABLE_IDX 195
#define PWM3_OUT3L_IDX 195
#define PWM3_OUT4H_IDX 196
#define PWM3_OUT4L_IDX 197
#define U2RXD_IN_IDX 198
#define U2TXD_OUT_IDX 198
#define U2CTS_IN_IDX 199
#define U2RTS_OUT_IDX 199
#define EMAC_MDC_I_IDX 200
#define EMAC_MDC_O_IDX 200
#define EMAC_MDI_I_IDX 201
#define EMAC_MDO_O_IDX 201
#define EMAC_CRS_I_IDX 202
#define EMAC_CRS_O_IDX 202
#define EMAC_COL_I_IDX 203
#define EMAC_COL_O_IDX 203
#define PCMFSYNC_IN_IDX 204
#define BT_AUDIO0_IRQ_IDX 204
#define PCMCLK_IN_IDX 205
#define BT_AUDIO1_IRQ_IDX 205
#define PCMDIN_IDX 206
#define BT_AUDIO2_IRQ_IDX 206
#define BLE_AUDIO0_IRQ_IDX 207
#define BLE_AUDIO1_IRQ_IDX 208
#define BLE_AUDIO2_IRQ_IDX 209
#define PCMFSYNC_OUT_IDX 210
#define PCMCLK_OUT_IDX 211
#define PCMDOUT_IDX 212
#define BLE_AUDIO_SYNC0_P_IDX 213
#define BLE_AUDIO_SYNC1_P_IDX 214
#define BLE_AUDIO_SYNC2_P_IDX 215
#define ANT_SEL0_IDX 216
#define ANT_SEL1_IDX 217
#define ANT_SEL2_IDX 218
#define ANT_SEL3_IDX 219
#define ANT_SEL4_IDX 220
#define ANT_SEL5_IDX 221
#define ANT_SEL6_IDX 222
#define ANT_SEL7_IDX 223
#define SIG_IN_FUNC224_IDX 224
#define SIG_IN_FUNC225_IDX 225
#define SIG_IN_FUNC226_IDX 226
#define SIG_IN_FUNC227_IDX 227
#define SIG_IN_FUNC228_IDX 228
#endif /* _SOC_GPIO_SIG_MAP_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_STRUCT_H_
#define _SOC_GPIO_STRUCT_H_
typedef volatile struct {
uint32_t bt_select; /*NA*/
uint32_t out; /*GPIO0~31 output value*/
uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/
uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/
union {
struct {
uint32_t data: 8; /*GPIO32~39 output value*/
uint32_t reserved8: 24;
};
uint32_t val;
} out1;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output value write 1 to set*/
uint32_t reserved8: 24;
};
uint32_t val;
} out1_w1ts;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output value write 1 to clear*/
uint32_t reserved8: 24;
};
uint32_t val;
} out1_w1tc;
union {
struct {
uint32_t sel: 8; /*SDIO PADS on/off control from outside*/
uint32_t reserved8: 24;
};
uint32_t val;
} sdio_select;
uint32_t enable; /*GPIO0~31 output enable*/
uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/
uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/
union {
struct {
uint32_t data: 8; /*GPIO32~39 output enable*/
uint32_t reserved8: 24;
};
uint32_t val;
} enable1;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output enable write 1 to set*/
uint32_t reserved8: 24;
};
uint32_t val;
} enable1_w1ts;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output enable write 1 to clear*/
uint32_t reserved8: 24;
};
uint32_t val;
} enable1_w1tc;
union {
struct {
uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]} . Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3} . vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} */
uint32_t reserved16:16;
};
uint32_t val;
} strap;
uint32_t in; /*GPIO0~31 input value*/
union {
struct {
uint32_t data: 8; /*GPIO32~39 input value*/
uint32_t reserved8: 24;
};
uint32_t val;
} in1;
uint32_t status; /*GPIO0~31 interrupt status*/
uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/
uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/
union {
struct {
uint32_t intr_st: 8; /*GPIO32~39 interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
} status1;
union {
struct {
uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to set*/
uint32_t reserved8: 24;
};
uint32_t val;
} status1_w1ts;
union {
struct {
uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to clear*/
uint32_t reserved8: 24;
};
uint32_t val;
} status1_w1tc;
uint32_t reserved_5c;
uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/
uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/
uint32_t pcpu_int; /*GPIO0~31 PRO CPU interrupt status*/
uint32_t pcpu_nmi_int; /*GPIO0~31 PRO CPU non-maskable interrupt status*/
uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/
union {
struct {
uint32_t intr: 8; /*GPIO32~39 APP CPU interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
} acpu_int1;
union {
struct {
uint32_t intr: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
} acpu_nmi_int1;
union {
struct {
uint32_t intr: 8; /*GPIO32~39 PRO CPU interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
} pcpu_int1;
union {
struct {
uint32_t intr: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
} pcpu_nmi_int1;
union {
struct {
uint32_t intr: 8; /*SDIO's extent GPIO32~39 interrupt*/
uint32_t reserved8: 24;
};
uint32_t val;
} cpusdio_int1;
union {
struct {
uint32_t reserved0: 2;
uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
uint32_t reserved3: 4;
uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/
uint32_t config: 2; /*NA*/
uint32_t int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
uint32_t reserved18: 14;
};
uint32_t val;
} pin[40];
union {
struct {
uint32_t rtc_max: 10;
uint32_t reserved10: 21;
uint32_t start: 1;
};
uint32_t val;
} cali_conf;
union {
struct {
uint32_t value_sync2: 20;
uint32_t reserved20: 10;
uint32_t rdy_real: 1;
uint32_t rdy_sync2: 1;
};
uint32_t val;
} cali_data;
union {
struct {
uint32_t func_sel: 6; /*select one of the 256 inputs*/
uint32_t sig_in_inv: 1; /*revert the value of the input if you want to revert please set the value to 1*/
uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/
uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/
};
uint32_t val;
} func_in_sel_cfg[256];
union {
struct {
uint32_t func_sel: 9; /*select one of the 256 output to 40 GPIO*/
uint32_t inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/
uint32_t oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/
uint32_t oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/
uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/
};
uint32_t val;
} func_out_sel_cfg[40];
} gpio_dev_t;
extern gpio_dev_t GPIO;
#endif /* _SOC_GPIO_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_I2C_REG_H_
#define _SOC_I2C_REG_H_
#include "soc.h"
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000)
/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This register is used to configure the low level width of SCL clock.*/
#define I2C_SCL_LOW_PERIOD 0x00003FFF
#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))
#define I2C_SCL_LOW_PERIOD_V 0x3FFF
#define I2C_SCL_LOW_PERIOD_S 0
#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004)
/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: This is the clock gating control bit for reading or writing registers.*/
#define I2C_CLK_EN (BIT(8))
#define I2C_CLK_EN_M (BIT(8))
#define I2C_CLK_EN_V 0x1
#define I2C_CLK_EN_S 8
/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
/*description: This bit is used to control the storage mode for received datas.
1: receive data from most significant bit 0: receive data from least significant bit*/
#define I2C_RX_LSB_FIRST (BIT(7))
#define I2C_RX_LSB_FIRST_M (BIT(7))
#define I2C_RX_LSB_FIRST_V 0x1
#define I2C_RX_LSB_FIRST_S 7
/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: This bit is used to control the sending mode for data need to
be send. 1: receive data from most significant bit 0: receive data from least significant bit*/
#define I2C_TX_LSB_FIRST (BIT(6))
#define I2C_TX_LSB_FIRST_M (BIT(6))
#define I2C_TX_LSB_FIRST_V 0x1
#define I2C_TX_LSB_FIRST_S 6
/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to start sending data in txfifo.*/
#define I2C_TRANS_START (BIT(5))
#define I2C_TRANS_START_M (BIT(5))
#define I2C_TRANS_START_V 0x1
#define I2C_TRANS_START_S 5
/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to configure the module as i2c master clear this
bit to configure the module as i2c slave.*/
#define I2C_MS_MODE (BIT(4))
#define I2C_MS_MODE_M (BIT(4))
#define I2C_MS_MODE_V 0x1
#define I2C_MS_MODE_S 4
/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to sample data in SCL low level. clear this bit
to sample data in SCL high level.*/
#define I2C_SAMPLE_SCL_LEVEL (BIT(2))
#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2))
#define I2C_SAMPLE_SCL_LEVEL_V 0x1
#define I2C_SAMPLE_SCL_LEVEL_S 2
/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: 1: normally ouput scl clock 0: exchange the function of scl_o
and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/
#define I2C_SCL_FORCE_OUT (BIT(1))
#define I2C_SCL_FORCE_OUT_M (BIT(1))
#define I2C_SCL_FORCE_OUT_V 0x1
#define I2C_SCL_FORCE_OUT_S 1
/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: 1: normally ouput sda data 0: exchange the function of sda_o
and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
#define I2C_SDA_FORCE_OUT (BIT(0))
#define I2C_SDA_FORCE_OUT_M (BIT(0))
#define I2C_SDA_FORCE_OUT_V 0x1
#define I2C_SDA_FORCE_OUT_S 0
#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008)
/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
/*description: This register stores the value of state machine to produce SCL.
3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/
#define I2C_SCL_STATE_LAST 0x00000007
#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
#define I2C_SCL_STATE_LAST_V 0x7
#define I2C_SCL_STATE_LAST_S 28
/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
/*description: This register stores the value of state machine for i2c module.
3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
#define I2C_SCL_MAIN_STATE_LAST 0x00000007
#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))
#define I2C_SCL_MAIN_STATE_LAST_V 0x7
#define I2C_SCL_MAIN_STATE_LAST_S 24
/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
/*description: This register stores the amount of received data in ram.*/
#define I2C_TXFIFO_CNT 0x0000003F
#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))
#define I2C_TXFIFO_CNT_V 0x3F
#define I2C_TXFIFO_CNT_S 18
/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
/*description: This register represent the amount of data need to send.*/
#define I2C_RXFIFO_CNT 0x0000003F
#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
#define I2C_RXFIFO_CNT_V 0x3F
#define I2C_RXFIFO_CNT_S 8
/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: This register changes to high level when one byte is transferred.*/
#define I2C_BYTE_TRANS (BIT(6))
#define I2C_BYTE_TRANS_M (BIT(6))
#define I2C_BYTE_TRANS_V 0x1
#define I2C_BYTE_TRANS_S 6
/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: when configured as i2c slave and the address send by master
is equal to slave's address then this bit will be high level.*/
#define I2C_SLAVE_ADDRESSED (BIT(5))
#define I2C_SLAVE_ADDRESSED_M (BIT(5))
#define I2C_SLAVE_ADDRESSED_V 0x1
#define I2C_SLAVE_ADDRESSED_S 5
/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
#define I2C_BUS_BUSY (BIT(4))
#define I2C_BUS_BUSY_M (BIT(4))
#define I2C_BUS_BUSY_V 0x1
#define I2C_BUS_BUSY_S 4
/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: when I2C lost control of SDA line this register changes to high level.*/
#define I2C_ARB_LOST (BIT(3))
#define I2C_ARB_LOST_M (BIT(3))
#define I2C_ARB_LOST_V 0x1
#define I2C_ARB_LOST_S 3
/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: when I2C takes more than time_out_reg clocks to receive a data
then this register changes to high level.*/
#define I2C_TIME_OUT (BIT(2))
#define I2C_TIME_OUT_M (BIT(2))
#define I2C_TIME_OUT_V 0x1
#define I2C_TIME_OUT_S 2
/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: when in slave mode 1: master read slave 0: master write slave.*/
#define I2C_SLAVE_RW (BIT(1))
#define I2C_SLAVE_RW_M (BIT(1))
#define I2C_SLAVE_RW_V 0x1
#define I2C_SLAVE_RW_S 1
/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: This register stores the value of ACK bit.*/
#define I2C_ACK_REC (BIT(0))
#define I2C_ACK_REC_M (BIT(0))
#define I2C_ACK_REC_V 0x1
#define I2C_ACK_REC_S 0
#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c)
/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
/*description: This register is used to configure the max clock number of receiving a data.*/
#define I2C_TIME_OUT_REG 0x000FFFFF
#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S))
#define I2C_TIME_OUT_REG_V 0xFFFFF
#define I2C_TIME_OUT_REG_S 0
#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010)
/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: This register is used to enable slave 10bit address mode.*/
#define I2C_ADDR_10BIT_EN (BIT(31))
#define I2C_ADDR_10BIT_EN_M (BIT(31))
#define I2C_ADDR_10BIT_EN_V 0x1
#define I2C_ADDR_10BIT_EN_S 31
/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
/*description: when configured as i2c slave this register is used to configure
slave's address.*/
#define I2C_SLAVE_ADDR 0x00007FFF
#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
#define I2C_SLAVE_ADDR_V 0x7FFF
#define I2C_SLAVE_ADDR_S 0
#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014)
/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
/*description: This is the offset address of the last sending data as described
in nonfifo_tx_thres register.*/
#define I2C_TXFIFO_END_ADDR 0x0000001F
#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S))
#define I2C_TXFIFO_END_ADDR_V 0x1F
#define I2C_TXFIFO_END_ADDR_S 15
/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
/*description: This is the offset address of the first sending data as described
in nonfifo_tx_thres register.*/
#define I2C_TXFIFO_START_ADDR 0x0000001F
#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S))
#define I2C_TXFIFO_START_ADDR_V 0x1F
#define I2C_TXFIFO_START_ADDR_S 10
/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
/*description: This is the offset address of the first receiving data as described
in nonfifo_rx_thres_register.*/
#define I2C_RXFIFO_END_ADDR 0x0000001F
#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S))
#define I2C_RXFIFO_END_ADDR_V 0x1F
#define I2C_RXFIFO_END_ADDR_S 5
/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
/*description: This is the offset address of the last receiving data as described
in nonfifo_rx_thres_register.*/
#define I2C_RXFIFO_START_ADDR 0x0000001F
#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S))
#define I2C_RXFIFO_START_ADDR_V 0x1F
#define I2C_RXFIFO_START_ADDR_S 0
#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018)
/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */
/*description: when I2C sends more than nonfifo_tx_thres data it will produce
tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
#define I2C_NONFIFO_TX_THRES 0x0000003F
#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S))
#define I2C_NONFIFO_TX_THRES_V 0x3F
#define I2C_NONFIFO_TX_THRES_S 20
/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */
/*description: when I2C receives more than nonfifo_rx_thres data it will produce
rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
#define I2C_NONFIFO_RX_THRES 0x0000003F
#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S))
#define I2C_NONFIFO_RX_THRES_V 0x3F
#define I2C_NONFIFO_RX_THRES_S 14
/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: Set this bit to reset tx fifo when using apb fifo access.*/
#define I2C_TX_FIFO_RST (BIT(13))
#define I2C_TX_FIFO_RST_M (BIT(13))
#define I2C_TX_FIFO_RST_V 0x1
#define I2C_TX_FIFO_RST_S 13
/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to reset rx fifo when using apb fifo access.*/
#define I2C_RX_FIFO_RST (BIT(12))
#define I2C_RX_FIFO_RST_M (BIT(12))
#define I2C_RX_FIFO_RST_V 0x1
#define I2C_RX_FIFO_RST_S 12
/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: When this bit is set to 1 then the byte after address represent
the offset address of I2C Slave's ram.*/
#define I2C_FIFO_ADDR_CFG_EN (BIT(11))
#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11))
#define I2C_FIFO_ADDR_CFG_EN_V 0x1
#define I2C_FIFO_ADDR_CFG_EN_S 11
/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set this bit to enble apb nonfifo access.*/
#define I2C_NONFIFO_EN (BIT(10))
#define I2C_NONFIFO_EN_M (BIT(10))
#define I2C_NONFIFO_EN_V 0x1
#define I2C_NONFIFO_EN_S 10
/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
/*description: Config txfifo empty threhd value when using apb fifo access*/
#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F
#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S))
#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F
#define I2C_TXFIFO_EMPTY_THRHD_S 5
/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */
/*description: */
#define I2C_RXFIFO_FULL_THRHD 0x0000001F
#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S))
#define I2C_RXFIFO_FULL_THRHD_V 0x1F
#define I2C_RXFIFO_FULL_THRHD_S 0
#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c)
/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: The register represent the byte data read from rxfifo when use apb fifo access*/
#define I2C_FIFO_RDATA 0x000000FF
#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
#define I2C_FIFO_RDATA_V 0xFF
#define I2C_FIFO_RDATA_S 0
#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020)
/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when
I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1
#define I2C_TX_SEND_EMPTY_INT_RAW_S 12
/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when
I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
#define I2C_RX_REC_FULL_INT_RAW (BIT(11))
#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11))
#define I2C_RX_REC_FULL_INT_RAW_V 0x1
#define I2C_RX_REC_FULL_INT_RAW_S 11
/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for ack_err_int interrupt. when
I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
#define I2C_ACK_ERR_INT_RAW (BIT(10))
#define I2C_ACK_ERR_INT_RAW_M (BIT(10))
#define I2C_ACK_ERR_INT_RAW_V 0x1
#define I2C_ACK_ERR_INT_RAW_S 10
/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for trans_start_int interrupt. when
I2C sends the START bit it will produce trans_start_int interrupt.*/
#define I2C_TRANS_START_INT_RAW (BIT(9))
#define I2C_TRANS_START_INT_RAW_M (BIT(9))
#define I2C_TRANS_START_INT_RAW_V 0x1
#define I2C_TRANS_START_INT_RAW_S 9
/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for time_out_int interrupt. when
I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
#define I2C_TIME_OUT_INT_RAW (BIT(8))
#define I2C_TIME_OUT_INT_RAW_M (BIT(8))
#define I2C_TIME_OUT_INT_RAW_V 0x1
#define I2C_TIME_OUT_INT_RAW_S 8
/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for trans_complete_int interrupt.
when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7))
#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1
#define I2C_TRANS_COMPLETE_INT_RAW_S 7
/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for master_tra_comp_int interrupt.
when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6
/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when
I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5))
#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1
#define I2C_ARBITRATION_LOST_INT_RAW_S 5
/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for slave_tran_comp_int interrupt.
when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/
#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4
/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for end_detect_int interrupt. when
I2C deals with the END command it will produce end_detect_int interrupt.*/
#define I2C_END_DETECT_INT_RAW (BIT(3))
#define I2C_END_DETECT_INT_RAW_M (BIT(3))
#define I2C_END_DETECT_INT_RAW_V 0x1
#define I2C_END_DETECT_INT_RAW_S 3
/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for receiving data overflow when
use apb fifo access.*/
#define I2C_RXFIFO_OVF_INT_RAW (BIT(2))
#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_RAW_V 0x1
#define I2C_RXFIFO_OVF_INT_RAW_S 2
/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/
#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1
#define I2C_TXFIFO_EMPTY_INT_RAW_S 1
/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/
#define I2C_RXFIFO_FULL_INT_RAW (BIT(0))
#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_RAW_V 0x1
#define I2C_RXFIFO_FULL_INT_RAW_S 0
#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024)
/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to clear the tx_send_empty_int interrupt.*/
#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1
#define I2C_TX_SEND_EMPTY_INT_CLR_S 12
/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
/*description: Set this bit to clear the rx_rec_full_int interrupt.*/
#define I2C_RX_REC_FULL_INT_CLR (BIT(11))
#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11))
#define I2C_RX_REC_FULL_INT_CLR_V 0x1
#define I2C_RX_REC_FULL_INT_CLR_S 11
/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set this bit to clear the ack_err_int interrupt.*/
#define I2C_ACK_ERR_INT_CLR (BIT(10))
#define I2C_ACK_ERR_INT_CLR_M (BIT(10))
#define I2C_ACK_ERR_INT_CLR_V 0x1
#define I2C_ACK_ERR_INT_CLR_S 10
/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
/*description: Set this bit to clear the trans_start_int interrupt.*/
#define I2C_TRANS_START_INT_CLR (BIT(9))
#define I2C_TRANS_START_INT_CLR_M (BIT(9))
#define I2C_TRANS_START_INT_CLR_V 0x1
#define I2C_TRANS_START_INT_CLR_S 9
/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to clear the time_out_int interrupt.*/
#define I2C_TIME_OUT_INT_CLR (BIT(8))
#define I2C_TIME_OUT_INT_CLR_M (BIT(8))
#define I2C_TIME_OUT_INT_CLR_V 0x1
#define I2C_TIME_OUT_INT_CLR_S 8
/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set this bit to clear the trans_complete_int interrupt.*/
#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7))
#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1
#define I2C_TRANS_COMPLETE_INT_CLR_S 7
/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to clear the master_tran_comp interrupt.*/
#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6
/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to clear the arbitration_lost_int interrupt.*/
#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5))
#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1
#define I2C_ARBITRATION_LOST_INT_CLR_S 5
/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/
#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4
/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to clear the end_detect_int interrupt.*/
#define I2C_END_DETECT_INT_CLR (BIT(3))
#define I2C_END_DETECT_INT_CLR_M (BIT(3))
#define I2C_END_DETECT_INT_CLR_V 0x1
#define I2C_END_DETECT_INT_CLR_S 3
/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/
#define I2C_RXFIFO_OVF_INT_CLR (BIT(2))
#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_CLR_V 0x1
#define I2C_RXFIFO_OVF_INT_CLR_S 2
/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to clear the txfifo_empty_int interrupt.*/
#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1
#define I2C_TXFIFO_EMPTY_INT_CLR_S 1
/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to clear the rxfifo_full_int interrupt.*/
#define I2C_RXFIFO_FULL_INT_CLR (BIT(0))
#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_CLR_V 0x1
#define I2C_RXFIFO_FULL_INT_CLR_S 0
#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028)
/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: The enable bit for tx_send_empty_int interrupt.*/
#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1
#define I2C_TX_SEND_EMPTY_INT_ENA_S 12
/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The enable bit for rx_rec_full_int interrupt.*/
#define I2C_RX_REC_FULL_INT_ENA (BIT(11))
#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11))
#define I2C_RX_REC_FULL_INT_ENA_V 0x1
#define I2C_RX_REC_FULL_INT_ENA_S 11
/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: The enable bit for ack_err_int interrupt.*/
#define I2C_ACK_ERR_INT_ENA (BIT(10))
#define I2C_ACK_ERR_INT_ENA_M (BIT(10))
#define I2C_ACK_ERR_INT_ENA_V 0x1
#define I2C_ACK_ERR_INT_ENA_S 10
/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: The enable bit for trans_start_int interrupt.*/
#define I2C_TRANS_START_INT_ENA (BIT(9))
#define I2C_TRANS_START_INT_ENA_M (BIT(9))
#define I2C_TRANS_START_INT_ENA_V 0x1
#define I2C_TRANS_START_INT_ENA_S 9
/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: The enable bit for time_out_int interrupt.*/
#define I2C_TIME_OUT_INT_ENA (BIT(8))
#define I2C_TIME_OUT_INT_ENA_M (BIT(8))
#define I2C_TIME_OUT_INT_ENA_V 0x1
#define I2C_TIME_OUT_INT_ENA_S 8
/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The enable bit for trans_complete_int interrupt.*/
#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1
#define I2C_TRANS_COMPLETE_INT_ENA_S 7
/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The enable bit for master_tran_comp_int interrupt.*/
#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6
/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The enable bit for arbitration_lost_int interrupt.*/
#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1
#define I2C_ARBITRATION_LOST_INT_ENA_S 5
/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The enable bit for slave_tran_comp_int interrupt.*/
#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4
/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The enable bit for end_detect_int interrupt.*/
#define I2C_END_DETECT_INT_ENA (BIT(3))
#define I2C_END_DETECT_INT_ENA_M (BIT(3))
#define I2C_END_DETECT_INT_ENA_V 0x1
#define I2C_END_DETECT_INT_ENA_S 3
/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The enable bit for rxfifo_ovf_int interrupt.*/
#define I2C_RXFIFO_OVF_INT_ENA (BIT(2))
#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_ENA_V 0x1
#define I2C_RXFIFO_OVF_INT_ENA_S 2
/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The enable bit for txfifo_empty_int interrupt.*/
#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1
#define I2C_TXFIFO_EMPTY_INT_ENA_S 1
/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The enable bit for rxfifo_full_int interrupt.*/
#define I2C_RXFIFO_FULL_INT_ENA (BIT(0))
#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_ENA_V 0x1
#define I2C_RXFIFO_FULL_INT_ENA_S 0
#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c)
/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: The masked interrupt status for tx_send_empty_int interrupt.*/
#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1
#define I2C_TX_SEND_EMPTY_INT_ST_S 12
/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The masked interrupt status for rx_rec_full_int interrupt.*/
#define I2C_RX_REC_FULL_INT_ST (BIT(11))
#define I2C_RX_REC_FULL_INT_ST_M (BIT(11))
#define I2C_RX_REC_FULL_INT_ST_V 0x1
#define I2C_RX_REC_FULL_INT_ST_S 11
/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The masked interrupt status for ack_err_int interrupt.*/
#define I2C_ACK_ERR_INT_ST (BIT(10))
#define I2C_ACK_ERR_INT_ST_M (BIT(10))
#define I2C_ACK_ERR_INT_ST_V 0x1
#define I2C_ACK_ERR_INT_ST_S 10
/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The masked interrupt status for trans_start_int interrupt.*/
#define I2C_TRANS_START_INT_ST (BIT(9))
#define I2C_TRANS_START_INT_ST_M (BIT(9))
#define I2C_TRANS_START_INT_ST_V 0x1
#define I2C_TRANS_START_INT_ST_S 9
/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The masked interrupt status for time_out_int interrupt.*/
#define I2C_TIME_OUT_INT_ST (BIT(8))
#define I2C_TIME_OUT_INT_ST_M (BIT(8))
#define I2C_TIME_OUT_INT_ST_V 0x1
#define I2C_TIME_OUT_INT_ST_S 8
/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The masked interrupt status for trans_complete_int interrupt.*/
#define I2C_TRANS_COMPLETE_INT_ST (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ST_V 0x1
#define I2C_TRANS_COMPLETE_INT_ST_S 7
/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The masked interrupt status for master_tran_comp_int interrupt.*/
#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_ST_S 6
/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The masked interrupt status for arbitration_lost_int interrupt.*/
#define I2C_ARBITRATION_LOST_INT_ST (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ST_V 0x1
#define I2C_ARBITRATION_LOST_INT_ST_S 5
/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/
#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4
/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The masked interrupt status for end_detect_int interrupt.*/
#define I2C_END_DETECT_INT_ST (BIT(3))
#define I2C_END_DETECT_INT_ST_M (BIT(3))
#define I2C_END_DETECT_INT_ST_V 0x1
#define I2C_END_DETECT_INT_ST_S 3
/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/
#define I2C_RXFIFO_OVF_INT_ST (BIT(2))
#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_ST_V 0x1
#define I2C_RXFIFO_OVF_INT_ST_S 2
/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The masked interrupt status for txfifo_empty_int interrupt.*/
#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1
#define I2C_TXFIFO_EMPTY_INT_ST_S 1
/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The masked interrupt status for rxfifo_full_int interrupt.*/
#define I2C_RXFIFO_FULL_INT_ST (BIT(0))
#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_ST_V 0x1
#define I2C_RXFIFO_FULL_INT_ST_S 0
#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030)
/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*description: This register is used to configure the clock num I2C used to
hold the data after the negedge of SCL.*/
#define I2C_SDA_HOLD_TIME 0x000003FF
#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
#define I2C_SDA_HOLD_TIME_V 0x3FF
#define I2C_SDA_HOLD_TIME_S 0
#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034)
/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*description: This register is used to configure the clock num I2C used to
sample data on SDA after the posedge of SCL*/
#define I2C_SDA_SAMPLE_TIME 0x000003FF
#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))
#define I2C_SDA_SAMPLE_TIME_V 0x3FF
#define I2C_SDA_SAMPLE_TIME_S 0
#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038)
/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This register is used to configure the clock num during SCL is low level.*/
#define I2C_SCL_HIGH_PERIOD 0x00003FFF
#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
#define I2C_SCL_HIGH_PERIOD_V 0x3FFF
#define I2C_SCL_HIGH_PERIOD_S 0
#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040)
/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
/*description: This register is used to configure the clock num between the
negedge of SDA and negedge of SCL for start mark.*/
#define I2C_SCL_START_HOLD_TIME 0x000003FF
#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
#define I2C_SCL_START_HOLD_TIME_V 0x3FF
#define I2C_SCL_START_HOLD_TIME_S 0
#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044)
/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
/*description: This register is used to configure the clock num between the
posedge of SCL and the negedge of SDA for restart mark.*/
#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF
#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))
#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF
#define I2C_SCL_RSTART_SETUP_TIME_S 0
#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048)
/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This register is used to configure the clock num after the STOP bit's posedge.*/
#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF
#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF
#define I2C_SCL_STOP_HOLD_TIME_S 0
#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C)
/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*description: This register is used to configure the clock num between the
posedge of SCL and the posedge of SDA.*/
#define I2C_SCL_STOP_SETUP_TIME 0x000003FF
#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF
#define I2C_SCL_STOP_SETUP_TIME_S 0
#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050)
/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: This is the filter enable bit for SCL.*/
#define I2C_SCL_FILTER_EN (BIT(3))
#define I2C_SCL_FILTER_EN_M (BIT(3))
#define I2C_SCL_FILTER_EN_V 0x1
#define I2C_SCL_FILTER_EN_S 3
/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: When input SCL's pulse width is smaller than this register value
I2C ignores this pulse.*/
#define I2C_SCL_FILTER_THRES 0x00000007
#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))
#define I2C_SCL_FILTER_THRES_V 0x7
#define I2C_SCL_FILTER_THRES_S 0
#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054)
/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: This is the filter enable bit for SDA.*/
#define I2C_SDA_FILTER_EN (BIT(3))
#define I2C_SDA_FILTER_EN_M (BIT(3))
#define I2C_SDA_FILTER_EN_V 0x1
#define I2C_SDA_FILTER_EN_S 3
/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: When input SCL's pulse width is smaller than this register value
I2C ignores this pulse.*/
#define I2C_SDA_FILTER_THRES 0x00000007
#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))
#define I2C_SDA_FILTER_THRES_V 0x7
#define I2C_SDA_FILTER_THRES_S 0
#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058)
/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command0 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND0_DONE (BIT(31))
#define I2C_COMMAND0_DONE_M (BIT(31))
#define I2C_COMMAND0_DONE_V 0x1
#define I2C_COMMAND0_DONE_S 31
/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command0. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND0 0x00003FFF
#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
#define I2C_COMMAND0_V 0x3FFF
#define I2C_COMMAND0_S 0
#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C)
/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command1 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND1_DONE (BIT(31))
#define I2C_COMMAND1_DONE_M (BIT(31))
#define I2C_COMMAND1_DONE_V 0x1
#define I2C_COMMAND1_DONE_S 31
/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command1. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND1 0x00003FFF
#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
#define I2C_COMMAND1_V 0x3FFF
#define I2C_COMMAND1_S 0
#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060)
/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command2 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND2_DONE (BIT(31))
#define I2C_COMMAND2_DONE_M (BIT(31))
#define I2C_COMMAND2_DONE_V 0x1
#define I2C_COMMAND2_DONE_S 31
/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command2. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND2 0x00003FFF
#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
#define I2C_COMMAND2_V 0x3FFF
#define I2C_COMMAND2_S 0
#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064)
/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command3 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND3_DONE (BIT(31))
#define I2C_COMMAND3_DONE_M (BIT(31))
#define I2C_COMMAND3_DONE_V 0x1
#define I2C_COMMAND3_DONE_S 31
/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command3. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND3 0x00003FFF
#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))
#define I2C_COMMAND3_V 0x3FFF
#define I2C_COMMAND3_S 0
#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068)
/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command4 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND4_DONE (BIT(31))
#define I2C_COMMAND4_DONE_M (BIT(31))
#define I2C_COMMAND4_DONE_V 0x1
#define I2C_COMMAND4_DONE_S 31
/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command4. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND4 0x00003FFF
#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
#define I2C_COMMAND4_V 0x3FFF
#define I2C_COMMAND4_S 0
#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C)
/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command5 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND5_DONE (BIT(31))
#define I2C_COMMAND5_DONE_M (BIT(31))
#define I2C_COMMAND5_DONE_V 0x1
#define I2C_COMMAND5_DONE_S 31
/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command5. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND5 0x00003FFF
#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
#define I2C_COMMAND5_V 0x3FFF
#define I2C_COMMAND5_S 0
#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070)
/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command6 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND6_DONE (BIT(31))
#define I2C_COMMAND6_DONE_M (BIT(31))
#define I2C_COMMAND6_DONE_V 0x1
#define I2C_COMMAND6_DONE_S 31
/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command6. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND6 0x00003FFF
#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
#define I2C_COMMAND6_V 0x3FFF
#define I2C_COMMAND6_S 0
#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074)
/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command7 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND7_DONE (BIT(31))
#define I2C_COMMAND7_DONE_M (BIT(31))
#define I2C_COMMAND7_DONE_V 0x1
#define I2C_COMMAND7_DONE_S 31
/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command7. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND7 0x00003FFF
#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))
#define I2C_COMMAND7_V 0x3FFF
#define I2C_COMMAND7_S 0
#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078)
/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command8 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND8_DONE (BIT(31))
#define I2C_COMMAND8_DONE_M (BIT(31))
#define I2C_COMMAND8_DONE_V 0x1
#define I2C_COMMAND8_DONE_S 31
/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command8. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND8 0x00003FFF
#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S))
#define I2C_COMMAND8_V 0x3FFF
#define I2C_COMMAND8_S 0
#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C)
/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command9 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND9_DONE (BIT(31))
#define I2C_COMMAND9_DONE_M (BIT(31))
#define I2C_COMMAND9_DONE_V 0x1
#define I2C_COMMAND9_DONE_S 31
/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command9. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND9 0x00003FFF
#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S))
#define I2C_COMMAND9_V 0x3FFF
#define I2C_COMMAND9_S 0
#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080)
/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command10 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND10_DONE (BIT(31))
#define I2C_COMMAND10_DONE_M (BIT(31))
#define I2C_COMMAND10_DONE_V 0x1
#define I2C_COMMAND10_DONE_S 31
/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command10. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND10 0x00003FFF
#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S))
#define I2C_COMMAND10_V 0x3FFF
#define I2C_COMMAND10_S 0
#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084)
/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command11 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND11_DONE (BIT(31))
#define I2C_COMMAND11_DONE_M (BIT(31))
#define I2C_COMMAND11_DONE_V 0x1
#define I2C_COMMAND11_DONE_S 31
/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command11. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND11 0x00003FFF
#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S))
#define I2C_COMMAND11_V 0x3FFF
#define I2C_COMMAND11_S 0
#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088)
/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command12 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND12_DONE (BIT(31))
#define I2C_COMMAND12_DONE_M (BIT(31))
#define I2C_COMMAND12_DONE_V 0x1
#define I2C_COMMAND12_DONE_S 31
/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command12. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND12 0x00003FFF
#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S))
#define I2C_COMMAND12_V 0x3FFF
#define I2C_COMMAND12_S 0
#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C)
/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command13 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND13_DONE (BIT(31))
#define I2C_COMMAND13_DONE_M (BIT(31))
#define I2C_COMMAND13_DONE_V 0x1
#define I2C_COMMAND13_DONE_S 31
/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command13. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND13 0x00003FFF
#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S))
#define I2C_COMMAND13_V 0x3FFF
#define I2C_COMMAND13_S 0
#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090)
/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command14 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND14_DONE (BIT(31))
#define I2C_COMMAND14_DONE_M (BIT(31))
#define I2C_COMMAND14_DONE_V 0x1
#define I2C_COMMAND14_DONE_S 31
/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command14. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND14 0x00003FFF
#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S))
#define I2C_COMMAND14_V 0x3FFF
#define I2C_COMMAND14_S 0
#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094)
/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command15 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND15_DONE (BIT(31))
#define I2C_COMMAND15_DONE_M (BIT(31))
#define I2C_COMMAND15_DONE_V 0x1
#define I2C_COMMAND15_DONE_S 31
/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command15. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND15 0x00003FFF
#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S))
#define I2C_COMMAND15_V 0x3FFF
#define I2C_COMMAND15_S 0
#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8)
/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */
/*description: */
#define I2C_DATE 0xFFFFFFFF
#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S))
#define I2C_DATE_V 0xFFFFFFFF
#define I2C_DATE_S 0
#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100)
#endif /*_SOC_I2C_REG_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_I2C_STRUCT_H_
#define _SOC_I2C_STRUCT_H_
typedef volatile struct {
union {
struct {
uint32_t scl_low_period:14; /*This register is used to configure the low level width of SCL clock.*/
uint32_t reserved14: 18;
};
uint32_t val;
} scl_low_period;
union {
struct {
uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/
uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/
uint32_t reserved3: 1;
uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/
uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/
uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data need to be send. 1：receive data from most significant bit 0：receive data from least significant bit*/
uint32_t rx_lsb_first: 1; /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit 0：receive data from least significant bit*/
uint32_t clk_en: 1; /*This is the clock gating control bit for reading or writing registers.*/
uint32_t reserved9: 23;
};
uint32_t val;
} ctr;
union {
struct {
uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/
uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/
uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/
uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/
uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/
uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/
uint32_t reserved7: 1;
uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/
uint32_t reserved14: 4;
uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/
uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
uint32_t reserved27: 1;
uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/
uint32_t reserved31: 1;
};
uint32_t val;
} status_reg;
union {
struct {
uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data.*/
uint32_t reserved20:12;
};
uint32_t val;
} timeout;
union {
struct {
uint32_t addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/
uint32_t reserved15: 16;
uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/
};
uint32_t val;
} slave_addr;
union {
struct {
uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/
uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/
uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/
uint32_t reserved20: 12;
};
uint32_t val;
} fifo_st;
union {
struct {
uint32_t rx_fifo_full_thrhd: 5;
uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/
uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/
uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/
uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/
uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/
uint32_t nonfifo_rx_thres: 6; /*when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
uint32_t nonfifo_tx_thres: 6; /*when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
uint32_t reserved26: 6;
};
uint32_t val;
} fifo_conf;
union {
struct {
uint8_t data; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
uint8_t reserved[3];
};
uint32_t val;
} fifo_data;
union {
struct {
uint32_t rx_fifo_full: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/
uint32_t tx_fifo_empty: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/
uint32_t rx_fifo_ovf: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/
uint32_t end_detect: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
uint32_t trans_complete: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
uint32_t time_out: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
uint32_t trans_start: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/
uint32_t ack_err: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
uint32_t rx_rec_full: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/
uint32_t tx_fifo_empty: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/
uint32_t rx_fifo_ovf: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/
uint32_t end_detect: 1; /*Set this bit to clear the end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*Set this bit to clear the master_tran_comp interrupt.*/
uint32_t trans_complete: 1; /*Set this bit to clear the trans_complete_int interrupt.*/
uint32_t time_out: 1; /*Set this bit to clear the time_out_int interrupt.*/
uint32_t trans_start: 1; /*Set this bit to clear the trans_start_int interrupt.*/
uint32_t ack_err: 1; /*Set this bit to clear the ack_err_int interrupt.*/
uint32_t rx_rec_full: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t rx_fifo_full: 1; /*The enable bit for rx_fifo_full_int interrupt.*/
uint32_t tx_fifo_empty: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/
uint32_t rx_fifo_ovf: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/
uint32_t end_detect: 1; /*The enable bit for end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*The enable bit for slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*The enable bit for arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*The enable bit for master_tran_comp_int interrupt.*/
uint32_t trans_complete: 1; /*The enable bit for trans_complete_int interrupt.*/
uint32_t time_out: 1; /*The enable bit for time_out_int interrupt.*/
uint32_t trans_start: 1; /*The enable bit for trans_start_int interrupt.*/
uint32_t ack_err: 1; /*The enable bit for ack_err_int interrupt.*/
uint32_t rx_rec_full: 1; /*The enable bit for rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*The enable bit for tx_send_empty_int interrupt.*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rx_fifo_full: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/
uint32_t tx_fifo_empty: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/
uint32_t rx_fifo_ovf: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/
uint32_t end_detect: 1; /*The masked interrupt status for end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/
uint32_t trans_complete: 1; /*The masked interrupt status for trans_complete_int interrupt.*/
uint32_t time_out: 1; /*The masked interrupt status for time_out_int interrupt.*/
uint32_t trans_start: 1; /*The masked interrupt status for trans_start_int interrupt.*/
uint32_t ack_err: 1; /*The masked interrupt status for ack_err_int interrupt.*/
uint32_t rx_rec_full: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_status;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
uint32_t reserved10: 22;
};
uint32_t val;
} sda_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
uint32_t reserved10: 22;
};
uint32_t val;
} sda_sample;
union {
struct {
uint32_t period: 14; /*This register is used to configure the clock num during SCL is low level.*/
uint32_t reserved14: 18;
};
uint32_t val;
} scl_high_period;
uint32_t reserved_3c;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
uint32_t reserved10: 22;
};
uint32_t val;
} scl_start_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
uint32_t reserved10: 22;
};
uint32_t val;
} scl_rstart_setup;
union {
struct {
uint32_t time: 14; /*This register is used to configure the clock num after the STOP bit's posedge.*/
uint32_t reserved14: 18;
};
uint32_t val;
} scl_stop_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
uint32_t reserved10: 22;
};
uint32_t val;
} scl_stop_setup;
union {
struct {
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
uint32_t en: 1; /*This is the filter enable bit for SCL.*/
uint32_t reserved4: 28;
};
uint32_t val;
} scl_filter_cfg;
union {
struct {
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
uint32_t en: 1; /*This is the filter enable bit for SDA.*/
uint32_t reserved4: 28;
};
uint32_t val;
} sda_filter_cfg;
union {
struct {
uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
uint32_t reserved14: 17;
uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/
};
uint32_t val;
} command[16];
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t date; /**/
uint32_t reserved_fc;
uint32_t fifo_start_addr; /*This the start address for ram when use apb nonfifo access.*/
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#endif /* _SOC_I2C_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_I2S_STRUCT_H_
#define _SOC_I2S_STRUCT_H_
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
union {
struct {
uint32_t tx_reset: 1;
uint32_t rx_reset: 1;
uint32_t tx_fifo_reset: 1;
uint32_t rx_fifo_reset: 1;
uint32_t tx_start: 1;
uint32_t rx_start: 1;
uint32_t tx_slave_mod: 1;
uint32_t rx_slave_mod: 1;
uint32_t tx_right_first: 1;
uint32_t rx_right_first: 1;
uint32_t tx_msb_shift: 1;
uint32_t rx_msb_shift: 1;
uint32_t tx_short_sync: 1;
uint32_t rx_short_sync: 1;
uint32_t tx_mono: 1;
uint32_t rx_mono: 1;
uint32_t tx_msb_right: 1;
uint32_t rx_msb_right: 1;
uint32_t sig_loopback: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} conf;
union {
struct {
uint32_t rx_take_data: 1;
uint32_t tx_put_data: 1;
uint32_t rx_wfull: 1;
uint32_t rx_rempty: 1;
uint32_t tx_wfull: 1;
uint32_t tx_rempty: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t out_total_eof: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_take_data: 1;
uint32_t tx_put_data: 1;
uint32_t rx_wfull: 1;
uint32_t rx_rempty: 1;
uint32_t tx_wfull: 1;
uint32_t tx_rempty: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t out_total_eof: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rx_take_data: 1;
uint32_t tx_put_data: 1;
uint32_t rx_wfull: 1;
uint32_t rx_rempty: 1;
uint32_t tx_wfull: 1;
uint32_t tx_rempty: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t out_total_eof: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t take_data: 1;
uint32_t put_data: 1;
uint32_t rx_wfull: 1;
uint32_t rx_rempty: 1;
uint32_t tx_wfull: 1;
uint32_t tx_rempty: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t out_total_eof: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t tx_bck_in_delay: 2;
uint32_t tx_ws_in_delay: 2;
uint32_t rx_bck_in_delay: 2;
uint32_t rx_ws_in_delay: 2;
uint32_t rx_sd_in_delay: 2;
uint32_t tx_bck_out_delay: 2;
uint32_t tx_ws_out_delay: 2;
uint32_t tx_sd_out_delay: 2;
uint32_t rx_ws_out_delay: 2;
uint32_t rx_bck_out_delay: 2;
uint32_t tx_dsync_sw: 1;
uint32_t rx_dsync_sw: 1;
uint32_t data_enable_delay: 2;
uint32_t tx_bck_in_inv: 1;
uint32_t reserved25: 7;
};
uint32_t val;
} timing;
union {
struct {
uint32_t rx_data_num: 6;
uint32_t tx_data_num: 6;
uint32_t dscr_en: 1;
uint32_t tx_fifo_mod: 3;
uint32_t rx_fifo_mod: 3;
uint32_t tx_fifo_mod_force_en: 1;
uint32_t rx_fifo_mod_force_en: 1;
uint32_t reserved21: 11;
};
uint32_t val;
} fifo_conf;
uint32_t rx_eof_num;
uint32_t conf_single_data;
union {
struct {
uint32_t tx_chan_mod: 3;
uint32_t rx_chan_mod: 2;
uint32_t reserved5: 27;
};
uint32_t val;
} conf_chan;
union {
struct {
uint32_t addr: 20;
uint32_t reserved20: 8;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t park: 1;
};
uint32_t val;
} out_link;
union {
struct {
uint32_t addr: 20;
uint32_t reserved20: 8;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t park: 1;
};
uint32_t val;
} in_link;
uint32_t out_eof_des_addr;
uint32_t in_eof_des_addr;
uint32_t out_eof_bfr_des_addr;
union {
struct {
uint32_t mode: 3;
uint32_t reserved3: 1;
uint32_t addr: 2;
uint32_t reserved6: 26;
};
uint32_t val;
} ahb_test;
uint32_t in_link_dscr;
uint32_t in_link_dscr_bf0;
uint32_t in_link_dscr_bf1;
uint32_t out_link_dscr;
uint32_t out_link_dscr_bf0;
uint32_t out_link_dscr_bf1;
union {
struct {
uint32_t in_rst: 1;
uint32_t out_rst: 1;
uint32_t ahbm_fifo_rst: 1;
uint32_t ahbm_rst: 1;
uint32_t out_loop_test: 1;
uint32_t in_loop_test: 1;
uint32_t out_auto_wrback: 1;
uint32_t out_no_restart_clr: 1;
uint32_t out_eof_mode: 1;
uint32_t outdscr_burst_en: 1;
uint32_t indscr_burst_en: 1;
uint32_t out_data_burst_en: 1;
uint32_t check_owner: 1;
uint32_t mem_trans_en: 1;
uint32_t reserved14: 18;
};
uint32_t val;
} lc_conf;
union {
struct {
uint32_t wdata: 9;
uint32_t reserved9: 7;
uint32_t push: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} out_fifo_push;
union {
struct {
uint32_t rdata: 12;
uint32_t reserved12: 4;
uint32_t pop: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} in_fifo_pop;
uint32_t lc_state0;
uint32_t lc_state1;
union {
struct {
uint32_t fifo_timeout: 8;
uint32_t fifo_timeout_shift: 3;
uint32_t fifo_timeout_ena: 1;
uint32_t reserved12: 20;
};
uint32_t val;
} lc_hung_conf;
uint32_t reserved_78;
uint32_t reserved_7c;
union {
struct {
uint32_t y_max:16;
uint32_t y_min:16;
};
uint32_t val;
} cvsd_conf0;
union {
struct {
uint32_t sigma_max:16;
uint32_t sigma_min:16;
};
uint32_t val;
} cvsd_conf1;
union {
struct {
uint32_t cvsd_k: 3;
uint32_t cvsd_j: 3;
uint32_t cvsd_beta: 10;
uint32_t cvsd_h: 3;
uint32_t reserved19:13;
};
uint32_t val;
} cvsd_conf2;
union {
struct {
uint32_t good_pack_max: 6;
uint32_t n_err_seg: 3;
uint32_t shift_rate: 3;
uint32_t max_slide_sample: 8;
uint32_t pack_len_8k: 5;
uint32_t n_min_err: 3;
uint32_t reserved28: 4;
};
uint32_t val;
} plc_conf0;
union {
struct {
uint32_t bad_cef_atten_para: 8;
uint32_t bad_cef_atten_para_shift: 4;
uint32_t bad_ola_win2_para_shift: 4;
uint32_t bad_ola_win2_para: 8;
uint32_t slide_win_len: 8;
};
uint32_t val;
} plc_conf1;
union {
struct {
uint32_t cvsd_seg_mod: 2;
uint32_t min_period: 5;
uint32_t reserved7: 25;
};
uint32_t val;
} plc_conf2;
union {
struct {
uint32_t en: 1;
uint32_t chan_mod: 1;
uint32_t cvsd_dec_pack_err: 1;
uint32_t cvsd_pack_len_8k: 5;
uint32_t cvsd_inf_en: 1;
uint32_t cvsd_dec_start: 1;
uint32_t cvsd_dec_reset: 1;
uint32_t plc_en: 1;
uint32_t plc2dma_en: 1;
uint32_t reserved13: 19;
};
uint32_t val;
} esco_conf0;
union {
struct {
uint32_t with_en: 1;
uint32_t no_en: 1;
uint32_t cvsd_enc_start: 1;
uint32_t cvsd_enc_reset: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} sco_conf0;
union {
struct {
uint32_t tx_pcm_conf: 3;
uint32_t tx_pcm_bypass: 1;
uint32_t rx_pcm_conf: 3;
uint32_t rx_pcm_bypass: 1;
uint32_t tx_stop_en: 1;
uint32_t tx_zeros_rm_en: 1;
uint32_t reserved10: 22;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t fifo_force_pd: 1;
uint32_t fifo_force_pu: 1;
uint32_t plc_mem_force_pd: 1;
uint32_t plc_mem_force_pu: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} pd_conf;
union {
struct {
uint32_t camera_en: 1;
uint32_t lcd_tx_wrx2_en: 1;
uint32_t lcd_tx_sdx2_en: 1;
uint32_t data_enable_test_en: 1;
uint32_t data_enable: 1;
uint32_t lcd_en: 1;
uint32_t ext_adc_start_en: 1;
uint32_t inter_valid_en: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} conf2;
union {
struct {
uint32_t clkm_div_num: 8;
uint32_t clkm_div_b: 6;
uint32_t clkm_div_a: 6;
uint32_t clk_en: 1;
uint32_t clka_en: 1;
uint32_t reserved22: 10;
};
uint32_t val;
} clkm_conf;
union {
struct {
uint32_t tx_bck_div_num: 6;
uint32_t rx_bck_div_num: 6;
uint32_t tx_bits_mod: 6;
uint32_t rx_bits_mod: 6;
uint32_t reserved24: 8;
};
uint32_t val;
} sample_rate_conf;
union {
struct {
uint32_t tx_pdm_en: 1;
uint32_t rx_pdm_en: 1;
uint32_t pcm2pdm_conv_en: 1;
uint32_t pdm2pcm_conv_en: 1;
uint32_t tx_sinc_osr2: 4;
uint32_t tx_prescale: 8;
uint32_t tx_hp_in_shift: 2;
uint32_t tx_lp_in_shift: 2;
uint32_t tx_sinc_in_shift: 2;
uint32_t tx_sigmadelta_in_shift: 2;
uint32_t rx_sinc_dsr_16_en: 1;
uint32_t txhp_bypass: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} pdm_conf;
union {
struct {
uint32_t tx_pdm_fs: 10;
uint32_t tx_pdm_fp: 10;
uint32_t reserved20:12;
};
uint32_t val;
} pdm_freq_conf;
union {
struct {
uint32_t tx_idle: 1;
uint32_t tx_fifo_reset_back: 1;
uint32_t rx_fifo_reset_back: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} state;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
} i2s_dev_t;
extern i2s_dev_t I2S0;
extern i2s_dev_t I2S1;
#endif /* _SOC_I2S_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_IO_MUX_REG_H_
#define _SOC_IO_MUX_REG_H_
#include "soc.h"
#define SLP_OE (BIT(0))
#define SLP_SEL (BIT(1))
#define SLP_PD (BIT(2))
#define SLP_PU (BIT(3))
#define SLP_IE (BIT(4))
#define SLP_DRV 0x3
#define SLP_DRV_S 5
#define FUN_PD (BIT(7))
#define FUN_PU (BIT(8))
#define FUN_IE (BIT(9))
#define FUN_DRV 0x3
#define FUN_DRV_S 10
#define MCU_SEL 0x7
#define MCU_SEL_S 12
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define PIN_FUNC_GPIO 2
#define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00)
#define CLK_OUT3 0xf
#define CLK_OUT3_S 8
#define CLK_OUT2 0xf
#define CLK_OUT2_S 4
#define CLK_OUT1 0xf
#define CLK_OUT1_S 0
#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44)
#define FUNC_GPIO0_EMAC_TX_CLK 5
#define FUNC_GPIO0_GPIO0 2
#define FUNC_GPIO0_CLK_OUT1 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88)
#define FUNC_U0TXD_EMAC_RXD2 3
#define FUNC_U0TXD_GPIO1 2
#define FUNC_U0TXD_CLK_OUT3 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40)
#define FUNC_GPIO2_SD_DATA0 4
#define FUNC_GPIO2_HS2_DATA0 3
#define FUNC_GPIO2_GPIO2 2
#define FUNC_GPIO2_HSPIWP 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84)
#define FUNC_U0RXD_GPIO3 2
#define FUNC_U0RXD_CLK_OUT2 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48)
#define FUNC_GPIO4_EMAC_TX_ER 5
#define FUNC_GPIO4_SD_DATA1 4
#define FUNC_GPIO4_HS2_DATA1 3
#define FUNC_GPIO4_GPIO4 2
#define FUNC_GPIO4_HSPIHD 1
#define FUNC_GPIO4_GPIO4_0 0
#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c)
#define FUNC_GPIO5_EMAC_RX_CLK 5
#define FUNC_GPIO5_HS1_DATA6 3
#define FUNC_GPIO5_GPIO5 2
#define FUNC_GPIO5_VSPICS0 1
#define FUNC_GPIO5_GPIO5_0 0
#define PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60)
#define FUNC_SD_CLK_U1CTS 4
#define FUNC_SD_CLK_HS1_CLK 3
#define FUNC_SD_CLK_GPIO6 2
#define FUNC_SD_CLK_SPICLK 1
#define FUNC_SD_CLK_SD_CLK 0
#define PERIPHS_IO_MUX_SD_DATA0_U (DR_REG_IO_MUX_BASE +0x64)
#define FUNC_SD_DATA0_U2RTS 4
#define FUNC_SD_DATA0_HS1_DATA0 3
#define FUNC_SD_DATA0_GPIO7 2
#define FUNC_SD_DATA0_SPIQ 1
#define FUNC_SD_DATA0_SD_DATA0 0
#define PERIPHS_IO_MUX_SD_DATA1_U (DR_REG_IO_MUX_BASE +0x68)
#define FUNC_SD_DATA1_U2CTS 4
#define FUNC_SD_DATA1_HS1_DATA1 3
#define FUNC_SD_DATA1_GPIO8 2
#define FUNC_SD_DATA1_SPID 1
#define FUNC_SD_DATA1_SD_DATA1 0
#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54)
#define FUNC_SD_DATA2_U1RXD 4
#define FUNC_SD_DATA2_HS1_DATA2 3
#define FUNC_SD_DATA2_GPIO9 2
#define FUNC_SD_DATA2_SPIHD 1
#define FUNC_SD_DATA2_SD_DATA2 0
#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58)
#define FUNC_SD_DATA3_U1TXD 4
#define FUNC_SD_DATA3_HS1_DATA3 3
#define FUNC_SD_DATA3_GPIO10 2
#define FUNC_SD_DATA3_SPIWP 1
#define FUNC_SD_DATA3_SD_DATA3 0
#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c)
#define FUNC_SD_CMD_U1RTS 4
#define FUNC_SD_CMD_HS1_CMD 3
#define FUNC_SD_CMD_GPIO11 2
#define FUNC_SD_CMD_SPICS0 1
#define FUNC_SD_CMD_SD_CMD 0
#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34)
#define FUNC_MTDI_EMAC_TXD3 5
#define FUNC_MTDI_SD_DATA2 4
#define FUNC_MTDI_HS2_DATA2 3
#define FUNC_MTDI_GPIO12 2
#define FUNC_MTDI_HSPIQ 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38)
#define FUNC_MTCK_EMAC_RX_ER 5
#define FUNC_MTCK_SD_DATA3 4
#define FUNC_MTCK_HS2_DATA3 3
#define FUNC_MTCK_GPIO13 2
#define FUNC_MTCK_HSPID 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30)
#define FUNC_MTMS_EMAC_TXD2 5
#define FUNC_MTMS_SD_CLK 4
#define FUNC_MTMS_HS2_CLk 3
#define FUNC_MTMS_GPIO14 2
#define FUNC_MTMS_HSPICLK 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c)
#define FUNC_MTDO_EMAC_RXD3 5
#define FUNC_MTDO_SD_CMD 4
#define FUNC_MTDO_HS2_CMD 3
#define FUNC_MTDO_GPIO15 2
#define FUNC_MTDO_HSPICS0 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c)
#define FUNC_GPIO16_EMAC_CLK_OUT 5
#define FUNC_GPIO16_U2RXD 4
#define FUNC_GPIO16_HS1_DATA4 3
#define FUNC_GPIO16_GPIO16 2
#define FUNC_GPIO16_GPIO16_0 0
#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50)
#define FUNC_GPIO17_EMAC_CLK_OUT_180 5
#define FUNC_GPIO17_U2TXD 4
#define FUNC_GPIO17_HS1_DATA5 3
#define FUNC_GPIO17_GPIO17 2
#define FUNC_GPIO17_GPIO17_0 0
#define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70)
#define FUNC_GPIO18_HS1_DATA7 3
#define FUNC_GPIO18_GPIO18 2
#define FUNC_GPIO18_VSPICLK 1
#define FUNC_GPIO18_GPIO18_0 0
#define PERIPHS_IO_MUX_GPIO19_U (DR_REG_IO_MUX_BASE +0x74)
#define FUNC_GPIO19_EMAC_TXD0 5
#define FUNC_GPIO19_U0CTS 3
#define FUNC_GPIO19_GPIO19 2
#define FUNC_GPIO19_VSPIQ 1
#define FUNC_GPIO19_GPIO19_0 0
#define PERIPHS_IO_MUX_GPIO20_U (DR_REG_IO_MUX_BASE +0x78)
#define FUNC_GPIO20_GPIO20 2
#define FUNC_GPIO20_GPIO20_0 0
#define PERIPHS_IO_MUX_GPIO21_U (DR_REG_IO_MUX_BASE +0x7c)
#define FUNC_GPIO21_EMAC_TX_EN 5
#define FUNC_GPIO21_GPIO21 2
#define FUNC_GPIO21_VSPIHD 1
#define FUNC_GPIO21_GPIO21_0 0
#define PERIPHS_IO_MUX_GPIO22_U (DR_REG_IO_MUX_BASE +0x80)
#define FUNC_GPIO22_EMAC_TXD1 5
#define FUNC_GPIO22_U0RTS 3
#define FUNC_GPIO22_GPIO22 2
#define FUNC_GPIO22_VSPIWP 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c)
#define FUNC_GPIO23_HS1_STROBE 3
#define FUNC_GPIO23_GPIO23 2
#define FUNC_GPIO23_VSPID 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_GPIO24_U (DR_REG_IO_MUX_BASE +0x90)
#define FUNC_GPIO24_GPIO24 2
#define FUNC_GPIO24_GPIO24_0 0
#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24)
#define FUNC_GPIO25_EMAC_RXD0 5
#define FUNC_GPIO25_GPIO25 2
#define FUNC_GPIO25_GPIO25_0 0
#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28)
#define FUNC_GPIO26_EMAC_RXD1 5
#define FUNC_GPIO26_GPIO26 2
#define FUNC_GPIO26_GPIO26_0 0
#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c)
#define FUNC_GPIO27_EMAC_RX_DV 5
#define FUNC_GPIO27_GPIO27 2
#define FUNC_GPIO27_GPIO27_0 0
#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c)
#define FUNC_GPIO32_GPIO32 2
#define FUNC_GPIO32_GPIO32_0 0
#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20)
#define FUNC_GPIO33_GPIO33 2
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14)
#define FUNC_GPIO34_GPIO34 2
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18)
#define FUNC_GPIO35_GPIO35 2
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04)
#define FUNC_GPIO36_GPIO36 2
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08)
#define FUNC_GPIO37_GPIO37 2
#define FUNC_GPIO37_GPIO37_0 0
#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c)
#define FUNC_GPIO38_GPIO38 2
#define FUNC_GPIO38_GPIO38_0 0
#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10)
#define FUNC_GPIO39_GPIO39 2
#define FUNC_GPIO39_GPIO39_0 0
#endif /* _SOC_IO_MUX_REG_H_ */

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tools/sdk/include/esp32/soc/ledc_reg.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_LEDC_STRUCT_H_
#define _SOC_LEDC_STRUCT_H_
typedef volatile struct {
struct {
struct {
union {
struct {
uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/
uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/
uint32_t reserved4: 27;
uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/
uint32_t reserved20: 12;
};
uint32_t val;
} hpoint;
union {
struct {
uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
uint32_t reserved25: 7;
};
uint32_t val;
} duty;
union {
struct {
uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/
uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/
uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/
uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/
uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/
uint32_t reserved25: 7;
};
uint32_t val;
} duty_rd;
} channel[8];
} channel_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
struct {
struct {
union {
struct {
uint32_t bit_num: 5; /*This register controls the range of the counter in high speed timer. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/
uint32_t div_num: 18; /*This register is used to configure parameter for divider in high speed timer the least significant eight bits represent the decimal part.*/
uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/
uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/
uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/
uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/
uint32_t reserved26: 5;
};
uint32_t val;
} conf;
union {
struct {
uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/
uint32_t reserved20: 12;
};
uint32_t val;
} value;
} timer[4];
} timer_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/
uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/
uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/
uint32_t hstimer3_ovf: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/
uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/
uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/
uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/
uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/
uint32_t duty_chng_end_hsch0: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/
uint32_t duty_chng_end_hsch5: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/
uint32_t duty_chng_end_hsch6: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/
uint32_t duty_chng_end_hsch7: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/
uint32_t hstimer1_ovf: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/
uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/
uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/
uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/
uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/
uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/
uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/
uint32_t duty_chng_end_hsch5: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/
uint32_t duty_chng_end_hsch6: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/
uint32_t duty_chng_end_hsch7: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/
uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/
uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/
uint32_t hstimer3_ovf: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/
uint32_t lstimer0_ovf: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/
uint32_t lstimer1_ovf: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/
uint32_t lstimer2_ovf: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/
uint32_t lstimer3_ovf: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/
uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_hsch5: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_hsch6: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_hsch7: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/
uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/
uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/
uint32_t hstimer3_ovf: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/
uint32_t lstimer0_ovf: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/
uint32_t lstimer1_ovf: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/
uint32_t lstimer2_ovf: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/
uint32_t lstimer3_ovf: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/
uint32_t duty_chng_end_hsch0: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_hsch3: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_hsch4: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_hsch5: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_hsch6: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_hsch7: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/
uint32_t duty_chng_end_lsch0: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_lsch3: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_lsch4: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_lsch5: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_lsch6: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_lsch7: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t apb_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/
uint32_t reserved1: 31;
};
uint32_t val;
} conf;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t date; /*This register represents the version .*/
} ledc_dev_t;
extern ledc_dev_t LEDC;
#endif /* _SOC_LEDC_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_PCNT_STRUCT_H_
#define _SOC_PCNT_STRUCT_H_
typedef volatile struct {
struct{
union {
struct {
uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/
uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/
uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/
uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/
uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/
uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/
uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/
uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/
uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/
uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/
};
uint32_t val;
} conf2;
} conf_unit[8];
union {
struct {
uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/
uint32_t reserved16: 16;
};
uint32_t val;
} cnt_unit[8];
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/
uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/
uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/
uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/
uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/
uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/
uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/
uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_clr;
uint32_t status_unit[8];
union {
struct {
uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/
uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/
uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/
uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/
uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/
uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/
uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/
uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/
uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/
uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/
uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/
uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/
uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/
uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/
uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/
uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/
uint32_t clk_en: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} ctrl;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#endif /* _SOC_PCNT_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_PID_H_
#define _SOC_PID_H_
#define PROPID_GEN_BASE 0x3FF1F000
//Bits 1..7: 1 if interrupt will be triggering PID change
#define PROPID_CONFIG_INTERRUPT_ENABLE ((PROPID_GEN_BASE)+0x000)
//Vectors for the various interrupt handlers
#define PROPID_CONFIG_INTERRUPT_ADDR_1 ((PROPID_GEN_BASE)+0x004)
#define PROPID_CONFIG_INTERRUPT_ADDR_2 ((PROPID_GEN_BASE)+0x008)
#define PROPID_CONFIG_INTERRUPT_ADDR_3 ((PROPID_GEN_BASE)+0x00C)
#define PROPID_CONFIG_INTERRUPT_ADDR_4 ((PROPID_GEN_BASE)+0x010)
#define PROPID_CONFIG_INTERRUPT_ADDR_5 ((PROPID_GEN_BASE)+0x014)
#define PROPID_CONFIG_INTERRUPT_ADDR_6 ((PROPID_GEN_BASE)+0x018)
#define PROPID_CONFIG_INTERRUPT_ADDR_7 ((PROPID_GEN_BASE)+0x01C)
//Delay, in CPU cycles, before switching to new PID
#define PROPID_CONFIG_PID_DELAY ((PROPID_GEN_BASE)+0x020)
#define PROPID_CONFIG_NMI_DELAY ((PROPID_GEN_BASE)+0x024)
//Last detected interrupt. Set by hw on int.
#define PROPID_TABLE_LEVEL ((PROPID_GEN_BASE)+0x028)
//PID/prev int data for each int
#define PROPID_FROM_1 ((PROPID_GEN_BASE)+0x02C)
#define PROPID_FROM_2 ((PROPID_GEN_BASE)+0x030)
#define PROPID_FROM_3 ((PROPID_GEN_BASE)+0x034)
#define PROPID_FROM_4 ((PROPID_GEN_BASE)+0x038)
#define PROPID_FROM_5 ((PROPID_GEN_BASE)+0x03C)
#define PROPID_FROM_6 ((PROPID_GEN_BASE)+0x040)
#define PROPID_FROM_7 ((PROPID_GEN_BASE)+0x044)
#define PROPID_FROM_PID_MASK 0x7
#define PROPID_FROM_PID_S 0
#define PROPID_FROM_INT_MASK 0xF
#define PROPID_FROM_INT_S 3
//PID to be set after confirm routine
#define PROPID_PID_NEW ((PROPID_GEN_BASE)+0x048)
//Write to kick off PID change
#define PROPID_PID_CONFIRM ((PROPID_GEN_BASE)+0x04c)
//current PID?
#define PROPID_PID_REG ((PROPID_GEN_BASE)+0x050)
//Write to mask NMI
#define PROPID_PID_NMI_MASK_HW_ENABLE ((PROPID_GEN_BASE)+0x054)
//Write to unmask NMI
#define PROPID_PID_NMI_MASK_HW_DISABLE ((PROPID_GEN_BASE)+0x058)
#define PROPID_PID_NMI_MASK_HW_REG ((PROPID_GEN_BASE)+0x05c)
//Debug regs
#define PROPID_PID ((PROPID_GEN_BASE)+0x060)
#define PROPID_NMI_MASK_HW ((PROPID_GEN_BASE)+0x064)
#endif /* _SOC_PID_H_ */

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tools/sdk/include/esp32/soc/rmt_reg.h Normal file
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tools/sdk/include/esp32/soc/rmt_struct.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RMT_STRUCT_H_
#define _SOC_RMT_STRUCT_H_
typedef volatile struct {
uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/
struct{
union {
struct {
uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/
uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/
uint32_t mem_size: 4; /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/
uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/
uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on high output level.*/
uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/
uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/
uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/
uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/
uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/
uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/
uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/
uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/
uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/
uint32_t rx_filter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is smaller then this value.*/
uint32_t ref_cnt_rst: 1; /*This bit is used to reset divider in channel0-7.*/
uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/
uint32_t idle_out_en: 1; /*This is the output enable control bit for channel0-7 in IDLE state.*/
uint32_t reserved20: 12;
};
uint32_t val;
} conf1;
} conf_ch[8];
uint32_t status_ch[8]; /*The status for channel0-7*/
uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/
union {
struct {
uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/
uint32_t ch0_rx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/
uint32_t ch0_err: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/
uint32_t ch1_tx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/
uint32_t ch1_rx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/
uint32_t ch1_err: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/
uint32_t ch2_tx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/
uint32_t ch2_rx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/
uint32_t ch2_err: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/
uint32_t ch3_tx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/
uint32_t ch3_rx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/
uint32_t ch3_err: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/
uint32_t ch4_tx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/
uint32_t ch4_rx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/
uint32_t ch4_err: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/
uint32_t ch5_tx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/
uint32_t ch5_rx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/
uint32_t ch5_err: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/
uint32_t ch6_tx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/
uint32_t ch6_rx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/
uint32_t ch6_err: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/
uint32_t ch7_tx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/
uint32_t ch7_rx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/
uint32_t ch7_err: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/
uint32_t ch0_tx_thr_event: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch1_tx_thr_event: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch2_tx_thr_event: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch3_tx_thr_event: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch4_tx_thr_event: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch5_tx_thr_event: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch6_tx_thr_event: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch7_tx_thr_event: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/
uint32_t ch0_rx_end: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/
uint32_t ch0_err: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/
uint32_t ch1_tx_end: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/
uint32_t ch1_rx_end: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/
uint32_t ch1_err: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/
uint32_t ch2_tx_end: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/
uint32_t ch2_rx_end: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/
uint32_t ch2_err: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/
uint32_t ch3_tx_end: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/
uint32_t ch3_rx_end: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/
uint32_t ch3_err: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/
uint32_t ch4_tx_end: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/
uint32_t ch4_rx_end: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/
uint32_t ch4_err: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/
uint32_t ch5_tx_end: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/
uint32_t ch5_rx_end: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/
uint32_t ch5_err: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/
uint32_t ch6_tx_end: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/
uint32_t ch6_rx_end: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/
uint32_t ch6_err: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/
uint32_t ch7_tx_end: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/
uint32_t ch7_rx_end: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/
uint32_t ch7_err: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/
uint32_t ch0_tx_thr_event: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/
uint32_t ch1_tx_thr_event: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/
uint32_t ch2_tx_thr_event: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/
uint32_t ch3_tx_thr_event: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/
uint32_t ch4_tx_thr_event: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/
uint32_t ch5_tx_thr_event: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/
uint32_t ch6_tx_thr_event: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/
uint32_t ch7_tx_thr_event: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/
uint32_t ch0_rx_end: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/
uint32_t ch0_err: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/
uint32_t ch1_tx_end: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/
uint32_t ch1_rx_end: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/
uint32_t ch1_err: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/
uint32_t ch2_tx_end: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/
uint32_t ch2_rx_end: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/
uint32_t ch2_err: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/
uint32_t ch3_tx_end: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/
uint32_t ch3_rx_end: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/
uint32_t ch3_err: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/
uint32_t ch4_tx_end: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/
uint32_t ch4_rx_end: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/
uint32_t ch4_err: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/
uint32_t ch5_tx_end: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/
uint32_t ch5_rx_end: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/
uint32_t ch5_err: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/
uint32_t ch6_tx_end: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/
uint32_t ch6_rx_end: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/
uint32_t ch6_err: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/
uint32_t ch7_tx_end: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/
uint32_t ch7_rx_end: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/
uint32_t ch7_err: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/
uint32_t ch0_tx_thr_event: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
uint32_t ch1_tx_thr_event: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
uint32_t ch2_tx_thr_event: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
uint32_t ch3_tx_thr_event: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
uint32_t ch4_tx_thr_event: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
uint32_t ch5_tx_thr_event: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
uint32_t ch6_tx_thr_event: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
uint32_t ch7_tx_thr_event: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t ch0_tx_end: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
uint32_t ch0_rx_end: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
uint32_t ch0_err: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/
uint32_t ch1_tx_end: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
uint32_t ch1_rx_end: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
uint32_t ch1_err: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/
uint32_t ch2_tx_end: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
uint32_t ch2_rx_end: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
uint32_t ch2_err: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/
uint32_t ch3_tx_end: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
uint32_t ch3_rx_end: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
uint32_t ch3_err: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/
uint32_t ch4_tx_end: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
uint32_t ch4_rx_end: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
uint32_t ch4_err: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/
uint32_t ch5_tx_end: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
uint32_t ch5_rx_end: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
uint32_t ch5_err: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/
uint32_t ch6_tx_end: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
uint32_t ch6_rx_end: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
uint32_t ch6_err: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/
uint32_t ch7_tx_end: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
uint32_t ch7_rx_end: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
uint32_t ch7_err: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/
uint32_t ch0_tx_thr_event: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/
uint32_t ch1_tx_thr_event: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/
uint32_t ch2_tx_thr_event: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/
uint32_t ch3_tx_thr_event: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/
uint32_t ch4_tx_thr_event: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/
uint32_t ch5_tx_thr_event: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/
uint32_t ch6_tx_thr_event: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/
uint32_t ch7_tx_thr_event: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/
uint32_t high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/
};
uint32_t val;
} carrier_duty_ch[8];
union {
struct {
uint32_t limit: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/
uint32_t reserved9: 23;
};
uint32_t val;
} tx_lim_ch[8];
union {
struct {
uint32_t fifo_mask: 1; /*Set this bit to disable apb fifo access*/
uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/
uint32_t reserved2: 30;
};
uint32_t val;
} apb_conf;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /*This is the version register.*/
} rmt_dev_t;
extern rmt_dev_t RMT;
#endif /* _SOC_RMT_STRUCT_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ESP32_SOC_H_
#define _ESP32_SOC_H_
#include <stdint.h>
//Register Bits{{
#define BIT31 0x80000000
#define BIT30 0x40000000
#define BIT29 0x20000000
#define BIT28 0x10000000
#define BIT27 0x08000000
#define BIT26 0x04000000
#define BIT25 0x02000000
#define BIT24 0x01000000
#define BIT23 0x00800000
#define BIT22 0x00400000
#define BIT21 0x00200000
#define BIT20 0x00100000
#define BIT19 0x00080000
#define BIT18 0x00040000
#define BIT17 0x00020000
#define BIT16 0x00010000
#define BIT15 0x00008000
#define BIT14 0x00004000
#define BIT13 0x00002000
#define BIT12 0x00001000
#define BIT11 0x00000800
#define BIT10 0x00000400
#define BIT9 0x00000200
#define BIT8 0x00000100
#define BIT7 0x00000080
#define BIT6 0x00000040
#define BIT5 0x00000020
#define BIT4 0x00000010
#define BIT3 0x00000008
#define BIT2 0x00000004
#define BIT1 0x00000002
#define BIT0 0x00000001
//}}
#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#define BIT(nr) (1UL << (nr))
//write value to register
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
//read value from register
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
//get bit or get bits from register
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
//set bit or set bits to register
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
//clear bit or clear bits of register
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
//set bits of register controlled by mask
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
//get field from register, used when _f is not left shifted by _f##_S
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f))
//set field to register, used when _f is not left shifted by _f##_S
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S)))))
//get field value from a variable, used when _f is not left shifted by _f##_S
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//read value from register
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
//write value to register
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
//clear bits of register controlled by mask
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
//set bits of register controlled by mask
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
//get bits of register controlled by mask
#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
//get bits of register controlled by highest bit and lowest bit
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
//set bits of register controlled by mask and shift
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
//get field of register
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM 26*1000000
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ 80*1000000 //unit: Hz
#define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
#define SPI_CLK_DIV 4
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
//}}
#define DR_REG_DPORT_BASE 0x3ff00000
#define DR_REG_UART_BASE 0x3ff40000
#define DR_REG_SPI1_BASE 0x3ff42000
#define DR_REG_SPI0_BASE 0x3ff43000
#define DR_REG_GPIO_BASE 0x3ff44000
#define DR_REG_GPIO_SD_BASE 0x3ff44f00
#define DR_REG_FE2_BASE 0x3ff45000
#define DR_REG_FE_BASE 0x3ff46000
#define DR_REG_RTCCNTL_BASE 0x3ff48000
#define DR_REG_RTCIO_BASE 0x3ff48400
#define DR_REG_SARADC_BASE 0x3ff48800
#define DR_REG_IO_MUX_BASE 0x3ff49000
#define DR_REG_RTCMEM0_BASE 0x3ff61000
#define DR_REG_RTCMEM1_BASE 0x3ff62000
#define DR_REG_RTCMEM2_BASE 0x3ff63000
#define DR_REG_HINF_BASE 0x3ff4B000
#define DR_REG_UHCI1_BASE 0x3ff4C000
#define DR_REG_I2S_BASE 0x3ff4F000
#define DR_REG_UART1_BASE 0x3ff50000
#define DR_REG_BT_BASE 0x3ff51000
#define DR_REG_I2C_EXT_BASE 0x3ff53000
#define DR_REG_UHCI0_BASE 0x3ff54000
#define DR_REG_SLCHOST_BASE 0x3ff55000
#define DR_REG_RMT_BASE 0x3ff56000
#define DR_REG_PCNT_BASE 0x3ff57000
#define DR_REG_SLC_BASE 0x3ff58000
#define DR_REG_LEDC_BASE 0x3ff59000
#define DR_REG_EFUSE_BASE 0x3ff5A000
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
#define DR_REG_PWM_BASE 0x3ff5E000
#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
#define DR_REG_SPI2_BASE 0x3ff64000
#define DR_REG_SPI3_BASE 0x3ff65000
#define DR_REG_I2C1_EXT_BASE 0x3ff67000
#define DR_REG_SDMMC_BASE 0x3ff68000
#define DR_REG_EMAC_BASE 0x3ff69000
#define DR_REG_PWM1_BASE 0x3ff6C000
#define DR_REG_I2S1_BASE 0x3ff6D000
#define DR_REG_UART2_BASE 0x3ff6E000
#define DR_REG_PWM2_BASE 0x3ff6F000
#define DR_REG_PWM3_BASE 0x3ff70000
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/
#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/
#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/
#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/
#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/
#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/
#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/
#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/
#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/
#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/
#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/
#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/
#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/
#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/
#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/
#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/
#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/
#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/
#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/
#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/
#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/
#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/
#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/
#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/
#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/
#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/
#define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/
#define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/
#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/
#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/
#define ETS_CAN_INTR_SOURCE 45/**< interrupt of can, level*/
#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/
#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/
#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/
#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/
#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/
#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/
#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/
#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/
#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/
#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/
#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/
#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/
#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/
#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host VHCI Reserved
* 2 1 extern level FROM_CPU FROM_CPU
* 3 1 extern level TG0_WDT Reserved
* 4 1 extern level WBB
* 5 1 extern level BT Controller
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software Reserved Reserved
* 8 1 extern level BLE Controller
* 9 1 extern level
* 10 1 extern edge Internal Timer
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level
* 25 4 extern level Reserved Reserved
* 26 5 extern level Reserved Reserved
* 27 3 extern level Reserved Reserved
* 28 4 extern edge
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level Reserved Reserved
*************************************************************************************************************
*/
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_FROM_CPU_INUM 2
#define ETS_T0_WDT_INUM 3
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
//CPU0 Intrrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
//Other interrupt number should be managed by the user
#endif /* _ESP32_SOC_H_ */

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tools/sdk/include/esp32/soc/spi_reg.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_STRUCT_H_
#define _SOC_SPI_STRUCT_H_
typedef volatile struct {
union {
struct {
uint32_t reserved0: 16; /*reserved*/
uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
};
uint32_t val;
} cmd;
union {
struct {
uint32_t reserved : 8;
uint32_t usr_addr_value:24; /*[31:8]:address to slave [7:0]:Reserved.*/
};
uint32_t val;
} addr;
union {
struct {
uint32_t reserved0: 10; /*reserved*/
uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t wait_flash_idle_en: 1; /*wait flash idle when program flash or erase flash. 1: enable 0: disable.*/
uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t resandres: 1; /*The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.*/
uint32_t reserved16: 4; /*reserved*/
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/
uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/
uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
uint32_t reserved27: 5; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t reserved0: 16; /*reserved*/
uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/
uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/
};
uint32_t val;
} ctrl1;
union {
struct {
uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/
uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/
uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/
};
uint32_t val;
} rd_status;
union {
struct {
uint32_t setup_time: 4; /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/
uint32_t hold_time: 4; /*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/
uint32_t ck_out_low_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/
uint32_t ck_out_high_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/
uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/
uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/
uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/
uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/
uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
};
uint32_t val;
} clock;
union {
struct {
uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/
uint32_t reserved1: 3; /*reserved*/
uint32_t cs_hold: 1; /*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/
uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/
uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
uint32_t reserved8: 2; /*reserved*/
uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/
uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/
uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/
uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/
uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/
uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/
uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/
uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/
uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/
uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/
uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_t reserved8: 18; /*reserved*/
uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value: 16; /*The value of command.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_dbitlen:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} miso_dlen;
uint32_t slv_wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/
union {
struct {
uint32_t cs0_dis: 1; /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/
uint32_t cs1_dis: 1; /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/
uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/
uint32_t reserved3: 2; /*reserved*/
uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/
uint32_t master_cs_pol: 5; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
uint32_t master_ck_sel: 5; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/
uint32_t reserved16: 13; /*reserved*/
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} pin;
union {
struct {
uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/
uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/
uint32_t rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/
uint32_t wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/
uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/
uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/
uint32_t reserved12: 5; /*reserved*/
uint32_t last_command: 3; /*In the slave mode it is the value of command.*/
uint32_t last_state: 3; /*In the slave mode it is the state of spi state machine.*/
uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/
uint32_t cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/
uint32_t wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/
uint32_t wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/
uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/
uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/
};
uint32_t val;
} slave;
union {
struct {
uint32_t rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/
uint32_t wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/
uint32_t rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/
uint32_t wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/
uint32_t wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/
uint32_t rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/
uint32_t reserved16: 9; /*reserved*/
uint32_t status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/
uint32_t status_fast_en: 1; /*In the slave mode enable fast read status.*/
uint32_t status_bitlen: 5; /*In the slave mode it is the length of status bit.*/
};
uint32_t val;
} slave1;
union {
struct {
uint32_t rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/
uint32_t wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/
uint32_t rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/
uint32_t wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/
};
uint32_t val;
} slave2;
union {
struct {
uint32_t rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/
uint32_t wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/
uint32_t rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/
uint32_t wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/
};
uint32_t val;
} slave3;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} slv_wrbuf_dlen;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} slv_rdbuf_dlen;
union {
struct {
uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/
uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/
uint32_t flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/
uint32_t reserved4: 28; /*reserved*/
};
uint32_t val;
} cache_fctrl;
union {
struct {
uint32_t reserved0: 1; /*reserved*/
uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/
uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/
uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/
uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/
uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/
uint32_t sram_bytes_len: 8; /*For SPI0 In the sram mode it is the byte length of spi read sram data.*/
uint32_t sram_dummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/
uint32_t reserved29: 3; /*reserved*/
};
uint32_t val;
} cache_sctrl;
union {
struct {
uint32_t dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
uint32_t qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/
uint32_t rst_io: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/
uint32_t reserved5:27; /*reserved*/
};
uint32_t val;
} sram_cmd;
union {
struct {
uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_drd_cmd;
union {
struct {
uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_dwr_cmd;
union {
struct {
uint32_t slv_rdata_bit:24; /*In the slave mode it is the bit length of read data. The value is the length - 1.*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} slv_rd_bit;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t data_buf[16]; /*data buffer*/
uint32_t tx_crc; /*For SPI1 the value of crc32 for 256 bits data.*/
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
union {
struct {
uint32_t t_pp_time: 12; /*page program delay time by system clock.*/
uint32_t reserved12: 4; /*reserved*/
uint32_t t_pp_shift: 4; /*page program delay time shift .*/
uint32_t reserved20:11; /*reserved*/
uint32_t t_pp_ena: 1; /*page program delay enable.*/
};
uint32_t val;
} ext0;
union {
struct {
uint32_t t_erase_time: 12; /*erase flash delay time by system clock.*/
uint32_t reserved12: 4; /*reserved*/
uint32_t t_erase_shift: 4; /*erase flash delay time shift.*/
uint32_t reserved20: 11; /*reserved*/
uint32_t t_erase_ena: 1; /*erase flash delay enable.*/
};
uint32_t val;
} ext1;
union {
struct {
uint32_t st: 3; /*The status of spi state machine .*/
uint32_t reserved3: 29; /*reserved*/
};
uint32_t val;
} ext2;
union {
struct {
uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/
uint32_t reserved2: 30; /*reserved*/
};
uint32_t val;
} ext3;
union {
struct {
uint32_t reserved0: 2; /*reserved*/
uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/
uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/
uint32_t ahbm_fifo_rst: 1; /*reset spi dma ahb master fifo pointer.*/
uint32_t ahbm_rst: 1; /*reset spi dma ahb master.*/
uint32_t in_loop_test: 1; /*Set bit to test in link.*/
uint32_t out_loop_test: 1; /*Set bit to test out link.*/
uint32_t out_auto_wrback: 1; /*when the link is empty jump to next automatically.*/
uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/
uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/
uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/
uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/
uint32_t reserved13: 1; /*reserved*/
uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/
uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/
uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/
uint32_t reserved17: 15; /*reserved*/
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t addr: 20; /*The address of the first outlink descriptor.*/
uint32_t reserved20: 8; /*reserved*/
uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/
uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} dma_out_link;
union {
struct {
uint32_t addr: 20; /*The address of the first inlink descriptor.*/
uint32_t auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/
uint32_t reserved21: 7; /*reserved*/
uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/
uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} dma_in_link;
union {
struct {
uint32_t rx_en: 1; /*spi dma read data status bit.*/
uint32_t tx_en: 1; /*spi dma write data status bit.*/
uint32_t reserved2: 30; /*spi dma read data from memory count.*/
};
uint32_t val;
} dma_status;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/
uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_ena;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_raw;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The status bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_st;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_clr;
uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/
uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/
uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/
uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/
uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/
uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/
uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/
uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/
uint32_t dma_rx_status; /*spi dma read data from memory status.*/
uint32_t dma_tx_status; /*spi dma write data to memory status.*/
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
union {
struct {
uint32_t date: 28; /*SPI register version.*/
uint32_t reserved28: 4; /*reserved*/
};
uint32_t val;
} date;
} spi_dev_t;
extern spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/
extern spi_dev_t SPI1;
extern spi_dev_t SPI2;
extern spi_dev_t SPI3;
#endif /* _SOC_SPI_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __TIMG_REG_H__
#define __TIMG_REG_H__
#include "soc.h"
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000)
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: When set timer 0 time-base counter is enabled*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (BIT(31))
#define TIMG_T0_EN_V 0x1
#define TIMG_T0_EN_S 31
/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: When set timer 0 time-base counter increment. When cleared timer
0 time-base counter decrement.*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (BIT(30))
#define TIMG_T0_INCREASE_V 0x1
#define TIMG_T0_INCREASE_S 30
/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: When set timer 0 auto-reload at alarming is enabled*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (BIT(29))
#define TIMG_T0_AUTORELOAD_V 0x1
#define TIMG_T0_AUTORELOAD_S 29
/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: Timer 0 clock (T0_clk) prescale value.*/
#define TIMG_T0_DIVIDER 0x0000FFFF
#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
#define TIMG_T0_DIVIDER_V 0xFFFF
#define TIMG_T0_DIVIDER_S 13
/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: When set edge type interrupt will be generated during alarm*/
#define TIMG_T0_EDGE_INT_EN (BIT(12))
#define TIMG_T0_EDGE_INT_EN_M (BIT(12))
#define TIMG_T0_EDGE_INT_EN_V 0x1
#define TIMG_T0_EDGE_INT_EN_S 12
/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
/*description: When set level type interrupt will be generated during alarm*/
#define TIMG_T0_LEVEL_INT_EN (BIT(11))
#define TIMG_T0_LEVEL_INT_EN_M (BIT(11))
#define TIMG_T0_LEVEL_INT_EN_V 0x1
#define TIMG_T0_LEVEL_INT_EN_S 11
/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: When set alarm is enabled*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (BIT(10))
#define TIMG_T0_ALARM_EN_V 0x1
#define TIMG_T0_ALARM_EN_S 10
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004)
/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Register to store timer 0 time-base counter current value lower 32 bits.*/
#define TIMG_T0_LO 0xFFFFFFFF
#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
#define TIMG_T0_LO_V 0xFFFFFFFF
#define TIMG_T0_LO_S 0
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Register to store timer 0 time-base counter current value higher 32 bits.*/
#define TIMG_T0_HI 0xFFFFFFFF
#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
#define TIMG_T0_HI_V 0xFFFFFFFF
#define TIMG_T0_HI_S 0
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c)
/* TIMG_T0_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Write any value will trigger a timer 0 time-base counter value
update (timer 0 current value will be stored in registers above)*/
#define TIMG_T0_UPDATE 0xFFFFFFFF
#define TIMG_T0_UPDATE_M ((TIMG_T0_UPDATE_V)<<(TIMG_T0_UPDATE_S))
#define TIMG_T0_UPDATE_V 0xFFFFFFFF
#define TIMG_T0_UPDATE_S 0
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010)
/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_S 0
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014)
/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
#define TIMG_T0_ALARM_HI 0xFFFFFFFF
#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
#define TIMG_T0_ALARM_HI_V 0xFFFFFFFF
#define TIMG_T0_ALARM_HI_S 0
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018)
/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Lower 32 bits of the value that will load into timer 0 time-base counter*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_S 0
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c)
/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: higher 32 bits of the value that will load into timer 0 time-base counter*/
#define TIMG_T0_LOAD_HI 0xFFFFFFFF
#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
#define TIMG_T0_LOAD_HI_V 0xFFFFFFFF
#define TIMG_T0_LOAD_HI_S 0
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020)
/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Write any value will trigger timer 0 time-base counter reload*/
#define TIMG_T0_LOAD 0xFFFFFFFF
#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
#define TIMG_T0_LOAD_V 0xFFFFFFFF
#define TIMG_T0_LOAD_S 0
#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024)
/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: When set timer 1 time-base counter is enabled*/
#define TIMG_T1_EN (BIT(31))
#define TIMG_T1_EN_M (BIT(31))
#define TIMG_T1_EN_V 0x1
#define TIMG_T1_EN_S 31
/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: When set timer 1 time-base counter increment. When cleared timer
1 time-base counter decrement.*/
#define TIMG_T1_INCREASE (BIT(30))
#define TIMG_T1_INCREASE_M (BIT(30))
#define TIMG_T1_INCREASE_V 0x1
#define TIMG_T1_INCREASE_S 30
/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: When set timer 1 auto-reload at alarming is enabled*/
#define TIMG_T1_AUTORELOAD (BIT(29))
#define TIMG_T1_AUTORELOAD_M (BIT(29))
#define TIMG_T1_AUTORELOAD_V 0x1
#define TIMG_T1_AUTORELOAD_S 29
/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: Timer 1 clock (T1_clk) prescale value.*/
#define TIMG_T1_DIVIDER 0x0000FFFF
#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S))
#define TIMG_T1_DIVIDER_V 0xFFFF
#define TIMG_T1_DIVIDER_S 13
/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: When set edge type interrupt will be generated during alarm*/
#define TIMG_T1_EDGE_INT_EN (BIT(12))
#define TIMG_T1_EDGE_INT_EN_M (BIT(12))
#define TIMG_T1_EDGE_INT_EN_V 0x1
#define TIMG_T1_EDGE_INT_EN_S 12
/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
/*description: When set level type interrupt will be generated during alarm*/
#define TIMG_T1_LEVEL_INT_EN (BIT(11))
#define TIMG_T1_LEVEL_INT_EN_M (BIT(11))
#define TIMG_T1_LEVEL_INT_EN_V 0x1
#define TIMG_T1_LEVEL_INT_EN_S 11
/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: When set alarm is enabled*/
#define TIMG_T1_ALARM_EN (BIT(10))
#define TIMG_T1_ALARM_EN_M (BIT(10))
#define TIMG_T1_ALARM_EN_V 0x1
#define TIMG_T1_ALARM_EN_S 10
#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028)
/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Register to store timer 1 time-base counter current value lower 32 bits.*/
#define TIMG_T1_LO 0xFFFFFFFF
#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S))
#define TIMG_T1_LO_V 0xFFFFFFFF
#define TIMG_T1_LO_S 0
#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c)
/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Register to store timer 1 time-base counter current value higher 32 bits.*/
#define TIMG_T1_HI 0xFFFFFFFF
#define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S))
#define TIMG_T1_HI_V 0xFFFFFFFF
#define TIMG_T1_HI_S 0
#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030)
/* TIMG_T1_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Write any value will trigger a timer 1 time-base counter value
update (timer 1 current value will be stored in registers above)*/
#define TIMG_T1_UPDATE 0xFFFFFFFF
#define TIMG_T1_UPDATE_M ((TIMG_T1_UPDATE_V)<<(TIMG_T1_UPDATE_S))
#define TIMG_T1_UPDATE_V 0xFFFFFFFF
#define TIMG_T1_UPDATE_S 0
#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034)
/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Timer 1 time-base counter value lower 32 bits that will trigger the alarm*/
#define TIMG_T1_ALARM_LO 0xFFFFFFFF
#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S))
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF
#define TIMG_T1_ALARM_LO_S 0
#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038)
/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Timer 1 time-base counter value higher 32 bits that will trigger the alarm*/
#define TIMG_T1_ALARM_HI 0xFFFFFFFF
#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S))
#define TIMG_T1_ALARM_HI_V 0xFFFFFFFF
#define TIMG_T1_ALARM_HI_S 0
#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c)
/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Lower 32 bits of the value that will load into timer 1 time-base counter*/
#define TIMG_T1_LOAD_LO 0xFFFFFFFF
#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S))
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF
#define TIMG_T1_LOAD_LO_S 0
#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040)
/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: higher 32 bits of the value that will load into timer 1 time-base counter*/
#define TIMG_T1_LOAD_HI 0xFFFFFFFF
#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S))
#define TIMG_T1_LOAD_HI_V 0xFFFFFFFF
#define TIMG_T1_LOAD_HI_S 0
#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044)
/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Write any value will trigger timer 1 time-base counter reload*/
#define TIMG_T1_LOAD 0xFFFFFFFF
#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S))
#define TIMG_T1_LOAD_V 0xFFFFFFFF
#define TIMG_T1_LOAD_S 0
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048)
/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: When set SWDT is enabled*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (BIT(31))
#define TIMG_WDT_EN_V 0x1
#define TIMG_WDT_EN_S 31
/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; */
/*description: Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
#define TIMG_WDT_STG0 0x00000003
#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
#define TIMG_WDT_STG0_V 0x3
#define TIMG_WDT_STG0_S 29
/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */
/*description: Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
#define TIMG_WDT_STG1 0x00000003
#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
#define TIMG_WDT_STG1_V 0x3
#define TIMG_WDT_STG1_S 27
/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; */
/*description: Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
#define TIMG_WDT_STG2 0x00000003
#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
#define TIMG_WDT_STG2_V 0x3
#define TIMG_WDT_STG2_S 25
/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; */
/*description: Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
#define TIMG_WDT_STG3 0x00000003
#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
#define TIMG_WDT_STG3_V 0x3
#define TIMG_WDT_STG3_S 23
/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
/*description: When set edge type interrupt generation is enabled*/
#define TIMG_WDT_EDGE_INT_EN (BIT(22))
#define TIMG_WDT_EDGE_INT_EN_M (BIT(22))
#define TIMG_WDT_EDGE_INT_EN_V 0x1
#define TIMG_WDT_EDGE_INT_EN_S 22
/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */
/*description: When set level type interrupt generation is enabled*/
#define TIMG_WDT_LEVEL_INT_EN (BIT(21))
#define TIMG_WDT_LEVEL_INT_EN_M (BIT(21))
#define TIMG_WDT_LEVEL_INT_EN_V 0x1
#define TIMG_WDT_LEVEL_INT_EN_S 21
/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
/*description: length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns
3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007
#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
/*description: length of system reset selection. 0: 100ns 1: 200ns 2: 300ns
3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007
#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
/*description: When set flash boot protection is enabled*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c)
/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
/*description: SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF
#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF
#define TIMG_WDT_CLK_PRESCALE_S 16
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050)
/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
/*description: Stage 0 timeout value in SWDT clock cycles*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_S 0
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054)
/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
/*description: Stage 1 timeout value in SWDT clock cycles*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_S 0
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058)
/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: Stage 2 timeout value in SWDT clock cycles*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_S 0
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c)
/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: Stage 3 timeout value in SWDT clock cycles*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_S 0
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060)
/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Write any value will feed SWDT*/
#define TIMG_WDT_FEED 0xFFFFFFFF
#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
#define TIMG_WDT_FEED_V 0xFFFFFFFF
#define TIMG_WDT_FEED_S 0
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064)
/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
/*description: If change its value from default then write protection is on.*/
#define TIMG_WDT_WKEY 0xFFFFFFFF
#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
#define TIMG_WDT_WKEY_V 0xFFFFFFFF
#define TIMG_WDT_WKEY_S 0
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (BIT(31))
#define TIMG_RTC_CALI_START_V 0x1
#define TIMG_RTC_CALI_START_S 31
/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
/*description: */
#define TIMG_RTC_CALI_MAX 0x00007FFF
#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
#define TIMG_RTC_CALI_MAX_V 0x7FFF
#define TIMG_RTC_CALI_MAX_S 16
/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (BIT(15))
#define TIMG_RTC_CALI_RDY_V 0x1
#define TIMG_RTC_CALI_RDY_S 15
/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
/*description: */
#define TIMG_RTC_CALI_CLK_SEL 0x00000003
#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
#define TIMG_RTC_CALI_CLK_SEL_V 0x3
#define TIMG_RTC_CALI_CLK_SEL_S 13
/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
/*description: */
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_V 0x1
#define TIMG_RTC_CALI_START_CYCLING_S 12
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c)
/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
/*description: */
#define TIMG_RTC_CALI_VALUE 0x01FFFFFF
#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF
#define TIMG_RTC_CALI_VALUE_S 7
#define TIMG_LACTCONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0070)
/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_EN (BIT(31))
#define TIMG_LACT_EN_M (BIT(31))
#define TIMG_LACT_EN_V 0x1
#define TIMG_LACT_EN_S 31
/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_INCREASE (BIT(30))
#define TIMG_LACT_INCREASE_M (BIT(30))
#define TIMG_LACT_INCREASE_V 0x1
#define TIMG_LACT_INCREASE_S 30
/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_AUTORELOAD (BIT(29))
#define TIMG_LACT_AUTORELOAD_M (BIT(29))
#define TIMG_LACT_AUTORELOAD_V 0x1
#define TIMG_LACT_AUTORELOAD_S 29
/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: */
#define TIMG_LACT_DIVIDER 0x0000FFFF
#define TIMG_LACT_DIVIDER_M ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S))
#define TIMG_LACT_DIVIDER_V 0xFFFF
#define TIMG_LACT_DIVIDER_S 13
/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_EDGE_INT_EN (BIT(12))
#define TIMG_LACT_EDGE_INT_EN_M (BIT(12))
#define TIMG_LACT_EDGE_INT_EN_V 0x1
#define TIMG_LACT_EDGE_INT_EN_S 12
/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_LEVEL_INT_EN (BIT(11))
#define TIMG_LACT_LEVEL_INT_EN_M (BIT(11))
#define TIMG_LACT_LEVEL_INT_EN_V 0x1
#define TIMG_LACT_LEVEL_INT_EN_S 11
/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_ALARM_EN (BIT(10))
#define TIMG_LACT_ALARM_EN_M (BIT(10))
#define TIMG_LACT_ALARM_EN_V 0x1
#define TIMG_LACT_ALARM_EN_S 10
/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_LAC_EN (BIT(9))
#define TIMG_LACT_LAC_EN_M (BIT(9))
#define TIMG_LACT_LAC_EN_V 0x1
#define TIMG_LACT_LAC_EN_S 9
/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_CPST_EN (BIT(8))
#define TIMG_LACT_CPST_EN_M (BIT(8))
#define TIMG_LACT_CPST_EN_V 0x1
#define TIMG_LACT_CPST_EN_S 8
/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_RTC_ONLY (BIT(7))
#define TIMG_LACT_RTC_ONLY_M (BIT(7))
#define TIMG_LACT_RTC_ONLY_V 0x1
#define TIMG_LACT_RTC_ONLY_S 7
#define TIMG_LACTRTC_REG(i) (REG_TIMG_BASE(i) + 0x0074)
/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; */
/*description: */
#define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF
#define TIMG_LACT_RTC_STEP_LEN_M ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S))
#define TIMG_LACT_RTC_STEP_LEN_V 0x3FFFFFF
#define TIMG_LACT_RTC_STEP_LEN_S 6
#define TIMG_LACTLO_REG(i) (REG_TIMG_BASE(i) + 0x0078)
/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LO 0xFFFFFFFF
#define TIMG_LACT_LO_M ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S))
#define TIMG_LACT_LO_V 0xFFFFFFFF
#define TIMG_LACT_LO_S 0
#define TIMG_LACTHI_REG(i) (REG_TIMG_BASE(i) + 0x007c)
/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_HI 0xFFFFFFFF
#define TIMG_LACT_HI_M ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S))
#define TIMG_LACT_HI_V 0xFFFFFFFF
#define TIMG_LACT_HI_S 0
#define TIMG_LACTUPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0080)
/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_UPDATE 0xFFFFFFFF
#define TIMG_LACT_UPDATE_M ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S))
#define TIMG_LACT_UPDATE_V 0xFFFFFFFF
#define TIMG_LACT_UPDATE_S 0
#define TIMG_LACTALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0084)
/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_ALARM_LO 0xFFFFFFFF
#define TIMG_LACT_ALARM_LO_M ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S))
#define TIMG_LACT_ALARM_LO_V 0xFFFFFFFF
#define TIMG_LACT_ALARM_LO_S 0
#define TIMG_LACTALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0088)
/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_ALARM_HI 0xFFFFFFFF
#define TIMG_LACT_ALARM_HI_M ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S))
#define TIMG_LACT_ALARM_HI_V 0xFFFFFFFF
#define TIMG_LACT_ALARM_HI_S 0
#define TIMG_LACTLOADLO_REG(i) (REG_TIMG_BASE(i) + 0x008c)
/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LOAD_LO 0xFFFFFFFF
#define TIMG_LACT_LOAD_LO_M ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S))
#define TIMG_LACT_LOAD_LO_V 0xFFFFFFFF
#define TIMG_LACT_LOAD_LO_S 0
#define TIMG_LACTLOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0090)
/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LOAD_HI 0xFFFFFFFF
#define TIMG_LACT_LOAD_HI_M ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S))
#define TIMG_LACT_LOAD_HI_V 0xFFFFFFFF
#define TIMG_LACT_LOAD_HI_S 0
#define TIMG_LACTLOAD_REG(i) (REG_TIMG_BASE(i) + 0x0094)
/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LOAD 0xFFFFFFFF
#define TIMG_LACT_LOAD_M ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S))
#define TIMG_LACT_LOAD_V 0xFFFFFFFF
#define TIMG_LACT_LOAD_S 0
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0098)
/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_ENA (BIT(3))
#define TIMG_LACT_INT_ENA_M (BIT(3))
#define TIMG_LACT_INT_ENA_V 0x1
#define TIMG_LACT_INT_ENA_S 3
/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Interrupt when an interrupt stage timeout*/
#define TIMG_WDT_INT_ENA (BIT(2))
#define TIMG_WDT_INT_ENA_M (BIT(2))
#define TIMG_WDT_INT_ENA_V 0x1
#define TIMG_WDT_INT_ENA_S 2
/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: interrupt when timer1 alarm*/
#define TIMG_T1_INT_ENA (BIT(1))
#define TIMG_T1_INT_ENA_M (BIT(1))
#define TIMG_T1_INT_ENA_V 0x1
#define TIMG_T1_INT_ENA_S 1
/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: interrupt when timer0 alarm*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (BIT(0))
#define TIMG_T0_INT_ENA_V 0x1
#define TIMG_T0_INT_ENA_S 0
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x009c)
/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_RAW (BIT(3))
#define TIMG_LACT_INT_RAW_M (BIT(3))
#define TIMG_LACT_INT_RAW_V 0x1
#define TIMG_LACT_INT_RAW_S 3
/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
/*description: Interrupt when an interrupt stage timeout*/
#define TIMG_WDT_INT_RAW (BIT(2))
#define TIMG_WDT_INT_RAW_M (BIT(2))
#define TIMG_WDT_INT_RAW_V 0x1
#define TIMG_WDT_INT_RAW_S 2
/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: interrupt when timer1 alarm*/
#define TIMG_T1_INT_RAW (BIT(1))
#define TIMG_T1_INT_RAW_M (BIT(1))
#define TIMG_T1_INT_RAW_V 0x1
#define TIMG_T1_INT_RAW_S 1
/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: interrupt when timer0 alarm*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (BIT(0))
#define TIMG_T0_INT_RAW_V 0x1
#define TIMG_T0_INT_RAW_S 0
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a0)
/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_ST (BIT(3))
#define TIMG_LACT_INT_ST_M (BIT(3))
#define TIMG_LACT_INT_ST_V 0x1
#define TIMG_LACT_INT_ST_S 3
/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
/*description: Interrupt when an interrupt stage timeout*/
#define TIMG_WDT_INT_ST (BIT(2))
#define TIMG_WDT_INT_ST_M (BIT(2))
#define TIMG_WDT_INT_ST_V 0x1
#define TIMG_WDT_INT_ST_S 2
/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: interrupt when timer1 alarm*/
#define TIMG_T1_INT_ST (BIT(1))
#define TIMG_T1_INT_ST_M (BIT(1))
#define TIMG_T1_INT_ST_V 0x1
#define TIMG_T1_INT_ST_S 1
/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: interrupt when timer0 alarm*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (BIT(0))
#define TIMG_T0_INT_ST_V 0x1
#define TIMG_T0_INT_ST_S 0
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a4)
/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_CLR (BIT(3))
#define TIMG_LACT_INT_CLR_M (BIT(3))
#define TIMG_LACT_INT_CLR_V 0x1
#define TIMG_LACT_INT_CLR_S 3
/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
/*description: Interrupt when an interrupt stage timeout*/
#define TIMG_WDT_INT_CLR (BIT(2))
#define TIMG_WDT_INT_CLR_M (BIT(2))
#define TIMG_WDT_INT_CLR_V 0x1
#define TIMG_WDT_INT_CLR_S 2
/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
/*description: interrupt when timer1 alarm*/
#define TIMG_T1_INT_CLR (BIT(1))
#define TIMG_T1_INT_CLR_M (BIT(1))
#define TIMG_T1_INT_CLR_V 0x1
#define TIMG_T1_INT_CLR_S 1
/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
/*description: interrupt when timer0 alarm*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (BIT(0))
#define TIMG_T0_INT_CLR_V 0x1
#define TIMG_T0_INT_CLR_S 0
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8)
/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604290 ; */
/*description: Version of this regfile*/
#define TIMG_NTIMERS_DATE 0x0FFFFFFF
#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
#define TIMG_NTIMERS_DATE_V 0xFFFFFFF
#define TIMG_NTIMERS_DATE_S 0
#define TIMGCLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc)
/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: Force clock enable for this regfile*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (BIT(31))
#define TIMG_CLK_EN_V 0x1
#define TIMG_CLK_EN_S 31
#endif /*__TIMG_REG_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMG_STRUCT_H_
#define _SOC_TIMG_STRUCT_H_
typedef volatile struct {
struct{
union {
struct {
uint32_t reserved0: 10;
uint32_t alarm_en: 1; /*When set alarm is enabled*/
uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/
uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/
uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/
uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/
uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/
uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/
};
uint32_t val;
} config;
uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/
uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/
uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/
} hw_timer[2];
union {
struct {
uint32_t reserved0: 14;
uint32_t flashboot_mod_en: 1; /*When set flash boot protection is enabled*/
uint32_t sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
uint32_t cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
uint32_t level_int_en: 1; /*When set level type interrupt generation is enabled*/
uint32_t edge_int_en: 1; /*When set edge type interrupt generation is enabled*/
uint32_t stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
uint32_t stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
uint32_t stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
uint32_t stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
uint32_t en: 1; /*When set SWDT is enabled*/
};
uint32_t val;
} wdt_config0;
union {
struct {
uint32_t reserved0: 16;
uint32_t clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
};
uint32_t val;
} wdt_config1;
uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/
uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/
uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/
uint32_t wdt_config5; /*Stage 3 timeout value in SWDT clock cycles*/
uint32_t wdt_feed; /*Write any value will feed SWDT*/
uint32_t wdt_wprotect; /*If change its value from default then write protection is on.*/
union {
struct {
uint32_t reserved0: 12;
uint32_t start_cycling: 1;
uint32_t clk_sel: 2;
uint32_t rdy: 1;
uint32_t max: 15;
uint32_t start: 1;
};
uint32_t val;
} rtc_cali_cfg;
union {
struct {
uint32_t reserved0: 7;
uint32_t value:25;
};
uint32_t val;
} rtc_cali_cfg1;
union {
struct {
uint32_t reserved0: 7;
uint32_t rtc_only: 1;
uint32_t cpst_en: 1;
uint32_t lac_en: 1;
uint32_t alarm_en: 1;
uint32_t level_int_en: 1;
uint32_t edge_int_en: 1;
uint32_t divider: 16;
uint32_t autoreload: 1;
uint32_t increase: 1;
uint32_t en: 1;
};
uint32_t val;
} lactconfig;
union {
struct {
uint32_t reserved0: 6;
uint32_t step_len:26;
};
uint32_t val;
} lactrtc;
uint32_t lactlo; /**/
uint32_t lacthi; /**/
uint32_t lactupdate; /**/
uint32_t lactalarmlo; /**/
uint32_t lactalarmhi; /**/
uint32_t lactloadlo; /**/
uint32_t lactloadhi; /**/
uint32_t lactload; /**/
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
uint32_t t1: 1; /*interrupt when timer1 alarm*/
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
uint32_t lact: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
uint32_t t1: 1; /*interrupt when timer1 alarm*/
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
uint32_t lact: 1;
uint32_t reserved4:28;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
uint32_t t1: 1; /*interrupt when timer1 alarm*/
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
uint32_t lact: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_st_timers;
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
uint32_t t1: 1; /*interrupt when timer1 alarm*/
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
uint32_t lact: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_clr_timers;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
union {
struct {
uint32_t date:28; /*Version of this regfile*/
uint32_t reserved28: 4;
};
uint32_t val;
} timg_date;
union {
struct {
uint32_t reserved0: 31;
uint32_t en: 1; /*Force clock enable for this regfile*/
};
uint32_t val;
} clk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
extern timg_dev_t TIMERG1;
#endif /* _SOC_TIMG_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_UART_STRUCT_H_
#define _SOC_UART_STRUCT_H_
typedef volatile struct {
union {
struct {
uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/
uint8_t reserved[3];
};
uint32_t val;
} fifo;
union {
struct {
uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/
uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/
uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/
uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/
uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/
uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/
uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/
uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/
uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/
uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/
uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/
uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/
uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/
uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/
uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/
uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/
uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/
uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/
uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/
uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/
uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/
uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/
uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/
uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/
uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/
uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/
uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/
uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/
uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/
uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/
uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/
uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/
uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/
uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/
uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/
uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/
uint32_t reserved24: 8;
};
uint32_t val;
} clk_div;
union {
struct {
uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/
uint32_t reserved1: 7;
uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/
uint32_t reserved16: 16;
};
uint32_t val;
} auto_baud;
union {
struct {
uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/
uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/
uint32_t reserved12: 1;
uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/
uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/
uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/
uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/
uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/
uint32_t reserved28: 1;
uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/
uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/
uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/
};
uint32_t val;
} status;
union {
struct {
uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/
uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/
uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/
uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/
uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/
uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/
uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/
uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/
uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/
uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/
uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/
uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/
uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/
uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/
uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/
uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/
uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/
uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/
uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/
uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/
uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/
uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/
uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/
uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/
uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/
uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/
uint32_t reserved28: 4;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rxfifo_full_thrhd: 7; /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/
uint32_t reserved7: 1;
uint32_t txfifo_empty_thrhd: 7; /*when the data amount in transmitter fifo is less than its threshold value， it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/
uint32_t reserved15: 1;
uint32_t rx_flow_thrhd: 7; /*when receiver receives more data than its threshold value， receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/
uint32_t rx_flow_en: 1; /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/
uint32_t rx_tout_thrhd: 7; /*This register is used to configure the timeout value for uart receiver receiving a byte.*/
uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} lowpulse;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} highpulse;
union {
struct {
uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/
uint32_t reserved10: 22;
};
uint32_t val;
} rxd_cnt;
union {
struct {
uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/
uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/
uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/
uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/
uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/
uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/
uint32_t reserved6: 26;
};
uint32_t val;
} flow_conf;
union {
struct {
uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/
uint32_t reserved10: 22;
};
uint32_t val;
} sleep_conf;
union {
struct {
uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/
uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/
uint32_t xon_char: 8; /*This register stores the xon flow control char.*/
uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/
};
uint32_t val;
} swfc_conf;
union {
struct {
uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/
uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/
uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/
uint32_t reserved28: 4;
};
uint32_t val;
} idle_conf;
union {
struct {
uint32_t en: 1; /*Set this bit to choose rs485 mode.*/
uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/
uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/
uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/
uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/
uint32_t reserved10: 22;
};
uint32_t val;
} rs485_conf;
union {
struct {
uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_precnt;
union {
struct {
uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_postcnt;
union {
struct {
uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_gaptout;
union {
struct {
uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/
uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/
uint32_t reserved16: 16;
};
uint32_t val;
} at_cmd_char;
union {
struct {
uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/
uint32_t reserved1: 1;
uint32_t reserved2: 1;
uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/
uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/
uint32_t reserved11: 4;
uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/
uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/
uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/
uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/
uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/
uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/
uint32_t reserved31: 1;
};
uint32_t val;
} mem_conf;
union {
struct {
uint32_t status:24;
uint32_t reserved24: 8;
};
uint32_t val;
} mem_tx_status;
union {
struct {
uint32_t status:24;
uint32_t reserved24: 8;
};
uint32_t val;
} mem_rx_status;
union {
struct {
uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/
uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/
uint32_t reserved6: 26;
};
uint32_t val;
} mem_cnt_status;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} pospulse;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} negpulse;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t date; /**/
uint32_t id; /**/
} uart_dev_t;
extern uart_dev_t UART0;
extern uart_dev_t UART1;
extern uart_dev_t UART2;
#endif /* _SOC_UART_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_UHCI_STRUCT_H_
#define _SOC_UHCI_STRUCT_H_
typedef volatile struct {
union {
struct {
uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/
uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/
uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/
uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/
uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/
uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/
uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next in link automatically.*/
uint32_t out_no_restart_clr: 1; /*don't use*/
uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/
uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive data.*/
uint32_t uart1_ce: 1; /*Set this bit to use UART1 to transmit or receive data.*/
uint32_t uart2_ce: 1; /*Set this bit to use UART2 to transmit or receive data.*/
uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/
uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/
uint32_t out_data_burst_en: 1; /*Set this bit to enable DMA burst MODE*/
uint32_t mem_trans_en: 1;
uint32_t seper_en: 1; /*Set this bit to use special char to separate the data frame.*/
uint32_t head_en: 1; /*Set this bit to enable to use head packet before the data frame.*/
uint32_t crc_rec_en: 1; /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/
uint32_t uart_idle_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/
uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/
uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/
uint32_t clk_en: 1; /*Set this bit to enable clock-gating for read or write registers.*/
uint32_t uart_rx_brk_eof_en: 1; /*Set this bit to enable to use brk char as the end of a data frame.*/
uint32_t reserved24: 8;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rx_start: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/
uint32_t tx_start: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/
uint32_t rx_hung: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/
uint32_t tx_hung: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/
uint32_t in_done: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/
uint32_t in_suc_eof: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/
uint32_t in_err_eof: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/
uint32_t out_done: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/
uint32_t out_eof: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/
uint32_t in_dscr_err: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/
uint32_t out_dscr_err: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/
uint32_t in_dscr_empty: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/
uint32_t outlink_eof_err: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/
uint32_t out_total_eof: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/
uint32_t send_s_q: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/
uint32_t send_a_q: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t outlink_eof_err: 1;
uint32_t out_total_eof: 1;
uint32_t send_s_q: 1;
uint32_t send_a_q: 1;
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t outlink_eof_err: 1;
uint32_t out_total_eof: 1;
uint32_t send_s_q: 1;
uint32_t send_a_q: 1;
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t outlink_eof_err: 1;
uint32_t out_total_eof: 1;
uint32_t send_s_q: 1;
uint32_t send_a_q: 1;
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t full: 1; /*1:DMA out link descriptor's fifo is full.*/
uint32_t empty: 1; /*1:DMA in link descriptor's fifo is empty.*/
uint32_t reserved2: 30;
};
uint32_t val;
} dma_out_status;
union {
struct {
uint32_t fifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/
uint32_t reserved9: 7;
uint32_t fifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/
uint32_t reserved17:15;
};
uint32_t val;
} dma_out_push;
union {
struct {
uint32_t full: 1;
uint32_t empty: 1;
uint32_t reserved2: 2;
uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/
uint32_t reserved7: 25;
};
uint32_t val;
} dma_in_status;
union {
struct {
uint32_t fifo_rdata: 12; /*This register stores the data pop from in link descriptor's fifo.*/
uint32_t reserved12: 4;
uint32_t fifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/
uint32_t reserved17: 15;
};
uint32_t val;
} dma_in_pop;
union {
struct {
uint32_t addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/
uint32_t reserved20: 8;
uint32_t stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/
uint32_t start: 1; /*Set this bit to start dealing with the out link descriptors.*/
uint32_t restart: 1; /*Set this bit to mount on new out link descriptors*/
uint32_t park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/
};
uint32_t val;
} dma_out_link;
union {
struct {
uint32_t addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/
uint32_t auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/
uint32_t reserved21: 7;
uint32_t stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/
uint32_t start: 1; /*Set this bit to start dealing with the in link descriptors.*/
uint32_t restart: 1; /*Set this bit to mount on new in link descriptors*/
uint32_t park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/
};
uint32_t val;
} dma_in_link;
union {
struct {
uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/
uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/
uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/
uint32_t save_head: 1; /*Set this bit to save packet header .*/
uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/
uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/
uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/
uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/
uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/
uint32_t dma_in_fifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_in_fifo_full_wm_int interrupt.*/
uint32_t reserved21: 11;
};
uint32_t val;
} conf1;
uint32_t state0; /**/
uint32_t state1; /**/
uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/
uint32_t dma_in_suc_eof_des_addr; /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/
uint32_t dma_in_err_eof_des_addr; /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/
uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/
union {
struct {
uint32_t test_mode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
uint32_t reserved3: 1;
uint32_t test_addr: 2; /*The two bits represent ahb bus address bit[20:19]*/
uint32_t reserved6: 26;
};
uint32_t val;
} ahb_test;
uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/
uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/
uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/
uint32_t dma_out_dscr; /*The content of current out link descriptor's third dword*/
uint32_t dma_out_dscr_bf0; /*The content of current out link descriptor's first dword*/
uint32_t dma_out_dscr_bf1; /*The content of current out link descriptor's second dword*/
union {
struct {
uint32_t tx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char decode when DMA receives data.*/
uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/
uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/
uint32_t tx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/
uint32_t rx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char replace when DMA sends data.*/
uint32_t rx_db_esc_en: 1; /*Set this bit to enable 0xdb char replace when DMA sends data.*/
uint32_t rx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 replace when DMA sends data.*/
uint32_t rx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 replace when DMA sends data.*/
uint32_t reserved8: 24;
};
uint32_t val;
} escape_conf;
union {
struct {
uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/
uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/
uint32_t txfifo_timeout_ena: 1; /*The enable bit for tx fifo receive data timeout*/
uint32_t rxfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/
uint32_t rxfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/
uint32_t rxfifo_timeout_ena: 1; /*This is the enable bit for DMA send data timeout*/
uint32_t reserved24: 8;
};
uint32_t val;
} hung_conf;
uint32_t ack_num; /**/
uint32_t rx_head; /*This register stores the packet header received by DMA*/
union {
struct {
uint32_t single_send_num: 3; /*The bits are used to choose which short packet*/
uint32_t single_send_en: 1; /*Set this bit to enable send a short packet*/
uint32_t always_send_num: 3; /*The bits are used to choose which short packet*/
uint32_t always_send_en: 1; /*Set this bit to enable continuously send the same short packet*/
uint32_t reserved8: 24;
};
uint32_t val;
} quick_sent;
struct{
uint32_t w_data[2]; /*This register stores the content of short packet's dword*/
} q_data[7];
union {
struct {
uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/
uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/
uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf0;
union {
struct {
uint32_t seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/
uint32_t seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/
uint32_t seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf1;
union {
struct {
uint32_t seq1: 8; /*This register stores the flow control char to turn on the flow_control*/
uint32_t seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/
uint32_t seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf2;
union {
struct {
uint32_t seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/
uint32_t seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/
uint32_t seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf3;
union {
struct {
uint32_t thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/
uint32_t reserved13:19;
};
uint32_t val;
} pkt_thres;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /*version information*/
} uhci_dev_t;
extern uhci_dev_t UHCI0;
extern uhci_dev_t UHCI1;
#endif /* _SOC_UHCI_STRUCT_H_ */

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tools/sdk/include/esp32/xtensa/board.h Executable file
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/* This header is supposed to be obtained from <board>/xtensa/board.h
using a -I directive passed to the compiler. */
#error "Unspecified board. Missing -I directive to select supported Xtensa board, usually -I XTENSA_TOOLS_ROOT/xtensa-elf/include/xtensa/<BOARD> (XTENSA_TOOLS_ROOT is root of Xtensa Tools install, see xt-run --show-config=xttools)"
/*
* Copyright (c) 2013 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/

1758
tools/sdk/include/esp32/xtensa/c6x-compat.h Executable file
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962
tools/sdk/include/esp32/xtensa/cacheasm.h Executable file
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/*
* xtensa/cacheasm.h -- assembler-specific cache related definitions
* that depend on CORE configuration
*
* This file is logically part of xtensa/coreasm.h ,
* but is kept separate for modularity / compilation-performance.
*/
/*
* Copyright (c) 2001-2014 Cadence Design Systems, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_CACHEASM_H
#define XTENSA_CACHEASM_H
#include <xtensa/coreasm.h>
#include <xtensa/corebits.h>
#include <xtensa/xtensa-xer.h>
#include <xtensa/xtensa-versions.h>
/*
* This header file defines assembler macros of the form:
* <x>cache_<func>
* where <x> is 'i' or 'd' for instruction and data caches,
* and <func> indicates the function of the macro.
*
* The following functions <func> are defined,
* and apply only to the specified cache (I or D):
*
* reset
* Resets the cache.
*
* sync
* Makes sure any previous cache instructions have been completed;
* ie. makes sure any previous cache control operations
* have had full effect and been synchronized to memory.
* Eg. any invalidate completed [so as not to generate a hit],
* any writebacks or other pipelined writes written to memory, etc.
*
* invalidate_line (single cache line)
* invalidate_region (specified memory range)
* invalidate_all (entire cache)
* Invalidates all cache entries that cache
* data from the specified memory range.
* NOTE: locked entries are not invalidated.
*
* writeback_line (single cache line)
* writeback_region (specified memory range)
* writeback_all (entire cache)
* Writes back to memory all dirty cache entries
* that cache data from the specified memory range,
* and marks these entries as clean.
* NOTE: on some future implementations, this might
* also invalidate.
* NOTE: locked entries are written back, but never invalidated.
* NOTE: instruction caches never implement writeback.
*
* writeback_inv_line (single cache line)
* writeback_inv_region (specified memory range)
* writeback_inv_all (entire cache)
* Writes back to memory all dirty cache entries
* that cache data from the specified memory range,
* and invalidates these entries (including all clean
* cache entries that cache data from that range).
* NOTE: locked entries are written back but not invalidated.
* NOTE: instruction caches never implement writeback.
*
* lock_line (single cache line)
* lock_region (specified memory range)
* Prefetch and lock the specified memory range into cache.
* NOTE: if any part of the specified memory range cannot
* be locked, a Load/Store Error (for dcache) or Instruction
* Fetch Error (for icache) exception occurs. These macros don't
* do anything special (yet anyway) to handle this situation.
*
* unlock_line (single cache line)
* unlock_region (specified memory range)
* unlock_all (entire cache)
* Unlock cache entries that cache the specified memory range.
* Entries not already locked are unaffected.
*
* coherence_on
* coherence_off
* Turn off and on cache coherence
*
*/
/*************************** GENERIC -- ALL CACHES ***************************/
/*
* The following macros assume the following cache size/parameter limits
* in the current Xtensa core implementation:
* cache size: 1024 bytes minimum
* line size: 16 - 64 bytes
* way count: 1 - 4
*
* Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
* Hence the assumption that each loop can execute four cache instructions.
*
* Correspondingly, the offset range of instructions is assumed able to cover
* four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
* both hit and indexed cache instructions. Ie. these offsets are all
* valid: 0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
* This is true of all original cache instructions
* (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
* of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
* This is also true of subsequent cache instructions
* (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
* of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
*
* (Maximum cache size, currently 32k, doesn't affect the following macros.
* Cache ways > MMU min page size cause aliasing but that's another matter.)
*/
/*
* Macro to apply an 'indexed' cache instruction to the entire cache.
*
* Parameters:
* cainst instruction/ that takes an address register parameter
* and an offset parameter (in range 0 .. 3*linesize).
* size size of cache in bytes
* linesize size of cache line in bytes (always power-of-2)
* assoc_or1 number of associativities (ways/sets) in cache
* if all sets affected by cainst,
* or 1 if only one set (or not all sets) of the cache
* is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
* aa, ab unique address registers (temporaries).
* awb set to other than a0 if wb type of instruction
* loopokay 1 allows use of zero-overhead loops, 0 does not
* immrange range (max value) of cainst's immediate offset parameter, in bytes
* (NOTE: macro assumes immrange allows power-of-2 number of lines)
*/
.macro cache_index_all cainst, size, linesize, assoc_or1, aa, ab, loopokay, maxofs, awb=a0
// Number of indices in cache (lines per way):
.set .Lindices, (\size / (\linesize * \assoc_or1))
// Number of indices processed per loop iteration (max 4):
.set .Lperloop, .Lindices
.ifgt .Lperloop - 4
.set .Lperloop, 4
.endif
// Also limit instructions per loop if cache line size exceeds immediate range:
.set .Lmaxperloop, (\maxofs / \linesize) + 1
.ifgt .Lperloop - .Lmaxperloop
.set .Lperloop, .Lmaxperloop
.endif
// Avoid addi of 128 which takes two instructions (addmi,addi):
.ifeq .Lperloop*\linesize - 128
.ifgt .Lperloop - 1
.set .Lperloop, .Lperloop / 2
.endif
.endif
// \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
// XCHAL_ERRATUM_497 - don't execute using loop, to reduce the amount of added code
.ifne (\loopokay & XCHAL_HAVE_LOOPS && !XCHAL_ERRATUM_497)
movi \aa, .Lindices / .Lperloop // number of loop iterations
// Possible improvement: need only loop if \aa > 1 ;
// however \aa == 1 is highly unlikely.
movi \ab, 0 // to iterate over cache
loop \aa, .Lend_cachex\@
.set .Li, 0 ; .rept .Lperloop
\cainst \ab, .Li*\linesize
.set .Li, .Li+1 ; .endr
addi \ab, \ab, .Lperloop*\linesize // move to next line
.Lend_cachex\@:
.else
movi \aa, (\size / \assoc_or1)
// Possible improvement: need only loop if \aa > 1 ;
// however \aa == 1 is highly unlikely.
movi \ab, 0 // to iterate over cache
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0
movi \awb, 0
.endif
.Lstart_cachex\@:
.set .Li, 0 ; .rept .Lperloop
\cainst \ab, .Li*\linesize
.set .Li, .Li+1 ; .endr
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions
addi \awb, \awb, .Lperloop
blti \awb, 8, .Lstart_memw\@
memw
movi \awb, 0
.Lstart_memw\@:
.endif
addi \ab, \ab, .Lperloop*\linesize // move to next line
bltu \ab, \aa, .Lstart_cachex\@
.endif
.endm
/*
* Macro to apply a 'hit' cache instruction to a memory region,
* ie. to any cache entries that cache a specified portion (region) of memory.
* Takes care of the unaligned cases, ie. may apply to one
* more cache line than $asize / lineSize if $aaddr is not aligned.
*
*
* Parameters are:
* cainst instruction/macro that takes an address register parameter
* and an offset parameter (currently always zero)
* and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
* linesize_log2 log2(size of cache line in bytes)
* addr register containing start address of region (clobbered)
* asize register containing size of the region in bytes (clobbered)
* askew unique register used as temporary
* awb unique register used as temporary for erratum 497.
*
* Note: A possible optimization to this macro is to apply the operation
* to the entire cache if the region exceeds the size of the cache
* by some empirically determined amount or factor. Some experimentation
* is required to determine the appropriate factors, which also need
* to be tunable if required.
*/
.macro cache_hit_region cainst, linesize_log2, addr, asize, askew, awb=a0
// Make \asize the number of iterations:
extui \askew, \addr, 0, \linesize_log2 // get unalignment amount of \addr
add \asize, \asize, \askew // ... and add it to \asize
addi \asize, \asize, (1 << \linesize_log2) - 1 // round up!
srli \asize, \asize, \linesize_log2
// Iterate over region:
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0
movi \awb, 0
.endif
floopnez \asize, cacheh\@
\cainst \addr, 0
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions
addi \awb, \awb, 1
blti \awb, 8, .Lstart_memw\@
memw
movi \awb, 0
.Lstart_memw\@:
.endif
addi \addr, \addr, (1 << \linesize_log2) // move to next line
floopend \asize, cacheh\@
.endm
/*************************** INSTRUCTION CACHE ***************************/
/*
* Reset/initialize the instruction cache by simply invalidating it:
* (need to unlock first also, if cache locking implemented):
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro icache_reset aa, ab, loopokay=0
icache_unlock_all \aa, \ab, \loopokay
icache_invalidate_all \aa, \ab, \loopokay
.endm
/*
* Synchronize after an instruction cache operation,
* to be sure everything is in sync with memory as to be
* expected following any previous instruction cache control operations.
*
* Even if a config doesn't have caches, an isync is still needed
* when instructions in any memory are modified, whether by a loader
* or self-modifying code. Therefore, this macro always produces
* an isync, whether or not an icache is present.
*
* Parameters are:
* ar an address register (temporary) (currently unused, but may be used in future)
*/
.macro icache_sync ar
isync
.endm
/*
* Invalidate a single line of the instruction cache.
* Parameters are:
* ar address register that contains (virtual) address to invalidate
* (may get clobbered in a future implementation, but not currently)
* offset (optional) offset to add to \ar to compute effective address to invalidate
* (note: some number of lsbits are ignored)
*/
.macro icache_invalidate_line ar, offset
#if XCHAL_ICACHE_SIZE > 0
ihi \ar, \offset // invalidate icache line
icache_sync \ar
#endif
.endm
/*
* Invalidate instruction cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro icache_invalidate_region astart, asize, ac
#if XCHAL_ICACHE_SIZE > 0
// Instruction cache region invalidation:
cache_hit_region ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
icache_sync \ac
// End of instruction cache region invalidation
#endif
.endm
/*
* Invalidate entire instruction cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro icache_invalidate_all aa, ab, loopokay=1
#if XCHAL_ICACHE_SIZE > 0
// Instruction cache invalidation:
cache_index_all iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loopokay, 1020
icache_sync \aa
// End of instruction cache invalidation
#endif
.endm
/*
* Lock (prefetch & lock) a single line of the instruction cache.
*
* Parameters are:
* ar address register that contains (virtual) address to lock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to lock
* (note: some number of lsbits are ignored)
*/
.macro icache_lock_line ar, offset
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
ipfl \ar, \offset /* prefetch and lock icache line */
icache_sync \ar
#endif
.endm
/*
* Lock (prefetch & lock) a specified portion of memory into the instruction cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro icache_lock_region astart, asize, ac
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
// Instruction cache region lock:
cache_hit_region ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
icache_sync \ac
// End of instruction cache region lock
#endif
.endm
/*
* Unlock a single line of the instruction cache.
*
* Parameters are:
* ar address register that contains (virtual) address to unlock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to unlock
* (note: some number of lsbits are ignored)
*/
.macro icache_unlock_line ar, offset
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
ihu \ar, \offset /* unlock icache line */
icache_sync \ar
#endif
.endm
/*
* Unlock a specified portion of memory from the instruction cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro icache_unlock_region astart, asize, ac
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
// Instruction cache region unlock:
cache_hit_region ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
icache_sync \ac
// End of instruction cache region unlock
#endif
.endm
/*
* Unlock entire instruction cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro icache_unlock_all aa, ab, loopokay=1
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
// Instruction cache unlock:
cache_index_all iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
icache_sync \aa
// End of instruction cache unlock
#endif
.endm
/*************************** DATA CACHE ***************************/
/*
* Reset/initialize the data cache by simply invalidating it
* (need to unlock first also, if cache locking implemented):
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_reset aa, ab, loopokay=0
dcache_unlock_all \aa, \ab, \loopokay
dcache_invalidate_all \aa, \ab, \loopokay
.endm
/*
* Synchronize after a data cache operation,
* to be sure everything is in sync with memory as to be
* expected following any previous data cache control operations.
*
* Parameters are:
* ar an address register (temporary) (currently unused, but may be used in future)
*/
.macro dcache_sync ar, wbtype=0
#if XCHAL_DCACHE_SIZE > 0
// No synchronization is needed.
// (memw may be desired e.g. after writeback operation to help ensure subsequent
// external accesses are seen to follow that writeback, however that's outside
// the scope of this macro)
//dsync
.ifne (\wbtype & XCHAL_ERRATUM_497)
memw
.endif
#endif
.endm
/*
* Turn on cache coherence.
*
* WARNING: for RE-201x.x and later hardware, any interrupt that tries
* to change MEMCTL will see its changes dropped if the interrupt comes
* in the middle of this routine. If this might be an issue, call this
* routine with interrupts disabled.
*
* Parameters are:
* ar,at two scratch address registers (both clobbered)
*/
.macro cache_coherence_on ar at
#if XCHAL_DCACHE_IS_COHERENT
# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
/* Have MEMCTL. Enable snoop responses. */
rsr.memctl \ar
movi \at, MEMCTL_SNOOP_EN
or \ar, \ar, \at
wsr.memctl \ar
# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
/* Opt into coherence for MX (for backward compatibility / testing). */
movi \ar, 1
movi \at, XER_CCON
wer \ar, \at
extw
# endif
#endif
.endm
/*
* Turn off cache coherence.
*
* NOTE: this is generally preceded by emptying the cache;
* see xthal_cache_coherence_optout() in hal/coherence.c for details.
*
* WARNING: for RE-201x.x and later hardware, any interrupt that tries
* to change MEMCTL will see its changes dropped if the interrupt comes
* in the middle of this routine. If this might be an issue, call this
* routine with interrupts disabled.
*
* Parameters are:
* ar,at two scratch address registers (both clobbered)
*/
.macro cache_coherence_off ar at
#if XCHAL_DCACHE_IS_COHERENT
# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
/* Have MEMCTL. Disable snoop responses. */
rsr.memctl \ar
movi \at, ~MEMCTL_SNOOP_EN
and \ar, \ar, \at
wsr.memctl \ar
# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
/* Opt out of coherence, for MX (for backward compatibility / testing). */
extw
movi \at, 0
movi \ar, XER_CCON
wer \at, \ar
extw
# endif
#endif
.endm
/*
* Synchronize after a data store operation,
* to be sure the stored data is completely off the processor
* (and assuming there is no buffering outside the processor,
* that the data is in memory). This may be required to
* ensure that the processor's write buffers are emptied.
* A MEMW followed by a read guarantees this, by definition.
* We also try to make sure the read itself completes.
*
* Parameters are:
* ar an address register (temporary)
*/
.macro write_sync ar
memw // ensure previous memory accesses are complete prior to subsequent memory accesses
l32i \ar, sp, 0 // completing this read ensures any previous write has completed, because of MEMW
//slot
add \ar, \ar, \ar // use the result of the read to help ensure the read completes (in future architectures)
.endm
/*
* Invalidate a single line of the data cache.
* Parameters are:
* ar address register that contains (virtual) address to invalidate
* (may get clobbered in a future implementation, but not currently)
* offset (optional) offset to add to \ar to compute effective address to invalidate
* (note: some number of lsbits are ignored)
*/
.macro dcache_invalidate_line ar, offset
#if XCHAL_DCACHE_SIZE > 0
dhi \ar, \offset
dcache_sync \ar
#endif
.endm
/*
* Invalidate data cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_invalidate_region astart, asize, ac
#if XCHAL_DCACHE_SIZE > 0
// Data cache region invalidation:
cache_hit_region dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
dcache_sync \ac
// End of data cache region invalidation
#endif
.endm
/*
* Invalidate entire data cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_invalidate_all aa, ab, loopokay=1
#if XCHAL_DCACHE_SIZE > 0
// Data cache invalidation:
cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loopokay, 1020
dcache_sync \aa
// End of data cache invalidation
#endif
.endm
/*
* Writeback a single line of the data cache.
* Parameters are:
* ar address register that contains (virtual) address to writeback
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to writeback
* (note: some number of lsbits are ignored)
*/
.macro dcache_writeback_line ar, offset
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
dhwb \ar, \offset
dcache_sync \ar, wbtype=1
#endif
.endm
/*
* Writeback dirty data cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_writeback_region astart, asize, ac, awb
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
// Data cache region writeback:
cache_hit_region dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
dcache_sync \ac, wbtype=1
// End of data cache region writeback
#endif
.endm
/*
* Writeback entire data cache.
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_writeback_all aa, ab, awb, loopokay=1
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
// Data cache writeback:
cache_index_all diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb,
dcache_sync \aa, wbtype=1
// End of data cache writeback
#endif
.endm
/*
* Writeback and invalidate a single line of the data cache.
* Parameters are:
* ar address register that contains (virtual) address to writeback and invalidate
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to writeback and invalidate
* (note: some number of lsbits are ignored)
*/
.macro dcache_writeback_inv_line ar, offset
#if XCHAL_DCACHE_SIZE > 0
dhwbi \ar, \offset /* writeback and invalidate dcache line */
dcache_sync \ar, wbtype=1
#endif
.endm
/*
* Writeback and invalidate data cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_writeback_inv_region astart, asize, ac, awb
#if XCHAL_DCACHE_SIZE > 0
// Data cache region writeback and invalidate:
cache_hit_region dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
dcache_sync \ac, wbtype=1
// End of data cache region writeback and invalidate
#endif
.endm
/*
* Writeback and invalidate entire data cache.
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_writeback_inv_all aa, ab, awb, loopokay=1
#if XCHAL_DCACHE_SIZE > 0
// Data cache writeback and invalidate:
#if XCHAL_DCACHE_IS_WRITEBACK
cache_index_all diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb
dcache_sync \aa, wbtype=1
#else /*writeback*/
// Data cache does not support writeback, so just invalidate: */
dcache_invalidate_all \aa, \ab, \loopokay
#endif /*writeback*/
// End of data cache writeback and invalidate
#endif
.endm
/*
* Lock (prefetch & lock) a single line of the data cache.
*
* Parameters are:
* ar address register that contains (virtual) address to lock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to lock
* (note: some number of lsbits are ignored)
*/
.macro dcache_lock_line ar, offset
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
dpfl \ar, \offset /* prefetch and lock dcache line */
dcache_sync \ar
#endif
.endm
/*
* Lock (prefetch & lock) a specified portion of memory into the data cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_lock_region astart, asize, ac
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
// Data cache region lock:
cache_hit_region dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
dcache_sync \ac
// End of data cache region lock
#endif
.endm
/*
* Unlock a single line of the data cache.
*
* Parameters are:
* ar address register that contains (virtual) address to unlock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to unlock
* (note: some number of lsbits are ignored)
*/
.macro dcache_unlock_line ar, offset
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
dhu \ar, \offset /* unlock dcache line */
dcache_sync \ar
#endif
.endm
/*
* Unlock a specified portion of memory from the data cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_unlock_region astart, asize, ac
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
// Data cache region unlock:
cache_hit_region dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
dcache_sync \ac
// End of data cache region unlock
#endif
.endm
/*
* Unlock entire data cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_unlock_all aa, ab, loopokay=1
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
// Data cache unlock:
cache_index_all diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
dcache_sync \aa
// End of data cache unlock
#endif
.endm
/*
* Get the number of enabled icache ways. Note that this may
* be different from the value read from the MEMCTL register.
*
* Parameters:
* aa address register where value is returned
*/
.macro icache_get_ways aa
#if XCHAL_ICACHE_SIZE > 0
#if XCHAL_HAVE_ICACHE_DYN_WAYS
// Read from MEMCTL and shift/mask
rsr \aa, MEMCTL
extui \aa, \aa, MEMCTL_ICWU_SHIFT, MEMCTL_ICWU_BITS
blti \aa, XCHAL_ICACHE_WAYS, .Licgw
movi \aa, XCHAL_ICACHE_WAYS
.Licgw:
#else
// All ways are always enabled
movi \aa, XCHAL_ICACHE_WAYS
#endif
#else
// No icache
movi \aa, 0
#endif
.endm
/*
* Set the number of enabled icache ways.
*
* Parameters:
* aa address register specifying number of ways (trashed)
* ab,ac address register for scratch use (trashed)
*/
.macro icache_set_ways aa, ab, ac
#if XCHAL_ICACHE_SIZE > 0
#if XCHAL_HAVE_ICACHE_DYN_WAYS
movi \ac, MEMCTL_ICWU_CLR_MASK // set up to clear bits 18-22
rsr \ab, MEMCTL
and \ab, \ab, \ac
movi \ac, MEMCTL_INV_EN // set bit 23
slli \aa, \aa, MEMCTL_ICWU_SHIFT // move to right spot
or \ab, \ab, \aa
or \ab, \ab, \ac
wsr \ab, MEMCTL
isync
#else
// All ways are always enabled
#endif
#else
// No icache
#endif
.endm
/*
* Get the number of enabled dcache ways. Note that this may
* be different from the value read from the MEMCTL register.
*
* Parameters:
* aa address register where value is returned
*/
.macro dcache_get_ways aa
#if XCHAL_DCACHE_SIZE > 0
#if XCHAL_HAVE_DCACHE_DYN_WAYS
// Read from MEMCTL and shift/mask
rsr \aa, MEMCTL
extui \aa, \aa, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS
blti \aa, XCHAL_DCACHE_WAYS, .Ldcgw
movi \aa, XCHAL_DCACHE_WAYS
.Ldcgw:
#else
// All ways are always enabled
movi \aa, XCHAL_DCACHE_WAYS
#endif
#else
// No dcache
movi \aa, 0
#endif
.endm
/*
* Set the number of enabled dcache ways.
*
* Parameters:
* aa address register specifying number of ways (trashed)
* ab,ac address register for scratch use (trashed)
*/
.macro dcache_set_ways aa, ab, ac
#if (XCHAL_DCACHE_SIZE > 0) && XCHAL_HAVE_DCACHE_DYN_WAYS
movi \ac, MEMCTL_DCWA_CLR_MASK // set up to clear bits 13-17
rsr \ab, MEMCTL
and \ab, \ab, \ac // clear ways allocatable
slli \ac, \aa, MEMCTL_DCWA_SHIFT
or \ab, \ab, \ac // set ways allocatable
wsr \ab, MEMCTL
#if XCHAL_DCACHE_IS_WRITEBACK
// Check if the way count is increasing or decreasing
extui \ac, \ab, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS // bits 8-12 - ways in use
bge \aa, \ac, .Ldsw3 // equal or increasing
slli \ab, \aa, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // start way number
slli \ac, \ac, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // end way number
.Ldsw1:
diwbui.p \ab // auto-increments ab
bge \ab, \ac, .Ldsw2
beqz \ab, .Ldsw2
j .Ldsw1
.Ldsw2:
rsr \ab, MEMCTL
#endif
.Ldsw3:
// No dirty data to write back, just set the new number of ways
movi \ac, MEMCTL_DCWU_CLR_MASK // set up to clear bits 8-12
and \ab, \ab, \ac // clear ways in use
movi \ac, MEMCTL_INV_EN
or \ab, \ab, \ac // set bit 23
slli \aa, \aa, MEMCTL_DCWU_SHIFT
or \ab, \ab, \aa // set ways in use
wsr \ab, MEMCTL
#else
// No dcache or no way disable support
#endif
.endm
#endif /*XTENSA_CACHEASM_H*/

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tools/sdk/include/esp32/xtensa/cacheattrasm.h Executable file
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/*
* xtensa/cacheattrasm.h -- assembler-specific CACHEATTR register related definitions
* that depend on CORE configuration
*
* This file is logically part of xtensa/coreasm.h (or perhaps xtensa/cacheasm.h),
* but is kept separate for modularity / compilation-performance.
*/
/*
* Copyright (c) 2001-2009 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_CACHEATTRASM_H
#define XTENSA_CACHEATTRASM_H
#include <xtensa/coreasm.h>
/* Determine whether cache attributes are controlled using eight 512MB entries: */
#define XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY))
/*
* This header file defines assembler macros of the form:
* <x>cacheattr_<func>
* where:
* <x> is 'i', 'd' or absent for instruction, data
* or both caches; and
* <func> indicates the function of the macro.
*
* The following functions are defined:
*
* icacheattr_get
* Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
*
* dcacheattr_get
* Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
* (Note: for configs with a real CACHEATTR register, the
* above two macros are identical.)
*
* cacheattr_set
* Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
* Works even when changing one's own code's attributes.
*
* icacheattr_is_enabled label
* Branches to \label if I-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* dcacheattr_is_enabled label
* Branches to \label if D-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* cacheattr_is_enabled label
* Branches to \label if either I-cache or D-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* The following macros are only defined under certain conditions:
*
* icacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
* Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
*
* dcacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
* Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
*/
/*************************** GENERIC -- ALL CACHES ***************************/
/*
* _cacheattr_get
*
* (Internal macro.)
* Returns value of CACHEATTR register (or closest equivalent) in a2.
*
* Entry:
* (none)
* Exit:
* a2 value read from CACHEATTR
* a3-a5 clobbered (temporaries)
*/
.macro _cacheattr_get tlb
#if XCHAL_HAVE_CACHEATTR
rsr a2, CACHEATTR
#elif XCHAL_CA_8X512
// We have a config that "mimics" CACHEATTR using a simplified
// "MMU" composed of a single statically-mapped way.
// DTLB and ITLB are independent, so there's no single
// cache attribute that can describe both. So for now
// just return the DTLB state.
movi a5, 0xE0000000
movi a2, 0
movi a3, XCHAL_SPANNING_WAY
1: add a3, a3, a5 // next segment
r&tlb&1 a4, a3 // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
dsync // interlock???
slli a2, a2, 4
extui a4, a4, 0, 4 // extract CA
or a2, a2, a4
bgeui a3, 16, 1b
#else
// This macro isn't applicable to arbitrary MMU configurations.
// Just return zero.
movi a2, 0
#endif
.endm
.macro icacheattr_get
_cacheattr_get itlb
.endm
.macro dcacheattr_get
_cacheattr_get dtlb
.endm
/* Default (powerup/reset) value of CACHEATTR,
all BYPASS mode (ie. disabled/bypassed caches): */
#if XCHAL_HAVE_PTP_MMU
# define XCHAL_CACHEATTR_ALL_BYPASS 0x33333333
#else
# define XCHAL_CACHEATTR_ALL_BYPASS 0x22222222
#endif
#if XCHAL_CA_8X512
#if XCHAL_HAVE_PTP_MMU
# define XCHAL_FCA_ENAMASK 0x0AA0 /* bitmap of fetch attributes that require enabled icache */
# define XCHAL_LCA_ENAMASK 0x0FF0 /* bitmap of load attributes that require enabled dcache */
# define XCHAL_SCA_ENAMASK 0x0CC0 /* bitmap of store attributes that require enabled dcache */
#else
# define XCHAL_FCA_ENAMASK 0x003A /* bitmap of fetch attributes that require enabled icache */
# define XCHAL_LCA_ENAMASK 0x0033 /* bitmap of load attributes that require enabled dcache */
# define XCHAL_SCA_ENAMASK 0x0033 /* bitmap of store attributes that require enabled dcache */
#endif
#define XCHAL_LSCA_ENAMASK (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK) /* l/s attrs requiring enabled dcache */
#define XCHAL_ALLCA_ENAMASK (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK) /* all attrs requiring enabled caches */
/*
* _cacheattr_is_enabled
*
* (Internal macro.)
* Branches to \label if CACHEATTR in a2 indicates an enabled
* cache, using mask in a3.
*
* Parameters:
* label where to branch to if cache is enabled
* Entry:
* a2 contains CACHEATTR value used to determine whether
* caches are enabled
* a3 16-bit constant where each bit correspond to
* one of the 16 possible CA values (in a CACHEATTR mask);
* CA values that indicate the cache is enabled
* have their corresponding bit set in this mask
* (eg. use XCHAL_xCA_ENAMASK , above)
* Exit:
* a2,a4,a5 clobbered
* SAR clobbered
*/
.macro _cacheattr_is_enabled label
movi a4, 8 // loop 8 times
.Lcaife\@:
extui a5, a2, 0, 4 // get CA nibble
ssr a5 // index into mask according to CA...
srl a5, a3 // ...and get CA's mask bit in a5 bit 0
bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label
srli a2, a2, 4 // next nibble
addi a4, a4, -1
bnez a4, .Lcaife\@ // loop for each nibble
.endm
#else /* XCHAL_CA_8X512 */
.macro _cacheattr_is_enabled label
j \label // macro not applicable, assume caches always enabled
.endm
#endif /* XCHAL_CA_8X512 */
/*
* icacheattr_is_enabled
*
* Branches to \label if I-cache is enabled.
*
* Parameters:
* label where to branch to if icache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro icacheattr_is_enabled label
#if XCHAL_CA_8X512
icacheattr_get
movi a3, XCHAL_FCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* dcacheattr_is_enabled
*
* Branches to \label if D-cache is enabled.
*
* Parameters:
* label where to branch to if dcache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro dcacheattr_is_enabled label
#if XCHAL_CA_8X512
dcacheattr_get
movi a3, XCHAL_LSCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* cacheattr_is_enabled
*
* Branches to \label if either I-cache or D-cache is enabled.
*
* Parameters:
* label where to branch to if a cache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro cacheattr_is_enabled label
#if XCHAL_HAVE_CACHEATTR
rsr a2, CACHEATTR
movi a3, XCHAL_ALLCA_ENAMASK
#elif XCHAL_CA_8X512
icacheattr_get
movi a3, XCHAL_FCA_ENAMASK
_cacheattr_is_enabled \label
dcacheattr_get
movi a3, XCHAL_LSCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* The ISA does not have a defined way to change the
* instruction cache attributes of the running code,
* ie. of the memory area that encloses the current PC.
* However, each micro-architecture (or class of
* configurations within a micro-architecture)
* provides a way to deal with this issue.
*
* Here are a few macros used to implement the relevant
* approach taken.
*/
#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR
// We have a config that "mimics" CACHEATTR using a simplified
// "MMU" composed of a single statically-mapped way.
/*
* icacheattr_set
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro icacheattr_set
movi a5, 0xE0000000 // mask of upper 3 bits
movi a6, 3f // PC where ITLB is set
movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
mov a7, a2 // copy a2 so it doesn't get clobbered
and a6, a6, a5 // upper 3 bits of local PC area
j 3f
// Use micro-architecture specific method.
// The following 4-instruction sequence is aligned such that
// it all fits within a single I-cache line. Sixteen byte
// alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
// actually causes problems because that can be greater than
// the alignment of the reset vector, where this macro is often
// invoked, which would cause the linker to align the reset
// vector code away from the reset vector!!).
.begin no-transform
.align 16 /*XCHAL_ICACHE_LINESIZE*/
1: witlb a4, a3 // write wired PTE (CA, no PPN) of 512MB segment to ITLB
isync
.end no-transform
nop
nop
sub a3, a3, a5 // next segment (add 0x20000000)
bltui a3, 16, 4f // done?
// Note that in the WITLB loop, we don't do any load/stores
// (may not be an issue here, but it is important in the DTLB case).
2: srli a7, a7, 4 // next CA
3:
# if XCHAL_HAVE_MIMIC_CACHEATTR
extui a4, a7, 0, 4 // extract CA to set
# else /* have translation, preserve it: */
ritlb1 a8, a3 // get current PPN+CA of segment
//dsync // interlock???
extui a4, a7, 0, 4 // extract CA to set
srli a8, a8, 4 // clear CA but keep PPN ...
slli a8, a8, 4 // ...
add a4, a4, a8 // combine new CA with PPN to preserve
# endif
beq a3, a6, 1b // current PC's region? if so, do it in a safe way
witlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to ITLB
sub a3, a3, a5 // next segment (add 0x20000000)
bgeui a3, 16, 2b
isync // make sure all ifetch changes take effect
4:
.endm // icacheattr_set
/*
* dcacheattr_set
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro dcacheattr_set
movi a5, 0xE0000000 // mask of upper 3 bits
movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
mov a7, a2 // copy a2 so it doesn't get clobbered
// Note that in the WDTLB loop, we don't do any load/stores
2: // (including implicit l32r via movi) because it isn't safe.
# if XCHAL_HAVE_MIMIC_CACHEATTR
extui a4, a7, 0, 4 // extract CA to set
# else /* have translation, preserve it: */
rdtlb1 a8, a3 // get current PPN+CA of segment
//dsync // interlock???
extui a4, a7, 0, 4 // extract CA to set
srli a8, a8, 4 // clear CA but keep PPN ...
slli a8, a8, 4 // ...
add a4, a4, a8 // combine new CA with PPN to preserve
# endif
wdtlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to DTLB
sub a3, a3, a5 // next segment (add 0x20000000)
srli a7, a7, 4 // next CA
bgeui a3, 16, 2b
dsync // make sure all data path changes take effect
.endm // dcacheattr_set
#endif /* XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR */
/*
* cacheattr_set
*
* Macro that sets the current CACHEATTR safely
* (both i and d) according to the current contents of a2.
* It works even when changing the cache attributes of
* the currently running code.
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro cacheattr_set
#if XCHAL_HAVE_CACHEATTR
# if XCHAL_ICACHE_LINESIZE < 4
// No i-cache, so can always safely write to CACHEATTR:
wsr a2, CACHEATTR
# else
// The Athens micro-architecture, when using the old
// exception architecture option (ie. with the CACHEATTR register)
// allows changing the cache attributes of the running code
// using the following exact sequence aligned to be within
// an instruction cache line. (NOTE: using XCHAL_ICACHE_LINESIZE
// alignment actually causes problems because that can be greater
// than the alignment of the reset vector, where this macro is often
// invoked, which would cause the linker to align the reset
// vector code away from the reset vector!!).
j 1f
.begin no-transform
.align 16 /*XCHAL_ICACHE_LINESIZE*/ // align to within an I-cache line
1: wsr a2, CACHEATTR
isync
.end no-transform
nop
nop
# endif
#elif XCHAL_CA_8X512
// DTLB and ITLB are independent, but to keep semantics
// of this macro we simply write to both.
icacheattr_set
dcacheattr_set
#else
// This macro isn't applicable to arbitrary MMU configurations.
// Do nothing in this case.
#endif
.endm
#endif /*XTENSA_CACHEATTRASM_H*/

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/*
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
* processor CORE configuration
*
* See <xtensa/config/core.h>, which includes this file, for more details.
*/
/* Xtensa processor core configuration information.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
/*
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
* configured, and a value of 0 otherwise. These macros are always defined.
*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS 1 /* */
#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID 1 /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
#define XCHAL_HAVE_HIFI_MINI 0
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_FP 1 /* single prec floating point */
#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay
(1 = 5-stage, 2 = 7-stage) */
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
/* In T1050, applies to selected core load and store instructions (see ISA): */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
#define XCHAL_SW_VERSION 1100003 /* sw version of this header */
#define XCHAL_CORE_ID "esp32_v3_49_prod" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x0005FE96 /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
#define XCHAL_HW_CONFIGID0 0xC2BCFFFE /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x1CC5FE96 /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 260003 /* major*100+minor */
#define XCHAL_HW_REL_LX6 1
#define XCHAL_HW_REL_LX6_0 1
#define XCHAL_HW_REL_LX6_0_3 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a *range* of hardware versions, these are the bounds: */
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */
#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
#define XCHAL_HAVE_AXI 0 /* AXI bus */
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 0
#define XCHAL_DCACHE_SETWIDTH 0
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 1
#define XCHAL_DCACHE_WAYS 1
/* Cache features: */
#define XCHAL_ICACHE_LINE_LOCKABLE 0
#define XCHAL_DCACHE_LINE_LOCKABLE 0
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_BANKS 0 /* number of banks */
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */
#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
/* Instruction ROM 0: */
#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */
#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */
#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Instruction RAM 1: */
#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */
#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */
#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Data ROM 0: */
#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */
#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */
#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */
#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATAROM0_BANKS 1 /* number of banks */
/* Data RAM 0: */
#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */
#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */
#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
/* Data RAM 1: */
#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */
#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */
#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */
#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM1_BANKS 1 /* number of banks */
/* XLMI Port 0: */
#define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */
#define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */
#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */
#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
(not including level zero) */
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x000637FF
#define XCHAL_INTLEVEL2_MASK 0x00380000
#define XCHAL_INTLEVEL3_MASK 0x28C08800
#define XCHAL_INTLEVEL4_MASK 0x53000000
#define XCHAL_INTLEVEL5_MASK 0x84010000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00004000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 1
#define XCHAL_INT2_LEVEL 1
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 1
#define XCHAL_INT5_LEVEL 1
#define XCHAL_INT6_LEVEL 1
#define XCHAL_INT7_LEVEL 1
#define XCHAL_INT8_LEVEL 1
#define XCHAL_INT9_LEVEL 1
#define XCHAL_INT10_LEVEL 1
#define XCHAL_INT11_LEVEL 3
#define XCHAL_INT12_LEVEL 1
#define XCHAL_INT13_LEVEL 1
#define XCHAL_INT14_LEVEL 7
#define XCHAL_INT15_LEVEL 3
#define XCHAL_INT16_LEVEL 5
#define XCHAL_INT17_LEVEL 1
#define XCHAL_INT18_LEVEL 1
#define XCHAL_INT19_LEVEL 2
#define XCHAL_INT20_LEVEL 2
#define XCHAL_INT21_LEVEL 2
#define XCHAL_INT22_LEVEL 3
#define XCHAL_INT23_LEVEL 3
#define XCHAL_INT24_LEVEL 4
#define XCHAL_INT25_LEVEL 4
#define XCHAL_INT26_LEVEL 5
#define XCHAL_INT27_LEVEL 3
#define XCHAL_INT28_LEVEL 4
#define XCHAL_INT29_LEVEL 3
#define XCHAL_INT30_LEVEL 4
#define XCHAL_INT31_LEVEL 5
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F
#define XCHAL_INTTYPE_MASK_TIMER 0x00018040
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800
/* Interrupt numbers assigned to specific interrupt sources: */
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
#define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */
/* Interrupt numbers for levels at which only one interrupt is configured: */
#define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
/*
* External interrupt mapping.
* These macros describe how Xtensa processor interrupt numbers
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
* map to external BInterrupt<n> pins, for those interrupts
* configured as external (level-triggered, edge-triggered, or NMI).
* See the Xtensa processor databook for more details.
*/
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */
#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */
#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */
#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */
#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */
#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */
#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */
#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */
#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */
#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */
#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */
#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */
#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */
#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */
#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */
#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */
#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */
#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */
#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */
#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */
#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */
#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */
#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */
#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */
#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
number: 1 == XEA1 (old)
2 == XEA2 (new)
0 == XEAX (extern) or TX */
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
#define XCHAL_RESET_VECBASE_OVERLAP 0
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
#define XCHAL_RESET_VECTOR_VADDR 0x40000400
#define XCHAL_RESET_VECTOR_PADDR 0x40000400
#define XCHAL_USER_VECOFS 0x00000340
#define XCHAL_USER_VECTOR_VADDR 0x40000340
#define XCHAL_USER_VECTOR_PADDR 0x40000340
#define XCHAL_KERNEL_VECOFS 0x00000300
#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
#define XCHAL_NMI_VECOFS 0x000002C0
#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/*----------------------------------------------------------------------
DEBUG MODULE
----------------------------------------------------------------------*/
/* Misc */
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
/* On-Chip Debug (OCD) */
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
/* TRAX (in core) */
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
/* Perf counters */
#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
[autorefill] and protection)
usable for an MMU-based OS */
/* If none of the above last 4 are set, it's a custom TLB configuration. */
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */

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/*
* xtensa/config/core-matmap.h -- Memory access and translation mapping
* parameters (CHAL) of the Xtensa processor core configuration.
*
* If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
* this file) for more details.
*
* In the Xtensa processor products released to date, all parameters
* defined in this file are derivable (at least in theory) from
* information contained in the core-isa.h header file.
* In particular, the following core configuration parameters are relevant:
* XCHAL_HAVE_CACHEATTR
* XCHAL_HAVE_MIMIC_CACHEATTR
* XCHAL_HAVE_XLT_CACHEATTR
* XCHAL_HAVE_PTP_MMU
* XCHAL_ITLB_ARF_ENTRIES_LOG2
* XCHAL_DTLB_ARF_ENTRIES_LOG2
* XCHAL_DCACHE_IS_WRITEBACK
* XCHAL_ICACHE_SIZE (presence of I-cache)
* XCHAL_DCACHE_SIZE (presence of D-cache)
* XCHAL_HW_VERSION_MAJOR
* XCHAL_HW_VERSION_MINOR
*/
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_CONFIG_CORE_MATMAP_H
#define XTENSA_CONFIG_CORE_MATMAP_H
/*----------------------------------------------------------------------
CACHE (MEMORY ACCESS) ATTRIBUTES
----------------------------------------------------------------------*/
/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION
#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION
#define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION
/*
* Specific encoded cache attribute values of general interest.
* If a specific cache mode is not available, the closest available
* one is returned instead (eg. writethru instead of writeback,
* bypass instead of writethru).
*/
#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */
#define XCHAL_CA_WRITETHRU 2 /* cache enabled (write-through) mode */
#define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */
#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */
#define XCHAL_CA_WRITEBACK_NOALLOC 2 /* cache enabled (write-back no-allocate) mode */
#define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */
#define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) */
#define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */
#define XCHAL_CA_WRITEBACK_NOALLOC_RW 0 /* cache enabled (write-back no-allocate) mode (no exec) */
#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
#define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/*
* General notes on MMU parameters.
*
* Terminology:
* ASID = address-space ID (acts as an "extension" of virtual addresses)
* VPN = virtual page number
* PPN = physical page number
* CA = encoded cache attribute (access modes)
* TLB = translation look-aside buffer (term is stretched somewhat here)
* I = instruction (fetch accesses)
* D = data (load and store accesses)
* way = each TLB (ITLB and DTLB) consists of a number of "ways"
* that simultaneously match the virtual address of an access;
* a TLB successfully translates a virtual address if exactly
* one way matches the vaddr; if none match, it is a miss;
* if multiple match, one gets a "multihit" exception;
* each way can be independently configured in terms of number of
* entries, page sizes, which fields are writable or constant, etc.
* set = group of contiguous ways with exactly identical parameters
* ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
* from the page table and storing it in one of the auto-refill ways;
* if this PTE load also misses, a miss exception is posted for s/w.
* min-wired = a "min-wired" way can be used to map a single (minimum-sized)
* page arbitrarily under program control; it has a single entry,
* is non-auto-refill (some other way(s) must be auto-refill),
* all its fields (VPN, PPN, ASID, CA) are all writable, and it
* supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
* restriction is that this be the only page size it supports).
*
* TLB way entries are virtually indexed.
* TLB ways that support multiple page sizes:
* - must have all writable VPN and PPN fields;
* - can only use one page size at any given time (eg. setup at startup),
* selected by the respective ITLBCFG or DTLBCFG special register,
* whose bits n*4+3 .. n*4 index the list of page sizes for way n
* (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
* this list may be sparse for auto-refill ways because auto-refill
* ways have independent lists of supported page sizes sharing a
* common encoding with PTE entries; the encoding is the index into
* this list; unsupported sizes for a given way are zero in the list;
* selecting unsupported sizes results in undefined hardware behaviour;
* - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
*/
#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
/*** Instruction TLB: ***/
#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
/* Way set to which each way belongs: */
#define XCHAL_ITLB_WAY0_SET 0
/* Ways sets that are used by hardware auto-refill (ARF): */
#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
/* Way sets that are "min-wired" (see terminology comment above): */
#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
/* ITLB way set 0 (group of ways 0 thru 0): */
#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
/*** Data TLB: ***/
#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
/* Way set to which each way belongs: */
#define XCHAL_DTLB_WAY0_SET 0
/* Ways sets that are used by hardware auto-refill (ARF): */
#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
/* Way sets that are "min-wired" (see terminology comment above): */
#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
/* DTLB way set 0 (group of ways 0 thru 0): */
#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/

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/* Definitions for Xtensa instructions, types, and protos. */
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2003-2004 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
/* NOTE: This file exists only for backward compatibility with T1050
and earlier Xtensa releases. It includes only a subset of the
available header files. */
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
#include <xtensa/tie/xt_core.h>
#include <xtensa/tie/xt_misc.h>
#include <xtensa/tie/xt_booleans.h>
#endif /* __XTENSA__ */
#endif /* !_XTENSA_BASE_HEADER */

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/*
* Xtensa Special Register symbolic names
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1998-2002 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Include these special register bitfield definitions, for historical reasons: */
#include <xtensa/corebits.h>
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define SCOMPARE1 12
#define ACCLO 16
#define ACCHI 17
#define MR_0 32
#define MR_1 33
#define MR_2 34
#define MR_3 35
#define WINDOWBASE 72
#define WINDOWSTART 73
#define IBREAKENABLE 96
#define MEMCTL 97
#define ATOMCTL 99
#define DDR 104
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define EPC_5 181
#define EPC_6 182
#define EPC_7 183
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EPS_5 197
#define EPS_6 198
#define EPS_7 199
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define EXCSAVE_5 213
#define EXCSAVE_6 214
#define EXCSAVE_7 215
#define CPENABLE 224
#define INTERRUPT 226
#define INTENABLE 228
#define PS 230
#define VECBASE 231
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
#define MISC_REG_2 246
#define MISC_REG_3 247
/* Special cases (bases of special register series): */
#define MR 32
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
/* Special names for read-only and write-only interrupt registers: */
#define INTREAD 226
#define INTSET 226
#define INTCLEAR 227
#endif /* XTENSA_SPECREG_H */

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/*
* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
*
* NOTE: The location and contents of this file are highly subject to change.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* The HAL itself has historically included this file in some instances,
* but this is not appropriate either, because the HAL is meant to be
* core-specific but system independent.
*/
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2000-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H
/*#include <xtensa/hal.h>*/
/*----------------------------------------------------------------------
CONFIGURED SOFTWARE OPTIONS
----------------------------------------------------------------------*/
#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */
/* The above maps to one of the following constants: */
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
/* Alternatives: */
/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
/* The above maps to one of the following constants: */
#define XTHAL_CLIB_NEWLIB 0
#define XTHAL_CLIB_UCLIBC 1
#define XTHAL_CLIB_XCLIB 2
/* Alternatives: */
/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
#define XSHAL_USE_FLOATING_POINT 1
#define XSHAL_FLOATING_POINT_ABI 0
/* SW workarounds enabled for HW errata: */
/*----------------------------------------------------------------------
DEVICE ADDRESSES
----------------------------------------------------------------------*/
/*
* Strange place to find these, but the configuration GUI
* allows moving these around to account for various core
* configurations. Specific boards (and their BSP software)
* will have specific meanings for these components.
*/
/* I/O Block areas: */
#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
/* System ROM: */
#define XSHAL_ROM_VADDR 0x50000000
#define XSHAL_ROM_PADDR 0x50000000
#define XSHAL_ROM_SIZE 0x01000000
/* Largest available area (free of vectors): */
#define XSHAL_ROM_AVAIL_VADDR 0x50000000
#define XSHAL_ROM_AVAIL_VSIZE 0x01000000
/* System RAM: */
#define XSHAL_RAM_VADDR 0x60000000
#define XSHAL_RAM_PADDR 0x60000000
#define XSHAL_RAM_VSIZE 0x20000000
#define XSHAL_RAM_PSIZE 0x20000000
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
/* Largest available area (free of vectors): */
#define XSHAL_RAM_AVAIL_VADDR 0x60000000
#define XSHAL_RAM_AVAIL_VSIZE 0x20000000
/*
* Shadow system RAM (same device as system RAM, at different address).
* (Emulation boards need this for the SONIC Ethernet driver
* when data caches are configured for writeback mode.)
* NOTE: on full MMU configs, this points to the BYPASS virtual address
* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
* addresses are viewed through the BYPASS static map rather than
* the CACHED static map.
*/
#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
#define XSHAL_RAM_BYPASS_PSIZE 0x20000000
/* Alternate system RAM (different device than system RAM): */
/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
/* Some available location in which to place devices in a simulation (eg. XTMP): */
#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
#define XSHAL_SIMIO_PADDR 0xC0000000
#define XSHAL_SIMIO_SIZE 0x20000000
/*----------------------------------------------------------------------
* For use by reference testbench exit and diagnostic routines.
*/
#define XSHAL_MAGIC_EXIT 0x0
/*----------------------------------------------------------------------
* DEVICE-ADDRESS DEPENDENT...
*
* Values written to CACHEATTR special register (or its equivalent)
* to enable and disable caches in various modes.
*----------------------------------------------------------------------*/
/*----------------------------------------------------------------------
BACKWARD COMPATIBILITY ...
----------------------------------------------------------------------*/
/*
* NOTE: the following two macros are DEPRECATED. Use the latter
* board-specific macros instead, which are specially tuned for the
* particular target environments' memory maps.
*/
#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
/*----------------------------------------------------------------------
GENERIC
----------------------------------------------------------------------*/
/* For the following, a 512MB region is used if it contains a system (PIF) RAM,
* system (PIF) ROM, local memory, or XLMI. */
/* These set any unused 512MB region to cache-BYPASS attribute: */
#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22221112 /* enable caches in write-back mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
/* These set any unused 512MB region to ILLEGAL attribute: */
#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF111F /* enable caches in write-back mode */
#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
* NULL-pointer dereference bugs; all other unused 512MB regions are set
* to cache-BYPASS attribute: */
#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
/*----------------------------------------------------------------------
ISS (Instruction Set Simulator) SPECIFIC ...
----------------------------------------------------------------------*/
/* For now, ISS defaults to the TRAPNULL settings: */
#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
#define XSHAL_ISS_PIPE_REGIONS 0
#define XSHAL_ISS_SDRAM_REGIONS 0
/*----------------------------------------------------------------------
XT2000 BOARD SPECIFIC ...
----------------------------------------------------------------------*/
/* For the following, a 512MB region is used if it contains any system RAM,
* system ROM, local memory, XLMI, or other XT2000 board device or memory.
* Regions containing devices are forced to cache-BYPASS mode regardless
* of whether the macro is _WRITEBACK vs. _BYPASS etc. */
/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22111F /* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
/*----------------------------------------------------------------------
VECTOR INFO AND SIZES
----------------------------------------------------------------------*/
#define XSHAL_VECTORS_PACKED 0
#define XSHAL_STATIC_VECTOR_SELECT 1
#define XSHAL_RESET_VECTOR_VADDR 0x40000400
#define XSHAL_RESET_VECTOR_PADDR 0x40000400
/*
* Sizes allocated to vectors by the system (memory map) configuration.
* These sizes are constrained by core configuration (eg. one vector's
* code cannot overflow into another vector) but are dependent on the
* system or board (or LSP) memory map configuration.
*
* Whether or not each vector happens to be in a system ROM is also
* a system configuration matter, sometimes useful, included here also:
*/
#define XSHAL_RESET_VECTOR_SIZE 0x00000300
#define XSHAL_RESET_VECTOR_ISROM 0
#define XSHAL_USER_VECTOR_SIZE 0x00000038
#define XSHAL_USER_VECTOR_ISROM 0
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
#define XSHAL_KERNEL_VECTOR_ISROM 0
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
#define XSHAL_WINDOW_VECTORS_ISROM 0
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
#define XSHAL_NMI_VECTOR_SIZE 0x00000038
#define XSHAL_NMI_VECTOR_ISROM 0
#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
#endif /*XTENSA_CONFIG_SYSTEM_H*/

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/*
* tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
*
* NOTE: This header file is not meant to be included directly.
*/
/* This header file contains assembly-language definitions (assembly
macros, etc.) for this specific Xtensa processor's TIE extensions
and options. It is customized to this Xtensa processor configuration.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_TIE_ASM_H
#define _XTENSA_CORE_TIE_ASM_H
/* Selection parameter values for save-area save/restore macros: */
/* Option vs. TIE: */
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
/* Whether used automatically by compiler: */
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
/* ABI handling across function calls: */
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
/* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
| ((ccuse) & XTHAL_SAS_ANYCC) \
| ((abi) & XTHAL_SAS_ANYABI) )
/*
* Macro to store all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger store sequence, set to 1
* if this is not the first in the sequence. Defaults to 0.
* ofs Offset from start of larger sequence (from value of first ptr
* in sequence) at which to store. Defaults to next available space
* (or 0 if <continue> is 0).
* select Select what category(ies) of registers to store, as a bitmask
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
* alloc Select what category(ies) of registers to allocate; if any
* category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any store.
*/
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
rur.THREADPTR \at1 // threadptr option
s32i \at1, \ptr, .Lxchal_ofs_+0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
// Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4
rsr.ACCLO \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.ACCHI \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1012, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4
rsr.BR \at1 // boolean option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.SCOMPARE1 \at1 // conditional store option
s32i \at1, \ptr, .Lxchal_ofs_+4
rsr.M0 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+8
rsr.M1 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+12
rsr.M2 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+16
rsr.M3 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+20
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1008, 4, 4
rur.F64R_LO \at1 // ureg 234
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.F64R_HI \at1 // ureg 235
s32i \at1, \ptr, .Lxchal_ofs_+4
rur.F64S \at1 // ureg 236
s32i \at1, \ptr, .Lxchal_ofs_+8
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1008, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.endif
.endm // xchal_ncp_store
/*
* Macro to load all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger load sequence, set to 1
* if this is not the first in the sequence. Defaults to 0.
* ofs Offset from start of larger sequence (from value of first ptr
* in sequence) at which to load. Defaults to next available space
* (or 0 if <continue> is 0).
* select Select what category(ies) of registers to load, as a bitmask
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
* alloc Select what category(ies) of registers to allocate; if any
* category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any load.
*/
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.THREADPTR \at1 // threadptr option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
// Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.ACCLO \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.ACCHI \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1012, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.BR \at1 // boolean option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.SCOMPARE1 \at1 // conditional store option
l32i \at1, \ptr, .Lxchal_ofs_+8
wsr.M0 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+12
wsr.M1 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+16
wsr.M2 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+20
wsr.M3 \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1008, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.F64R_LO \at1 // ureg 234
l32i \at1, \ptr, .Lxchal_ofs_+4
wur.F64R_HI \at1 // ureg 235
l32i \at1, \ptr, .Lxchal_ofs_+8
wur.F64S \at1 // ureg 236
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1008, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.endif
.endm // xchal_ncp_load
#define XCHAL_NCP_NUM_ATMPS 1
/*
* Macro to store the state of TIE coprocessor FPU.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_store.
*/
#define xchal_cp_FPU_store xchal_cp0_store
.macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4
rur.FCR \at1 // ureg 232
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.FSR \at1 // ureg 233
s32i \at1, \ptr, .Lxchal_ofs_+4
ssi f0, \ptr, .Lxchal_ofs_+8
ssi f1, \ptr, .Lxchal_ofs_+12
ssi f2, \ptr, .Lxchal_ofs_+16
ssi f3, \ptr, .Lxchal_ofs_+20
ssi f4, \ptr, .Lxchal_ofs_+24
ssi f5, \ptr, .Lxchal_ofs_+28
ssi f6, \ptr, .Lxchal_ofs_+32
ssi f7, \ptr, .Lxchal_ofs_+36
ssi f8, \ptr, .Lxchal_ofs_+40
ssi f9, \ptr, .Lxchal_ofs_+44
ssi f10, \ptr, .Lxchal_ofs_+48
ssi f11, \ptr, .Lxchal_ofs_+52
ssi f12, \ptr, .Lxchal_ofs_+56
ssi f13, \ptr, .Lxchal_ofs_+60
ssi f14, \ptr, .Lxchal_ofs_+64
ssi f15, \ptr, .Lxchal_ofs_+68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 948, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_store
/*
* Macro to load the state of TIE coprocessor FPU.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_load.
*/
#define xchal_cp_FPU_load xchal_cp0_load
.macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.FCR \at1 // ureg 232
l32i \at1, \ptr, .Lxchal_ofs_+4
wur.FSR \at1 // ureg 233
lsi f0, \ptr, .Lxchal_ofs_+8
lsi f1, \ptr, .Lxchal_ofs_+12
lsi f2, \ptr, .Lxchal_ofs_+16
lsi f3, \ptr, .Lxchal_ofs_+20
lsi f4, \ptr, .Lxchal_ofs_+24
lsi f5, \ptr, .Lxchal_ofs_+28
lsi f6, \ptr, .Lxchal_ofs_+32
lsi f7, \ptr, .Lxchal_ofs_+36
lsi f8, \ptr, .Lxchal_ofs_+40
lsi f9, \ptr, .Lxchal_ofs_+44
lsi f10, \ptr, .Lxchal_ofs_+48
lsi f11, \ptr, .Lxchal_ofs_+52
lsi f12, \ptr, .Lxchal_ofs_+56
lsi f13, \ptr, .Lxchal_ofs_+60
lsi f14, \ptr, .Lxchal_ofs_+64
lsi f15, \ptr, .Lxchal_ofs_+68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 948, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_load
#define XCHAL_CP0_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
/* Empty macros for unconfigured coprocessors: */
.macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
#endif /*_XTENSA_CORE_TIE_ASM_H*/

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/*
* tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
*
* NOTE: This header file is not meant to be included directly.
*/
/* This header file describes this specific Xtensa processor's TIE extensions
that extend basic Xtensa core functionality. It is customized to this
Xtensa processor configuration.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_TIE_H
#define _XTENSA_CORE_TIE_H
#define XCHAL_CP_NUM 1 /* number of coprocessors */
#define XCHAL_CP_MAX 1 /* max CP ID + 1 (0 if none) */
#define XCHAL_CP_MASK 0x01 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
/* Basic parameters of each coprocessor: */
#define XCHAL_CP0_NAME "FPU"
#define XCHAL_CP0_IDENT FPU
#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_SIZE 0
#define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 48
#define XCHAL_NCP_SA_ALIGN 4
/* Total save area for optional and custom state (NCP + CPn): */
#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
/*
* Detailed contents of save areas.
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
* before expanding the XCHAL_xxx_SA_LIST() macros.
*
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
*
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
* ccused = set if used by compiler without special options or code
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
* name = lowercase reg name (no quotes)
* galign = group byte alignment (power of 2) (galign >= align)
* align = register byte alignment (power of 2)
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
* (not including any pad bytes required to galign this or next reg)
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
* regnum = reg index in regfile, or special/TIE-user reg number
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
* gapsz = intervening bits, if bitsz bits not stored contiguously
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
* reset = register reset value (or 0 if undefined at reset)
* x = reserved for future use (0 until then)
*
* To filter out certain registers, e.g. to expand only the non-global
* registers used by the compiler, you can do something like this:
*
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* ...what you want to expand...
*/
#define XCHAL_NCP_SA_NUM 12
#define XCHAL_NCP_SA_LIST(s) \
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64r_lo, 4, 4, 4,0x03EA, ur,234, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64r_hi, 4, 4, 4,0x03EB, ur,235, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64s, 4, 4, 4,0x03EC, ur,236, 32,0,0,0)
#define XCHAL_CP0_SA_NUM 18
#define XCHAL_CP0_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
#define XCHAL_CP1_SA_NUM 0
#define XCHAL_CP1_SA_LIST(s) /* empty */
#define XCHAL_CP2_SA_NUM 0
#define XCHAL_CP2_SA_LIST(s) /* empty */
#define XCHAL_CP3_SA_NUM 0
#define XCHAL_CP3_SA_LIST(s) /* empty */
#define XCHAL_CP4_SA_NUM 0
#define XCHAL_CP4_SA_LIST(s) /* empty */
#define XCHAL_CP5_SA_NUM 0
#define XCHAL_CP5_SA_LIST(s) /* empty */
#define XCHAL_CP6_SA_NUM 0
#define XCHAL_CP6_SA_LIST(s) /* empty */
#define XCHAL_CP7_SA_NUM 0
#define XCHAL_CP7_SA_LIST(s) /* empty */
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
/* Byte length of instruction from its first byte, per FLIX. */
#define XCHAL_BYTE0_FORMAT_LENGTHS \
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_XTENSA_CORE_TIE_H*/

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/*
* xtensa/core-macros.h -- C specific definitions
* that depend on CORE configuration
*/
/*
* Copyright (c) 2012 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_CACHE_H
#define XTENSA_CACHE_H
#include <xtensa/config/core.h>
/* Only define things for C code. */
#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
/*************************** CACHE ***************************/
/* All the macros are in the lower case now and some of them
* share the name with the existing functions from hal.h.
* Including this header file will define XTHAL_USE_CACHE_MACROS
* which directs hal.h not to use the functions.
*
/*
* Single-cache-line operations in C-callable inline assembly.
* Essentially macro versions (uppercase) of:
*
* xthal_icache_line_invalidate(void *addr);
* xthal_icache_line_lock(void *addr);
* xthal_icache_line_unlock(void *addr);
* xthal_icache_sync(void);
*
* NOTE: unlike the above functions, the following macros do NOT
* execute the xthal_icache_sync() as part of each line operation.
* This sync must be called explicitly by the caller. This is to
* allow better optimization when operating on more than one line.
*
* xthal_dcache_line_invalidate(void *addr);
* xthal_dcache_line_writeback(void *addr);
* xthal_dcache_line_writeback_inv(void *addr);
* xthal_dcache_line_lock(void *addr);
* xthal_dcache_line_unlock(void *addr);
* xthal_dcache_sync(void);
* xthal_dcache_line_prefetch_for_write(void *addr);
* xthal_dcache_line_prefetch_for_read(void *addr);
*
* All are made memory-barriers, given that's how they're typically used
* (ops operate on a whole line, so clobbers all memory not just *addr).
*
* NOTE: All the block block cache ops and line prefetches are implemented
* using intrinsics so they are better optimized regarding memory barriers etc.
*
* All block downgrade functions exist in two forms: with and without
* the 'max' parameter: This parameter allows compiler to optimize
* the functions whenever the parameter is smaller than the cache size.
*
* xthal_dcache_block_invalidate(void *addr, unsigned size);
* xthal_dcache_block_writeback(void *addr, unsigned size);
* xthal_dcache_block_writeback_inv(void *addr, unsigned size);
* xthal_dcache_block_invalidate_max(void *addr, unsigned size, unsigned max);
* xthal_dcache_block_writeback_max(void *addr, unsigned size, unsigned max);
* xthal_dcache_block_writeback_inv_max(void *addr, unsigned size, unsigned max);
*
* xthal_dcache_block_prefetch_for_read(void *addr, unsigned size);
* xthal_dcache_block_prefetch_for_write(void *addr, unsigned size);
* xthal_dcache_block_prefetch_modify(void *addr, unsigned size);
* xthal_dcache_block_prefetch_read_write(void *addr, unsigned size);
* xthal_dcache_block_prefetch_for_read_grp(void *addr, unsigned size);
* xthal_dcache_block_prefetch_for_write_grp(void *addr, unsigned size);
* xthal_dcache_block_prefetch_modify_grp(void *addr, unsigned size);
* xthal_dcache_block_prefetch_read_write_grp(void *addr, unsigned size)
*
* xthal_dcache_block_wait();
* xthal_dcache_block_required_wait();
* xthal_dcache_block_abort();
* xthal_dcache_block_prefetch_end();
* xthal_dcache_block_newgrp();
*/
/*** INSTRUCTION CACHE ***/
#define XTHAL_USE_CACHE_MACROS
#if XCHAL_ICACHE_SIZE > 0
# define xthal_icache_line_invalidate(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("ihi %0, 0" :: "a"(__a) : "memory"); \
} while(0)
#else
# define xthal_icache_line_invalidate(addr) do {/*nothing*/} while(0)
#endif
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
# define xthal_icache_line_lock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("ipfl %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_icache_line_unlock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("ihu %0, 0" :: "a"(__a) : "memory"); \
} while(0)
#else
# define xthal_icache_line_lock(addr) do {/*nothing*/} while(0)
# define xthal_icache_line_unlock(addr) do {/*nothing*/} while(0)
#endif
/*
* Even if a config doesn't have caches, an isync is still needed
* when instructions in any memory are modified, whether by a loader
* or self-modifying code. Therefore, this macro always produces
* an isync, whether or not an icache is present.
*/
#define xthal_icache_sync() \
__asm__ __volatile__("isync":::"memory")
/*** DATA CACHE ***/
#if XCHAL_DCACHE_SIZE > 0
# include <xtensa/tie/xt_datacache.h>
# define xthal_dcache_line_invalidate(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhi %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_line_writeback(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhwb %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_line_writeback_inv(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhwbi %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_sync() \
__asm__ __volatile__("" /*"dsync"?*/:::"memory")
# define xthal_dcache_line_prefetch_for_read(addr) do { \
XT_DPFR((const int*)addr, 0); \
} while(0)
#else
# define xthal_dcache_line_invalidate(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_writeback(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_writeback_inv(addr) do {/*nothing*/} while(0)
# define xthal_dcache_sync() __asm__ __volatile__("":::"memory")
# define xthal_dcache_line_prefetch_for_read(addr) do {/*nothing*/} while(0)
#endif
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
# define xthal_dcache_line_lock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dpfl %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_line_unlock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhu %0, 0" :: "a"(__a) : "memory"); \
} while(0)
#else
# define xthal_dcache_line_lock(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_unlock(addr) do {/*nothing*/} while(0)
#endif
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
# define xthal_dcache_line_prefetch_for_write(addr) do { \
XT_DPFW((const int*)addr, 0); \
} while(0)
#else
# define xthal_dcache_line_prefetch_for_write(addr) do {/*nothing*/} while(0)
#endif
/***** Block Operations *****/
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS
/* upgrades */
# define _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, type) \
{ \
type((const int*)addr, size); \
}
/*downgrades */
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type) \
unsigned _s = size; \
unsigned _a = addr; \
do { \
unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? \
XCHAL_DCACHE_SIZE : _s; \
type((const int*)_a, __s); \
_s -= __s; \
_a += __s; \
} while(_s > 0);
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max) \
if (max <= XCHAL_DCACHE_SIZE) { \
unsigned _s = size; \
unsigned _a = addr; \
type((const int*)_a, _s); \
} \
else { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type); \
}
# define xthal_dcache_block_invalidate(addr, size) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHI_B); \
} while(0)
# define xthal_dcache_block_writeback(addr, size) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWB_B); \
} while(0)
# define xthal_dcache_block_writeback_inv(addr, size) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWBI_B); \
} while(0)
# define xthal_dcache_block_invalidate_max(addr, size, max) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHI_B, max); \
} while(0)
# define xthal_dcache_block_writeback_max(addr, size, max) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWB_B, max); \
} while(0)
# define xthal_dcache_block_writeback_inv_max(addr, size, max) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWBI_B, max); \
} while(0)
/* upgrades that are performed even with write-thru caches */
# define xthal_dcache_block_prefetch_read_write(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
} while(0)
# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
} while(0)
# define xthal_dcache_block_prefetch_for_read(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_B); \
} while(0)
# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_BF); \
} while(0)
/* abort all or end optional block cache operations */
# define xthal_dcache_block_abort() do { \
XT_PFEND_A(); \
} while(0)
# define xthal_dcache_block_end() do { \
XT_PFEND_O(); \
} while(0)
/* wait for all/required block cache operations to finish */
# define xthal_dcache_block_wait() do { \
XT_PFWAIT_A(); \
} while(0)
# define xthal_dcache_block_required_wait() do { \
XT_PFWAIT_R(); \
} while(0)
/* Start a new group */
# define xthal_dcache_block_newgrp() do { \
XT_PFNXT_F(); \
} while(0)
#else
# define xthal_dcache_block_invalidate(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback_inv(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_invalidate_max(addr, size, max) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback_max(addr, size, max) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback_inv_max(addr, size, max) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_read_write(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_for_read(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_end() do {/*nothing*/} while(0)
# define xthal_dcache_block_abort() do {/*nothing*/} while(0)
# define xthal_dcache_block_wait() do {/*nothing*/} while(0)
# define xthal_dcache_block_required_wait() do {/*nothing*/} while(0)
# define xthal_dcache_block_newgrp() do {/*nothing*/} while(0)
#endif
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK
# define xthal_dcache_block_prefetch_for_write(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
} while(0)
# define xthal_dcache_block_prefetch_modify(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_B); \
} while(0)
# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
} while(0)
# define xthal_dcache_block_prefetch_modify_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_BF); \
} while(0)
#else
# define xthal_dcache_block_prefetch_for_write(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_modify(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_modify_grp(addr, size) do {/*nothing*/} while(0)
#endif
/*************************** INTERRUPTS ***************************/
/*
* Macro versions of:
* unsigned xthal_get_intenable( void );
* void xthal_set_intenable( unsigned );
* unsigned xthal_get_interrupt( void );
* void xthal_set_intset( unsigned );
* void xthal_set_intclear( unsigned );
* unsigned xthal_get_ccount(void);
* void xthal_set_ccompare(int, unsigned);
* unsigned xthal_get_ccompare(int);
*
* NOTE: for {set,get}_ccompare, the first argument MUST be a decimal constant.
*/
#if XCHAL_HAVE_INTERRUPTS
# define XTHAL_GET_INTENABLE() ({ int __intenable; \
__asm__("rsr.intenable %0" : "=a"(__intenable)); \
__intenable; })
# define XTHAL_SET_INTENABLE(v) do { int __intenable = (int)(v); \
__asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
} while(0)
# define XTHAL_GET_INTERRUPT() ({ int __interrupt; \
__asm__("rsr.interrupt %0" : "=a"(__interrupt)); \
__interrupt; })
# define XTHAL_SET_INTSET(v) do { int __interrupt = (int)(v); \
__asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \
} while(0)
# define XTHAL_SET_INTCLEAR(v) do { int __interrupt = (int)(v); \
__asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \
} while(0)
# define XTHAL_GET_CCOUNT() ({ int __ccount; \
__asm__("rsr.ccount %0" : "=a"(__ccount)); \
__ccount; })
# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \
__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \
} while(0)
# define _XTHAL_GET_CCOMPARE(n) ({ int __ccompare; \
__asm__("rsr.ccompare" #n " %0" : "=a"(__ccompare)); \
__ccompare; })
# define XTHAL_GET_CCOMPARE(n) _XTHAL_GET_CCOMPARE(n)
# define _XTHAL_SET_CCOMPARE(n,v) do { int __ccompare = (int)(v); \
__asm__ __volatile__("wsr.ccompare" #n " %0 ; esync" :: "a"(__ccompare):"memory"); \
} while(0)
# define XTHAL_SET_CCOMPARE(n,v) _XTHAL_SET_CCOMPARE(n,v)
#else
# define XTHAL_GET_INTENABLE() 0
# define XTHAL_SET_INTENABLE(v) do {/*nothing*/} while(0)
# define XTHAL_GET_INTERRUPT() 0
# define XTHAL_SET_INTSET(v) do {/*nothing*/} while(0)
# define XTHAL_SET_INTCLEAR(v) do {/*nothing*/} while(0)
# define XTHAL_GET_CCOUNT() 0
# define XTHAL_SET_CCOUNT(v) do {/*nothing*/} while(0)
# define XTHAL_GET_CCOMPARE(n) 0
# define XTHAL_SET_CCOMPARE(n,v) do {/*nothing*/} while(0)
#endif
/*************************** MISC ***************************/
/*
* Macro or inline versions of:
* void xthal_clear_regcached_code( void );
* unsigned xthal_get_prid( void );
* unsigned xthal_compare_and_set( int *addr, int testval, int setval );
*/
#if XCHAL_HAVE_LOOPS
# define XTHAL_CLEAR_REGCACHED_CODE() \
__asm__ __volatile__("wsr.lcount %0" :: "a"(0) : "memory")
#else
# define XTHAL_CLEAR_REGCACHED_CODE() do {/*nothing*/} while(0)
#endif
#if XCHAL_HAVE_PRID
# define XTHAL_GET_PRID() ({ int __prid; \
__asm__("rsr.prid %0" : "=a"(__prid)); \
__prid; })
#else
# define XTHAL_GET_PRID() 0
#endif
static inline unsigned XTHAL_COMPARE_AND_SET( int *addr, int testval, int setval )
{
int result;
#if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
__asm__ __volatile__ (
" wsr.scompare1 %2 \n"
" s32c1i %0, %3, 0 \n"
: "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
: "memory");
#elif XCHAL_HAVE_INTERRUPTS
int tmp;
__asm__ __volatile__ (
" rsil %4, 15 \n" // %4 == saved ps
" l32i %0, %3, 0 \n" // %0 == value to test, return val
" bne %2, %0, 9f \n" // test
" s32i %1, %3, 0 \n" // write the new value
"9: wsr.ps %4 ; rsync \n" // restore the PS
: "=a"(result)
: "0" (setval), "a" (testval), "a" (addr), "a" (tmp)
: "memory");
#else
__asm__ __volatile__ (
" l32i %0, %3, 0 \n" // %0 == value to test, return val
" bne %2, %0, 9f \n" // test
" s32i %1, %3, 0 \n" // write the new value
"9: \n"
: "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
: "memory");
#endif
return result;
}
#if XCHAL_HAVE_EXTERN_REGS
static inline unsigned XTHAL_RER (unsigned int reg)
{
unsigned result;
__asm__ __volatile__ (
" rer %0, %1"
: "=a" (result) : "a" (reg) : "memory");
return result;
}
static inline void XTHAL_WER (unsigned reg, unsigned value)
{
__asm__ __volatile__ (
" wer %0, %1"
: : "a" (value), "a" (reg) : "memory");
}
#endif /* XCHAL_HAVE_EXTERN_REGS */
#endif /* C code */
#endif /*XTENSA_CACHE_H*/

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/*
* xtensa/coreasm.h -- assembler-specific definitions that depend on CORE configuration
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL itself to include this file.
*
* This file must NOT include xtensa/config/system.h. Any assembler
* header file that depends on system information should likely go
* in a new systemasm.h (or sysasm.h) header file.
*
* NOTE: macro beqi32 is NOT configuration-dependent, and is placed
* here until we have a proper configuration-independent header file.
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/coreasm.h#3 $ */
/*
* Copyright (c) 2000-2014 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_COREASM_H
#define XTENSA_COREASM_H
/*
* Tell header files this is assembly source, so they can avoid non-assembler
* definitions (eg. C types etc):
*/
#ifndef _ASMLANGUAGE /* conditionalize to avoid cpp warnings (3rd parties might use same macro) */
#define _ASMLANGUAGE
#endif
#include <xtensa/config/core.h>
#include <xtensa/config/specreg.h>
#include <xtensa/config/system.h>
/*
* Assembly-language specific definitions (assembly macros, etc.).
*/
/*----------------------------------------------------------------------
* find_ms_setbit
*
* This macro finds the most significant bit that is set in <as>
* and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
* The index counts starting at zero for the lsbit, so the return
* value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
*
* Parameters:
* <ad> destination address register (any register)
* <as> source address register
* <at> temporary address register (must be different than <as>)
* <base> constant value added to result (usually 0 or 1)
* On entry:
* <ad> = undefined if different than <as>
* <as> = value whose most significant set bit is to be found
* <at> = undefined
* no other registers are used by this macro.
* On exit:
* <ad> = <base> + index of msbit set in original <as>,
* = <base> - 1 if original <as> was zero.
* <as> clobbered (if not <ad>)
* <at> clobbered (if not <ad>)
* Example:
* find_ms_setbit a0, a4, a0, 0 -- return in a0 index of msbit set in a4
*/
.macro find_ms_setbit ad, as, at, base
#if XCHAL_HAVE_NSA
movi \at, 31+\base
nsau \as, \as // get index of \as, numbered from msbit (32 if absent)
sub \ad, \at, \as // get numbering from lsbit (0..31, -1 if absent)
#else /* XCHAL_HAVE_NSA */
movi \at, \base // start with result of 0 (point to lsbit of 32)
beqz \as, 2f // special case for zero argument: return -1
bltui \as, 0x10000, 1f // is it one of the 16 lsbits? (if so, check lower 16 bits)
addi \at, \at, 16 // no, increment result to upper 16 bits (of 32)
//srli \as, \as, 16 // check upper half (shift right 16 bits)
extui \as, \as, 16, 16 // check upper half (shift right 16 bits)
1: bltui \as, 0x100, 1f // is it one of the 8 lsbits? (if so, check lower 8 bits)
addi \at, \at, 8 // no, increment result to upper 8 bits (of 16)
srli \as, \as, 8 // shift right to check upper 8 bits
1: bltui \as, 0x10, 1f // is it one of the 4 lsbits? (if so, check lower 4 bits)
addi \at, \at, 4 // no, increment result to upper 4 bits (of 8)
srli \as, \as, 4 // shift right 4 bits to check upper half
1: bltui \as, 0x4, 1f // is it one of the 2 lsbits? (if so, check lower 2 bits)
addi \at, \at, 2 // no, increment result to upper 2 bits (of 4)
srli \as, \as, 2 // shift right 2 bits to check upper half
1: bltui \as, 0x2, 1f // is it the lsbit?
addi \at, \at, 2 // no, increment result to upper bit (of 2)
2: addi \at, \at, -1 // (from just above: add 1; from beqz: return -1)
//srli \as, \as, 1
1: // done! \at contains index of msbit set (or -1 if none set)
.if 0x\ad - 0x\at // destination different than \at ? (works because regs are a0-a15)
mov \ad, \at // then move result to \ad
.endif
#endif /* XCHAL_HAVE_NSA */
.endm // find_ms_setbit
/*----------------------------------------------------------------------
* find_ls_setbit
*
* This macro finds the least significant bit that is set in <as>,
* and return its index in <ad>.
* Usage is the same as for the find_ms_setbit macro.
* Example:
* find_ls_setbit a0, a4, a0, 0 -- return in a0 index of lsbit set in a4
*/
.macro find_ls_setbit ad, as, at, base
neg \at, \as // keep only the least-significant bit that is set...
and \as, \at, \as // ... in \as
find_ms_setbit \ad, \as, \at, \base
.endm // find_ls_setbit
/*----------------------------------------------------------------------
* find_ls_one
*
* Same as find_ls_setbit with base zero.
* Source (as) and destination (ad) registers must be different.
* Provided for backward compatibility.
*/
.macro find_ls_one ad, as
find_ls_setbit \ad, \as, \ad, 0
.endm // find_ls_one
/*----------------------------------------------------------------------
* floop, floopnez, floopgtz, floopend
*
* These macros are used for fast inner loops that
* work whether or not the Loops options is configured.
* If the Loops option is configured, they simply use
* the zero-overhead LOOP instructions; otherwise
* they use explicit decrement and branch instructions.
*
* They are used in pairs, with floop, floopnez or floopgtz
* at the beginning of the loop, and floopend at the end.
*
* Each pair of loop macro calls must be given the loop count
* address register and a unique label for that loop.
*
* Example:
*
* movi a3, 16 // loop 16 times
* floop a3, myloop1
* :
* bnez a7, end1 // exit loop if a7 != 0
* :
* floopend a3, myloop1
* end1:
*
* Like the LOOP instructions, these macros cannot be
* nested, must include at least one instruction,
* cannot call functions inside the loop, etc.
* The loop can be exited by jumping to the instruction
* following floopend (or elsewhere outside the loop),
* or continued by jumping to a NOP instruction placed
* immediately before floopend.
*
* Unlike LOOP instructions, the register passed to floop*
* cannot be used inside the loop, because it is used as
* the loop counter if the Loops option is not configured.
* And its value is undefined after exiting the loop.
* And because the loop counter register is active inside
* the loop, you can't easily use this construct to loop
* across a register file using ROTW as you might with LOOP
* instructions, unless you copy the loop register along.
*/
/* Named label version of the macros: */
.macro floop ar, endlabel
floop_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
.macro floopnez ar, endlabel
floopnez_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
.macro floopgtz ar, endlabel
floopgtz_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
.macro floopend ar, endlabel
floopend_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
/* Numbered local label version of the macros: */
#if 0 /*UNTESTED*/
.macro floop89 ar
floop_ \ar, 8, 9f
.endm
.macro floopnez89 ar
floopnez_ \ar, 8, 9f
.endm
.macro floopgtz89 ar
floopgtz_ \ar, 8, 9f
.endm
.macro floopend89 ar
floopend_ \ar, 8b, 9
.endm
#endif /*0*/
/* Underlying version of the macros: */
.macro floop_ ar, startlabel, endlabelref
.ifdef _infloop_
.if _infloop_
.err // Error: floop cannot be nested
.endif
.endif
.set _infloop_, 1
#if XCHAL_HAVE_LOOPS
loop \ar, \endlabelref
#else /* XCHAL_HAVE_LOOPS */
\startlabel:
addi \ar, \ar, -1
#endif /* XCHAL_HAVE_LOOPS */
.endm // floop_
.macro floopnez_ ar, startlabel, endlabelref
.ifdef _infloop_
.if _infloop_
.err // Error: floopnez cannot be nested
.endif
.endif
.set _infloop_, 1
#if XCHAL_HAVE_LOOPS
loopnez \ar, \endlabelref
#else /* XCHAL_HAVE_LOOPS */
beqz \ar, \endlabelref
\startlabel:
addi \ar, \ar, -1
#endif /* XCHAL_HAVE_LOOPS */
.endm // floopnez_
.macro floopgtz_ ar, startlabel, endlabelref
.ifdef _infloop_
.if _infloop_
.err // Error: floopgtz cannot be nested
.endif
.endif
.set _infloop_, 1
#if XCHAL_HAVE_LOOPS
loopgtz \ar, \endlabelref
#else /* XCHAL_HAVE_LOOPS */
bltz \ar, \endlabelref
beqz \ar, \endlabelref
\startlabel:
addi \ar, \ar, -1
#endif /* XCHAL_HAVE_LOOPS */
.endm // floopgtz_
.macro floopend_ ar, startlabelref, endlabel
.ifndef _infloop_
.err // Error: floopend without matching floopXXX
.endif
.ifeq _infloop_
.err // Error: floopend without matching floopXXX
.endif
.set _infloop_, 0
#if ! XCHAL_HAVE_LOOPS
bnez \ar, \startlabelref
#endif /* XCHAL_HAVE_LOOPS */
\endlabel:
.endm // floopend_
/*----------------------------------------------------------------------
* crsil -- conditional RSIL (read/set interrupt level)
*
* Executes the RSIL instruction if it exists, else just reads PS.
* The RSIL instruction does not exist in the new exception architecture
* if the interrupt option is not selected.
*/
.macro crsil ar, newlevel
#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
rsil \ar, \newlevel
#else
rsr \ar, PS
#endif
.endm // crsil
/*----------------------------------------------------------------------
* safe_movi_a0 -- move constant into a0 when L32R is not safe
*
* This macro is typically used by interrupt/exception handlers.
* Loads a 32-bit constant in a0, without using any other register,
* and without corrupting the LITBASE register, even when the
* value of the LITBASE register is unknown (eg. when application
* code and interrupt/exception handling code are built independently,
* and thus with independent values of the LITBASE register;
* debug monitors are one example of this).
*
* Worst-case size of resulting code: 17 bytes.
*/
.macro safe_movi_a0 constant
#if XCHAL_HAVE_ABSOLUTE_LITERALS
/* Contort a PC-relative literal load even though we may be in litbase-relative mode: */
j 1f
.begin no-transform // ensure what follows is assembled exactly as-is
.align 4 // ensure constant and call0 target ...
.byte 0 // ... are 4-byte aligned (call0 instruction is 3 bytes long)
1: call0 2f // read PC (that follows call0) in a0
.long \constant // 32-bit constant to load into a0
2:
.end no-transform
l32i a0, a0, 0 // load constant
#else
movi a0, \constant // no LITBASE, can assume PC-relative L32R
#endif
.endm
/*----------------------------------------------------------------------
* window_spill{4,8,12}
*
* These macros spill callers' register windows to the stack.
* They work for both privileged and non-privileged tasks.
* Must be called from a windowed ABI context, eg. within
* a windowed ABI function (ie. valid stack frame, window
* exceptions enabled, not in exception mode, etc).
*
* This macro requires a single invocation of the window_spill_common
* macro in the same assembly unit and section.
*
* Note that using window_spill{4,8,12} macros is more efficient
* than calling a function implemented using window_spill_function,
* because the latter needs extra code to figure out the size of
* the call to the spilling function.
*
* Example usage:
*
* .text
* .align 4
* .global some_function
* .type some_function,@function
* some_function:
* entry a1, 16
* :
* :
*
* window_spill4 // Spill windows of some_function's callers; preserves a0..a3 only;
* // to use window_spill{8,12} in this example function we'd have
* // to increase space allocated by the entry instruction, because
* // 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
* // for call8/window_spill8 or call12/window_spill12 respectively.
*
* :
*
* retw
*
* window_spill_common // instantiates code used by window_spill4
*
*
* On entry:
* none (if window_spill4)
* stack frame has enough space allocated for call8 (if window_spill8)
* stack frame has enough space allocated for call12 (if window_spill12)
* On exit:
* a4..a15 clobbered (if window_spill4)
* a8..a15 clobbered (if window_spill8)
* a12..a15 clobbered (if window_spill12)
* no caller windows are in live registers
*/
.macro window_spill4
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 16
movi a15, 0 // for 16-register files, no need to call to reach the end
# elif XCHAL_NUM_AREGS == 32
call4 .L__wdwspill_assist28 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call4 .L__wdwspill_assist60 // call deep enough to clear out any live callers
# endif
#endif
.endm // window_spill4
.macro window_spill8
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 16
movi a15, 0 // for 16-register files, no need to call to reach the end
# elif XCHAL_NUM_AREGS == 32
call8 .L__wdwspill_assist24 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call8 .L__wdwspill_assist56 // call deep enough to clear out any live callers
# endif
#endif
.endm // window_spill8
.macro window_spill12
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 16
movi a15, 0 // for 16-register files, no need to call to reach the end
# elif XCHAL_NUM_AREGS == 32
call12 .L__wdwspill_assist20 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call12 .L__wdwspill_assist52 // call deep enough to clear out any live callers
# endif
#endif
.endm // window_spill12
/*----------------------------------------------------------------------
* window_spill_function
*
* This macro outputs a function that will spill its caller's callers'
* register windows to the stack. Eg. it could be used to implement
* a version of xthal_window_spill() that works in non-privileged tasks.
* This works for both privileged and non-privileged tasks.
*
* Typical usage:
*
* .text
* .align 4
* .global my_spill_function
* .type my_spill_function,@function
* my_spill_function:
* window_spill_function
*
* On entry to resulting function:
* none
* On exit from resulting function:
* none (no caller windows are in live registers)
*/
.macro window_spill_function
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 32
entry sp, 48
bbci.l a0, 31, 1f // branch if called with call4
bbsi.l a0, 30, 2f // branch if called with call12
call8 .L__wdwspill_assist16 // called with call8, only need another 8
retw
1: call12 .L__wdwspill_assist16 // called with call4, only need another 12
retw
2: call4 .L__wdwspill_assist16 // called with call12, only need another 4
retw
# elif XCHAL_NUM_AREGS == 64
entry sp, 48
bbci.l a0, 31, 1f // branch if called with call4
bbsi.l a0, 30, 2f // branch if called with call12
call4 .L__wdwspill_assist52 // called with call8, only need a call4
retw
1: call8 .L__wdwspill_assist52 // called with call4, only need a call8
retw
2: call12 .L__wdwspill_assist40 // called with call12, can skip a call12
retw
# elif XCHAL_NUM_AREGS == 16
entry sp, 16
bbci.l a0, 31, 1f // branch if called with call4
bbsi.l a0, 30, 2f // branch if called with call12
movi a7, 0 // called with call8
retw
1: movi a11, 0 // called with call4
2: retw // if called with call12, everything already spilled
// movi a15, 0 // trick to spill all but the direct caller
// j 1f
// // The entry instruction is magical in the assembler (gets auto-aligned)
// // so we have to jump to it to avoid falling through the padding.
// // We need entry/retw to know where to return.
//1: entry sp, 16
// retw
# else
# error "unrecognized address register file size"
# endif
#endif /* XCHAL_HAVE_WINDOWED */
window_spill_common
.endm // window_spill_function
/*----------------------------------------------------------------------
* window_spill_common
*
* Common code used by any number of invocations of the window_spill##
* and window_spill_function macros.
*
* Must be instantiated exactly once within a given assembly unit,
* within call/j range of and same section as window_spill##
* macro invocations for that assembly unit.
* (Is automatically instantiated by the window_spill_function macro.)
*/
.macro window_spill_common
#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
.ifndef .L__wdwspill_defined
# if XCHAL_NUM_AREGS >= 64
.L__wdwspill_assist60:
entry sp, 32
call8 .L__wdwspill_assist52
retw
.L__wdwspill_assist56:
entry sp, 16
call4 .L__wdwspill_assist52
retw
.L__wdwspill_assist52:
entry sp, 48
call12 .L__wdwspill_assist40
retw
.L__wdwspill_assist40:
entry sp, 48
call12 .L__wdwspill_assist28
retw
# endif
.L__wdwspill_assist28:
entry sp, 48
call12 .L__wdwspill_assist16
retw
.L__wdwspill_assist24:
entry sp, 32
call8 .L__wdwspill_assist16
retw
.L__wdwspill_assist20:
entry sp, 16
call4 .L__wdwspill_assist16
retw
.L__wdwspill_assist16:
entry sp, 16
movi a15, 0
retw
.set .L__wdwspill_defined, 1
.endif
#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
.endm // window_spill_common
/*----------------------------------------------------------------------
* beqi32
*
* macro implements version of beqi for arbitrary 32-bit immediate value
*
* beqi32 ax, ay, imm32, label
*
* Compares value in register ax with imm32 value and jumps to label if
* equal. Clobbers register ay if needed
*
*/
.macro beqi32 ax, ay, imm, label
.ifeq ((\imm-1) & ~7) // 1..8 ?
beqi \ax, \imm, \label
.else
.ifeq (\imm+1) // -1 ?
beqi \ax, \imm, \label
.else
.ifeq (\imm) // 0 ?
beqz \ax, \label
.else
// We could also handle immediates 10,12,16,32,64,128,256
// but it would be a long macro...
movi \ay, \imm
beq \ax, \ay, \label
.endif
.endif
.endif
.endm // beqi32
/*----------------------------------------------------------------------
* isync_retw_nop
*
* This macro must be invoked immediately after ISYNC if ISYNC
* would otherwise be immediately followed by RETW (or other instruction
* modifying WindowBase or WindowStart), in a context where
* kernel vector mode may be selected, and level-one interrupts
* and window overflows may be enabled, on an XEA1 configuration.
*
* On hardware with erratum "XEA1KWIN" (see <xtensa/core.h> for details),
* XEA1 code must have at least one instruction between ISYNC and RETW if
* run in kernel vector mode with interrupts and window overflows enabled.
*/
.macro isync_retw_nop
#if XCHAL_MAYHAVE_ERRATUM_XEA1KWIN
nop
#endif
.endm
/*----------------------------------------------------------------------
* isync_erratum453
*
* This macro must be invoked at certain points in the code,
* such as in exception and interrupt vectors in particular,
* to work around erratum 453.
*/
.macro isync_erratum453
#if XCHAL_ERRATUM_453
isync
#endif
.endm
/*----------------------------------------------------------------------
* abs
*
* implements abs on machines that do not have it configured
*/
#if !XCHAL_HAVE_ABS
.macro abs arr, ars
.ifc \arr, \ars
//src equal dest is less efficient
bgez \arr, 1f
neg \arr, \arr
1:
.else
neg \arr, \ars
movgez \arr, \ars, \ars
.endif
.endm
#endif /* !XCHAL_HAVE_ABS */
/*----------------------------------------------------------------------
* addx2
*
* implements addx2 on machines that do not have it configured
*
*/
#if !XCHAL_HAVE_ADDX
.macro addx2 arr, ars, art
.ifc \arr, \art
.ifc \arr, \ars
// addx2 a, a, a (not common)
.err
.else
add \arr, \ars, \art
add \arr, \ars, \art
.endif
.else
//addx2 a, b, c
//addx2 a, a, b
//addx2 a, b, b
slli \arr, \ars, 1
add \arr, \arr, \art
.endif
.endm
#endif /* !XCHAL_HAVE_ADDX */
/*----------------------------------------------------------------------
* addx4
*
* implements addx4 on machines that do not have it configured
*
*/
#if !XCHAL_HAVE_ADDX
.macro addx4 arr, ars, art
.ifc \arr, \art
.ifc \arr, \ars
// addx4 a, a, a (not common)
.err
.else
//# addx4 a, b, a
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
.endif
.else
//addx4 a, b, c
//addx4 a, a, b
//addx4 a, b, b
slli \arr, \ars, 2
add \arr, \arr, \art
.endif
.endm
#endif /* !XCHAL_HAVE_ADDX */
/*----------------------------------------------------------------------
* addx8
*
* implements addx8 on machines that do not have it configured
*
*/
#if !XCHAL_HAVE_ADDX
.macro addx8 arr, ars, art
.ifc \arr, \art
.ifc \arr, \ars
//addx8 a, a, a (not common)
.err
.else
//addx8 a, b, a
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
add \arr, \ars, \art
.endif
.else
//addx8 a, b, c
//addx8 a, a, b
//addx8 a, b, b
slli \arr, \ars, 3
add \arr, \arr, \art
.endif
.endm
#endif /* !XCHAL_HAVE_ADDX */
/*----------------------------------------------------------------------
* rfe_rfue
*
* Maps to RFUE on XEA1, and RFE on XEA2. No mapping on XEAX.
*/
#if XCHAL_HAVE_XEA1
.macro rfe_rfue
rfue
.endm
#elif XCHAL_HAVE_XEA2
.macro rfe_rfue
rfe
.endm
#endif
/*----------------------------------------------------------------------
* abi_entry
*
* Generate proper function entry sequence for the current ABI
* (windowed or call0). Takes care of allocating stack space (up to 1kB)
* and saving the return PC, if necessary. The corresponding abi_return
* macro does the corresponding stack deallocation and restoring return PC.
*
* Parameters are:
*
* locsize Number of bytes to allocate on the stack
* for local variables (and for args to pass to
* callees, if any calls are made). Defaults to zero.
* The macro rounds this up to a multiple of 16.
* NOTE: large values are allowed (e.g. up to 1 GB).
*
* callsize Maximum call size made by this function.
* Leave zero (default) for leaf functions, i.e. if
* this function makes no calls to other functions.
* Otherwise must be set to 4, 8, or 12 according
* to whether the "largest" call made is a call[x]4,
* call[x]8, or call[x]12 (for call0 ABI, it makes
* no difference whether this is set to 4, 8 or 12,
* but it must be set to one of these values).
*
* NOTE: It is up to the caller to align the entry point, declare the
* function symbol, make it global, etc.
*
* NOTE: This macro relies on assembler relaxation for large values
* of locsize. It might not work with the no-transform directive.
* NOTE: For the call0 ABI, this macro ensures SP is allocated or
* de-allocated cleanly, i.e. without temporarily allocating too much
* (or allocating negatively!) due to addi relaxation.
*
* NOTE: Generating the proper sequence and register allocation for
* making calls in an ABI independent manner is a separate topic not
* covered by this macro.
*
* NOTE: To access arguments, you can't use a fixed offset from SP.
* The offset depends on the ABI, whether the function is leaf, etc.
* The simplest method is probably to use the .locsz symbol, which
* is set by this macro to the actual number of bytes allocated on
* the stack, in other words, to the offset from SP to the arguments.
* E.g. for a function whose arguments are all 32-bit integers, you
* can get the 7th and 8th arguments (1st and 2nd args stored on stack)
* using:
* l32i a2, sp, .locsz
* l32i a3, sp, .locsz+4
* (this example works as long as locsize is under L32I's offset limit
* of 1020 minus up to 48 bytes of ABI-specific stack usage;
* otherwise you might first need to do "addi a?, sp, .locsz"
* or similar sequence).
*
* NOTE: For call0 ABI, this macro (and abi_return) may clobber a9
* (a caller-saved register).
*
* Examples:
* abi_entry
* abi_entry 5
* abi_entry 22, 8
* abi_entry 0, 4
*/
/*
* Compute .locsz and .callsz without emitting any instructions.
* Used by both abi_entry and abi_return.
* Assumes locsize >= 0.
*/
.macro abi_entry_size locsize=0, callsize=0
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
.ifeq \callsize
.set .callsz, 16
.else
.ifeq \callsize-4
.set .callsz, 16
.else
.ifeq \callsize-8
.set .callsz, 32
.else
.ifeq \callsize-12
.set .callsz, 48
.else
.error "abi_entry: invalid call size \callsize"
.endif
.endif
.endif
.endif
.set .locsz, .callsz + ((\locsize + 15) & -16)
#else
.set .callsz, \callsize
.if .callsz /* if calls, need space for return PC */
.set .locsz, (\locsize + 4 + 15) & -16
.else
.set .locsz, (\locsize + 15) & -16
.endif
#endif
.endm
.macro abi_entry locsize=0, callsize=0
.iflt \locsize
.error "abi_entry: invalid negative size of locals (\locsize)"
.endif
abi_entry_size \locsize, \callsize
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
.ifgt .locsz - 32760 /* .locsz > 32760 (ENTRY's max range)? */
/* Funky computation to try to have assembler use addmi efficiently if possible: */
entry sp, 0x7F00 + (.locsz & 0xF0)
addi a12, sp, - ((.locsz & -0x100) - 0x7F00)
movsp sp, a12
.else
entry sp, .locsz
.endif
#else
.if .locsz
.ifle .locsz - 128 /* if locsz <= 128 */
addi sp, sp, -.locsz
.if .callsz
s32i a0, sp, .locsz - 4
.endif
.elseif .callsz /* locsz > 128, with calls: */
movi a9, .locsz - 16 /* note: a9 is caller-saved */
addi sp, sp, -16
s32i a0, sp, 12
sub sp, sp, a9
.else /* locsz > 128, no calls: */
movi a9, .locsz
sub sp, sp, a9
.endif /* end */
.endif
#endif
.endm
/*----------------------------------------------------------------------
* abi_return
*
* Generate proper function exit sequence for the current ABI
* (windowed or call0). Takes care of freeing stack space and
* restoring the return PC, if necessary.
* NOTE: This macro MUST be invoked following a corresponding
* abi_entry macro invocation. For call0 ABI in particular,
* all stack and PC restoration are done according to the last
* abi_entry macro invoked before this macro in the assembly file.
*
* Normally this macro takes no arguments. However to allow
* for placing abi_return *before* abi_entry (as must be done
* for some highly optimized assembly), it optionally takes
* exactly the same arguments as abi_entry.
*/
.macro abi_return locsize=-1, callsize=0
.ifge \locsize
abi_entry_size \locsize, \callsize
.endif
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
retw
#else
.if .locsz
.iflt .locsz - 128 /* if locsz < 128 */
.if .callsz
l32i a0, sp, .locsz - 4
.endif
addi sp, sp, .locsz
.elseif .callsz /* locsz >= 128, with calls: */
addi a9, sp, .locsz - 16
l32i a0, a9, 12
addi sp, a9, 16
.else /* locsz >= 128, no calls: */
movi a9, .locsz
add sp, sp, a9
.endif /* end */
.endif
ret
#endif
.endm
/*
* HW erratum fixes.
*/
.macro hw_erratum_487_fix
#if defined XSHAL_ERRATUM_487_FIX
isync
#endif
.endm
#endif /*XTENSA_COREASM_H*/

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/*
* xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
*
* (In previous releases, these were defined in specreg.h, a generated file.
* This file is not generated, ie. it is processor configuration independent.)
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/corebits.h#2 $ */
/*
* Copyright (c) 2005-2011 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_COREBITS_H
#define XTENSA_COREBITS_H
/* EXCCAUSE register fields: */
#define EXCCAUSE_EXCCAUSE_SHIFT 0
#define EXCCAUSE_EXCCAUSE_MASK 0x3F
/* EXCCAUSE register values: */
/*
* General Exception Causes
* (values of EXCCAUSE special register set by general exceptions,
* which vector to the user, kernel, or double-exception vectors).
*/
#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
/* Reserved 10..11 */
#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
/* Reserved 21..23 */
#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
/* Reserved 30..31 */
#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
/* Reserved 40..63 */
/* PS register fields: */
#define PS_WOE_SHIFT 18
#define PS_WOE_MASK 0x00040000
#define PS_WOE PS_WOE_MASK
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_MASK 0x00030000
#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
#define PS_OWB_SHIFT 8
#define PS_OWB_MASK 0x00000F00
#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
#define PS_RING_SHIFT 6
#define PS_RING_MASK 0x000000C0
#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
#define PS_UM_SHIFT 5
#define PS_UM_MASK 0x00000020
#define PS_UM PS_UM_MASK
#define PS_EXCM_SHIFT 4
#define PS_EXCM_MASK 0x00000010
#define PS_EXCM PS_EXCM_MASK
#define PS_INTLEVEL_SHIFT 0
#define PS_INTLEVEL_MASK 0x0000000F
#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
/* Backward compatibility (deprecated): */
#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
#define PS_PROGSTACK_MASK PS_UM_MASK
#define PS_PROG_SHIFT PS_UM_SHIFT
#define PS_PROG_MASK PS_UM_MASK
#define PS_PROG PS_UM
/* DBREAKCn register fields: */
#define DBREAKC_MASK_SHIFT 0
#define DBREAKC_MASK_MASK 0x0000003F
#define DBREAKC_LOADBREAK_SHIFT 30
#define DBREAKC_LOADBREAK_MASK 0x40000000
#define DBREAKC_STOREBREAK_SHIFT 31
#define DBREAKC_STOREBREAK_MASK 0x80000000
/* DEBUGCAUSE register fields: */
#define DEBUGCAUSE_DEBUGINT_SHIFT 5
#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
#define DEBUGCAUSE_BREAKN_SHIFT 4
#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
#define DEBUGCAUSE_BREAK_SHIFT 3
#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
#define DEBUGCAUSE_DBREAK_SHIFT 2
#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
#define DEBUGCAUSE_IBREAK_SHIFT 1
#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
#define DEBUGCAUSE_ICOUNT_SHIFT 0
#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
/* MESR register fields: */
#define MESR_MEME 0x00000001 /* memory error */
#define MESR_MEME_SHIFT 0
#define MESR_DME 0x00000002 /* double memory error */
#define MESR_DME_SHIFT 1
#define MESR_RCE 0x00000010 /* recorded memory error */
#define MESR_RCE_SHIFT 4
#define MESR_LCE
#define MESR_LCE_SHIFT ?
#define MESR_LCE_L
#define MESR_ERRENAB 0x00000100
#define MESR_ERRENAB_SHIFT 8
#define MESR_ERRTEST 0x00000200
#define MESR_ERRTEST_SHIFT 9
#define MESR_DATEXC 0x00000400
#define MESR_DATEXC_SHIFT 10
#define MESR_INSEXC 0x00000800
#define MESR_INSEXC_SHIFT 11
#define MESR_WAYNUM_SHIFT 16
#define MESR_ACCTYPE_SHIFT 20
#define MESR_MEMTYPE_SHIFT 24
#define MESR_ERRTYPE_SHIFT 30
/* MEMCTL register fields: */
#define MEMCTL_SNOOP_EN_SHIFT 1
#define MEMCTL_SNOOP_EN 0x02 /* enable snoop responses (default 0) */
#define MEMCTL_L0IBUF_EN_SHIFT 0
#define MEMCTL_L0IBUF_EN 0x01 /* enable loop instr. buffer (default 1) */
#define MEMCTL_INV_EN_SHIFT 23
#define MEMCTL_INV_EN 0x00800000 /* invalidate cache ways being increased */
#define MEMCTL_DCWU_SHIFT 8
#define MEMCTL_DCWU_BITS 5
#define MEMCTL_DCWA_SHIFT 13
#define MEMCTL_DCWA_BITS 5
#define MEMCTL_ICWU_SHIFT 18
#define MEMCTL_ICWU_BITS 5
#define MEMCTL_DCWU_MASK 0x00001F00 /* Bits 8-12 dcache ways in use */
#define MEMCTL_DCWA_MASK 0x0003E000 /* Bits 13-17 dcache ways allocatable */
#define MEMCTL_ICWU_MASK 0x007C0000 /* Bits 18-22 icache ways in use */
#define MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK)
#define MEMCTL_DCWA_CLR_MASK ~(MEMCTL_DCWA_MASK)
#define MEMCTL_ICWU_CLR_MASK ~(MEMCTL_ICWU_MASK)
#define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
#define MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
#endif /*XTENSA_COREBITS_H*/

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tools/sdk/include/esp32/xtensa/debugfs.h Executable file
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/* Xtensa Debug-FileSystem definitions */
/*
* Copyright (c) 2005-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef __DEBUGFS_H__
#define __DEBUGFS_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <unistd.h>
#include <fcntl.h>
#include <stdlib.h>
int xt_dbfs_open(const char *pathname, int flags, mode_t mode);
int xt_dbfs_ftruncate(int fd, off_t length);
int xt_dbfs_truncate(const char * filename, off_t length);
int xt_dbfs_creat(const char *pathname, mode_t mode);
int xt_dbfs_errno(void);
int xt_dbfs_lseek(int fd, off_t offset, int whence);
ssize_t xt_dbfs_write(int fd, const void * buf, size_t bytes);
ssize_t xt_dbfs_open_append_close(const char * filename, int align,
const void * buf, size_t bytes);
ssize_t xt_dbfs_read(int fd, void * buf, size_t bytes);
int xt_dbfs_close(int fd);
int xt_dbfs_unlink(const char *pathname);
/* By default, this function is a wrapper around sbrk, and follows
sbrk semantics:
On success, it returns increment bytes of memory allocated from
system memory.
On failure, it returns 0xFFFFFFFF
If you want to use a method of allocating memory other than sbrk,
implement xt_dbfs_sbrk in your own sources, and the linker will
automatically use that copy.
*/
void * xt_dbfs_sbrk(int increment);
#ifdef REPLACE_FS_WITH_DBFS
#define open xt_dbfs_open
#define close xt_dbfs_close
#define creat xt_dbfs_creat
#define lseek xt_dbfs_lseek
#define write xt_dbfs_write
#define read xt_dbfs_read
#define close xt_dbfs_close
#define unlink xt_dbfs_unlink
#define rmdir NOT_IMPLEMENTED_IN_DBFS
#define opendir NOT_IMPLEMENTED_IN_DBFS
#define closedir NOT_IMPLEMENTED_IN_DBFS
#define dirfs NOT_IMPLEMENTED_IN_DBFS
#define readdir NOT_IMPLEMENTED_IN_DBFS
#define scandir NOT_IMPLEMENTED_IN_DBFS
#define seekdir NOT_IMPLEMENTED_IN_DBFS
#define telldir NOT_IMPLEMENTED_IN_DBFS
#define fcntl NOT_IMPLEMENTED_IN_DBFS
#define dup2 NOT_IMPLEMENTED_IN_DBFS
#define dup NOT_IMPLEMENTED_IN_DBFS
#define flock NOT_IMPLEMENTED_IN_DBFS
#define lockf NOT_IMPLEMENTED_IN_DBFS
#define link NOT_IMPLEMENTED_IN_DBFS
#define stat NOT_IMPLEMENTED_IN_DBFS
#define fstat NOT_IMPLEMENTED_IN_DBFS
#define lstat NOT_IMPLEMENTED_IN_DBFS
#define chmod NOT_IMPLEMENTED_IN_DBFS
#define fchmod NOT_IMPLEMENTED_IN_DBFS
#define chmown NOT_IMPLEMENTED_IN_DBFS
#define lchown NOT_IMPLEMENTED_IN_DBFS
#define fchown NOT_IMPLEMENTED_IN_DBFS
#endif
#ifdef __cplusplus
}
#endif
#endif

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tools/sdk/include/esp32/xtensa/feedback.h Executable file
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/*
* Copyright (c) 2013 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef __XT_FEEDBACK_INCLUDED__
#define __XT_FEEDBACK_INCLUDED__
#ifdef __cplusplus
extern "C" {
#endif
/* xt_feedback_save_and_reset
Save and reset the accumulated feedback data.
*/
extern void xt_feedback_save_and_reset(void);
/* xt_feedback_enable
Turn on feedback accumulation. Ordinarily, feedback accumulation is on
by default. If you turn it off using xt_feedback_disable, You can turn
it on again via this function.
*/
extern void xt_feedback_enable (void);
/* xt_feedback_disable
Turn off feedback accumulation. If you don't want to gather feedback for a
portion of your code, use this function and then xt_feedback_enable when
you want to start again.
*/
extern void xt_feedback_disable (void);
#ifdef __cplusplus
}
#endif
#endif /* __XT_FEEDBACK_INCLUDED__ */

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tools/sdk/include/esp32/xtensa/gdbio.h Executable file
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/* Xtensa Debug-FileSystem definitions
*
* Copyright (c) 2006-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef __DEBUGFS_H__
#define __DEBUGFS_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <unistd.h>
#include <fcntl.h>
#include <stdlib.h>
#include <errno.h>
int _gdbio_open_r(void * ptr, const char *pathname, int flags, mode_t mode);
int _gdbio_creat_r(void * ptr, const char *pathname, mode_t mode);
int _gdbio_lseek_r(void * ptr, int fd, off_t offset, int whence);
ssize_t _gdbio_write_r(void * ptr, int fd, const void * buf, size_t bytes);
ssize_t _gdbio_read_r(void * ptr, int fd, void * buf, size_t bytes);
int _gdbio_close_r(void * ptr, int fd);
int _gdbio_unlink_r(void * ptr, const char * pathname);
static inline
int gdbio_open(const char *pathname, int flags, mode_t mode) {
return _gdbio_open_r(&errno, pathname, flags, mode);
}
static inline int
gdbio_creat(const char *pathname, mode_t mode) {
return _gdbio_open_r(&errno, pathname, O_CREAT|O_WRONLY|O_TRUNC, mode);
}
static inline int
gdbio_errno(void) {
return errno;
}
static inline int
gdbio_lseek(int fd, off_t offset, int whence) {
return _gdbio_lseek_r(&errno, fd, offset, whence);
}
static inline
ssize_t gdbio_write(int fd, const void * buf, size_t bytes) {
return _gdbio_write_r(&errno, fd, buf, bytes);
}
static inline
ssize_t gdbio_read(int fd, void * buf, size_t bytes) {
return _gdbio_read_r(&errno, fd, buf, bytes);
}
static inline int
gdbio_close(int fd) {
return _gdbio_close_r(&errno, fd);
}
static inline int
gdbio_unlink(const char * pathname) {
return _gdbio_unlink_r(&errno, pathname);
}
#ifdef REPLACE_FS_WITH_GDBIO
#define open gdbio_open
#define close gdbio_close
#define creat gdbio_creat
#define lseek gdbio_lseek
#define write gdbio_write
#define read gdbio_read
#define close gdbio_close
#define unlink gdbio_unlink
#endif
#ifdef __cplusplus
}
#endif
#endif

1024
tools/sdk/include/esp32/xtensa/hal.h Executable file
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tools/sdk/include/esp32/xtensa/jtag-xtensa.h Executable file
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/* Copyright (c) 2011-2012 Tensilica Inc. ALL RIGHTS RESERVED.
// These coded instructions, statements, and computer programs are the
// copyrighted works and confidential proprietary information of Tensilica Inc.
// They may not be modified, copied, reproduced, distributed, or disclosed to
// third parties in any manner, medium, or form, in whole or in part, without
// the prior written consent of Tensilica Inc.
*/
#ifndef _JTAG_XTENSA_H_
#define _JTAG_XTENSA_H_
/* ---------------- JTAG registers ------------------ */
/* -- ER and later JTAG registers */
typedef enum {
regIR,
regBypass,
regNAR,
regNDR,
regIdcode,
regPWRCTL,
regPWRSTAT,
regJtagMAX,
} xtensaJtagReg;
/* -- pre-ER JTAG registers */
typedef enum {
regOldIR,
regOldBypass,
regOldDIRW,
regOldDIR,
regOldDDR,
regOldDOSR,
regOldESR,
regOldDCR,
regOldTraxNDR,
regOldTraxNAR,
regOldMAX
} xtensaOldJtagReg;
/* ---------------- JTAG Instructions ------------------ */
/* -- pre-ER JTAG instructions */
typedef enum {
ji_EnableOCD = 0x11,
ji_DebugInt,
ji_RetDebugInt, // TBD: remove
ji_DisRetOCD, // TBD: remove
ji_ExecuteDI,
ji_LoadDI,
ji_ScanDDR,
ji_ReadDOSR,
ji_ScanDCR,
ji_LoadWDI,
ji_TRAX = 0x1c,
ji_BYPASS = 0x1f,
} xtensaJtagInstruction;
typedef enum {
OCDNormalMode,
OCDRunMode,
OCDHaltMode,
OCDStepMode
} xtensaMode;
typedef struct {
xtensaMode mode;
int DRsel;
XTMP_core core;
XTMP_tap tap;
int core_num;
jtagReg_t *jtagRegs;
void *dap; // used for ARM DAP only
bool isBig;
int dir_array_option; // used by pre-ER devices only
// for testing, below - FIXME - delete later
int ocdReg;
unsigned int wr_data;
XTMP_event start_OCD_trans;
bool data_cycle;
bool data_pending;
} coreSlaveData_t;
enum OCD_ACCESS_TYPE{
NEXUS_ACCESS,
CS_ACCESS,
};
// pre-ER Xtensa initializiation
EXTERN XTMP_deviceStatus
XTMP_jtagCoreSlaveEX(XTMP_component component, XTMP_jtagSlave slave, void* mydata);
extern char *OCDrd;
extern char *OCDwr;
#endif

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tools/sdk/include/esp32/xtensa/lcd-splc780d-4bitmode-board.h Executable file
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/*******************************************************************************
Copyright (c) 2009-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
lcd-splc780d-4bitmode-board.h Board-specific LCD info for these boards:
Avnet AV110 (XT-AV110)
Xilinx ML605 (XT-ML605)
Xilinx KC705 (XT-KC705)
Interface between board-independent driver and board-specific header.
This is used by a board-independent SPLC780D LCD controller (4 bit mode)
driver to obtain board-specific information about LCD displays on the board,
such as the controller register base address and spacing (a function of how
the address lines are connected on the board) and length of the visible window
of the display (a function of the LCD panel the controller drives).
The driver doesnot refer directly to the board-specific header, which therefore is not
constrained to use macro names consistent with other boards.
!! Must not contain any board-specific macro names (only controller specific) !!
Included at compile-time via an include path specific to the board.
The listed boards contain a single MYTech MOC-16216B-B display driven by
a Sunplus SPLC870D controller.
*******************************************************************************/
#ifndef _LCD_SPLC780D_4BIT_BOARD_H
#define _LCD_SPLC780D_4BIT_BOARD_H
#include <xtensa/board.h> /* Board info */
/* Base address of the controller's registers. */
#ifdef SPLC780D_4BIT_VADDR
#define SPLC780D_4BIT_REGBASE SPLC780D_4BIT_VADDR
#endif
/*
The controller's registers are connected at word addresses on these boards.
Each byte-wide register appears as the least-significant-byte (LSB) of the
word regardless of the endianness of the processor (so if using word accesses
then endianness doesn't matter).
*/
#define SPLC780D_4BIT_REGSPACING 4
typedef unsigned splc780d_4bit_reg_t;
/* Include generic information shared by all boards that use this device. */
#include <xtensa/lcd-splc780d-4bitmode.h>
/* Display limits of the LCD panel. */
#define DISPLAY_VISIBLE_LEN 16 /* length (chars) of visible window */
#endif /* _LCD_SPLC780D_4BIT_BOARD_H */

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/*******************************************************************************
Copyright (c) 2009-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
lcd-SPLC780D-4bitmode.h Generic definitions for Sunplus SPLC780D LCD Controller
operating in 4 bit mode.
This is used by board-support-packages with one or more LCD displays that use
a SPLC780D controller in 4 bit mode. A BSP provides a base address for each
instance of an SPLC780D LCD controller on the board.
Note that LCD display operation is almost totally independent of the LCD
display, depending almost entirely on the controller. However the display
may limit the number of characters of the controller's RAM buffer that are
actually visible at one time. The length of the display's visible window
is not specifified in this controller-specific header, but comes to the
driver from the board-specific "display.h" header.
*******************************************************************************/
#ifndef _LCD_SPLC780D_4BIT_H_
#define _LCD_SPLC780D_4BIT_H_
/* Offsets to controller registers from base. */
#define SPLC780D_4BIT_INST 0
#define SPLC780D_4BIT_DATA (SPLC780D_4BIT_INST + SPLC780D_4BIT_REGSPACING)
#define SPLC780D_4BIT_INST_INIT1 0xFF /* First command in
init sequence */
#define SPLC780D_4BIT_INST_INIT2 0x30 /* Second command in
init sequence,
issued 3 times */
#define SPLC780D_4BIT_INST_INIT3 0x20 /* Third and last command
in init sequence */
#define SPLC780D_4BIT_INST_CLEAR 0x01 /* clear (blank) display) */
#define SPLC780D_4BIT_INST_SET_MODE 0x28 /* Set LCD mode. Supported
setting is 4 bit data
length, 2 lines, 5*8 */
#define SPLC780D_4BIT_INST_DSPLY_ON 0x0C /* Set Display ON */
#define SPLC780D_4BIT_INST_CRSR_INC 0x06 /* Set cursor moving direction
as increment */
#define SPLC780D_4BIT_LINET_ADDR 0x80 /* clear (blank) display) */
#define SPLC780D_4BIT_LINEB_ADDR 0xC0 /* clear (blank) display) */
#ifndef __ASSEMBLER__
/* C interface to controller registers. */
struct splc780d_4bit_s {
splc780d_4bit_reg_t inst; /* instruction register */
splc780d_4bit_reg_t data; /* data register */
};
typedef volatile struct splc780d_4bit_s splc780d_4bit_t;
/*
Prototypes of high level driver functions.
*/
/* Write an instruction byte to LCD, result in two back to back writes since the
* LCD is hooked up in 4 bit mode*/
extern void lcd_write_inst_byte(splc780d_4bit_t *lcd, unsigned char inst);
/* Write a data byte to LCD, result in two back to back writes since the
* LCD is hooked up in 4 bit mode*/
extern void lcd_write_data_byte(splc780d_4bit_t *lcd, unsigned char data);
/*
Initialize the display with default settings.
*/
extern void splc780d_4bit_init_default(splc780d_4bit_t *lcd);
/*
Write a single character at a given position (chars from left, starting at 0).
Wait long enough afterward for the controller to be ready for more input.
Positions beyond the end of the display are ignored.
*/
extern void splc780d_4bit_write_char(splc780d_4bit_t *lcd, unsigned pos, const char c);
/*
Write a string to the display starting at the left (position 0).
Blank-pad to or truncate at the end of the display (overwrites any previous
string so don't need to blank the display first).
Wait long enough after each char for the controller to be ready for more input.
*/
extern void splc780d_4bit_write_string(splc780d_4bit_t *lcd, const char *s);
/*
Blank (clear) the entire display.
Wait long enough afterward for the controller to be ready for more input.
*/
extern void splc780d_4bit_blank(splc780d_4bit_t *lcd);
#endif /* __ASSEMBLER__ */
#endif /* _LCD_SPLC780D_4BIT_H_ */

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/*******************************************************************************
Copyright (c) 2006-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
lcd-SPLC780D.h Generic definitions for Sunplus SPLC780D LCD Controller
This is used by board-support-packages with one or more LCD displays that use
a SPLC780D controller. A BSP provides a base address for each instance of an
SPLC780D LCD controller on the board.
Note that LCD display operation is almost totally independent of the LCD
display, depending almost entirely on the controller. However the display
may limit the number of characters of the controller's RAM buffer that are
actually visible at one time. The length of the display's visible window
is not specifified in this controller-specific header, but comes to the
driver from the board-specific "display.h" header.
*******************************************************************************/
#ifndef _LCD_SPLC780D_H_
#define _LCD_SPLC780D_H_
/* Offsets to controller registers from base. */
#define SPLC780D_INST 0
#define SPLC780D_DATA (SPLC780D_INST + SPLC780D_REGSPACING)
/*
Bit fields and their values in the instruction register.
These fields are NOT orthogonal - they overlap!
Thus only one field may be written at a time, determined by the
most-significant 1 bit in the pattern (the field selector).
All less significant bits are part of the value of the selected field.
The fields and their values are grouped together to emphasize this format.
Field selector macro names end in '_' (implying something more needs
to be ORed) and the value macros are indented. The pattern written to a
bitfield is a bitwise OR of a field selector and one or more values, eg.
(SPLC780D_INST_ON_ | SPLC780D_INST_ON_DISPLAY | SPLC780D_INST_ON_CURSOR)
A single bit field (eg. SPCL780D_INST_HOME) need not have a value.
NOTE: Controller requires a software delay after writing to the control
or data registers. For the data register it is 38us. For the control
register it is 38us for most bit fields, with the following exceptions:
SPLC780D_FUNC_ 100us.
SPLC780D_INST_CLEAR, SPLC780D_INST_HOME 1520us.
For more details and reset timing, see the SUNPLUS SPLC780D data sheet.
*/
#define SPLC780D_INST_CLEAR_ 0x1 /* clear (blank) display) */
#define SPLC780D_INST_HOME_ 0x2 /* home cursor and shift pos */
#define SPLC780D_INST_ENTRY_ 0x4 /* combine *ENTRY_* flags below */
#define SPLC780D_INST_ENTRY_SHIFT 0x1 /* display shift on entry / not */
#define SPLC780D_INST_ENTRY_INCR 0x2 /* cursor incr / decr */
#define SPLC780D_INST_ENTRY_DECR 0 /* cursor incr / decr */
#define SPLC780D_INST_ON_ 0x8 /* combine *ON_* flags below */
#define SPLC780D_INST_ON_DISPLAY 0x4 /* display on / off */
#define SPLC780D_INST_ON_CURSOR 0x2 /* cursor on / off */
#define SPLC780D_INST_ON_BLINK 0x1 /* blink on / off */
#define SPLC780D_INST_SHIFT_ 0x10 /* combine *SHIFT_* flags below */
#define SPLC780D_INST_SHIFT_DISP 0x8 /* shift display / move cursor */
#define SPLC780D_INST_SHIFT_CURS 0 /* shift display / move cursor */
#define SPLC780D_INST_SHIFT_RIGHT 0x4 /* shift right / left */
#define SPLC780D_INST_SHIFT_LEFT 0 /* shift right / left */
#define SPLC780D_INST_FUNC_ 0x20 /* combine *FUNC_* flags below */
#define SPLC780D_INST_FUNC_8BIT 0x10 /* data length 8 bit / 4 bit */
#define SPLC780D_INST_FUNC_4BIT 0 /* data length 8 bit / 4 bit */
#define SPLC780D_INST_FUNC_2LINE 0x08 /* display lines 2 / 1 */
#define SPLC780D_INST_FUNC_1LINE 0 /* display lines 2 / 1 */
#define SPLC780D_INST_FUNC_F5x10 0x04 /* character font 5x10 / 5x8 */
#define SPLC780D_INST_FUNC_F5x8 0 /* character font 5x10 / 5x8 */
/* font must be 5x8 for 2 lines */
#define SPLC780D_INST_CGEN_ 0x40 /* set char generator address */
#define SPLC780D_INST_CGEN_ADDR 0x3F /* to address in this field */
#define SPLC780D_INST_DRAM_ 0x80 /* set display data RAM address */
#define SPLC780D_INST_DRAM_ADDR 0x7F /* to address in this field */
#define SPLC780D_INST_DRAM_LINE2 0x40 /* address offset to line 2 */
/* Controller limits */
#define SPLC780D_RAMLEN_1LINE 0x50 /* length of line in RAM (1 line) */
#define SPLC780D_RAMLEN_2LINE 0x28 /* length of line in RAM (2 line) */
#ifndef __ASSEMBLER__
/* C interface to controller registers. */
struct splc780d_s {
splc780d_reg_t inst; /* instruction register */
splc780d_reg_t data; /* data register */
};
typedef volatile struct splc780d_s splc780d_t;
/*
Prototypes of high level driver functions.
*/
/*
Initialize the display with the FUNC_, ENTRY_ and ON_ fields as specified in
terms of the values above. The splc780d_init_default() macro is an example.
*/
extern void splc780d_init(splc780d_t *lcd,
unsigned func, unsigned entry, unsigned on);
/*
Initialize the display to default mode: 8-bit interface, 2 line, 5x8 font,
increment cursor on entry, display on (cursor and blinking off).
*/
#define splc780d_init_default(lcd) \
splc780d_init( lcd, \
SPLC780D_INST_FUNC_8BIT \
| SPLC780D_INST_FUNC_2LINE \
| SPLC780D_INST_FUNC_F5x8, \
SPLC780D_INST_ENTRY_INCR, \
SPLC780D_INST_ON_DISPLAY \
)
/*
Write a single character at a given position (chars from left, starting at 0).
Wait long enough afterward for the controller to be ready for more input.
Positions beyond the end of the display are ignored.
*/
extern void splc780d_write_char(splc780d_t *lcd, unsigned pos, const char c);
/*
Write a string to the display starting at the left (position 0).
Blank-pad to or truncate at the end of the display (overwrites any previous
string so don't need to blank the display first).
Wait long enough after each char for the controller to be ready for more input.
*/
extern void splc780d_write_string(splc780d_t *lcd, const char *s);
/*
Blank (clear) the entire display.
Wait long enough afterward for the controller to be ready for more input.
*/
extern void splc780d_blank(splc780d_t *lcd);
#endif /* __ASSEMBLER__ */
#endif /* _LCD_SPLC780D_H_ */

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tools/sdk/include/esp32/xtensa/overlay.h Executable file
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// overlay.h -- Overlay manager header file
// $Id$
// Copyright (c) 2013 Tensilica Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef OVERLAY_H
#define OVERLAY_H
#include <xtensa/xtruntime.h>
#ifdef __cplusplus
extern "C" {
#endif
// Define this to turn off overlay support
#ifdef XT_DISABLE_OVERLAYS
#define OVERLAY(n)
#define DECLARE_OVERLAY(n)
#define xt_overlay_map(ov_id)
#define xt_overlay_map_async(ov_id) 0
#define xt_overlay_map_in_progress() 0
#define xt_overlay_get_id() 0
#define xt_overlay_get_state(pc) 0
#define xt_overlay_check_map(pc,ps,ovstate,sp) 0
#else
// Shorthand for convenience and portability.
#define OVERLAY(n) __attribute__((overlay(n)))
// Structure of the overlay table required by gdb and the overlay
// manager. Should not be accessed by user code unless overriding
// the load process.
struct ovly_table {
void * vma; // The overlay's mapped address.
unsigned int size; // The size of the overlay, in bytes.
void * lma; // The overlay's load address.
unsigned int mapped; // Non-zero if overlay is currently mapped; zero otherwise.
};
// Constructed by the linker. Required for gdb and for the overlay
// manager. Should not be accessed by user code unless overriding
// the load process.
extern struct ovly_table _ovly_table[];
// Functions.
void xt_overlay_map(int ov_id);
int xt_overlay_map_async(int ov_id);
int xt_overlay_map_in_progress(void);
unsigned int xt_overlay_get_state(unsigned int pc);
unsigned int xt_overlay_check_map(unsigned int * pc, unsigned int * ps,
unsigned int ovstate, unsigned int sp);
int xt_overlay_start_map(void * dst, void * src, unsigned int len, int ov_id);
int xt_overlay_is_mapping(int ov_id);
void xt_overlay_fatal_error(int ov_id);
// Returns the current overlay ID. If no overlay is mapped or an overlay
// is in the middle of being mapped, returns -1. Inlined to avoid calling
// out of overlay (wastes cycles, can end up reading wrong ID on interrupt
// activity).
//
static inline int xt_overlay_get_id(void)
{
#pragma always_inline
extern short _mapping_id;
extern short _ovly_id;
int ret;
unsigned int flags = XTOS_SET_INTLEVEL(15);
if (_mapping_id >= 0) {
ret = -1;
}
else {
ret = _ovly_id;
}
XTOS_RESTORE_INTLEVEL(flags);
return ret;
}
// The following macros are used to declare numbered overlays and generate
// the corresponding call stubs. Use as follows:
//
// DECLARE_OVERLAY(n)
//
// See documentation for more details.
//#include <xtensa/config/core-isa.h>
// At this time overlays are not supported without windowing.
#if defined(__XTENSA_WINDOWED_ABI__)
#define xstr(x) str(x)
#define str(x) #x
// At entry, register a8 holds the return address and a9 holds the target
// function address. This stub saves a8 on the stack at (SP - 20) which
// is the only location that is safe for us to use. Then it allocates 32
// bytes on the stack for working storage, loads the overlay number into
// a8, and jumps to the common handler. The common handler will make sure
// that the called function is loaded into memory before calling it.
// NOTE: we are using the stack area normally reserved for nested functions.
// This means nested functions cannot be used when overlays are in use.
#define CALL_IN(num) \
asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \
".global _overlay_call_in_" xstr(num) "_\n" \
".align 4\n" \
"_overlay_call_in_" xstr(num) "_:\n" \
"s32e a8, a1, -20\n" \
"addi a8, a1, -32\n" \
"movsp a1, a8\n" \
"movi a8, " xstr(num) "\n" \
"j _overlay_call_in_common\n" \
".size _overlay_call_in_" xstr(num) "_, . - _overlay_call_in_" xstr(num) "_\n");
// The call-out stub first calls the target function, then loads the overlay
// number into register a14 and jumps to the common handler. The handler will
// make sure that the caller function is present in memory before returning.
// Note that registers a10-a13 may contain return values so must be preserved.
//
// Because we came here via a call4, the return address is in a4, and the top
// 2 bits are set to the window increment. We'll restore the top 2 bits of
// the return address from the called function's address, assuming that both
// are in the same 1 GB segment. For now this is always true.
#define CALL_OUT(num) \
asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \
".global _overlay_call_out_" xstr(num) "_\n" \
".align 4\n" \
"_overlay_call_out_" xstr(num) "_:\n" \
"slli a4, a4, 2\n" \
"srli a4, a4, 2\n" \
"extui a8, a9, 30, 2\n" \
"slli a8, a8, 30\n" \
"or a4, a4, a8\n" \
"callx8 a9\n" \
"movi a14, " xstr(num) "\n" \
"j _overlay_call_out_common\n" \
".size _overlay_call_out_" xstr(num) "_, . - _overlay_call_out_" xstr(num) "_\n");
// Generate a call-in and a call-out stub for each overlay.
#define DECLARE_OVERLAY(num) \
CALL_IN(num) \
CALL_OUT(num)
#endif // defined(__XTENSA_WINDOWED_ABI__)
#endif // XT_DISABLE_OVERLAYS
#ifdef __cplusplus
}
#endif
#endif // OVERLAY_H

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// overlay_os_asm.h -- Overlay manager assembly macros for OS use.
// $Id$
// Copyright (c) 2013 Tensilica Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef OVERLAY_OS_ASM_H
#define OVERLAY_OS_ASM_H
// The macros in here are intended to be used by RTOS task switch code
// to check overlay status. Such code is usually in assembly and cannot
// call C code without penalty. For C code usage, it is best to use the
// corresponding C functions from the library.
// Inline assembly version of xt_overlay_get_state(). The arguments are
// three AR registers (a0-a15):
//
// "pcreg" - should contain the outgoing task's PC, i.e. the point at
// which the task got interrupted. The return value is also
// returned in this register.
// "sr1/2" - Scratch registers. These must be distinct from "pcreg".
//
// The return value is a 32-bit result that should be saved with the
// task context and passed as-is to xt_overlay_check_map.
.macro _xt_overlay_get_state pcreg sr1 sr2
movi \sr1, _mapping_id
movi \sr2, _ovly_id
l16si \sr1, \sr1, 0
l16ui \sr2, \sr2, 0
slli \sr1, \sr1, 16
or \pcreg, \sr1, \sr2
.endm
// Inline assembly version of xt_overlay_check_map(). It requires 5 AR
// registers (a0-a15) as arguments.
//
// "pcreg" - should contain the interrupted task's PC, i.e. the point
// at which the task got interrupted. This will be adjusted
// if required.
// "psreg" - should contain the interrupted task's PS. This will be
// adjusted if required.
// "ovreg" - should contain the overlay state on entry. Contents may
// be clobbered.
// "spreg" - should contain the tasks stack pointer on entry.
// "sr1" - Scratch register. Must be distinct from any of the above.
//
// The return values are "pcreg" and "psreg" and these must be used
// to update the task's PC and PS.
// Note that this macro may store data below the "spreg" pointer. If
// it does, then it will also disable interrupts via the PS, so that
// the task resumes with all interrupts disabled (to avoid corrupting
// this data).
//
// (SP - 24) Overlay ID to restore
// (SP - 28) Task PC
// (SP - 32) Task PS
.macro _xt_overlay_check_map pcreg psreg ovreg spreg sr1
// There are four cases to deal with:
//
// _ovly_id = -1, _mapping_id = -1
// No overlay is mapped or mapping, nothing to do.
//
// _ovly_id >= 0, _mapping_id = -1
// An overlay was mapped, check PC to see if we need a restore.
//
// _ovly_id = -1, _mapping_id >= 0
// An overlay is being mapped. Either it belongs to this task, which
// implies that the PC is in the mapping function, or it does not
// belong to this task. Either way there is nothing to do.
//
// _ovly_id >= 0, _mapping_id >= 0
// Illegal, cannot happen by design. Don't need to handle this.
//
// So, the logic is to check _ovly_id first. If this is >= 0, then
// we check the task PC. If the PC is in the regions of interest then
// we'll patch the return PC to invoke xt_overlay_restore.
.L1:
extui \sr1, \ovreg, 0, 16 // Extract _ovly_id
bbsi.l \sr1, 15, .Lno // If -1 then we're done
mov \ovreg, \sr1 // Restore this one
// Next check the PC to see if it falls within the ranges of interest.
.L2:
movi \sr1, _overlay_vma // Is PC < VMA range ?
bltu \pcreg, \sr1, .L3
movi \sr1, _overlay_vma_end // Is PC > VMA range ?
bgeu \pcreg, \sr1, .L3
j .L4 // PC is in VMA range
.L3:
movi \sr1, _overlay_call_stubs_start // Is PC < call stubs range ?
bltu \pcreg, \sr1, .Lno
movi \sr1, _overlay_call_stubs_end // Is PC > call stubs range ?
bgeu \pcreg, \sr1, .Lno
// If we get here then a restore is needed. Save the overlay ID, PC and PS.
// Return modified PC and PS so that xt_overlay_restore() will execute in
// the context of the task when resumed. Note that the OS resumption code
// may expect PS.EXCM to be set so we leave it as is in the return value.
.L4:
s32e \ovreg, \spreg, -24 // Save overlay ID
s32e \pcreg, \spreg, -28 // Save task PC
s32e \psreg, \spreg, -32 // Save task PS
movi \pcreg, xt_overlay_restore // Adjust resumption PC
movi \sr1, 15
or \psreg, \psreg, \sr1 // Set intlevel to highest
.Lno:
.endm
#endif // OVERLAY_OS_ASM_H

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tools/sdk/include/esp32/xtensa/sim.h Executable file
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/* Copyright (c) 2004-2006 by Tensilica Inc. ALL RIGHTS RESERVED.
/ These coded instructions, statements, and computer programs are the
/ copyrighted works and confidential proprietary information of Tensilica Inc.
/ They may not be modified, copied, reproduced, distributed, or disclosed to
/ third parties in any manner, medium, or form, in whole or in part, without
/ the prior written consent of Tensilica Inc.
*/
/* sim.h
*
* Definitions and prototypes for specific ISS SIMCALLs
* (ie. outside the standard C library).
*/
#ifndef _INC_SIM_H_
#define _INC_SIM_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Shortcuts for enabling/disabling profiling in the Xtensa ISS */
extern void xt_iss_profile_enable(void);
extern void xt_iss_profile_disable(void);
/* Shortcut for setting the trace level in the Xtensa ISS */
extern void xt_iss_trace_level(unsigned level);
/* Generic interface for passing client commands in the Xtensa ISS:
* returns 0 on success, -1 on failure.
*/
extern int xt_iss_client_command(const char *client, const char *command);
/* Interface for switching simulation modes in the Xtensa ISS:
* returns 0 on success, -1 on failure.
*/
#define XT_ISS_CYCLE_ACCURATE 0
#define XT_ISS_FUNCTIONAL 1
extern int xt_iss_switch_mode(int mode);
/* Interface for waiting on a system synchronization event */
extern void xt_iss_event_wait(unsigned event_id);
/* Interface for firing a system synchronization event */
extern void xt_iss_event_fire(unsigned event_id);
/* Interface for invoking a user simcall action,
* which can be registered in XTMP or XTSC.
*/
extern int xt_iss_simcall(int arg1, int arg2, int arg3,
int arg4, int arg5, int arg6);
#ifdef __cplusplus
}
#endif
#endif /*_INC_SIM_H_*/

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tools/sdk/include/esp32/xtensa/simboard.h Executable file
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/*
* Copyright (c) 2001 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* simboard.h - Xtensa ISS "Board" specific definitions */
#ifndef _INC_SIMBOARD_H_
#define _INC_SIMBOARD_H_
#include <xtensa/config/core.h>
#include <xtensa/config/system.h>
/*
* Device addresses.
*/
/* System ROM: */
#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
#ifdef XSHAL_ROM_VADDR
#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
#endif
#ifdef XSHAL_ROM_PADDR
#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
#endif
/* System RAM: */
#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
#ifdef XSHAL_RAM_VADDR
#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
#endif
#ifdef XSHAL_RAM_PADDR
#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
#endif
/*
* Things that depend on device addresses.
*/
#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_ISS_CACHEATTR_WRITEBACK
#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_ISS_CACHEATTR_WRITEALLOC
#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_ISS_CACHEATTR_WRITETHRU
#define XTBOARD_CACHEATTR_BYPASS XSHAL_ISS_CACHEATTR_BYPASS
#define XTBOARD_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_DEFAULT
#define XTBOARD_BUSINT_PIPE_REGIONS 0
#define XTBOARD_BUSINT_SDRAM_REGIONS 0
#endif /*_INC_SIMBOARD_H_*/

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/* Error numbers for Xtensa ISS semihosting. */
/* Copyright (c) 2003 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc. */
#ifndef _SIMCALL_ERRNO_H
#define _SIMCALL_ERRNO_H
/* Define the error numbers (using the default newlib values) with prefixes
so they can be used in ISS without conflicting with the host values. */
#define _SIMC_EPERM 1
#define _SIMC_ENOENT 2
#define _SIMC_ESRCH 3
#define _SIMC_EINTR 4
#define _SIMC_EIO 5
#define _SIMC_ENXIO 6
#define _SIMC_E2BIG 7
#define _SIMC_ENOEXEC 8
#define _SIMC_EBADF 9
#define _SIMC_ECHILD 10
#define _SIMC_EAGAIN 11
#define _SIMC_ENOMEM 12
#define _SIMC_EACCES 13
#define _SIMC_EFAULT 14
#define _SIMC_ENOTBLK 15
#define _SIMC_EBUSY 16
#define _SIMC_EEXIST 17
#define _SIMC_EXDEV 18
#define _SIMC_ENODEV 19
#define _SIMC_ENOTDIR 20
#define _SIMC_EISDIR 21
#define _SIMC_EINVAL 22
#define _SIMC_ENFILE 23
#define _SIMC_EMFILE 24
#define _SIMC_ENOTTY 25
#define _SIMC_ETXTBSY 26
#define _SIMC_EFBIG 27
#define _SIMC_ENOSPC 28
#define _SIMC_ESPIPE 29
#define _SIMC_EROFS 30
#define _SIMC_EMLINK 31
#define _SIMC_EPIPE 32
#define _SIMC_EDOM 33
#define _SIMC_ERANGE 34
#define _SIMC_ENOMSG 35
#define _SIMC_EIDRM 36
#define _SIMC_ECHRNG 37
#define _SIMC_EL2NSYNC 38
#define _SIMC_EL3HLT 39
#define _SIMC_EL3RST 40
#define _SIMC_ELNRNG 41
#define _SIMC_EUNATCH 42
#define _SIMC_ENOCSI 43
#define _SIMC_EL2HLT 44
#define _SIMC_EDEADLK 45
#define _SIMC_ENOLCK 46
#define _SIMC_EBADE 50
#define _SIMC_EBADR 51
#define _SIMC_EXFULL 52
#define _SIMC_ENOANO 53
#define _SIMC_EBADRQC 54
#define _SIMC_EBADSLT 55
#define _SIMC_EDEADLOCK 56
#define _SIMC_EBFONT 57
#define _SIMC_ENOSTR 60
#define _SIMC_ENODATA 61
#define _SIMC_ETIME 62
#define _SIMC_ENOSR 63
#define _SIMC_ENONET 64
#define _SIMC_ENOPKG 65
#define _SIMC_EREMOTE 66
#define _SIMC_ENOLINK 67
#define _SIMC_EADV 68
#define _SIMC_ESRMNT 69
#define _SIMC_ECOMM 70
#define _SIMC_EPROTO 71
#define _SIMC_EMULTIHOP 74
#define _SIMC_ELBIN 75
#define _SIMC_EDOTDOT 76
#define _SIMC_EBADMSG 77
#define _SIMC_EFTYPE 79
#define _SIMC_ENOTUNIQ 80
#define _SIMC_EBADFD 81
#define _SIMC_EREMCHG 82
#define _SIMC_ELIBACC 83
#define _SIMC_ELIBBAD 84
#define _SIMC_ELIBSCN 85
#define _SIMC_ELIBMAX 86
#define _SIMC_ELIBEXEC 87
#define _SIMC_ENOSYS 88
#define _SIMC_ENMFILE 89
#define _SIMC_ENOTEMPTY 90
#define _SIMC_ENAMETOOLONG 91
#define _SIMC_ELOOP 92
#define _SIMC_EOPNOTSUPP 95
#define _SIMC_EPFNOSUPPORT 96
#define _SIMC_ECONNRESET 104
#define _SIMC_ENOBUFS 105
#define _SIMC_EAFNOSUPPORT 106
#define _SIMC_EPROTOTYPE 107
#define _SIMC_ENOTSOCK 108
#define _SIMC_ENOPROTOOPT 109
#define _SIMC_ESHUTDOWN 110
#define _SIMC_ECONNREFUSED 111
#define _SIMC_EADDRINUSE 112
#define _SIMC_ECONNABORTED 113
#define _SIMC_ENETUNREACH 114
#define _SIMC_ENETDOWN 115
#define _SIMC_ETIMEDOUT 116
#define _SIMC_EHOSTDOWN 117
#define _SIMC_EHOSTUNREACH 118
#define _SIMC_EINPROGRESS 119
#define _SIMC_EALREADY 120
#define _SIMC_EDESTADDRREQ 121
#define _SIMC_EMSGSIZE 122
#define _SIMC_EPROTONOSUPPORT 123
#define _SIMC_ESOCKTNOSUPPORT 124
#define _SIMC_EADDRNOTAVAIL 125
#define _SIMC_ENETRESET 126
#define _SIMC_EISCONN 127
#define _SIMC_ENOTCONN 128
#define _SIMC_ETOOMANYREFS 129
#define _SIMC_EPROCLIM 130
#define _SIMC_EUSERS 131
#define _SIMC_EDQUOT 132
#define _SIMC_ESTALE 133
#define _SIMC_ENOTSUP 134
#define _SIMC_ENOMEDIUM 135
#define _SIMC_ENOSHARE 136
#define _SIMC_ECASECLASH 137
#define _SIMC_EILSEQ 138
#define _SIMC_EOVERFLOW 139
#endif /* ! _SIMCALL_ERRNO_H */

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tools/sdk/include/esp32/xtensa/simcall-fcntl.h Executable file
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/* File control operations for Xtensa ISS semihosting. */
/* Copyright (c) 2003 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc. */
#ifndef _SIMCALL_FCNTL_H
#define _SIMCALL_FCNTL_H
#define _SIMC_O_APPEND 0x0008
#define _SIMC_O_NONBLOCK 0x0080
#define _SIMC_O_CREAT 0x0100
#define _SIMC_O_TRUNC 0x0200
#define _SIMC_O_EXCL 0x0400
#define _SIMC_O_TEXT 0x4000
#define _SIMC_O_BINARY 0x8000
#endif /* ! _SIMCALL_FCNTL_H */

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tools/sdk/include/esp32/xtensa/simcall.h Executable file
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/*
* simcall.h - Simulator call numbers
*
* Software that runs on a simulated Xtensa processor using
* the instruction set simulator (ISS) can invoke simulator
* services using the SIMCALL instruction. The a2 register
* is set prior to executing SIMCALL to a "simcall number",
* indicating which service to invoke. This file defines the
* simcall numbers defined and/or supported by the Xtensa ISS.
*
* IMPORTANT NOTE: These numbers are highly subject to change!
*
* Copyright (c) 2002-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef SIMCALL_INCLUDED
#define SIMCALL_INCLUDED
/*
* System call like services offered by the simulator host.
* These are modeled after the Linux 2.4 kernel system calls
* for Xtensa processors. However not all system calls and
* not all functionality of a given system call are implemented,
* or necessarily have well defined or equivalent semantics in
* the context of a simulation (as opposed to a Unix kernel).
*
* These services behave largely as if they had been invoked
* as a task in the simulator host's operating system
* (eg. files accessed are those of the simulator host).
* However, these SIMCALLs model a virtual operating system
* so that various definitions, bit assignments etc
* (eg. open mode bits, errno values, etc) are independent
* of the host operating system used to run the simulation.
* Rather these definitions are specific to the Xtensa ISS.
* This way Xtensa ISA code written to use these SIMCALLs
* can (in principle) be simulated on any host.
*
* Up to 6 parameters are passed in registers a3 to a8
* (note the 6th parameter isn't passed on the stack,
* unlike windowed function calling conventions).
* The return value is in a2. A negative value in the
* range -4096 to -1 indicates a negated error code to be
* reported in errno with a return value of -1, otherwise
* the value in a2 is returned as is.
*/
/* These #defines need to match what's in Xtensa/OS/vxworks/xtiss/simcalls.c */
#define SYS_nop 0 /* n/a - setup; used to flush register windows */
#define SYS_exit 1 /*x*/
#define SYS_fork 2
#define SYS_read 3 /*x*/
#define SYS_write 4 /*x*/
#define SYS_open 5 /*x*/
#define SYS_close 6 /*x*/
#define SYS_rename 7 /*x 38 - waitpid */
#define SYS_creat 8 /*x*/
#define SYS_link 9 /*x (not implemented on WIN32) */
#define SYS_unlink 10 /*x*/
#define SYS_execv 11 /* n/a - execve */
#define SYS_execve 12 /* 11 - chdir */
#define SYS_pipe 13 /* 42 - time */
#define SYS_stat 14 /* 106 - mknod */
#define SYS_chmod 15
#define SYS_chown 16 /* 202 - lchown */
#define SYS_utime 17 /* 30 - break */
#define SYS_wait 18 /* n/a - oldstat */
#define SYS_lseek 19 /*x*/
#define SYS_getpid 20
#define SYS_isatty 21 /* n/a - mount */
#define SYS_fstat 22 /* 108 - oldumount */
#define SYS_time 23 /* 13 - setuid */
#define SYS_gettimeofday 24 /*x 78 - getuid (not implemented on WIN32) */
#define SYS_times 25 /*X 43 - stime (Xtensa-specific implementation) */
#define SYS_socket 26
#define SYS_sendto 27
#define SYS_recvfrom 28
#define SYS_select_one 29 /* not compitible select, one file descriptor at the time */
#define SYS_bind 30
#define SYS_ioctl 31
/*
* Other...
*/
#define SYS_iss_argc 1000 /* returns value of argc */
#define SYS_iss_argv_size 1001 /* bytes needed for argv & arg strings */
#define SYS_iss_set_argv 1002 /* saves argv & arg strings at given addr */
#define SYS_memset 1004 /* fill a range of memory (fast) */
/*
* SIMCALLs for the ferret memory debugger. All are invoked by
* libferret.a ... ( Xtensa/Target-Libs/ferret )
*/
#define SYS_ferret 1010
#define SYS_malloc 1011
#define SYS_free 1012
#define SYS_more_heap 1013
#define SYS_no_heap 1014
#define SYS_enter_ferret 1015
#define SYS_leave_ferret 1016
/*
* SIMCALLs for ISS client commands
*/
#define SYS_profile_enable 1020
#define SYS_profile_disable 1021
#define SYS_trace_level 1022
#define SYS_client_command 1023
/*
* SIMCALL for simulation mode switching
*/
#define SYS_sim_mode_switch 1030
/*
* SIMCALLs for XTMP/XTSC event notify and core stall
*/
#define SYS_event_fire 1040
#define SYS_event_stall 1041
/*
* SIMCALLs for callbacks registered in XTMP/XTSC
*/
#define SYS_callback_first 100
#define SYS_callback_last 999
/*
* User defined simcall
*/
#define SYS_user_simcall 100
#define SYS_xmpa_errinfo 200
#define SYS_xmpa_proc_status 201
#define SYS_xmpa_proc_start 202
#define SYS_xmpa_proc_stop 203
#define SYS_xmpa_proc_mem_read 204
#define SYS_xmpa_proc_mem_write 205
#define SYS_xmpa_proc_mem_fill 206
#define SYS_xmpa_proc_reg_read 207
#define SYS_xmpa_proc_reg_write 208
/*
* Extra SIMCALLs for GDB:
*/
#define SYS_gdb_break -1 /* invoked by XTOS on user exceptions if EPC points
to a break.n/break, regardless of cause! */
#define SYS_xmon_out -2 /* invoked by XMON: ... */
#define SYS_xmon_in -3 /* invoked by XMON: ... */
#define SYS_xmon_flush -4 /* invoked by XMON: ... */
#define SYS_gdb_abort -5 /* invoked by XTOS in _xtos_panic() */
#define SYS_gdb_illegal_inst -6 /* invoked by XTOS for illegal instructions (too deeply) */
#define SYS_xmon_init -7 /* invoked by XMON: ... */
#define SYS_gdb_enter_sktloop -8 /* invoked by XTOS on debug exceptions */
#define SYS_unhandled_kernel_exc -9 /* invoked by XTOS for unhandled kernel exceptions */
#define SYS_unhandled_user_exc -10 /* invoked by XTOS for unhandled user exceptions */
#define SYS_unhandled_double_exc -11 /* invoked by XTOS for unhandled double exceptions */
#define SYS_unhandled_highpri_interrupt -12 /* invoked by XTOS for unhandled high-priority interrupts */
#define SYS_xmon_close -13 /* invoked by XMON: ... */
/*
* SIMCALLs for vxWorks xtiss BSP:
*/
#define SYS_setup_ppp_pipes -83
#define SYS_log_msg -84
/*
* SYS_select_one specifiers
*/
#define XTISS_SELECT_ONE_READ 1
#define XTISS_SELECT_ONE_WRITE 2
#define XTISS_SELECT_ONE_EXCEPT 3
/*
* SIMCALL for client calling arbitrary code in a client plug in.
* see clients/xcc_instr to see how this works.
*/
#define SYS_client 0xC0DECAFE
#endif /* !SIMCALL_INCLUDED */

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tools/sdk/include/esp32/xtensa/specreg.h Executable file
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/*
* Xtensa Special Register symbolic names
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/specreg.h#2 $ */
/*
* Copyright (c) 2005-2011 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define LITBASE 5
#define SCOMPARE1 12
#define ACCLO 16
#define ACCHI 17
#define MR_0 32
#define MR_1 33
#define MR_2 34
#define MR_3 35
#define PREFCTL 40
#define WINDOWBASE 72
#define WINDOWSTART 73
#define PTEVADDR 83
#define RASID 90
#define ITLBCFG 91
#define DTLBCFG 92
#define IBREAKENABLE 96
#define MEMCTL 97
#define CACHEATTR 98
#define ATOMCTL 99
#define DDR 104
#define MECR 110
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define CONFIGID0 176
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define EPC_5 181
#define EPC_6 182
#define EPC_7 183
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EPS_5 197
#define EPS_6 198
#define EPS_7 199
#define CONFIGID1 208
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define EXCSAVE_5 213
#define EXCSAVE_6 214
#define EXCSAVE_7 215
#define CPENABLE 224
#define INTERRUPT 226
#define INTREAD INTERRUPT /* alternate name for backward compatibility */
#define INTSET INTERRUPT /* alternate name for backward compatibility */
#define INTCLEAR 227
#define INTENABLE 228
#define PS 230
#define VECBASE 231
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
#define MISC_REG_2 246
#define MISC_REG_3 247
/* Special cases (bases of special register series): */
#define MR 32
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
#define MISC_REG 244
/* Tensilica-defined user registers: */
#if 0
/*#define ... 21..24 */ /* (545CK) */
/*#define ... 140..143 */ /* (545CK) */
#define EXPSTATE 230 /* Diamond */
#define THREADPTR 231 /* threadptr option */
#define FCR 232 /* FPU */
#define FSR 233 /* FPU */
#define AE_OVF_SAR 240 /* HiFi2 */
#define AE_BITHEAD 241 /* HiFi2 */
#define AE_TS_FTS_BU_BP 242 /* HiFi2 */
#define AE_SD_NO 243 /* HiFi2 */
#define VSAR 240 /* VectraLX */
#define ROUND_LO 242 /* VectraLX */
#define ROUND_HI 243 /* VectraLX */
#define CBEGIN 246 /* VectraLX */
#define CEND 247 /* VectraLX */
#endif
#endif /* XTENSA_SPECREG_H */

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