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initial import
This commit is contained in:
me-no-dev
committed by
Ivan Grokhotkov
Ivan Grokhotkov
parent
668acc2c08
commit
5f3a205955
323
tools/sdk/include/esp32/xtensa/config/tie-asm.h
Normal file
323
tools/sdk/include/esp32/xtensa/config/tie-asm.h
Normal file
@ -0,0 +1,323 @@
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/*
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* tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
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*
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* NOTE: This header file is not meant to be included directly.
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*/
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/* This header file contains assembly-language definitions (assembly
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macros, etc.) for this specific Xtensa processor's TIE extensions
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and options. It is customized to this Xtensa processor configuration.
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Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
|
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef _XTENSA_CORE_TIE_ASM_H
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#define _XTENSA_CORE_TIE_ASM_H
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/* Selection parameter values for save-area save/restore macros: */
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/* Option vs. TIE: */
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#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
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#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
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#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
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/* Whether used automatically by compiler: */
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#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
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#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
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#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
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/* ABI handling across function calls: */
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#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
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#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
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#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
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#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
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/* Misc */
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#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
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#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
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| ((ccuse) & XTHAL_SAS_ANYCC) \
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| ((abi) & XTHAL_SAS_ANYABI) )
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/*
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* Macro to store all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 4 byte aligned address).
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* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
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* registers are clobbered, the remaining are unused).
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* Optional parameters:
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* continue If macro invoked as part of a larger store sequence, set to 1
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* if this is not the first in the sequence. Defaults to 0.
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* ofs Offset from start of larger sequence (from value of first ptr
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* in sequence) at which to store. Defaults to next available space
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* (or 0 if <continue> is 0).
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* select Select what category(ies) of registers to store, as a bitmask
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* (see XTHAL_SAS_xxx constants). Defaults to all registers.
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* alloc Select what category(ies) of registers to allocate; if any
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* category is selected here that is not in <select>, space for
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* the corresponding registers is skipped without doing any store.
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*/
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.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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// Optional global registers used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
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xchal_sa_align \ptr, 0, 1016, 4, 4
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rur.THREADPTR \at1 // threadptr option
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s32i \at1, \ptr, .Lxchal_ofs_+0
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1016, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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// Optional caller-saved registers used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1012, 4, 4
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rsr.ACCLO \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+0
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rsr.ACCHI \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1012, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.endif
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// Optional caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 996, 4, 4
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rsr.BR \at1 // boolean option
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s32i \at1, \ptr, .Lxchal_ofs_+0
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rsr.SCOMPARE1 \at1 // conditional store option
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s32i \at1, \ptr, .Lxchal_ofs_+4
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rsr.M0 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+8
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rsr.M1 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+12
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rsr.M2 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+16
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rsr.M3 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+20
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 996, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
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.endif
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// Custom caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1008, 4, 4
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rur.F64R_LO \at1 // ureg 234
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s32i \at1, \ptr, .Lxchal_ofs_+0
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rur.F64R_HI \at1 // ureg 235
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s32i \at1, \ptr, .Lxchal_ofs_+4
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rur.F64S \at1 // ureg 236
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s32i \at1, \ptr, .Lxchal_ofs_+8
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
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.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1008, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
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.endif
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.endm // xchal_ncp_store
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/*
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* Macro to load all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 4 byte aligned address).
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* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
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* registers are clobbered, the remaining are unused).
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* Optional parameters:
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* continue If macro invoked as part of a larger load sequence, set to 1
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* if this is not the first in the sequence. Defaults to 0.
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* ofs Offset from start of larger sequence (from value of first ptr
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* in sequence) at which to load. Defaults to next available space
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* (or 0 if <continue> is 0).
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* select Select what category(ies) of registers to load, as a bitmask
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* (see XTHAL_SAS_xxx constants). Defaults to all registers.
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* alloc Select what category(ies) of registers to allocate; if any
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* category is selected here that is not in <select>, space for
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* the corresponding registers is skipped without doing any load.
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*/
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.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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// Optional global registers used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
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xchal_sa_align \ptr, 0, 1016, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wur.THREADPTR \at1 // threadptr option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1016, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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// Optional caller-saved registers used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1012, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wsr.ACCLO \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+4
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wsr.ACCHI \at1 // MAC16 option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1012, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.endif
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// Optional caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 996, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wsr.BR \at1 // boolean option
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l32i \at1, \ptr, .Lxchal_ofs_+4
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wsr.SCOMPARE1 \at1 // conditional store option
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l32i \at1, \ptr, .Lxchal_ofs_+8
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wsr.M0 \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+12
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wsr.M1 \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+16
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wsr.M2 \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+20
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wsr.M3 \at1 // MAC16 option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 996, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
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.endif
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// Custom caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1008, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wur.F64R_LO \at1 // ureg 234
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l32i \at1, \ptr, .Lxchal_ofs_+4
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wur.F64R_HI \at1 // ureg 235
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l32i \at1, \ptr, .Lxchal_ofs_+8
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wur.F64S \at1 // ureg 236
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
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.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1008, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
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.endif
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.endm // xchal_ncp_load
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#define XCHAL_NCP_NUM_ATMPS 1
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/*
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* Macro to store the state of TIE coprocessor FPU.
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 4 byte aligned address).
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* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
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* registers are clobbered, the remaining are unused).
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* Optional parameters are the same as for xchal_ncp_store.
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*/
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#define xchal_cp_FPU_store xchal_cp0_store
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.macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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// Custom caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 948, 4, 4
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rur.FCR \at1 // ureg 232
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s32i \at1, \ptr, .Lxchal_ofs_+0
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rur.FSR \at1 // ureg 233
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s32i \at1, \ptr, .Lxchal_ofs_+4
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ssi f0, \ptr, .Lxchal_ofs_+8
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ssi f1, \ptr, .Lxchal_ofs_+12
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ssi f2, \ptr, .Lxchal_ofs_+16
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ssi f3, \ptr, .Lxchal_ofs_+20
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ssi f4, \ptr, .Lxchal_ofs_+24
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ssi f5, \ptr, .Lxchal_ofs_+28
|
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ssi f6, \ptr, .Lxchal_ofs_+32
|
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ssi f7, \ptr, .Lxchal_ofs_+36
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ssi f8, \ptr, .Lxchal_ofs_+40
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ssi f9, \ptr, .Lxchal_ofs_+44
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ssi f10, \ptr, .Lxchal_ofs_+48
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ssi f11, \ptr, .Lxchal_ofs_+52
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ssi f12, \ptr, .Lxchal_ofs_+56
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ssi f13, \ptr, .Lxchal_ofs_+60
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ssi f14, \ptr, .Lxchal_ofs_+64
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ssi f15, \ptr, .Lxchal_ofs_+68
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
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.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 948, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
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.endif
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.endm // xchal_cp0_store
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/*
|
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* Macro to load the state of TIE coprocessor FPU.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
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* Optional parameters are the same as for xchal_ncp_load.
|
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*/
|
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#define xchal_cp_FPU_load xchal_cp0_load
|
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.macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
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xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.FCR \at1 // ureg 232
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wur.FSR \at1 // ureg 233
|
||||
lsi f0, \ptr, .Lxchal_ofs_+8
|
||||
lsi f1, \ptr, .Lxchal_ofs_+12
|
||||
lsi f2, \ptr, .Lxchal_ofs_+16
|
||||
lsi f3, \ptr, .Lxchal_ofs_+20
|
||||
lsi f4, \ptr, .Lxchal_ofs_+24
|
||||
lsi f5, \ptr, .Lxchal_ofs_+28
|
||||
lsi f6, \ptr, .Lxchal_ofs_+32
|
||||
lsi f7, \ptr, .Lxchal_ofs_+36
|
||||
lsi f8, \ptr, .Lxchal_ofs_+40
|
||||
lsi f9, \ptr, .Lxchal_ofs_+44
|
||||
lsi f10, \ptr, .Lxchal_ofs_+48
|
||||
lsi f11, \ptr, .Lxchal_ofs_+52
|
||||
lsi f12, \ptr, .Lxchal_ofs_+56
|
||||
lsi f13, \ptr, .Lxchal_ofs_+60
|
||||
lsi f14, \ptr, .Lxchal_ofs_+64
|
||||
lsi f15, \ptr, .Lxchal_ofs_+68
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.endif
|
||||
.endm // xchal_cp0_load
|
||||
|
||||
#define XCHAL_CP0_NUM_ATMPS 1
|
||||
#define XCHAL_SA_NUM_ATMPS 1
|
||||
|
||||
/* Empty macros for unconfigured coprocessors: */
|
||||
.macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_ASM_H*/
|
||||
|
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Reference in New Issue
Block a user