IDF master c69f0ec32 (#5449)

esp-dsp: master f4d7d6e
esp-face: master 420fc7e
esp-rainmaker: f1b82c7
esp32-camera: master 6a9497b
esp_littlefs: master b58f00c

tools/sdk/esp32/include/hal/esp32/include/hal/spi_ll.h

@@ -496,6 +496,16 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id)
     hw->pin.cs2_dis = (cs_id == 2) ? 0 : 1;
 }
 
+/**
+ * Keep Chip Select activated after the current transaction.
+ *
+ * @param hw Beginning address of the peripheral registers.
+ * @param keep_active if 0 don't keep CS activated, else keep CS activated
+ */
+static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) {
+    hw->pin.cs_keep_active = (keep_active != 0) ? 1 : 0;
+}
+
 /*------------------------------------------------------------------------------
  * Configs: parameters
  *----------------------------------------------------------------------------*/
@@ -744,7 +754,7 @@ static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen)
  */
 static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
 {
-    hw->slv_wrbuf_dlen.bit_len = bitlen - 1;
+    hw->slv_rdbuf_dlen.bit_len = bitlen - 1;
 }
 
 /**
@@ -755,7 +765,7 @@ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
  */
 static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen)
 {
-    hw->slv_rdbuf_dlen.bit_len = bitlen - 1;
+    hw->slv_wrbuf_dlen.bit_len = bitlen - 1;
 }
 
 /**

tools/sdk/esp32/include/hal/include/hal/adc_types.h

@@ -133,7 +133,7 @@ typedef struct {
 -                                         2: 11 bit;
 -                                         3: 12 bit. */
             int8_t channel:   4;   /*!< ADC channel index. */
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#elif CONFIG_IDF_TARGET_ESP32S2
             uint8_t reserved:  2;   /*!< reserved0 */
             uint8_t channel:   4;   /*!< ADC channel index. */
 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
@@ -295,7 +295,7 @@ typedef struct {
 #endif
 } adc_digi_config_t;
 
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if CONFIG_IDF_TARGET_ESP32S2
 /**
  * @brief ADC digital controller (DMA mode) interrupt type options.
  */

tools/sdk/esp32/include/hal/include/hal/dma_types.h

@@ -14,12 +14,12 @@
 
 #pragma once
 
+#include <stdint.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdint.h>
-
 /**
  * @brief Type of DMA descriptor
  *
@@ -43,3 +43,7 @@ _Static_assert(sizeof(dma_descriptor_t) == 12, "dma_descriptor_t should occupy 1
 #define DMA_DESCRIPTOR_BUFFER_OWNER_CPU (0)   /*!< DMA buffer is allowed to be accessed by CPU */
 #define DMA_DESCRIPTOR_BUFFER_OWNER_DMA (1)   /*!< DMA buffer is allowed to be accessed by DMA engine */
 #define DMA_DESCRIPTOR_BUFFER_MAX_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */
+
+#ifdef __cplusplus
+}
+#endif

tools/sdk/esp32/include/hal/include/hal/eth_types.h

@@ -24,8 +24,8 @@
 *
 */
 typedef enum {
-    EMAC_INTERFACE_MII,     /*!< Media Independent Interface */
-    EMAC_INTERFACE_RMII     /*!< Reduced Media Independent Interface */
+    EMAC_DATA_INTERFACE_RMII,    /*!< Reduced Media Independent Interface */
+    EMAC_DATA_INTERFACE_MII,     /*!< Media Independent Interface */
 } eth_data_interface_t;
 
 /**

tools/sdk/esp32/include/hal/include/hal/i2c_hal.h

@@ -110,6 +110,16 @@ typedef struct {
  */
 #define i2c_hal_slave_clr_rx_it(hal)    i2c_ll_slave_clr_rx_it((hal)->dev)
 
+/**
+ * @brief  Set the source clock. This function is meant to be used in
+ *         slave mode, in order to select a source clock abe to handle
+ *         the expected SCL frequency.
+ *
+ * @param  hal Context of the HAL layer
+ * @param  src_clk Source clock to use choosen from `i2c_sclk_t` type
+ */
+#define i2c_hal_set_source_clk(hal, src_clk) i2c_ll_set_source_clk((hal)->dev, src_clk)
+
 /**
  * @brief  Init the I2C master.
  *

tools/sdk/esp32/include/hal/include/hal/sha_types.h

@@ -19,25 +19,26 @@
 /* Use enum from rom for backwards compatibility */
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/sha.h"
-typedef enum SHA_TYPE esp_sha_type;
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/sha.h"
-typedef SHA_TYPE esp_sha_type;
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/sha.h"
-typedef SHA_TYPE esp_sha_type;
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/sha.h"
-typedef SHA_TYPE esp_sha_type;
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/sha.h"
-typedef SHA_TYPE esp_sha_type;
 #endif
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/* Use enum from rom for backwards compatibility */
+#if CONFIG_IDF_TARGET_ESP32
+typedef enum SHA_TYPE esp_sha_type;
+#else
+typedef SHA_TYPE esp_sha_type;
+#endif
 
 #ifdef __cplusplus
 }

tools/sdk/esp32/include/hal/include/hal/spi_flash_hal.h

@@ -25,7 +25,7 @@
 #include "hal/spi_flash_ll.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
-#include "soc/soc_memory_layout.h"
+#include "soc/soc_memory_types.h"
 
 /* Hardware host-specific constants */
 #define SPI_FLASH_HAL_MAX_WRITE_BYTES 64

tools/sdk/esp32/include/hal/include/hal/spi_hal.h

@@ -101,6 +101,7 @@ typedef struct {
     uint8_t *send_buffer;               ///< Data to be sent
     uint8_t *rcv_buffer;                ///< Buffer to hold the receive data.
     spi_ll_io_mode_t io_mode;           ///< IO mode of the master
+    int cs_keep_active;                 ///< Keep CS active after transaction
 } spi_hal_trans_config_t;
 
 /**

tools/sdk/esp32/include/hal/include/hal/twai_types.h

@@ -61,9 +61,9 @@ extern "C" {
  * @note The available bit rates are dependent on the chip target and revision.
  */
 #if (SOC_TWAI_BRP_MAX > 256)
-#define TWAI_TIMING_CONFIG_1KBITS()     {.brp = 4000, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
-#define TWAI_TIMING_CONFIG_5KBITS()     {.brp = 800, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
-#define TWAI_TIMING_CONFIG_10KBITS()    {.brp = 400, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
+#define TWAI_TIMING_CONFIG_1KBITS()     {.brp = 4000, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
+#define TWAI_TIMING_CONFIG_5KBITS()     {.brp = 800, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
+#define TWAI_TIMING_CONFIG_10KBITS()    {.brp = 400, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
 #endif
 #if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
 #define TWAI_TIMING_CONFIG_12_5KBITS()  {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}

tools/sdk/esp32/include/hal/include/hal/uart_hal.h

@@ -124,6 +124,16 @@ typedef struct {
  */
 #define uart_hal_is_tx_idle(hal)  uart_ll_is_tx_idle((hal)->dev)
 
+/**
+ * @brief  Configure the UART core reset
+ *
+ * @param  hal Context of the HAL layer
+ * @param  Set true to enable the core reset, otherwise set it false
+ *
+ * @return None
+ */
+#define uart_hal_set_reset_core(hal, core_rst_en)  uart_ll_set_reset_core((hal)->dev, core_rst_en)
+
 /**
  * @brief  Read data from the UART rxfifo
  *