IDF master c69f0ec32 (#5449)

esp-dsp: master f4d7d6e
esp-face: master 420fc7e
esp-rainmaker: f1b82c7
esp32-camera: master 6a9497b
esp_littlefs: master b58f00c

tools/sdk/esp32c3/include/esp_eth/include/esp_eth_mac.h

@@ -287,17 +287,98 @@ struct esp_eth_mac_s {
     esp_err_t (*del)(esp_eth_mac_t *mac);
 };
 
+/**
+ * @brief RMII Clock Mode Options
+ *
+ */
+typedef enum {
+    /**
+     * @brief Default values configured using Kconfig are going to be used when "Default" selected.
+     *
+     */
+    EMAC_CLK_DEFAULT,
+
+    /**
+     * @brief Input RMII Clock from external. EMAC Clock GPIO number needs to be configured when this option is selected.
+     *
+     * @note MAC will get RMII clock from outside. Note that ESP32 only supports GPIO0 to input the RMII clock.
+     *
+     */
+    EMAC_CLK_EXT_IN,
+
+    /**
+     * @brief Output RMII Clock from internal APLL Clock. EMAC Clock GPIO number needs to be configured when this option is selected.
+     *
+     */
+    EMAC_CLK_OUT
+} emac_rmii_clock_mode_t;
+
+/**
+ * @brief RMII Clock GPIO number Options
+ *
+ */
+typedef enum {
+    /**
+     * @brief MAC will get RMII clock from outside at this GPIO.
+     *
+     * @note ESP32 only supports GPIO0 to input the RMII clock.
+     *
+     */
+    EMAC_CLK_IN_GPIO = 0,
+
+    /**
+     * @brief Output RMII Clock from internal APLL Clock available at GPIO0
+     *
+     * @note GPIO0 can be set to output a pre-divided PLL clock (test only!). Enabling this option will configure GPIO0 to output a 50MHz clock.
+     * In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock won’t work well with your PHY chip.
+     * You might need to add some extra devices after GPIO0 (e.g. inverter). Note that outputting RMII clock on GPIO0 is an experimental practice.
+     * If you want the Ethernet to work with WiFi, don’t select GPIO0 output mode for stability.
+     *
+     */
+    EMAC_APPL_CLK_OUT_GPIO = 0,
+
+    /**
+     * @brief Output RMII Clock from internal APLL Clock available at GPIO16
+     *
+     */
+    EMAC_CLK_OUT_GPIO = 16,
+
+    /**
+     * @brief Inverted Output RMII Clock from internal APLL Clock available at GPIO17
+     *
+     */
+    EMAC_CLK_OUT_180_GPIO = 17
+} emac_rmii_clock_gpio_t;
+
+/**
+ * @brief Ethernet MAC Clock Configuration
+ *
+ */
+typedef union {
+    struct {
+        // MII interface is not fully implemented...
+        // Reserved for GPIO number, clock source, etc. in MII mode
+    } mii; /*!< EMAC MII Clock Configuration */
+    struct {
+        emac_rmii_clock_mode_t clock_mode; /*!< RMII Clock Mode Configuration */
+        emac_rmii_clock_gpio_t clock_gpio; /*!< RMII Clock GPIO Configuration */
+    } rmii; /*!< EMAC RMII Clock Configuration */
+} eth_mac_clock_config_t;
+
+
 /**
 * @brief Configuration of Ethernet MAC object
 *
 */
 typedef struct {
-    uint32_t sw_reset_timeout_ms; /*!< Software reset timeout value (Unit: ms) */
-    uint32_t rx_task_stack_size;  /*!< Stack size of the receive task */
-    uint32_t rx_task_prio;        /*!< Priority of the receive task */
-    int smi_mdc_gpio_num;         /*!< SMI MDC GPIO number, set to -1 could bypass the SMI GPIO configuration */
-    int smi_mdio_gpio_num;        /*!< SMI MDIO GPIO number, set to -1 could bypass the SMI GPIO configuration */
-    uint32_t flags;               /*!< Flags that specify extra capability for mac driver */
+    uint32_t sw_reset_timeout_ms;        /*!< Software reset timeout value (Unit: ms) */
+    uint32_t rx_task_stack_size;         /*!< Stack size of the receive task */
+    uint32_t rx_task_prio;               /*!< Priority of the receive task */
+    int smi_mdc_gpio_num;                /*!< SMI MDC GPIO number, set to -1 could bypass the SMI GPIO configuration */
+    int smi_mdio_gpio_num;               /*!< SMI MDIO GPIO number, set to -1 could bypass the SMI GPIO configuration */
+    uint32_t flags;                      /*!< Flags that specify extra capability for mac driver */
+    eth_data_interface_t interface;      /*!< EMAC Data interface to PHY (MII/RMII) */
+    eth_mac_clock_config_t clock_config; /*!< EMAC Interface clock configuration */
 } eth_mac_config_t;
 
 #define ETH_MAC_FLAG_WORK_WITH_CACHE_DISABLE (1 << 0) /*!< MAC driver can work when cache is disabled */
@@ -307,14 +388,23 @@ typedef struct {
  * @brief Default configuration for Ethernet MAC object
  *
  */
-#define ETH_MAC_DEFAULT_CONFIG()    \
-    {                               \
-        .sw_reset_timeout_ms = 100, \
-        .rx_task_stack_size = 4096, \
-        .rx_task_prio = 15,         \
-        .smi_mdc_gpio_num = 23,     \
-        .smi_mdio_gpio_num = 18,    \
-        .flags = 0,                 \
+#define ETH_MAC_DEFAULT_CONFIG()                          \
+    {                                                     \
+        .sw_reset_timeout_ms = 100,                       \
+        .rx_task_stack_size = 4096,                       \
+        .rx_task_prio = 15,                               \
+        .smi_mdc_gpio_num = 23,                           \
+        .smi_mdio_gpio_num = 18,                          \
+        .flags = 0,                                       \
+        .interface = EMAC_DATA_INTERFACE_RMII,            \
+        .clock_config =                                   \
+        {                                                 \
+            .rmii =                                       \
+            {                                             \
+                .clock_mode = EMAC_CLK_DEFAULT,           \
+                .clock_gpio = EMAC_CLK_IN_GPIO            \
+            }                                             \
+        }                                                 \
     }
 
 #if CONFIG_ETH_USE_ESP32_EMAC