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IDF master c69f0ec32 (#5449)

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esp-dsp: master f4d7d6e
esp-face: master 420fc7e
esp-rainmaker: f1b82c7
esp32-camera: master 6a9497b
esp_littlefs: master b58f00c
This commit is contained in:
Me No Dev
2021-07-26 15:56:05 +03:00
committed by GitHub
parent e0e5c88658
commit 6972695d95
588 changed files with 15433 additions and 1657 deletions
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38
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/memprot_ll.h
View File

@ -42,6 +42,18 @@ extern "C" {
#define I_D_SPLIT_LINE_SHIFT 0x9
#define I_D_FAULT_ADDR_SHIFT 0x2
typedef union {
struct {
uint32_t cat0 : 2;
uint32_t cat1 : 2;
uint32_t cat2 : 2;
uint32_t res0 : 8;
uint32_t splitaddr : 8;
uint32_t res1 : 10;
};
uint32_t val;
} constrain_reg_fields_t;
static inline void memprot_ll_set_iram0_dram0_split_line_lock(void)
{
REG_WRITE(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG, 1);
@ -54,9 +66,21 @@ static inline bool memprot_ll_get_iram0_dram0_split_line_lock(void)
static inline void* memprot_ll_get_split_addr_from_reg(uint32_t regval, uint32_t base)
{
return (void*)
(base + ((regval & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M)
>> (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S - I_D_SPLIT_LINE_SHIFT)));
constrain_reg_fields_t reg_val;
reg_val.val = regval;
uint32_t off = reg_val.splitaddr << 9;
if (reg_val.cat0 == 0x1 || reg_val.cat0 == 0x2) {
return (void *)(base + off);
} else if (reg_val.cat1 == 0x1 || reg_val.cat1 == 0x2) {
return (void *)(base + I_D_SRAM_SEGMENT_SIZE + off);
} else if (reg_val.cat2 == 0x1 || reg_val.cat2 == 0x2) {
return (void *)(base + (2 * I_D_SRAM_SEGMENT_SIZE) + off);
} else {
/* Either the register was not configured at all or incorrectly configured */
return NULL;
}
}
/* ******************************************************************************************************
@ -382,22 +406,22 @@ static inline void memprot_ll_set_dram0_split_line(const void *line_addr, uint32
static inline void memprot_ll_set_dram0_split_line_D_0(const void *line_addr)
{
memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG);
memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG);
}
static inline void memprot_ll_set_dram0_split_line_D_1(const void *line_addr)
{
memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG);
memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG);
}
static inline void* memprot_ll_get_dram0_split_line_D_0(void)
{
return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG), SOC_DIRAM_DRAM_LOW);
return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG), SOC_DIRAM_DRAM_LOW);
}
static inline void* memprot_ll_get_dram0_split_line_D_1(void)
{
return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG), SOC_DIRAM_DRAM_LOW);
return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG), SOC_DIRAM_DRAM_LOW);
}

17
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/spi_ll.h
View File

@ -136,6 +136,8 @@ static inline void spi_ll_slave_init(spi_dev_t *hw)
hw->user.usr_miso_highpart = 0;
hw->user.usr_mosi_highpart = 0;
// Configure DMA In-Link to not be terminated when transaction bit counter exceeds
hw->dma_conf.rx_eof_en = 0;
hw->dma_conf.dma_seg_trans_en = 0;
//Disable unneeded ints
@ -584,7 +586,6 @@ static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_
static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans)
{
hw->dma_conf.dma_seg_trans_en = seg_trans;
hw->dma_conf.rx_eof_en = seg_trans;
}
/**
@ -603,6 +604,16 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id)
hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1;
}
/**
* Keep Chip Select activated after the current transaction.
*
* @param hw Beginning address of the peripheral registers.
* @param keep_active if 0 don't keep CS activated, else keep CS activated
*/
static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) {
hw->misc.cs_keep_active = (keep_active != 0) ? 1 : 0;
}
/*------------------------------------------------------------------------------
* Configs: parameters
*----------------------------------------------------------------------------*/
@ -819,7 +830,7 @@ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen)
*/
static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
{
spi_ll_set_mosi_bitlen(hw, bitlen);
//This is not used in esp32c3
}
/**
@ -830,7 +841,7 @@ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
*/
static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen)
{
spi_ll_set_mosi_bitlen(hw, bitlen);
//This is not used in esp32c3
}
/**

5
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/uart_ll.h
View File

@ -58,9 +58,8 @@ typedef enum {
UART_INTR_CMD_CHAR_DET = (0x1 << 18),
} uart_intr_t;
static inline void uart_ll_reset_core(uart_dev_t *hw) {
hw->clk_conf.rst_core = 1;
hw->clk_conf.rst_core = 0;
static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) {
hw->clk_conf.rst_core = core_rst_en;
}
static inline void uart_ll_sclk_enable(uart_dev_t *hw) {

4
tools/sdk/esp32c3/include/hal/include/hal/adc_types.h
View File

@ -133,7 +133,7 @@ typedef struct {
- 2: 11 bit;
- 3: 12 bit. */
int8_t channel: 4; /*!< ADC channel index. */
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#elif CONFIG_IDF_TARGET_ESP32S2
uint8_t reserved: 2; /*!< reserved0 */
uint8_t channel: 4; /*!< ADC channel index. */
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
@ -295,7 +295,7 @@ typedef struct {
#endif
} adc_digi_config_t;
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#if CONFIG_IDF_TARGET_ESP32S2
/**
* @brief ADC digital controller (DMA mode) interrupt type options.
*/

8
tools/sdk/esp32c3/include/hal/include/hal/dma_types.h
View File

@ -14,12 +14,12 @@
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief Type of DMA descriptor
*
@ -43,3 +43,7 @@ _Static_assert(sizeof(dma_descriptor_t) == 12, "dma_descriptor_t should occupy 1
#define DMA_DESCRIPTOR_BUFFER_OWNER_CPU (0) /*!< DMA buffer is allowed to be accessed by CPU */
#define DMA_DESCRIPTOR_BUFFER_OWNER_DMA (1) /*!< DMA buffer is allowed to be accessed by DMA engine */
#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */
#ifdef __cplusplus
}
#endif

4
tools/sdk/esp32c3/include/hal/include/hal/eth_types.h
View File

@ -24,8 +24,8 @@
*
*/
typedef enum {
EMAC_INTERFACE_MII, /*!< Media Independent Interface */
EMAC_INTERFACE_RMII /*!< Reduced Media Independent Interface */
EMAC_DATA_INTERFACE_RMII, /*!< Reduced Media Independent Interface */
EMAC_DATA_INTERFACE_MII, /*!< Media Independent Interface */
} eth_data_interface_t;
/**

10
tools/sdk/esp32c3/include/hal/include/hal/i2c_hal.h
View File

@ -110,6 +110,16 @@ typedef struct {
*/
#define i2c_hal_slave_clr_rx_it(hal) i2c_ll_slave_clr_rx_it((hal)->dev)
/**
* @brief Set the source clock. This function is meant to be used in
* slave mode, in order to select a source clock abe to handle
* the expected SCL frequency.
*
* @param hal Context of the HAL layer
* @param src_clk Source clock to use choosen from `i2c_sclk_t` type
*/
#define i2c_hal_set_source_clk(hal, src_clk) i2c_ll_set_source_clk((hal)->dev, src_clk)
/**
* @brief Init the I2C master.
*

11
tools/sdk/esp32c3/include/hal/include/hal/sha_types.h
View File

@ -19,25 +19,26 @@
/* Use enum from rom for backwards compatibility */
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/sha.h"
typedef enum SHA_TYPE esp_sha_type;
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/sha.h"
typedef SHA_TYPE esp_sha_type;
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/sha.h"
typedef SHA_TYPE esp_sha_type;
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/sha.h"
typedef SHA_TYPE esp_sha_type;
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/sha.h"
typedef SHA_TYPE esp_sha_type;
#endif
#ifdef __cplusplus
extern "C" {
#endif
/* Use enum from rom for backwards compatibility */
#if CONFIG_IDF_TARGET_ESP32
typedef enum SHA_TYPE esp_sha_type;
#else
typedef SHA_TYPE esp_sha_type;
#endif
#ifdef __cplusplus
}

2
tools/sdk/esp32c3/include/hal/include/hal/spi_flash_hal.h
View File

@ -25,7 +25,7 @@
#include "hal/spi_flash_ll.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include "soc/soc_memory_layout.h"
#include "soc/soc_memory_types.h"
/* Hardware host-specific constants */
#define SPI_FLASH_HAL_MAX_WRITE_BYTES 64

1
tools/sdk/esp32c3/include/hal/include/hal/spi_hal.h
View File

@ -101,6 +101,7 @@ typedef struct {
uint8_t *send_buffer; ///< Data to be sent
uint8_t *rcv_buffer; ///< Buffer to hold the receive data.
spi_ll_io_mode_t io_mode; ///< IO mode of the master
int cs_keep_active; ///< Keep CS active after transaction
} spi_hal_trans_config_t;
/**

6
tools/sdk/esp32c3/include/hal/include/hal/twai_types.h
View File

@ -61,9 +61,9 @@ extern "C" {
* @note The available bit rates are dependent on the chip target and revision.
*/
#if (SOC_TWAI_BRP_MAX > 256)
#define TWAI_TIMING_CONFIG_1KBITS() {.brp = 4000, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_5KBITS() {.brp = 800, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_10KBITS() {.brp = 400, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_1KBITS() {.brp = 4000, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_5KBITS() {.brp = 800, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_10KBITS() {.brp = 400, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#endif
#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
#define TWAI_TIMING_CONFIG_12_5KBITS() {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}

10
tools/sdk/esp32c3/include/hal/include/hal/uart_hal.h
View File

@ -124,6 +124,16 @@ typedef struct {
*/
#define uart_hal_is_tx_idle(hal) uart_ll_is_tx_idle((hal)->dev)
/**
* @brief Configure the UART core reset
*
* @param hal Context of the HAL layer
* @param Set true to enable the core reset, otherwise set it false
*
* @return None
*/
#define uart_hal_set_reset_core(hal, core_rst_en) uart_ll_set_reset_core((hal)->dev, core_rst_en)
/**
* @brief Read data from the UART rxfifo
*