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Me No Dev
2021-07-26 15:56:05 +03:00
committed by GitHub
parent e0e5c88658
commit 6972695d95
588 changed files with 15433 additions and 1657 deletions
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58
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/reset_reasons.h Normal file
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@ -0,0 +1,58 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

26
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/rtc.h
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@ -143,6 +143,13 @@ typedef enum {
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
} rtc_xtal_freq_t;
/** @brief Fixed crystal frequency for this SoC
On an SoC where only one crystal frequency is supported,
using this macro is an alternative to calling rtc_clk_xtal_freq_get()
*/
#define RTC_XTAL_FREQ RTC_XTAL_FREQ_40M
/**
* @brief CPU frequency values
*/
@ -315,23 +322,16 @@ void rtc_clk_init(rtc_clk_config_t cfg);
/**
* @brief Get main XTAL frequency
*
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
* rtc_clk_init function
* Result is a constant as XTAL frequency is fixed.
*
* @return XTAL frequency, one of rtc_xtal_freq_t
* @note Function is included for ESP32 compatible code only. Code which only
* needs to support this SoC can use the macro RTC_XTAL_FREQ for this SoC's
* fixed crystal value.
*
* @return XTAL frequency in MHz, RTC_XTAL_FREQ_40M
*/
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
/**
* @brief Update XTAL frequency
*
* Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
* after startup.
*
* @param xtal_freq New frequency value
*/
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
/**
* @brief Enable or disable 32 kHz XTAL oscillator
* @param en true to enable, false to disable

4
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/soc_caps.h
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@ -54,7 +54,11 @@
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_CACHE_SUPPORT_WRAP 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define SOC_PSRAM_DMA_CAPABLE 1
/*-------------------------- ADC CAPS ----------------------------------------*/
#define SOC_ADC_PERIPH_NUM (2)

147
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/usb_struct.h
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@ -22,82 +22,81 @@ extern "C" {
#endif
typedef struct usb_reg {
volatile uint32_t gotgctl; /*!< 0x0 */
volatile uint32_t gotgint;
volatile uint32_t gahbcfg;
volatile uint32_t gusbcfg;
volatile uint32_t grstctl; /*!< 0x10 */
volatile uint32_t gintsts;
volatile uint32_t gintmsk;
volatile uint32_t grxstsr;
volatile uint32_t grxstsp; /*!< 0x20 */
volatile uint32_t grxfsiz;
volatile uint32_t gnptxfsiz;
volatile uint32_t gnptxsts;
volatile uint32_t reserved0x2c;
volatile uint32_t gpvndctl; /*!< 0x30 */
volatile uint32_t ggpio;
volatile uint32_t guid;
volatile uint32_t gsnpsid;
volatile uint32_t ghwcfg1; /*!< 0x40 */
volatile uint32_t ghwcfg2;
volatile uint32_t ghwcfg3;
volatile uint32_t ghwcfg4; /*!< 0x50 */
volatile uint32_t glpmcfg; /*!< 0x54 */
volatile uint32_t gpwrdn; /*!< 0x58 */
volatile uint32_t gdfifocfg; /*!< 0x5c */
volatile uint32_t gadpctl; /*!< 0x60 */
uint32_t reserved0x64[39];
volatile uint32_t hptxfsiz; /*!< 0x100 */
volatile uint32_t dieptxf[15]; /*!< 0x104 */
uint32_t reserved0x140[176]; /*!< 0x140 */
volatile uint32_t gotgctl; // 0x0000 OTG Control and Status Register
volatile uint32_t gotgint; // 0x0004 OTG Interrupt Register
volatile uint32_t gahbcfg; // 0x0008 AHB Configuration Register
volatile uint32_t gusbcfg; // 0x000c USB Configuration Register
volatile uint32_t grstctl; // 0x0010 Reset Register
volatile uint32_t gintsts; // 0x0014 Interrupt Register
volatile uint32_t gintmsk; // 0x0018 Interrupt Mask Register
volatile uint32_t grxstsr; // 0x001c Receive Status Debug Read Register
volatile uint32_t grxstsp; // 0x0020 Receive Status Read/Pop Register
volatile uint32_t grxfsiz; // 0x0024 Receive FIFO Size Register
volatile uint32_t gnptxfsiz; // 0x0028 Non-periodic Transmit FIFO Size Register
volatile uint32_t gnptxsts; // 0x002c Non-periodic Transmit FIFO/Queue Status Register
uint32_t reserved_0x0030_0x0040[4]; // 0x0030 to 0x0040
volatile uint32_t gsnpsid; // 0x0040 Synopsys ID Register
volatile uint32_t ghwcfg1; // 0x0044 User Hardware Configuration 1 Register
volatile uint32_t ghwcfg2; // 0x0048 User Hardware Configuration 2 Register
volatile uint32_t ghwcfg3; // 0x004c User Hardware Configuration 3 Register
volatile uint32_t ghwcfg4; // 0x0050 User Hardware Configuration 4 Register
uint32_t reserved_0x0054_0x005c[2]; // 0x0054 to 0x005c
volatile uint32_t gdfifocfg; // 0x005c Global DFIFO Configuration Register
uint32_t reserved_0x0060_0x0100[40]; // 0x0060 to 0x0100
volatile uint32_t hptxfsiz; // 0x0100 Host Periodic Transmit FIFO Size Register
volatile uint32_t dieptxf[4]; // 0x0104 to 0x0114 Device IN Endpoint Transmit FIFO Size Register i
uint32_t reserved_0x0114_0x0140[11]; // 0x0114 to 0x0140
uint32_t reserved_0x0140_0x0400[176]; // 0x0140 to 0x0400
/**
* The Host Global Registers structure defines the size and relative
* field offsets for the Host Mode Global Registers. Host Global
* Registers offsets 400h-7FFh.
*/
volatile uint32_t hcfg; /*!< Host Configuration Register. <i>Offset: 400h</i> */
volatile uint32_t hfir; /*!< Host Frame Interval Register. <i>Offset: 404h</i> */
volatile uint32_t hfnum; /*!< Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
uint32_t reserved0x40C; /*!< Reserved. <i>Offset: 40Ch</i> */
volatile uint32_t hptxsts; /*!< Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
volatile uint32_t haint; /*!< Host All Channels Interrupt Register. <i>Offset: 414h</i> */
volatile uint32_t haintmsk; /*!< Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
volatile uint32_t hflbaddr; /*!< Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
uint32_t reserved0x420[7];
volatile uint32_t hprt; //0x440
uint32_t reserved0x444[240];
volatile uint32_t dcfg; /*!< Device Configuration Register. <i>Offset 800h</i> */
volatile uint32_t dctl; /*!< Device Control Register. <i>Offset: 804h</i> */
volatile uint32_t dsts; /*!< Device Status Register (Read Only). <i>Offset: 808h</i> */
uint32_t reserved0x80c; /*!< Reserved. <i>Offset: 80Ch</i> */
volatile uint32_t diepmsk; /*!< Device IN Endpoint Common Interrupt Mask Register. <i>Offset: 810h</i> */
volatile uint32_t doepmsk; /*!< Device OUT Endpoint Common Interrupt Mask Register. <i>Offset: 814h</i> */
volatile uint32_t daint; /*!< Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
volatile uint32_t daintmsk; /*!< Device All Endpoints Interrupt Mask Register. <i>Offset: 81Ch</i> */
volatile uint32_t dtknqr1; /*!< Device IN Token Queue Read Register-1 (Read Only). <i>Offset: 820h</i> */
volatile uint32_t dtknqr2; /*!< Device IN Token Queue Read Register-2 (Read Only). <i>Offset: 824h</i> */
volatile uint32_t dvbusdis; /*!< Device VBUS discharge Register. <i>Offset: 828h</i> */
volatile uint32_t dvbuspulse; /*!< Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
volatile uint32_t dtknqr3_dthrctl; /*!< Device IN Token Queue Read Register-3 (Read Only). Device Thresholding control register (Read/Write) <i>Offset: 830h</i> */
volatile uint32_t dtknqr4_fifoemptymsk; /*!< Device IN Token Queue Read Register-4 (Read Only). Device IN EPs empty Inr. Mask Register (Read/Write)<i>Offset: 834h</i> */
volatile uint32_t deachint; /*!< Device Each Endpoint Interrupt Register (Read Only). <i>Offset: 838h</i> */
volatile uint32_t deachintmsk; /*!< Device Each Endpoint Interrupt mask Register (Read/Write). <i>Offset: 83Ch</i> */
volatile uint32_t diepeachintmsk[16]; /*!< Device Each In Endpoint Interrupt mask Register (Read/Write). <i>Offset: 840h</i> */
volatile uint32_t doepeachintmsk[16]; /*!< Device Each Out Endpoint Interrupt mask Register (Read/Write). <i>Offset: 880h</i> */
uint32_t reserved0x8c0[16];
/* Input Endpoints*/
usb_in_endpoint_t in_ep_reg[USB_IN_EP_NUM]; /*!< 0x900*/
uint32_t reserved6[72];
/* Output Endpoints */
usb_out_endpoint_t out_ep_reg[USB_OUT_EP_NUM];
uint32_t reserved7[136];
uint32_t pcgctrl; /*!<0xe00*/
uint32_t pcgctrl1;
uint8_t reserved8[0x1000 - 0xe08]; /*!<0xd00*/
uint32_t fifo[16][0x400]; /*!<0x1000*/
* Host mode registers offsets from 0x0400 to 0x07FF
*/
volatile uint32_t hcfg; // 0x0400 Host Configuration Register
volatile uint32_t hfir; // 0x0404 Host Frame Interval Register
volatile uint32_t hfnum; // 0x0408 Host Frame Number/Frame Remaining Register
uint32_t reserved0x40C; // 0x040c Reserved
volatile uint32_t hptxsts; // 0x0410 Host Periodic Transmit FIFO/ Queue Status Register
volatile uint32_t haint; // 0x0414 Host All Channels Interrupt Register
volatile uint32_t haintmsk; // 0x0418 Host All Channels Interrupt Mask Register
volatile uint32_t hflbaddr; // 0x041c Host Frame List Base Address Register
uint32_t reserved0x0420_0x0440[8]; // 0x0420 to 0x0440
volatile uint32_t hprt; // 0x0440 Host Port Control and Status Register
uint32_t reserved_0x0444_0x0500[47]; // 0x0444 to 0x0500
//Skip over the host channel registers
volatile uint32_t host_chan_regs[128]; // 0x0500 to 0x0700
uint32_t reserved_0x0700_0x0800[64]; // 0x0700 to 0x0800
/**
* Device mode registers offsets from
*/
volatile uint32_t dcfg; // 0x0800 Device Configuration Register
volatile uint32_t dctl; // 0x0804 Device Control Register
volatile uint32_t dsts; // 0x0808 Device Status Register (Read Only)
uint32_t reserved0x80c; // 0x080c
volatile uint32_t diepmsk; // 0x0810 Device IN Endpoint Common Interrupt Mask Register
volatile uint32_t doepmsk; // 0x0814 Device OUT Endpoint Common Interrupt Mask Register
volatile uint32_t daint; // 0x0818 Device All Endpoints Interrupt Register
volatile uint32_t daintmsk; // 0x081c Device All Endpoints Interrupt Mask Register
uint32_t reserved_0x0820_0x0828[2]; // 0x0820 to 0x0828
volatile uint32_t dvbusdis; // 0x0828 Device VBUS discharge Register
volatile uint32_t dvbuspulse; // 0x082c Device VBUS Pulse Register
volatile uint32_t dthrctl; // 0x0830 Device Thresholding control register (Read/Write)
volatile uint32_t dtknqr4_fifoemptymsk; // 0x0834 Device IN Endpoint FIFO Empty Interrupt Mask register
uint32_t reserved_0x0838_0x0900[50]; // 0x0838 to 0x0900
// Input Endpoints
usb_in_endpoint_t in_ep_reg[USB_IN_EP_NUM]; // 0x0900 to 0x09e0 IN EP registers
uint32_t reserved_0x09e0_0x0b00[72]; // 0x09e0 to 0x0b00
// Output Endpoints
usb_out_endpoint_t out_ep_reg[USB_OUT_EP_NUM]; // 0x0b00 to 0x0be0 OUT EP registers
uint32_t reserved_0x0be0_0x0d00[72]; // 0x0be0 to 0x0d00
uint32_t reserved_0x0d00_0x0e00[64]; // 0x0d00 to 0x0e00
/**
* Power Control and direct FIFO access
*/
uint32_t pcgctrl; // 0x0e00 Power and Clock Gating Control Register
uint32_t reserved_0x0e04; // 0x0e04
uint8_t reserved8[0x1000 - 0xe08]; // 0x0d00 to 0x1000
uint32_t fifo[16][0x400]; // 0x1000 to 0x2000 Device EP i/Host Channel i FIFO
uint8_t reserved0x11000[0x20000 - 0x11000];
uint32_t dbg_fifo[0x20000]; /*!< 0x20000*/
uint32_t dbg_fifo[0x20000]; // 0x2000 to 0x22000 Direct Access to Data FIFO RAM for Debugging
} usb_dev_t;
extern usb_dev_t USB0;

127
tools/sdk/esp32s2/include/soc/include/soc/soc_memory_layout.h → tools/sdk/esp32s2/include/soc/include/soc/soc_memory_types.h
View File

@ -22,124 +22,9 @@
#include "sdkconfig.h"
#include "esp_attr.h"
#ifdef CONFIG_BT_ENABLED
#define SOC_MEM_BT_DATA_START 0x3ffae6e0
#define SOC_MEM_BT_DATA_END 0x3ffaff10
#define SOC_MEM_BT_EM_START 0x3ffb0000
#define SOC_MEM_BT_EM_END 0x3ffb7cd8
#define SOC_MEM_BT_EM_BTDM0_START 0x3ffb0000
#define SOC_MEM_BT_EM_BTDM0_END 0x3ffb09a8
#define SOC_MEM_BT_EM_BLE_START 0x3ffb09a8
#define SOC_MEM_BT_EM_BLE_END 0x3ffb1ddc
#define SOC_MEM_BT_EM_BTDM1_START 0x3ffb1ddc
#define SOC_MEM_BT_EM_BTDM1_END 0x3ffb2730
#define SOC_MEM_BT_EM_BREDR_START 0x3ffb2730
#define SOC_MEM_BT_EM_BREDR_NO_SYNC_END 0x3ffb6388 //Not calculate with synchronize connection support
#define SOC_MEM_BT_EM_BREDR_END 0x3ffb7cd8 //Calculate with synchronize connection support
#define SOC_MEM_BT_EM_SYNC0_START 0x3ffb6388
#define SOC_MEM_BT_EM_SYNC0_END 0x3ffb6bf8
#define SOC_MEM_BT_EM_SYNC1_START 0x3ffb6bf8
#define SOC_MEM_BT_EM_SYNC1_END 0x3ffb7468
#define SOC_MEM_BT_EM_SYNC2_START 0x3ffb7468
#define SOC_MEM_BT_EM_SYNC2_END 0x3ffb7cd8
#define SOC_MEM_BT_BSS_START 0x3ffb8000
#define SOC_MEM_BT_BSS_END 0x3ffb9a20
#define SOC_MEM_BT_MISC_START 0x3ffbdb28
#define SOC_MEM_BT_MISC_END 0x3ffbdb5c
#define SOC_MEM_BT_EM_PER_SYNC_SIZE 0x870
#define SOC_MEM_BT_EM_BREDR_REAL_END (SOC_MEM_BT_EM_BREDR_NO_SYNC_END + CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF * SOC_MEM_BT_EM_PER_SYNC_SIZE)
#endif //CONFIG_BT_ENABLED
#define SOC_MEMORY_TYPE_NO_PRIOS 3
/* Type descriptor holds a description for a particular type of memory on a particular SoC.
*/
typedef struct {
const char *name; ///< Name of this memory type
uint32_t caps[SOC_MEMORY_TYPE_NO_PRIOS]; ///< Capabilities for this memory type (as a prioritised set)
bool aliased_iram; ///< If true, this is data memory that is is also mapped in IRAM
bool startup_stack; ///< If true, memory of this type is used for ROM stack during startup
} soc_memory_type_desc_t;
/* Constant table of tag descriptors for all this SoC's tags */
extern const soc_memory_type_desc_t soc_memory_types[];
extern const size_t soc_memory_type_count;
/* Region descriptor holds a description for a particular region of memory on a particular SoC.
*/
typedef struct
{
intptr_t start; ///< Start address of the region
size_t size; ///< Size of the region in bytes
size_t type; ///< Type of the region (index into soc_memory_types array)
intptr_t iram_address; ///< If non-zero, is equivalent address in IRAM
} soc_memory_region_t;
extern const soc_memory_region_t soc_memory_regions[];
extern const size_t soc_memory_region_count;
/* Region descriptor holds a description for a particular region of
memory reserved on this SoC for a particular use (ie not available
for stack/heap usage.) */
typedef struct
{
intptr_t start;
intptr_t end;
} soc_reserved_region_t;
/* Use this macro to reserved a fixed region of RAM (hardcoded addresses)
* for a particular purpose.
*
* Usually used to mark out memory addresses needed for hardware or ROM code
* purposes.
*
* Don't call this macro from user code which can use normal C static allocation
* instead.
*
* @param START Start address to be reserved.
* @param END One after the address of the last byte to be reserved. (ie length of
* the reserved region is (END - START) in bytes.
* @param NAME Name for the reserved region. Must be a valid variable name,
* unique to this source file.
*/
#define SOC_RESERVE_MEMORY_REGION(START, END, NAME) \
__attribute__((section(".reserved_memory_address"))) __attribute__((used)) \
static soc_reserved_region_t reserved_region_##NAME = { START, END };
/* Return available memory regions for this SoC. Each available memory
* region is a contiguous piece of memory which is not being used by
* static data, used by ROM code, or reserved by a component using
* the SOC_RESERVE_MEMORY_REGION() macro.
*
* This result is soc_memory_regions[] minus all regions reserved
* via the SOC_RESERVE_MEMORY_REGION() macro (which may also split
* some regions up.)
*
* At startup, all available memory returned by this function is
* registered as heap space.
*
* @note OS-level startup function only, not recommended to call from
* app code.
*
* @param regions Pointer to an array for reading available regions into.
* Size of the array should be at least the result of
* soc_get_available_memory_region_max_count(). Entries in the array
* will be ordered by memory address.
*
* @return Number of entries copied to 'regions'. Will be no greater than
* the result of soc_get_available_memory_region_max_count().
*/
size_t soc_get_available_memory_regions(soc_memory_region_t *regions);
/* Return the maximum number of available memory regions which could be
* returned by soc_get_available_memory_regions(). Used to size the
* array passed to that function.
*/
size_t soc_get_available_memory_region_max_count(void);
#ifdef __cplusplus
extern "C" {
#endif
inline static bool IRAM_ATTR esp_ptr_dma_capable(const void *p)
{
@ -148,7 +33,7 @@ inline static bool IRAM_ATTR esp_ptr_dma_capable(const void *p)
inline static bool IRAM_ATTR esp_ptr_dma_ext_capable(const void *p)
{
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#ifdef SOC_PSRAM_DMA_CAPABLE
return (intptr_t)p >= SOC_DMA_EXT_LOW && (intptr_t)p < SOC_DMA_EXT_HIGH;
#else
return false;
@ -302,3 +187,7 @@ inline static bool IRAM_ATTR esp_stack_ptr_is_sane(uint32_t sp)
#endif
;
}
#ifdef __cplusplus
}
#endif