mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
synced 2025-07-01 04:50:58 +02:00
Update IDF to f586f5e (#1296)
* Update BLE lib * Update IDF to f586f5e * Restructure Bluetooth Serial includes * Update esptool and gen_esp32part * Add partition scheme selection for menuconfig * Add partition scheme selection for Arduino IDE * Fix BLE example * Second attempt BLE fix * Add exceptions to PIO
This commit is contained in:
Me No Dev
GitHub
@ -79,21 +79,33 @@
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#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0
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#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c)
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/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
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/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
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/*description: bit is set to 1 for rev1 silicon*/
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#define EFUSE_RD_CHIP_VER_REV1 (BIT(15))
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#define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S))
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#define EFUSE_RD_CHIP_VER_REV1_V 0x1
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#define EFUSE_RD_CHIP_VER_REV1_S 15
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/* EFUSE_RD_CHIP_VER_RESERVE : R/W ;bitpos:[15:12] ;default: 3'b0 ; */
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/*description: */
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#define EFUSE_RD_CHIP_VER_RESERVE 0x00000007
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#define EFUSE_RD_CHIP_VER_RESERVE_M ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S))
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#define EFUSE_RD_CHIP_VER_RESERVE_V 0x7
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#define EFUSE_RD_CHIP_VER_RESERVE_S 12
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/* EFUSE_RD_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
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/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */
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/*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/
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#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14))
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#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S))
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#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1
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#define EFUSE_RD_BLK3_PART_RESERVE_S 14
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/* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */
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/*description: If set, the ESP32's maximum CPU frequency has been rated*/
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#define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13))
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#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_RD_CHIP_CPU_FREQ_RATED_S))
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#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1
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#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13
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/* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */
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/*description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/
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#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12))
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#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_RD_CHIP_CPU_FREQ_LOW_S))
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#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1
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#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12
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/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
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/*description: chip package */
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#define EFUSE_RD_CHIP_VER 0x00000007
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#define EFUSE_RD_CHIP_VER_PKG 0x00000007
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#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S))
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#define EFUSE_RD_CHIP_VER_PKG_V 0x7
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#define EFUSE_RD_CHIP_VER_PKG_S 9
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@ -152,6 +164,15 @@
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#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14))
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#define EFUSE_RD_XPD_SDIO_REG_V 0x1
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#define EFUSE_RD_XPD_SDIO_REG_S 14
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/* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */
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/*description: True ADC reference voltage */
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#define EFUSE_RD_ADC_VREF 0x0000001F
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#define EFUSE_RD_ADC_VREF_M ((EFUSE_RD_ADC_VREF_V)<<(EFUSE_RD_ADC_VREF_S))
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#define EFUSE_RD_ADC_VREF_V 0x1F
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#define EFUSE_RD_ADC_VREF_S 8
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/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer
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* versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore
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* SDIO_DREFH/M/L is only available in older versions of ESP32 */
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/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */
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/*description: */
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#define EFUSE_RD_SDIO_DREFL 0x00000003
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@ -314,24 +335,41 @@
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#define EFUSE_WIFI_MAC_CRC_HIGH_S 0
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#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028)
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/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
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/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
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/*description: */
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#define EFUSE_CHIP_VER_REV1 (BIT(15))
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#define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S))
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#define EFUSE_CHIP_VER_REV1_V 0x1
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#define EFUSE_CHIP_VER_REV1_S 15
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/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[15:12] ;default: 3'b0 ; */
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/*description: */
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#define EFUSE_CHIP_VER_RESERVE 0x00000007
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#define EFUSE_CHIP_VER_RESERVE_M ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S))
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#define EFUSE_CHIP_VER_RESERVE_V 0x7
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#define EFUSE_CHIP_VER_RESERVE_S 12
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/* EFUSE_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
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/* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */
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/*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/
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#define EFUSE_BLK3_PART_RESERVE (BIT(14))
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#define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S))
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#define EFUSE_BLK3_PART_RESERVE_V 0x1
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#define EFUSE_BLK3_PART_RESERVE_S 14
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/* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */
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/*description: If set, the ESP32's maximum CPU frequency has been rated*/
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#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13))
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#define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_CHIP_CPU_FREQ_RATED_S))
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#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1
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#define EFUSE_CHIP_CPU_FREQ_RATED_S 13
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/* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */
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/*description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/
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#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12))
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#define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_CHIP_CPU_FREQ_LOW_S))
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#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1
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#define EFUSE_CHIP_CPU_FREQ_LOW_S 12
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/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
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/*description: */
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#define EFUSE_CHIP_VER_PKG 0x00000007
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#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S))
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#define EFUSE_CHIP_VER_PKG_V 0x7
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#define EFUSE_CHIP_VER_PKG_S 9
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#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0
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#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1
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#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2
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#define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4
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#define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5
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/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */
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/*description: program for SPI_pad_config_hd*/
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#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F
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@ -382,6 +420,15 @@
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#define EFUSE_XPD_SDIO_REG_M (BIT(14))
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#define EFUSE_XPD_SDIO_REG_V 0x1
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#define EFUSE_XPD_SDIO_REG_S 14
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/* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */
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/*description: True ADC reference voltage */
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#define EFUSE_ADC_VREF 0x0000001F
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#define EFUSE_ADC_VREF_M ((EFUSE_ADC_VREF_V)<<(EFUSE_ADC_VREF_S))
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#define EFUSE_ADC_VREF_V 0x1F
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#define EFUSE_ADC_VREF_S 8
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/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer
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* versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore
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* SDIO_DREFH/M/L is only available in older versions of ESP32 */
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/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
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/*description: */
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#define EFUSE_SDIO_DREFL 0x00000003
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@ -659,6 +706,8 @@
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#define EFUSE_BLK3_DOUT2_V 0xFFFFFFFF
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#define EFUSE_BLK3_DOUT2_S 0
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/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration
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* purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/
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#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084)
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/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: read for BLOCK3*/
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@ -666,6 +715,30 @@
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#define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S))
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#define EFUSE_BLK3_DOUT3_V 0xFFFFFFFF
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#define EFUSE_BLK3_DOUT3_S 0
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/* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */
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/*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
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#define EFUSE_RD_ADC2_TP_HIGH 0x1FF
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#define EFUSE_RD_ADC2_TP_HIGH_M ((EFUSE_RD_ADC2_TP_HIGH_V)<<(EFUSE_RD_ADC2_TP_HIGH_S))
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#define EFUSE_RD_ADC2_TP_HIGH_V 0x1FF
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#define EFUSE_RD_ADC2_TP_HIGH_S 23
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/* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */
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/*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
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#define EFUSE_RD_ADC2_TP_LOW 0x7F
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#define EFUSE_RD_ADC2_TP_LOW_M ((EFUSE_RD_ADC2_TP_LOW_V)<<(EFUSE_RD_ADC2_TP_LOW_S))
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#define EFUSE_RD_ADC2_TP_LOW_V 0x7F
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#define EFUSE_RD_ADC2_TP_LOW_S 16
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/* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */
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/*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
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#define EFUSE_RD_ADC1_TP_HIGH 0x1FF
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#define EFUSE_RD_ADC1_TP_HIGH_M ((EFUSE_RD_ADC1_TP_HIGH_V)<<(EFUSE_RD_ADC1_TP_HIGH_S))
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#define EFUSE_RD_ADC1_TP_HIGH_V 0x1FF
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#define EFUSE_RD_ADC1_TP_HIGH_S 7
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/* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */
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/*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
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#define EFUSE_RD_ADC1_TP_LOW 0x7F
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#define EFUSE_RD_ADC1_TP_LOW_M ((EFUSE_RD_ADC1_TP_LOW_V)<<(EFUSE_RD_ADC1_TP_LOW_S))
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#define EFUSE_RD_ADC1_TP_LOW_V 0x7F
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#define EFUSE_RD_ADC1_TP_LOW_S 0
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#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088)
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/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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@ -674,6 +747,12 @@
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#define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S))
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#define EFUSE_BLK3_DOUT4_V 0xFFFFFFFF
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#define EFUSE_BLK3_DOUT4_S 0
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/* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */
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/*description: Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE */
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#define EFUSE_RD_CAL_RESERVED 0x0000FFFF
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#define EFUSE_RD_CAL_RESERVED_M ((EFUSE_RD_CAL_RESERVED_V)<<(EFUSE_RD_CAL_RESERVED_S))
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#define EFUSE_RD_CAL_RESERVED_V 0xFFFF
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#define EFUSE_RD_CAL_RESERVED_S 0
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#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c)
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/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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@ -851,6 +930,8 @@
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#define EFUSE_BLK3_DIN2_V 0xFFFFFFFF
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#define EFUSE_BLK3_DIN2_S 0
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/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration
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* purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/
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#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4)
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/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: program for BLOCK3*/
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@ -858,6 +939,30 @@
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#define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S))
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#define EFUSE_BLK3_DIN3_V 0xFFFFFFFF
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#define EFUSE_BLK3_DIN3_S 0
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/* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */
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/*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
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#define EFUSE_ADC2_TP_HIGH 0x1FF
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#define EFUSE_ADC2_TP_HIGH_M ((EFUSE_ADC2_TP_HIGH_V)<<(EFUSE_ADC2_TP_HIGH_S))
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#define EFUSE_ADC2_TP_HIGH_V 0x1FF
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#define EFUSE_ADC2_TP_HIGH_S 23
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/* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */
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/*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
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#define EFUSE_ADC2_TP_LOW 0x7F
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#define EFUSE_ADC2_TP_LOW_M ((EFUSE_ADC2_TP_LOW_V)<<(EFUSE_ADC2_TP_LOW_S))
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#define EFUSE_ADC2_TP_LOW_V 0x7F
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#define EFUSE_ADC2_TP_LOW_S 16
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/* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */
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/*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
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#define EFUSE_ADC1_TP_HIGH 0x1FF
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#define EFUSE_ADC1_TP_HIGH_M ((EFUSE_ADC1_TP_HIGH_V)<<(EFUSE_ADC1_TP_HIGH_S))
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#define EFUSE_ADC1_TP_HIGH_V 0x1FF
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#define EFUSE_ADC1_TP_HIGH_S 7
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/* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */
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/*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
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#define EFUSE_ADC1_TP_LOW 0x7F
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#define EFUSE_ADC1_TP_LOW_M ((EFUSE_ADC1_TP_LOW_V)<<(EFUSE_ADC1_TP_LOW_S))
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#define EFUSE_ADC1_TP_LOW_V 0x7F
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#define EFUSE_ADC1_TP_LOW_S 0
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#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8)
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/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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@ -866,6 +971,12 @@
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#define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S))
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#define EFUSE_BLK3_DIN4_V 0xFFFFFFFF
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#define EFUSE_BLK3_DIN4_S 0
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/* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */
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/*description: Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE */
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#define EFUSE_CAL_RESERVED 0x0000FFFF
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#define EFUSE_CAL_RESERVED_M ((EFUSE_CAL_RESERVED_V)<<(EFUSE_CAL_RESERVED_S))
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#define EFUSE_CAL_RESERVED_V 0xFFFF
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#define EFUSE_CAL_RESERVED_S 0
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#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec)
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/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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@ -124,18 +124,21 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
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#define CLK_OUT1_S 0
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#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44)
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#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
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#define FUNC_GPIO0_EMAC_TX_CLK 5
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#define FUNC_GPIO0_GPIO0 2
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#define FUNC_GPIO0_CLK_OUT1 1
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#define FUNC_GPIO0_GPIO0_0 0
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#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88)
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#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U0TXD_U
|
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#define FUNC_U0TXD_EMAC_RXD2 5
|
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#define FUNC_U0TXD_GPIO1 2
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#define FUNC_U0TXD_CLK_OUT3 1
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#define FUNC_U0TXD_U0TXD 0
|
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|
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#define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40)
|
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#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
|
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#define FUNC_GPIO2_SD_DATA0 4
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#define FUNC_GPIO2_HS2_DATA0 3
|
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#define FUNC_GPIO2_GPIO2 2
|
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@ -143,11 +146,13 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
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#define FUNC_GPIO2_GPIO2_0 0
|
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|
||||
#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84)
|
||||
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U0RXD_U
|
||||
#define FUNC_U0RXD_GPIO3 2
|
||||
#define FUNC_U0RXD_CLK_OUT2 1
|
||||
#define FUNC_U0RXD_U0RXD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48)
|
||||
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U
|
||||
#define FUNC_GPIO4_EMAC_TX_ER 5
|
||||
#define FUNC_GPIO4_SD_DATA1 4
|
||||
#define FUNC_GPIO4_HS2_DATA1 3
|
||||
@ -156,6 +161,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_GPIO4_GPIO4_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c)
|
||||
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U
|
||||
#define FUNC_GPIO5_EMAC_RX_CLK 5
|
||||
#define FUNC_GPIO5_HS1_DATA6 3
|
||||
#define FUNC_GPIO5_GPIO5 2
|
||||
@ -163,6 +169,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_GPIO5_GPIO5_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60)
|
||||
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_SD_CLK_U
|
||||
#define FUNC_SD_CLK_U1CTS 4
|
||||
#define FUNC_SD_CLK_HS1_CLK 3
|
||||
#define FUNC_SD_CLK_GPIO6 2
|
||||
@ -170,6 +177,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_SD_CLK_SD_CLK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA0_U (DR_REG_IO_MUX_BASE +0x64)
|
||||
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_SD_DATA0_U
|
||||
#define FUNC_SD_DATA0_U2RTS 4
|
||||
#define FUNC_SD_DATA0_HS1_DATA0 3
|
||||
#define FUNC_SD_DATA0_GPIO7 2
|
||||
@ -177,6 +185,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_SD_DATA0_SD_DATA0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA1_U (DR_REG_IO_MUX_BASE +0x68)
|
||||
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_SD_DATA1_U
|
||||
#define FUNC_SD_DATA1_U2CTS 4
|
||||
#define FUNC_SD_DATA1_HS1_DATA1 3
|
||||
#define FUNC_SD_DATA1_GPIO8 2
|
||||
@ -184,6 +193,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_SD_DATA1_SD_DATA1 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54)
|
||||
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_SD_DATA2_U
|
||||
#define FUNC_SD_DATA2_U1RXD 4
|
||||
#define FUNC_SD_DATA2_HS1_DATA2 3
|
||||
#define FUNC_SD_DATA2_GPIO9 2
|
||||
@ -191,6 +201,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_SD_DATA2_SD_DATA2 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58)
|
||||
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_SD_DATA3_U
|
||||
#define FUNC_SD_DATA3_U1TXD 4
|
||||
#define FUNC_SD_DATA3_HS1_DATA3 3
|
||||
#define FUNC_SD_DATA3_GPIO10 2
|
||||
@ -198,6 +209,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_SD_DATA3_SD_DATA3 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c)
|
||||
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_SD_CMD_U
|
||||
#define FUNC_SD_CMD_U1RTS 4
|
||||
#define FUNC_SD_CMD_HS1_CMD 3
|
||||
#define FUNC_SD_CMD_GPIO11 2
|
||||
@ -205,6 +217,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_SD_CMD_SD_CMD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34)
|
||||
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_MTDI_U
|
||||
#define FUNC_MTDI_EMAC_TXD3 5
|
||||
#define FUNC_MTDI_SD_DATA2 4
|
||||
#define FUNC_MTDI_HS2_DATA2 3
|
||||
@ -213,6 +226,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_MTDI_MTDI 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38)
|
||||
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_MTCK_U
|
||||
#define FUNC_MTCK_EMAC_RX_ER 5
|
||||
#define FUNC_MTCK_SD_DATA3 4
|
||||
#define FUNC_MTCK_HS2_DATA3 3
|
||||
@ -221,6 +235,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_MTCK_MTCK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30)
|
||||
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_MTMS_U
|
||||
#define FUNC_MTMS_EMAC_TXD2 5
|
||||
#define FUNC_MTMS_SD_CLK 4
|
||||
#define FUNC_MTMS_HS2_CLK 3
|
||||
@ -229,6 +244,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_MTMS_MTMS 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c)
|
||||
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_MTDO_U
|
||||
#define FUNC_MTDO_EMAC_RXD3 5
|
||||
#define FUNC_MTDO_SD_CMD 4
|
||||
#define FUNC_MTDO_HS2_CMD 3
|
||||
@ -237,6 +253,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_MTDO_MTDO 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c)
|
||||
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_GPIO16_U
|
||||
#define FUNC_GPIO16_EMAC_CLK_OUT 5
|
||||
#define FUNC_GPIO16_U2RXD 4
|
||||
#define FUNC_GPIO16_HS1_DATA4 3
|
||||
@ -244,6 +261,7 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_GPIO16_GPIO16_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50)
|
||||
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_GPIO17_U
|
||||
#define FUNC_GPIO17_EMAC_CLK_OUT_180 5
|
||||
#define FUNC_GPIO17_U2TXD 4
|
||||
#define FUNC_GPIO17_HS1_DATA5 3
|
||||
@ -251,12 +269,14 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_GPIO17_GPIO17_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70)
|
||||
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U
|
||||
#define FUNC_GPIO18_HS1_DATA7 3
|
||||
#define FUNC_GPIO18_GPIO18 2
|
||||
#define FUNC_GPIO18_VSPICLK 1
|
||||
#define FUNC_GPIO18_GPIO18_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO19_U (DR_REG_IO_MUX_BASE +0x74)
|
||||
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
|
||||
#define FUNC_GPIO19_EMAC_TXD0 5
|
||||
#define FUNC_GPIO19_U0CTS 3
|
||||
#define FUNC_GPIO19_GPIO19 2
|
||||
@ -264,16 +284,19 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_GPIO19_GPIO19_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO20_U (DR_REG_IO_MUX_BASE +0x78)
|
||||
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
|
||||
#define FUNC_GPIO20_GPIO20 2
|
||||
#define FUNC_GPIO20_GPIO20_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO21_U (DR_REG_IO_MUX_BASE +0x7c)
|
||||
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U
|
||||
#define FUNC_GPIO21_EMAC_TX_EN 5
|
||||
#define FUNC_GPIO21_GPIO21 2
|
||||
#define FUNC_GPIO21_VSPIHD 1
|
||||
#define FUNC_GPIO21_GPIO21_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO22_U (DR_REG_IO_MUX_BASE +0x80)
|
||||
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_GPIO22_U
|
||||
#define FUNC_GPIO22_EMAC_TXD1 5
|
||||
#define FUNC_GPIO22_U0RTS 3
|
||||
#define FUNC_GPIO22_GPIO22 2
|
||||
@ -281,59 +304,72 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
|
||||
#define FUNC_GPIO22_GPIO22_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c)
|
||||
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U
|
||||
#define FUNC_GPIO23_HS1_STROBE 3
|
||||
#define FUNC_GPIO23_GPIO23 2
|
||||
#define FUNC_GPIO23_VSPID 1
|
||||
#define FUNC_GPIO23_GPIO23_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO24_U (DR_REG_IO_MUX_BASE +0x90)
|
||||
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U
|
||||
#define FUNC_GPIO24_GPIO24 2
|
||||
#define FUNC_GPIO24_GPIO24_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24)
|
||||
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U
|
||||
#define FUNC_GPIO25_EMAC_RXD0 5
|
||||
#define FUNC_GPIO25_GPIO25 2
|
||||
#define FUNC_GPIO25_GPIO25_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28)
|
||||
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_GPIO26_U
|
||||
#define FUNC_GPIO26_EMAC_RXD1 5
|
||||
#define FUNC_GPIO26_GPIO26 2
|
||||
#define FUNC_GPIO26_GPIO26_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c)
|
||||
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_GPIO27_U
|
||||
#define FUNC_GPIO27_EMAC_RX_DV 5
|
||||
#define FUNC_GPIO27_GPIO27 2
|
||||
#define FUNC_GPIO27_GPIO27_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c)
|
||||
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_GPIO32_U
|
||||
#define FUNC_GPIO32_GPIO32 2
|
||||
#define FUNC_GPIO32_GPIO32_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20)
|
||||
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
|
||||
#define FUNC_GPIO33_GPIO33 2
|
||||
#define FUNC_GPIO33_GPIO33_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14)
|
||||
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
|
||||
#define FUNC_GPIO34_GPIO34 2
|
||||
#define FUNC_GPIO34_GPIO34_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18)
|
||||
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
|
||||
#define FUNC_GPIO35_GPIO35 2
|
||||
#define FUNC_GPIO35_GPIO35_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04)
|
||||
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
|
||||
#define FUNC_GPIO36_GPIO36 2
|
||||
#define FUNC_GPIO36_GPIO36_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08)
|
||||
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
|
||||
#define FUNC_GPIO37_GPIO37 2
|
||||
#define FUNC_GPIO37_GPIO37_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c)
|
||||
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
|
||||
#define FUNC_GPIO38_GPIO38 2
|
||||
#define FUNC_GPIO38_GPIO38_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10)
|
||||
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_GPIO39_U
|
||||
#define FUNC_GPIO39_GPIO39 2
|
||||
#define FUNC_GPIO39_GPIO39_0 0
|
||||
|
||||
|
||||
@ -185,8 +185,11 @@ bool rtc_clk_32k_enabled();
|
||||
* must be called one the 32k XTAL oscillator has started up. This function
|
||||
* will initially disable the 32k XTAL oscillator, so it should not be called
|
||||
* when the system is using 32k XTAL as RTC_SLOW_CLK.
|
||||
*
|
||||
* @param cycle Number of 32kHz cycles to bootstrap external crystal.
|
||||
* If 0, no square wave will be used to bootstrap crystal oscillation.
|
||||
*/
|
||||
void rtc_clk_32k_bootstrap();
|
||||
void rtc_clk_32k_bootstrap(uint32_t cycle);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 8 MHz internal oscillator
|
||||
@ -604,7 +607,6 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config();
|
||||
*/
|
||||
void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -96,6 +96,7 @@
|
||||
#define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S))
|
||||
#define SENS_FORCE_XPD_SAR_V 0x3
|
||||
#define SENS_FORCE_XPD_SAR_S 18
|
||||
#define SENS_FORCE_XPD_SAR_SW_M (BIT1)
|
||||
#define SENS_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down
|
||||
#define SENS_FORCE_XPD_SAR_PD 2 // Force power down
|
||||
#define SENS_FORCE_XPD_SAR_PU 3 // Force power up
|
||||
|
||||
@ -26,7 +26,7 @@ typedef volatile struct {
|
||||
uint32_t sar1_sample_bit: 2;
|
||||
uint32_t sar1_clk_gated: 1;
|
||||
uint32_t sar1_sample_num: 8;
|
||||
uint32_t sar1_dig_force: 1;
|
||||
uint32_t sar1_dig_force: 1; /*1: ADC1 is controlled by the digital controller 0: RTC controller*/
|
||||
uint32_t sar1_data_inv: 1;
|
||||
uint32_t reserved29: 3;
|
||||
};
|
||||
@ -162,9 +162,9 @@ typedef volatile struct {
|
||||
uint32_t meas1_data_sar: 16;
|
||||
uint32_t meas1_done_sar: 1;
|
||||
uint32_t meas1_start_sar: 1;
|
||||
uint32_t meas1_start_force: 1;
|
||||
uint32_t meas1_start_force: 1; /*1: ADC1 is controlled by the digital or RTC controller 0: Ulp coprocessor*/
|
||||
uint32_t sar1_en_pad: 12;
|
||||
uint32_t sar1_en_pad_force: 1;
|
||||
uint32_t sar1_en_pad_force: 1; /*1: Data ports are controlled by the digital or RTC controller 0: Ulp coprocessor*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_start1;
|
||||
@ -174,8 +174,8 @@ typedef volatile struct {
|
||||
uint32_t touch_xpd_wait: 8;
|
||||
uint32_t touch_out_sel: 1;
|
||||
uint32_t touch_out_1en: 1;
|
||||
uint32_t xpd_hall_force: 1;
|
||||
uint32_t hall_phase_force: 1;
|
||||
uint32_t xpd_hall_force: 1; /*1: Power of hall sensor is controlled by the digital or RTC controller 0: Ulp coprocessor*/
|
||||
uint32_t hall_phase_force: 1; /*1: Phase of hall sensor is controlled by the digital or RTC controller 0: Ulp coprocessor*/
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -224,8 +224,8 @@ typedef volatile struct {
|
||||
uint32_t sar2_sample_bit: 2;
|
||||
uint32_t sar2_clk_gated: 1;
|
||||
uint32_t sar2_sample_num: 8;
|
||||
uint32_t sar2_pwdet_force: 1;
|
||||
uint32_t sar2_dig_force: 1;
|
||||
uint32_t sar2_pwdet_force: 1; /*1: ADC2 is controlled by PWDET 0: digital or RTC controller*/
|
||||
uint32_t sar2_dig_force: 1; /*1: ADC2 is controlled by the digital controller 0: RTC controller*/
|
||||
uint32_t sar2_data_inv: 1;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
@ -236,9 +236,9 @@ typedef volatile struct {
|
||||
uint32_t meas2_data_sar: 16;
|
||||
uint32_t meas2_done_sar: 1;
|
||||
uint32_t meas2_start_sar: 1;
|
||||
uint32_t meas2_start_force: 1;
|
||||
uint32_t meas2_start_force: 1; /*1: ADC2 is controlled by the digital or RTC controller 0: Ulp coprocessor*/
|
||||
uint32_t sar2_en_pad: 12;
|
||||
uint32_t sar2_en_pad_force: 1;
|
||||
uint32_t sar2_en_pad_force: 1; /*1: Data ports are controlled by the digital or RTC controller 0: Ulp coprocessor*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_start2;
|
||||
|
||||
@ -308,7 +308,6 @@
|
||||
#define SOC_MEM_INTERNAL_LOW 0x3FF90000
|
||||
#define SOC_MEM_INTERNAL_HIGH 0x400C2000
|
||||
|
||||
|
||||
//Interrupt hardware source table
|
||||
//This table is decided by hardware, don't touch this.
|
||||
#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
|
||||
|
||||
@ -89,3 +89,8 @@ inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
|
||||
r |= ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
||||
inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) {
|
||||
return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user