Add analogRead, touchRead, dacWrite and updated esp-idf

tools/sdk/include/esp32/esp_coexist.h

@@ -0,0 +1,46 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Init software coexist
+ *
+ * @return Init ok or failed.
+ */
+esp_err_t coex_init(void);
+
+/**
+ * @brief Get software coexist enable or not
+ *
+ * @return software coexist enable status.
+ */
+bool coexist_get_enable(void);
+
+/**
+ * @brief Set software coexist enable or not
+ *
+ * @param enable software coexist or disable it
+ *
+ * @return Void.
+ */
+void coexist_set_enable(bool enable);
+
+#ifdef __cplusplus
+}
+#endif

tools/sdk/include/esp32/rom/uart.h

@@ -18,6 +18,8 @@
 #include "esp_types.h"
 #include "esp_attr.h"
 #include "ets_sys.h"
+#include "soc/soc.h"
+#include "soc/uart_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -260,11 +262,16 @@ void uart_tx_flush(uint8_t uart_no);
 /**
   * @brief Wait until uart tx full empty and the last char send ok.
   *
-  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  * @param  uart_no : 0 for UART0, 1 for UART1, 2 for UART2
   *
-  * @return None.
+  * The function defined in ROM code has a bug, so we define the correct version
+  * here for compatibility.
   */
-void uart_tx_wait_idle(uint8_t uart_no);
+static inline void uart_tx_wait_idle(uint8_t uart_no) {
+    while(REG_GET_FIELD(UART_STATUS_REG(uart_no), UART_ST_UTX_OUT)) {
+        ;
+    }
+}
 
 /**
   * @brief Get an input char from message channel.

tools/sdk/include/esp32/soc/soc.h

@@ -153,7 +153,7 @@
 #define DR_REG_FRC_TIMER_BASE                   0x3ff47000
 #define DR_REG_RTCCNTL_BASE                     0x3ff48000
 #define DR_REG_RTCIO_BASE                       0x3ff48400
-#define DR_REG_SARADC_BASE                      0x3ff48800
+#define DR_REG_SENS_BASE                      0x3ff48800
 #define DR_REG_IO_MUX_BASE                      0x3ff49000
 #define DR_REG_RTCMEM0_BASE                     0x3ff61000
 #define DR_REG_RTCMEM1_BASE                     0x3ff62000
@@ -213,10 +213,10 @@
 #define ETS_TG1_LACT_LEVEL_INTR_SOURCE          21/**< interrupt of TIMER_GROUP1, LACT, level*/
 #define ETS_GPIO_INTR_SOURCE                    22/**< interrupt of GPIO, level*/
 #define ETS_GPIO_NMI_SOURCE                     23/**< interrupt of GPIO, NMI*/
-#define ETS_FROM_CPU_INTR0_SOURCE               24/**< interrupt0 generated from a CPU, level*/
-#define ETS_FROM_CPU_INTR1_SOURCE               25/**< interrupt1 generated from a CPU, level*/
-#define ETS_FROM_CPU_INTR2_SOURCE               26/**< interrupt2 generated from a CPU, level*/
-#define ETS_FROM_CPU_INTR3_SOURCE               27/**< interrupt3 generated from a CPU, level*/
+#define ETS_FROM_CPU_INTR0_SOURCE               24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
+#define ETS_FROM_CPU_INTR1_SOURCE               25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
+#define ETS_FROM_CPU_INTR2_SOURCE               26/**< interrupt2 generated from a CPU, level*/ /* Used for VHCI */
+#define ETS_FROM_CPU_INTR3_SOURCE               27/**< interrupt3 generated from a CPU, level*/ /* Reserved */
 #define ETS_SPI0_INTR_SOURCE                    28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
 #define ETS_SPI1_INTR_SOURCE                    29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
 #define ETS_SPI2_INTR_SOURCE                    30/**< interrupt of SPI2, level*/