mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
synced 2025-07-01 04:50:58 +02:00
Set ESP-IDF to 3.2 (#2662)
* Set IDF to v3.2 * Remove BLE submodule * Add BLE lib source * Update Camera example to support OV3660
This commit is contained in:
Me No Dev
GitHub
@ -14,8 +14,6 @@
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#ifndef _SOC_APB_CTRL_STRUCT_H_
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#define _SOC_APB_CTRL_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -14,8 +14,6 @@
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#ifndef _SOC_CAN_STRUCT_H_
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#define _SOC_CAN_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -205,28 +205,12 @@
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#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S))
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#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF
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#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28
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/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */
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/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO)
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BIT[27] is the sign bit, 0: + , 1: -
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BIT[26:24] is the difference value, unit: 0.017V
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volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */
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#define EFUSE_RD_DIG_VOL_L6 0x0F
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#define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S))
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#define EFUSE_RD_DIG_VOL_L6_V 0x0F
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#define EFUSE_RD_DIG_VOL_L6_S 24
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/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */
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/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.
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0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/
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#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03
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#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S))
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#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03
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#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22
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/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */
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/* Deprecated */
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#define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/
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#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/
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#define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/
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#define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/
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/*description: */
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#define EFUSE_RD_INST_CONFIG 0x000000FF
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#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S))
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#define EFUSE_RD_INST_CONFIG_V 0xFF
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#define EFUSE_RD_INST_CONFIG_S 20
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/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */
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/*description: read for SPI_pad_config_cs0*/
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#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F
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@ -316,7 +300,6 @@
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#define EFUSE_CODING_SCHEME_VAL_NONE 0x0
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#define EFUSE_CODING_SCHEME_VAL_34 0x1
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#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2
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#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c)
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/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[27:20] ;default: 8'b0 ; */
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@ -481,28 +464,12 @@
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#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S))
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#define EFUSE_FLASH_CRYPT_CONFIG_V 0xF
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#define EFUSE_FLASH_CRYPT_CONFIG_S 28
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/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */
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/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W)
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BIT[27] is the sign bit, 0: + , 1: -
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BIT[26:24] is the difference value, unit: 0.017V
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volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */
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#define EFUSE_DIG_VOL_L6 0x0F
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#define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S))
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#define EFUSE_DIG_VOL_L6_V 0x0F
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#define EFUSE_DIG_VOL_L6_S 24
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/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */
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/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.
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0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/
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#define EFUSE_VOL_LEVEL_HP_INV 0x03
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#define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S))
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#define EFUSE_VOL_LEVEL_HP_INV_V 0x03
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#define EFUSE_VOL_LEVEL_HP_INV_S 22
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/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */
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/* Deprecated */
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#define EFUSE_INST_CONFIG 0x000000FF /** Deprecated **/
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#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) /** Deprecated **/
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#define EFUSE_INST_CONFIG_V 0xFF /** Deprecated **/
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#define EFUSE_INST_CONFIG_S 20 /** Deprecated **/
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/*description: */
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#define EFUSE_INST_CONFIG 0x000000FF
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#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S))
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#define EFUSE_INST_CONFIG_V 0xFF
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#define EFUSE_INST_CONFIG_S 20
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/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */
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/*description: program for SPI_pad_config_cs0*/
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#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F
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@ -14,8 +14,6 @@
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#ifndef _SOC_GPIO_SD_STRUCT_H_
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#define _SOC_GPIO_SD_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -14,8 +14,6 @@
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#ifndef _SOC_GPIO_STRUCT_H_
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#define _SOC_GPIO_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -14,8 +14,6 @@
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#ifndef _SOC_HINF_STRUCT_H_
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#define _SOC_HINF_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -14,8 +14,6 @@
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#ifndef _SOC_HOST_STRUCT_H_
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#define _SOC_HOST_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -14,8 +14,6 @@
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#ifndef _SOC_I2C_STRUCT_H_
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#define _SOC_I2C_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -14,8 +14,6 @@
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#ifndef _SOC_I2S_STRUCT_H_
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#define _SOC_I2S_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -1469,15 +1469,10 @@
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/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in high speed
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timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/
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#define LEDC_HSTIMER0_DUTY_RES 0x0000001F
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#define LEDC_HSTIMER0_DUTY_RES_M ((LEDC_HSTIMER0_DUTY_RES_V)<<(LEDC_HSTIMER0_DUTY_RES_S))
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#define LEDC_HSTIMER0_DUTY_RES_V 0x1F
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#define LEDC_HSTIMER0_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_HSTIMER0_LIM LEDC_HSTIMER0_DUTY_RES
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#define LEDC_HSTIMER0_LIM_M LEDC_HSTIMER0_DUTY_RES_M
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#define LEDC_HSTIMER0_LIM_V LEDC_HSTIMER0_DUTY_RES_V
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#define LEDC_HSTIMER0_LIM_S LEDC_HSTIMER0_DUTY_RES_S
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#define LEDC_HSTIMER0_LIM 0x0000001F
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#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S))
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#define LEDC_HSTIMER0_LIM_V 0x1F
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#define LEDC_HSTIMER0_LIM_S 0
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#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144)
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/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1518,15 +1513,10 @@
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/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in high speed
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timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/
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#define LEDC_HSTIMER1_DUTY_RES 0x0000001F
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#define LEDC_HSTIMER1_DUTY_RES_M ((LEDC_HSTIMER1_DUTY_RES_V)<<(LEDC_HSTIMER1_DUTY_RES_S))
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#define LEDC_HSTIMER1_DUTY_RES_V 0x1F
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#define LEDC_HSTIMER1_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_HSTIMER1_LIM LEDC_HSTIMER1_DUTY_RES
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#define LEDC_HSTIMER1_LIM_M LEDC_HSTIMER1_DUTY_RES_M
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#define LEDC_HSTIMER1_LIM_V LEDC_HSTIMER1_DUTY_RES_V
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#define LEDC_HSTIMER1_LIM_S LEDC_HSTIMER1_DUTY_RES_S
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#define LEDC_HSTIMER1_LIM 0x0000001F
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#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S))
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#define LEDC_HSTIMER1_LIM_V 0x1F
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#define LEDC_HSTIMER1_LIM_S 0
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#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C)
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/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1567,15 +1557,10 @@
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/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in high speed
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timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/
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#define LEDC_HSTIMER2_DUTY_RES 0x0000001F
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#define LEDC_HSTIMER2_DUTY_RES_M ((LEDC_HSTIMER2_DUTY_RES_V)<<(LEDC_HSTIMER2_DUTY_RES_S))
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#define LEDC_HSTIMER2_DUTY_RES_V 0x1F
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#define LEDC_HSTIMER2_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_HSTIMER2_LIM LEDC_HSTIMER2_DUTY_RES
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#define LEDC_HSTIMER2_LIM_M LEDC_HSTIMER2_DUTY_RES_M
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#define LEDC_HSTIMER2_LIM_V LEDC_HSTIMER2_DUTY_RES_V
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#define LEDC_HSTIMER2_LIM_S LEDC_HSTIMER2_DUTY_RES_S
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#define LEDC_HSTIMER2_LIM 0x0000001F
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#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S))
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#define LEDC_HSTIMER2_LIM_V 0x1F
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#define LEDC_HSTIMER2_LIM_S 0
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#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154)
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/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1616,15 +1601,10 @@
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/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in high speed
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timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/
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#define LEDC_HSTIMER3_DUTY_RES 0x0000001F
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#define LEDC_HSTIMER3_DUTY_RES_M ((LEDC_HSTIMER3_DUTY_RES_V)<<(LEDC_HSTIMER3_DUTY_RES_S))
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#define LEDC_HSTIMER3_DUTY_RES_V 0x1F
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#define LEDC_HSTIMER3_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_HSTIMER3_LIM LEDC_HSTIMER3_DUTY_RES
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#define LEDC_HSTIMER3_LIM_M LEDC_HSTIMER3_DUTY_RES_M
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#define LEDC_HSTIMER3_LIM_V LEDC_HSTIMER3_DUTY_RES_V
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#define LEDC_HSTIMER3_LIM_S LEDC_HSTIMER3_DUTY_RES_S
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#define LEDC_HSTIMER3_LIM 0x0000001F
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#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S))
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#define LEDC_HSTIMER3_LIM_V 0x1F
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#define LEDC_HSTIMER3_LIM_S 0
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#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C)
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/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1671,15 +1651,10 @@
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/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in low speed
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timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/
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#define LEDC_LSTIMER0_DUTY_RES 0x0000001F
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#define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
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#define LEDC_LSTIMER0_DUTY_RES_V 0x1F
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#define LEDC_LSTIMER0_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_LSTIMER0_LIM LEDC_LSTIMER0_DUTY_RES
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#define LEDC_LSTIMER0_LIM_M LEDC_LSTIMER0_DUTY_RES_M
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#define LEDC_LSTIMER0_LIM_V LEDC_LSTIMER0_DUTY_RES_V
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#define LEDC_LSTIMER0_LIM_S LEDC_LSTIMER0_DUTY_RES_S
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#define LEDC_LSTIMER0_LIM 0x0000001F
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#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S))
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#define LEDC_LSTIMER0_LIM_V 0x1F
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#define LEDC_LSTIMER0_LIM_S 0
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#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164)
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/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1726,15 +1701,10 @@
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/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in low speed
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timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/
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#define LEDC_LSTIMER1_DUTY_RES 0x0000001F
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#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
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#define LEDC_LSTIMER1_DUTY_RES_V 0x1F
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#define LEDC_LSTIMER1_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_LSTIMER1_LIM LEDC_LSTIMER1_DUTY_RES
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#define LEDC_LSTIMER1_LIM_M LEDC_LSTIMER1_DUTY_RES_M
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#define LEDC_LSTIMER1_LIM_V LEDC_LSTIMER1_DUTY_RES_V
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#define LEDC_LSTIMER1_LIM_S LEDC_LSTIMER1_DUTY_RES_S
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#define LEDC_LSTIMER1_LIM 0x0000001F
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#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S))
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#define LEDC_LSTIMER1_LIM_V 0x1F
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#define LEDC_LSTIMER1_LIM_S 0
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#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C)
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/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1781,15 +1751,10 @@
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/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in low speed
|
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timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/
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#define LEDC_LSTIMER2_DUTY_RES 0x0000001F
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#define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
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#define LEDC_LSTIMER2_DUTY_RES_V 0x1F
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#define LEDC_LSTIMER2_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_LSTIMER2_LIM LEDC_LSTIMER2_DUTY_RES
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#define LEDC_LSTIMER2_LIM_M LEDC_LSTIMER2_DUTY_RES_M
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#define LEDC_LSTIMER2_LIM_V LEDC_LSTIMER2_DUTY_RES_V
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#define LEDC_LSTIMER2_LIM_S LEDC_LSTIMER2_DUTY_RES_S
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#define LEDC_LSTIMER2_LIM 0x0000001F
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#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S))
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#define LEDC_LSTIMER2_LIM_V 0x1F
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#define LEDC_LSTIMER2_LIM_S 0
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#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174)
|
||||
/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
|
||||
@ -1836,15 +1801,10 @@
|
||||
/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
|
||||
/*description: This register controls the range of the counter in low speed
|
||||
timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/
|
||||
#define LEDC_LSTIMER3_DUTY_RES 0x0000001F
|
||||
#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
|
||||
#define LEDC_LSTIMER3_DUTY_RES_V 0x1F
|
||||
#define LEDC_LSTIMER3_DUTY_RES_S 0
|
||||
// Keep the definitions below to be compatible with previous version
|
||||
#define LEDC_LSTIMER3_LIM LEDC_LSTIMER3_DUTY_RES
|
||||
#define LEDC_LSTIMER3_LIM_M LEDC_LSTIMER3_DUTY_RES_M
|
||||
#define LEDC_LSTIMER3_LIM_V LEDC_LSTIMER3_DUTY_RES_V
|
||||
#define LEDC_LSTIMER3_LIM_S LEDC_LSTIMER3_DUTY_RES_S
|
||||
#define LEDC_LSTIMER3_LIM 0x0000001F
|
||||
#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S))
|
||||
#define LEDC_LSTIMER3_LIM_V 0x1F
|
||||
#define LEDC_LSTIMER3_LIM_S 0
|
||||
|
||||
#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C)
|
||||
/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_LEDC_STRUCT_H_
|
||||
#define _SOC_LEDC_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_MCPWM_STRUCT_H__
|
||||
#define _SOC_MCPWM_STRUCT_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_PCNT_STRUCT_H_
|
||||
#define _SOC_PCNT_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -995,60 +995,6 @@
|
||||
#define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S))
|
||||
#define RMT_STATUS_CH0_V 0xFFFFFFFF
|
||||
#define RMT_STATUS_CH0_S 0
|
||||
/* RMT_APB_MEM_RD_ERR_CH0 : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: The apb read memory status bit for channel0 turns to
|
||||
high level when the apb read address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_RD_ERR_CH0 (BIT(31))
|
||||
#define RMT_APB_MEM_RD_ERR_CH0_M ((RMT_APB_MEM_RD_ERR_CH0_V)<<(RMT_APB_MEM_RD_ERR_CH0_S))
|
||||
#define RMT_APB_MEM_RD_ERR_CH0_V 0x1
|
||||
#define RMT_APB_MEM_RD_ERR_CH0_S 31
|
||||
/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: The apb write memory status bit for channel0 turns to
|
||||
high level when the apb write address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_WR_ERR_CH0 (BIT(30))
|
||||
#define RMT_APB_MEM_WR_ERR_CH0_M ((RMT_APB_MEM_WR_ERR_CH0_V)<<(RMT_APB_MEM_WR_ERR_CH0_S))
|
||||
#define RMT_APB_MEM_WR_ERR_CH0_V 0x1
|
||||
#define RMT_APB_MEM_WR_ERR_CH0_S 30
|
||||
/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: The memory empty status bit for channel0. in acyclic mode,
|
||||
this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
|
||||
#define RMT_MEM_EMPTY_CH0 (BIT(29))
|
||||
#define RMT_MEM_EMPTY_CH0_M ((RMT_MEM_EMPTY_CH0_V)<<(RMT_MEM_EMPTY_CH0_S))
|
||||
#define RMT_MEM_EMPTY_CH0_V 0x1
|
||||
#define RMT_MEM_EMPTY_CH0_S 29
|
||||
/* RMT_MEM_FULL_CH0 : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: The memory full status bit for channel0 turns to high level
|
||||
when mem_waddr_ex is greater than or equal to the configuration range.*/
|
||||
#define RMT_MEM_FULL_CH0 (BIT(28))
|
||||
#define RMT_MEM_FULL_CH0_M ((RMT_MEM_FULL_CH0_V)<<(RMT_MEM_FULL_CH0_S))
|
||||
#define RMT_MEM_FULL_CH0_V 0x1
|
||||
#define RMT_MEM_FULL_CH0_S 28
|
||||
/* RMT_MEM_OWNER_ERR_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: When channel0 is configured for receive mode, this bit will turn to high level
|
||||
if rmt_mem_owner register is not set to 1.*/
|
||||
#define RMT_MEM_OWNER_ERR_CH0 (BIT(27))
|
||||
#define RMT_MEM_OWNER_ERR_CH0_M ((RMT_MEM_OWNER_ERR_CH0_V)<<(RMT_MEM_OWNER_ERR_CH0_S))
|
||||
#define RMT_MEM_OWNER_ERR_CH0_V 0x1
|
||||
#define RMT_MEM_OWNER_ERR_CH0_S 27
|
||||
/* RMT_STATE_CH0 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
|
||||
/*description: The channel0 state machine status register.
|
||||
3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
|
||||
#define RMT_STATE_CH0 0x07000000
|
||||
#define RMT_STATE_CH0_M ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S))
|
||||
#define RMT_STATE_CH0_V 0x7
|
||||
#define RMT_STATE_CH0_S 24
|
||||
/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
|
||||
/*description: The current memory write address of channel0.*/
|
||||
#define RMT_MEM_RADDR_EX_CH0 0x003ff000
|
||||
#define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S))
|
||||
#define RMT_MEM_RADDR_EX_CH0_V 0x3ff
|
||||
#define RMT_MEM_RADDR_EX_CH0_S 12
|
||||
/* RMT_MEM_WADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
|
||||
/*description: The current memory read address of channel0.*/
|
||||
#define RMT_MEM_WADDR_EX_CH0 0x000003ff
|
||||
#define RMT_MEM_WADDR_EX_CH0_M ((RMT_MEM_WADDR_EX_CH0_V)<<(RMT_MEM_WADDR_EX_CH0_S))
|
||||
#define RMT_MEM_WADDR_EX_CH0_V 0x3ff
|
||||
#define RMT_MEM_WADDR_EX_CH0_S 0
|
||||
|
||||
#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064)
|
||||
/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
@ -1057,60 +1003,6 @@
|
||||
#define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S))
|
||||
#define RMT_STATUS_CH1_V 0xFFFFFFFF
|
||||
#define RMT_STATUS_CH1_S 0
|
||||
/* RMT_APB_MEM_RD_ERR_CH1 : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: The apb read memory status bit for channel1 turns to
|
||||
high level when the apb read address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_RD_ERR_CH1 (BIT(31))
|
||||
#define RMT_APB_MEM_RD_ERR_CH1_M ((RMT_APB_MEM_RD_ERR_CH1_V)<<(RMT_APB_MEM_RD_ERR_CH1_S))
|
||||
#define RMT_APB_MEM_RD_ERR_CH1_V 0x1
|
||||
#define RMT_APB_MEM_RD_ERR_CH1_S 31
|
||||
/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: The apb write memory status bit for channel1 turns to
|
||||
high level when the apb write address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_WR_ERR_CH1 (BIT(30))
|
||||
#define RMT_APB_MEM_WR_ERR_CH1_M ((RMT_APB_MEM_WR_ERR_CH1_V)<<(RMT_APB_MEM_WR_ERR_CH1_S))
|
||||
#define RMT_APB_MEM_WR_ERR_CH1_V 0x1
|
||||
#define RMT_APB_MEM_WR_ERR_CH1_S 30
|
||||
/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: The memory empty status bit for channel1. in acyclic mode,
|
||||
this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
|
||||
#define RMT_MEM_EMPTY_CH1 (BIT(29))
|
||||
#define RMT_MEM_EMPTY_CH1_M ((RMT_MEM_EMPTY_CH1_V)<<(RMT_MEM_EMPTY_CH1_S))
|
||||
#define RMT_MEM_EMPTY_CH1_V 0x1
|
||||
#define RMT_MEM_EMPTY_CH1_S 29
|
||||
/* RMT_MEM_FULL_CH1 : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: The memory full status bit for channel1 turns to high level
|
||||
when mem_waddr_ex is greater than or equal to the configuration range.*/
|
||||
#define RMT_MEM_FULL_CH1 (BIT(28))
|
||||
#define RMT_MEM_FULL_CH1_M ((RMT_MEM_FULL_CH1_V)<<(RMT_MEM_FULL_CH1_S))
|
||||
#define RMT_MEM_FULL_CH1_V 0x1
|
||||
#define RMT_MEM_FULL_CH1_S 28
|
||||
/* RMT_MEM_OWNER_ERR_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: When channel1 is configured for receive mode, this bit will turn to high level
|
||||
if rmt_mem_owner register is not set to 1.*/
|
||||
#define RMT_MEM_OWNER_ERR_CH1 (BIT(27))
|
||||
#define RMT_MEM_OWNER_ERR_CH1_M ((RMT_MEM_OWNER_ERR_CH1_V)<<(RMT_MEM_OWNER_ERR_CH1_S))
|
||||
#define RMT_MEM_OWNER_ERR_CH1_V 0x1
|
||||
#define RMT_MEM_OWNER_ERR_CH1_S 27
|
||||
/* RMT_STATE_CH1 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
|
||||
/*description: The channel1 state machine status register.
|
||||
3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
|
||||
#define RMT_STATE_CH1 0x07000000
|
||||
#define RMT_STATE_CH1_M ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S))
|
||||
#define RMT_STATE_CH1_V 0x7
|
||||
#define RMT_STATE_CH1_S 24
|
||||
/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
|
||||
/*description: The current memory write address of channel1.*/
|
||||
#define RMT_MEM_RADDR_EX_CH1 0x003ff000
|
||||
#define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S))
|
||||
#define RMT_MEM_RADDR_EX_CH1_V 0x3ff
|
||||
#define RMT_MEM_RADDR_EX_CH1_S 12
|
||||
/* RMT_MEM_WADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
|
||||
/*description: The current memory read address of channel1.*/
|
||||
#define RMT_MEM_WADDR_EX_CH1 0x000003ff
|
||||
#define RMT_MEM_WADDR_EX_CH1_M ((RMT_MEM_WADDR_EX_CH1_V)<<(RMT_MEM_WADDR_EX_CH1_S))
|
||||
#define RMT_MEM_WADDR_EX_CH1_V 0x3ff
|
||||
#define RMT_MEM_WADDR_EX_CH1_S 0
|
||||
|
||||
#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068)
|
||||
/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
@ -1119,60 +1011,6 @@
|
||||
#define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S))
|
||||
#define RMT_STATUS_CH2_V 0xFFFFFFFF
|
||||
#define RMT_STATUS_CH2_S 0
|
||||
/* RMT_APB_MEM_RD_ERR_CH2 : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: The apb read memory status bit for channel2 turns to
|
||||
high level when the apb read address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_RD_ERR_CH2 (BIT(31))
|
||||
#define RMT_APB_MEM_RD_ERR_CH2_M ((RMT_APB_MEM_RD_ERR_CH2_V)<<(RMT_APB_MEM_RD_ERR_CH2_S))
|
||||
#define RMT_APB_MEM_RD_ERR_CH2_V 0x1
|
||||
#define RMT_APB_MEM_RD_ERR_CH2_S 31
|
||||
/* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: The apb write memory status bit for channel2 turns to
|
||||
high level when the apb write address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_WR_ERR_CH2 (BIT(30))
|
||||
#define RMT_APB_MEM_WR_ERR_CH2_M ((RMT_APB_MEM_WR_ERR_CH2_V)<<(RMT_APB_MEM_WR_ERR_CH2_S))
|
||||
#define RMT_APB_MEM_WR_ERR_CH2_V 0x1
|
||||
#define RMT_APB_MEM_WR_ERR_CH2_S 30
|
||||
/* RMT_MEM_EMPTY_CH2 : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: The memory empty status bit for channel2. in acyclic mode,
|
||||
this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
|
||||
#define RMT_MEM_EMPTY_CH2 (BIT(29))
|
||||
#define RMT_MEM_EMPTY_CH2_M ((RMT_MEM_EMPTY_CH2_V)<<(RMT_MEM_EMPTY_CH2_S))
|
||||
#define RMT_MEM_EMPTY_CH2_V 0x1
|
||||
#define RMT_MEM_EMPTY_CH2_S 29
|
||||
/* RMT_MEM_FULL_CH2 : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: The memory full status bit for channel2 turns to high level
|
||||
when mem_waddr_ex is greater than or equal to the configuration range.*/
|
||||
#define RMT_MEM_FULL_CH2 (BIT(28))
|
||||
#define RMT_MEM_FULL_CH2_M ((RMT_MEM_FULL_CH2_V)<<(RMT_MEM_FULL_CH2_S))
|
||||
#define RMT_MEM_FULL_CH2_V 0x1
|
||||
#define RMT_MEM_FULL_CH2_S 28
|
||||
/* RMT_MEM_OWNER_ERR_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: When channel2 is configured for receive mode, this bit will turn to high level
|
||||
if rmt_mem_owner register is not set to 1.*/
|
||||
#define RMT_MEM_OWNER_ERR_CH2 (BIT(27))
|
||||
#define RMT_MEM_OWNER_ERR_CH2_M ((RMT_MEM_OWNER_ERR_CH2_V)<<(RMT_MEM_OWNER_ERR_CH2_S))
|
||||
#define RMT_MEM_OWNER_ERR_CH2_V 0x1
|
||||
#define RMT_MEM_OWNER_ERR_CH2_S 27
|
||||
/* RMT_STATE_CH2 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
|
||||
/*description: The channel2 state machine status register.
|
||||
3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
|
||||
#define RMT_STATE_CH2 0x07000000
|
||||
#define RMT_STATE_CH2_M ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S))
|
||||
#define RMT_STATE_CH2_V 0x7
|
||||
#define RMT_STATE_CH2_S 24
|
||||
/* RMT_MEM_RADDR_EX_CH2 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
|
||||
/*description: The current memory write address of channel2.*/
|
||||
#define RMT_MEM_RADDR_EX_CH2 0x003ff000
|
||||
#define RMT_MEM_RADDR_EX_CH2_M ((RMT_MEM_RADDR_EX_CH2_V)<<(RMT_MEM_RADDR_EX_CH2_S))
|
||||
#define RMT_MEM_RADDR_EX_CH2_V 0x3ff
|
||||
#define RMT_MEM_RADDR_EX_CH2_S 12
|
||||
/* RMT_MEM_WADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
|
||||
/*description: The current memory read address of channel2.*/
|
||||
#define RMT_MEM_WADDR_EX_CH2 0x000003ff
|
||||
#define RMT_MEM_WADDR_EX_CH2_M ((RMT_MEM_WADDR_EX_CH2_V)<<(RMT_MEM_WADDR_EX_CH2_S))
|
||||
#define RMT_MEM_WADDR_EX_CH2_V 0x3ff
|
||||
#define RMT_MEM_WADDR_EX_CH2_S 0
|
||||
|
||||
#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c)
|
||||
/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
@ -1181,60 +1019,6 @@
|
||||
#define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S))
|
||||
#define RMT_STATUS_CH3_V 0xFFFFFFFF
|
||||
#define RMT_STATUS_CH3_S 0
|
||||
/* RMT_APB_MEM_RD_ERR_CH3 : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: The apb read memory status bit for channel3 turns to
|
||||
high level when the apb read address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_RD_ERR_CH3 (BIT(31))
|
||||
#define RMT_APB_MEM_RD_ERR_CH3_M ((RMT_APB_MEM_RD_ERR_CH3_V)<<(RMT_APB_MEM_RD_ERR_CH3_S))
|
||||
#define RMT_APB_MEM_RD_ERR_CH3_V 0x1
|
||||
#define RMT_APB_MEM_RD_ERR_CH3_S 31
|
||||
/* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: The apb write memory status bit for channel3 turns to
|
||||
high level when the apb write address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_WR_ERR_CH3 (BIT(30))
|
||||
#define RMT_APB_MEM_WR_ERR_CH3_M ((RMT_APB_MEM_WR_ERR_CH3_V)<<(RMT_APB_MEM_WR_ERR_CH3_S))
|
||||
#define RMT_APB_MEM_WR_ERR_CH3_V 0x1
|
||||
#define RMT_APB_MEM_WR_ERR_CH3_S 30
|
||||
/* RMT_MEM_EMPTY_CH3 : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: The memory empty status bit for channel3. in acyclic mode,
|
||||
this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
|
||||
#define RMT_MEM_EMPTY_CH3 (BIT(29))
|
||||
#define RMT_MEM_EMPTY_CH3_M ((RMT_MEM_EMPTY_CH3_V)<<(RMT_MEM_EMPTY_CH3_S))
|
||||
#define RMT_MEM_EMPTY_CH3_V 0x1
|
||||
#define RMT_MEM_EMPTY_CH3_S 29
|
||||
/* RMT_MEM_FULL_CH3 : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: The memory full status bit for channel3 turns to high level
|
||||
when mem_waddr_ex is greater than or equal to the configuration range.*/
|
||||
#define RMT_MEM_FULL_CH3 (BIT(28))
|
||||
#define RMT_MEM_FULL_CH3_M ((RMT_MEM_FULL_CH3_V)<<(RMT_MEM_FULL_CH3_S))
|
||||
#define RMT_MEM_FULL_CH3_V 0x1
|
||||
#define RMT_MEM_FULL_CH3_S 28
|
||||
/* RMT_MEM_OWNER_ERR_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: When channel3 is configured for receive mode, this bit will turn to high level
|
||||
if rmt_mem_owner register is not set to 1.*/
|
||||
#define RMT_MEM_OWNER_ERR_CH3 (BIT(27))
|
||||
#define RMT_MEM_OWNER_ERR_CH3_M ((RMT_MEM_OWNER_ERR_CH3_V)<<(RMT_MEM_OWNER_ERR_CH3_S))
|
||||
#define RMT_MEM_OWNER_ERR_CH3_V 0x1
|
||||
#define RMT_MEM_OWNER_ERR_CH3_S 27
|
||||
/* RMT_STATE_CH3 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
|
||||
/*description: The channel3 state machine status register.
|
||||
3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
|
||||
#define RMT_STATE_CH3 0x07000000
|
||||
#define RMT_STATE_CH3_M ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S))
|
||||
#define RMT_STATE_CH3_V 0x7
|
||||
#define RMT_STATE_CH3_S 24
|
||||
/* RMT_MEM_RADDR_EX_CH3 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
|
||||
/*description: The current memory write address of channel3.*/
|
||||
#define RMT_MEM_RADDR_EX_CH3 0x003ff000
|
||||
#define RMT_MEM_RADDR_EX_CH3_M ((RMT_MEM_RADDR_EX_CH3_V)<<(RMT_MEM_RADDR_EX_CH3_S))
|
||||
#define RMT_MEM_RADDR_EX_CH3_V 0x3ff
|
||||
#define RMT_MEM_RADDR_EX_CH3_S 12
|
||||
/* RMT_MEM_WADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
|
||||
/*description: The current memory read address of channel3.*/
|
||||
#define RMT_MEM_WADDR_EX_CH3 0x000003ff
|
||||
#define RMT_MEM_WADDR_EX_CH3_M ((RMT_MEM_WADDR_EX_CH3_V)<<(RMT_MEM_WADDR_EX_CH3_S))
|
||||
#define RMT_MEM_WADDR_EX_CH3_V 0x3ff
|
||||
#define RMT_MEM_WADDR_EX_CH3_S 0
|
||||
|
||||
#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070)
|
||||
/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
@ -1243,60 +1027,6 @@
|
||||
#define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S))
|
||||
#define RMT_STATUS_CH4_V 0xFFFFFFFF
|
||||
#define RMT_STATUS_CH4_S 0
|
||||
/* RMT_APB_MEM_RD_ERR_CH4 : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: The apb read memory status bit for channel4 turns to
|
||||
high level when the apb read address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_RD_ERR_CH4 (BIT(31))
|
||||
#define RMT_APB_MEM_RD_ERR_CH4_M ((RMT_APB_MEM_RD_ERR_CH4_V)<<(RMT_APB_MEM_RD_ERR_CH4_S))
|
||||
#define RMT_APB_MEM_RD_ERR_CH4_V 0x1
|
||||
#define RMT_APB_MEM_RD_ERR_CH4_S 31
|
||||
/* RMT_APB_MEM_WR_ERR_CH4 : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: The apb write memory status bit for channel4 turns to
|
||||
high level when the apb write address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_WR_ERR_CH4 (BIT(30))
|
||||
#define RMT_APB_MEM_WR_ERR_CH4_M ((RMT_APB_MEM_WR_ERR_CH4_V)<<(RMT_APB_MEM_WR_ERR_CH4_S))
|
||||
#define RMT_APB_MEM_WR_ERR_CH4_V 0x1
|
||||
#define RMT_APB_MEM_WR_ERR_CH4_S 30
|
||||
/* RMT_MEM_EMPTY_CH4 : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: The memory empty status bit for channel4. in acyclic mode,
|
||||
this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
|
||||
#define RMT_MEM_EMPTY_CH4 (BIT(29))
|
||||
#define RMT_MEM_EMPTY_CH4_M ((RMT_MEM_EMPTY_CH4_V)<<(RMT_MEM_EMPTY_CH4_S))
|
||||
#define RMT_MEM_EMPTY_CH4_V 0x1
|
||||
#define RMT_MEM_EMPTY_CH4_S 29
|
||||
/* RMT_MEM_FULL_CH4 : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: The memory full status bit for channel4 turns to high level
|
||||
when mem_waddr_ex is greater than or equal to the configuration range.*/
|
||||
#define RMT_MEM_FULL_CH4 (BIT(28))
|
||||
#define RMT_MEM_FULL_CH4_M ((RMT_MEM_FULL_CH4_V)<<(RMT_MEM_FULL_CH4_S))
|
||||
#define RMT_MEM_FULL_CH4_V 0x1
|
||||
#define RMT_MEM_FULL_CH4_S 28
|
||||
/* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: When channel4 is configured for receive mode, this bit will turn to high level
|
||||
if rmt_mem_owner register is not set to 1.*/
|
||||
#define RMT_MEM_OWNER_ERR_CH4 (BIT(27))
|
||||
#define RMT_MEM_OWNER_ERR_CH4_M ((RMT_MEM_OWNER_ERR_CH4_V)<<(RMT_MEM_OWNER_ERR_CH4_S))
|
||||
#define RMT_MEM_OWNER_ERR_CH4_V 0x1
|
||||
#define RMT_MEM_OWNER_ERR_CH4_S 27
|
||||
/* RMT_STATE_CH4 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
|
||||
/*description: The channel4 state machine status register.
|
||||
3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
|
||||
#define RMT_STATE_CH4 0x07000000
|
||||
#define RMT_STATE_CH4_M ((RMT_STATE_CH4_V)<<(RMT_STATE_CH4_S))
|
||||
#define RMT_STATE_CH4_V 0x7
|
||||
#define RMT_STATE_CH4_S 24
|
||||
/* RMT_MEM_RADDR_EX_CH4 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
|
||||
/*description: The current memory write address of channel4.*/
|
||||
#define RMT_MEM_RADDR_EX_CH4 0x003ff000
|
||||
#define RMT_MEM_RADDR_EX_CH4_M ((RMT_MEM_RADDR_EX_CH4_V)<<(RMT_MEM_RADDR_EX_CH4_S))
|
||||
#define RMT_MEM_RADDR_EX_CH4_V 0x3ff
|
||||
#define RMT_MEM_RADDR_EX_CH4_S 12
|
||||
/* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
|
||||
/*description: The current memory read address of channel4.*/
|
||||
#define RMT_MEM_WADDR_EX_CH4 0x000003ff
|
||||
#define RMT_MEM_WADDR_EX_CH4_M ((RMT_MEM_WADDR_EX_CH4_V)<<(RMT_MEM_WADDR_EX_CH4_S))
|
||||
#define RMT_MEM_WADDR_EX_CH4_V 0x3ff
|
||||
#define RMT_MEM_WADDR_EX_CH4_S 0
|
||||
|
||||
#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074)
|
||||
/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
@ -1305,60 +1035,6 @@
|
||||
#define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S))
|
||||
#define RMT_STATUS_CH5_V 0xFFFFFFFF
|
||||
#define RMT_STATUS_CH5_S 0
|
||||
/* RMT_APB_MEM_RD_ERR_CH5 : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: The apb read memory status bit for channel5 turns to
|
||||
high level when the apb read address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_RD_ERR_CH5 (BIT(31))
|
||||
#define RMT_APB_MEM_RD_ERR_CH5_M ((RMT_APB_MEM_RD_ERR_CH5_V)<<(RMT_APB_MEM_RD_ERR_CH5_S))
|
||||
#define RMT_APB_MEM_RD_ERR_CH5_V 0x1
|
||||
#define RMT_APB_MEM_RD_ERR_CH5_S 31
|
||||
/* RMT_APB_MEM_WR_ERR_CH5 : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: The apb write memory status bit for channel5 turns to
|
||||
high level when the apb write address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_WR_ERR_CH5 (BIT(30))
|
||||
#define RMT_APB_MEM_WR_ERR_CH5_M ((RMT_APB_MEM_WR_ERR_CH5_V)<<(RMT_APB_MEM_WR_ERR_CH5_S))
|
||||
#define RMT_APB_MEM_WR_ERR_CH5_V 0x1
|
||||
#define RMT_APB_MEM_WR_ERR_CH5_S 30
|
||||
/* RMT_MEM_EMPTY_CH5 : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: The memory empty status bit for channel5. in acyclic mode,
|
||||
this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
|
||||
#define RMT_MEM_EMPTY_CH5 (BIT(29))
|
||||
#define RMT_MEM_EMPTY_CH5_M ((RMT_MEM_EMPTY_CH5_V)<<(RMT_MEM_EMPTY_CH5_S))
|
||||
#define RMT_MEM_EMPTY_CH5_V 0x1
|
||||
#define RMT_MEM_EMPTY_CH5_S 29
|
||||
/* RMT_MEM_FULL_CH5 : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: The memory full status bit for channel5 turns to high level
|
||||
when mem_waddr_ex is greater than or equal to the configuration range.*/
|
||||
#define RMT_MEM_FULL_CH5 (BIT(28))
|
||||
#define RMT_MEM_FULL_CH5_M ((RMT_MEM_FULL_CH5_V)<<(RMT_MEM_FULL_CH5_S))
|
||||
#define RMT_MEM_FULL_CH5_V 0x1
|
||||
#define RMT_MEM_FULL_CH5_S 28
|
||||
/* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: When channel5 is configured for receive mode, this bit will turn to high level
|
||||
if rmt_mem_owner register is not set to 1.*/
|
||||
#define RMT_MEM_OWNER_ERR_CH5 (BIT(27))
|
||||
#define RMT_MEM_OWNER_ERR_CH5_M ((RMT_MEM_OWNER_ERR_CH5_V)<<(RMT_MEM_OWNER_ERR_CH5_S))
|
||||
#define RMT_MEM_OWNER_ERR_CH5_V 0x1
|
||||
#define RMT_MEM_OWNER_ERR_CH5_S 27
|
||||
/* RMT_STATE_CH5 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
|
||||
/*description: The channel5 state machine status register.
|
||||
3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
|
||||
#define RMT_STATE_CH5 0x07000000
|
||||
#define RMT_STATE_CH5_M ((RMT_STATE_CH5_V)<<(RMT_STATE_CH5_S))
|
||||
#define RMT_STATE_CH5_V 0x7
|
||||
#define RMT_STATE_CH5_S 24
|
||||
/* RMT_MEM_RADDR_EX_CH5 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
|
||||
/*description: The current memory write address of channel5.*/
|
||||
#define RMT_MEM_RADDR_EX_CH5 0x003ff000
|
||||
#define RMT_MEM_RADDR_EX_CH5_M ((RMT_MEM_RADDR_EX_CH5_V)<<(RMT_MEM_RADDR_EX_CH5_S))
|
||||
#define RMT_MEM_RADDR_EX_CH5_V 0x3ff
|
||||
#define RMT_MEM_RADDR_EX_CH5_S 12
|
||||
/* RMT_MEM_WADDR_EX_CH5 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
|
||||
/*description: The current memory read address of channel5.*/
|
||||
#define RMT_MEM_WADDR_EX_CH5 0x000003ff
|
||||
#define RMT_MEM_WADDR_EX_CH5_M ((RMT_MEM_WADDR_EX_CH5_V)<<(RMT_MEM_WADDR_EX_CH5_S))
|
||||
#define RMT_MEM_WADDR_EX_CH5_V 0x3ff
|
||||
#define RMT_MEM_WADDR_EX_CH5_S 0
|
||||
|
||||
#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078)
|
||||
/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
@ -1367,60 +1043,6 @@
|
||||
#define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S))
|
||||
#define RMT_STATUS_CH6_V 0xFFFFFFFF
|
||||
#define RMT_STATUS_CH6_S 0
|
||||
/* RMT_APB_MEM_RD_ERR_CH6 : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: The apb read memory status bit for channel6 turns to
|
||||
high level when the apb read address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_RD_ERR_CH6 (BIT(31))
|
||||
#define RMT_APB_MEM_RD_ERR_CH6_M ((RMT_APB_MEM_RD_ERR_CH6_V)<<(RMT_APB_MEM_RD_ERR_CH6_S))
|
||||
#define RMT_APB_MEM_RD_ERR_CH6_V 0x1
|
||||
#define RMT_APB_MEM_RD_ERR_CH6_S 31
|
||||
/* RMT_APB_MEM_WR_ERR_CH6 : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: The apb write memory status bit for channel6 turns to
|
||||
high level when the apb write address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_WR_ERR_CH6 (BIT(30))
|
||||
#define RMT_APB_MEM_WR_ERR_CH6_M ((RMT_APB_MEM_WR_ERR_CH6_V)<<(RMT_APB_MEM_WR_ERR_CH6_S))
|
||||
#define RMT_APB_MEM_WR_ERR_CH6_V 0x1
|
||||
#define RMT_APB_MEM_WR_ERR_CH6_S 30
|
||||
/* RMT_MEM_EMPTY_CH6 : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: The memory empty status bit for channel6. in acyclic mode,
|
||||
this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
|
||||
#define RMT_MEM_EMPTY_CH6 (BIT(29))
|
||||
#define RMT_MEM_EMPTY_CH6_M ((RMT_MEM_EMPTY_CH6_V)<<(RMT_MEM_EMPTY_CH6_S))
|
||||
#define RMT_MEM_EMPTY_CH6_V 0x1
|
||||
#define RMT_MEM_EMPTY_CH6_S 29
|
||||
/* RMT_MEM_FULL_CH6 : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: The memory full status bit for channel6 turns to high level
|
||||
when mem_waddr_ex is greater than or equal to the configuration range.*/
|
||||
#define RMT_MEM_FULL_CH6 (BIT(28))
|
||||
#define RMT_MEM_FULL_CH6_M ((RMT_MEM_FULL_CH6_V)<<(RMT_MEM_FULL_CH6_S))
|
||||
#define RMT_MEM_FULL_CH6_V 0x1
|
||||
#define RMT_MEM_FULL_CH6_S 28
|
||||
/* RMT_MEM_OWNER_ERR_CH6 : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: When channel6 is configured for receive mode, this bit will turn to high level
|
||||
if rmt_mem_owner register is not set to 1.*/
|
||||
#define RMT_MEM_OWNER_ERR_CH6 (BIT(27))
|
||||
#define RMT_MEM_OWNER_ERR_CH6_M ((RMT_MEM_OWNER_ERR_CH6_V)<<(RMT_MEM_OWNER_ERR_CH6_S))
|
||||
#define RMT_MEM_OWNER_ERR_CH6_V 0x1
|
||||
#define RMT_MEM_OWNER_ERR_CH6_S 27
|
||||
/* RMT_STATE_CH6 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
|
||||
/*description: The channel6 state machine status register.
|
||||
3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
|
||||
#define RMT_STATE_CH6 0x07000000
|
||||
#define RMT_STATE_CH6_M ((RMT_STATE_CH6_V)<<(RMT_STATE_CH6_S))
|
||||
#define RMT_STATE_CH6_V 0x7
|
||||
#define RMT_STATE_CH6_S 24
|
||||
/* RMT_MEM_RADDR_EX_CH6 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
|
||||
/*description: The current memory write address of channel6.*/
|
||||
#define RMT_MEM_RADDR_EX_CH6 0x003ff000
|
||||
#define RMT_MEM_RADDR_EX_CH6_M ((RMT_MEM_RADDR_EX_CH6_V)<<(RMT_MEM_RADDR_EX_CH6_S))
|
||||
#define RMT_MEM_RADDR_EX_CH6_V 0x3ff
|
||||
#define RMT_MEM_RADDR_EX_CH6_S 12
|
||||
/* RMT_MEM_WADDR_EX_CH6 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
|
||||
/*description: The current memory read address of channel6.*/
|
||||
#define RMT_MEM_WADDR_EX_CH6 0x000003ff
|
||||
#define RMT_MEM_WADDR_EX_CH6_M ((RMT_MEM_WADDR_EX_CH6_V)<<(RMT_MEM_WADDR_EX_CH6_S))
|
||||
#define RMT_MEM_WADDR_EX_CH6_V 0x3ff
|
||||
#define RMT_MEM_WADDR_EX_CH6_S 0
|
||||
|
||||
#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c)
|
||||
/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
@ -1429,60 +1051,6 @@
|
||||
#define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S))
|
||||
#define RMT_STATUS_CH7_V 0xFFFFFFFF
|
||||
#define RMT_STATUS_CH7_S 0
|
||||
/* RMT_APB_MEM_RD_ERR_CH7 : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: The apb read memory status bit for channel7 turns to
|
||||
high level when the apb read address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_RD_ERR_CH7 (BIT(31))
|
||||
#define RMT_APB_MEM_RD_ERR_CH7_M ((RMT_APB_MEM_RD_ERR_CH7_V)<<(RMT_APB_MEM_RD_ERR_CH7_S))
|
||||
#define RMT_APB_MEM_RD_ERR_CH7_V 0x1
|
||||
#define RMT_APB_MEM_RD_ERR_CH7_S 31
|
||||
/* RMT_APB_MEM_WR_ERR_CH7 : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: The apb write memory status bit for channel7 turns to
|
||||
high level when the apb write address exceeds the configuration range.*/
|
||||
#define RMT_APB_MEM_WR_ERR_CH7 (BIT(30))
|
||||
#define RMT_APB_MEM_WR_ERR_CH7_M ((RMT_APB_MEM_WR_ERR_CH7_V)<<(RMT_APB_MEM_WR_ERR_CH7_S))
|
||||
#define RMT_APB_MEM_WR_ERR_CH7_V 0x1
|
||||
#define RMT_APB_MEM_WR_ERR_CH7_S 30
|
||||
/* RMT_MEM_EMPTY_CH7 : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: The memory empty status bit for channel7. in acyclic mode,
|
||||
this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
|
||||
#define RMT_MEM_EMPTY_CH7 (BIT(29))
|
||||
#define RMT_MEM_EMPTY_CH7_M ((RMT_MEM_EMPTY_CH7_V)<<(RMT_MEM_EMPTY_CH7_S))
|
||||
#define RMT_MEM_EMPTY_CH7_V 0x1
|
||||
#define RMT_MEM_EMPTY_CH7_S 29
|
||||
/* RMT_MEM_FULL_CH7 : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: The memory full status bit for channel7 turns to high level
|
||||
when mem_waddr_ex is greater than or equal to the configuration range.*/
|
||||
#define RMT_MEM_FULL_CH7 (BIT(28))
|
||||
#define RMT_MEM_FULL_CH7_M ((RMT_MEM_FULL_CH7_V)<<(RMT_MEM_FULL_CH7_S))
|
||||
#define RMT_MEM_FULL_CH7_V 0x1
|
||||
#define RMT_MEM_FULL_CH7_S 28
|
||||
/* RMT_MEM_OWNER_ERR_CH7 : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: When channel7 is configured for receive mode, this bit will turn to high level
|
||||
if rmt_mem_owner register is not set to 1.*/
|
||||
#define RMT_MEM_OWNER_ERR_CH7 (BIT(27))
|
||||
#define RMT_MEM_OWNER_ERR_CH7_M ((RMT_MEM_OWNER_ERR_CH7_V)<<(RMT_MEM_OWNER_ERR_CH7_S))
|
||||
#define RMT_MEM_OWNER_ERR_CH7_V 0x1
|
||||
#define RMT_MEM_OWNER_ERR_CH7_S 27
|
||||
/* RMT_STATE_CH7 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
|
||||
/*description: The channel7 state machine status register.
|
||||
3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
|
||||
#define RMT_STATE_CH7 0x07000000
|
||||
#define RMT_STATE_CH7_M ((RMT_STATE_CH7_V)<<(RMT_STATE_CH7_S))
|
||||
#define RMT_STATE_CH7_V 0x7
|
||||
#define RMT_STATE_CH7_S 24
|
||||
/* RMT_MEM_RADDR_EX_CH7 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
|
||||
/*description: The current memory write address of channel7.*/
|
||||
#define RMT_MEM_RADDR_EX_CH7 0x003ff000
|
||||
#define RMT_MEM_RADDR_EX_CH7_M ((RMT_MEM_RADDR_EX_CH7_V)<<(RMT_MEM_RADDR_EX_CH7_S))
|
||||
#define RMT_MEM_RADDR_EX_CH7_V 0x3ff
|
||||
#define RMT_MEM_RADDR_EX_CH7_S 12
|
||||
/* RMT_MEM_WADDR_EX_CH7 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
|
||||
/*description: The current memory read address of channel7.*/
|
||||
#define RMT_MEM_WADDR_EX_CH7 0x000003ff
|
||||
#define RMT_MEM_WADDR_EX_CH7_M ((RMT_MEM_WADDR_EX_CH7_V)<<(RMT_MEM_WADDR_EX_CH7_S))
|
||||
#define RMT_MEM_WADDR_EX_CH7_V 0x3ff
|
||||
#define RMT_MEM_WADDR_EX_CH7_S 0
|
||||
|
||||
#define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080)
|
||||
/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
@ -1550,8 +1118,8 @@
|
||||
|
||||
#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0)
|
||||
/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: The interrupt raw bit for channel7 turns to high level when
|
||||
transmitter in channle 7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/
|
||||
/*description: The interrupt raw bit for channel 7 turns to high level when
|
||||
transmitter in channle7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/
|
||||
#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31))
|
||||
#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31))
|
||||
#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_RMT_STRUCT_H_
|
||||
#define _SOC_RMT_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_RTC_CNTL_STRUCT_H_
|
||||
#define _SOC_RTC_CNTL_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_RTC_IO_STRUCT_H_
|
||||
#define _SOC_RTC_IO_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -16,8 +16,6 @@
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_SENS_STRUCT_H_
|
||||
#define _SOC_SENS_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_SLC_STRUCT_H_
|
||||
#define _SOC_SLC_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -72,6 +72,8 @@
|
||||
#define SOC_EXTRAM_DATA_LOW 0x3F800000
|
||||
#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
|
||||
|
||||
#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
|
||||
|
||||
|
||||
#define DR_REG_DPORT_BASE 0x3ff00000
|
||||
#define DR_REG_AES_BASE 0x3ff01000
|
||||
|
||||
@ -144,11 +144,6 @@ inline static bool IRAM_ATTR esp_ptr_dma_capable(const void *p)
|
||||
return (intptr_t)p >= SOC_DMA_LOW && (intptr_t)p < SOC_DMA_HIGH;
|
||||
}
|
||||
|
||||
inline static bool IRAM_ATTR esp_ptr_word_aligned(const void *p)
|
||||
{
|
||||
return ((intptr_t)p) % 4 == 0;
|
||||
}
|
||||
|
||||
inline static bool IRAM_ATTR esp_ptr_executable(const void *p)
|
||||
{
|
||||
intptr_t ip = (intptr_t) p;
|
||||
@ -194,3 +189,11 @@ inline static bool IRAM_ATTR esp_ptr_in_drom(const void *p) {
|
||||
inline static bool IRAM_ATTR esp_ptr_in_dram(const void *p) {
|
||||
return ((intptr_t)p >= SOC_DRAM_LOW && (intptr_t)p < SOC_DRAM_HIGH);
|
||||
}
|
||||
|
||||
inline static bool IRAM_ATTR esp_ptr_in_diram_dram(const void *p) {
|
||||
return ((intptr_t)p >= SOC_DIRAM_DRAM_LOW && (intptr_t)p < SOC_DIRAM_DRAM_HIGH);
|
||||
}
|
||||
|
||||
inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) {
|
||||
return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH);
|
||||
}
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_SPI_STRUCT_H_
|
||||
#define _SOC_SPI_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_SYSCON_STRUCT_H_
|
||||
#define _SOC_SYSCON_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_TIMG_STRUCT_H_
|
||||
#define _SOC_TIMG_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_UART_STRUCT_H_
|
||||
#define _SOC_UART_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#ifndef _SOC_UHCI_STRUCT_H_
|
||||
#define _SOC_UHCI_STRUCT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user