espressif/arduino-esp32
1
0
Fork 1
mirror of https://github.com/0xFEEDC0DE64/arduino-esp32.git synced 2025-07-01 04:50:58 +02:00
Code Issues Packages Projects Releases Wiki Activity

Update IDF to ebdcbe8c6 (#2539)

Browse Source 
- ESP-Face to 2937054
- ESP32-Camera to 113629b
This commit is contained in:
Me No Dev
2019-03-03 17:19:11 +01:00
committed by GitHub
parent 566f659e90
commit 7df50a97d1
127 changed files with 1594 additions and 681 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
tools/sdk/include/soc/soc/dport_reg.h
View File

@ -179,6 +179,9 @@
#define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
#define DPORT_CPUPERIOD_SEL_V 0x3
#define DPORT_CPUPERIOD_SEL_S 0
#define DPORT_CPUPERIOD_SEL_80 0
#define DPORT_CPUPERIOD_SEL_160 1
#define DPORT_CPUPERIOD_SEL_240 2
#define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040)
/* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */

1
tools/sdk/include/soc/soc/efuse_reg.h
View File

@ -316,6 +316,7 @@
#define EFUSE_CODING_SCHEME_VAL_NONE 0x0
#define EFUSE_CODING_SCHEME_VAL_34 0x1
#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2
#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c)
/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[27:20] ;default: 8'b0 ; */

104
tools/sdk/include/soc/soc/ledc_reg.h
View File

@ -1469,10 +1469,15 @@
/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
/*description: This register controls the range of the counter in high speed
timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/
#define LEDC_HSTIMER0_LIM 0x0000001F
#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S))
#define LEDC_HSTIMER0_LIM_V 0x1F
#define LEDC_HSTIMER0_LIM_S 0
#define LEDC_HSTIMER0_DUTY_RES 0x0000001F
#define LEDC_HSTIMER0_DUTY_RES_M ((LEDC_HSTIMER0_DUTY_RES_V)<<(LEDC_HSTIMER0_DUTY_RES_S))
#define LEDC_HSTIMER0_DUTY_RES_V 0x1F
#define LEDC_HSTIMER0_DUTY_RES_S 0
// Keep the definitions below to be compatible with previous version
#define LEDC_HSTIMER0_LIM LEDC_HSTIMER0_DUTY_RES
#define LEDC_HSTIMER0_LIM_M LEDC_HSTIMER0_DUTY_RES_M
#define LEDC_HSTIMER0_LIM_V LEDC_HSTIMER0_DUTY_RES_V
#define LEDC_HSTIMER0_LIM_S LEDC_HSTIMER0_DUTY_RES_S
#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144)
/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
@ -1513,10 +1518,15 @@
/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
/*description: This register controls the range of the counter in high speed
timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/
#define LEDC_HSTIMER1_LIM 0x0000001F
#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S))
#define LEDC_HSTIMER1_LIM_V 0x1F
#define LEDC_HSTIMER1_LIM_S 0
#define LEDC_HSTIMER1_DUTY_RES 0x0000001F
#define LEDC_HSTIMER1_DUTY_RES_M ((LEDC_HSTIMER1_DUTY_RES_V)<<(LEDC_HSTIMER1_DUTY_RES_S))
#define LEDC_HSTIMER1_DUTY_RES_V 0x1F
#define LEDC_HSTIMER1_DUTY_RES_S 0
// Keep the definitions below to be compatible with previous version
#define LEDC_HSTIMER1_LIM LEDC_HSTIMER1_DUTY_RES
#define LEDC_HSTIMER1_LIM_M LEDC_HSTIMER1_DUTY_RES_M
#define LEDC_HSTIMER1_LIM_V LEDC_HSTIMER1_DUTY_RES_V
#define LEDC_HSTIMER1_LIM_S LEDC_HSTIMER1_DUTY_RES_S
#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C)
/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
@ -1557,10 +1567,15 @@
/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
/*description: This register controls the range of the counter in high speed
timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/
#define LEDC_HSTIMER2_LIM 0x0000001F
#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S))
#define LEDC_HSTIMER2_LIM_V 0x1F
#define LEDC_HSTIMER2_LIM_S 0
#define LEDC_HSTIMER2_DUTY_RES 0x0000001F
#define LEDC_HSTIMER2_DUTY_RES_M ((LEDC_HSTIMER2_DUTY_RES_V)<<(LEDC_HSTIMER2_DUTY_RES_S))
#define LEDC_HSTIMER2_DUTY_RES_V 0x1F
#define LEDC_HSTIMER2_DUTY_RES_S 0
// Keep the definitions below to be compatible with previous version
#define LEDC_HSTIMER2_LIM LEDC_HSTIMER2_DUTY_RES
#define LEDC_HSTIMER2_LIM_M LEDC_HSTIMER2_DUTY_RES_M
#define LEDC_HSTIMER2_LIM_V LEDC_HSTIMER2_DUTY_RES_V
#define LEDC_HSTIMER2_LIM_S LEDC_HSTIMER2_DUTY_RES_S
#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154)
/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
@ -1601,10 +1616,15 @@
/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
/*description: This register controls the range of the counter in high speed
timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/
#define LEDC_HSTIMER3_LIM 0x0000001F
#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S))
#define LEDC_HSTIMER3_LIM_V 0x1F
#define LEDC_HSTIMER3_LIM_S 0
#define LEDC_HSTIMER3_DUTY_RES 0x0000001F
#define LEDC_HSTIMER3_DUTY_RES_M ((LEDC_HSTIMER3_DUTY_RES_V)<<(LEDC_HSTIMER3_DUTY_RES_S))
#define LEDC_HSTIMER3_DUTY_RES_V 0x1F
#define LEDC_HSTIMER3_DUTY_RES_S 0
// Keep the definitions below to be compatible with previous version
#define LEDC_HSTIMER3_LIM LEDC_HSTIMER3_DUTY_RES
#define LEDC_HSTIMER3_LIM_M LEDC_HSTIMER3_DUTY_RES_M
#define LEDC_HSTIMER3_LIM_V LEDC_HSTIMER3_DUTY_RES_V
#define LEDC_HSTIMER3_LIM_S LEDC_HSTIMER3_DUTY_RES_S
#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C)
/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
@ -1651,10 +1671,15 @@
/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
/*description: This register controls the range of the counter in low speed
timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/
#define LEDC_LSTIMER0_LIM 0x0000001F
#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S))
#define LEDC_LSTIMER0_LIM_V 0x1F
#define LEDC_LSTIMER0_LIM_S 0
#define LEDC_LSTIMER0_DUTY_RES 0x0000001F
#define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
#define LEDC_LSTIMER0_DUTY_RES_V 0x1F
#define LEDC_LSTIMER0_DUTY_RES_S 0
// Keep the definitions below to be compatible with previous version
#define LEDC_LSTIMER0_LIM LEDC_LSTIMER0_DUTY_RES
#define LEDC_LSTIMER0_LIM_M LEDC_LSTIMER0_DUTY_RES_M
#define LEDC_LSTIMER0_LIM_V LEDC_LSTIMER0_DUTY_RES_V
#define LEDC_LSTIMER0_LIM_S LEDC_LSTIMER0_DUTY_RES_S
#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164)
/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
@ -1701,10 +1726,15 @@
/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
/*description: This register controls the range of the counter in low speed
timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/
#define LEDC_LSTIMER1_LIM 0x0000001F
#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S))
#define LEDC_LSTIMER1_LIM_V 0x1F
#define LEDC_LSTIMER1_LIM_S 0
#define LEDC_LSTIMER1_DUTY_RES 0x0000001F
#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
#define LEDC_LSTIMER1_DUTY_RES_V 0x1F
#define LEDC_LSTIMER1_DUTY_RES_S 0
// Keep the definitions below to be compatible with previous version
#define LEDC_LSTIMER1_LIM LEDC_LSTIMER1_DUTY_RES
#define LEDC_LSTIMER1_LIM_M LEDC_LSTIMER1_DUTY_RES_M
#define LEDC_LSTIMER1_LIM_V LEDC_LSTIMER1_DUTY_RES_V
#define LEDC_LSTIMER1_LIM_S LEDC_LSTIMER1_DUTY_RES_S
#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C)
/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
@ -1751,10 +1781,15 @@
/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
/*description: This register controls the range of the counter in low speed
timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/
#define LEDC_LSTIMER2_LIM 0x0000001F
#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S))
#define LEDC_LSTIMER2_LIM_V 0x1F
#define LEDC_LSTIMER2_LIM_S 0
#define LEDC_LSTIMER2_DUTY_RES 0x0000001F
#define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
#define LEDC_LSTIMER2_DUTY_RES_V 0x1F
#define LEDC_LSTIMER2_DUTY_RES_S 0
// Keep the definitions below to be compatible with previous version
#define LEDC_LSTIMER2_LIM LEDC_LSTIMER2_DUTY_RES
#define LEDC_LSTIMER2_LIM_M LEDC_LSTIMER2_DUTY_RES_M
#define LEDC_LSTIMER2_LIM_V LEDC_LSTIMER2_DUTY_RES_V
#define LEDC_LSTIMER2_LIM_S LEDC_LSTIMER2_DUTY_RES_S
#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174)
/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
@ -1801,10 +1836,15 @@
/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
/*description: This register controls the range of the counter in low speed
timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/
#define LEDC_LSTIMER3_LIM 0x0000001F
#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S))
#define LEDC_LSTIMER3_LIM_V 0x1F
#define LEDC_LSTIMER3_LIM_S 0
#define LEDC_LSTIMER3_DUTY_RES 0x0000001F
#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
#define LEDC_LSTIMER3_DUTY_RES_V 0x1F
#define LEDC_LSTIMER3_DUTY_RES_S 0
// Keep the definitions below to be compatible with previous version
#define LEDC_LSTIMER3_LIM LEDC_LSTIMER3_DUTY_RES
#define LEDC_LSTIMER3_LIM_M LEDC_LSTIMER3_DUTY_RES_M
#define LEDC_LSTIMER3_LIM_V LEDC_LSTIMER3_DUTY_RES_V
#define LEDC_LSTIMER3_LIM_S LEDC_LSTIMER3_DUTY_RES_S
#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C)
/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */

9
tools/sdk/include/soc/soc/rtc_wdt.h
View File

@ -118,6 +118,15 @@ void rtc_wdt_protect_off();
*/
void rtc_wdt_enable();
/**
* @brief Enable the flash boot protection procedure for WDT.
*
* Do not recommend to use it in the app.
* This function was added to be compatibility with the old bootloaders.
* This mode is disabled in bootloader or using rtc_wdt_disable() function.
*/
void rtc_wdt_flashboot_mode_enable();
/**
* @brief Disable rtc_wdt.
*/