Update IDF to e5b2c1c (#865)

* Update BLE Library

* Fix SD driver

* Update toolchain

* Update IDF to e5b2c1c

tools/sdk/include/soc/soc/cpu.h

@@ -85,6 +85,13 @@ void esp_cpu_stall(int cpu_id);
  */
 void esp_cpu_unstall(int cpu_id);
 
+/**
+ * @brief Reset CPU using RTC controller
+ * @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
+ */
+void esp_cpu_reset(int cpu_id);
+
+
 /**
  * @brief Returns true if a JTAG debugger is attached to CPU
  * OCD (on chip debug) port.

tools/sdk/include/soc/soc/dport_reg.h

@@ -1043,16 +1043,19 @@
 #define DPORT_WIFI_CLK_EN_V  0xFFFFFFFF
 #define DPORT_WIFI_CLK_EN_S  0
 
-/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15 */
-#define DPORT_WIFI_CLK_WIFI_EN  0x000007cf
+/* Mask for all Wifi clock bits - 1, 2, 10 */
+#define DPORT_WIFI_CLK_WIFI_EN  0x00000406
 #define DPORT_WIFI_CLK_WIFI_EN_M  ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S))
-#define DPORT_WIFI_CLK_WIFI_EN_V  0x1FF
+#define DPORT_WIFI_CLK_WIFI_EN_V  0x406
 #define DPORT_WIFI_CLK_WIFI_EN_S  0
 /* Mask for all Bluetooth clock bits - 11, 16, 17 */
 #define DPORT_WIFI_CLK_BT_EN  0x61
 #define DPORT_WIFI_CLK_BT_EN_M  ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S))
 #define DPORT_WIFI_CLK_BT_EN_V  0x61
 #define DPORT_WIFI_CLK_BT_EN_S  11
+/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
+#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
+
 /* Remaining single bit clock masks */
 #define DPORT_WIFI_CLK_SDIOSLAVE_EN  BIT(4)
 #define DPORT_WIFI_CLK_UNUSED_BIT5  BIT(5)

tools/sdk/include/soc/soc/efuse_reg.h

@@ -100,6 +100,8 @@
 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6  0
 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5  1
 #define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5  2
+#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2  4
+#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4  5
 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */
 /*description: read for SPI_pad_config_hd*/
 #define EFUSE_RD_SPI_PAD_CONFIG_HD  0x0000001F

tools/sdk/include/soc/soc/gpio_reg.h

@@ -129,8 +129,7 @@
 
 #define GPIO_STRAP_REG          (DR_REG_GPIO_BASE + 0x0038)
 /* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default:  ; */
-/*description: GPIO strapping results: {2'd0  boot_sel_dig[7:1]  vsdio_boot_sel
-  boot_sel_chip[5:0]}.   Boot_sel_dig[7:1]: {U0RXD  SD_CLK  SD_CMD  SD_DATA0  SD_DATA1  SD_DATA2  SD_DATA3}.  vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0  U0TXD  GPIO2  GPIO4  MTDO  GPIO5}*/
+/*description: {10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} */
 #define GPIO_STRAPPING  0x0000FFFF
 #define GPIO_STRAPPING_M  ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
 #define GPIO_STRAPPING_V  0xFFFF

tools/sdk/include/soc/soc/io_mux_reg.h

@@ -72,7 +72,6 @@
 #define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
 #define MCU_SEL_V 0x7
 #define MCU_SEL_S 12
-#define MCU_SEL_V 0x7
 
 #define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
 #define PIN_INPUT_DISABLE(PIN_NAME)              CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)

tools/sdk/include/soc/soc/rtc.h

@@ -400,6 +400,15 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
  */
 uint64_t rtc_time_get();
 
+/**
+ * @brief Busy loop until next RTC_SLOW_CLK cycle
+ *
+ * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
+ * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
+ * one RTC_SLOW_CLK cycle later.
+ */
+void rtc_clk_wait_for_slow_cycle();
+
 /**
  * @brief sleep configuration for rtc_sleep_init function
  */
@@ -554,6 +563,36 @@ typedef struct {
  */
 void rtc_init(rtc_config_t cfg);
 
+/**
+ * Structure describing vddsdio configuration
+ */
+typedef struct {
+    uint32_t force : 1;     //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
+    uint32_t enable : 1;    //!< Enable VDDSDIO regulator
+    uint32_t tieh  : 1;     //!< Select VDDSDIO voltage: 1 — 1.8V, 0 — 3.3V
+    uint32_t drefh : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefm : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefl : 2;     //!< Tuning parameter for VDDSDIO regulator
+} rtc_vddsdio_config_t;
+
+/**
+ * Get current VDDSDIO configuration
+ * If VDDSDIO configuration is overridden by RTC, get values from RTC
+ * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
+ * Otherwise, use default values and the level of MTDI bootstrapping pin.
+ * @return currently used VDDSDIO configuration
+ */
+rtc_vddsdio_config_t rtc_vddsdio_get_config();
+
+/**
+ * Set new VDDSDIO configuration using RTC registers.
+ * If config.force == 1, this overrides configuration done using bootstrapping
+ * pins and EFUSE.
+ *
+ * @param config new VDDSDIO configuration
+ */
+void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
+
 
 #ifdef __cplusplus
 }

tools/sdk/include/soc/soc/sens_reg.h

@@ -96,12 +96,18 @@
 #define SENS_FORCE_XPD_SAR_M  ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S))
 #define SENS_FORCE_XPD_SAR_V  0x3
 #define SENS_FORCE_XPD_SAR_S  18
+#define SENS_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down
+#define SENS_FORCE_XPD_SAR_PD  2 // Force power down
+#define SENS_FORCE_XPD_SAR_PU  3 // Force power up
 /* SENS_FORCE_XPD_AMP : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
 /*description: */
 #define SENS_FORCE_XPD_AMP  0x00000003
 #define SENS_FORCE_XPD_AMP_M  ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S))
 #define SENS_FORCE_XPD_AMP_V  0x3
 #define SENS_FORCE_XPD_AMP_S  16
+#define SENS_FORCE_XPD_AMP_FSM 0 // Use FSM to control power down
+#define SENS_FORCE_XPD_AMP_PD  2 // Force power down
+#define SENS_FORCE_XPD_AMP_PU  3 // Force power up
 /* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */
 /*description: */
 #define SENS_SAR_AMP_WAIT3  0x0000FFFF
@@ -958,24 +964,36 @@
 #define SENS_AMP_SHORT_REF_GND_FORCE_M  ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S))
 #define SENS_AMP_SHORT_REF_GND_FORCE_V  0x3
 #define SENS_AMP_SHORT_REF_GND_FORCE_S  17
+#define SENS_AMP_SHORT_REF_GND_FORCE_FSM 0 // Use FSM to control power down
+#define SENS_AMP_SHORT_REF_GND_FORCE_PD  2 // Force power down
+#define SENS_AMP_SHORT_REF_GND_FORCE_PU  3 // Force power up
 /* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[16:15] ;default: 2'b0 ; */
 /*description: */
 #define SENS_AMP_SHORT_REF_FORCE  0x00000003
 #define SENS_AMP_SHORT_REF_FORCE_M  ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S))
 #define SENS_AMP_SHORT_REF_FORCE_V  0x3
 #define SENS_AMP_SHORT_REF_FORCE_S  15
+#define SENS_AMP_SHORT_REF_FORCE_FSM 0 // Use FSM to control power down
+#define SENS_AMP_SHORT_REF_FORCE_PD  2 // Force power down
+#define SENS_AMP_SHORT_REF_FORCE_PU  3 // Force power up
 /* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[14:13] ;default: 2'b0 ; */
 /*description: */
 #define SENS_AMP_RST_FB_FORCE  0x00000003
 #define SENS_AMP_RST_FB_FORCE_M  ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S))
 #define SENS_AMP_RST_FB_FORCE_V  0x3
 #define SENS_AMP_RST_FB_FORCE_S  13
+#define SENS_AMP_RST_FB_FORCE_FSM 0 // Use FSM to control power down
+#define SENS_AMP_RST_FB_FORCE_PD  2 // Force power down
+#define SENS_AMP_RST_FB_FORCE_PU  3 // Force power up
 /* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[12:11] ;default: 2'b0 ; */
 /*description: */
 #define SENS_SAR2_RSTB_FORCE  0x00000003
 #define SENS_SAR2_RSTB_FORCE_M  ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S))
 #define SENS_SAR2_RSTB_FORCE_V  0x3
 #define SENS_SAR2_RSTB_FORCE_S  11
+#define SENS_SAR2_RSTB_FORCE_FSM 0 // Use FSM to control power down
+#define SENS_SAR2_RSTB_FORCE_PD  2 // Force power down
+#define SENS_SAR2_RSTB_FORCE_PU  3 // Force power up
 /* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */
 /*description: */
 #define SENS_SAR_RSTB_FSM_IDLE  (BIT(10))