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update IDF libs and esptool.py

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adds autoreset after firmware upload
This commit is contained in:
me-no-dev
2017-01-05 13:54:40 +02:00
parent d84d912973
commit 8b96b1a5f4
35 changed files with 1213 additions and 177 deletions
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9
tools/sdk/include/esp32/soc/cpu.h
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@ -104,4 +104,13 @@ void esp_cpu_stall(int cpu_id);
*/
void esp_cpu_unstall(int cpu_id);
/**
* @brief Returns true if a JTAG debugger is attached to CPU
* OCD (on chip debug) port.
*
* @note If "Make exception and panic handlers JTAG/OCD aware"
* is disabled, this function always returns false.
*/
bool esp_cpu_in_ocd_debug_mode();
#endif

2
tools/sdk/include/esp32/soc/i2c_reg.h
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@ -261,6 +261,8 @@
#define I2C_RXFIFO_FULL_THRHD_V 0x1F
#define I2C_RXFIFO_FULL_THRHD_S 0
#define I2C_DATA_APB_REG(i) (0x60013000 + (i) * 0x14000 + 0x001c)
#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c)
/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: The register represent the byte data read from rxfifo when use apb fifo access*/

6
tools/sdk/include/esp32/soc/i2c_struct.h
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@ -16,7 +16,7 @@
typedef volatile struct {
union {
struct {
uint32_t scl_low_period:14; /*This register is used to configure the low level width of SCL clock.*/
uint32_t period:14; /*This register is used to configure the low level width of SCL clock.*/
uint32_t reserved14: 18;
};
uint32_t val;
@ -58,7 +58,7 @@ typedef volatile struct {
} status_reg;
union {
struct {
uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data.*/
uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data, unit: APB clock cycle.*/
uint32_t reserved20:12;
};
uint32_t val;
@ -282,7 +282,7 @@ typedef volatile struct {
uint32_t reserved_f4;
uint32_t date; /**/
uint32_t reserved_fc;
uint32_t fifo_start_addr; /*This the start address for ram when use apb nonfifo access.*/
uint32_t ram_data[32]; /*This the start address for ram when use apb nonfifo access.*/
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;