mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
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Esp32 s3 support (#6341)
Co-authored-by: Jason2866 <24528715+Jason2866@users.noreply.github.com> Co-authored-by: Unexpected Maker <seon@unexpectedmaker.com> Co-authored-by: Rodrigo Garcia <rodrigo.garcia@espressif.com> Co-authored-by: Tomáš Pilný <34927466+PilnyTomas@users.noreply.github.com> Co-authored-by: Pedro Minatel <pedro.minatel@espressif.com> Co-authored-by: Ivan Grokhotkov <ivan@espressif.com> Co-authored-by: Jan Procházka <90197375+P-R-O-C-H-Y@users.noreply.github.com> Co-authored-by: Limor "Ladyada" Fried <limor@ladyada.net>
This commit is contained in:
Me No Dev
GitHub
@ -1,16 +1,8 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_EFUSE_REG_H_
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#define _SOC_EFUSE_REG_H_
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@ -282,30 +274,12 @@ extern "C" {
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#define EFUSE_FORCE_SEND_RESUME_M (BIT(13))
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#define EFUSE_FORCE_SEND_RESUME_V 0x1
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#define EFUSE_FORCE_SEND_RESUME_S 13
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/* EFUSE_FLASH_ECC_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
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/*description: Set 1 to enable ECC for flash boot.*/
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#define EFUSE_FLASH_ECC_EN (BIT(12))
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#define EFUSE_FLASH_ECC_EN_M (BIT(12))
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#define EFUSE_FLASH_ECC_EN_V 0x1
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#define EFUSE_FLASH_ECC_EN_S 12
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/* EFUSE_FLASH_PAGE_SIZE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
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/*description: Set Flash page size.*/
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#define EFUSE_FLASH_PAGE_SIZE 0x00000003
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#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
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#define EFUSE_FLASH_PAGE_SIZE_V 0x3
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#define EFUSE_FLASH_PAGE_SIZE_S 10
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/* EFUSE_FLASH_TYPE : R/W ;bitpos:[9] ;default: 1'b0 ; */
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/*description: Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/
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#define EFUSE_FLASH_TYPE (BIT(9))
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#define EFUSE_FLASH_TYPE_M (BIT(9))
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#define EFUSE_FLASH_TYPE_V 0x1
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#define EFUSE_FLASH_TYPE_S 9
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/* EFUSE_PIN_POWER_SELECTION : R/W ;bitpos:[8] ;default: 1'b0 ; */
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/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/
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#define EFUSE_PIN_POWER_SELECTION (BIT(8))
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#define EFUSE_PIN_POWER_SELECTION_M (BIT(8))
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#define EFUSE_PIN_POWER_SELECTION_V 0x1
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#define EFUSE_PIN_POWER_SELECTION_S 8
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/* EFUSE_RPT4_RESERVED7 : R/W ;bitpos:[12:8] ;default: 5'h0 ; */
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/*description: Reserved (used for four backups method).*/
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#define EFUSE_RPT4_RESERVED7 0x0000001F
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#define EFUSE_RPT4_RESERVED7_M ((EFUSE_RPT4_RESERVED7_V)<<(EFUSE_RPT4_RESERVED7_S))
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#define EFUSE_RPT4_RESERVED7_V 0x1F
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#define EFUSE_RPT4_RESERVED7_S 8
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/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
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/*description: Set the default UARTboot message output mode. 00: Enabled. 01:
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Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/
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@ -325,13 +299,12 @@ extern "C" {
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#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4))
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#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1
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#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4
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/* EFUSE_FLASH_ECC_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: Set ECC mode in ROM 0: ROM would Enable Flash ECC 16to18 byte
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mode. 1:ROM would use 16to17 byte mode.*/
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#define EFUSE_FLASH_ECC_MODE (BIT(3))
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#define EFUSE_FLASH_ECC_MODE_M (BIT(3))
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#define EFUSE_FLASH_ECC_MODE_V 0x1
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#define EFUSE_FLASH_ECC_MODE_S 3
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/* EFUSE_RPT4_RESERVED8 : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: Reserved (used for four backups method).*/
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#define EFUSE_RPT4_RESERVED8 (BIT(3))
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#define EFUSE_RPT4_RESERVED8_M (BIT(3))
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#define EFUSE_RPT4_RESERVED8_V 0x1
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#define EFUSE_RPT4_RESERVED8_S 3
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/* EFUSE_UART_PRINT_CHANNEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: Selectes the default UART print channel. 0: UART0. 1: UART1.*/
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#define EFUSE_UART_PRINT_CHANNEL (BIT(2))
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@ -654,30 +627,12 @@ extern "C" {
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#define EFUSE_FORCE_SEND_RESUME_M (BIT(13))
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#define EFUSE_FORCE_SEND_RESUME_V 0x1
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#define EFUSE_FORCE_SEND_RESUME_S 13
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/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */
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/*description: The value of FLASH_ECC_EN.*/
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#define EFUSE_FLASH_ECC_EN (BIT(12))
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#define EFUSE_FLASH_ECC_EN_M (BIT(12))
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#define EFUSE_FLASH_ECC_EN_V 0x1
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#define EFUSE_FLASH_ECC_EN_S 12
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/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */
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/*description: The value of FLASH_PAGE_SIZE.*/
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#define EFUSE_FLASH_PAGE_SIZE 0x00000003
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#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
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#define EFUSE_FLASH_PAGE_SIZE_V 0x3
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#define EFUSE_FLASH_PAGE_SIZE_S 10
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/* EFUSE_FLASH_TYPE : RO ;bitpos:[9] ;default: 1'b0 ; */
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/*description: The value of FLASH_TYPE.*/
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#define EFUSE_FLASH_TYPE (BIT(9))
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#define EFUSE_FLASH_TYPE_M (BIT(9))
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#define EFUSE_FLASH_TYPE_V 0x1
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#define EFUSE_FLASH_TYPE_S 9
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/* EFUSE_PIN_POWER_SELECTION : RO ;bitpos:[8] ;default: 1'b0 ; */
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/*description: The value of PIN_POWER_SELECTION.*/
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#define EFUSE_PIN_POWER_SELECTION (BIT(8))
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#define EFUSE_PIN_POWER_SELECTION_M (BIT(8))
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#define EFUSE_PIN_POWER_SELECTION_V 0x1
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#define EFUSE_PIN_POWER_SELECTION_S 8
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/* EFUSE_RPT4_RESERVED7 : RO ;bitpos:[12:8] ;default: 5'h0 ; */
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/*description: Reserved.*/
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#define EFUSE_RPT4_RESERVED7 0x0000001F
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#define EFUSE_RPT4_RESERVED7_M ((EFUSE_RPT4_RESERVED7_V)<<(EFUSE_RPT4_RESERVED7_S))
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#define EFUSE_RPT4_RESERVED7_V 0x1F
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#define EFUSE_RPT4_RESERVED7_S 8
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/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */
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/*description: The value of UART_PRINT_CONTROL.*/
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#define EFUSE_UART_PRINT_CONTROL 0x00000003
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@ -696,12 +651,12 @@ extern "C" {
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#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4))
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#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1
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#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4
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/* EFUSE_FLASH_ECC_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
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/*description: The value of FLASH_ECC_MODE.*/
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#define EFUSE_FLASH_ECC_MODE (BIT(3))
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#define EFUSE_FLASH_ECC_MODE_M (BIT(3))
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#define EFUSE_FLASH_ECC_MODE_V 0x1
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#define EFUSE_FLASH_ECC_MODE_S 3
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/* EFUSE_RPT4_RESERVED8 : RO ;bitpos:[3] ;default: 1'b0 ; */
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/*description: Reserved.*/
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#define EFUSE_RPT4_RESERVED8 (BIT(3))
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#define EFUSE_RPT4_RESERVED8_M (BIT(3))
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#define EFUSE_RPT4_RESERVED8_V 0x1
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#define EFUSE_RPT4_RESERVED8_S 3
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/* EFUSE_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'b0 ; */
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/*description: The value of UART_PRINT_CHANNEL.*/
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#define EFUSE_UART_PRINT_CHANNEL (BIT(2))
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@ -1624,30 +1579,12 @@ extern "C" {
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#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(13))
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#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1
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#define EFUSE_FORCE_SEND_RESUME_ERR_S 13
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/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */
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/*description: If FLASH_ECC_EN_ERR is 1 then it indicates a programming error.*/
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#define EFUSE_FLASH_ECC_EN (BIT(12))
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#define EFUSE_FLASH_ECC_EN_M (BIT(12))
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#define EFUSE_FLASH_ECC_EN_V 0x1
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#define EFUSE_FLASH_ECC_EN_S 12
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/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */
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/*description: If any bits in FLASH_PAGE_SIZE is 1 then it indicates a programming error.*/
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#define EFUSE_FLASH_PAGE_SIZE 0x00000003
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#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
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#define EFUSE_FLASH_PAGE_SIZE_V 0x3
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#define EFUSE_FLASH_PAGE_SIZE_S 10
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/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */
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/*description: If FLASH_TYPE is 1 then it indicates a programming error.*/
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#define EFUSE_FLASH_TYPE_ERR (BIT(9))
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#define EFUSE_FLASH_TYPE_ERR_M (BIT(9))
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#define EFUSE_FLASH_TYPE_ERR_V 0x1
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#define EFUSE_FLASH_TYPE_ERR_S 9
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/* EFUSE_PIN_POWER_SELECTION_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
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/*description: If PIN_POWER_SELECTION is 1 then it indicates a programming error.*/
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#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8))
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#define EFUSE_PIN_POWER_SELECTION_ERR_M (BIT(8))
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#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x1
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#define EFUSE_PIN_POWER_SELECTION_ERR_S 8
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/* EFUSE_RPT4_RESERVED7_ERR : RO ;bitpos:[12:8] ;default: 5'h0 ; */
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/*description: Reserved.*/
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#define EFUSE_RPT4_RESERVED7_ERR 0x0000001F
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#define EFUSE_RPT4_RESERVED7_ERR_M ((EFUSE_RPT4_RESERVED7_ERR_V)<<(EFUSE_RPT4_RESERVED7_ERR_S))
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#define EFUSE_RPT4_RESERVED7_ERR_V 0x1F
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#define EFUSE_RPT4_RESERVED7_ERR_S 8
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/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */
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/*description: If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/
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#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003
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@ -1666,12 +1603,12 @@ extern "C" {
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#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (BIT(4))
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#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x1
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#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4
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/* EFUSE_FLASH_ECC_MODE_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */
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/*description: If FLASH_ECC_MODE is 1 then it indicates a programming error.*/
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#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3))
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#define EFUSE_FLASH_ECC_MODE_ERR_M (BIT(3))
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#define EFUSE_FLASH_ECC_MODE_ERR_V 0x1
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#define EFUSE_FLASH_ECC_MODE_ERR_S 3
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/* EFUSE_RPT4_RESERVED8_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */
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/*description: Reserved.*/
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#define EFUSE_RPT4_RESERVED8_ERR (BIT(3))
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#define EFUSE_RPT4_RESERVED8_ERR_M (BIT(3))
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#define EFUSE_RPT4_RESERVED8_ERR_V 0x1
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#define EFUSE_RPT4_RESERVED8_ERR_S 3
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/* EFUSE_UART_PRINT_CHANNEL_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */
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/*description: If UART_PRINT_CHANNEL is 1 then it indicates a programming error.*/
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#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2))
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@ -1867,6 +1804,9 @@ extern "C" {
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#define EFUSE_OP_CODE_V 0xFFFF
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#define EFUSE_OP_CODE_S 0
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#define EFUSE_WRITE_OP_CODE 0x5a5a
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#define EFUSE_READ_OP_CODE 0x5aa5
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#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1D0)
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/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */
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/*description: Indicates the number of error bits during programming BLOCK0.*/
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@ -76,14 +76,11 @@ typedef volatile struct efuse_dev_s {
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uint32_t dis_download_mode: 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/
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uint32_t dis_legacy_spi_boot: 1; /*Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/
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uint32_t uart_print_channel: 1; /*Selectes the default UART print channel. 0: UART0. 1: UART1.*/
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uint32_t flash_ecc_mode: 1; /*Set ECC mode in ROM 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/
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uint32_t rpt4_reserved8: 1; /*Reserved (used for four backups method).*/
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uint32_t dis_usb_download_mode: 1; /*Set this bit to disable UART download mode through USB.*/
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uint32_t enable_security_download: 1; /*Set this bit to enable secure UART download mode.*/
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uint32_t uart_print_control: 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/
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uint32_t pin_power_selection: 1; /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/
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uint32_t flash_type: 1; /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/
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uint32_t flash_page_size: 2; /*Set Flash page size.*/
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uint32_t flash_ecc_en: 1; /*Set 1 to enable ECC for flash boot.*/
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uint32_t rpt4_reserved7: 5; /*Reserved (used for four backups method).*/
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uint32_t force_send_resume: 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/
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uint32_t secure_version: 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/
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uint32_t rpt4_reserved1: 2; /*Reserved (used for four backups method).*/
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@ -160,14 +157,11 @@ typedef volatile struct efuse_dev_s {
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uint32_t dis_download_mode: 1; /*The value of DIS_DOWNLOAD_MODE.*/
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uint32_t dis_legacy_spi_boot: 1; /*The value of DIS_LEGACY_SPI_BOOT.*/
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uint32_t uart_print_channel: 1; /*The value of UART_PRINT_CHANNEL.*/
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uint32_t flash_ecc_mode: 1; /*The value of FLASH_ECC_MODE.*/
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uint32_t rpt4_reserved8: 1; /*Reserved.*/
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uint32_t dis_usb_download_mode: 1; /*The value of DIS_USB_DOWNLOAD_MODE.*/
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uint32_t enable_security_download: 1; /*The value of ENABLE_SECURITY_DOWNLOAD.*/
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uint32_t uart_print_control: 2; /*The value of UART_PRINT_CONTROL.*/
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uint32_t pin_power_selection: 1; /*The value of PIN_POWER_SELECTION.*/
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uint32_t flash_type: 1; /*The value of FLASH_TYPE.*/
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uint32_t flash_page_size: 2; /*The value of FLASH_PAGE_SIZE.*/
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uint32_t flash_ecc_en: 1; /*The value of FLASH_ECC_EN.*/
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uint32_t rpt4_reserved7: 5; /*Reserved.*/
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uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/
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uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/
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uint32_t rpt4_reserved1: 2; /*Reserved.*/
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@ -328,14 +322,11 @@ typedef volatile struct efuse_dev_s {
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uint32_t dis_download_mode_err: 1; /*If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/
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uint32_t dis_legacy_spi_boot_err: 1; /*If DIS_LEGACY_SPI_BOOT is 1 then it indicates a programming error.*/
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uint32_t uart_print_channel_err: 1; /*If UART_PRINT_CHANNEL is 1 then it indicates a programming error.*/
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uint32_t flash_ecc_mode_err: 1; /*If FLASH_ECC_MODE is 1 then it indicates a programming error.*/
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uint32_t rpt4_reserved8_err: 1; /*Reserved.*/
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uint32_t dis_usb_download_mode_err: 1; /*If DIS_USB_DOWNLOAD_MODE is 1 then it indicates a programming error.*/
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uint32_t enable_security_download_err: 1; /*If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/
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uint32_t uart_print_control_err: 2; /*If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/
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uint32_t pin_power_selection_err: 1; /*If PIN_POWER_SELECTION is 1 then it indicates a programming error.*/
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uint32_t flash_type_err: 1; /*If FLASH_TYPE is 1 then it indicates a programming error.*/
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uint32_t flash_page_size: 2; /*If any bits in FLASH_PAGE_SIZE is 1 then it indicates a programming error.*/
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uint32_t flash_ecc_en: 1; /*If FLASH_ECC_EN_ERR is 1 then it indicates a programming error.*/
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uint32_t rpt4_reserved7_err: 5; /*Reserved*/
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uint32_t force_send_resume_err: 1; /*If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/
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uint32_t secure_version_err: 16; /*If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/
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uint32_t rpt4_reserved1_err: 2; /*Reserved.*/
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@ -138,9 +138,9 @@
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#define SD_DATA2_GPIO_NUM 9
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#define SD_DATA3_GPIO_NUM 10
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#define MAX_RTC_GPIO_NUM 0
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#define MAX_PAD_GPIO_NUM 22
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#define MAX_GPIO_NUM 22
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#define MAX_RTC_GPIO_NUM 5
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#define MAX_PAD_GPIO_NUM 21
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#define MAX_GPIO_NUM 25
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#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
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#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
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100
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/memprot_defs.h
Normal file
100
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/memprot_defs.h
Normal file
@ -0,0 +1,100 @@
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/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/sensitive_reg.h"
|
||||
#include "esp32c3/rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t cat0 : 2;
|
||||
uint32_t cat1 : 2;
|
||||
uint32_t cat2 : 2;
|
||||
uint32_t res0 : 8;
|
||||
uint32_t splitaddr : 8;
|
||||
uint32_t res1 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} constrain_reg_fields_t;
|
||||
|
||||
#ifndef I_D_SRAM_SEGMENT_SIZE
|
||||
#define I_D_SRAM_SEGMENT_SIZE 0x20000
|
||||
#endif
|
||||
|
||||
#define I_D_SPLIT_LINE_SHIFT 0x9
|
||||
#define I_D_FAULT_ADDR_SHIFT 0x2
|
||||
|
||||
#define DRAM_SRAM_START 0x3FC7C000
|
||||
|
||||
#ifndef MAP_DRAM_TO_IRAM
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr - DRAM_SRAM_START + SOC_IRAM_LOW)
|
||||
#endif
|
||||
|
||||
#ifndef MAP_IRAM_TO_DRAM
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_IRAM_LOW + DRAM_SRAM_START)
|
||||
#endif
|
||||
|
||||
//IRAM0
|
||||
|
||||
//16kB (ICACHE)
|
||||
#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000
|
||||
#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF
|
||||
|
||||
//128kB (LEVEL 1)
|
||||
#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000
|
||||
#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF
|
||||
|
||||
//128kB (LEVEL 2)
|
||||
#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000
|
||||
#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF
|
||||
|
||||
//128kB (LEVEL 3)
|
||||
#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000
|
||||
#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF
|
||||
|
||||
//permission bits
|
||||
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
|
||||
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
|
||||
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4
|
||||
|
||||
//DRAM0
|
||||
|
||||
//16kB ICACHE not available from DRAM0
|
||||
|
||||
//128kB (LEVEL 1)
|
||||
#define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000
|
||||
#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF
|
||||
|
||||
//128kB (LEVEL 2)
|
||||
#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000
|
||||
#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF
|
||||
|
||||
//128kB (LEVEL 3)
|
||||
#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000
|
||||
#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF
|
||||
|
||||
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
|
||||
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
|
||||
|
||||
//RTC FAST
|
||||
|
||||
//permission bits
|
||||
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1
|
||||
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2
|
||||
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4
|
||||
|
||||
#define AREA_LOW 0
|
||||
#define AREA_HIGH 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -1,16 +1,8 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
@ -175,7 +175,7 @@
|
||||
/*-------------------------- RTCIO CAPS --------------------------------------*/
|
||||
/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
|
||||
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
|
||||
#define SOC_RTCIO_PIN_COUNT 0
|
||||
#define SOC_RTCIO_PIN_COUNT (0U)
|
||||
|
||||
/*--------------------------- RSA CAPS ---------------------------------------*/
|
||||
#define SOC_RSA_MAX_BIT_LEN (3072)
|
||||
|
||||
@ -1,61 +1,21 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C3.
|
||||
|
||||
#ifndef _SOC_UART_CHANNEL_H
|
||||
#define _SOC_UART_CHANNEL_H
|
||||
|
||||
//UART channels
|
||||
#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1
|
||||
#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3
|
||||
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19
|
||||
#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22
|
||||
#define UART_GPIO21_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 21
|
||||
#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 20
|
||||
|
||||
#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL
|
||||
#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL
|
||||
#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL
|
||||
#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL
|
||||
|
||||
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1
|
||||
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10
|
||||
#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1
|
||||
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9
|
||||
#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1
|
||||
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6
|
||||
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1
|
||||
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11
|
||||
|
||||
#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL
|
||||
#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL
|
||||
#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL
|
||||
#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
|
||||
|
||||
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2
|
||||
#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17
|
||||
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2
|
||||
#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16
|
||||
#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2
|
||||
#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8
|
||||
#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2
|
||||
#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7
|
||||
|
||||
#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
|
||||
#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
|
||||
#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL
|
||||
#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL
|
||||
#define UART_TXD_GPIO21_DIRECT_CHANNEL UART_GPIO21_DIRECT_CHANNEL
|
||||
#define UART_RXD_GPIO20_DIRECT_CHANNEL UART_GPIO20_DIRECT_CHANNEL
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user