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Esp32 s3 support (#6341)

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Co-authored-by: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Co-authored-by: Unexpected Maker <seon@unexpectedmaker.com>
Co-authored-by: Rodrigo Garcia <rodrigo.garcia@espressif.com>
Co-authored-by: Tomáš Pilný <34927466+PilnyTomas@users.noreply.github.com>
Co-authored-by: Pedro Minatel <pedro.minatel@espressif.com>
Co-authored-by: Ivan Grokhotkov <ivan@espressif.com>
Co-authored-by: Jan Procházka <90197375+P-R-O-C-H-Y@users.noreply.github.com>
Co-authored-by: Limor "Ladyada" Fried <limor@ladyada.net>
This commit is contained in:
Me No Dev
2022-03-28 12:09:41 +03:00
committed by GitHub
parent 3f79097d5f
commit 8ee5f0a11e
3774 changed files with 685773 additions and 19284 deletions
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22
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/dport_reg.h
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@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_DPORT_REG_H_
#define _SOC_DPORT_REG_H_
@ -25,10 +17,6 @@ extern "C" {
#define DPORT_DATE_REG SYSTEM_DATE_REG
#define TRACEMEM_MUX_BLK0_NUM 19
#define TRACEMEM_MUX_BLK1_NUM 20
#define TRACEMEM_BLK_NUM2ADDR(_n_) (0x3FFB8000UL + 0x4000UL*((_n_)-4))
#ifndef __ASSEMBLER__
#include "dport_access.h"
#endif

3722
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/rmt_reg.h
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tools/sdk/esp32s2/include/soc/esp32s2/include/soc/rmt_struct.h
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26
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/soc_caps.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -98,18 +98,18 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-S2 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT (48)
#define SOC_GPIO_PIN_COUNT (47)
// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
// On ESP32-S2 those PADs which have RTC functions must set pullup/down/capability via RTC register.
// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-S2
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// 0~47 except from 22~25, 47 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47))
// GPIO 46, 47 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47))
// 0~46 except from 22~25 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0x7FFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
// GPIO 46 is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46))
// Support to configure slept status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
@ -135,14 +135,19 @@
#define SOC_I2C_SUPPORT_REF_TICK (1)
#define SOC_I2C_SUPPORT_APB (1)
/*-------------------------- APLL CAPS ----------------------------------------*/
#define SOC_CLK_APLL_SUPPORTED (1)
// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
#define SOC_APLL_MULTIPLIER_OUT_MIN_HZ (350000000) // 350 MHz
#define SOC_APLL_MULTIPLIER_OUT_MAX_HZ (500000000) // 500 MHz
#define SOC_APLL_MIN_HZ (5303031) // 5.303031 MHz
#define SOC_APLL_MAX_HZ (125000000) // 125MHz
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32-S2 have 1 I2S
#define SOC_I2S_NUM (1)
#define SOC_I2S_SUPPORTS_APLL (1)// ESP32-S2 support APLL
#define SOC_I2S_SUPPORTS_DMA_EQUAL (1)
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define SOC_I2S_LCD_I80_VARIANT (1)
/*-------------------------- LCD CAPS ----------------------------------------*/
@ -176,7 +181,6 @@
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Receive in each group */
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
#define SOC_RMT_MEM_WORDS_PER_CHANNEL (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmiting specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */

21
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/tracemem_config.h Normal file
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@ -0,0 +1,21 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define TRACEMEM_MUX_BLK0_NUM 19
#define TRACEMEM_MUX_BLK1_NUM 20
#define TRACEMEM_BLK_NUM2ADDR(_n_) (0x3FFB8000UL + 0x4000UL*((_n_)-4))
#define TRACEMEM_BLK0_ADDR TRACEMEM_BLK_NUM2ADDR(TRACEMEM_MUX_BLK0_NUM)
#define TRACEMEM_BLK1_ADDR TRACEMEM_BLK_NUM2ADDR(TRACEMEM_MUX_BLK1_NUM)
#ifdef __cplusplus
}
#endif

78
tools/sdk/esp32s2/include/soc/esp32s2/include/soc/uart_channel.h
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@ -1,61 +1,41 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32S2.
#ifndef _SOC_UART_CHANNEL_H
#define _SOC_UART_CHANNEL_H
//UART channels
#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1
#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19
#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22
#define UART_GPIO43_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 43
#define UART_GPIO44_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 44
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 16
#define UART_GPIO15_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 15
#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL
#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL
#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL
#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL
#define UART_TXD_GPIO43_DIRECT_CHANNEL UART_GPIO43_DIRECT_CHANNEL
#define UART_RXD_GPIO44_DIRECT_CHANNEL UART_GPIO44_DIRECT_CHANNEL
#define UART_CTS_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_RTS_GPIO15_DIRECT_CHANNEL UART_GPIO15_DIRECT_CHANNEL
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10
#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9
#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11
#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL
#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL
#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL
#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16
#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8
#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 17
#define UART_GPIO18_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 18
#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 20
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 19
#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL
#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL
#define UART_RXD_GPIO18_DIRECT_CHANNEL UART_GPIO18_DIRECT_CHANNEL
#define UART_CTS_GPIO20_DIRECT_CHANNEL UART_GPIO20_DIRECT_CHANNEL
#define UART_RTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL
#endif