mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
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Update IDF to 3.2-3276a13 and esptool.py to 2.5.0 (#1878)
* TX Flow Control and Code cleanup * Use semaphore instead of delay TX functionality is done. * Use single buffer and empty queue on exit * Fix compile issues because of LwIP code relocation * Add temporary header to fix Azure not compiling * Fix AsyncUDP early init * AsyncUDP Multicast fixes * Add source mac address and rework multicast * Allow redefinition of default pins for Serials 1 and 2 * Update IDF to 3276a13 * Update esptool.py to 2.5.0 * Fix sketches * Fix log level in BluetoothSetial
This commit is contained in:
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211
tools/sdk/include/soc/soc/can_struct.h
Normal file
211
tools/sdk/include/soc/soc/can_struct.h
Normal file
@ -0,0 +1,211 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_CAN_STRUCT_H_
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#define _SOC_CAN_STRUCT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* -------------------------- Register Definitions -------------------------- */
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/* The CAN peripheral's registers are 8bits, however the ESP32 can only access
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* peripheral registers every 32bits. Therefore each CAN register is mapped to
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* the least significant byte of every 32bits.
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*/
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typedef union {
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struct {
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uint32_t byte: 8; /* LSB */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_reg_t;
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typedef union {
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struct {
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uint32_t reset: 1; /* MOD.0 Reset Mode */
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uint32_t listen_only: 1; /* MOD.1 Listen Only Mode */
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uint32_t self_test: 1; /* MOD.2 Self Test Mode */
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uint32_t acceptance_filter: 1; /* MOD.3 Acceptance Filter Mode */
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uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
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};
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uint32_t val;
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} can_mode_reg_t;
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typedef union {
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struct {
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uint32_t tx_req: 1; /* CMR.0 Transmission Request */
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uint32_t abort_tx: 1; /* CMR.1 Abort Transmission */
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uint32_t release_rx_buff: 1; /* CMR.2 Release Receive Buffer */
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uint32_t clear_data_overrun: 1; /* CMR.3 Clear Data Overrun */
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uint32_t self_rx_req: 1; /* CMR.4 Self Reception Request */
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uint32_t reserved27: 27; /* Internal Reserved */
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};
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uint32_t val;
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} can_cmd_reg_t;
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typedef union {
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struct {
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uint32_t rx_buff: 1; /* SR.0 Receive Buffer Status */
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uint32_t data_overrun: 1; /* SR.1 Data Overrun Status */
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uint32_t tx_buff: 1; /* SR.2 Transmit Buffer Status */
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uint32_t tx_complete: 1; /* SR.3 Transmission Complete Status */
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uint32_t rx: 1; /* SR.4 Receive Status */
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uint32_t tx: 1; /* SR.5 Transmit Status */
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uint32_t error: 1; /* SR.6 Error Status */
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uint32_t bus: 1; /* SR.7 Bus Status */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_status_reg_t;
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typedef union {
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struct {
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uint32_t rx: 1; /* IR.0 Receive Interrupt */
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uint32_t tx: 1; /* IR.1 Transmit Interrupt */
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uint32_t err_warn: 1; /* IR.2 Error Interrupt */
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uint32_t data_overrun: 1; /* IR.3 Data Overrun Interrupt */
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uint32_t reserved1: 1; /* Internal Reserved (Wake-up not supported) */
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uint32_t err_passive: 1; /* IR.5 Error Passive Interrupt */
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uint32_t arb_lost: 1; /* IR.6 Arbitration Lost Interrupt */
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uint32_t bus_err: 1; /* IR.7 Bus Error Interrupt */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_intr_reg_t;
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typedef union {
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struct {
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uint32_t rx: 1; /* IER.0 Receive Interrupt Enable */
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uint32_t tx: 1; /* IER.1 Transmit Interrupt Enable */
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uint32_t err_warn: 1; /* IER.2 Error Interrupt Enable */
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uint32_t data_overrun: 1; /* IER.3 Data Overrun Interrupt Enable */
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uint32_t reserved1: 1; /* Internal Reserved (Wake-up not supported) */
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uint32_t err_passive: 1; /* IER.5 Error Passive Interrupt Enable */
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uint32_t arb_lost: 1; /* IER.6 Arbitration Lost Interrupt Enable */
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uint32_t bus_err: 1; /* IER.7 Bus Error Interrupt Enable */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_intr_en_reg_t;
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typedef union {
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struct {
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uint32_t baud_rate_prescaler: 6; /* BTR0[5:0] Baud Rate Prescaler */
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uint32_t sync_jump_width: 2; /* BTR0[7:6] Synchronization Jump Width*/
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_bus_tim_0_reg_t;
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typedef union {
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struct {
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uint32_t time_seg_1: 4; /* BTR1[3:0] Timing Segment 1 */
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uint32_t time_seg_2: 3; /* BTR1[6:4] Timing Segment 2 */
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uint32_t sampling: 1; /* BTR1.7 Sampling*/
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_bus_tim_1_reg_t;
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typedef union {
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struct {
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uint32_t arbitration_lost_capture: 5; /* ALC[4:0] Arbitration lost capture */
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uint32_t reserved27: 27; /* Internal Reserved */
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};
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uint32_t val;
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} can_arb_lost_cap_reg_t;
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typedef union {
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struct {
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uint32_t segment: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
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uint32_t direction: 1; /* ECC.5 Error Direction (TX/RX) */
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uint32_t error_code: 2; /* ECC[7:6] Error Code */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_err_code_cap_reg_t;
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typedef struct {
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can_reg_t code_reg[4];
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can_reg_t mask_reg[4];
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uint32_t reserved32[5];
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} can_acc_filter_t;
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typedef union {
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struct {
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uint32_t rx_message_counter: 5; /* RMC[4:0] RX Message Counter */
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uint32_t reserved27: 27; /* Internal Reserved */
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};
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uint32_t val;
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} can_rx_msg_cnt_reg_t;
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typedef union {
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struct {
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uint32_t clock_divider: 3; /* CDR[2:0] CLKOUT frequency selector based of fOSC */
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uint32_t clock_off: 1; /* CDR.3 CLKOUT enable/disable */
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uint32_t reserved3: 3; /* Internal Reserved. RXINTEN and CBP not supported */
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uint32_t can_mode: 1; /* CDR.7 BasicCAN:0 PeliCAN:1 */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_clk_div_reg_t;
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/* ---------------------------- Register Layout ------------------------------ */
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typedef volatile struct {
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//Configuration and Control Registers
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can_mode_reg_t mode_reg; /* Address 0 */
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can_cmd_reg_t command_reg; /* Address 1 */
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can_status_reg_t status_reg; /* Address 2 */
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can_intr_reg_t interrupt_reg; /* Address 3 */
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can_intr_en_reg_t interrupt_enable_reg; /* Address 4 */
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uint32_t reserved_05; /* Address 5 */
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can_bus_tim_0_reg_t bus_timing_0_reg; /* Address 6 */
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can_bus_tim_1_reg_t bus_timing_1_reg; /* Address 7 */
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uint32_t reserved_08; /* Address 8 (Output control not supported) */
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uint32_t reserved_09; /* Address 9 (Test Register not supported) */
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uint32_t reserved_10; /* Address 10 */
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//Capture and Counter Registers
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can_arb_lost_cap_reg_t arbitration_lost_captue_reg; /* Address 11 */
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can_err_code_cap_reg_t error_code_capture_reg; /* Address 12 */
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can_reg_t error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
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can_reg_t rx_error_counter_reg; /* RXERR[7:0] Receive Error Counter: Address 14 */
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can_reg_t tx_error_counter_reg; /* TXERR[7:0] Transmit Error Counter: Address 15 */
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//Shared Registers (TX Buff/RX Buff/Acc Filter)
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union {
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can_acc_filter_t acceptance_filter;
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can_reg_t tx_rx_buffer[13];
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}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
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//Misc Registers
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can_rx_msg_cnt_reg_t rx_message_counter_reg; /* Address 29 */
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can_reg_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
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can_clk_div_reg_t clock_divider_reg; /* Address 31 */
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//Start of RX FIFO
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} can_dev_t;
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_Static_assert(sizeof(can_dev_t) == 128, "CAN registers should be 32 * 4 bytes");
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extern can_dev_t CAN;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_CAN_STRUCT_H_ */
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@ -19,7 +19,9 @@ extern "C" {
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#endif
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typedef volatile struct {
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uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/
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uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.
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Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue
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and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/
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struct{
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union {
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struct {
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@ -39,7 +41,7 @@ typedef volatile struct {
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uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/
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uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/
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uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/
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uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/
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uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/
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uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/
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uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/
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uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/
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@ -54,7 +56,7 @@ typedef volatile struct {
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} conf1;
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} conf_ch[8];
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uint32_t status_ch[8]; /*The status for channel0-7*/
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uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/
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uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/
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union {
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struct {
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uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/
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@ -219,7 +221,7 @@ typedef volatile struct {
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} tx_lim_ch[8];
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union {
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struct {
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uint32_t fifo_mask: 1; /*Set this bit to disable apb fifo access*/
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uint32_t fifo_mask: 1; /*Set this bit to enable RMTMEM and disable apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/
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uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/
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uint32_t reserved2: 30;
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};
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@ -243,22 +245,11 @@ typedef struct {
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};
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} rmt_item32_t;
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typedef struct {
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union {
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struct {
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uint16_t duration :15;
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uint16_t level :1;
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};
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uint16_t val;
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};
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} rmt_item16_t;
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//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
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typedef volatile struct {
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struct {
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union {
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rmt_item32_t data32[64];
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rmt_item16_t data16[128];
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};
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} chan[8];
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} rmt_mem_t;
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@ -75,6 +75,26 @@ typedef enum {
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RTC_CPU_FREQ_2M = 4, //!< 2 MHz
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} rtc_cpu_freq_t;
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|
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/**
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* @brief CPU clock source
|
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*/
|
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typedef enum {
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RTC_CPU_FREQ_SRC_XTAL, //!< XTAL
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RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M)
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RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator
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RTC_CPU_FREQ_SRC_APLL //!< APLL
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} rtc_cpu_freq_src_t;
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|
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/**
|
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* @brief CPU clock configuration structure
|
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*/
|
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typedef struct {
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rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived
|
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uint32_t source_freq_mhz; //!< Source clock frequency
|
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uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div
|
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uint32_t freq_mhz; //!< CPU clock frequency
|
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} rtc_cpu_freq_config_t;
|
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|
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/**
|
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* @brief RTC SLOW_CLK frequency values
|
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*/
|
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@ -108,13 +128,13 @@ typedef enum {
|
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* Initialization parameters for rtc_clk_init
|
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*/
|
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typedef struct {
|
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rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
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rtc_cpu_freq_t cpu_freq : 3; //!< CPU frequency to set
|
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rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
|
||||
rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set
|
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uint32_t clk_8m_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
|
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uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
|
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uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
|
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rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
rtc_cpu_freq_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
|
||||
rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set
|
||||
uint32_t clk_8m_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
|
||||
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
|
||||
uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
|
||||
} rtc_clk_config_t;
|
||||
|
||||
/**
|
||||
@ -122,7 +142,7 @@ typedef struct {
|
||||
*/
|
||||
#define RTC_CLK_CONFIG_DEFAULT() { \
|
||||
.xtal_freq = RTC_XTAL_FREQ_AUTO, \
|
||||
.cpu_freq = RTC_CPU_FREQ_80M, \
|
||||
.cpu_freq_mhz = 80, \
|
||||
.fast_freq = RTC_FAST_FREQ_8M, \
|
||||
.slow_freq = RTC_SLOW_FREQ_RTC, \
|
||||
.clk_8m_div = 0, \
|
||||
@ -173,6 +193,11 @@ void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
|
||||
*/
|
||||
void rtc_clk_32k_enable(bool en);
|
||||
|
||||
/**
|
||||
* @brief Configure 32 kHz XTAL oscillator to accept external clock signal
|
||||
*/
|
||||
void rtc_clk_32k_enable_external();
|
||||
|
||||
/**
|
||||
* @brief Get the state of 32k XTAL oscillator
|
||||
* @return true if 32k XTAL oscillator has been enabled
|
||||
@ -281,6 +306,9 @@ rtc_fast_freq_t rtc_clk_fast_freq_get();
|
||||
/**
|
||||
* @brief Switch CPU frequency
|
||||
*
|
||||
* @note This function is deprecated and will be removed.
|
||||
* See rtc_clk_cpu_freq_config_set instead.
|
||||
*
|
||||
* If a PLL-derived frequency is requested (80, 160, 240 MHz), this function
|
||||
* will enable the PLL. Otherwise, PLL will be disabled.
|
||||
* Note: this function is not optimized for switching speed. It may take several
|
||||
@ -288,11 +316,14 @@ rtc_fast_freq_t rtc_clk_fast_freq_get();
|
||||
*
|
||||
* @param cpu_freq new CPU frequency
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq);
|
||||
void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated));
|
||||
|
||||
/**
|
||||
* @brief Switch CPU frequency
|
||||
*
|
||||
* @note This function is deprecated and will be removed.
|
||||
* See rtc_clk_cpu_freq_set_config_fast instead.
|
||||
*
|
||||
* This is a faster version of rtc_clk_cpu_freq_set, which can handle some of
|
||||
* the frequency switch paths (XTAL -> PLL, PLL -> XTAL).
|
||||
* When switching from PLL to XTAL, PLL is not disabled (unlike rtc_clk_cpu_freq_set).
|
||||
@ -307,11 +338,14 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq);
|
||||
*
|
||||
* @param cpu_freq new CPU frequency
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq);
|
||||
void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated));
|
||||
|
||||
/**
|
||||
* @brief Get the currently selected CPU frequency
|
||||
*
|
||||
* @note This function is deprecated and will be removed.
|
||||
* See rtc_clk_cpu_freq_get_config instead.
|
||||
*
|
||||
* Although CPU can be clocked by APLL and RTC 8M sources, such support is not
|
||||
* exposed through this library. As such, this function will not return
|
||||
* meaningful values when these clock sources are configured (e.g. using direct
|
||||
@ -320,22 +354,97 @@ void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq);
|
||||
*
|
||||
* @return CPU frequency (one of rtc_cpu_freq_t values)
|
||||
*/
|
||||
rtc_cpu_freq_t rtc_clk_cpu_freq_get();
|
||||
rtc_cpu_freq_t rtc_clk_cpu_freq_get() __attribute__((deprecated));
|
||||
|
||||
/**
|
||||
* @brief Get corresponding frequency value for rtc_cpu_freq_t enum value
|
||||
*
|
||||
* @note This function is deprecated and will be removed.
|
||||
* See rtc_clk_cpu_freq_get/set_config instead.
|
||||
*
|
||||
* @param cpu_freq CPU frequency, on of rtc_cpu_freq_t values
|
||||
* @return CPU frequency, in HZ
|
||||
*/
|
||||
uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq);
|
||||
uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated));
|
||||
|
||||
/**
|
||||
* @brief Get rtc_cpu_freq_t enum value for given CPU frequency
|
||||
*
|
||||
* @note This function is deprecated and will be removed.
|
||||
* See rtc_clk_cpu_freq_mhz_to_config instead.
|
||||
*
|
||||
* @param cpu_freq_mhz CPU frequency, one of 80, 160, 240, 2, and XTAL frequency
|
||||
* @param[out] out_val output, rtc_cpu_freq_t value corresponding to the frequency
|
||||
* @return true if the given frequency value matches one of enum values
|
||||
*/
|
||||
bool rtc_clk_cpu_freq_from_mhz(int cpu_freq_mhz, rtc_cpu_freq_t* out_val);
|
||||
bool rtc_clk_cpu_freq_from_mhz(int cpu_freq_mhz, rtc_cpu_freq_t* out_val) __attribute__((deprecated));
|
||||
|
||||
/**
|
||||
* @brief Get CPU frequency config corresponding to a rtc_cpu_freq_t value
|
||||
* @param cpu_freq CPU frequency enumeration value
|
||||
* @param[out] out_config Output, CPU frequency configuration structure
|
||||
*/
|
||||
void rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq, rtc_cpu_freq_config_t* out_config);
|
||||
|
||||
/**
|
||||
* @brief Get CPU frequency config for a given frequency
|
||||
* @param freq_mhz Frequency in MHz
|
||||
* @param[out] out_config Output, CPU frequency configuration structure
|
||||
* @return true if frequency can be obtained, false otherwise
|
||||
*/
|
||||
bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config);
|
||||
|
||||
/**
|
||||
* @brief Switch CPU frequency
|
||||
*
|
||||
* This function sets CPU frequency according to the given configuration
|
||||
* structure. It enables PLLs, if necessary.
|
||||
*
|
||||
* @note This function in not intended to be called by applications in FreeRTOS
|
||||
* environment. This is because it does not adjust various timers based on the
|
||||
* new CPU frequency.
|
||||
*
|
||||
* @param config CPU frequency configuration structure
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config);
|
||||
|
||||
/**
|
||||
* @brief Switch CPU frequency (optimized for speed)
|
||||
*
|
||||
* This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
|
||||
* It works faster because it does not disable PLLs when switching from PLL to
|
||||
* XTAL and does not enabled them when switching back. If PLL is not already
|
||||
* enabled when this function is called to switch from XTAL to PLL frequency,
|
||||
* or the PLL which is enabled is the wrong one, this function will fall back
|
||||
* to calling rtc_clk_cpu_freq_set_config.
|
||||
*
|
||||
* Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
|
||||
* so it is less safe to use it e.g. from a panic handler (when memory might
|
||||
* be corrupted).
|
||||
*
|
||||
* @note This function in not intended to be called by applications in FreeRTOS
|
||||
* environment. This is because it does not adjust various timers based on the
|
||||
* new CPU frequency.
|
||||
*
|
||||
* @param config CPU frequency configuration structure
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config);
|
||||
|
||||
/**
|
||||
* @brief Get the currently used CPU frequency configuration
|
||||
* @param[out] out_config Output, CPU frequency configuration structure
|
||||
*/
|
||||
void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config);
|
||||
|
||||
/**
|
||||
* @brief Switch CPU clock source to XTAL
|
||||
*
|
||||
* Short form for filling in rtc_cpu_freq_config_t structure and calling
|
||||
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
|
||||
* Assumes that XTAL frequency has been determined — don't call in startup code.
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_xtal();
|
||||
|
||||
|
||||
/**
|
||||
* @brief Store new APB frequency value into RTC_APB_FREQ_REG
|
||||
|
||||
193
tools/sdk/include/soc/soc/rtc_wdt.h
Normal file
193
tools/sdk/include/soc/soc/rtc_wdt.h
Normal file
@ -0,0 +1,193 @@
|
||||
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/* Recommendation of using API RTC_WDT.
|
||||
1) Setting and enabling rtc_wdt:
|
||||
@code
|
||||
rtc_wdt_protect_off();
|
||||
rtc_wdt_disable();
|
||||
rtc_wdt_set_length_of_reset_signal(RTC_WDT_SYS_RESET_SIG, RTC_WDT_LENGTH_3_2us);
|
||||
rtc_wdt_set_stage(RTC_WDT_STAGE0, RTC_WDT_STAGE_ACTION_RESET_SYSTEM); //RTC_WDT_STAGE_ACTION_RESET_SYSTEM or RTC_WDT_STAGE_ACTION_RESET_RTC
|
||||
rtc_wdt_set_time(RTC_WDT_STAGE0, 7000); // timeout rtd_wdt 7000ms.
|
||||
rtc_wdt_enable();
|
||||
rtc_wdt_protect_on();
|
||||
@endcode
|
||||
|
||||
* If you use this option RTC_WDT_STAGE_ACTION_RESET_SYSTEM then after reset you can see these messages.
|
||||
They can help to understand where the CPUs were when the WDT was triggered.
|
||||
W (30) boot: PRO CPU has been reset by WDT.
|
||||
W (30) boot: WDT reset info: PRO CPU PC=0x400xxxxx
|
||||
... function where it happened
|
||||
|
||||
W (31) boot: WDT reset info: APP CPU PC=0x400xxxxx
|
||||
... function where it happened
|
||||
|
||||
* If you use this option RTC_WDT_STAGE_ACTION_RESET_RTC then you will see message (rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT))
|
||||
without description where were CPUs when it happened.
|
||||
|
||||
2) Reset counter of rtc_wdt:
|
||||
@code
|
||||
rtc_wdt_feed();
|
||||
@endcode
|
||||
|
||||
3) Disable rtc_wdt:
|
||||
@code
|
||||
rtc_wdt_disable();
|
||||
@endcode
|
||||
*/
|
||||
|
||||
#ifndef _SOC_RTC_WDT_H
|
||||
#define _SOC_RTC_WDT_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "esp_err.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/// List of stage of rtc watchdog. WDT has 4 stage.
|
||||
typedef enum {
|
||||
RTC_WDT_STAGE0 = 0, /*!< Stage 0 */
|
||||
RTC_WDT_STAGE1 = 1, /*!< Stage 1 */
|
||||
RTC_WDT_STAGE2 = 2, /*!< Stage 2 */
|
||||
RTC_WDT_STAGE3 = 3 /*!< Stage 3 */
|
||||
} rtc_wdt_stage_t;
|
||||
|
||||
/// List of action. When the time of stage expires this action will be triggered.
|
||||
typedef enum {
|
||||
RTC_WDT_STAGE_ACTION_OFF = RTC_WDT_STG_SEL_OFF, /*!< Disabled. This stage will have no effects on the system. */
|
||||
RTC_WDT_STAGE_ACTION_INTERRUPT = RTC_WDT_STG_SEL_INT, /*!< Trigger an interrupt. When the stage expires an interrupt is triggered. */
|
||||
RTC_WDT_STAGE_ACTION_RESET_CPU = RTC_WDT_STG_SEL_RESET_CPU, /*!< Reset a CPU core. */
|
||||
RTC_WDT_STAGE_ACTION_RESET_SYSTEM = RTC_WDT_STG_SEL_RESET_SYSTEM, /*!< Reset the main system includes the CPU and all peripherals. The RTC is an exception to this, and it will not be reset. */
|
||||
RTC_WDT_STAGE_ACTION_RESET_RTC = RTC_WDT_STG_SEL_RESET_RTC /*!< Reset the main system and the RTC. */
|
||||
} rtc_wdt_stage_action_t;
|
||||
|
||||
/// Type of reset signal
|
||||
typedef enum {
|
||||
RTC_WDT_SYS_RESET_SIG = 0, /*!< System reset signal length selection */
|
||||
RTC_WDT_CPU_RESET_SIG = 1 /*!< CPU reset signal length selection */
|
||||
} rtc_wdt_reset_sig_t;
|
||||
|
||||
/// Length of reset signal
|
||||
typedef enum {
|
||||
RTC_WDT_LENGTH_100ns = 0, /*!< 100 ns */
|
||||
RTC_WDT_LENGTH_200ns = 1, /*!< 200 ns */
|
||||
RTC_WDT_LENGTH_300ns = 2, /*!< 300 ns */
|
||||
RTC_WDT_LENGTH_400ns = 3, /*!< 400 ns */
|
||||
RTC_WDT_LENGTH_500ns = 4, /*!< 500 ns */
|
||||
RTC_WDT_LENGTH_800ns = 5, /*!< 800 ns */
|
||||
RTC_WDT_LENGTH_1_6us = 6, /*!< 1.6 us */
|
||||
RTC_WDT_LENGTH_3_2us = 7 /*!< 3.2 us */
|
||||
} rtc_wdt_length_sig_t;
|
||||
|
||||
/**
|
||||
* @brief Get status of protect of rtc_wdt.
|
||||
*
|
||||
* @return
|
||||
* - True if the protect of RTC_WDT is set
|
||||
*/
|
||||
bool rtc_wdt_get_protect_status();
|
||||
|
||||
/**
|
||||
* @brief Set protect of rtc_wdt.
|
||||
*/
|
||||
void rtc_wdt_protect_on();
|
||||
|
||||
/**
|
||||
* @brief Reset protect of rtc_wdt.
|
||||
*/
|
||||
void rtc_wdt_protect_off();
|
||||
|
||||
/**
|
||||
* @brief Enable rtc_wdt.
|
||||
*/
|
||||
void rtc_wdt_enable();
|
||||
|
||||
/**
|
||||
* @brief Disable rtc_wdt.
|
||||
*/
|
||||
void rtc_wdt_disable();
|
||||
|
||||
/**
|
||||
* @brief Reset counter rtc_wdt.
|
||||
*
|
||||
* It returns to stage 0 and its expiry counter restarts from 0.
|
||||
*/
|
||||
void rtc_wdt_feed();
|
||||
|
||||
/**
|
||||
* @brief Set time for required stage.
|
||||
*
|
||||
* @param[in] stage Stage of rtc_wdt.
|
||||
* @param[in] timeout_ms Timeout for this stage.
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK In case of success
|
||||
* - ESP_ERR_INVALID_ARG If stage has invalid value
|
||||
*/
|
||||
esp_err_t rtc_wdt_set_time(rtc_wdt_stage_t stage, unsigned int timeout_ms);
|
||||
|
||||
/**
|
||||
* @brief Get the timeout set for the required stage.
|
||||
*
|
||||
* @param[in] stage Stage of rtc_wdt.
|
||||
* @param[out] timeout_ms Timeout set for this stage. (not elapsed time).
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK In case of success
|
||||
* - ESP_ERR_INVALID_ARG If stage has invalid value
|
||||
*/
|
||||
esp_err_t rtc_wdt_get_timeout(rtc_wdt_stage_t stage, unsigned int* timeout_ms);
|
||||
|
||||
/**
|
||||
* @brief Set an action for required stage.
|
||||
*
|
||||
* @param[in] stage Stage of rtc_wdt.
|
||||
* @param[in] stage_sel Action for this stage. When the time of stage expires this action will be triggered.
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK In case of success
|
||||
* - ESP_ERR_INVALID_ARG If stage or stage_sel have invalid value
|
||||
*/
|
||||
esp_err_t rtc_wdt_set_stage(rtc_wdt_stage_t stage, rtc_wdt_stage_action_t stage_sel);
|
||||
|
||||
/**
|
||||
* @brief Set a length of reset signal.
|
||||
*
|
||||
* @param[in] reset_src Type of reset signal.
|
||||
* @param[in] reset_signal_length A length of reset signal.
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK In case of success
|
||||
* - ESP_ERR_INVALID_ARG If reset_src or reset_signal_length have invalid value
|
||||
*/
|
||||
esp_err_t rtc_wdt_set_length_of_reset_signal(rtc_wdt_reset_sig_t reset_src, rtc_wdt_length_sig_t reset_signal_length);
|
||||
|
||||
/**
|
||||
* @brief Return true if rtc_wdt is enabled.
|
||||
*
|
||||
* @return
|
||||
* - True rtc_wdt is enabled
|
||||
*/
|
||||
bool rtc_wdt_is_on();
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _SOC_RTC_WDT_H
|
||||
@ -1,49 +1,49 @@
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SDIO_SLAVE_PERIPH_H_
|
||||
#define _SOC_SDIO_SLAVE_PERIPH_H_
|
||||
|
||||
#include <stdint.h>
|
||||
//include soc related (generated) definitions
|
||||
#include "soc/sdio_slave_pins.h"
|
||||
#include "soc/slc_reg.h"
|
||||
#include "soc/slc_struct.h"
|
||||
#include "soc/host_reg.h"
|
||||
#include "soc/host_struct.h"
|
||||
#include "soc/hinf_reg.h"
|
||||
#include "soc/hinf_struct.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** pin and signal information of each slot */
|
||||
typedef struct {
|
||||
uint32_t clk_gpio;
|
||||
uint32_t cmd_gpio;
|
||||
uint32_t d0_gpio;
|
||||
uint32_t d1_gpio;
|
||||
uint32_t d2_gpio;
|
||||
uint32_t d3_gpio;
|
||||
int func;
|
||||
} sdio_slave_slot_info_t;
|
||||
|
||||
extern const sdio_slave_slot_info_t sdio_slave_slot_info[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SDIO_SLAVE_PERIPH_H_
|
||||
#define _SOC_SDIO_SLAVE_PERIPH_H_
|
||||
|
||||
#include <stdint.h>
|
||||
//include soc related (generated) definitions
|
||||
#include "soc/sdio_slave_pins.h"
|
||||
#include "soc/slc_reg.h"
|
||||
#include "soc/slc_struct.h"
|
||||
#include "soc/host_reg.h"
|
||||
#include "soc/host_struct.h"
|
||||
#include "soc/hinf_reg.h"
|
||||
#include "soc/hinf_struct.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** pin and signal information of each slot */
|
||||
typedef struct {
|
||||
uint32_t clk_gpio;
|
||||
uint32_t cmd_gpio;
|
||||
uint32_t d0_gpio;
|
||||
uint32_t d1_gpio;
|
||||
uint32_t d2_gpio;
|
||||
uint32_t d3_gpio;
|
||||
int func;
|
||||
} sdio_slave_slot_info_t;
|
||||
|
||||
extern const sdio_slave_slot_info_t sdio_slave_slot_info[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SDIO_SLAVE_PERIPH_H_ */
|
||||
@ -1,34 +1,34 @@
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SDIO_SLAVE_PINS_H_
|
||||
#define _SOC_SDIO_SLAVE_PINS_H_
|
||||
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK 6
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD 11
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0 7
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1 8
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2 9
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3 10
|
||||
#define SDIO_SLAVE_SLOT0_FUNC 0
|
||||
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK 14
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD 15
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0 2
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1 4
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2 12
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3 13
|
||||
#define SDIO_SLAVE_SLOT1_FUNC 4
|
||||
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SDIO_SLAVE_PINS_H_
|
||||
#define _SOC_SDIO_SLAVE_PINS_H_
|
||||
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK 6
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD 11
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0 7
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1 8
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2 9
|
||||
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3 10
|
||||
#define SDIO_SLAVE_SLOT0_FUNC 0
|
||||
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK 14
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD 15
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0 2
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1 4
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2 12
|
||||
#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3 13
|
||||
#define SDIO_SLAVE_SLOT1_FUNC 4
|
||||
|
||||
#endif /* _SOC_SDIO_SLAVE_PINS_H_ */
|
||||
@ -1,53 +1,53 @@
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SDMMC_PERIPH_H_
|
||||
#define _SOC_SDMMC_PERIPH_H_
|
||||
|
||||
#include <stdint.h>
|
||||
//include soc related (generated) definitions
|
||||
#include "soc/sdmmc_pins.h"
|
||||
#include "soc/sdmmc_reg.h"
|
||||
#include "soc/sdmmc_struct.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
uint8_t clk_gpio;
|
||||
uint8_t cmd_gpio;
|
||||
uint8_t d0_gpio;
|
||||
uint8_t d1_gpio;
|
||||
uint8_t d2_gpio;
|
||||
uint8_t d3_gpio;
|
||||
uint8_t d4_gpio;
|
||||
uint8_t d5_gpio;
|
||||
uint8_t d6_gpio;
|
||||
uint8_t d7_gpio;
|
||||
uint8_t card_detect;
|
||||
uint8_t write_protect;
|
||||
uint8_t card_int;
|
||||
uint8_t width;
|
||||
} sdmmc_slot_info_t;
|
||||
|
||||
/** pin and signal information of each slot */
|
||||
extern const sdmmc_slot_info_t sdmmc_slot_info[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SDMMC_PERIPH_H_
|
||||
#define _SOC_SDMMC_PERIPH_H_
|
||||
|
||||
#include <stdint.h>
|
||||
//include soc related (generated) definitions
|
||||
#include "soc/sdmmc_pins.h"
|
||||
#include "soc/sdmmc_reg.h"
|
||||
#include "soc/sdmmc_struct.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
uint8_t clk_gpio;
|
||||
uint8_t cmd_gpio;
|
||||
uint8_t d0_gpio;
|
||||
uint8_t d1_gpio;
|
||||
uint8_t d2_gpio;
|
||||
uint8_t d3_gpio;
|
||||
uint8_t d4_gpio;
|
||||
uint8_t d5_gpio;
|
||||
uint8_t d6_gpio;
|
||||
uint8_t d7_gpio;
|
||||
uint8_t card_detect;
|
||||
uint8_t write_protect;
|
||||
uint8_t card_int;
|
||||
uint8_t width;
|
||||
} sdmmc_slot_info_t;
|
||||
|
||||
/** pin and signal information of each slot */
|
||||
extern const sdmmc_slot_info_t sdmmc_slot_info[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SDMMC_PERIPH_H_ */
|
||||
@ -1,38 +1,38 @@
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SDMMC_PINS_H_
|
||||
#define _SOC_SDMMC_PINS_H_
|
||||
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK 6
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD 11
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0 7
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1 8
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2 9
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3 10
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4 16
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D5 17
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D6 5
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D7 18
|
||||
#define SDMMC_SLOT0_FUNC 0
|
||||
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_CLK 14
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_CMD 15
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D0 2
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D1 4
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D2 12
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D3 13
|
||||
#define SDMMC_SLOT1_FUNC 4
|
||||
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SDMMC_PINS_H_
|
||||
#define _SOC_SDMMC_PINS_H_
|
||||
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK 6
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD 11
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0 7
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1 8
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2 9
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3 10
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4 16
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D5 17
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D6 5
|
||||
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D7 18
|
||||
#define SDMMC_SLOT0_FUNC 0
|
||||
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_CLK 14
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_CMD 15
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D0 2
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D1 4
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D2 12
|
||||
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D3 13
|
||||
#define SDMMC_SLOT1_FUNC 4
|
||||
|
||||
#endif /* _SOC_SDMMC_PINS_H_ */
|
||||
@ -71,6 +71,7 @@
|
||||
#define SDMMC_INTMASK_EBE BIT(15)
|
||||
#define SDMMC_INTMASK_ACD BIT(14)
|
||||
#define SDMMC_INTMASK_SBE BIT(13)
|
||||
#define SDMMC_INTMASK_BCI BIT(13)
|
||||
#define SDMMC_INTMASK_HLE BIT(12)
|
||||
#define SDMMC_INTMASK_FRUN BIT(11)
|
||||
#define SDMMC_INTMASK_HTO BIT(10)
|
||||
|
||||
@ -283,7 +283,12 @@ typedef volatile struct {
|
||||
uint32_t usrid; ///< user ID
|
||||
uint32_t verid; ///< IP block version
|
||||
uint32_t hcon; ///< compile-time IP configuration
|
||||
uint32_t uhs; ///< TBD
|
||||
union {
|
||||
struct {
|
||||
uint32_t voltage: 16; ///< voltage control for slots; no-op on ESP32.
|
||||
uint32_t ddr: 16; ///< bit N enables DDR mode for card N
|
||||
};
|
||||
} uhs; ///< UHS related settings
|
||||
|
||||
union {
|
||||
struct {
|
||||
@ -348,7 +353,16 @@ typedef volatile struct {
|
||||
uint32_t bufaddrl; ///< unused
|
||||
uint32_t bufaddru; ///< unused
|
||||
uint32_t reserved_a8[22];
|
||||
uint32_t cardthrctl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t read_thr_en : 1; ///< initiate transfer only if FIFO has more space than the read threshold
|
||||
uint32_t busy_clr_int_en : 1; ///< enable generation of busy clear interrupts
|
||||
uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes
|
||||
uint32_t reserved1 : 13;
|
||||
uint32_t card_threshold : 12; ///< threshold value for reads/writes, in bytes
|
||||
};
|
||||
uint32_t val;
|
||||
} cardthrctl;
|
||||
uint32_t back_end_power;
|
||||
uint32_t uhs_reg_ext;
|
||||
uint32_t emmc_ddr_reg;
|
||||
|
||||
@ -120,6 +120,7 @@
|
||||
#define DR_REG_I2C1_EXT_BASE 0x3ff67000
|
||||
#define DR_REG_SDMMC_BASE 0x3ff68000
|
||||
#define DR_REG_EMAC_BASE 0x3ff69000
|
||||
#define DR_REG_CAN_BASE 0x3ff6B000
|
||||
#define DR_REG_PWM1_BASE 0x3ff6C000
|
||||
#define DR_REG_I2S1_BASE 0x3ff6D000
|
||||
#define DR_REG_UART2_BASE 0x3ff6E000
|
||||
@ -133,6 +134,7 @@
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
#define BIT64(nr) (1ULL << (nr))
|
||||
#else
|
||||
#define BIT(nr) (1 << (nr))
|
||||
#endif
|
||||
|
||||
@ -20,6 +20,38 @@
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
#ifdef CONFIG_BT_ENABLED
|
||||
|
||||
#define SOC_MEM_BT_DATA_START 0x3ffae6e0
|
||||
#define SOC_MEM_BT_DATA_END 0x3ffaff10
|
||||
#define SOC_MEM_BT_EM_START 0x3ffb0000
|
||||
#define SOC_MEM_BT_EM_END 0x3ffb7cd8
|
||||
#define SOC_MEM_BT_EM_BTDM0_START 0x3ffb0000
|
||||
#define SOC_MEM_BT_EM_BTDM0_END 0x3ffb09a8
|
||||
#define SOC_MEM_BT_EM_BLE_START 0x3ffb09a8
|
||||
#define SOC_MEM_BT_EM_BLE_END 0x3ffb1ddc
|
||||
#define SOC_MEM_BT_EM_BTDM1_START 0x3ffb1ddc
|
||||
#define SOC_MEM_BT_EM_BTDM1_END 0x3ffb2730
|
||||
#define SOC_MEM_BT_EM_BREDR_START 0x3ffb2730
|
||||
#define SOC_MEM_BT_EM_BREDR_NO_SYNC_END 0x3ffb6388 //Not calculate with synchronize connection support
|
||||
#define SOC_MEM_BT_EM_BREDR_END 0x3ffb7cd8 //Calculate with synchronize connection support
|
||||
#define SOC_MEM_BT_EM_SYNC0_START 0x3ffb6388
|
||||
#define SOC_MEM_BT_EM_SYNC0_END 0x3ffb6bf8
|
||||
#define SOC_MEM_BT_EM_SYNC1_START 0x3ffb6bf8
|
||||
#define SOC_MEM_BT_EM_SYNC1_END 0x3ffb7468
|
||||
#define SOC_MEM_BT_EM_SYNC2_START 0x3ffb7468
|
||||
#define SOC_MEM_BT_EM_SYNC2_END 0x3ffb7cd8
|
||||
#define SOC_MEM_BT_BSS_START 0x3ffb8000
|
||||
#define SOC_MEM_BT_BSS_END 0x3ffb9a20
|
||||
#define SOC_MEM_BT_MISC_START 0x3ffbdb28
|
||||
#define SOC_MEM_BT_MISC_END 0x3ffbdb5c
|
||||
|
||||
#define SOC_MEM_BT_EM_PER_SYNC_SIZE 0x870
|
||||
|
||||
#define SOC_MEM_BT_EM_BREDR_REAL_END (SOC_MEM_BT_EM_BREDR_NO_SYNC_END + CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF * SOC_MEM_BT_EM_PER_SYNC_SIZE)
|
||||
|
||||
#endif //CONFIG_BT_ENABLED
|
||||
|
||||
#define SOC_MEMORY_TYPE_NO_PRIOS 3
|
||||
|
||||
/* Type descriptor holds a description for a particular type of memory on a particular SoC.
|
||||
@ -57,8 +89,55 @@ typedef struct
|
||||
intptr_t end;
|
||||
} soc_reserved_region_t;
|
||||
|
||||
extern const soc_reserved_region_t soc_reserved_regions[];
|
||||
extern const size_t soc_reserved_region_count;
|
||||
/* Use this macro to reserved a fixed region of RAM (hardcoded addresses)
|
||||
* for a particular purpose.
|
||||
*
|
||||
* Usually used to mark out memory addresses needed for hardware or ROM code
|
||||
* purposes.
|
||||
*
|
||||
* Don't call this macro from user code which can use normal C static allocation
|
||||
* instead.
|
||||
*
|
||||
* @param START Start address to be reserved.
|
||||
* @param END One after the address of the last byte to be reserved. (ie length of
|
||||
* the reserved region is (END - START) in bytes.
|
||||
* @param NAME Name for the reserved region. Must be a valid variable name,
|
||||
* unique to this source file.
|
||||
*/
|
||||
#define SOC_RESERVE_MEMORY_REGION(START, END, NAME) \
|
||||
__attribute__((section(".reserved_memory_address"))) __attribute__((used)) \
|
||||
static soc_reserved_region_t reserved_region_##NAME = { START, END };
|
||||
|
||||
/* Return available memory regions for this SoC. Each available memory
|
||||
* region is a contiguous piece of memory which is not being used by
|
||||
* static data, used by ROM code, or reserved by a component using
|
||||
* the SOC_RESERVE_MEMORY_REGION() macro.
|
||||
*
|
||||
* This result is soc_memory_regions[] minus all regions reserved
|
||||
* via the SOC_RESERVE_MEMORY_REGION() macro (which may also split
|
||||
* some regions up.)
|
||||
*
|
||||
* At startup, all available memory returned by this function is
|
||||
* registered as heap space.
|
||||
*
|
||||
* @note OS-level startup function only, not recommended to call from
|
||||
* app code.
|
||||
*
|
||||
* @param regions Pointer to an array for reading available regions into.
|
||||
* Size of the array should be at least the result of
|
||||
* soc_get_available_memory_region_max_count(). Entries in the array
|
||||
* will be ordered by memory address.
|
||||
*
|
||||
* @return Number of entries copied to 'regions'. Will be no greater than
|
||||
* the result of soc_get_available_memory_region_max_count().
|
||||
*/
|
||||
size_t soc_get_available_memory_regions(soc_memory_region_t *regions);
|
||||
|
||||
/* Return the maximum number of available memory regions which could be
|
||||
* returned by soc_get_available_memory_regions(). Used to size the
|
||||
* array passed to that function.
|
||||
*/
|
||||
size_t soc_get_available_memory_region_max_count();
|
||||
|
||||
inline static bool IRAM_ATTR esp_ptr_dma_capable(const void *p)
|
||||
{
|
||||
|
||||
@ -1,66 +1,66 @@
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SPI_PERIPH_H_
|
||||
#define _SOC_SPI_PERIPH_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/periph_defs.h"
|
||||
//include soc related (generated) definitions
|
||||
#include "soc/spi_pins.h"
|
||||
#include "soc/spi_reg.h"
|
||||
#include "soc/spi_struct.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*
|
||||
Stores a bunch of per-spi-peripheral data.
|
||||
*/
|
||||
typedef struct {
|
||||
const uint8_t spiclk_out; //GPIO mux output signals
|
||||
const uint8_t spiclk_in;
|
||||
const uint8_t spid_out;
|
||||
const uint8_t spiq_out;
|
||||
const uint8_t spiwp_out;
|
||||
const uint8_t spihd_out;
|
||||
const uint8_t spid_in; //GPIO mux input signals
|
||||
const uint8_t spiq_in;
|
||||
const uint8_t spiwp_in;
|
||||
const uint8_t spihd_in;
|
||||
const uint8_t spics_out[3]; // /CS GPIO output mux signals
|
||||
const uint8_t spics_in;
|
||||
const uint8_t spiclk_iomux_pin; //IO pins of IO_MUX muxed signals
|
||||
const uint8_t spid_iomux_pin;
|
||||
const uint8_t spiq_iomux_pin;
|
||||
const uint8_t spiwp_iomux_pin;
|
||||
const uint8_t spihd_iomux_pin;
|
||||
const uint8_t spics0_iomux_pin;
|
||||
const uint8_t irq; //irq source for interrupt mux
|
||||
const uint8_t irq_dma; //dma irq source for interrupt mux
|
||||
const periph_module_t module; //peripheral module, for enabling clock etc
|
||||
spi_dev_t *hw; //Pointer to the hardware registers
|
||||
} spi_signal_conn_t;
|
||||
|
||||
extern const spi_signal_conn_t spi_periph_signal[3];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SPI_PERIPH_H_
|
||||
#define _SOC_SPI_PERIPH_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/periph_defs.h"
|
||||
//include soc related (generated) definitions
|
||||
#include "soc/spi_pins.h"
|
||||
#include "soc/spi_reg.h"
|
||||
#include "soc/spi_struct.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*
|
||||
Stores a bunch of per-spi-peripheral data.
|
||||
*/
|
||||
typedef struct {
|
||||
const uint8_t spiclk_out; //GPIO mux output signals
|
||||
const uint8_t spiclk_in;
|
||||
const uint8_t spid_out;
|
||||
const uint8_t spiq_out;
|
||||
const uint8_t spiwp_out;
|
||||
const uint8_t spihd_out;
|
||||
const uint8_t spid_in; //GPIO mux input signals
|
||||
const uint8_t spiq_in;
|
||||
const uint8_t spiwp_in;
|
||||
const uint8_t spihd_in;
|
||||
const uint8_t spics_out[3]; // /CS GPIO output mux signals
|
||||
const uint8_t spics_in;
|
||||
const uint8_t spiclk_iomux_pin; //IO pins of IO_MUX muxed signals
|
||||
const uint8_t spid_iomux_pin;
|
||||
const uint8_t spiq_iomux_pin;
|
||||
const uint8_t spiwp_iomux_pin;
|
||||
const uint8_t spihd_iomux_pin;
|
||||
const uint8_t spics0_iomux_pin;
|
||||
const uint8_t irq; //irq source for interrupt mux
|
||||
const uint8_t irq_dma; //dma irq source for interrupt mux
|
||||
const periph_module_t module; //peripheral module, for enabling clock etc
|
||||
spi_dev_t *hw; //Pointer to the hardware registers
|
||||
} spi_signal_conn_t;
|
||||
|
||||
extern const spi_signal_conn_t spi_periph_signal[3];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SPI_PERIPH_H_ */
|
||||
@ -1,39 +1,39 @@
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SPI_PINS_H_
|
||||
#define _SOC_SPI_PINS_H_
|
||||
|
||||
#define SPI_IOMUX_PIN_NUM_MISO 7
|
||||
#define SPI_IOMUX_PIN_NUM_MOSI 8
|
||||
#define SPI_IOMUX_PIN_NUM_CLK 6
|
||||
#define SPI_IOMUX_PIN_NUM_CS 11
|
||||
#define SPI_IOMUX_PIN_NUM_WP 10
|
||||
#define SPI_IOMUX_PIN_NUM_HD 9
|
||||
|
||||
#define HSPI_IOMUX_PIN_NUM_MISO 12
|
||||
#define HSPI_IOMUX_PIN_NUM_MOSI 13
|
||||
#define HSPI_IOMUX_PIN_NUM_CLK 14
|
||||
#define HSPI_IOMUX_PIN_NUM_CS 15
|
||||
#define HSPI_IOMUX_PIN_NUM_WP 2
|
||||
#define HSPI_IOMUX_PIN_NUM_HD 4
|
||||
|
||||
#define VSPI_IOMUX_PIN_NUM_MISO 19
|
||||
#define VSPI_IOMUX_PIN_NUM_MOSI 23
|
||||
#define VSPI_IOMUX_PIN_NUM_CLK 18
|
||||
#define VSPI_IOMUX_PIN_NUM_CS 5
|
||||
#define VSPI_IOMUX_PIN_NUM_WP 22
|
||||
#define VSPI_IOMUX_PIN_NUM_HD 21
|
||||
|
||||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SPI_PINS_H_
|
||||
#define _SOC_SPI_PINS_H_
|
||||
|
||||
#define SPI_IOMUX_PIN_NUM_MISO 7
|
||||
#define SPI_IOMUX_PIN_NUM_MOSI 8
|
||||
#define SPI_IOMUX_PIN_NUM_CLK 6
|
||||
#define SPI_IOMUX_PIN_NUM_CS 11
|
||||
#define SPI_IOMUX_PIN_NUM_WP 10
|
||||
#define SPI_IOMUX_PIN_NUM_HD 9
|
||||
|
||||
#define HSPI_IOMUX_PIN_NUM_MISO 12
|
||||
#define HSPI_IOMUX_PIN_NUM_MOSI 13
|
||||
#define HSPI_IOMUX_PIN_NUM_CLK 14
|
||||
#define HSPI_IOMUX_PIN_NUM_CS 15
|
||||
#define HSPI_IOMUX_PIN_NUM_WP 2
|
||||
#define HSPI_IOMUX_PIN_NUM_HD 4
|
||||
|
||||
#define VSPI_IOMUX_PIN_NUM_MISO 19
|
||||
#define VSPI_IOMUX_PIN_NUM_MOSI 23
|
||||
#define VSPI_IOMUX_PIN_NUM_CLK 18
|
||||
#define VSPI_IOMUX_PIN_NUM_CS 5
|
||||
#define VSPI_IOMUX_PIN_NUM_WP 22
|
||||
#define VSPI_IOMUX_PIN_NUM_HD 21
|
||||
|
||||
#endif /* _SOC_SPI_PINS_H_ */
|
||||
Reference in New Issue
Block a user