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IDF master c13afea63 (#5214)

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esp-dsp: master 7cc5073
esp-face: master 420fc7e
esp-rainmaker: f1b82c7
esp32-camera: master 6f8489e
esp_littlefs: master b58f00c
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Me No Dev
2021-05-31 16:32:51 +03:00
committed by GitHub
parent 0db9e2f45b
commit a618fc1361
616 changed files with 11842 additions and 4932 deletions
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41
tools/sdk/esp32/include/xtensa/include/xtensa/xtensa_api.h
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@ -136,45 +136,4 @@ extern void * xt_get_interrupt_handler_arg(int n);
*/
bool xt_int_has_handler(int intr, int cpu);
/*
-------------------------------------------------------------------------------
Call this function to disable non iram located interrupts.
newmask - mask containing the interrupts to disable.
-------------------------------------------------------------------------------
*/
static inline uint32_t xt_int_disable_mask(uint32_t newmask)
{
uint32_t oldint;
asm volatile (
"movi %0,0\n"
"xsr %0,INTENABLE\n" //disable all ints first
"rsync\n"
"and a3,%0,%1\n" //mask ints that need disabling
"wsr a3,INTENABLE\n" //write back
"rsync\n"
:"=&r"(oldint):"r"(newmask):"a3");
return oldint;
}
/*
-------------------------------------------------------------------------------
Call this function to enable non iram located interrupts.
newmask - mask containing the interrupts to enable.
-------------------------------------------------------------------------------
*/
static inline void xt_int_enable_mask(uint32_t newmask)
{
asm volatile (
"movi a3,0\n"
"xsr a3,INTENABLE\n"
"rsync\n"
"or a3,a3,%0\n"
"wsr a3,INTENABLE\n"
"rsync\n"
::"r"(newmask):"a3");
}
#endif /* __XTENSA_API_H__ */